1 /* 2 * Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2000, 2001 4 * Bill Paul <wpaul@bsdi.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 * $FreeBSD$ 34 */ 35 36 /* 37 * National Semiconductor DP83820/DP83821 gigabit ethernet driver 38 * for FreeBSD. Datasheets are available from: 39 * 40 * http://www.national.com/ds/DP/DP83820.pdf 41 * http://www.national.com/ds/DP/DP83821.pdf 42 * 43 * These chips are used on several low cost gigabit ethernet NICs 44 * sold by D-Link, Addtron, SMC and Asante. Both parts are 45 * virtually the same, except the 83820 is a 64-bit/32-bit part, 46 * while the 83821 is 32-bit only. 47 * 48 * Many cards also use National gigE transceivers, such as the 49 * DP83891, DP83861 and DP83862 gigPHYTER parts. The DP83861 datasheet 50 * contains a full register description that applies to all of these 51 * components: 52 * 53 * http://www.national.com/ds/DP/DP83861.pdf 54 * 55 * Written by Bill Paul <wpaul@bsdi.com> 56 * BSDi Open Source Solutions 57 */ 58 59 /* 60 * The NatSemi DP83820 and 83821 controllers are enhanced versions 61 * of the NatSemi MacPHYTER 10/100 devices. They support 10, 100 62 * and 1000Mbps speeds with 1000baseX (ten bit interface), MII and GMII 63 * ports. Other features include 8K TX FIFO and 32K RX FIFO, TCP/IP 64 * hardware checksum offload (IPv4 only), VLAN tagging and filtering, 65 * priority TX and RX queues, a 2048 bit multicast hash filter, 4 RX pattern 66 * matching buffers, one perfect address filter buffer and interrupt 67 * moderation. The 83820 supports both 64-bit and 32-bit addressing 68 * and data transfers: the 64-bit support can be toggled on or off 69 * via software. This affects the size of certain fields in the DMA 70 * descriptors. 71 * 72 * As far as I can tell, the 83820 and 83821 are decent chips, marred by 73 * only one flaw: the RX buffers must be aligned on 64-bit boundaries. 74 * So far this is the only gigE MAC that I've encountered with this 75 * requirement. 76 */ 77 78 #include "vlan.h" 79 80 #include <sys/param.h> 81 #include <sys/systm.h> 82 #include <sys/sockio.h> 83 #include <sys/mbuf.h> 84 #include <sys/malloc.h> 85 #include <sys/kernel.h> 86 #include <sys/socket.h> 87 88 #include <net/if.h> 89 #include <net/if_arp.h> 90 #include <net/ethernet.h> 91 #include <net/if_dl.h> 92 #include <net/if_media.h> 93 94 #if NVLAN > 0 95 #include <net/if_types.h> 96 #include <net/if_vlan_var.h> 97 #endif 98 99 #include <net/bpf.h> 100 101 #include <vm/vm.h> /* for vtophys */ 102 #include <vm/pmap.h> /* for vtophys */ 103 #include <machine/clock.h> /* for DELAY */ 104 #include <machine/bus_pio.h> 105 #include <machine/bus_memio.h> 106 #include <machine/bus.h> 107 #include <machine/resource.h> 108 #include <sys/bus.h> 109 #include <sys/rman.h> 110 111 #include <dev/mii/mii.h> 112 #include <dev/mii/miivar.h> 113 114 #include <pci/pcireg.h> 115 #include <pci/pcivar.h> 116 117 #define NGE_USEIOSPACE 118 119 #include <dev/nge/if_ngereg.h> 120 121 MODULE_DEPEND(nge, miibus, 1, 1, 1); 122 123 /* "controller miibus0" required. See GENERIC if you get errors here. */ 124 #include "miibus_if.h" 125 126 #ifndef lint 127 static const char rcsid[] = 128 "$FreeBSD$"; 129 #endif 130 131 #define NGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 132 133 /* 134 * Various supported device vendors/types and their names. 135 */ 136 static struct nge_type nge_devs[] = { 137 { NGE_VENDORID, NGE_DEVICEID, 138 "National Semiconductor Gigabit Ethernet" }, 139 { 0, 0, NULL } 140 }; 141 142 static int nge_probe __P((device_t)); 143 static int nge_attach __P((device_t)); 144 static int nge_detach __P((device_t)); 145 146 static int nge_alloc_jumbo_mem __P((struct nge_softc *)); 147 static void nge_free_jumbo_mem __P((struct nge_softc *)); 148 static void *nge_jalloc __P((struct nge_softc *)); 149 static void nge_jfree __P((caddr_t, void *)); 150 151 static int nge_newbuf __P((struct nge_softc *, 152 struct nge_desc *, 153 struct mbuf *)); 154 static int nge_encap __P((struct nge_softc *, 155 struct mbuf *, u_int32_t *)); 156 static void nge_rxeof __P((struct nge_softc *)); 157 static void nge_rxeoc __P((struct nge_softc *)); 158 static void nge_txeof __P((struct nge_softc *)); 159 static void nge_intr __P((void *)); 160 static void nge_tick __P((void *)); 161 static void nge_start __P((struct ifnet *)); 162 static int nge_ioctl __P((struct ifnet *, u_long, caddr_t)); 163 static void nge_init __P((void *)); 164 static void nge_stop __P((struct nge_softc *)); 165 static void nge_watchdog __P((struct ifnet *)); 166 static void nge_shutdown __P((device_t)); 167 static int nge_ifmedia_upd __P((struct ifnet *)); 168 static void nge_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 169 170 static void nge_delay __P((struct nge_softc *)); 171 static void nge_eeprom_idle __P((struct nge_softc *)); 172 static void nge_eeprom_putbyte __P((struct nge_softc *, int)); 173 static void nge_eeprom_getword __P((struct nge_softc *, int, u_int16_t *)); 174 static void nge_read_eeprom __P((struct nge_softc *, caddr_t, int, 175 int, int)); 176 177 static void nge_mii_sync __P((struct nge_softc *)); 178 static void nge_mii_send __P((struct nge_softc *, u_int32_t, int)); 179 static int nge_mii_readreg __P((struct nge_softc *, 180 struct nge_mii_frame *)); 181 static int nge_mii_writereg __P((struct nge_softc *, 182 struct nge_mii_frame *)); 183 184 static int nge_miibus_readreg __P((device_t, int, int)); 185 static int nge_miibus_writereg __P((device_t, int, int, int)); 186 static void nge_miibus_statchg __P((device_t)); 187 188 static void nge_setmulti __P((struct nge_softc *)); 189 static u_int32_t nge_crc __P((struct nge_softc *, caddr_t)); 190 static void nge_reset __P((struct nge_softc *)); 191 static int nge_list_rx_init __P((struct nge_softc *)); 192 static int nge_list_tx_init __P((struct nge_softc *)); 193 194 #ifdef NGE_USEIOSPACE 195 #define NGE_RES SYS_RES_IOPORT 196 #define NGE_RID NGE_PCI_LOIO 197 #else 198 #define NGE_RES SYS_RES_MEMORY 199 #define NGE_RID NGE_PCI_LOMEM 200 #endif 201 202 static device_method_t nge_methods[] = { 203 /* Device interface */ 204 DEVMETHOD(device_probe, nge_probe), 205 DEVMETHOD(device_attach, nge_attach), 206 DEVMETHOD(device_detach, nge_detach), 207 DEVMETHOD(device_shutdown, nge_shutdown), 208 209 /* bus interface */ 210 DEVMETHOD(bus_print_child, bus_generic_print_child), 211 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 212 213 /* MII interface */ 214 DEVMETHOD(miibus_readreg, nge_miibus_readreg), 215 DEVMETHOD(miibus_writereg, nge_miibus_writereg), 216 DEVMETHOD(miibus_statchg, nge_miibus_statchg), 217 218 { 0, 0 } 219 }; 220 221 static driver_t nge_driver = { 222 "nge", 223 nge_methods, 224 sizeof(struct nge_softc) 225 }; 226 227 static devclass_t nge_devclass; 228 229 DRIVER_MODULE(if_nge, pci, nge_driver, nge_devclass, 0, 0); 230 DRIVER_MODULE(miibus, nge, miibus_driver, miibus_devclass, 0, 0); 231 232 #define NGE_SETBIT(sc, reg, x) \ 233 CSR_WRITE_4(sc, reg, \ 234 CSR_READ_4(sc, reg) | (x)) 235 236 #define NGE_CLRBIT(sc, reg, x) \ 237 CSR_WRITE_4(sc, reg, \ 238 CSR_READ_4(sc, reg) & ~(x)) 239 240 #define SIO_SET(x) \ 241 CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) | x) 242 243 #define SIO_CLR(x) \ 244 CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) & ~x) 245 246 static void nge_delay(sc) 247 struct nge_softc *sc; 248 { 249 int idx; 250 251 for (idx = (300 / 33) + 1; idx > 0; idx--) 252 CSR_READ_4(sc, NGE_CSR); 253 254 return; 255 } 256 257 static void nge_eeprom_idle(sc) 258 struct nge_softc *sc; 259 { 260 register int i; 261 262 SIO_SET(NGE_MEAR_EE_CSEL); 263 nge_delay(sc); 264 SIO_SET(NGE_MEAR_EE_CLK); 265 nge_delay(sc); 266 267 for (i = 0; i < 25; i++) { 268 SIO_CLR(NGE_MEAR_EE_CLK); 269 nge_delay(sc); 270 SIO_SET(NGE_MEAR_EE_CLK); 271 nge_delay(sc); 272 } 273 274 SIO_CLR(NGE_MEAR_EE_CLK); 275 nge_delay(sc); 276 SIO_CLR(NGE_MEAR_EE_CSEL); 277 nge_delay(sc); 278 CSR_WRITE_4(sc, NGE_MEAR, 0x00000000); 279 280 return; 281 } 282 283 /* 284 * Send a read command and address to the EEPROM, check for ACK. 285 */ 286 static void nge_eeprom_putbyte(sc, addr) 287 struct nge_softc *sc; 288 int addr; 289 { 290 register int d, i; 291 292 d = addr | NGE_EECMD_READ; 293 294 /* 295 * Feed in each bit and stobe the clock. 296 */ 297 for (i = 0x400; i; i >>= 1) { 298 if (d & i) { 299 SIO_SET(NGE_MEAR_EE_DIN); 300 } else { 301 SIO_CLR(NGE_MEAR_EE_DIN); 302 } 303 nge_delay(sc); 304 SIO_SET(NGE_MEAR_EE_CLK); 305 nge_delay(sc); 306 SIO_CLR(NGE_MEAR_EE_CLK); 307 nge_delay(sc); 308 } 309 310 return; 311 } 312 313 /* 314 * Read a word of data stored in the EEPROM at address 'addr.' 315 */ 316 static void nge_eeprom_getword(sc, addr, dest) 317 struct nge_softc *sc; 318 int addr; 319 u_int16_t *dest; 320 { 321 register int i; 322 u_int16_t word = 0; 323 324 /* Force EEPROM to idle state. */ 325 nge_eeprom_idle(sc); 326 327 /* Enter EEPROM access mode. */ 328 nge_delay(sc); 329 SIO_CLR(NGE_MEAR_EE_CLK); 330 nge_delay(sc); 331 SIO_SET(NGE_MEAR_EE_CSEL); 332 nge_delay(sc); 333 334 /* 335 * Send address of word we want to read. 336 */ 337 nge_eeprom_putbyte(sc, addr); 338 339 /* 340 * Start reading bits from EEPROM. 341 */ 342 for (i = 0x8000; i; i >>= 1) { 343 SIO_SET(NGE_MEAR_EE_CLK); 344 nge_delay(sc); 345 if (CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_EE_DOUT) 346 word |= i; 347 nge_delay(sc); 348 SIO_CLR(NGE_MEAR_EE_CLK); 349 nge_delay(sc); 350 } 351 352 /* Turn off EEPROM access mode. */ 353 nge_eeprom_idle(sc); 354 355 *dest = word; 356 357 return; 358 } 359 360 /* 361 * Read a sequence of words from the EEPROM. 362 */ 363 static void nge_read_eeprom(sc, dest, off, cnt, swap) 364 struct nge_softc *sc; 365 caddr_t dest; 366 int off; 367 int cnt; 368 int swap; 369 { 370 int i; 371 u_int16_t word = 0, *ptr; 372 373 for (i = 0; i < cnt; i++) { 374 nge_eeprom_getword(sc, off + i, &word); 375 ptr = (u_int16_t *)(dest + (i * 2)); 376 if (swap) 377 *ptr = ntohs(word); 378 else 379 *ptr = word; 380 } 381 382 return; 383 } 384 385 /* 386 * Sync the PHYs by setting data bit and strobing the clock 32 times. 387 */ 388 static void nge_mii_sync(sc) 389 struct nge_softc *sc; 390 { 391 register int i; 392 393 SIO_SET(NGE_MEAR_MII_DIR|NGE_MEAR_MII_DATA); 394 395 for (i = 0; i < 32; i++) { 396 SIO_SET(NGE_MEAR_MII_CLK); 397 DELAY(1); 398 SIO_CLR(NGE_MEAR_MII_CLK); 399 DELAY(1); 400 } 401 402 return; 403 } 404 405 /* 406 * Clock a series of bits through the MII. 407 */ 408 static void nge_mii_send(sc, bits, cnt) 409 struct nge_softc *sc; 410 u_int32_t bits; 411 int cnt; 412 { 413 int i; 414 415 SIO_CLR(NGE_MEAR_MII_CLK); 416 417 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 418 if (bits & i) { 419 SIO_SET(NGE_MEAR_MII_DATA); 420 } else { 421 SIO_CLR(NGE_MEAR_MII_DATA); 422 } 423 DELAY(1); 424 SIO_CLR(NGE_MEAR_MII_CLK); 425 DELAY(1); 426 SIO_SET(NGE_MEAR_MII_CLK); 427 } 428 } 429 430 /* 431 * Read an PHY register through the MII. 432 */ 433 static int nge_mii_readreg(sc, frame) 434 struct nge_softc *sc; 435 struct nge_mii_frame *frame; 436 437 { 438 int i, ack, s; 439 440 s = splimp(); 441 442 /* 443 * Set up frame for RX. 444 */ 445 frame->mii_stdelim = NGE_MII_STARTDELIM; 446 frame->mii_opcode = NGE_MII_READOP; 447 frame->mii_turnaround = 0; 448 frame->mii_data = 0; 449 450 CSR_WRITE_4(sc, NGE_MEAR, 0); 451 452 /* 453 * Turn on data xmit. 454 */ 455 SIO_SET(NGE_MEAR_MII_DIR); 456 457 nge_mii_sync(sc); 458 459 /* 460 * Send command/address info. 461 */ 462 nge_mii_send(sc, frame->mii_stdelim, 2); 463 nge_mii_send(sc, frame->mii_opcode, 2); 464 nge_mii_send(sc, frame->mii_phyaddr, 5); 465 nge_mii_send(sc, frame->mii_regaddr, 5); 466 467 /* Idle bit */ 468 SIO_CLR((NGE_MEAR_MII_CLK|NGE_MEAR_MII_DATA)); 469 DELAY(1); 470 SIO_SET(NGE_MEAR_MII_CLK); 471 DELAY(1); 472 473 /* Turn off xmit. */ 474 SIO_CLR(NGE_MEAR_MII_DIR); 475 /* Check for ack */ 476 SIO_CLR(NGE_MEAR_MII_CLK); 477 DELAY(1); 478 SIO_SET(NGE_MEAR_MII_CLK); 479 DELAY(1); 480 ack = CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_MII_DATA; 481 482 /* 483 * Now try reading data bits. If the ack failed, we still 484 * need to clock through 16 cycles to keep the PHY(s) in sync. 485 */ 486 if (ack) { 487 for(i = 0; i < 16; i++) { 488 SIO_CLR(NGE_MEAR_MII_CLK); 489 DELAY(1); 490 SIO_SET(NGE_MEAR_MII_CLK); 491 DELAY(1); 492 } 493 goto fail; 494 } 495 496 for (i = 0x8000; i; i >>= 1) { 497 SIO_CLR(NGE_MEAR_MII_CLK); 498 DELAY(1); 499 if (!ack) { 500 if (CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_MII_DATA) 501 frame->mii_data |= i; 502 DELAY(1); 503 } 504 SIO_SET(NGE_MEAR_MII_CLK); 505 DELAY(1); 506 } 507 508 fail: 509 510 SIO_CLR(NGE_MEAR_MII_CLK); 511 DELAY(1); 512 SIO_SET(NGE_MEAR_MII_CLK); 513 DELAY(1); 514 515 splx(s); 516 517 if (ack) 518 return(1); 519 return(0); 520 } 521 522 /* 523 * Write to a PHY register through the MII. 524 */ 525 static int nge_mii_writereg(sc, frame) 526 struct nge_softc *sc; 527 struct nge_mii_frame *frame; 528 529 { 530 int s; 531 532 s = splimp(); 533 /* 534 * Set up frame for TX. 535 */ 536 537 frame->mii_stdelim = NGE_MII_STARTDELIM; 538 frame->mii_opcode = NGE_MII_WRITEOP; 539 frame->mii_turnaround = NGE_MII_TURNAROUND; 540 541 /* 542 * Turn on data output. 543 */ 544 SIO_SET(NGE_MEAR_MII_DIR); 545 546 nge_mii_sync(sc); 547 548 nge_mii_send(sc, frame->mii_stdelim, 2); 549 nge_mii_send(sc, frame->mii_opcode, 2); 550 nge_mii_send(sc, frame->mii_phyaddr, 5); 551 nge_mii_send(sc, frame->mii_regaddr, 5); 552 nge_mii_send(sc, frame->mii_turnaround, 2); 553 nge_mii_send(sc, frame->mii_data, 16); 554 555 /* Idle bit. */ 556 SIO_SET(NGE_MEAR_MII_CLK); 557 DELAY(1); 558 SIO_CLR(NGE_MEAR_MII_CLK); 559 DELAY(1); 560 561 /* 562 * Turn off xmit. 563 */ 564 SIO_CLR(NGE_MEAR_MII_DIR); 565 566 splx(s); 567 568 return(0); 569 } 570 571 static int nge_miibus_readreg(dev, phy, reg) 572 device_t dev; 573 int phy, reg; 574 { 575 struct nge_softc *sc; 576 struct nge_mii_frame frame; 577 578 sc = device_get_softc(dev); 579 580 bzero((char *)&frame, sizeof(frame)); 581 582 frame.mii_phyaddr = phy; 583 frame.mii_regaddr = reg; 584 nge_mii_readreg(sc, &frame); 585 586 return(frame.mii_data); 587 } 588 589 static int nge_miibus_writereg(dev, phy, reg, data) 590 device_t dev; 591 int phy, reg, data; 592 { 593 struct nge_softc *sc; 594 struct nge_mii_frame frame; 595 596 sc = device_get_softc(dev); 597 598 bzero((char *)&frame, sizeof(frame)); 599 600 frame.mii_phyaddr = phy; 601 frame.mii_regaddr = reg; 602 frame.mii_data = data; 603 nge_mii_writereg(sc, &frame); 604 605 return(0); 606 } 607 608 static void nge_miibus_statchg(dev) 609 device_t dev; 610 { 611 struct nge_softc *sc; 612 struct mii_data *mii; 613 614 sc = device_get_softc(dev); 615 mii = device_get_softc(sc->nge_miibus); 616 617 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 618 NGE_SETBIT(sc, NGE_TX_CFG, 619 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 620 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 621 } else { 622 NGE_CLRBIT(sc, NGE_TX_CFG, 623 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 624 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 625 } 626 627 return; 628 } 629 630 static u_int32_t nge_crc(sc, addr) 631 struct nge_softc *sc; 632 caddr_t addr; 633 { 634 u_int32_t crc, carry; 635 int i, j; 636 u_int8_t c; 637 638 /* Compute CRC for the address value. */ 639 crc = 0xFFFFFFFF; /* initial value */ 640 641 for (i = 0; i < 6; i++) { 642 c = *(addr + i); 643 for (j = 0; j < 8; j++) { 644 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 645 crc <<= 1; 646 c >>= 1; 647 if (carry) 648 crc = (crc ^ 0x04c11db6) | carry; 649 } 650 } 651 652 /* 653 * return the filter bit position 654 */ 655 656 return((crc >> 21) & 0x00000FFF); 657 } 658 659 static void nge_setmulti(sc) 660 struct nge_softc *sc; 661 { 662 struct ifnet *ifp; 663 struct ifmultiaddr *ifma; 664 u_int32_t h = 0, i, filtsave; 665 int bit, index; 666 667 ifp = &sc->arpcom.ac_if; 668 669 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 670 NGE_CLRBIT(sc, NGE_RXFILT_CTL, 671 NGE_RXFILTCTL_MCHASH|NGE_RXFILTCTL_UCHASH); 672 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLMULTI); 673 return; 674 } 675 676 /* 677 * We have to explicitly enable the multicast hash table 678 * on the NatSemi chip if we want to use it, which we do. 679 * We also have to tell it that we don't want to use the 680 * hash table for matching unicast addresses. 681 */ 682 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_MCHASH); 683 NGE_CLRBIT(sc, NGE_RXFILT_CTL, 684 NGE_RXFILTCTL_ALLMULTI|NGE_RXFILTCTL_UCHASH); 685 686 filtsave = CSR_READ_4(sc, NGE_RXFILT_CTL); 687 688 /* first, zot all the existing hash bits */ 689 for (i = 0; i < NGE_MCAST_FILTER_LEN; i += 2) { 690 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_MCAST_LO + i); 691 CSR_WRITE_4(sc, NGE_RXFILT_DATA, 0); 692 } 693 694 /* 695 * From the 11 bits returned by the crc routine, the top 7 696 * bits represent the 16-bit word in the mcast hash table 697 * that needs to be updated, and the lower 4 bits represent 698 * which bit within that byte needs to be set. 699 */ 700 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 701 if (ifma->ifma_addr->sa_family != AF_LINK) 702 continue; 703 h = nge_crc(sc, LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 704 index = (h >> 4) & 0x7F; 705 bit = h & 0xF; 706 CSR_WRITE_4(sc, NGE_RXFILT_CTL, 707 NGE_FILTADDR_MCAST_LO + (index * 2)); 708 NGE_SETBIT(sc, NGE_RXFILT_DATA, (1 << bit)); 709 } 710 711 CSR_WRITE_4(sc, NGE_RXFILT_CTL, filtsave); 712 713 return; 714 } 715 716 static void nge_reset(sc) 717 struct nge_softc *sc; 718 { 719 register int i; 720 721 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RESET); 722 723 for (i = 0; i < NGE_TIMEOUT; i++) { 724 if (!(CSR_READ_4(sc, NGE_CSR) & NGE_CSR_RESET)) 725 break; 726 } 727 728 if (i == NGE_TIMEOUT) 729 printf("nge%d: reset never completed\n", sc->nge_unit); 730 731 /* Wait a little while for the chip to get its brains in order. */ 732 DELAY(1000); 733 734 /* 735 * If this is a NetSemi chip, make sure to clear 736 * PME mode. 737 */ 738 CSR_WRITE_4(sc, NGE_CLKRUN, NGE_CLKRUN_PMESTS); 739 CSR_WRITE_4(sc, NGE_CLKRUN, 0); 740 741 return; 742 } 743 744 /* 745 * Probe for an NatSemi chip. Check the PCI vendor and device 746 * IDs against our list and return a device name if we find a match. 747 */ 748 static int nge_probe(dev) 749 device_t dev; 750 { 751 struct nge_type *t; 752 753 t = nge_devs; 754 755 while(t->nge_name != NULL) { 756 if ((pci_get_vendor(dev) == t->nge_vid) && 757 (pci_get_device(dev) == t->nge_did)) { 758 device_set_desc(dev, t->nge_name); 759 return(0); 760 } 761 t++; 762 } 763 764 return(ENXIO); 765 } 766 767 /* 768 * Attach the interface. Allocate softc structures, do ifmedia 769 * setup and ethernet/BPF attach. 770 */ 771 static int nge_attach(dev) 772 device_t dev; 773 { 774 int s; 775 u_char eaddr[ETHER_ADDR_LEN]; 776 u_int32_t command; 777 struct nge_softc *sc; 778 struct ifnet *ifp; 779 int unit, error = 0, rid; 780 781 s = splimp(); 782 783 sc = device_get_softc(dev); 784 unit = device_get_unit(dev); 785 bzero(sc, sizeof(struct nge_softc)); 786 787 mtx_init(&sc->nge_mtx, device_get_nameunit(dev), MTX_DEF|MTX_RECURSE); 788 789 /* 790 * Handle power management nonsense. 791 */ 792 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 793 u_int32_t iobase, membase, irq; 794 795 /* Save important PCI config data. */ 796 iobase = pci_read_config(dev, NGE_PCI_LOIO, 4); 797 membase = pci_read_config(dev, NGE_PCI_LOMEM, 4); 798 irq = pci_read_config(dev, NGE_PCI_INTLINE, 4); 799 800 /* Reset the power state. */ 801 printf("nge%d: chip is in D%d power mode " 802 "-- setting to D0\n", unit, 803 pci_get_powerstate(dev)); 804 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 805 806 /* Restore PCI config data. */ 807 pci_write_config(dev, NGE_PCI_LOIO, iobase, 4); 808 pci_write_config(dev, NGE_PCI_LOMEM, membase, 4); 809 pci_write_config(dev, NGE_PCI_INTLINE, irq, 4); 810 } 811 812 /* 813 * Map control/status registers. 814 */ 815 pci_enable_busmaster(dev); 816 pci_enable_io(dev, PCIM_CMD_PORTEN); 817 pci_enable_io(dev, PCIM_CMD_MEMEN); 818 command = pci_read_config(dev, PCIR_COMMAND, 4); 819 820 #ifdef NGE_USEIOSPACE 821 if (!(command & PCIM_CMD_PORTEN)) { 822 printf("nge%d: failed to enable I/O ports!\n", unit); 823 error = ENXIO;; 824 goto fail; 825 } 826 #else 827 if (!(command & PCIM_CMD_MEMEN)) { 828 printf("nge%d: failed to enable memory mapping!\n", unit); 829 error = ENXIO;; 830 goto fail; 831 } 832 #endif 833 834 rid = NGE_RID; 835 sc->nge_res = bus_alloc_resource(dev, NGE_RES, &rid, 836 0, ~0, 1, RF_ACTIVE); 837 838 if (sc->nge_res == NULL) { 839 printf("nge%d: couldn't map ports/memory\n", unit); 840 error = ENXIO; 841 goto fail; 842 } 843 844 sc->nge_btag = rman_get_bustag(sc->nge_res); 845 sc->nge_bhandle = rman_get_bushandle(sc->nge_res); 846 847 /* Allocate interrupt */ 848 rid = 0; 849 sc->nge_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 850 RF_SHAREABLE | RF_ACTIVE); 851 852 if (sc->nge_irq == NULL) { 853 printf("nge%d: couldn't map interrupt\n", unit); 854 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res); 855 error = ENXIO; 856 goto fail; 857 } 858 859 error = bus_setup_intr(dev, sc->nge_irq, INTR_TYPE_NET, 860 nge_intr, sc, &sc->nge_intrhand); 861 862 if (error) { 863 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq); 864 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res); 865 printf("nge%d: couldn't set up irq\n", unit); 866 goto fail; 867 } 868 869 /* Reset the adapter. */ 870 nge_reset(sc); 871 872 /* 873 * Get station address from the EEPROM. 874 */ 875 nge_read_eeprom(sc, (caddr_t)&eaddr[4], NGE_EE_NODEADDR, 1, 0); 876 nge_read_eeprom(sc, (caddr_t)&eaddr[2], NGE_EE_NODEADDR + 1, 1, 0); 877 nge_read_eeprom(sc, (caddr_t)&eaddr[0], NGE_EE_NODEADDR + 2, 1, 0); 878 879 /* 880 * A NatSemi chip was detected. Inform the world. 881 */ 882 printf("nge%d: Ethernet address: %6D\n", unit, eaddr, ":"); 883 884 sc->nge_unit = unit; 885 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 886 887 sc->nge_ldata = contigmalloc(sizeof(struct nge_list_data), M_DEVBUF, 888 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 889 890 if (sc->nge_ldata == NULL) { 891 printf("nge%d: no memory for list buffers!\n", unit); 892 bus_teardown_intr(dev, sc->nge_irq, sc->nge_intrhand); 893 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq); 894 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res); 895 error = ENXIO; 896 goto fail; 897 } 898 bzero(sc->nge_ldata, sizeof(struct nge_list_data)); 899 900 /* Try to allocate memory for jumbo buffers. */ 901 if (nge_alloc_jumbo_mem(sc)) { 902 printf("nge%d: jumbo buffer allocation failed\n", 903 sc->nge_unit); 904 contigfree(sc->nge_ldata, 905 sizeof(struct nge_list_data), M_DEVBUF); 906 bus_teardown_intr(dev, sc->nge_irq, sc->nge_intrhand); 907 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq); 908 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res); 909 error = ENXIO; 910 goto fail; 911 } 912 913 ifp = &sc->arpcom.ac_if; 914 ifp->if_softc = sc; 915 ifp->if_unit = unit; 916 ifp->if_name = "nge"; 917 ifp->if_mtu = ETHERMTU; 918 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 919 ifp->if_ioctl = nge_ioctl; 920 ifp->if_output = ether_output; 921 ifp->if_start = nge_start; 922 ifp->if_watchdog = nge_watchdog; 923 ifp->if_init = nge_init; 924 ifp->if_baudrate = 1000000000; 925 ifp->if_snd.ifq_maxlen = NGE_TX_LIST_CNT - 1; 926 ifp->if_hwassist = NGE_CSUM_FEATURES; 927 928 /* 929 * Do MII setup. 930 */ 931 if (mii_phy_probe(dev, &sc->nge_miibus, 932 nge_ifmedia_upd, nge_ifmedia_sts)) { 933 printf("nge%d: MII without any PHY!\n", sc->nge_unit); 934 nge_free_jumbo_mem(sc); 935 bus_teardown_intr(dev, sc->nge_irq, sc->nge_intrhand); 936 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq); 937 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res); 938 error = ENXIO; 939 goto fail; 940 } 941 942 /* 943 * Call MI attach routine. 944 */ 945 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 946 callout_handle_init(&sc->nge_stat_ch); 947 948 fail: 949 splx(s); 950 mtx_destroy(&sc->nge_mtx); 951 return(error); 952 } 953 954 static int nge_detach(dev) 955 device_t dev; 956 { 957 struct nge_softc *sc; 958 struct ifnet *ifp; 959 int s; 960 961 s = splimp(); 962 963 sc = device_get_softc(dev); 964 ifp = &sc->arpcom.ac_if; 965 966 nge_reset(sc); 967 nge_stop(sc); 968 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 969 970 bus_generic_detach(dev); 971 device_delete_child(dev, sc->nge_miibus); 972 973 bus_teardown_intr(dev, sc->nge_irq, sc->nge_intrhand); 974 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq); 975 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res); 976 977 contigfree(sc->nge_ldata, sizeof(struct nge_list_data), M_DEVBUF); 978 nge_free_jumbo_mem(sc); 979 980 splx(s); 981 mtx_destroy(&sc->nge_mtx); 982 983 return(0); 984 } 985 986 /* 987 * Initialize the transmit descriptors. 988 */ 989 static int nge_list_tx_init(sc) 990 struct nge_softc *sc; 991 { 992 struct nge_list_data *ld; 993 struct nge_ring_data *cd; 994 int i; 995 996 cd = &sc->nge_cdata; 997 ld = sc->nge_ldata; 998 999 for (i = 0; i < NGE_TX_LIST_CNT; i++) { 1000 if (i == (NGE_TX_LIST_CNT - 1)) { 1001 ld->nge_tx_list[i].nge_nextdesc = 1002 &ld->nge_tx_list[0]; 1003 ld->nge_tx_list[i].nge_next = 1004 vtophys(&ld->nge_tx_list[0]); 1005 } else { 1006 ld->nge_tx_list[i].nge_nextdesc = 1007 &ld->nge_tx_list[i + 1]; 1008 ld->nge_tx_list[i].nge_next = 1009 vtophys(&ld->nge_tx_list[i + 1]); 1010 } 1011 ld->nge_tx_list[i].nge_mbuf = NULL; 1012 ld->nge_tx_list[i].nge_ptr = 0; 1013 ld->nge_tx_list[i].nge_ctl = 0; 1014 } 1015 1016 cd->nge_tx_prod = cd->nge_tx_cons = cd->nge_tx_cnt = 0; 1017 1018 return(0); 1019 } 1020 1021 1022 /* 1023 * Initialize the RX descriptors and allocate mbufs for them. Note that 1024 * we arrange the descriptors in a closed ring, so that the last descriptor 1025 * points back to the first. 1026 */ 1027 static int nge_list_rx_init(sc) 1028 struct nge_softc *sc; 1029 { 1030 struct nge_list_data *ld; 1031 struct nge_ring_data *cd; 1032 int i; 1033 1034 ld = sc->nge_ldata; 1035 cd = &sc->nge_cdata; 1036 1037 for (i = 0; i < NGE_RX_LIST_CNT; i++) { 1038 if (nge_newbuf(sc, &ld->nge_rx_list[i], NULL) == ENOBUFS) 1039 return(ENOBUFS); 1040 if (i == (NGE_RX_LIST_CNT - 1)) { 1041 ld->nge_rx_list[i].nge_nextdesc = 1042 &ld->nge_rx_list[0]; 1043 ld->nge_rx_list[i].nge_next = 1044 vtophys(&ld->nge_rx_list[0]); 1045 } else { 1046 ld->nge_rx_list[i].nge_nextdesc = 1047 &ld->nge_rx_list[i + 1]; 1048 ld->nge_rx_list[i].nge_next = 1049 vtophys(&ld->nge_rx_list[i + 1]); 1050 } 1051 } 1052 1053 cd->nge_rx_prod = 0; 1054 1055 return(0); 1056 } 1057 1058 /* 1059 * Initialize an RX descriptor and attach an MBUF cluster. 1060 */ 1061 static int nge_newbuf(sc, c, m) 1062 struct nge_softc *sc; 1063 struct nge_desc *c; 1064 struct mbuf *m; 1065 { 1066 struct mbuf *m_new = NULL; 1067 caddr_t *buf = NULL; 1068 1069 if (m == NULL) { 1070 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1071 if (m_new == NULL) { 1072 printf("nge%d: no memory for rx list " 1073 "-- packet dropped!\n", sc->nge_unit); 1074 return(ENOBUFS); 1075 } 1076 1077 /* Allocate the jumbo buffer */ 1078 buf = nge_jalloc(sc); 1079 if (buf == NULL) { 1080 #ifdef NGE_VERBOSE 1081 printf("nge%d: jumbo allocation failed " 1082 "-- packet dropped!\n", sc->nge_unit); 1083 #endif 1084 m_freem(m_new); 1085 return(ENOBUFS); 1086 } 1087 /* Attach the buffer to the mbuf */ 1088 m_new->m_data = (void *)buf; 1089 m_new->m_len = m_new->m_pkthdr.len = NGE_MCLBYTES; 1090 MEXTADD(m_new, buf, NGE_MCLBYTES, nge_jfree, 1091 (struct ti_softc *)sc, 0, EXT_NET_DRV); 1092 } else { 1093 m_new = m; 1094 m_new->m_len = m_new->m_pkthdr.len = NGE_MCLBYTES; 1095 m_new->m_data = m_new->m_ext.ext_buf; 1096 } 1097 1098 m_adj(m_new, sizeof(u_int64_t)); 1099 1100 c->nge_mbuf = m_new; 1101 c->nge_ptr = vtophys(mtod(m_new, caddr_t)); 1102 c->nge_ctl = m_new->m_len; 1103 c->nge_extsts = 0; 1104 1105 return(0); 1106 } 1107 1108 static int nge_alloc_jumbo_mem(sc) 1109 struct nge_softc *sc; 1110 { 1111 caddr_t ptr; 1112 register int i; 1113 struct nge_jpool_entry *entry; 1114 1115 /* Grab a big chunk o' storage. */ 1116 sc->nge_cdata.nge_jumbo_buf = contigmalloc(NGE_JMEM, M_DEVBUF, 1117 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1118 1119 if (sc->nge_cdata.nge_jumbo_buf == NULL) { 1120 printf("nge%d: no memory for jumbo buffers!\n", sc->nge_unit); 1121 return(ENOBUFS); 1122 } 1123 1124 SLIST_INIT(&sc->nge_jfree_listhead); 1125 SLIST_INIT(&sc->nge_jinuse_listhead); 1126 1127 /* 1128 * Now divide it up into 9K pieces and save the addresses 1129 * in an array. 1130 */ 1131 ptr = sc->nge_cdata.nge_jumbo_buf; 1132 for (i = 0; i < NGE_JSLOTS; i++) { 1133 sc->nge_cdata.nge_jslots[i] = ptr; 1134 ptr += NGE_MCLBYTES; 1135 entry = malloc(sizeof(struct nge_jpool_entry), 1136 M_DEVBUF, M_NOWAIT); 1137 if (entry == NULL) { 1138 free(sc->nge_cdata.nge_jumbo_buf, M_DEVBUF); 1139 sc->nge_cdata.nge_jumbo_buf = NULL; 1140 printf("nge%d: no memory for jumbo " 1141 "buffer queue!\n", sc->nge_unit); 1142 return(ENOBUFS); 1143 } 1144 entry->slot = i; 1145 SLIST_INSERT_HEAD(&sc->nge_jfree_listhead, 1146 entry, jpool_entries); 1147 } 1148 1149 return(0); 1150 } 1151 1152 static void nge_free_jumbo_mem(sc) 1153 struct nge_softc *sc; 1154 { 1155 register int i; 1156 struct nge_jpool_entry *entry; 1157 1158 for (i = 0; i < NGE_JSLOTS; i++) { 1159 entry = SLIST_FIRST(&sc->nge_jfree_listhead); 1160 free(entry, M_DEVBUF); 1161 SLIST_REMOVE_HEAD(&sc->nge_jfree_listhead, jpool_entries); 1162 } 1163 1164 contigfree(sc->nge_cdata.nge_jumbo_buf, NGE_JMEM, M_DEVBUF); 1165 1166 return; 1167 } 1168 1169 /* 1170 * Allocate a jumbo buffer. 1171 */ 1172 static void *nge_jalloc(sc) 1173 struct nge_softc *sc; 1174 { 1175 struct nge_jpool_entry *entry; 1176 1177 entry = SLIST_FIRST(&sc->nge_jfree_listhead); 1178 1179 if (entry == NULL) { 1180 #ifdef NGE_VERBOSE 1181 printf("nge%d: no free jumbo buffers\n", sc->nge_unit); 1182 #endif 1183 return(NULL); 1184 } 1185 1186 SLIST_REMOVE_HEAD(&sc->nge_jfree_listhead, jpool_entries); 1187 SLIST_INSERT_HEAD(&sc->nge_jinuse_listhead, entry, jpool_entries); 1188 return(sc->nge_cdata.nge_jslots[entry->slot]); 1189 } 1190 1191 /* 1192 * Release a jumbo buffer. 1193 */ 1194 static void nge_jfree(buf, args) 1195 caddr_t buf; 1196 void *args; 1197 { 1198 struct nge_softc *sc; 1199 int i; 1200 struct nge_jpool_entry *entry; 1201 1202 /* Extract the softc struct pointer. */ 1203 sc = args; 1204 1205 if (sc == NULL) 1206 panic("nge_jfree: can't find softc pointer!"); 1207 1208 /* calculate the slot this buffer belongs to */ 1209 i = ((vm_offset_t)buf 1210 - (vm_offset_t)sc->nge_cdata.nge_jumbo_buf) / NGE_JLEN; 1211 1212 if ((i < 0) || (i >= NGE_JSLOTS)) 1213 panic("nge_jfree: asked to free buffer that we don't manage!"); 1214 1215 entry = SLIST_FIRST(&sc->nge_jinuse_listhead); 1216 if (entry == NULL) 1217 panic("nge_jfree: buffer not in use!"); 1218 entry->slot = i; 1219 SLIST_REMOVE_HEAD(&sc->nge_jinuse_listhead, jpool_entries); 1220 SLIST_INSERT_HEAD(&sc->nge_jfree_listhead, entry, jpool_entries); 1221 1222 return; 1223 } 1224 /* 1225 * A frame has been uploaded: pass the resulting mbuf chain up to 1226 * the higher level protocols. 1227 */ 1228 static void nge_rxeof(sc) 1229 struct nge_softc *sc; 1230 { 1231 struct ether_header *eh; 1232 struct mbuf *m; 1233 struct ifnet *ifp; 1234 struct nge_desc *cur_rx; 1235 int i, total_len = 0; 1236 u_int32_t rxstat; 1237 1238 ifp = &sc->arpcom.ac_if; 1239 i = sc->nge_cdata.nge_rx_prod; 1240 1241 while(NGE_OWNDESC(&sc->nge_ldata->nge_rx_list[i])) { 1242 struct mbuf *m0 = NULL; 1243 u_int32_t extsts; 1244 1245 cur_rx = &sc->nge_ldata->nge_rx_list[i]; 1246 rxstat = cur_rx->nge_rxstat; 1247 extsts = cur_rx->nge_extsts; 1248 m = cur_rx->nge_mbuf; 1249 cur_rx->nge_mbuf = NULL; 1250 total_len = NGE_RXBYTES(cur_rx); 1251 NGE_INC(i, NGE_RX_LIST_CNT); 1252 1253 /* 1254 * If an error occurs, update stats, clear the 1255 * status word and leave the mbuf cluster in place: 1256 * it should simply get re-used next time this descriptor 1257 * comes up in the ring. 1258 */ 1259 if (!(rxstat & NGE_CMDSTS_PKT_OK)) { 1260 ifp->if_ierrors++; 1261 nge_newbuf(sc, cur_rx, m); 1262 continue; 1263 } 1264 1265 1266 /* 1267 * Ok. NatSemi really screwed up here. This is the 1268 * only gigE chip I know of with alignment constraints 1269 * on receive buffers. RX buffers must be 64-bit aligned. 1270 */ 1271 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 1272 total_len + ETHER_ALIGN, 0, ifp, NULL); 1273 nge_newbuf(sc, cur_rx, m); 1274 if (m0 == NULL) { 1275 printf("nge%d: no receive buffers " 1276 "available -- packet dropped!\n", 1277 sc->nge_unit); 1278 ifp->if_ierrors++; 1279 continue; 1280 } 1281 m_adj(m0, ETHER_ALIGN); 1282 m = m0; 1283 1284 ifp->if_ipackets++; 1285 eh = mtod(m, struct ether_header *); 1286 1287 /* Remove header from mbuf and pass it on. */ 1288 m_adj(m, sizeof(struct ether_header)); 1289 1290 /* Do IP checksum checking. */ 1291 if (ifp->if_hwassist) { 1292 if (extsts & NGE_RXEXTSTS_IPPKT) 1293 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1294 if (!(extsts & NGE_RXEXTSTS_IPCSUMERR)) 1295 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1296 } 1297 1298 #if NVLAN > 0 1299 /* 1300 * If we received a packet with a vlan tag, pass it 1301 * to vlan_input() instead of ether_input(). 1302 */ 1303 if (extsts & NGE_RXEXTSTS_VLANPKT) { 1304 vlan_input_tag(eh, m, extsts & NGE_RXEXTSTS_VTCI); 1305 continue; 1306 } 1307 #endif 1308 1309 ether_input(ifp, eh, m); 1310 } 1311 1312 sc->nge_cdata.nge_rx_prod = i; 1313 1314 return; 1315 } 1316 1317 void nge_rxeoc(sc) 1318 struct nge_softc *sc; 1319 { 1320 struct ifnet *ifp; 1321 1322 ifp = &sc->arpcom.ac_if; 1323 nge_rxeof(sc); 1324 ifp->if_flags &= ~IFF_RUNNING; 1325 nge_init(sc); 1326 return; 1327 } 1328 1329 /* 1330 * A frame was downloaded to the chip. It's safe for us to clean up 1331 * the list buffers. 1332 */ 1333 1334 static void nge_txeof(sc) 1335 struct nge_softc *sc; 1336 { 1337 struct nge_desc *cur_tx = NULL; 1338 struct ifnet *ifp; 1339 u_int32_t idx; 1340 1341 ifp = &sc->arpcom.ac_if; 1342 1343 /* Clear the timeout timer. */ 1344 ifp->if_timer = 0; 1345 1346 /* 1347 * Go through our tx list and free mbufs for those 1348 * frames that have been transmitted. 1349 */ 1350 idx = sc->nge_cdata.nge_tx_cons; 1351 while (idx != sc->nge_cdata.nge_tx_prod) { 1352 cur_tx = &sc->nge_ldata->nge_tx_list[idx]; 1353 1354 if (NGE_OWNDESC(cur_tx)) 1355 break; 1356 1357 if (cur_tx->nge_ctl & NGE_CMDSTS_MORE) { 1358 sc->nge_cdata.nge_tx_cnt--; 1359 NGE_INC(idx, NGE_TX_LIST_CNT); 1360 continue; 1361 } 1362 1363 if (!(cur_tx->nge_ctl & NGE_CMDSTS_PKT_OK)) { 1364 ifp->if_oerrors++; 1365 if (cur_tx->nge_txstat & NGE_TXSTAT_EXCESSCOLLS) 1366 ifp->if_collisions++; 1367 if (cur_tx->nge_txstat & NGE_TXSTAT_OUTOFWINCOLL) 1368 ifp->if_collisions++; 1369 } 1370 1371 ifp->if_collisions += 1372 (cur_tx->nge_txstat & NGE_TXSTAT_COLLCNT) >> 16; 1373 1374 ifp->if_opackets++; 1375 if (cur_tx->nge_mbuf != NULL) { 1376 m_freem(cur_tx->nge_mbuf); 1377 cur_tx->nge_mbuf = NULL; 1378 } 1379 1380 sc->nge_cdata.nge_tx_cnt--; 1381 NGE_INC(idx, NGE_TX_LIST_CNT); 1382 ifp->if_timer = 0; 1383 } 1384 1385 sc->nge_cdata.nge_tx_cons = idx; 1386 1387 if (cur_tx != NULL) 1388 ifp->if_flags &= ~IFF_OACTIVE; 1389 1390 return; 1391 } 1392 1393 static void nge_tick(xsc) 1394 void *xsc; 1395 { 1396 struct nge_softc *sc; 1397 struct mii_data *mii; 1398 struct ifnet *ifp; 1399 int s; 1400 1401 s = splimp(); 1402 1403 sc = xsc; 1404 ifp = &sc->arpcom.ac_if; 1405 1406 mii = device_get_softc(sc->nge_miibus); 1407 mii_tick(mii); 1408 1409 if (!sc->nge_link) { 1410 mii_pollstat(mii); 1411 if (mii->mii_media_status & IFM_ACTIVE && 1412 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1413 sc->nge_link++; 1414 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_TX) 1415 printf("nge%d: gigabit link up\n", 1416 sc->nge_unit); 1417 if (ifp->if_snd.ifq_head != NULL) 1418 nge_start(ifp); 1419 } else 1420 sc->nge_stat_ch = timeout(nge_tick, sc, hz); 1421 } 1422 1423 1424 splx(s); 1425 1426 return; 1427 } 1428 1429 static void nge_intr(arg) 1430 void *arg; 1431 { 1432 struct nge_softc *sc; 1433 struct ifnet *ifp; 1434 u_int32_t status; 1435 1436 sc = arg; 1437 ifp = &sc->arpcom.ac_if; 1438 1439 /* Supress unwanted interrupts */ 1440 if (!(ifp->if_flags & IFF_UP)) { 1441 nge_stop(sc); 1442 return; 1443 } 1444 1445 /* Disable interrupts. */ 1446 CSR_WRITE_4(sc, NGE_IER, 0); 1447 1448 for (;;) { 1449 /* Reading the ISR register clears all interrupts. */ 1450 status = CSR_READ_4(sc, NGE_ISR); 1451 1452 if ((status & NGE_INTRS) == 0) 1453 break; 1454 1455 if ((status & NGE_ISR_TX_DESC_OK) || 1456 (status & NGE_ISR_TX_ERR) || 1457 (status & NGE_ISR_TX_OK) || 1458 (status & NGE_ISR_TX_IDLE)) 1459 nge_txeof(sc); 1460 1461 if ((status & NGE_ISR_RX_DESC_OK) || 1462 (status & NGE_ISR_RX_OK)) 1463 nge_rxeof(sc); 1464 1465 if ((status & NGE_ISR_RX_ERR) || 1466 (status & NGE_ISR_RX_OFLOW)) { 1467 nge_rxeoc(sc); 1468 } 1469 1470 if (status & NGE_ISR_SYSERR) { 1471 nge_reset(sc); 1472 ifp->if_flags &= ~IFF_RUNNING; 1473 nge_init(sc); 1474 } 1475 1476 if (status & NGE_IMR_PHY_INTR) { 1477 sc->nge_link = 0; 1478 nge_tick(sc); 1479 } 1480 } 1481 1482 /* Re-enable interrupts. */ 1483 CSR_WRITE_4(sc, NGE_IER, 1); 1484 1485 if (ifp->if_snd.ifq_head != NULL) 1486 nge_start(ifp); 1487 1488 return; 1489 } 1490 1491 /* 1492 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1493 * pointers to the fragment pointers. 1494 */ 1495 static int nge_encap(sc, m_head, txidx) 1496 struct nge_softc *sc; 1497 struct mbuf *m_head; 1498 u_int32_t *txidx; 1499 { 1500 struct nge_desc *f = NULL; 1501 struct mbuf *m; 1502 int frag, cur, cnt = 0; 1503 #if NVLAN > 0 1504 struct ifvlan *ifv = NULL; 1505 1506 if ((m_head->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) && 1507 m_head->m_pkthdr.rcvif != NULL && 1508 m_head->m_pkthdr.rcvif->if_type == IFT_8021_VLAN) 1509 ifv = m_head->m_pkthdr.rcvif->if_softc; 1510 #endif 1511 1512 /* 1513 * Start packing the mbufs in this chain into 1514 * the fragment pointers. Stop when we run out 1515 * of fragments or hit the end of the mbuf chain. 1516 */ 1517 m = m_head; 1518 cur = frag = *txidx; 1519 1520 for (m = m_head; m != NULL; m = m->m_next) { 1521 if (m->m_len != 0) { 1522 if ((NGE_TX_LIST_CNT - 1523 (sc->nge_cdata.nge_tx_cnt + cnt)) < 2) 1524 return(ENOBUFS); 1525 f = &sc->nge_ldata->nge_tx_list[frag]; 1526 f->nge_ctl = NGE_CMDSTS_MORE | m->m_len; 1527 f->nge_ptr = vtophys(mtod(m, vm_offset_t)); 1528 if (cnt != 0) 1529 f->nge_ctl |= NGE_CMDSTS_OWN; 1530 cur = frag; 1531 NGE_INC(frag, NGE_TX_LIST_CNT); 1532 cnt++; 1533 } 1534 } 1535 1536 if (m != NULL) 1537 return(ENOBUFS); 1538 1539 sc->nge_ldata->nge_tx_list[cur].nge_extsts = 0; 1540 if (m_head->m_pkthdr.csum_flags) { 1541 if (m_head->m_pkthdr.csum_flags & CSUM_IP) 1542 sc->nge_ldata->nge_tx_list[cur].nge_extsts |= 1543 NGE_TXEXTSTS_IPCSUM; 1544 if (m_head->m_pkthdr.csum_flags & CSUM_TCP) 1545 sc->nge_ldata->nge_tx_list[cur].nge_extsts |= 1546 NGE_TXEXTSTS_TCPCSUM; 1547 if (m_head->m_pkthdr.csum_flags & CSUM_UDP) 1548 sc->nge_ldata->nge_tx_list[cur].nge_extsts |= 1549 NGE_TXEXTSTS_UDPCSUM; 1550 } 1551 1552 #if NVLAN > 0 1553 if (ifv != NULL) { 1554 sc->nge_ldata->nge_tx_list[cur].nge_extsts |= 1555 (NGE_TXEXTSTS_VLANPKT|ifv->ifv_tag); 1556 } 1557 #endif 1558 1559 sc->nge_ldata->nge_tx_list[cur].nge_mbuf = m_head; 1560 sc->nge_ldata->nge_tx_list[cur].nge_ctl &= ~NGE_CMDSTS_MORE; 1561 sc->nge_ldata->nge_tx_list[*txidx].nge_ctl |= NGE_CMDSTS_OWN; 1562 sc->nge_cdata.nge_tx_cnt += cnt; 1563 *txidx = frag; 1564 1565 return(0); 1566 } 1567 1568 /* 1569 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1570 * to the mbuf data regions directly in the transmit lists. We also save a 1571 * copy of the pointers since the transmit list fragment pointers are 1572 * physical addresses. 1573 */ 1574 1575 static void nge_start(ifp) 1576 struct ifnet *ifp; 1577 { 1578 struct nge_softc *sc; 1579 struct mbuf *m_head = NULL; 1580 u_int32_t idx; 1581 1582 sc = ifp->if_softc; 1583 1584 if (!sc->nge_link) 1585 return; 1586 1587 idx = sc->nge_cdata.nge_tx_prod; 1588 1589 if (ifp->if_flags & IFF_OACTIVE) 1590 return; 1591 1592 while(sc->nge_ldata->nge_tx_list[idx].nge_mbuf == NULL) { 1593 IF_DEQUEUE(&ifp->if_snd, m_head); 1594 if (m_head == NULL) 1595 break; 1596 1597 if (nge_encap(sc, m_head, &idx)) { 1598 IF_PREPEND(&ifp->if_snd, m_head); 1599 ifp->if_flags |= IFF_OACTIVE; 1600 break; 1601 } 1602 1603 /* 1604 * If there's a BPF listener, bounce a copy of this frame 1605 * to him. 1606 */ 1607 if (ifp->if_bpf) 1608 bpf_mtap(ifp, m_head); 1609 1610 } 1611 1612 /* Transmit */ 1613 sc->nge_cdata.nge_tx_prod = idx; 1614 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_TX_ENABLE); 1615 1616 /* 1617 * Set a timeout in case the chip goes out to lunch. 1618 */ 1619 ifp->if_timer = 5; 1620 1621 return; 1622 } 1623 1624 static void nge_init(xsc) 1625 void *xsc; 1626 { 1627 struct nge_softc *sc = xsc; 1628 struct ifnet *ifp = &sc->arpcom.ac_if; 1629 struct mii_data *mii; 1630 int s; 1631 1632 if (ifp->if_flags & IFF_RUNNING) 1633 return; 1634 1635 s = splimp(); 1636 1637 /* 1638 * Cancel pending I/O and free all RX/TX buffers. 1639 */ 1640 nge_stop(sc); 1641 1642 mii = device_get_softc(sc->nge_miibus); 1643 1644 /* Set MAC address */ 1645 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR0); 1646 CSR_WRITE_4(sc, NGE_RXFILT_DATA, 1647 ((u_int16_t *)sc->arpcom.ac_enaddr)[0]); 1648 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR1); 1649 CSR_WRITE_4(sc, NGE_RXFILT_DATA, 1650 ((u_int16_t *)sc->arpcom.ac_enaddr)[1]); 1651 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR2); 1652 CSR_WRITE_4(sc, NGE_RXFILT_DATA, 1653 ((u_int16_t *)sc->arpcom.ac_enaddr)[2]); 1654 1655 /* Init circular RX list. */ 1656 if (nge_list_rx_init(sc) == ENOBUFS) { 1657 printf("nge%d: initialization failed: no " 1658 "memory for rx buffers\n", sc->nge_unit); 1659 nge_stop(sc); 1660 (void)splx(s); 1661 return; 1662 } 1663 1664 /* 1665 * Init tx descriptors. 1666 */ 1667 nge_list_tx_init(sc); 1668 1669 /* 1670 * For the NatSemi chip, we have to explicitly enable the 1671 * reception of ARP frames, as well as turn on the 'perfect 1672 * match' filter where we store the station address, otherwise 1673 * we won't receive unicasts meant for this host. 1674 */ 1675 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ARP); 1676 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_PERFECT); 1677 1678 /* If we want promiscuous mode, set the allframes bit. */ 1679 if (ifp->if_flags & IFF_PROMISC) { 1680 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLPHYS); 1681 } else { 1682 NGE_CLRBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLPHYS); 1683 } 1684 1685 /* 1686 * Set the capture broadcast bit to capture broadcast frames. 1687 */ 1688 if (ifp->if_flags & IFF_BROADCAST) { 1689 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_BROAD); 1690 } else { 1691 NGE_CLRBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_BROAD); 1692 } 1693 1694 /* 1695 * Load the multicast filter. 1696 */ 1697 nge_setmulti(sc); 1698 1699 /* Turn the receive filter on */ 1700 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ENABLE); 1701 1702 /* 1703 * Load the address of the RX and TX lists. 1704 */ 1705 CSR_WRITE_4(sc, NGE_RX_LISTPTR, 1706 vtophys(&sc->nge_ldata->nge_rx_list[0])); 1707 CSR_WRITE_4(sc, NGE_TX_LISTPTR, 1708 vtophys(&sc->nge_ldata->nge_tx_list[0])); 1709 1710 /* Set RX configuration */ 1711 CSR_WRITE_4(sc, NGE_RX_CFG, NGE_RXCFG); 1712 /* 1713 * Enable hardware checksum validation for all IPv4 1714 * packets, do not reject packets with bad checksums. 1715 */ 1716 if (ifp->if_hwassist) 1717 CSR_WRITE_4(sc, NGE_VLAN_IP_RXCTL, NGE_VIPRXCTL_IPCSUM_ENB); 1718 1719 #if NVLAN > 0 1720 /* 1721 * If VLAN support is enabled, tell the chip to detect 1722 * and strip VLAN tag info from received frames. The tag 1723 * will be provided in the extsts field in the RX descriptors. 1724 */ 1725 NGE_SETBIT(sc, NGE_VLAN_IP_RXCTL, 1726 NGE_VIPRXCTL_TAG_DETECT_ENB|NGE_VIPRXCTL_TAG_STRIP_ENB); 1727 #endif 1728 1729 /* Set TX configuration */ 1730 CSR_WRITE_4(sc, NGE_TX_CFG, NGE_TXCFG); 1731 1732 /* 1733 * Enable TX IPv4 checksumming on a per-packet basis. 1734 */ 1735 if (ifp->if_hwassist) 1736 CSR_WRITE_4(sc, NGE_VLAN_IP_TXCTL, NGE_VIPTXCTL_CSUM_PER_PKT); 1737 1738 #if NVLAN > 0 1739 /* 1740 * If VLAN support is enabled, tell the chip to insert 1741 * VLAN tags on a per-packet basis as dictated by the 1742 * code in the frame encapsulation routine. 1743 */ 1744 NGE_SETBIT(sc, NGE_VLAN_IP_TXCTL, NGE_VIPTXCTL_TAG_PER_PKT); 1745 #endif 1746 1747 /* Set full/half duplex mode. */ 1748 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 1749 NGE_SETBIT(sc, NGE_TX_CFG, 1750 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 1751 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 1752 } else { 1753 NGE_CLRBIT(sc, NGE_TX_CFG, 1754 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 1755 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 1756 } 1757 1758 /* 1759 * Enable the delivery of PHY interrupts based on 1760 * link/speed/duplex status changes. 1761 */ 1762 NGE_SETBIT(sc, NGE_CFG, NGE_CFG_PHYINTR_SPD|NGE_CFG_MODE_1000| 1763 NGE_CFG_PHYINTR_LNK|NGE_CFG_PHYINTR_DUP); 1764 1765 /* 1766 * Enable interrupts. 1767 */ 1768 CSR_WRITE_4(sc, NGE_IMR, NGE_INTRS); 1769 CSR_WRITE_4(sc, NGE_IER, 1); 1770 1771 /* Enable receiver and transmitter. */ 1772 NGE_CLRBIT(sc, NGE_CSR, NGE_CSR_TX_DISABLE|NGE_CSR_RX_DISABLE); 1773 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE); 1774 1775 nge_ifmedia_upd(ifp); 1776 1777 ifp->if_flags |= IFF_RUNNING; 1778 ifp->if_flags &= ~IFF_OACTIVE; 1779 1780 (void)splx(s); 1781 1782 return; 1783 } 1784 1785 /* 1786 * Set media options. 1787 */ 1788 static int nge_ifmedia_upd(ifp) 1789 struct ifnet *ifp; 1790 { 1791 struct nge_softc *sc; 1792 struct mii_data *mii; 1793 1794 sc = ifp->if_softc; 1795 1796 mii = device_get_softc(sc->nge_miibus); 1797 sc->nge_link = 0; 1798 if (mii->mii_instance) { 1799 struct mii_softc *miisc; 1800 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 1801 miisc = LIST_NEXT(miisc, mii_list)) 1802 mii_phy_reset(miisc); 1803 } 1804 mii_mediachg(mii); 1805 1806 return(0); 1807 } 1808 1809 /* 1810 * Report current media status. 1811 */ 1812 static void nge_ifmedia_sts(ifp, ifmr) 1813 struct ifnet *ifp; 1814 struct ifmediareq *ifmr; 1815 { 1816 struct nge_softc *sc; 1817 struct mii_data *mii; 1818 1819 sc = ifp->if_softc; 1820 1821 mii = device_get_softc(sc->nge_miibus); 1822 mii_pollstat(mii); 1823 ifmr->ifm_active = mii->mii_media_active; 1824 ifmr->ifm_status = mii->mii_media_status; 1825 1826 return; 1827 } 1828 1829 static int nge_ioctl(ifp, command, data) 1830 struct ifnet *ifp; 1831 u_long command; 1832 caddr_t data; 1833 { 1834 struct nge_softc *sc = ifp->if_softc; 1835 struct ifreq *ifr = (struct ifreq *) data; 1836 struct mii_data *mii; 1837 int s, error = 0; 1838 1839 s = splimp(); 1840 1841 switch(command) { 1842 case SIOCSIFADDR: 1843 case SIOCGIFADDR: 1844 error = ether_ioctl(ifp, command, data); 1845 break; 1846 case SIOCSIFMTU: 1847 if (ifr->ifr_mtu > NGE_JUMBO_MTU) 1848 error = EINVAL; 1849 else 1850 ifp->if_mtu = ifr->ifr_mtu; 1851 break; 1852 case SIOCSIFFLAGS: 1853 if (ifp->if_flags & IFF_UP) { 1854 if (ifp->if_flags & IFF_RUNNING && 1855 ifp->if_flags & IFF_PROMISC && 1856 !(sc->nge_if_flags & IFF_PROMISC)) { 1857 NGE_SETBIT(sc, NGE_RXFILT_CTL, 1858 NGE_RXFILTCTL_ALLPHYS| 1859 NGE_RXFILTCTL_ALLMULTI); 1860 } else if (ifp->if_flags & IFF_RUNNING && 1861 !(ifp->if_flags & IFF_PROMISC) && 1862 sc->nge_if_flags & IFF_PROMISC) { 1863 NGE_CLRBIT(sc, NGE_RXFILT_CTL, 1864 NGE_RXFILTCTL_ALLPHYS); 1865 if (!(ifp->if_flags & IFF_ALLMULTI)) 1866 NGE_CLRBIT(sc, NGE_RXFILT_CTL, 1867 NGE_RXFILTCTL_ALLMULTI); 1868 } else { 1869 ifp->if_flags &= ~IFF_RUNNING; 1870 nge_init(sc); 1871 } 1872 } else { 1873 if (ifp->if_flags & IFF_RUNNING) 1874 nge_stop(sc); 1875 } 1876 sc->nge_if_flags = ifp->if_flags; 1877 error = 0; 1878 break; 1879 case SIOCADDMULTI: 1880 case SIOCDELMULTI: 1881 nge_setmulti(sc); 1882 error = 0; 1883 break; 1884 case SIOCGIFMEDIA: 1885 case SIOCSIFMEDIA: 1886 mii = device_get_softc(sc->nge_miibus); 1887 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1888 break; 1889 default: 1890 error = EINVAL; 1891 break; 1892 } 1893 1894 (void)splx(s); 1895 1896 return(error); 1897 } 1898 1899 static void nge_watchdog(ifp) 1900 struct ifnet *ifp; 1901 { 1902 struct nge_softc *sc; 1903 1904 sc = ifp->if_softc; 1905 1906 ifp->if_oerrors++; 1907 printf("nge%d: watchdog timeout\n", sc->nge_unit); 1908 1909 nge_stop(sc); 1910 nge_reset(sc); 1911 ifp->if_flags &= ~IFF_RUNNING; 1912 nge_init(sc); 1913 1914 if (ifp->if_snd.ifq_head != NULL) 1915 nge_start(ifp); 1916 1917 return; 1918 } 1919 1920 /* 1921 * Stop the adapter and free any mbufs allocated to the 1922 * RX and TX lists. 1923 */ 1924 static void nge_stop(sc) 1925 struct nge_softc *sc; 1926 { 1927 register int i; 1928 struct ifnet *ifp; 1929 struct ifmedia_entry *ifm; 1930 struct mii_data *mii; 1931 int mtmp, itmp; 1932 1933 ifp = &sc->arpcom.ac_if; 1934 ifp->if_timer = 0; 1935 mii = device_get_softc(sc->nge_miibus); 1936 1937 untimeout(nge_tick, sc, sc->nge_stat_ch); 1938 CSR_WRITE_4(sc, NGE_IER, 0); 1939 CSR_WRITE_4(sc, NGE_IMR, 0); 1940 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_TX_DISABLE|NGE_CSR_RX_DISABLE); 1941 DELAY(1000); 1942 CSR_WRITE_4(sc, NGE_TX_LISTPTR, 0); 1943 CSR_WRITE_4(sc, NGE_RX_LISTPTR, 0); 1944 1945 /* 1946 * Isolate/power down the PHY, but leave the media selection 1947 * unchanged so that things will be put back to normal when 1948 * we bring the interface back up. 1949 */ 1950 itmp = ifp->if_flags; 1951 ifp->if_flags |= IFF_UP; 1952 ifm = mii->mii_media.ifm_cur; 1953 mtmp = ifm->ifm_media; 1954 ifm->ifm_media = IFM_ETHER|IFM_NONE; 1955 mii_mediachg(mii); 1956 ifm->ifm_media = mtmp; 1957 ifp->if_flags = itmp; 1958 1959 sc->nge_link = 0; 1960 1961 /* 1962 * Free data in the RX lists. 1963 */ 1964 for (i = 0; i < NGE_RX_LIST_CNT; i++) { 1965 if (sc->nge_ldata->nge_rx_list[i].nge_mbuf != NULL) { 1966 m_freem(sc->nge_ldata->nge_rx_list[i].nge_mbuf); 1967 sc->nge_ldata->nge_rx_list[i].nge_mbuf = NULL; 1968 } 1969 } 1970 bzero((char *)&sc->nge_ldata->nge_rx_list, 1971 sizeof(sc->nge_ldata->nge_rx_list)); 1972 1973 /* 1974 * Free the TX list buffers. 1975 */ 1976 for (i = 0; i < NGE_TX_LIST_CNT; i++) { 1977 if (sc->nge_ldata->nge_tx_list[i].nge_mbuf != NULL) { 1978 m_freem(sc->nge_ldata->nge_tx_list[i].nge_mbuf); 1979 sc->nge_ldata->nge_tx_list[i].nge_mbuf = NULL; 1980 } 1981 } 1982 1983 bzero((char *)&sc->nge_ldata->nge_tx_list, 1984 sizeof(sc->nge_ldata->nge_tx_list)); 1985 1986 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1987 1988 return; 1989 } 1990 1991 /* 1992 * Stop all chip I/O so that the kernel's probe routines don't 1993 * get confused by errant DMAs when rebooting. 1994 */ 1995 static void nge_shutdown(dev) 1996 device_t dev; 1997 { 1998 struct nge_softc *sc; 1999 2000 sc = device_get_softc(dev); 2001 2002 nge_reset(sc); 2003 nge_stop(sc); 2004 2005 return; 2006 } 2007