1 /*- 2 * SPDX-License-Identifier: BSD-4-Clause 3 * 4 * Copyright (c) 2001 Wind River Systems 5 * Copyright (c) 1997, 1998, 1999, 2000, 2001 6 * Bill Paul <wpaul@bsdi.com>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 */ 35 36 #include <sys/cdefs.h> 37 /* 38 * National Semiconductor DP83820/DP83821 gigabit ethernet driver 39 * for FreeBSD. Datasheets are available from: 40 * 41 * http://www.national.com/ds/DP/DP83820.pdf 42 * http://www.national.com/ds/DP/DP83821.pdf 43 * 44 * These chips are used on several low cost gigabit ethernet NICs 45 * sold by D-Link, Addtron, SMC and Asante. Both parts are 46 * virtually the same, except the 83820 is a 64-bit/32-bit part, 47 * while the 83821 is 32-bit only. 48 * 49 * Many cards also use National gigE transceivers, such as the 50 * DP83891, DP83861 and DP83862 gigPHYTER parts. The DP83861 datasheet 51 * contains a full register description that applies to all of these 52 * components: 53 * 54 * http://www.national.com/ds/DP/DP83861.pdf 55 * 56 * Written by Bill Paul <wpaul@bsdi.com> 57 * BSDi Open Source Solutions 58 */ 59 60 /* 61 * The NatSemi DP83820 and 83821 controllers are enhanced versions 62 * of the NatSemi MacPHYTER 10/100 devices. They support 10, 100 63 * and 1000Mbps speeds with 1000baseX (ten bit interface), MII and GMII 64 * ports. Other features include 8K TX FIFO and 32K RX FIFO, TCP/IP 65 * hardware checksum offload (IPv4 only), VLAN tagging and filtering, 66 * priority TX and RX queues, a 2048 bit multicast hash filter, 4 RX pattern 67 * matching buffers, one perfect address filter buffer and interrupt 68 * moderation. The 83820 supports both 64-bit and 32-bit addressing 69 * and data transfers: the 64-bit support can be toggled on or off 70 * via software. This affects the size of certain fields in the DMA 71 * descriptors. 72 * 73 * There are two bugs/misfeatures in the 83820/83821 that I have 74 * discovered so far: 75 * 76 * - Receive buffers must be aligned on 64-bit boundaries, which means 77 * you must resort to copying data in order to fix up the payload 78 * alignment. 79 * 80 * - In order to transmit jumbo frames larger than 8170 bytes, you have 81 * to turn off transmit checksum offloading, because the chip can't 82 * compute the checksum on an outgoing frame unless it fits entirely 83 * within the TX FIFO, which is only 8192 bytes in size. If you have 84 * TX checksum offload enabled and you transmit attempt to transmit a 85 * frame larger than 8170 bytes, the transmitter will wedge. 86 * 87 * To work around the latter problem, TX checksum offload is disabled 88 * if the user selects an MTU larger than 8152 (8170 - 18). 89 */ 90 91 #ifdef HAVE_KERNEL_OPTION_HEADERS 92 #include "opt_device_polling.h" 93 #endif 94 95 #include <sys/param.h> 96 #include <sys/systm.h> 97 #include <sys/bus.h> 98 #include <sys/endian.h> 99 #include <sys/kernel.h> 100 #include <sys/lock.h> 101 #include <sys/malloc.h> 102 #include <sys/mbuf.h> 103 #include <sys/module.h> 104 #include <sys/mutex.h> 105 #include <sys/rman.h> 106 #include <sys/socket.h> 107 #include <sys/sockio.h> 108 #include <sys/sysctl.h> 109 110 #include <net/bpf.h> 111 #include <net/if.h> 112 #include <net/if_var.h> 113 #include <net/if_arp.h> 114 #include <net/ethernet.h> 115 #include <net/if_dl.h> 116 #include <net/if_media.h> 117 #include <net/if_types.h> 118 #include <net/if_vlan_var.h> 119 120 #include <dev/mii/mii.h> 121 #include <dev/mii/mii_bitbang.h> 122 #include <dev/mii/miivar.h> 123 124 #include <dev/pci/pcireg.h> 125 #include <dev/pci/pcivar.h> 126 127 #include <machine/bus.h> 128 129 #include <dev/nge/if_ngereg.h> 130 131 /* "device miibus" required. See GENERIC if you get errors here. */ 132 #include "miibus_if.h" 133 134 MODULE_DEPEND(nge, pci, 1, 1, 1); 135 MODULE_DEPEND(nge, ether, 1, 1, 1); 136 MODULE_DEPEND(nge, miibus, 1, 1, 1); 137 138 #define NGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 139 140 /* 141 * Various supported device vendors/types and their names. 142 */ 143 static const struct nge_type nge_devs[] = { 144 { NGE_VENDORID, NGE_DEVICEID, 145 "National Semiconductor Gigabit Ethernet" }, 146 { 0, 0, NULL } 147 }; 148 149 static int nge_probe(device_t); 150 static int nge_attach(device_t); 151 static int nge_detach(device_t); 152 static int nge_shutdown(device_t); 153 static int nge_suspend(device_t); 154 static int nge_resume(device_t); 155 156 static __inline void nge_discard_rxbuf(struct nge_softc *, int); 157 static int nge_newbuf(struct nge_softc *, int); 158 static int nge_encap(struct nge_softc *, struct mbuf **); 159 #ifndef __NO_STRICT_ALIGNMENT 160 static __inline void nge_fixup_rx(struct mbuf *); 161 #endif 162 static int nge_rxeof(struct nge_softc *); 163 static void nge_txeof(struct nge_softc *); 164 static void nge_intr(void *); 165 static void nge_tick(void *); 166 static void nge_stats_update(struct nge_softc *); 167 static void nge_start(if_t); 168 static void nge_start_locked(if_t); 169 static int nge_ioctl(if_t, u_long, caddr_t); 170 static void nge_init(void *); 171 static void nge_init_locked(struct nge_softc *); 172 static int nge_stop_mac(struct nge_softc *); 173 static void nge_stop(struct nge_softc *); 174 static void nge_wol(struct nge_softc *); 175 static void nge_watchdog(struct nge_softc *); 176 static int nge_mediachange(if_t); 177 static void nge_mediastatus(if_t, struct ifmediareq *); 178 179 static void nge_delay(struct nge_softc *); 180 static void nge_eeprom_idle(struct nge_softc *); 181 static void nge_eeprom_putbyte(struct nge_softc *, int); 182 static void nge_eeprom_getword(struct nge_softc *, int, uint16_t *); 183 static void nge_read_eeprom(struct nge_softc *, caddr_t, int, int); 184 185 static int nge_miibus_readreg(device_t, int, int); 186 static int nge_miibus_writereg(device_t, int, int, int); 187 static void nge_miibus_statchg(device_t); 188 189 static void nge_rxfilter(struct nge_softc *); 190 static void nge_reset(struct nge_softc *); 191 static void nge_dmamap_cb(void *, bus_dma_segment_t *, int, int); 192 static int nge_dma_alloc(struct nge_softc *); 193 static void nge_dma_free(struct nge_softc *); 194 static int nge_list_rx_init(struct nge_softc *); 195 static int nge_list_tx_init(struct nge_softc *); 196 static void nge_sysctl_node(struct nge_softc *); 197 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int); 198 static int sysctl_hw_nge_int_holdoff(SYSCTL_HANDLER_ARGS); 199 200 /* 201 * MII bit-bang glue 202 */ 203 static uint32_t nge_mii_bitbang_read(device_t); 204 static void nge_mii_bitbang_write(device_t, uint32_t); 205 206 static const struct mii_bitbang_ops nge_mii_bitbang_ops = { 207 nge_mii_bitbang_read, 208 nge_mii_bitbang_write, 209 { 210 NGE_MEAR_MII_DATA, /* MII_BIT_MDO */ 211 NGE_MEAR_MII_DATA, /* MII_BIT_MDI */ 212 NGE_MEAR_MII_CLK, /* MII_BIT_MDC */ 213 NGE_MEAR_MII_DIR, /* MII_BIT_DIR_HOST_PHY */ 214 0, /* MII_BIT_DIR_PHY_HOST */ 215 } 216 }; 217 218 static device_method_t nge_methods[] = { 219 /* Device interface */ 220 DEVMETHOD(device_probe, nge_probe), 221 DEVMETHOD(device_attach, nge_attach), 222 DEVMETHOD(device_detach, nge_detach), 223 DEVMETHOD(device_shutdown, nge_shutdown), 224 DEVMETHOD(device_suspend, nge_suspend), 225 DEVMETHOD(device_resume, nge_resume), 226 227 /* MII interface */ 228 DEVMETHOD(miibus_readreg, nge_miibus_readreg), 229 DEVMETHOD(miibus_writereg, nge_miibus_writereg), 230 DEVMETHOD(miibus_statchg, nge_miibus_statchg), 231 232 DEVMETHOD_END 233 }; 234 235 static driver_t nge_driver = { 236 "nge", 237 nge_methods, 238 sizeof(struct nge_softc) 239 }; 240 241 DRIVER_MODULE(nge, pci, nge_driver, 0, 0); 242 DRIVER_MODULE(miibus, nge, miibus_driver, 0, 0); 243 244 #define NGE_SETBIT(sc, reg, x) \ 245 CSR_WRITE_4(sc, reg, \ 246 CSR_READ_4(sc, reg) | (x)) 247 248 #define NGE_CLRBIT(sc, reg, x) \ 249 CSR_WRITE_4(sc, reg, \ 250 CSR_READ_4(sc, reg) & ~(x)) 251 252 #define SIO_SET(x) \ 253 CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) | (x)) 254 255 #define SIO_CLR(x) \ 256 CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) & ~(x)) 257 258 static void 259 nge_delay(struct nge_softc *sc) 260 { 261 int idx; 262 263 for (idx = (300 / 33) + 1; idx > 0; idx--) 264 CSR_READ_4(sc, NGE_CSR); 265 } 266 267 static void 268 nge_eeprom_idle(struct nge_softc *sc) 269 { 270 int i; 271 272 SIO_SET(NGE_MEAR_EE_CSEL); 273 nge_delay(sc); 274 SIO_SET(NGE_MEAR_EE_CLK); 275 nge_delay(sc); 276 277 for (i = 0; i < 25; i++) { 278 SIO_CLR(NGE_MEAR_EE_CLK); 279 nge_delay(sc); 280 SIO_SET(NGE_MEAR_EE_CLK); 281 nge_delay(sc); 282 } 283 284 SIO_CLR(NGE_MEAR_EE_CLK); 285 nge_delay(sc); 286 SIO_CLR(NGE_MEAR_EE_CSEL); 287 nge_delay(sc); 288 CSR_WRITE_4(sc, NGE_MEAR, 0x00000000); 289 } 290 291 /* 292 * Send a read command and address to the EEPROM, check for ACK. 293 */ 294 static void 295 nge_eeprom_putbyte(struct nge_softc *sc, int addr) 296 { 297 int d, i; 298 299 d = addr | NGE_EECMD_READ; 300 301 /* 302 * Feed in each bit and stobe the clock. 303 */ 304 for (i = 0x400; i; i >>= 1) { 305 if (d & i) { 306 SIO_SET(NGE_MEAR_EE_DIN); 307 } else { 308 SIO_CLR(NGE_MEAR_EE_DIN); 309 } 310 nge_delay(sc); 311 SIO_SET(NGE_MEAR_EE_CLK); 312 nge_delay(sc); 313 SIO_CLR(NGE_MEAR_EE_CLK); 314 nge_delay(sc); 315 } 316 } 317 318 /* 319 * Read a word of data stored in the EEPROM at address 'addr.' 320 */ 321 static void 322 nge_eeprom_getword(struct nge_softc *sc, int addr, uint16_t *dest) 323 { 324 int i; 325 uint16_t word = 0; 326 327 /* Force EEPROM to idle state. */ 328 nge_eeprom_idle(sc); 329 330 /* Enter EEPROM access mode. */ 331 nge_delay(sc); 332 SIO_CLR(NGE_MEAR_EE_CLK); 333 nge_delay(sc); 334 SIO_SET(NGE_MEAR_EE_CSEL); 335 nge_delay(sc); 336 337 /* 338 * Send address of word we want to read. 339 */ 340 nge_eeprom_putbyte(sc, addr); 341 342 /* 343 * Start reading bits from EEPROM. 344 */ 345 for (i = 0x8000; i; i >>= 1) { 346 SIO_SET(NGE_MEAR_EE_CLK); 347 nge_delay(sc); 348 if (CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_EE_DOUT) 349 word |= i; 350 nge_delay(sc); 351 SIO_CLR(NGE_MEAR_EE_CLK); 352 nge_delay(sc); 353 } 354 355 /* Turn off EEPROM access mode. */ 356 nge_eeprom_idle(sc); 357 358 *dest = word; 359 } 360 361 /* 362 * Read a sequence of words from the EEPROM. 363 */ 364 static void 365 nge_read_eeprom(struct nge_softc *sc, caddr_t dest, int off, int cnt) 366 { 367 int i; 368 uint16_t word = 0, *ptr; 369 370 for (i = 0; i < cnt; i++) { 371 nge_eeprom_getword(sc, off + i, &word); 372 ptr = (uint16_t *)(dest + (i * 2)); 373 *ptr = word; 374 } 375 } 376 377 /* 378 * Read the MII serial port for the MII bit-bang module. 379 */ 380 static uint32_t 381 nge_mii_bitbang_read(device_t dev) 382 { 383 struct nge_softc *sc; 384 uint32_t val; 385 386 sc = device_get_softc(dev); 387 388 val = CSR_READ_4(sc, NGE_MEAR); 389 CSR_BARRIER_4(sc, NGE_MEAR, 390 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 391 392 return (val); 393 } 394 395 /* 396 * Write the MII serial port for the MII bit-bang module. 397 */ 398 static void 399 nge_mii_bitbang_write(device_t dev, uint32_t val) 400 { 401 struct nge_softc *sc; 402 403 sc = device_get_softc(dev); 404 405 CSR_WRITE_4(sc, NGE_MEAR, val); 406 CSR_BARRIER_4(sc, NGE_MEAR, 407 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 408 } 409 410 static int 411 nge_miibus_readreg(device_t dev, int phy, int reg) 412 { 413 struct nge_softc *sc; 414 int rv; 415 416 sc = device_get_softc(dev); 417 if ((sc->nge_flags & NGE_FLAG_TBI) != 0) { 418 /* Pretend PHY is at address 0. */ 419 if (phy != 0) 420 return (0); 421 switch (reg) { 422 case MII_BMCR: 423 reg = NGE_TBI_BMCR; 424 break; 425 case MII_BMSR: 426 /* 83820/83821 has different bit layout for BMSR. */ 427 rv = BMSR_ANEG | BMSR_EXTCAP | BMSR_EXTSTAT; 428 reg = CSR_READ_4(sc, NGE_TBI_BMSR); 429 if ((reg & NGE_TBIBMSR_ANEG_DONE) != 0) 430 rv |= BMSR_ACOMP; 431 if ((reg & NGE_TBIBMSR_LINKSTAT) != 0) 432 rv |= BMSR_LINK; 433 return (rv); 434 case MII_ANAR: 435 reg = NGE_TBI_ANAR; 436 break; 437 case MII_ANLPAR: 438 reg = NGE_TBI_ANLPAR; 439 break; 440 case MII_ANER: 441 reg = NGE_TBI_ANER; 442 break; 443 case MII_EXTSR: 444 reg = NGE_TBI_ESR; 445 break; 446 case MII_PHYIDR1: 447 case MII_PHYIDR2: 448 return (0); 449 default: 450 device_printf(sc->nge_dev, 451 "bad phy register read : %d\n", reg); 452 return (0); 453 } 454 return (CSR_READ_4(sc, reg)); 455 } 456 457 return (mii_bitbang_readreg(dev, &nge_mii_bitbang_ops, phy, reg)); 458 } 459 460 static int 461 nge_miibus_writereg(device_t dev, int phy, int reg, int data) 462 { 463 struct nge_softc *sc; 464 465 sc = device_get_softc(dev); 466 if ((sc->nge_flags & NGE_FLAG_TBI) != 0) { 467 /* Pretend PHY is at address 0. */ 468 if (phy != 0) 469 return (0); 470 switch (reg) { 471 case MII_BMCR: 472 reg = NGE_TBI_BMCR; 473 break; 474 case MII_BMSR: 475 return (0); 476 case MII_ANAR: 477 reg = NGE_TBI_ANAR; 478 break; 479 case MII_ANLPAR: 480 reg = NGE_TBI_ANLPAR; 481 break; 482 case MII_ANER: 483 reg = NGE_TBI_ANER; 484 break; 485 case MII_EXTSR: 486 reg = NGE_TBI_ESR; 487 break; 488 case MII_PHYIDR1: 489 case MII_PHYIDR2: 490 return (0); 491 default: 492 device_printf(sc->nge_dev, 493 "bad phy register write : %d\n", reg); 494 return (0); 495 } 496 CSR_WRITE_4(sc, reg, data); 497 return (0); 498 } 499 500 mii_bitbang_writereg(dev, &nge_mii_bitbang_ops, phy, reg, data); 501 502 return (0); 503 } 504 505 /* 506 * media status/link state change handler. 507 */ 508 static void 509 nge_miibus_statchg(device_t dev) 510 { 511 struct nge_softc *sc; 512 struct mii_data *mii; 513 if_t ifp; 514 struct nge_txdesc *txd; 515 uint32_t done, reg, status; 516 int i; 517 518 sc = device_get_softc(dev); 519 NGE_LOCK_ASSERT(sc); 520 521 mii = device_get_softc(sc->nge_miibus); 522 ifp = sc->nge_ifp; 523 if (mii == NULL || ifp == NULL || 524 (if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) 525 return; 526 527 sc->nge_flags &= ~NGE_FLAG_LINK; 528 if ((mii->mii_media_status & (IFM_AVALID | IFM_ACTIVE)) == 529 (IFM_AVALID | IFM_ACTIVE)) { 530 switch (IFM_SUBTYPE(mii->mii_media_active)) { 531 case IFM_10_T: 532 case IFM_100_TX: 533 case IFM_1000_T: 534 case IFM_1000_SX: 535 case IFM_1000_LX: 536 case IFM_1000_CX: 537 sc->nge_flags |= NGE_FLAG_LINK; 538 break; 539 default: 540 break; 541 } 542 } 543 544 /* Stop Tx/Rx MACs. */ 545 if (nge_stop_mac(sc) == ETIMEDOUT) 546 device_printf(sc->nge_dev, 547 "%s: unable to stop Tx/Rx MAC\n", __func__); 548 nge_txeof(sc); 549 nge_rxeof(sc); 550 if (sc->nge_head != NULL) { 551 m_freem(sc->nge_head); 552 sc->nge_head = sc->nge_tail = NULL; 553 } 554 555 /* Release queued frames. */ 556 for (i = 0; i < NGE_TX_RING_CNT; i++) { 557 txd = &sc->nge_cdata.nge_txdesc[i]; 558 if (txd->tx_m != NULL) { 559 bus_dmamap_sync(sc->nge_cdata.nge_tx_tag, 560 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 561 bus_dmamap_unload(sc->nge_cdata.nge_tx_tag, 562 txd->tx_dmamap); 563 m_freem(txd->tx_m); 564 txd->tx_m = NULL; 565 } 566 } 567 568 /* Program MAC with resolved speed/duplex. */ 569 if ((sc->nge_flags & NGE_FLAG_LINK) != 0) { 570 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 571 NGE_SETBIT(sc, NGE_TX_CFG, 572 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR)); 573 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 574 #ifdef notyet 575 /* Enable flow-control. */ 576 if ((IFM_OPTIONS(mii->mii_media_active) & 577 (IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE)) != 0) 578 NGE_SETBIT(sc, NGE_PAUSECSR, 579 NGE_PAUSECSR_PAUSE_ENB); 580 #endif 581 } else { 582 NGE_CLRBIT(sc, NGE_TX_CFG, 583 (NGE_TXCFG_IGN_HBEAT | NGE_TXCFG_IGN_CARR)); 584 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 585 NGE_CLRBIT(sc, NGE_PAUSECSR, NGE_PAUSECSR_PAUSE_ENB); 586 } 587 /* If we have a 1000Mbps link, set the mode_1000 bit. */ 588 reg = CSR_READ_4(sc, NGE_CFG); 589 switch (IFM_SUBTYPE(mii->mii_media_active)) { 590 case IFM_1000_SX: 591 case IFM_1000_LX: 592 case IFM_1000_CX: 593 case IFM_1000_T: 594 reg |= NGE_CFG_MODE_1000; 595 break; 596 default: 597 reg &= ~NGE_CFG_MODE_1000; 598 break; 599 } 600 CSR_WRITE_4(sc, NGE_CFG, reg); 601 602 /* Reset Tx/Rx MAC. */ 603 reg = CSR_READ_4(sc, NGE_CSR); 604 reg |= NGE_CSR_TX_RESET | NGE_CSR_RX_RESET; 605 CSR_WRITE_4(sc, NGE_CSR, reg); 606 /* Check the completion of reset. */ 607 done = 0; 608 for (i = 0; i < NGE_TIMEOUT; i++) { 609 DELAY(1); 610 status = CSR_READ_4(sc, NGE_ISR); 611 if ((status & NGE_ISR_RX_RESET_DONE) != 0) 612 done |= NGE_ISR_RX_RESET_DONE; 613 if ((status & NGE_ISR_TX_RESET_DONE) != 0) 614 done |= NGE_ISR_TX_RESET_DONE; 615 if (done == 616 (NGE_ISR_TX_RESET_DONE | NGE_ISR_RX_RESET_DONE)) 617 break; 618 } 619 if (i == NGE_TIMEOUT) 620 device_printf(sc->nge_dev, 621 "%s: unable to reset Tx/Rx MAC\n", __func__); 622 /* Reuse Rx buffer and reset consumer pointer. */ 623 sc->nge_cdata.nge_rx_cons = 0; 624 /* 625 * It seems that resetting Rx/Tx MAC results in 626 * resetting Tx/Rx descriptor pointer registers such 627 * that reloading Tx/Rx lists address are needed. 628 */ 629 CSR_WRITE_4(sc, NGE_RX_LISTPTR_HI, 630 NGE_ADDR_HI(sc->nge_rdata.nge_rx_ring_paddr)); 631 CSR_WRITE_4(sc, NGE_RX_LISTPTR_LO, 632 NGE_ADDR_LO(sc->nge_rdata.nge_rx_ring_paddr)); 633 CSR_WRITE_4(sc, NGE_TX_LISTPTR_HI, 634 NGE_ADDR_HI(sc->nge_rdata.nge_tx_ring_paddr)); 635 CSR_WRITE_4(sc, NGE_TX_LISTPTR_LO, 636 NGE_ADDR_LO(sc->nge_rdata.nge_tx_ring_paddr)); 637 /* Reinitialize Tx buffers. */ 638 nge_list_tx_init(sc); 639 640 /* Restart Rx MAC. */ 641 reg = CSR_READ_4(sc, NGE_CSR); 642 reg |= NGE_CSR_RX_ENABLE; 643 CSR_WRITE_4(sc, NGE_CSR, reg); 644 for (i = 0; i < NGE_TIMEOUT; i++) { 645 if ((CSR_READ_4(sc, NGE_CSR) & NGE_CSR_RX_ENABLE) != 0) 646 break; 647 DELAY(1); 648 } 649 if (i == NGE_TIMEOUT) 650 device_printf(sc->nge_dev, 651 "%s: unable to restart Rx MAC\n", __func__); 652 } 653 654 /* Data LED off for TBI mode */ 655 if ((sc->nge_flags & NGE_FLAG_TBI) != 0) 656 CSR_WRITE_4(sc, NGE_GPIO, 657 CSR_READ_4(sc, NGE_GPIO) & ~NGE_GPIO_GP3_OUT); 658 } 659 660 static u_int 661 nge_write_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) 662 { 663 struct nge_softc *sc = arg; 664 uint32_t h; 665 int bit, index; 666 667 /* 668 * From the 11 bits returned by the crc routine, the top 7 669 * bits represent the 16-bit word in the mcast hash table 670 * that needs to be updated, and the lower 4 bits represent 671 * which bit within that byte needs to be set. 672 */ 673 h = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN) >> 21; 674 index = (h >> 4) & 0x7F; 675 bit = h & 0xF; 676 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_MCAST_LO + (index * 2)); 677 NGE_SETBIT(sc, NGE_RXFILT_DATA, (1 << bit)); 678 679 return (1); 680 } 681 682 static void 683 nge_rxfilter(struct nge_softc *sc) 684 { 685 if_t ifp; 686 uint32_t i, rxfilt; 687 688 NGE_LOCK_ASSERT(sc); 689 ifp = sc->nge_ifp; 690 691 /* Make sure to stop Rx filtering. */ 692 rxfilt = CSR_READ_4(sc, NGE_RXFILT_CTL); 693 rxfilt &= ~NGE_RXFILTCTL_ENABLE; 694 CSR_WRITE_4(sc, NGE_RXFILT_CTL, rxfilt); 695 CSR_BARRIER_4(sc, NGE_RXFILT_CTL, BUS_SPACE_BARRIER_WRITE); 696 697 rxfilt &= ~(NGE_RXFILTCTL_ALLMULTI | NGE_RXFILTCTL_ALLPHYS); 698 rxfilt &= ~NGE_RXFILTCTL_BROAD; 699 /* 700 * We don't want to use the hash table for matching unicast 701 * addresses. 702 */ 703 rxfilt &= ~(NGE_RXFILTCTL_MCHASH | NGE_RXFILTCTL_UCHASH); 704 705 /* 706 * For the NatSemi chip, we have to explicitly enable the 707 * reception of ARP frames, as well as turn on the 'perfect 708 * match' filter where we store the station address, otherwise 709 * we won't receive unicasts meant for this host. 710 */ 711 rxfilt |= NGE_RXFILTCTL_ARP | NGE_RXFILTCTL_PERFECT; 712 713 /* 714 * Set the capture broadcast bit to capture broadcast frames. 715 */ 716 if ((if_getflags(ifp) & IFF_BROADCAST) != 0) 717 rxfilt |= NGE_RXFILTCTL_BROAD; 718 719 if ((if_getflags(ifp) & IFF_PROMISC) != 0 || 720 (if_getflags(ifp) & IFF_ALLMULTI) != 0) { 721 rxfilt |= NGE_RXFILTCTL_ALLMULTI; 722 if ((if_getflags(ifp) & IFF_PROMISC) != 0) 723 rxfilt |= NGE_RXFILTCTL_ALLPHYS; 724 goto done; 725 } 726 727 /* 728 * We have to explicitly enable the multicast hash table 729 * on the NatSemi chip if we want to use it, which we do. 730 */ 731 rxfilt |= NGE_RXFILTCTL_MCHASH; 732 733 /* first, zot all the existing hash bits */ 734 for (i = 0; i < NGE_MCAST_FILTER_LEN; i += 2) { 735 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_MCAST_LO + i); 736 CSR_WRITE_4(sc, NGE_RXFILT_DATA, 0); 737 } 738 739 if_foreach_llmaddr(ifp, nge_write_maddr, sc); 740 done: 741 CSR_WRITE_4(sc, NGE_RXFILT_CTL, rxfilt); 742 /* Turn the receive filter on. */ 743 rxfilt |= NGE_RXFILTCTL_ENABLE; 744 CSR_WRITE_4(sc, NGE_RXFILT_CTL, rxfilt); 745 CSR_BARRIER_4(sc, NGE_RXFILT_CTL, BUS_SPACE_BARRIER_WRITE); 746 } 747 748 static void 749 nge_reset(struct nge_softc *sc) 750 { 751 uint32_t v; 752 int i; 753 754 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RESET); 755 756 for (i = 0; i < NGE_TIMEOUT; i++) { 757 if (!(CSR_READ_4(sc, NGE_CSR) & NGE_CSR_RESET)) 758 break; 759 DELAY(1); 760 } 761 762 if (i == NGE_TIMEOUT) 763 device_printf(sc->nge_dev, "reset never completed\n"); 764 765 /* Wait a little while for the chip to get its brains in order. */ 766 DELAY(1000); 767 768 /* 769 * If this is a NetSemi chip, make sure to clear 770 * PME mode. 771 */ 772 CSR_WRITE_4(sc, NGE_CLKRUN, NGE_CLKRUN_PMESTS); 773 CSR_WRITE_4(sc, NGE_CLKRUN, 0); 774 775 /* Clear WOL events which may interfere normal Rx filter opertaion. */ 776 CSR_WRITE_4(sc, NGE_WOLCSR, 0); 777 778 /* 779 * Only DP83820 supports 64bits addressing/data transfers and 780 * 64bit addressing requires different descriptor structures. 781 * To make it simple, disable 64bit addressing/data transfers. 782 */ 783 v = CSR_READ_4(sc, NGE_CFG); 784 v &= ~(NGE_CFG_64BIT_ADDR_ENB | NGE_CFG_64BIT_DATA_ENB); 785 CSR_WRITE_4(sc, NGE_CFG, v); 786 } 787 788 /* 789 * Probe for a NatSemi chip. Check the PCI vendor and device 790 * IDs against our list and return a device name if we find a match. 791 */ 792 static int 793 nge_probe(device_t dev) 794 { 795 const struct nge_type *t; 796 797 t = nge_devs; 798 799 while (t->nge_name != NULL) { 800 if ((pci_get_vendor(dev) == t->nge_vid) && 801 (pci_get_device(dev) == t->nge_did)) { 802 device_set_desc(dev, t->nge_name); 803 return (BUS_PROBE_DEFAULT); 804 } 805 t++; 806 } 807 808 return (ENXIO); 809 } 810 811 /* 812 * Attach the interface. Allocate softc structures, do ifmedia 813 * setup and ethernet/BPF attach. 814 */ 815 static int 816 nge_attach(device_t dev) 817 { 818 uint8_t eaddr[ETHER_ADDR_LEN]; 819 uint16_t ea[ETHER_ADDR_LEN/2], ea_temp, reg; 820 struct nge_softc *sc; 821 if_t ifp; 822 int error, i, rid; 823 824 error = 0; 825 sc = device_get_softc(dev); 826 sc->nge_dev = dev; 827 828 NGE_LOCK_INIT(sc, device_get_nameunit(dev)); 829 callout_init_mtx(&sc->nge_stat_ch, &sc->nge_mtx, 0); 830 831 /* 832 * Map control/status registers. 833 */ 834 pci_enable_busmaster(dev); 835 836 #ifdef NGE_USEIOSPACE 837 sc->nge_res_type = SYS_RES_IOPORT; 838 sc->nge_res_id = PCIR_BAR(0); 839 #else 840 sc->nge_res_type = SYS_RES_MEMORY; 841 sc->nge_res_id = PCIR_BAR(1); 842 #endif 843 sc->nge_res = bus_alloc_resource_any(dev, sc->nge_res_type, 844 &sc->nge_res_id, RF_ACTIVE); 845 846 if (sc->nge_res == NULL) { 847 if (sc->nge_res_type == SYS_RES_MEMORY) { 848 sc->nge_res_type = SYS_RES_IOPORT; 849 sc->nge_res_id = PCIR_BAR(0); 850 } else { 851 sc->nge_res_type = SYS_RES_MEMORY; 852 sc->nge_res_id = PCIR_BAR(1); 853 } 854 sc->nge_res = bus_alloc_resource_any(dev, sc->nge_res_type, 855 &sc->nge_res_id, RF_ACTIVE); 856 if (sc->nge_res == NULL) { 857 device_printf(dev, "couldn't allocate %s resources\n", 858 sc->nge_res_type == SYS_RES_MEMORY ? "memory" : 859 "I/O"); 860 NGE_LOCK_DESTROY(sc); 861 return (ENXIO); 862 } 863 } 864 865 /* Allocate interrupt */ 866 rid = 0; 867 sc->nge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 868 RF_SHAREABLE | RF_ACTIVE); 869 870 if (sc->nge_irq == NULL) { 871 device_printf(dev, "couldn't map interrupt\n"); 872 error = ENXIO; 873 goto fail; 874 } 875 876 /* Enable MWI. */ 877 reg = pci_read_config(dev, PCIR_COMMAND, 2); 878 reg |= PCIM_CMD_MWRICEN; 879 pci_write_config(dev, PCIR_COMMAND, reg, 2); 880 881 /* Reset the adapter. */ 882 nge_reset(sc); 883 884 /* 885 * Get station address from the EEPROM. 886 */ 887 nge_read_eeprom(sc, (caddr_t)ea, NGE_EE_NODEADDR, 3); 888 for (i = 0; i < ETHER_ADDR_LEN / 2; i++) 889 ea[i] = le16toh(ea[i]); 890 ea_temp = ea[0]; 891 ea[0] = ea[2]; 892 ea[2] = ea_temp; 893 bcopy(ea, eaddr, sizeof(eaddr)); 894 895 if (nge_dma_alloc(sc) != 0) { 896 error = ENXIO; 897 goto fail; 898 } 899 900 nge_sysctl_node(sc); 901 902 ifp = sc->nge_ifp = if_alloc(IFT_ETHER); 903 if (ifp == NULL) { 904 device_printf(dev, "can not allocate ifnet structure\n"); 905 error = ENOSPC; 906 goto fail; 907 } 908 if_setsoftc(ifp, sc); 909 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 910 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 911 if_setioctlfn(ifp, nge_ioctl); 912 if_setstartfn(ifp, nge_start); 913 if_setinitfn(ifp, nge_init); 914 if_setsendqlen(ifp, NGE_TX_RING_CNT - 1); 915 if_setsendqready(ifp); 916 if_sethwassist(ifp, NGE_CSUM_FEATURES); 917 if_setcapabilities(ifp, IFCAP_HWCSUM); 918 /* 919 * It seems that some hardwares doesn't provide 3.3V auxiliary 920 * supply(3VAUX) to drive PME such that checking PCI power 921 * management capability is necessary. 922 */ 923 if (pci_find_cap(sc->nge_dev, PCIY_PMG, &i) == 0) 924 if_setcapabilitiesbit(ifp, IFCAP_WOL, 0); 925 if_setcapenable(ifp, if_getcapabilities(ifp)); 926 927 if ((CSR_READ_4(sc, NGE_CFG) & NGE_CFG_TBI_EN) != 0) { 928 sc->nge_flags |= NGE_FLAG_TBI; 929 device_printf(dev, "Using TBI\n"); 930 /* Configure GPIO. */ 931 CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO) 932 | NGE_GPIO_GP4_OUT 933 | NGE_GPIO_GP1_OUTENB | NGE_GPIO_GP2_OUTENB 934 | NGE_GPIO_GP3_OUTENB 935 | NGE_GPIO_GP3_IN | NGE_GPIO_GP4_IN); 936 } 937 938 /* 939 * Do MII setup. 940 */ 941 error = mii_attach(dev, &sc->nge_miibus, ifp, nge_mediachange, 942 nge_mediastatus, BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0); 943 if (error != 0) { 944 device_printf(dev, "attaching PHYs failed\n"); 945 goto fail; 946 } 947 948 /* 949 * Call MI attach routine. 950 */ 951 ether_ifattach(ifp, eaddr); 952 953 /* VLAN capability setup. */ 954 if_setcapabilitiesbit(ifp, IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING, 0); 955 if_setcapabilitiesbit(ifp, IFCAP_VLAN_HWCSUM, 0); 956 if_setcapenable(ifp, if_getcapabilities(ifp)); 957 #ifdef DEVICE_POLLING 958 if_setcapabilitiesbit(ifp, IFCAP_POLLING, 0); 959 #endif 960 /* 961 * Tell the upper layer(s) we support long frames. 962 * Must appear after the call to ether_ifattach() because 963 * ether_ifattach() sets ifi_hdrlen to the default value. 964 */ 965 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 966 967 /* 968 * Hookup IRQ last. 969 */ 970 error = bus_setup_intr(dev, sc->nge_irq, INTR_TYPE_NET | INTR_MPSAFE, 971 NULL, nge_intr, sc, &sc->nge_intrhand); 972 if (error) { 973 device_printf(dev, "couldn't set up irq\n"); 974 goto fail; 975 } 976 977 fail: 978 if (error != 0) 979 nge_detach(dev); 980 return (error); 981 } 982 983 static int 984 nge_detach(device_t dev) 985 { 986 struct nge_softc *sc; 987 if_t ifp; 988 989 sc = device_get_softc(dev); 990 ifp = sc->nge_ifp; 991 992 #ifdef DEVICE_POLLING 993 if (ifp != NULL && if_getcapenable(ifp) & IFCAP_POLLING) 994 ether_poll_deregister(ifp); 995 #endif 996 997 if (device_is_attached(dev)) { 998 NGE_LOCK(sc); 999 sc->nge_flags |= NGE_FLAG_DETACH; 1000 nge_stop(sc); 1001 NGE_UNLOCK(sc); 1002 callout_drain(&sc->nge_stat_ch); 1003 if (ifp != NULL) 1004 ether_ifdetach(ifp); 1005 } 1006 1007 if (sc->nge_miibus != NULL) { 1008 device_delete_child(dev, sc->nge_miibus); 1009 sc->nge_miibus = NULL; 1010 } 1011 bus_generic_detach(dev); 1012 if (sc->nge_intrhand != NULL) 1013 bus_teardown_intr(dev, sc->nge_irq, sc->nge_intrhand); 1014 if (sc->nge_irq != NULL) 1015 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq); 1016 if (sc->nge_res != NULL) 1017 bus_release_resource(dev, sc->nge_res_type, sc->nge_res_id, 1018 sc->nge_res); 1019 1020 nge_dma_free(sc); 1021 if (ifp != NULL) 1022 if_free(ifp); 1023 1024 NGE_LOCK_DESTROY(sc); 1025 1026 return (0); 1027 } 1028 1029 struct nge_dmamap_arg { 1030 bus_addr_t nge_busaddr; 1031 }; 1032 1033 static void 1034 nge_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1035 { 1036 struct nge_dmamap_arg *ctx; 1037 1038 if (error != 0) 1039 return; 1040 ctx = arg; 1041 ctx->nge_busaddr = segs[0].ds_addr; 1042 } 1043 1044 static int 1045 nge_dma_alloc(struct nge_softc *sc) 1046 { 1047 struct nge_dmamap_arg ctx; 1048 struct nge_txdesc *txd; 1049 struct nge_rxdesc *rxd; 1050 int error, i; 1051 1052 /* Create parent DMA tag. */ 1053 error = bus_dma_tag_create( 1054 bus_get_dma_tag(sc->nge_dev), /* parent */ 1055 1, 0, /* alignment, boundary */ 1056 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1057 BUS_SPACE_MAXADDR, /* highaddr */ 1058 NULL, NULL, /* filter, filterarg */ 1059 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1060 0, /* nsegments */ 1061 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1062 0, /* flags */ 1063 NULL, NULL, /* lockfunc, lockarg */ 1064 &sc->nge_cdata.nge_parent_tag); 1065 if (error != 0) { 1066 device_printf(sc->nge_dev, "failed to create parent DMA tag\n"); 1067 goto fail; 1068 } 1069 /* Create tag for Tx ring. */ 1070 error = bus_dma_tag_create(sc->nge_cdata.nge_parent_tag,/* parent */ 1071 NGE_RING_ALIGN, 0, /* alignment, boundary */ 1072 BUS_SPACE_MAXADDR, /* lowaddr */ 1073 BUS_SPACE_MAXADDR, /* highaddr */ 1074 NULL, NULL, /* filter, filterarg */ 1075 NGE_TX_RING_SIZE, /* maxsize */ 1076 1, /* nsegments */ 1077 NGE_TX_RING_SIZE, /* maxsegsize */ 1078 0, /* flags */ 1079 NULL, NULL, /* lockfunc, lockarg */ 1080 &sc->nge_cdata.nge_tx_ring_tag); 1081 if (error != 0) { 1082 device_printf(sc->nge_dev, "failed to create Tx ring DMA tag\n"); 1083 goto fail; 1084 } 1085 1086 /* Create tag for Rx ring. */ 1087 error = bus_dma_tag_create(sc->nge_cdata.nge_parent_tag,/* parent */ 1088 NGE_RING_ALIGN, 0, /* alignment, boundary */ 1089 BUS_SPACE_MAXADDR, /* lowaddr */ 1090 BUS_SPACE_MAXADDR, /* highaddr */ 1091 NULL, NULL, /* filter, filterarg */ 1092 NGE_RX_RING_SIZE, /* maxsize */ 1093 1, /* nsegments */ 1094 NGE_RX_RING_SIZE, /* maxsegsize */ 1095 0, /* flags */ 1096 NULL, NULL, /* lockfunc, lockarg */ 1097 &sc->nge_cdata.nge_rx_ring_tag); 1098 if (error != 0) { 1099 device_printf(sc->nge_dev, 1100 "failed to create Rx ring DMA tag\n"); 1101 goto fail; 1102 } 1103 1104 /* Create tag for Tx buffers. */ 1105 error = bus_dma_tag_create(sc->nge_cdata.nge_parent_tag,/* parent */ 1106 1, 0, /* alignment, boundary */ 1107 BUS_SPACE_MAXADDR, /* lowaddr */ 1108 BUS_SPACE_MAXADDR, /* highaddr */ 1109 NULL, NULL, /* filter, filterarg */ 1110 MCLBYTES * NGE_MAXTXSEGS, /* maxsize */ 1111 NGE_MAXTXSEGS, /* nsegments */ 1112 MCLBYTES, /* maxsegsize */ 1113 0, /* flags */ 1114 NULL, NULL, /* lockfunc, lockarg */ 1115 &sc->nge_cdata.nge_tx_tag); 1116 if (error != 0) { 1117 device_printf(sc->nge_dev, "failed to create Tx DMA tag\n"); 1118 goto fail; 1119 } 1120 1121 /* Create tag for Rx buffers. */ 1122 error = bus_dma_tag_create(sc->nge_cdata.nge_parent_tag,/* parent */ 1123 NGE_RX_ALIGN, 0, /* alignment, boundary */ 1124 BUS_SPACE_MAXADDR, /* lowaddr */ 1125 BUS_SPACE_MAXADDR, /* highaddr */ 1126 NULL, NULL, /* filter, filterarg */ 1127 MCLBYTES, /* maxsize */ 1128 1, /* nsegments */ 1129 MCLBYTES, /* maxsegsize */ 1130 0, /* flags */ 1131 NULL, NULL, /* lockfunc, lockarg */ 1132 &sc->nge_cdata.nge_rx_tag); 1133 if (error != 0) { 1134 device_printf(sc->nge_dev, "failed to create Rx DMA tag\n"); 1135 goto fail; 1136 } 1137 1138 /* Allocate DMA'able memory and load the DMA map for Tx ring. */ 1139 error = bus_dmamem_alloc(sc->nge_cdata.nge_tx_ring_tag, 1140 (void **)&sc->nge_rdata.nge_tx_ring, BUS_DMA_WAITOK | 1141 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->nge_cdata.nge_tx_ring_map); 1142 if (error != 0) { 1143 device_printf(sc->nge_dev, 1144 "failed to allocate DMA'able memory for Tx ring\n"); 1145 goto fail; 1146 } 1147 1148 ctx.nge_busaddr = 0; 1149 error = bus_dmamap_load(sc->nge_cdata.nge_tx_ring_tag, 1150 sc->nge_cdata.nge_tx_ring_map, sc->nge_rdata.nge_tx_ring, 1151 NGE_TX_RING_SIZE, nge_dmamap_cb, &ctx, 0); 1152 if (error != 0 || ctx.nge_busaddr == 0) { 1153 device_printf(sc->nge_dev, 1154 "failed to load DMA'able memory for Tx ring\n"); 1155 goto fail; 1156 } 1157 sc->nge_rdata.nge_tx_ring_paddr = ctx.nge_busaddr; 1158 1159 /* Allocate DMA'able memory and load the DMA map for Rx ring. */ 1160 error = bus_dmamem_alloc(sc->nge_cdata.nge_rx_ring_tag, 1161 (void **)&sc->nge_rdata.nge_rx_ring, BUS_DMA_WAITOK | 1162 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->nge_cdata.nge_rx_ring_map); 1163 if (error != 0) { 1164 device_printf(sc->nge_dev, 1165 "failed to allocate DMA'able memory for Rx ring\n"); 1166 goto fail; 1167 } 1168 1169 ctx.nge_busaddr = 0; 1170 error = bus_dmamap_load(sc->nge_cdata.nge_rx_ring_tag, 1171 sc->nge_cdata.nge_rx_ring_map, sc->nge_rdata.nge_rx_ring, 1172 NGE_RX_RING_SIZE, nge_dmamap_cb, &ctx, 0); 1173 if (error != 0 || ctx.nge_busaddr == 0) { 1174 device_printf(sc->nge_dev, 1175 "failed to load DMA'able memory for Rx ring\n"); 1176 goto fail; 1177 } 1178 sc->nge_rdata.nge_rx_ring_paddr = ctx.nge_busaddr; 1179 1180 /* Create DMA maps for Tx buffers. */ 1181 for (i = 0; i < NGE_TX_RING_CNT; i++) { 1182 txd = &sc->nge_cdata.nge_txdesc[i]; 1183 txd->tx_m = NULL; 1184 txd->tx_dmamap = NULL; 1185 error = bus_dmamap_create(sc->nge_cdata.nge_tx_tag, 0, 1186 &txd->tx_dmamap); 1187 if (error != 0) { 1188 device_printf(sc->nge_dev, 1189 "failed to create Tx dmamap\n"); 1190 goto fail; 1191 } 1192 } 1193 /* Create DMA maps for Rx buffers. */ 1194 if ((error = bus_dmamap_create(sc->nge_cdata.nge_rx_tag, 0, 1195 &sc->nge_cdata.nge_rx_sparemap)) != 0) { 1196 device_printf(sc->nge_dev, 1197 "failed to create spare Rx dmamap\n"); 1198 goto fail; 1199 } 1200 for (i = 0; i < NGE_RX_RING_CNT; i++) { 1201 rxd = &sc->nge_cdata.nge_rxdesc[i]; 1202 rxd->rx_m = NULL; 1203 rxd->rx_dmamap = NULL; 1204 error = bus_dmamap_create(sc->nge_cdata.nge_rx_tag, 0, 1205 &rxd->rx_dmamap); 1206 if (error != 0) { 1207 device_printf(sc->nge_dev, 1208 "failed to create Rx dmamap\n"); 1209 goto fail; 1210 } 1211 } 1212 1213 fail: 1214 return (error); 1215 } 1216 1217 static void 1218 nge_dma_free(struct nge_softc *sc) 1219 { 1220 struct nge_txdesc *txd; 1221 struct nge_rxdesc *rxd; 1222 int i; 1223 1224 /* Tx ring. */ 1225 if (sc->nge_cdata.nge_tx_ring_tag) { 1226 if (sc->nge_rdata.nge_tx_ring_paddr) 1227 bus_dmamap_unload(sc->nge_cdata.nge_tx_ring_tag, 1228 sc->nge_cdata.nge_tx_ring_map); 1229 if (sc->nge_rdata.nge_tx_ring) 1230 bus_dmamem_free(sc->nge_cdata.nge_tx_ring_tag, 1231 sc->nge_rdata.nge_tx_ring, 1232 sc->nge_cdata.nge_tx_ring_map); 1233 sc->nge_rdata.nge_tx_ring = NULL; 1234 sc->nge_rdata.nge_tx_ring_paddr = 0; 1235 bus_dma_tag_destroy(sc->nge_cdata.nge_tx_ring_tag); 1236 sc->nge_cdata.nge_tx_ring_tag = NULL; 1237 } 1238 /* Rx ring. */ 1239 if (sc->nge_cdata.nge_rx_ring_tag) { 1240 if (sc->nge_rdata.nge_rx_ring_paddr) 1241 bus_dmamap_unload(sc->nge_cdata.nge_rx_ring_tag, 1242 sc->nge_cdata.nge_rx_ring_map); 1243 if (sc->nge_rdata.nge_rx_ring) 1244 bus_dmamem_free(sc->nge_cdata.nge_rx_ring_tag, 1245 sc->nge_rdata.nge_rx_ring, 1246 sc->nge_cdata.nge_rx_ring_map); 1247 sc->nge_rdata.nge_rx_ring = NULL; 1248 sc->nge_rdata.nge_rx_ring_paddr = 0; 1249 bus_dma_tag_destroy(sc->nge_cdata.nge_rx_ring_tag); 1250 sc->nge_cdata.nge_rx_ring_tag = NULL; 1251 } 1252 /* Tx buffers. */ 1253 if (sc->nge_cdata.nge_tx_tag) { 1254 for (i = 0; i < NGE_TX_RING_CNT; i++) { 1255 txd = &sc->nge_cdata.nge_txdesc[i]; 1256 if (txd->tx_dmamap) { 1257 bus_dmamap_destroy(sc->nge_cdata.nge_tx_tag, 1258 txd->tx_dmamap); 1259 txd->tx_dmamap = NULL; 1260 } 1261 } 1262 bus_dma_tag_destroy(sc->nge_cdata.nge_tx_tag); 1263 sc->nge_cdata.nge_tx_tag = NULL; 1264 } 1265 /* Rx buffers. */ 1266 if (sc->nge_cdata.nge_rx_tag) { 1267 for (i = 0; i < NGE_RX_RING_CNT; i++) { 1268 rxd = &sc->nge_cdata.nge_rxdesc[i]; 1269 if (rxd->rx_dmamap) { 1270 bus_dmamap_destroy(sc->nge_cdata.nge_rx_tag, 1271 rxd->rx_dmamap); 1272 rxd->rx_dmamap = NULL; 1273 } 1274 } 1275 if (sc->nge_cdata.nge_rx_sparemap) { 1276 bus_dmamap_destroy(sc->nge_cdata.nge_rx_tag, 1277 sc->nge_cdata.nge_rx_sparemap); 1278 sc->nge_cdata.nge_rx_sparemap = 0; 1279 } 1280 bus_dma_tag_destroy(sc->nge_cdata.nge_rx_tag); 1281 sc->nge_cdata.nge_rx_tag = NULL; 1282 } 1283 1284 if (sc->nge_cdata.nge_parent_tag) { 1285 bus_dma_tag_destroy(sc->nge_cdata.nge_parent_tag); 1286 sc->nge_cdata.nge_parent_tag = NULL; 1287 } 1288 } 1289 1290 /* 1291 * Initialize the transmit descriptors. 1292 */ 1293 static int 1294 nge_list_tx_init(struct nge_softc *sc) 1295 { 1296 struct nge_ring_data *rd; 1297 struct nge_txdesc *txd; 1298 bus_addr_t addr; 1299 int i; 1300 1301 sc->nge_cdata.nge_tx_prod = 0; 1302 sc->nge_cdata.nge_tx_cons = 0; 1303 sc->nge_cdata.nge_tx_cnt = 0; 1304 1305 rd = &sc->nge_rdata; 1306 bzero(rd->nge_tx_ring, sizeof(struct nge_desc) * NGE_TX_RING_CNT); 1307 for (i = 0; i < NGE_TX_RING_CNT; i++) { 1308 if (i == NGE_TX_RING_CNT - 1) 1309 addr = NGE_TX_RING_ADDR(sc, 0); 1310 else 1311 addr = NGE_TX_RING_ADDR(sc, i + 1); 1312 rd->nge_tx_ring[i].nge_next = htole32(NGE_ADDR_LO(addr)); 1313 txd = &sc->nge_cdata.nge_txdesc[i]; 1314 txd->tx_m = NULL; 1315 } 1316 1317 bus_dmamap_sync(sc->nge_cdata.nge_tx_ring_tag, 1318 sc->nge_cdata.nge_tx_ring_map, 1319 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1320 1321 return (0); 1322 } 1323 1324 /* 1325 * Initialize the RX descriptors and allocate mbufs for them. Note that 1326 * we arrange the descriptors in a closed ring, so that the last descriptor 1327 * points back to the first. 1328 */ 1329 static int 1330 nge_list_rx_init(struct nge_softc *sc) 1331 { 1332 struct nge_ring_data *rd; 1333 bus_addr_t addr; 1334 int i; 1335 1336 sc->nge_cdata.nge_rx_cons = 0; 1337 sc->nge_head = sc->nge_tail = NULL; 1338 1339 rd = &sc->nge_rdata; 1340 bzero(rd->nge_rx_ring, sizeof(struct nge_desc) * NGE_RX_RING_CNT); 1341 for (i = 0; i < NGE_RX_RING_CNT; i++) { 1342 if (nge_newbuf(sc, i) != 0) 1343 return (ENOBUFS); 1344 if (i == NGE_RX_RING_CNT - 1) 1345 addr = NGE_RX_RING_ADDR(sc, 0); 1346 else 1347 addr = NGE_RX_RING_ADDR(sc, i + 1); 1348 rd->nge_rx_ring[i].nge_next = htole32(NGE_ADDR_LO(addr)); 1349 } 1350 1351 bus_dmamap_sync(sc->nge_cdata.nge_rx_ring_tag, 1352 sc->nge_cdata.nge_rx_ring_map, 1353 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1354 1355 return (0); 1356 } 1357 1358 static __inline void 1359 nge_discard_rxbuf(struct nge_softc *sc, int idx) 1360 { 1361 struct nge_desc *desc; 1362 1363 desc = &sc->nge_rdata.nge_rx_ring[idx]; 1364 desc->nge_cmdsts = htole32(MCLBYTES - sizeof(uint64_t)); 1365 desc->nge_extsts = 0; 1366 } 1367 1368 /* 1369 * Initialize an RX descriptor and attach an MBUF cluster. 1370 */ 1371 static int 1372 nge_newbuf(struct nge_softc *sc, int idx) 1373 { 1374 struct nge_desc *desc; 1375 struct nge_rxdesc *rxd; 1376 struct mbuf *m; 1377 bus_dma_segment_t segs[1]; 1378 bus_dmamap_t map; 1379 int nsegs; 1380 1381 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 1382 if (m == NULL) 1383 return (ENOBUFS); 1384 m->m_len = m->m_pkthdr.len = MCLBYTES; 1385 m_adj(m, sizeof(uint64_t)); 1386 1387 if (bus_dmamap_load_mbuf_sg(sc->nge_cdata.nge_rx_tag, 1388 sc->nge_cdata.nge_rx_sparemap, m, segs, &nsegs, 0) != 0) { 1389 m_freem(m); 1390 return (ENOBUFS); 1391 } 1392 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1393 1394 rxd = &sc->nge_cdata.nge_rxdesc[idx]; 1395 if (rxd->rx_m != NULL) { 1396 bus_dmamap_sync(sc->nge_cdata.nge_rx_tag, rxd->rx_dmamap, 1397 BUS_DMASYNC_POSTREAD); 1398 bus_dmamap_unload(sc->nge_cdata.nge_rx_tag, rxd->rx_dmamap); 1399 } 1400 map = rxd->rx_dmamap; 1401 rxd->rx_dmamap = sc->nge_cdata.nge_rx_sparemap; 1402 sc->nge_cdata.nge_rx_sparemap = map; 1403 bus_dmamap_sync(sc->nge_cdata.nge_rx_tag, rxd->rx_dmamap, 1404 BUS_DMASYNC_PREREAD); 1405 rxd->rx_m = m; 1406 desc = &sc->nge_rdata.nge_rx_ring[idx]; 1407 desc->nge_ptr = htole32(NGE_ADDR_LO(segs[0].ds_addr)); 1408 desc->nge_cmdsts = htole32(segs[0].ds_len); 1409 desc->nge_extsts = 0; 1410 1411 return (0); 1412 } 1413 1414 #ifndef __NO_STRICT_ALIGNMENT 1415 static __inline void 1416 nge_fixup_rx(struct mbuf *m) 1417 { 1418 int i; 1419 uint16_t *src, *dst; 1420 1421 src = mtod(m, uint16_t *); 1422 dst = src - 1; 1423 1424 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 1425 *dst++ = *src++; 1426 1427 m->m_data -= ETHER_ALIGN; 1428 } 1429 #endif 1430 1431 /* 1432 * A frame has been uploaded: pass the resulting mbuf chain up to 1433 * the higher level protocols. 1434 */ 1435 static int 1436 nge_rxeof(struct nge_softc *sc) 1437 { 1438 struct mbuf *m; 1439 if_t ifp; 1440 struct nge_desc *cur_rx; 1441 struct nge_rxdesc *rxd; 1442 int cons, prog, rx_npkts, total_len; 1443 uint32_t cmdsts, extsts; 1444 1445 NGE_LOCK_ASSERT(sc); 1446 1447 ifp = sc->nge_ifp; 1448 cons = sc->nge_cdata.nge_rx_cons; 1449 rx_npkts = 0; 1450 1451 bus_dmamap_sync(sc->nge_cdata.nge_rx_ring_tag, 1452 sc->nge_cdata.nge_rx_ring_map, 1453 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1454 1455 for (prog = 0; prog < NGE_RX_RING_CNT && 1456 (if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0; 1457 NGE_INC(cons, NGE_RX_RING_CNT)) { 1458 #ifdef DEVICE_POLLING 1459 if (if_getcapenable(ifp) & IFCAP_POLLING) { 1460 if (sc->rxcycles <= 0) 1461 break; 1462 sc->rxcycles--; 1463 } 1464 #endif 1465 cur_rx = &sc->nge_rdata.nge_rx_ring[cons]; 1466 cmdsts = le32toh(cur_rx->nge_cmdsts); 1467 extsts = le32toh(cur_rx->nge_extsts); 1468 if ((cmdsts & NGE_CMDSTS_OWN) == 0) 1469 break; 1470 prog++; 1471 rxd = &sc->nge_cdata.nge_rxdesc[cons]; 1472 m = rxd->rx_m; 1473 total_len = cmdsts & NGE_CMDSTS_BUFLEN; 1474 1475 if ((cmdsts & NGE_CMDSTS_MORE) != 0) { 1476 if (nge_newbuf(sc, cons) != 0) { 1477 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 1478 if (sc->nge_head != NULL) { 1479 m_freem(sc->nge_head); 1480 sc->nge_head = sc->nge_tail = NULL; 1481 } 1482 nge_discard_rxbuf(sc, cons); 1483 continue; 1484 } 1485 m->m_len = total_len; 1486 if (sc->nge_head == NULL) { 1487 m->m_pkthdr.len = total_len; 1488 sc->nge_head = sc->nge_tail = m; 1489 } else { 1490 m->m_flags &= ~M_PKTHDR; 1491 sc->nge_head->m_pkthdr.len += total_len; 1492 sc->nge_tail->m_next = m; 1493 sc->nge_tail = m; 1494 } 1495 continue; 1496 } 1497 1498 /* 1499 * If an error occurs, update stats, clear the 1500 * status word and leave the mbuf cluster in place: 1501 * it should simply get re-used next time this descriptor 1502 * comes up in the ring. 1503 */ 1504 if ((cmdsts & NGE_CMDSTS_PKT_OK) == 0) { 1505 if ((cmdsts & NGE_RXSTAT_RUNT) && 1506 total_len >= (ETHER_MIN_LEN - ETHER_CRC_LEN - 4)) { 1507 /* 1508 * Work-around hardware bug, accept runt frames 1509 * if its length is larger than or equal to 56. 1510 */ 1511 } else { 1512 /* 1513 * Input error counters are updated by hardware. 1514 */ 1515 if (sc->nge_head != NULL) { 1516 m_freem(sc->nge_head); 1517 sc->nge_head = sc->nge_tail = NULL; 1518 } 1519 nge_discard_rxbuf(sc, cons); 1520 continue; 1521 } 1522 } 1523 1524 /* Try conjure up a replacement mbuf. */ 1525 1526 if (nge_newbuf(sc, cons) != 0) { 1527 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 1528 if (sc->nge_head != NULL) { 1529 m_freem(sc->nge_head); 1530 sc->nge_head = sc->nge_tail = NULL; 1531 } 1532 nge_discard_rxbuf(sc, cons); 1533 continue; 1534 } 1535 1536 /* Chain received mbufs. */ 1537 if (sc->nge_head != NULL) { 1538 m->m_len = total_len; 1539 m->m_flags &= ~M_PKTHDR; 1540 sc->nge_tail->m_next = m; 1541 m = sc->nge_head; 1542 m->m_pkthdr.len += total_len; 1543 sc->nge_head = sc->nge_tail = NULL; 1544 } else 1545 m->m_pkthdr.len = m->m_len = total_len; 1546 1547 /* 1548 * Ok. NatSemi really screwed up here. This is the 1549 * only gigE chip I know of with alignment constraints 1550 * on receive buffers. RX buffers must be 64-bit aligned. 1551 */ 1552 /* 1553 * By popular demand, ignore the alignment problems 1554 * on the non-strict alignment platform. The performance hit 1555 * incurred due to unaligned accesses is much smaller 1556 * than the hit produced by forcing buffer copies all 1557 * the time, especially with jumbo frames. We still 1558 * need to fix up the alignment everywhere else though. 1559 */ 1560 #ifndef __NO_STRICT_ALIGNMENT 1561 nge_fixup_rx(m); 1562 #endif 1563 m->m_pkthdr.rcvif = ifp; 1564 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 1565 1566 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0) { 1567 /* Do IP checksum checking. */ 1568 if ((extsts & NGE_RXEXTSTS_IPPKT) != 0) 1569 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1570 if ((extsts & NGE_RXEXTSTS_IPCSUMERR) == 0) 1571 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1572 if ((extsts & NGE_RXEXTSTS_TCPPKT && 1573 !(extsts & NGE_RXEXTSTS_TCPCSUMERR)) || 1574 (extsts & NGE_RXEXTSTS_UDPPKT && 1575 !(extsts & NGE_RXEXTSTS_UDPCSUMERR))) { 1576 m->m_pkthdr.csum_flags |= 1577 CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 1578 m->m_pkthdr.csum_data = 0xffff; 1579 } 1580 } 1581 1582 /* 1583 * If we received a packet with a vlan tag, pass it 1584 * to vlan_input() instead of ether_input(). 1585 */ 1586 if ((extsts & NGE_RXEXTSTS_VLANPKT) != 0 && 1587 (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0) { 1588 m->m_pkthdr.ether_vtag = 1589 bswap16(extsts & NGE_RXEXTSTS_VTCI); 1590 m->m_flags |= M_VLANTAG; 1591 } 1592 NGE_UNLOCK(sc); 1593 if_input(ifp, m); 1594 NGE_LOCK(sc); 1595 rx_npkts++; 1596 } 1597 1598 if (prog > 0) { 1599 sc->nge_cdata.nge_rx_cons = cons; 1600 bus_dmamap_sync(sc->nge_cdata.nge_rx_ring_tag, 1601 sc->nge_cdata.nge_rx_ring_map, 1602 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1603 } 1604 return (rx_npkts); 1605 } 1606 1607 /* 1608 * A frame was downloaded to the chip. It's safe for us to clean up 1609 * the list buffers. 1610 */ 1611 static void 1612 nge_txeof(struct nge_softc *sc) 1613 { 1614 struct nge_desc *cur_tx; 1615 struct nge_txdesc *txd; 1616 if_t ifp; 1617 uint32_t cmdsts; 1618 int cons, prod; 1619 1620 NGE_LOCK_ASSERT(sc); 1621 ifp = sc->nge_ifp; 1622 1623 cons = sc->nge_cdata.nge_tx_cons; 1624 prod = sc->nge_cdata.nge_tx_prod; 1625 if (cons == prod) 1626 return; 1627 1628 bus_dmamap_sync(sc->nge_cdata.nge_tx_ring_tag, 1629 sc->nge_cdata.nge_tx_ring_map, 1630 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1631 1632 /* 1633 * Go through our tx list and free mbufs for those 1634 * frames that have been transmitted. 1635 */ 1636 for (; cons != prod; NGE_INC(cons, NGE_TX_RING_CNT)) { 1637 cur_tx = &sc->nge_rdata.nge_tx_ring[cons]; 1638 cmdsts = le32toh(cur_tx->nge_cmdsts); 1639 if ((cmdsts & NGE_CMDSTS_OWN) != 0) 1640 break; 1641 sc->nge_cdata.nge_tx_cnt--; 1642 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 1643 if ((cmdsts & NGE_CMDSTS_MORE) != 0) 1644 continue; 1645 1646 txd = &sc->nge_cdata.nge_txdesc[cons]; 1647 bus_dmamap_sync(sc->nge_cdata.nge_tx_tag, txd->tx_dmamap, 1648 BUS_DMASYNC_POSTWRITE); 1649 bus_dmamap_unload(sc->nge_cdata.nge_tx_tag, txd->tx_dmamap); 1650 if ((cmdsts & NGE_CMDSTS_PKT_OK) == 0) { 1651 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 1652 if ((cmdsts & NGE_TXSTAT_EXCESSCOLLS) != 0) 1653 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 1); 1654 if ((cmdsts & NGE_TXSTAT_OUTOFWINCOLL) != 0) 1655 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 1); 1656 } else 1657 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 1658 1659 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, (cmdsts & NGE_TXSTAT_COLLCNT) >> 16); 1660 KASSERT(txd->tx_m != NULL, ("%s: freeing NULL mbuf!\n", 1661 __func__)); 1662 m_freem(txd->tx_m); 1663 txd->tx_m = NULL; 1664 } 1665 1666 sc->nge_cdata.nge_tx_cons = cons; 1667 if (sc->nge_cdata.nge_tx_cnt == 0) 1668 sc->nge_watchdog_timer = 0; 1669 } 1670 1671 static void 1672 nge_tick(void *xsc) 1673 { 1674 struct nge_softc *sc; 1675 struct mii_data *mii; 1676 1677 sc = xsc; 1678 NGE_LOCK_ASSERT(sc); 1679 mii = device_get_softc(sc->nge_miibus); 1680 mii_tick(mii); 1681 /* 1682 * For PHYs that does not reset established link, it is 1683 * necessary to check whether driver still have a valid 1684 * link(e.g link state change callback is not called). 1685 * Otherwise, driver think it lost link because driver 1686 * initialization routine clears link state flag. 1687 */ 1688 if ((sc->nge_flags & NGE_FLAG_LINK) == 0) 1689 nge_miibus_statchg(sc->nge_dev); 1690 nge_stats_update(sc); 1691 nge_watchdog(sc); 1692 callout_reset(&sc->nge_stat_ch, hz, nge_tick, sc); 1693 } 1694 1695 static void 1696 nge_stats_update(struct nge_softc *sc) 1697 { 1698 if_t ifp; 1699 struct nge_stats now, *stats, *nstats; 1700 1701 NGE_LOCK_ASSERT(sc); 1702 1703 ifp = sc->nge_ifp; 1704 stats = &now; 1705 stats->rx_pkts_errs = 1706 CSR_READ_4(sc, NGE_MIB_RXERRPKT) & 0xFFFF; 1707 stats->rx_crc_errs = 1708 CSR_READ_4(sc, NGE_MIB_RXERRFCS) & 0xFFFF; 1709 stats->rx_fifo_oflows = 1710 CSR_READ_4(sc, NGE_MIB_RXERRMISSEDPKT) & 0xFFFF; 1711 stats->rx_align_errs = 1712 CSR_READ_4(sc, NGE_MIB_RXERRALIGN) & 0xFFFF; 1713 stats->rx_sym_errs = 1714 CSR_READ_4(sc, NGE_MIB_RXERRSYM) & 0xFFFF; 1715 stats->rx_pkts_jumbos = 1716 CSR_READ_4(sc, NGE_MIB_RXERRGIANT) & 0xFFFF; 1717 stats->rx_len_errs = 1718 CSR_READ_4(sc, NGE_MIB_RXERRRANGLEN) & 0xFFFF; 1719 stats->rx_unctl_frames = 1720 CSR_READ_4(sc, NGE_MIB_RXBADOPCODE) & 0xFFFF; 1721 stats->rx_pause = 1722 CSR_READ_4(sc, NGE_MIB_RXPAUSEPKTS) & 0xFFFF; 1723 stats->tx_pause = 1724 CSR_READ_4(sc, NGE_MIB_TXPAUSEPKTS) & 0xFFFF; 1725 stats->tx_seq_errs = 1726 CSR_READ_4(sc, NGE_MIB_TXERRSQE) & 0xFF; 1727 1728 /* 1729 * Since we've accept errored frames exclude Rx length errors. 1730 */ 1731 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1732 stats->rx_pkts_errs + stats->rx_crc_errs + 1733 stats->rx_fifo_oflows + stats->rx_sym_errs); 1734 1735 nstats = &sc->nge_stats; 1736 nstats->rx_pkts_errs += stats->rx_pkts_errs; 1737 nstats->rx_crc_errs += stats->rx_crc_errs; 1738 nstats->rx_fifo_oflows += stats->rx_fifo_oflows; 1739 nstats->rx_align_errs += stats->rx_align_errs; 1740 nstats->rx_sym_errs += stats->rx_sym_errs; 1741 nstats->rx_pkts_jumbos += stats->rx_pkts_jumbos; 1742 nstats->rx_len_errs += stats->rx_len_errs; 1743 nstats->rx_unctl_frames += stats->rx_unctl_frames; 1744 nstats->rx_pause += stats->rx_pause; 1745 nstats->tx_pause += stats->tx_pause; 1746 nstats->tx_seq_errs += stats->tx_seq_errs; 1747 } 1748 1749 #ifdef DEVICE_POLLING 1750 static poll_handler_t nge_poll; 1751 1752 static int 1753 nge_poll(if_t ifp, enum poll_cmd cmd, int count) 1754 { 1755 struct nge_softc *sc; 1756 int rx_npkts = 0; 1757 1758 sc = if_getsoftc(ifp); 1759 1760 NGE_LOCK(sc); 1761 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) { 1762 NGE_UNLOCK(sc); 1763 return (rx_npkts); 1764 } 1765 1766 /* 1767 * On the nge, reading the status register also clears it. 1768 * So before returning to intr mode we must make sure that all 1769 * possible pending sources of interrupts have been served. 1770 * In practice this means run to completion the *eof routines, 1771 * and then call the interrupt routine. 1772 */ 1773 sc->rxcycles = count; 1774 rx_npkts = nge_rxeof(sc); 1775 nge_txeof(sc); 1776 if (!if_sendq_empty(ifp)) 1777 nge_start_locked(ifp); 1778 1779 if (sc->rxcycles > 0 || cmd == POLL_AND_CHECK_STATUS) { 1780 uint32_t status; 1781 1782 /* Reading the ISR register clears all interrupts. */ 1783 status = CSR_READ_4(sc, NGE_ISR); 1784 1785 if ((status & (NGE_ISR_RX_ERR|NGE_ISR_RX_OFLOW)) != 0) 1786 rx_npkts += nge_rxeof(sc); 1787 1788 if ((status & NGE_ISR_RX_IDLE) != 0) 1789 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE); 1790 1791 if ((status & NGE_ISR_SYSERR) != 0) { 1792 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 1793 nge_init_locked(sc); 1794 } 1795 } 1796 NGE_UNLOCK(sc); 1797 return (rx_npkts); 1798 } 1799 #endif /* DEVICE_POLLING */ 1800 1801 static void 1802 nge_intr(void *arg) 1803 { 1804 struct nge_softc *sc; 1805 if_t ifp; 1806 uint32_t status; 1807 1808 sc = (struct nge_softc *)arg; 1809 ifp = sc->nge_ifp; 1810 1811 NGE_LOCK(sc); 1812 1813 if ((sc->nge_flags & NGE_FLAG_SUSPENDED) != 0) 1814 goto done_locked; 1815 1816 /* Reading the ISR register clears all interrupts. */ 1817 status = CSR_READ_4(sc, NGE_ISR); 1818 if (status == 0xffffffff || (status & NGE_INTRS) == 0) 1819 goto done_locked; 1820 #ifdef DEVICE_POLLING 1821 if ((if_getcapenable(ifp) & IFCAP_POLLING) != 0) 1822 goto done_locked; 1823 #endif 1824 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) 1825 goto done_locked; 1826 1827 /* Disable interrupts. */ 1828 CSR_WRITE_4(sc, NGE_IER, 0); 1829 1830 /* Data LED on for TBI mode */ 1831 if ((sc->nge_flags & NGE_FLAG_TBI) != 0) 1832 CSR_WRITE_4(sc, NGE_GPIO, 1833 CSR_READ_4(sc, NGE_GPIO) | NGE_GPIO_GP3_OUT); 1834 1835 for (; (status & NGE_INTRS) != 0;) { 1836 if ((status & (NGE_ISR_TX_DESC_OK | NGE_ISR_TX_ERR | 1837 NGE_ISR_TX_OK | NGE_ISR_TX_IDLE)) != 0) 1838 nge_txeof(sc); 1839 1840 if ((status & (NGE_ISR_RX_DESC_OK | NGE_ISR_RX_ERR | 1841 NGE_ISR_RX_OFLOW | NGE_ISR_RX_FIFO_OFLOW | 1842 NGE_ISR_RX_IDLE | NGE_ISR_RX_OK)) != 0) 1843 nge_rxeof(sc); 1844 1845 if ((status & NGE_ISR_RX_IDLE) != 0) 1846 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE); 1847 1848 if ((status & NGE_ISR_SYSERR) != 0) { 1849 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 1850 nge_init_locked(sc); 1851 } 1852 /* Reading the ISR register clears all interrupts. */ 1853 status = CSR_READ_4(sc, NGE_ISR); 1854 } 1855 1856 /* Re-enable interrupts. */ 1857 CSR_WRITE_4(sc, NGE_IER, 1); 1858 1859 if (!if_sendq_empty(ifp)) 1860 nge_start_locked(ifp); 1861 1862 /* Data LED off for TBI mode */ 1863 if ((sc->nge_flags & NGE_FLAG_TBI) != 0) 1864 CSR_WRITE_4(sc, NGE_GPIO, 1865 CSR_READ_4(sc, NGE_GPIO) & ~NGE_GPIO_GP3_OUT); 1866 1867 done_locked: 1868 NGE_UNLOCK(sc); 1869 } 1870 1871 /* 1872 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1873 * pointers to the fragment pointers. 1874 */ 1875 static int 1876 nge_encap(struct nge_softc *sc, struct mbuf **m_head) 1877 { 1878 struct nge_txdesc *txd, *txd_last; 1879 struct nge_desc *desc; 1880 struct mbuf *m; 1881 bus_dmamap_t map; 1882 bus_dma_segment_t txsegs[NGE_MAXTXSEGS]; 1883 int error, i, nsegs, prod, si; 1884 1885 NGE_LOCK_ASSERT(sc); 1886 1887 m = *m_head; 1888 prod = sc->nge_cdata.nge_tx_prod; 1889 txd = &sc->nge_cdata.nge_txdesc[prod]; 1890 txd_last = txd; 1891 map = txd->tx_dmamap; 1892 error = bus_dmamap_load_mbuf_sg(sc->nge_cdata.nge_tx_tag, map, 1893 *m_head, txsegs, &nsegs, BUS_DMA_NOWAIT); 1894 if (error == EFBIG) { 1895 m = m_collapse(*m_head, M_NOWAIT, NGE_MAXTXSEGS); 1896 if (m == NULL) { 1897 m_freem(*m_head); 1898 *m_head = NULL; 1899 return (ENOBUFS); 1900 } 1901 *m_head = m; 1902 error = bus_dmamap_load_mbuf_sg(sc->nge_cdata.nge_tx_tag, 1903 map, *m_head, txsegs, &nsegs, BUS_DMA_NOWAIT); 1904 if (error != 0) { 1905 m_freem(*m_head); 1906 *m_head = NULL; 1907 return (error); 1908 } 1909 } else if (error != 0) 1910 return (error); 1911 if (nsegs == 0) { 1912 m_freem(*m_head); 1913 *m_head = NULL; 1914 return (EIO); 1915 } 1916 1917 /* Check number of available descriptors. */ 1918 if (sc->nge_cdata.nge_tx_cnt + nsegs >= (NGE_TX_RING_CNT - 1)) { 1919 bus_dmamap_unload(sc->nge_cdata.nge_tx_tag, map); 1920 return (ENOBUFS); 1921 } 1922 1923 bus_dmamap_sync(sc->nge_cdata.nge_tx_tag, map, BUS_DMASYNC_PREWRITE); 1924 1925 si = prod; 1926 for (i = 0; i < nsegs; i++) { 1927 desc = &sc->nge_rdata.nge_tx_ring[prod]; 1928 desc->nge_ptr = htole32(NGE_ADDR_LO(txsegs[i].ds_addr)); 1929 if (i == 0) 1930 desc->nge_cmdsts = htole32(txsegs[i].ds_len | 1931 NGE_CMDSTS_MORE); 1932 else 1933 desc->nge_cmdsts = htole32(txsegs[i].ds_len | 1934 NGE_CMDSTS_MORE | NGE_CMDSTS_OWN); 1935 desc->nge_extsts = 0; 1936 sc->nge_cdata.nge_tx_cnt++; 1937 NGE_INC(prod, NGE_TX_RING_CNT); 1938 } 1939 /* Update producer index. */ 1940 sc->nge_cdata.nge_tx_prod = prod; 1941 1942 prod = (prod + NGE_TX_RING_CNT - 1) % NGE_TX_RING_CNT; 1943 desc = &sc->nge_rdata.nge_tx_ring[prod]; 1944 /* Check if we have a VLAN tag to insert. */ 1945 if ((m->m_flags & M_VLANTAG) != 0) 1946 desc->nge_extsts |= htole32(NGE_TXEXTSTS_VLANPKT | 1947 bswap16(m->m_pkthdr.ether_vtag)); 1948 /* Set EOP on the last descriptor. */ 1949 desc->nge_cmdsts &= htole32(~NGE_CMDSTS_MORE); 1950 1951 /* Set checksum offload in the first descriptor. */ 1952 desc = &sc->nge_rdata.nge_tx_ring[si]; 1953 if ((m->m_pkthdr.csum_flags & NGE_CSUM_FEATURES) != 0) { 1954 if ((m->m_pkthdr.csum_flags & CSUM_IP) != 0) 1955 desc->nge_extsts |= htole32(NGE_TXEXTSTS_IPCSUM); 1956 if ((m->m_pkthdr.csum_flags & CSUM_TCP) != 0) 1957 desc->nge_extsts |= htole32(NGE_TXEXTSTS_TCPCSUM); 1958 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0) 1959 desc->nge_extsts |= htole32(NGE_TXEXTSTS_UDPCSUM); 1960 } 1961 /* Lastly, turn the first descriptor ownership to hardware. */ 1962 desc->nge_cmdsts |= htole32(NGE_CMDSTS_OWN); 1963 1964 txd = &sc->nge_cdata.nge_txdesc[prod]; 1965 map = txd_last->tx_dmamap; 1966 txd_last->tx_dmamap = txd->tx_dmamap; 1967 txd->tx_dmamap = map; 1968 txd->tx_m = m; 1969 1970 return (0); 1971 } 1972 1973 /* 1974 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1975 * to the mbuf data regions directly in the transmit lists. We also save a 1976 * copy of the pointers since the transmit list fragment pointers are 1977 * physical addresses. 1978 */ 1979 1980 static void 1981 nge_start(if_t ifp) 1982 { 1983 struct nge_softc *sc; 1984 1985 sc = if_getsoftc(ifp); 1986 NGE_LOCK(sc); 1987 nge_start_locked(ifp); 1988 NGE_UNLOCK(sc); 1989 } 1990 1991 static void 1992 nge_start_locked(if_t ifp) 1993 { 1994 struct nge_softc *sc; 1995 struct mbuf *m_head; 1996 int enq; 1997 1998 sc = if_getsoftc(ifp); 1999 2000 NGE_LOCK_ASSERT(sc); 2001 2002 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2003 IFF_DRV_RUNNING || (sc->nge_flags & NGE_FLAG_LINK) == 0) 2004 return; 2005 2006 for (enq = 0; !if_sendq_empty(ifp) && 2007 sc->nge_cdata.nge_tx_cnt < NGE_TX_RING_CNT - 2; ) { 2008 m_head = if_dequeue(ifp); 2009 if (m_head == NULL) 2010 break; 2011 /* 2012 * Pack the data into the transmit ring. If we 2013 * don't have room, set the OACTIVE flag and wait 2014 * for the NIC to drain the ring. 2015 */ 2016 if (nge_encap(sc, &m_head)) { 2017 if (m_head == NULL) 2018 break; 2019 if_sendq_prepend(ifp, m_head); 2020 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); 2021 break; 2022 } 2023 2024 enq++; 2025 /* 2026 * If there's a BPF listener, bounce a copy of this frame 2027 * to him. 2028 */ 2029 ETHER_BPF_MTAP(ifp, m_head); 2030 } 2031 2032 if (enq > 0) { 2033 bus_dmamap_sync(sc->nge_cdata.nge_tx_ring_tag, 2034 sc->nge_cdata.nge_tx_ring_map, 2035 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2036 /* Transmit */ 2037 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_TX_ENABLE); 2038 2039 /* Set a timeout in case the chip goes out to lunch. */ 2040 sc->nge_watchdog_timer = 5; 2041 } 2042 } 2043 2044 static void 2045 nge_init(void *xsc) 2046 { 2047 struct nge_softc *sc = xsc; 2048 2049 NGE_LOCK(sc); 2050 nge_init_locked(sc); 2051 NGE_UNLOCK(sc); 2052 } 2053 2054 static void 2055 nge_init_locked(struct nge_softc *sc) 2056 { 2057 if_t ifp = sc->nge_ifp; 2058 struct mii_data *mii; 2059 uint8_t *eaddr; 2060 uint32_t reg; 2061 2062 NGE_LOCK_ASSERT(sc); 2063 2064 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 2065 return; 2066 2067 /* 2068 * Cancel pending I/O and free all RX/TX buffers. 2069 */ 2070 nge_stop(sc); 2071 2072 /* Reset the adapter. */ 2073 nge_reset(sc); 2074 2075 /* Disable Rx filter prior to programming Rx filter. */ 2076 CSR_WRITE_4(sc, NGE_RXFILT_CTL, 0); 2077 CSR_BARRIER_4(sc, NGE_RXFILT_CTL, BUS_SPACE_BARRIER_WRITE); 2078 2079 mii = device_get_softc(sc->nge_miibus); 2080 2081 /* Set MAC address. */ 2082 eaddr = if_getlladdr(sc->nge_ifp); 2083 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR0); 2084 CSR_WRITE_4(sc, NGE_RXFILT_DATA, (eaddr[1] << 8) | eaddr[0]); 2085 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR1); 2086 CSR_WRITE_4(sc, NGE_RXFILT_DATA, (eaddr[3] << 8) | eaddr[2]); 2087 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR2); 2088 CSR_WRITE_4(sc, NGE_RXFILT_DATA, (eaddr[5] << 8) | eaddr[4]); 2089 2090 /* Init circular RX list. */ 2091 if (nge_list_rx_init(sc) == ENOBUFS) { 2092 device_printf(sc->nge_dev, "initialization failed: no " 2093 "memory for rx buffers\n"); 2094 nge_stop(sc); 2095 return; 2096 } 2097 2098 /* 2099 * Init tx descriptors. 2100 */ 2101 nge_list_tx_init(sc); 2102 2103 /* Set Rx filter. */ 2104 nge_rxfilter(sc); 2105 2106 /* Disable PRIQ ctl. */ 2107 CSR_WRITE_4(sc, NGE_PRIOQCTL, 0); 2108 2109 /* 2110 * Set pause frames parameters. 2111 * Rx stat FIFO hi-threshold : 2 or more packets 2112 * Rx stat FIFO lo-threshold : less than 2 packets 2113 * Rx data FIFO hi-threshold : 2K or more bytes 2114 * Rx data FIFO lo-threshold : less than 2K bytes 2115 * pause time : (512ns * 0xffff) -> 33.55ms 2116 */ 2117 CSR_WRITE_4(sc, NGE_PAUSECSR, 2118 NGE_PAUSECSR_PAUSE_ON_MCAST | 2119 NGE_PAUSECSR_PAUSE_ON_DA | 2120 ((1 << 24) & NGE_PAUSECSR_RX_STATFIFO_THR_HI) | 2121 ((1 << 22) & NGE_PAUSECSR_RX_STATFIFO_THR_LO) | 2122 ((1 << 20) & NGE_PAUSECSR_RX_DATAFIFO_THR_HI) | 2123 ((1 << 18) & NGE_PAUSECSR_RX_DATAFIFO_THR_LO) | 2124 NGE_PAUSECSR_CNT); 2125 2126 /* 2127 * Load the address of the RX and TX lists. 2128 */ 2129 CSR_WRITE_4(sc, NGE_RX_LISTPTR_HI, 2130 NGE_ADDR_HI(sc->nge_rdata.nge_rx_ring_paddr)); 2131 CSR_WRITE_4(sc, NGE_RX_LISTPTR_LO, 2132 NGE_ADDR_LO(sc->nge_rdata.nge_rx_ring_paddr)); 2133 CSR_WRITE_4(sc, NGE_TX_LISTPTR_HI, 2134 NGE_ADDR_HI(sc->nge_rdata.nge_tx_ring_paddr)); 2135 CSR_WRITE_4(sc, NGE_TX_LISTPTR_LO, 2136 NGE_ADDR_LO(sc->nge_rdata.nge_tx_ring_paddr)); 2137 2138 /* Set RX configuration. */ 2139 CSR_WRITE_4(sc, NGE_RX_CFG, NGE_RXCFG); 2140 2141 CSR_WRITE_4(sc, NGE_VLAN_IP_RXCTL, 0); 2142 /* 2143 * Enable hardware checksum validation for all IPv4 2144 * packets, do not reject packets with bad checksums. 2145 */ 2146 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0) 2147 NGE_SETBIT(sc, NGE_VLAN_IP_RXCTL, NGE_VIPRXCTL_IPCSUM_ENB); 2148 2149 /* 2150 * Tell the chip to detect and strip VLAN tag info from 2151 * received frames. The tag will be provided in the extsts 2152 * field in the RX descriptors. 2153 */ 2154 NGE_SETBIT(sc, NGE_VLAN_IP_RXCTL, NGE_VIPRXCTL_TAG_DETECT_ENB); 2155 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0) 2156 NGE_SETBIT(sc, NGE_VLAN_IP_RXCTL, NGE_VIPRXCTL_TAG_STRIP_ENB); 2157 2158 /* Set TX configuration. */ 2159 CSR_WRITE_4(sc, NGE_TX_CFG, NGE_TXCFG); 2160 2161 /* 2162 * Enable TX IPv4 checksumming on a per-packet basis. 2163 */ 2164 CSR_WRITE_4(sc, NGE_VLAN_IP_TXCTL, NGE_VIPTXCTL_CSUM_PER_PKT); 2165 2166 /* 2167 * Tell the chip to insert VLAN tags on a per-packet basis as 2168 * dictated by the code in the frame encapsulation routine. 2169 */ 2170 NGE_SETBIT(sc, NGE_VLAN_IP_TXCTL, NGE_VIPTXCTL_TAG_PER_PKT); 2171 2172 /* 2173 * Enable the delivery of PHY interrupts based on 2174 * link/speed/duplex status changes. Also enable the 2175 * extsts field in the DMA descriptors (needed for 2176 * TCP/IP checksum offload on transmit). 2177 */ 2178 NGE_SETBIT(sc, NGE_CFG, NGE_CFG_PHYINTR_SPD | 2179 NGE_CFG_PHYINTR_LNK | NGE_CFG_PHYINTR_DUP | NGE_CFG_EXTSTS_ENB); 2180 2181 /* 2182 * Configure interrupt holdoff (moderation). We can 2183 * have the chip delay interrupt delivery for a certain 2184 * period. Units are in 100us, and the max setting 2185 * is 25500us (0xFF x 100us). Default is a 100us holdoff. 2186 */ 2187 CSR_WRITE_4(sc, NGE_IHR, sc->nge_int_holdoff); 2188 2189 /* 2190 * Enable MAC statistics counters and clear. 2191 */ 2192 reg = CSR_READ_4(sc, NGE_MIBCTL); 2193 reg &= ~NGE_MIBCTL_FREEZE_CNT; 2194 reg |= NGE_MIBCTL_CLEAR_CNT; 2195 CSR_WRITE_4(sc, NGE_MIBCTL, reg); 2196 2197 /* 2198 * Enable interrupts. 2199 */ 2200 CSR_WRITE_4(sc, NGE_IMR, NGE_INTRS); 2201 #ifdef DEVICE_POLLING 2202 /* 2203 * ... only enable interrupts if we are not polling, make sure 2204 * they are off otherwise. 2205 */ 2206 if ((if_getcapenable(ifp) & IFCAP_POLLING) != 0) 2207 CSR_WRITE_4(sc, NGE_IER, 0); 2208 else 2209 #endif 2210 CSR_WRITE_4(sc, NGE_IER, 1); 2211 2212 sc->nge_flags &= ~NGE_FLAG_LINK; 2213 mii_mediachg(mii); 2214 2215 sc->nge_watchdog_timer = 0; 2216 callout_reset(&sc->nge_stat_ch, hz, nge_tick, sc); 2217 2218 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0); 2219 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 2220 } 2221 2222 /* 2223 * Set media options. 2224 */ 2225 static int 2226 nge_mediachange(if_t ifp) 2227 { 2228 struct nge_softc *sc; 2229 struct mii_data *mii; 2230 struct mii_softc *miisc; 2231 int error; 2232 2233 sc = if_getsoftc(ifp); 2234 NGE_LOCK(sc); 2235 mii = device_get_softc(sc->nge_miibus); 2236 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 2237 PHY_RESET(miisc); 2238 error = mii_mediachg(mii); 2239 NGE_UNLOCK(sc); 2240 2241 return (error); 2242 } 2243 2244 /* 2245 * Report current media status. 2246 */ 2247 static void 2248 nge_mediastatus(if_t ifp, struct ifmediareq *ifmr) 2249 { 2250 struct nge_softc *sc; 2251 struct mii_data *mii; 2252 2253 sc = if_getsoftc(ifp); 2254 NGE_LOCK(sc); 2255 mii = device_get_softc(sc->nge_miibus); 2256 mii_pollstat(mii); 2257 ifmr->ifm_active = mii->mii_media_active; 2258 ifmr->ifm_status = mii->mii_media_status; 2259 NGE_UNLOCK(sc); 2260 } 2261 2262 static int 2263 nge_ioctl(if_t ifp, u_long command, caddr_t data) 2264 { 2265 struct nge_softc *sc = if_getsoftc(ifp); 2266 struct ifreq *ifr = (struct ifreq *) data; 2267 struct mii_data *mii; 2268 int error = 0, mask; 2269 2270 switch (command) { 2271 case SIOCSIFMTU: 2272 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > NGE_JUMBO_MTU) 2273 error = EINVAL; 2274 else { 2275 NGE_LOCK(sc); 2276 if_setmtu(ifp, ifr->ifr_mtu); 2277 /* 2278 * Workaround: if the MTU is larger than 2279 * 8152 (TX FIFO size minus 64 minus 18), turn off 2280 * TX checksum offloading. 2281 */ 2282 if (ifr->ifr_mtu >= 8152) { 2283 if_setcapenablebit(ifp, 0, IFCAP_TXCSUM); 2284 if_sethwassistbits(ifp, 0, NGE_CSUM_FEATURES); 2285 } else { 2286 if_setcapenablebit(ifp, IFCAP_TXCSUM, 0); 2287 if_sethwassistbits(ifp, NGE_CSUM_FEATURES, 0); 2288 } 2289 NGE_UNLOCK(sc); 2290 VLAN_CAPABILITIES(ifp); 2291 } 2292 break; 2293 case SIOCSIFFLAGS: 2294 NGE_LOCK(sc); 2295 if ((if_getflags(ifp) & IFF_UP) != 0) { 2296 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 2297 if ((if_getflags(ifp) ^ sc->nge_if_flags) & 2298 (IFF_PROMISC | IFF_ALLMULTI)) 2299 nge_rxfilter(sc); 2300 } else { 2301 if ((sc->nge_flags & NGE_FLAG_DETACH) == 0) 2302 nge_init_locked(sc); 2303 } 2304 } else { 2305 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 2306 nge_stop(sc); 2307 } 2308 sc->nge_if_flags = if_getflags(ifp); 2309 NGE_UNLOCK(sc); 2310 error = 0; 2311 break; 2312 case SIOCADDMULTI: 2313 case SIOCDELMULTI: 2314 NGE_LOCK(sc); 2315 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 2316 nge_rxfilter(sc); 2317 NGE_UNLOCK(sc); 2318 break; 2319 case SIOCGIFMEDIA: 2320 case SIOCSIFMEDIA: 2321 mii = device_get_softc(sc->nge_miibus); 2322 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2323 break; 2324 case SIOCSIFCAP: 2325 NGE_LOCK(sc); 2326 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp); 2327 #ifdef DEVICE_POLLING 2328 if ((mask & IFCAP_POLLING) != 0 && 2329 (IFCAP_POLLING & if_getcapabilities(ifp)) != 0) { 2330 if_togglecapenable(ifp, IFCAP_POLLING); 2331 if ((IFCAP_POLLING & if_getcapenable(ifp)) != 0) { 2332 error = ether_poll_register(nge_poll, ifp); 2333 if (error != 0) { 2334 NGE_UNLOCK(sc); 2335 break; 2336 } 2337 /* Disable interrupts. */ 2338 CSR_WRITE_4(sc, NGE_IER, 0); 2339 } else { 2340 error = ether_poll_deregister(ifp); 2341 /* Enable interrupts. */ 2342 CSR_WRITE_4(sc, NGE_IER, 1); 2343 } 2344 } 2345 #endif /* DEVICE_POLLING */ 2346 if ((mask & IFCAP_TXCSUM) != 0 && 2347 (IFCAP_TXCSUM & if_getcapabilities(ifp)) != 0) { 2348 if_togglecapenable(ifp, IFCAP_TXCSUM); 2349 if ((IFCAP_TXCSUM & if_getcapenable(ifp)) != 0) 2350 if_sethwassistbits(ifp, NGE_CSUM_FEATURES, 0); 2351 else 2352 if_sethwassistbits(ifp, 0, NGE_CSUM_FEATURES); 2353 } 2354 if ((mask & IFCAP_RXCSUM) != 0 && 2355 (IFCAP_RXCSUM & if_getcapabilities(ifp)) != 0) 2356 if_togglecapenable(ifp, IFCAP_RXCSUM); 2357 2358 if ((mask & IFCAP_WOL) != 0 && 2359 (if_getcapabilities(ifp) & IFCAP_WOL) != 0) { 2360 if ((mask & IFCAP_WOL_UCAST) != 0) 2361 if_togglecapenable(ifp, IFCAP_WOL_UCAST); 2362 if ((mask & IFCAP_WOL_MCAST) != 0) 2363 if_togglecapenable(ifp, IFCAP_WOL_MCAST); 2364 if ((mask & IFCAP_WOL_MAGIC) != 0) 2365 if_togglecapenable(ifp, IFCAP_WOL_MAGIC); 2366 } 2367 2368 if ((mask & IFCAP_VLAN_HWCSUM) != 0 && 2369 (if_getcapabilities(ifp) & IFCAP_VLAN_HWCSUM) != 0) 2370 if_togglecapenable(ifp, IFCAP_VLAN_HWCSUM); 2371 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 2372 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTAGGING) != 0) { 2373 if_togglecapenable(ifp, IFCAP_VLAN_HWTAGGING); 2374 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 2375 if ((if_getcapenable(ifp) & 2376 IFCAP_VLAN_HWTAGGING) != 0) 2377 NGE_SETBIT(sc, 2378 NGE_VLAN_IP_RXCTL, 2379 NGE_VIPRXCTL_TAG_STRIP_ENB); 2380 else 2381 NGE_CLRBIT(sc, 2382 NGE_VLAN_IP_RXCTL, 2383 NGE_VIPRXCTL_TAG_STRIP_ENB); 2384 } 2385 } 2386 /* 2387 * Both VLAN hardware tagging and checksum offload is 2388 * required to do checksum offload on VLAN interface. 2389 */ 2390 if ((if_getcapenable(ifp) & IFCAP_TXCSUM) == 0) 2391 if_setcapenablebit(ifp, 0, IFCAP_VLAN_HWCSUM); 2392 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) == 0) 2393 if_setcapenablebit(ifp, 0, IFCAP_VLAN_HWCSUM); 2394 NGE_UNLOCK(sc); 2395 VLAN_CAPABILITIES(ifp); 2396 break; 2397 default: 2398 error = ether_ioctl(ifp, command, data); 2399 break; 2400 } 2401 2402 return (error); 2403 } 2404 2405 static void 2406 nge_watchdog(struct nge_softc *sc) 2407 { 2408 if_t ifp; 2409 2410 NGE_LOCK_ASSERT(sc); 2411 2412 if (sc->nge_watchdog_timer == 0 || --sc->nge_watchdog_timer) 2413 return; 2414 2415 ifp = sc->nge_ifp; 2416 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 2417 if_printf(ifp, "watchdog timeout\n"); 2418 2419 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 2420 nge_init_locked(sc); 2421 2422 if (!if_sendq_empty(ifp)) 2423 nge_start_locked(ifp); 2424 } 2425 2426 static int 2427 nge_stop_mac(struct nge_softc *sc) 2428 { 2429 uint32_t reg; 2430 int i; 2431 2432 NGE_LOCK_ASSERT(sc); 2433 2434 reg = CSR_READ_4(sc, NGE_CSR); 2435 if ((reg & (NGE_CSR_TX_ENABLE | NGE_CSR_RX_ENABLE)) != 0) { 2436 reg &= ~(NGE_CSR_TX_ENABLE | NGE_CSR_RX_ENABLE); 2437 reg |= NGE_CSR_TX_DISABLE | NGE_CSR_RX_DISABLE; 2438 CSR_WRITE_4(sc, NGE_CSR, reg); 2439 for (i = 0; i < NGE_TIMEOUT; i++) { 2440 DELAY(1); 2441 if ((CSR_READ_4(sc, NGE_CSR) & 2442 (NGE_CSR_RX_ENABLE | NGE_CSR_TX_ENABLE)) == 0) 2443 break; 2444 } 2445 if (i == NGE_TIMEOUT) 2446 return (ETIMEDOUT); 2447 } 2448 2449 return (0); 2450 } 2451 2452 /* 2453 * Stop the adapter and free any mbufs allocated to the 2454 * RX and TX lists. 2455 */ 2456 static void 2457 nge_stop(struct nge_softc *sc) 2458 { 2459 struct nge_txdesc *txd; 2460 struct nge_rxdesc *rxd; 2461 int i; 2462 if_t ifp; 2463 2464 NGE_LOCK_ASSERT(sc); 2465 ifp = sc->nge_ifp; 2466 2467 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)); 2468 sc->nge_flags &= ~NGE_FLAG_LINK; 2469 callout_stop(&sc->nge_stat_ch); 2470 sc->nge_watchdog_timer = 0; 2471 2472 CSR_WRITE_4(sc, NGE_IER, 0); 2473 CSR_WRITE_4(sc, NGE_IMR, 0); 2474 if (nge_stop_mac(sc) == ETIMEDOUT) 2475 device_printf(sc->nge_dev, 2476 "%s: unable to stop Tx/Rx MAC\n", __func__); 2477 CSR_WRITE_4(sc, NGE_TX_LISTPTR_HI, 0); 2478 CSR_WRITE_4(sc, NGE_TX_LISTPTR_LO, 0); 2479 CSR_WRITE_4(sc, NGE_RX_LISTPTR_HI, 0); 2480 CSR_WRITE_4(sc, NGE_RX_LISTPTR_LO, 0); 2481 nge_stats_update(sc); 2482 if (sc->nge_head != NULL) { 2483 m_freem(sc->nge_head); 2484 sc->nge_head = sc->nge_tail = NULL; 2485 } 2486 2487 /* 2488 * Free RX and TX mbufs still in the queues. 2489 */ 2490 for (i = 0; i < NGE_RX_RING_CNT; i++) { 2491 rxd = &sc->nge_cdata.nge_rxdesc[i]; 2492 if (rxd->rx_m != NULL) { 2493 bus_dmamap_sync(sc->nge_cdata.nge_rx_tag, 2494 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 2495 bus_dmamap_unload(sc->nge_cdata.nge_rx_tag, 2496 rxd->rx_dmamap); 2497 m_freem(rxd->rx_m); 2498 rxd->rx_m = NULL; 2499 } 2500 } 2501 for (i = 0; i < NGE_TX_RING_CNT; i++) { 2502 txd = &sc->nge_cdata.nge_txdesc[i]; 2503 if (txd->tx_m != NULL) { 2504 bus_dmamap_sync(sc->nge_cdata.nge_tx_tag, 2505 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2506 bus_dmamap_unload(sc->nge_cdata.nge_tx_tag, 2507 txd->tx_dmamap); 2508 m_freem(txd->tx_m); 2509 txd->tx_m = NULL; 2510 } 2511 } 2512 } 2513 2514 /* 2515 * Before setting WOL bits, caller should have stopped Receiver. 2516 */ 2517 static void 2518 nge_wol(struct nge_softc *sc) 2519 { 2520 if_t ifp; 2521 uint32_t reg; 2522 uint16_t pmstat; 2523 int pmc; 2524 2525 NGE_LOCK_ASSERT(sc); 2526 2527 if (pci_find_cap(sc->nge_dev, PCIY_PMG, &pmc) != 0) 2528 return; 2529 2530 ifp = sc->nge_ifp; 2531 if ((if_getcapenable(ifp) & IFCAP_WOL) == 0) { 2532 /* Disable WOL & disconnect CLKRUN to save power. */ 2533 CSR_WRITE_4(sc, NGE_WOLCSR, 0); 2534 CSR_WRITE_4(sc, NGE_CLKRUN, 0); 2535 } else { 2536 if (nge_stop_mac(sc) == ETIMEDOUT) 2537 device_printf(sc->nge_dev, 2538 "%s: unable to stop Tx/Rx MAC\n", __func__); 2539 /* 2540 * Make sure wake frames will be buffered in the Rx FIFO. 2541 * (i.e. Silent Rx mode.) 2542 */ 2543 CSR_WRITE_4(sc, NGE_RX_LISTPTR_HI, 0); 2544 CSR_BARRIER_4(sc, NGE_RX_LISTPTR_HI, BUS_SPACE_BARRIER_WRITE); 2545 CSR_WRITE_4(sc, NGE_RX_LISTPTR_LO, 0); 2546 CSR_BARRIER_4(sc, NGE_RX_LISTPTR_LO, BUS_SPACE_BARRIER_WRITE); 2547 /* Enable Rx again. */ 2548 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE); 2549 CSR_BARRIER_4(sc, NGE_CSR, BUS_SPACE_BARRIER_WRITE); 2550 2551 /* Configure WOL events. */ 2552 reg = 0; 2553 if ((if_getcapenable(ifp) & IFCAP_WOL_UCAST) != 0) 2554 reg |= NGE_WOLCSR_WAKE_ON_UNICAST; 2555 if ((if_getcapenable(ifp) & IFCAP_WOL_MCAST) != 0) 2556 reg |= NGE_WOLCSR_WAKE_ON_MULTICAST; 2557 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) != 0) 2558 reg |= NGE_WOLCSR_WAKE_ON_MAGICPKT; 2559 CSR_WRITE_4(sc, NGE_WOLCSR, reg); 2560 2561 /* Activate CLKRUN. */ 2562 reg = CSR_READ_4(sc, NGE_CLKRUN); 2563 reg |= NGE_CLKRUN_PMEENB | NGE_CLNRUN_CLKRUN_ENB; 2564 CSR_WRITE_4(sc, NGE_CLKRUN, reg); 2565 } 2566 2567 /* Request PME. */ 2568 pmstat = pci_read_config(sc->nge_dev, pmc + PCIR_POWER_STATUS, 2); 2569 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 2570 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) 2571 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 2572 pci_write_config(sc->nge_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 2573 } 2574 2575 /* 2576 * Stop all chip I/O so that the kernel's probe routines don't 2577 * get confused by errant DMAs when rebooting. 2578 */ 2579 static int 2580 nge_shutdown(device_t dev) 2581 { 2582 2583 return (nge_suspend(dev)); 2584 } 2585 2586 static int 2587 nge_suspend(device_t dev) 2588 { 2589 struct nge_softc *sc; 2590 2591 sc = device_get_softc(dev); 2592 2593 NGE_LOCK(sc); 2594 nge_stop(sc); 2595 nge_wol(sc); 2596 sc->nge_flags |= NGE_FLAG_SUSPENDED; 2597 NGE_UNLOCK(sc); 2598 2599 return (0); 2600 } 2601 2602 static int 2603 nge_resume(device_t dev) 2604 { 2605 struct nge_softc *sc; 2606 if_t ifp; 2607 uint16_t pmstat; 2608 int pmc; 2609 2610 sc = device_get_softc(dev); 2611 2612 NGE_LOCK(sc); 2613 ifp = sc->nge_ifp; 2614 if (pci_find_cap(sc->nge_dev, PCIY_PMG, &pmc) == 0) { 2615 /* Disable PME and clear PME status. */ 2616 pmstat = pci_read_config(sc->nge_dev, 2617 pmc + PCIR_POWER_STATUS, 2); 2618 if ((pmstat & PCIM_PSTAT_PMEENABLE) != 0) { 2619 pmstat &= ~PCIM_PSTAT_PMEENABLE; 2620 pci_write_config(sc->nge_dev, 2621 pmc + PCIR_POWER_STATUS, pmstat, 2); 2622 } 2623 } 2624 if (if_getflags(ifp) & IFF_UP) { 2625 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 2626 nge_init_locked(sc); 2627 } 2628 2629 sc->nge_flags &= ~NGE_FLAG_SUSPENDED; 2630 NGE_UNLOCK(sc); 2631 2632 return (0); 2633 } 2634 2635 #define NGE_SYSCTL_STAT_ADD32(c, h, n, p, d) \ 2636 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d) 2637 2638 static void 2639 nge_sysctl_node(struct nge_softc *sc) 2640 { 2641 struct sysctl_ctx_list *ctx; 2642 struct sysctl_oid_list *child, *parent; 2643 struct sysctl_oid *tree; 2644 struct nge_stats *stats; 2645 int error; 2646 2647 ctx = device_get_sysctl_ctx(sc->nge_dev); 2648 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->nge_dev)); 2649 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_holdoff", 2650 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, &sc->nge_int_holdoff, 2651 0, sysctl_hw_nge_int_holdoff, "I", "NGE interrupt moderation"); 2652 /* Pull in device tunables. */ 2653 sc->nge_int_holdoff = NGE_INT_HOLDOFF_DEFAULT; 2654 error = resource_int_value(device_get_name(sc->nge_dev), 2655 device_get_unit(sc->nge_dev), "int_holdoff", &sc->nge_int_holdoff); 2656 if (error == 0) { 2657 if (sc->nge_int_holdoff < NGE_INT_HOLDOFF_MIN || 2658 sc->nge_int_holdoff > NGE_INT_HOLDOFF_MAX ) { 2659 device_printf(sc->nge_dev, 2660 "int_holdoff value out of range; " 2661 "using default: %d(%d us)\n", 2662 NGE_INT_HOLDOFF_DEFAULT, 2663 NGE_INT_HOLDOFF_DEFAULT * 100); 2664 sc->nge_int_holdoff = NGE_INT_HOLDOFF_DEFAULT; 2665 } 2666 } 2667 2668 stats = &sc->nge_stats; 2669 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", 2670 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "NGE statistics"); 2671 parent = SYSCTL_CHILDREN(tree); 2672 2673 /* Rx statistics. */ 2674 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", 2675 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Rx MAC statistics"); 2676 child = SYSCTL_CHILDREN(tree); 2677 NGE_SYSCTL_STAT_ADD32(ctx, child, "pkts_errs", 2678 &stats->rx_pkts_errs, 2679 "Packet errors including both wire errors and FIFO overruns"); 2680 NGE_SYSCTL_STAT_ADD32(ctx, child, "crc_errs", 2681 &stats->rx_crc_errs, "CRC errors"); 2682 NGE_SYSCTL_STAT_ADD32(ctx, child, "fifo_oflows", 2683 &stats->rx_fifo_oflows, "FIFO overflows"); 2684 NGE_SYSCTL_STAT_ADD32(ctx, child, "align_errs", 2685 &stats->rx_align_errs, "Frame alignment errors"); 2686 NGE_SYSCTL_STAT_ADD32(ctx, child, "sym_errs", 2687 &stats->rx_sym_errs, "One or more symbol errors"); 2688 NGE_SYSCTL_STAT_ADD32(ctx, child, "pkts_jumbos", 2689 &stats->rx_pkts_jumbos, 2690 "Packets received with length greater than 1518 bytes"); 2691 NGE_SYSCTL_STAT_ADD32(ctx, child, "len_errs", 2692 &stats->rx_len_errs, "In Range Length errors"); 2693 NGE_SYSCTL_STAT_ADD32(ctx, child, "unctl_frames", 2694 &stats->rx_unctl_frames, "Control frames with unsupported opcode"); 2695 NGE_SYSCTL_STAT_ADD32(ctx, child, "pause", 2696 &stats->rx_pause, "Pause frames"); 2697 2698 /* Tx statistics. */ 2699 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", 2700 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Tx MAC statistics"); 2701 child = SYSCTL_CHILDREN(tree); 2702 NGE_SYSCTL_STAT_ADD32(ctx, child, "pause", 2703 &stats->tx_pause, "Pause frames"); 2704 NGE_SYSCTL_STAT_ADD32(ctx, child, "seq_errs", 2705 &stats->tx_seq_errs, 2706 "Loss of collision heartbeat during transmission"); 2707 } 2708 2709 #undef NGE_SYSCTL_STAT_ADD32 2710 2711 static int 2712 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 2713 { 2714 int error, value; 2715 2716 if (arg1 == NULL) 2717 return (EINVAL); 2718 value = *(int *)arg1; 2719 error = sysctl_handle_int(oidp, &value, 0, req); 2720 if (error != 0 || req->newptr == NULL) 2721 return (error); 2722 if (value < low || value > high) 2723 return (EINVAL); 2724 *(int *)arg1 = value; 2725 2726 return (0); 2727 } 2728 2729 static int 2730 sysctl_hw_nge_int_holdoff(SYSCTL_HANDLER_ARGS) 2731 { 2732 2733 return (sysctl_int_range(oidp, arg1, arg2, req, NGE_INT_HOLDOFF_MIN, 2734 NGE_INT_HOLDOFF_MAX)); 2735 } 2736