1 /* 2 * Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2000, 2001 4 * Bill Paul <wpaul@bsdi.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <sys/cdefs.h> 35 __FBSDID("$FreeBSD$"); 36 37 /* 38 * National Semiconductor DP83820/DP83821 gigabit ethernet driver 39 * for FreeBSD. Datasheets are available from: 40 * 41 * http://www.national.com/ds/DP/DP83820.pdf 42 * http://www.national.com/ds/DP/DP83821.pdf 43 * 44 * These chips are used on several low cost gigabit ethernet NICs 45 * sold by D-Link, Addtron, SMC and Asante. Both parts are 46 * virtually the same, except the 83820 is a 64-bit/32-bit part, 47 * while the 83821 is 32-bit only. 48 * 49 * Many cards also use National gigE transceivers, such as the 50 * DP83891, DP83861 and DP83862 gigPHYTER parts. The DP83861 datasheet 51 * contains a full register description that applies to all of these 52 * components: 53 * 54 * http://www.national.com/ds/DP/DP83861.pdf 55 * 56 * Written by Bill Paul <wpaul@bsdi.com> 57 * BSDi Open Source Solutions 58 */ 59 60 /* 61 * The NatSemi DP83820 and 83821 controllers are enhanced versions 62 * of the NatSemi MacPHYTER 10/100 devices. They support 10, 100 63 * and 1000Mbps speeds with 1000baseX (ten bit interface), MII and GMII 64 * ports. Other features include 8K TX FIFO and 32K RX FIFO, TCP/IP 65 * hardware checksum offload (IPv4 only), VLAN tagging and filtering, 66 * priority TX and RX queues, a 2048 bit multicast hash filter, 4 RX pattern 67 * matching buffers, one perfect address filter buffer and interrupt 68 * moderation. The 83820 supports both 64-bit and 32-bit addressing 69 * and data transfers: the 64-bit support can be toggled on or off 70 * via software. This affects the size of certain fields in the DMA 71 * descriptors. 72 * 73 * There are two bugs/misfeatures in the 83820/83821 that I have 74 * discovered so far: 75 * 76 * - Receive buffers must be aligned on 64-bit boundaries, which means 77 * you must resort to copying data in order to fix up the payload 78 * alignment. 79 * 80 * - In order to transmit jumbo frames larger than 8170 bytes, you have 81 * to turn off transmit checksum offloading, because the chip can't 82 * compute the checksum on an outgoing frame unless it fits entirely 83 * within the TX FIFO, which is only 8192 bytes in size. If you have 84 * TX checksum offload enabled and you transmit attempt to transmit a 85 * frame larger than 8170 bytes, the transmitter will wedge. 86 * 87 * To work around the latter problem, TX checksum offload is disabled 88 * if the user selects an MTU larger than 8152 (8170 - 18). 89 */ 90 91 #include <sys/param.h> 92 #include <sys/systm.h> 93 #include <sys/sockio.h> 94 #include <sys/mbuf.h> 95 #include <sys/malloc.h> 96 #include <sys/kernel.h> 97 #include <sys/socket.h> 98 99 #include <net/if.h> 100 #include <net/if_arp.h> 101 #include <net/ethernet.h> 102 #include <net/if_dl.h> 103 #include <net/if_media.h> 104 #include <net/if_types.h> 105 #include <net/if_vlan_var.h> 106 107 #include <net/bpf.h> 108 109 #include <vm/vm.h> /* for vtophys */ 110 #include <vm/pmap.h> /* for vtophys */ 111 #include <machine/clock.h> /* for DELAY */ 112 #include <machine/bus_pio.h> 113 #include <machine/bus_memio.h> 114 #include <machine/bus.h> 115 #include <machine/resource.h> 116 #include <sys/bus.h> 117 #include <sys/rman.h> 118 119 #include <dev/mii/mii.h> 120 #include <dev/mii/miivar.h> 121 122 #include <dev/pci/pcireg.h> 123 #include <dev/pci/pcivar.h> 124 125 #define NGE_USEIOSPACE 126 127 #include <dev/nge/if_ngereg.h> 128 129 MODULE_DEPEND(nge, pci, 1, 1, 1); 130 MODULE_DEPEND(nge, ether, 1, 1, 1); 131 MODULE_DEPEND(nge, miibus, 1, 1, 1); 132 133 /* "controller miibus0" required. See GENERIC if you get errors here. */ 134 #include "miibus_if.h" 135 136 #define NGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 137 138 /* 139 * Various supported device vendors/types and their names. 140 */ 141 static struct nge_type nge_devs[] = { 142 { NGE_VENDORID, NGE_DEVICEID, 143 "National Semiconductor Gigabit Ethernet" }, 144 { 0, 0, NULL } 145 }; 146 147 static int nge_probe(device_t); 148 static int nge_attach(device_t); 149 static int nge_detach(device_t); 150 151 static int nge_alloc_jumbo_mem(struct nge_softc *); 152 static void nge_free_jumbo_mem(struct nge_softc *); 153 static void *nge_jalloc(struct nge_softc *); 154 static void nge_jfree(void *, void *); 155 156 static int nge_newbuf(struct nge_softc *, struct nge_desc *, struct mbuf *); 157 static int nge_encap(struct nge_softc *, struct mbuf *, u_int32_t *); 158 static void nge_rxeof(struct nge_softc *); 159 static void nge_txeof(struct nge_softc *); 160 static void nge_intr(void *); 161 static void nge_tick(void *); 162 static void nge_start(struct ifnet *); 163 static int nge_ioctl(struct ifnet *, u_long, caddr_t); 164 static void nge_init(void *); 165 static void nge_stop(struct nge_softc *); 166 static void nge_watchdog(struct ifnet *); 167 static void nge_shutdown(device_t); 168 static int nge_ifmedia_upd(struct ifnet *); 169 static void nge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 170 171 static void nge_delay(struct nge_softc *); 172 static void nge_eeprom_idle(struct nge_softc *); 173 static void nge_eeprom_putbyte(struct nge_softc *, int); 174 static void nge_eeprom_getword(struct nge_softc *, int, u_int16_t *); 175 static void nge_read_eeprom(struct nge_softc *, caddr_t, int, int, int); 176 177 static void nge_mii_sync(struct nge_softc *); 178 static void nge_mii_send(struct nge_softc *, u_int32_t, int); 179 static int nge_mii_readreg(struct nge_softc *, struct nge_mii_frame *); 180 static int nge_mii_writereg(struct nge_softc *, struct nge_mii_frame *); 181 182 static int nge_miibus_readreg(device_t, int, int); 183 static int nge_miibus_writereg(device_t, int, int, int); 184 static void nge_miibus_statchg(device_t); 185 186 static void nge_setmulti(struct nge_softc *); 187 static u_int32_t nge_mchash(caddr_t); 188 static void nge_reset(struct nge_softc *); 189 static int nge_list_rx_init(struct nge_softc *); 190 static int nge_list_tx_init(struct nge_softc *); 191 192 #ifdef NGE_USEIOSPACE 193 #define NGE_RES SYS_RES_IOPORT 194 #define NGE_RID NGE_PCI_LOIO 195 #else 196 #define NGE_RES SYS_RES_MEMORY 197 #define NGE_RID NGE_PCI_LOMEM 198 #endif 199 200 static device_method_t nge_methods[] = { 201 /* Device interface */ 202 DEVMETHOD(device_probe, nge_probe), 203 DEVMETHOD(device_attach, nge_attach), 204 DEVMETHOD(device_detach, nge_detach), 205 DEVMETHOD(device_shutdown, nge_shutdown), 206 207 /* bus interface */ 208 DEVMETHOD(bus_print_child, bus_generic_print_child), 209 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 210 211 /* MII interface */ 212 DEVMETHOD(miibus_readreg, nge_miibus_readreg), 213 DEVMETHOD(miibus_writereg, nge_miibus_writereg), 214 DEVMETHOD(miibus_statchg, nge_miibus_statchg), 215 216 { 0, 0 } 217 }; 218 219 static driver_t nge_driver = { 220 "nge", 221 nge_methods, 222 sizeof(struct nge_softc) 223 }; 224 225 static devclass_t nge_devclass; 226 227 DRIVER_MODULE(nge, pci, nge_driver, nge_devclass, 0, 0); 228 DRIVER_MODULE(miibus, nge, miibus_driver, miibus_devclass, 0, 0); 229 230 #define NGE_SETBIT(sc, reg, x) \ 231 CSR_WRITE_4(sc, reg, \ 232 CSR_READ_4(sc, reg) | (x)) 233 234 #define NGE_CLRBIT(sc, reg, x) \ 235 CSR_WRITE_4(sc, reg, \ 236 CSR_READ_4(sc, reg) & ~(x)) 237 238 #define SIO_SET(x) \ 239 CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) | (x)) 240 241 #define SIO_CLR(x) \ 242 CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) & ~(x)) 243 244 static void 245 nge_delay(sc) 246 struct nge_softc *sc; 247 { 248 int idx; 249 250 for (idx = (300 / 33) + 1; idx > 0; idx--) 251 CSR_READ_4(sc, NGE_CSR); 252 253 return; 254 } 255 256 static void 257 nge_eeprom_idle(sc) 258 struct nge_softc *sc; 259 { 260 register int i; 261 262 SIO_SET(NGE_MEAR_EE_CSEL); 263 nge_delay(sc); 264 SIO_SET(NGE_MEAR_EE_CLK); 265 nge_delay(sc); 266 267 for (i = 0; i < 25; i++) { 268 SIO_CLR(NGE_MEAR_EE_CLK); 269 nge_delay(sc); 270 SIO_SET(NGE_MEAR_EE_CLK); 271 nge_delay(sc); 272 } 273 274 SIO_CLR(NGE_MEAR_EE_CLK); 275 nge_delay(sc); 276 SIO_CLR(NGE_MEAR_EE_CSEL); 277 nge_delay(sc); 278 CSR_WRITE_4(sc, NGE_MEAR, 0x00000000); 279 280 return; 281 } 282 283 /* 284 * Send a read command and address to the EEPROM, check for ACK. 285 */ 286 static void 287 nge_eeprom_putbyte(sc, addr) 288 struct nge_softc *sc; 289 int addr; 290 { 291 register int d, i; 292 293 d = addr | NGE_EECMD_READ; 294 295 /* 296 * Feed in each bit and stobe the clock. 297 */ 298 for (i = 0x400; i; i >>= 1) { 299 if (d & i) { 300 SIO_SET(NGE_MEAR_EE_DIN); 301 } else { 302 SIO_CLR(NGE_MEAR_EE_DIN); 303 } 304 nge_delay(sc); 305 SIO_SET(NGE_MEAR_EE_CLK); 306 nge_delay(sc); 307 SIO_CLR(NGE_MEAR_EE_CLK); 308 nge_delay(sc); 309 } 310 311 return; 312 } 313 314 /* 315 * Read a word of data stored in the EEPROM at address 'addr.' 316 */ 317 static void 318 nge_eeprom_getword(sc, addr, dest) 319 struct nge_softc *sc; 320 int addr; 321 u_int16_t *dest; 322 { 323 register int i; 324 u_int16_t word = 0; 325 326 /* Force EEPROM to idle state. */ 327 nge_eeprom_idle(sc); 328 329 /* Enter EEPROM access mode. */ 330 nge_delay(sc); 331 SIO_CLR(NGE_MEAR_EE_CLK); 332 nge_delay(sc); 333 SIO_SET(NGE_MEAR_EE_CSEL); 334 nge_delay(sc); 335 336 /* 337 * Send address of word we want to read. 338 */ 339 nge_eeprom_putbyte(sc, addr); 340 341 /* 342 * Start reading bits from EEPROM. 343 */ 344 for (i = 0x8000; i; i >>= 1) { 345 SIO_SET(NGE_MEAR_EE_CLK); 346 nge_delay(sc); 347 if (CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_EE_DOUT) 348 word |= i; 349 nge_delay(sc); 350 SIO_CLR(NGE_MEAR_EE_CLK); 351 nge_delay(sc); 352 } 353 354 /* Turn off EEPROM access mode. */ 355 nge_eeprom_idle(sc); 356 357 *dest = word; 358 359 return; 360 } 361 362 /* 363 * Read a sequence of words from the EEPROM. 364 */ 365 static void 366 nge_read_eeprom(sc, dest, off, cnt, swap) 367 struct nge_softc *sc; 368 caddr_t dest; 369 int off; 370 int cnt; 371 int swap; 372 { 373 int i; 374 u_int16_t word = 0, *ptr; 375 376 for (i = 0; i < cnt; i++) { 377 nge_eeprom_getword(sc, off + i, &word); 378 ptr = (u_int16_t *)(dest + (i * 2)); 379 if (swap) 380 *ptr = ntohs(word); 381 else 382 *ptr = word; 383 } 384 385 return; 386 } 387 388 /* 389 * Sync the PHYs by setting data bit and strobing the clock 32 times. 390 */ 391 static void 392 nge_mii_sync(sc) 393 struct nge_softc *sc; 394 { 395 register int i; 396 397 SIO_SET(NGE_MEAR_MII_DIR|NGE_MEAR_MII_DATA); 398 399 for (i = 0; i < 32; i++) { 400 SIO_SET(NGE_MEAR_MII_CLK); 401 DELAY(1); 402 SIO_CLR(NGE_MEAR_MII_CLK); 403 DELAY(1); 404 } 405 406 return; 407 } 408 409 /* 410 * Clock a series of bits through the MII. 411 */ 412 static void 413 nge_mii_send(sc, bits, cnt) 414 struct nge_softc *sc; 415 u_int32_t bits; 416 int cnt; 417 { 418 int i; 419 420 SIO_CLR(NGE_MEAR_MII_CLK); 421 422 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 423 if (bits & i) { 424 SIO_SET(NGE_MEAR_MII_DATA); 425 } else { 426 SIO_CLR(NGE_MEAR_MII_DATA); 427 } 428 DELAY(1); 429 SIO_CLR(NGE_MEAR_MII_CLK); 430 DELAY(1); 431 SIO_SET(NGE_MEAR_MII_CLK); 432 } 433 } 434 435 /* 436 * Read an PHY register through the MII. 437 */ 438 static int 439 nge_mii_readreg(sc, frame) 440 struct nge_softc *sc; 441 struct nge_mii_frame *frame; 442 443 { 444 int i, ack, s; 445 446 s = splimp(); 447 448 /* 449 * Set up frame for RX. 450 */ 451 frame->mii_stdelim = NGE_MII_STARTDELIM; 452 frame->mii_opcode = NGE_MII_READOP; 453 frame->mii_turnaround = 0; 454 frame->mii_data = 0; 455 456 CSR_WRITE_4(sc, NGE_MEAR, 0); 457 458 /* 459 * Turn on data xmit. 460 */ 461 SIO_SET(NGE_MEAR_MII_DIR); 462 463 nge_mii_sync(sc); 464 465 /* 466 * Send command/address info. 467 */ 468 nge_mii_send(sc, frame->mii_stdelim, 2); 469 nge_mii_send(sc, frame->mii_opcode, 2); 470 nge_mii_send(sc, frame->mii_phyaddr, 5); 471 nge_mii_send(sc, frame->mii_regaddr, 5); 472 473 /* Idle bit */ 474 SIO_CLR((NGE_MEAR_MII_CLK|NGE_MEAR_MII_DATA)); 475 DELAY(1); 476 SIO_SET(NGE_MEAR_MII_CLK); 477 DELAY(1); 478 479 /* Turn off xmit. */ 480 SIO_CLR(NGE_MEAR_MII_DIR); 481 /* Check for ack */ 482 SIO_CLR(NGE_MEAR_MII_CLK); 483 DELAY(1); 484 ack = CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_MII_DATA; 485 SIO_SET(NGE_MEAR_MII_CLK); 486 DELAY(1); 487 488 /* 489 * Now try reading data bits. If the ack failed, we still 490 * need to clock through 16 cycles to keep the PHY(s) in sync. 491 */ 492 if (ack) { 493 for(i = 0; i < 16; i++) { 494 SIO_CLR(NGE_MEAR_MII_CLK); 495 DELAY(1); 496 SIO_SET(NGE_MEAR_MII_CLK); 497 DELAY(1); 498 } 499 goto fail; 500 } 501 502 for (i = 0x8000; i; i >>= 1) { 503 SIO_CLR(NGE_MEAR_MII_CLK); 504 DELAY(1); 505 if (!ack) { 506 if (CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_MII_DATA) 507 frame->mii_data |= i; 508 DELAY(1); 509 } 510 SIO_SET(NGE_MEAR_MII_CLK); 511 DELAY(1); 512 } 513 514 fail: 515 516 SIO_CLR(NGE_MEAR_MII_CLK); 517 DELAY(1); 518 SIO_SET(NGE_MEAR_MII_CLK); 519 DELAY(1); 520 521 splx(s); 522 523 if (ack) 524 return(1); 525 return(0); 526 } 527 528 /* 529 * Write to a PHY register through the MII. 530 */ 531 static int 532 nge_mii_writereg(sc, frame) 533 struct nge_softc *sc; 534 struct nge_mii_frame *frame; 535 536 { 537 int s; 538 539 s = splimp(); 540 /* 541 * Set up frame for TX. 542 */ 543 544 frame->mii_stdelim = NGE_MII_STARTDELIM; 545 frame->mii_opcode = NGE_MII_WRITEOP; 546 frame->mii_turnaround = NGE_MII_TURNAROUND; 547 548 /* 549 * Turn on data output. 550 */ 551 SIO_SET(NGE_MEAR_MII_DIR); 552 553 nge_mii_sync(sc); 554 555 nge_mii_send(sc, frame->mii_stdelim, 2); 556 nge_mii_send(sc, frame->mii_opcode, 2); 557 nge_mii_send(sc, frame->mii_phyaddr, 5); 558 nge_mii_send(sc, frame->mii_regaddr, 5); 559 nge_mii_send(sc, frame->mii_turnaround, 2); 560 nge_mii_send(sc, frame->mii_data, 16); 561 562 /* Idle bit. */ 563 SIO_SET(NGE_MEAR_MII_CLK); 564 DELAY(1); 565 SIO_CLR(NGE_MEAR_MII_CLK); 566 DELAY(1); 567 568 /* 569 * Turn off xmit. 570 */ 571 SIO_CLR(NGE_MEAR_MII_DIR); 572 573 splx(s); 574 575 return(0); 576 } 577 578 static int 579 nge_miibus_readreg(dev, phy, reg) 580 device_t dev; 581 int phy, reg; 582 { 583 struct nge_softc *sc; 584 struct nge_mii_frame frame; 585 586 sc = device_get_softc(dev); 587 588 bzero((char *)&frame, sizeof(frame)); 589 590 frame.mii_phyaddr = phy; 591 frame.mii_regaddr = reg; 592 nge_mii_readreg(sc, &frame); 593 594 return(frame.mii_data); 595 } 596 597 static int 598 nge_miibus_writereg(dev, phy, reg, data) 599 device_t dev; 600 int phy, reg, data; 601 { 602 struct nge_softc *sc; 603 struct nge_mii_frame frame; 604 605 sc = device_get_softc(dev); 606 607 bzero((char *)&frame, sizeof(frame)); 608 609 frame.mii_phyaddr = phy; 610 frame.mii_regaddr = reg; 611 frame.mii_data = data; 612 nge_mii_writereg(sc, &frame); 613 614 return(0); 615 } 616 617 static void 618 nge_miibus_statchg(dev) 619 device_t dev; 620 { 621 int status; 622 struct nge_softc *sc; 623 struct mii_data *mii; 624 625 sc = device_get_softc(dev); 626 if (sc->nge_tbi) { 627 if (IFM_SUBTYPE(sc->nge_ifmedia.ifm_cur->ifm_media) 628 == IFM_AUTO) { 629 status = CSR_READ_4(sc, NGE_TBI_ANLPAR); 630 if (status == 0 || status & NGE_TBIANAR_FDX) { 631 NGE_SETBIT(sc, NGE_TX_CFG, 632 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 633 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 634 } else { 635 NGE_CLRBIT(sc, NGE_TX_CFG, 636 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 637 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 638 } 639 640 } else if ((sc->nge_ifmedia.ifm_cur->ifm_media & IFM_GMASK) 641 != IFM_FDX) { 642 NGE_CLRBIT(sc, NGE_TX_CFG, 643 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 644 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 645 } else { 646 NGE_SETBIT(sc, NGE_TX_CFG, 647 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 648 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 649 } 650 } else { 651 mii = device_get_softc(sc->nge_miibus); 652 653 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 654 NGE_SETBIT(sc, NGE_TX_CFG, 655 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 656 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 657 } else { 658 NGE_CLRBIT(sc, NGE_TX_CFG, 659 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 660 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 661 } 662 663 /* If we have a 1000Mbps link, set the mode_1000 bit. */ 664 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 665 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) { 666 NGE_SETBIT(sc, NGE_CFG, NGE_CFG_MODE_1000); 667 } else { 668 NGE_CLRBIT(sc, NGE_CFG, NGE_CFG_MODE_1000); 669 } 670 } 671 return; 672 } 673 674 static u_int32_t 675 nge_mchash(addr) 676 caddr_t addr; 677 { 678 u_int32_t crc, carry; 679 int idx, bit; 680 u_int8_t data; 681 682 /* Compute CRC for the address value. */ 683 crc = 0xFFFFFFFF; /* initial value */ 684 685 for (idx = 0; idx < 6; idx++) { 686 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) { 687 carry = ((crc & 0x80000000) ? 1 : 0) ^ (data & 0x01); 688 crc <<= 1; 689 if (carry) 690 crc = (crc ^ 0x04c11db6) | carry; 691 } 692 } 693 694 /* 695 * return the filter bit position 696 */ 697 698 return((crc >> 21) & 0x00000FFF); 699 } 700 701 static void 702 nge_setmulti(sc) 703 struct nge_softc *sc; 704 { 705 struct ifnet *ifp; 706 struct ifmultiaddr *ifma; 707 u_int32_t h = 0, i, filtsave; 708 int bit, index; 709 710 ifp = &sc->arpcom.ac_if; 711 712 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 713 NGE_CLRBIT(sc, NGE_RXFILT_CTL, 714 NGE_RXFILTCTL_MCHASH|NGE_RXFILTCTL_UCHASH); 715 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLMULTI); 716 return; 717 } 718 719 /* 720 * We have to explicitly enable the multicast hash table 721 * on the NatSemi chip if we want to use it, which we do. 722 * We also have to tell it that we don't want to use the 723 * hash table for matching unicast addresses. 724 */ 725 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_MCHASH); 726 NGE_CLRBIT(sc, NGE_RXFILT_CTL, 727 NGE_RXFILTCTL_ALLMULTI|NGE_RXFILTCTL_UCHASH); 728 729 filtsave = CSR_READ_4(sc, NGE_RXFILT_CTL); 730 731 /* first, zot all the existing hash bits */ 732 for (i = 0; i < NGE_MCAST_FILTER_LEN; i += 2) { 733 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_MCAST_LO + i); 734 CSR_WRITE_4(sc, NGE_RXFILT_DATA, 0); 735 } 736 737 /* 738 * From the 11 bits returned by the crc routine, the top 7 739 * bits represent the 16-bit word in the mcast hash table 740 * that needs to be updated, and the lower 4 bits represent 741 * which bit within that byte needs to be set. 742 */ 743 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 744 if (ifma->ifma_addr->sa_family != AF_LINK) 745 continue; 746 h = nge_mchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 747 index = (h >> 4) & 0x7F; 748 bit = h & 0xF; 749 CSR_WRITE_4(sc, NGE_RXFILT_CTL, 750 NGE_FILTADDR_MCAST_LO + (index * 2)); 751 NGE_SETBIT(sc, NGE_RXFILT_DATA, (1 << bit)); 752 } 753 754 CSR_WRITE_4(sc, NGE_RXFILT_CTL, filtsave); 755 756 return; 757 } 758 759 static void 760 nge_reset(sc) 761 struct nge_softc *sc; 762 { 763 register int i; 764 765 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RESET); 766 767 for (i = 0; i < NGE_TIMEOUT; i++) { 768 if (!(CSR_READ_4(sc, NGE_CSR) & NGE_CSR_RESET)) 769 break; 770 } 771 772 if (i == NGE_TIMEOUT) 773 printf("nge%d: reset never completed\n", sc->nge_unit); 774 775 /* Wait a little while for the chip to get its brains in order. */ 776 DELAY(1000); 777 778 /* 779 * If this is a NetSemi chip, make sure to clear 780 * PME mode. 781 */ 782 CSR_WRITE_4(sc, NGE_CLKRUN, NGE_CLKRUN_PMESTS); 783 CSR_WRITE_4(sc, NGE_CLKRUN, 0); 784 785 return; 786 } 787 788 /* 789 * Probe for a NatSemi chip. Check the PCI vendor and device 790 * IDs against our list and return a device name if we find a match. 791 */ 792 static int 793 nge_probe(dev) 794 device_t dev; 795 { 796 struct nge_type *t; 797 798 t = nge_devs; 799 800 while(t->nge_name != NULL) { 801 if ((pci_get_vendor(dev) == t->nge_vid) && 802 (pci_get_device(dev) == t->nge_did)) { 803 device_set_desc(dev, t->nge_name); 804 return(0); 805 } 806 t++; 807 } 808 809 return(ENXIO); 810 } 811 812 /* 813 * Attach the interface. Allocate softc structures, do ifmedia 814 * setup and ethernet/BPF attach. 815 */ 816 static int 817 nge_attach(dev) 818 device_t dev; 819 { 820 int s; 821 u_char eaddr[ETHER_ADDR_LEN]; 822 struct nge_softc *sc; 823 struct ifnet *ifp; 824 int unit, error = 0, rid; 825 const char *sep = ""; 826 827 s = splimp(); 828 829 sc = device_get_softc(dev); 830 unit = device_get_unit(dev); 831 bzero(sc, sizeof(struct nge_softc)); 832 833 mtx_init(&sc->nge_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 834 MTX_DEF | MTX_RECURSE); 835 #ifndef BURN_BRIDGES 836 /* 837 * Handle power management nonsense. 838 */ 839 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 840 u_int32_t iobase, membase, irq; 841 842 /* Save important PCI config data. */ 843 iobase = pci_read_config(dev, NGE_PCI_LOIO, 4); 844 membase = pci_read_config(dev, NGE_PCI_LOMEM, 4); 845 irq = pci_read_config(dev, NGE_PCI_INTLINE, 4); 846 847 /* Reset the power state. */ 848 printf("nge%d: chip is in D%d power mode " 849 "-- setting to D0\n", unit, 850 pci_get_powerstate(dev)); 851 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 852 853 /* Restore PCI config data. */ 854 pci_write_config(dev, NGE_PCI_LOIO, iobase, 4); 855 pci_write_config(dev, NGE_PCI_LOMEM, membase, 4); 856 pci_write_config(dev, NGE_PCI_INTLINE, irq, 4); 857 } 858 #endif 859 /* 860 * Map control/status registers. 861 */ 862 pci_enable_busmaster(dev); 863 864 rid = NGE_RID; 865 sc->nge_res = bus_alloc_resource(dev, NGE_RES, &rid, 866 0, ~0, 1, RF_ACTIVE); 867 868 if (sc->nge_res == NULL) { 869 printf("nge%d: couldn't map ports/memory\n", unit); 870 error = ENXIO; 871 goto fail; 872 } 873 874 sc->nge_btag = rman_get_bustag(sc->nge_res); 875 sc->nge_bhandle = rman_get_bushandle(sc->nge_res); 876 877 /* Allocate interrupt */ 878 rid = 0; 879 sc->nge_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 880 RF_SHAREABLE | RF_ACTIVE); 881 882 if (sc->nge_irq == NULL) { 883 printf("nge%d: couldn't map interrupt\n", unit); 884 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res); 885 error = ENXIO; 886 goto fail; 887 } 888 889 error = bus_setup_intr(dev, sc->nge_irq, INTR_TYPE_NET, 890 nge_intr, sc, &sc->nge_intrhand); 891 892 if (error) { 893 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq); 894 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res); 895 printf("nge%d: couldn't set up irq\n", unit); 896 goto fail; 897 } 898 899 /* Reset the adapter. */ 900 nge_reset(sc); 901 902 /* 903 * Get station address from the EEPROM. 904 */ 905 nge_read_eeprom(sc, (caddr_t)&eaddr[4], NGE_EE_NODEADDR, 1, 0); 906 nge_read_eeprom(sc, (caddr_t)&eaddr[2], NGE_EE_NODEADDR + 1, 1, 0); 907 nge_read_eeprom(sc, (caddr_t)&eaddr[0], NGE_EE_NODEADDR + 2, 1, 0); 908 909 /* 910 * A NatSemi chip was detected. Inform the world. 911 */ 912 printf("nge%d: Ethernet address: %6D\n", unit, eaddr, ":"); 913 914 sc->nge_unit = unit; 915 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 916 917 sc->nge_ldata = contigmalloc(sizeof(struct nge_list_data), M_DEVBUF, 918 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 919 920 if (sc->nge_ldata == NULL) { 921 printf("nge%d: no memory for list buffers!\n", unit); 922 bus_teardown_intr(dev, sc->nge_irq, sc->nge_intrhand); 923 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq); 924 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res); 925 error = ENXIO; 926 goto fail; 927 } 928 bzero(sc->nge_ldata, sizeof(struct nge_list_data)); 929 930 /* Try to allocate memory for jumbo buffers. */ 931 if (nge_alloc_jumbo_mem(sc)) { 932 printf("nge%d: jumbo buffer allocation failed\n", 933 sc->nge_unit); 934 contigfree(sc->nge_ldata, 935 sizeof(struct nge_list_data), M_DEVBUF); 936 bus_teardown_intr(dev, sc->nge_irq, sc->nge_intrhand); 937 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq); 938 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res); 939 error = ENXIO; 940 goto fail; 941 } 942 943 ifp = &sc->arpcom.ac_if; 944 ifp->if_softc = sc; 945 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 946 ifp->if_mtu = ETHERMTU; 947 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 948 ifp->if_ioctl = nge_ioctl; 949 ifp->if_output = ether_output; 950 ifp->if_start = nge_start; 951 ifp->if_watchdog = nge_watchdog; 952 ifp->if_init = nge_init; 953 ifp->if_baudrate = 1000000000; 954 ifp->if_snd.ifq_maxlen = NGE_TX_LIST_CNT - 1; 955 ifp->if_hwassist = NGE_CSUM_FEATURES; 956 ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING; 957 ifp->if_capenable = ifp->if_capabilities; 958 959 /* 960 * Do MII setup. 961 */ 962 if (mii_phy_probe(dev, &sc->nge_miibus, 963 nge_ifmedia_upd, nge_ifmedia_sts)) { 964 if (CSR_READ_4(sc, NGE_CFG) & NGE_CFG_TBI_EN) { 965 sc->nge_tbi = 1; 966 device_printf(dev, "Using TBI\n"); 967 968 sc->nge_miibus = dev; 969 970 ifmedia_init(&sc->nge_ifmedia, 0, nge_ifmedia_upd, 971 nge_ifmedia_sts); 972 #define ADD(m, c) ifmedia_add(&sc->nge_ifmedia, (m), (c), NULL) 973 #define PRINT(s) printf("%s%s", sep, s); sep = ", " 974 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, 0), 0); 975 device_printf(dev, " "); 976 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_SX, 0, 0), 0); 977 PRINT("1000baseSX"); 978 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_SX, IFM_FDX, 0),0); 979 PRINT("1000baseSX-FDX"); 980 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, 0), 0); 981 PRINT("auto"); 982 983 printf("\n"); 984 #undef ADD 985 #undef PRINT 986 ifmedia_set(&sc->nge_ifmedia, 987 IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, 0)); 988 989 CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO) 990 | NGE_GPIO_GP4_OUT 991 | NGE_GPIO_GP1_OUTENB | NGE_GPIO_GP2_OUTENB 992 | NGE_GPIO_GP3_OUTENB 993 | NGE_GPIO_GP3_IN | NGE_GPIO_GP4_IN); 994 995 } else { 996 printf("nge%d: MII without any PHY!\n", sc->nge_unit); 997 nge_free_jumbo_mem(sc); 998 bus_teardown_intr(dev, sc->nge_irq, sc->nge_intrhand); 999 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq); 1000 bus_release_resource(dev, NGE_RES, NGE_RID, 1001 sc->nge_res); 1002 error = ENXIO; 1003 goto fail; 1004 } 1005 } 1006 1007 /* 1008 * Call MI attach routine. 1009 */ 1010 ether_ifattach(ifp, eaddr); 1011 callout_handle_init(&sc->nge_stat_ch); 1012 1013 fail: 1014 1015 splx(s); 1016 mtx_destroy(&sc->nge_mtx); 1017 return(error); 1018 } 1019 1020 static int 1021 nge_detach(dev) 1022 device_t dev; 1023 { 1024 struct nge_softc *sc; 1025 struct ifnet *ifp; 1026 int s; 1027 1028 s = splimp(); 1029 1030 sc = device_get_softc(dev); 1031 ifp = &sc->arpcom.ac_if; 1032 1033 nge_reset(sc); 1034 nge_stop(sc); 1035 ether_ifdetach(ifp); 1036 1037 bus_generic_detach(dev); 1038 if (!sc->nge_tbi) { 1039 device_delete_child(dev, sc->nge_miibus); 1040 } 1041 bus_teardown_intr(dev, sc->nge_irq, sc->nge_intrhand); 1042 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq); 1043 bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res); 1044 1045 contigfree(sc->nge_ldata, sizeof(struct nge_list_data), M_DEVBUF); 1046 nge_free_jumbo_mem(sc); 1047 1048 splx(s); 1049 mtx_destroy(&sc->nge_mtx); 1050 1051 return(0); 1052 } 1053 1054 /* 1055 * Initialize the transmit descriptors. 1056 */ 1057 static int 1058 nge_list_tx_init(sc) 1059 struct nge_softc *sc; 1060 { 1061 struct nge_list_data *ld; 1062 struct nge_ring_data *cd; 1063 int i; 1064 1065 cd = &sc->nge_cdata; 1066 ld = sc->nge_ldata; 1067 1068 for (i = 0; i < NGE_TX_LIST_CNT; i++) { 1069 if (i == (NGE_TX_LIST_CNT - 1)) { 1070 ld->nge_tx_list[i].nge_nextdesc = 1071 &ld->nge_tx_list[0]; 1072 ld->nge_tx_list[i].nge_next = 1073 vtophys(&ld->nge_tx_list[0]); 1074 } else { 1075 ld->nge_tx_list[i].nge_nextdesc = 1076 &ld->nge_tx_list[i + 1]; 1077 ld->nge_tx_list[i].nge_next = 1078 vtophys(&ld->nge_tx_list[i + 1]); 1079 } 1080 ld->nge_tx_list[i].nge_mbuf = NULL; 1081 ld->nge_tx_list[i].nge_ptr = 0; 1082 ld->nge_tx_list[i].nge_ctl = 0; 1083 } 1084 1085 cd->nge_tx_prod = cd->nge_tx_cons = cd->nge_tx_cnt = 0; 1086 1087 return(0); 1088 } 1089 1090 1091 /* 1092 * Initialize the RX descriptors and allocate mbufs for them. Note that 1093 * we arrange the descriptors in a closed ring, so that the last descriptor 1094 * points back to the first. 1095 */ 1096 static int 1097 nge_list_rx_init(sc) 1098 struct nge_softc *sc; 1099 { 1100 struct nge_list_data *ld; 1101 struct nge_ring_data *cd; 1102 int i; 1103 1104 ld = sc->nge_ldata; 1105 cd = &sc->nge_cdata; 1106 1107 for (i = 0; i < NGE_RX_LIST_CNT; i++) { 1108 if (nge_newbuf(sc, &ld->nge_rx_list[i], NULL) == ENOBUFS) 1109 return(ENOBUFS); 1110 if (i == (NGE_RX_LIST_CNT - 1)) { 1111 ld->nge_rx_list[i].nge_nextdesc = 1112 &ld->nge_rx_list[0]; 1113 ld->nge_rx_list[i].nge_next = 1114 vtophys(&ld->nge_rx_list[0]); 1115 } else { 1116 ld->nge_rx_list[i].nge_nextdesc = 1117 &ld->nge_rx_list[i + 1]; 1118 ld->nge_rx_list[i].nge_next = 1119 vtophys(&ld->nge_rx_list[i + 1]); 1120 } 1121 } 1122 1123 cd->nge_rx_prod = 0; 1124 1125 return(0); 1126 } 1127 1128 /* 1129 * Initialize an RX descriptor and attach an MBUF cluster. 1130 */ 1131 static int 1132 nge_newbuf(sc, c, m) 1133 struct nge_softc *sc; 1134 struct nge_desc *c; 1135 struct mbuf *m; 1136 { 1137 struct mbuf *m_new = NULL; 1138 caddr_t *buf = NULL; 1139 1140 if (m == NULL) { 1141 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1142 if (m_new == NULL) { 1143 printf("nge%d: no memory for rx list " 1144 "-- packet dropped!\n", sc->nge_unit); 1145 return(ENOBUFS); 1146 } 1147 1148 /* Allocate the jumbo buffer */ 1149 buf = nge_jalloc(sc); 1150 if (buf == NULL) { 1151 #ifdef NGE_VERBOSE 1152 printf("nge%d: jumbo allocation failed " 1153 "-- packet dropped!\n", sc->nge_unit); 1154 #endif 1155 m_freem(m_new); 1156 return(ENOBUFS); 1157 } 1158 /* Attach the buffer to the mbuf */ 1159 m_new->m_data = (void *)buf; 1160 m_new->m_len = m_new->m_pkthdr.len = NGE_JUMBO_FRAMELEN; 1161 MEXTADD(m_new, buf, NGE_JUMBO_FRAMELEN, nge_jfree, 1162 (struct nge_softc *)sc, 0, EXT_NET_DRV); 1163 } else { 1164 m_new = m; 1165 m_new->m_len = m_new->m_pkthdr.len = NGE_JUMBO_FRAMELEN; 1166 m_new->m_data = m_new->m_ext.ext_buf; 1167 } 1168 1169 m_adj(m_new, sizeof(u_int64_t)); 1170 1171 c->nge_mbuf = m_new; 1172 c->nge_ptr = vtophys(mtod(m_new, caddr_t)); 1173 c->nge_ctl = m_new->m_len; 1174 c->nge_extsts = 0; 1175 1176 return(0); 1177 } 1178 1179 static int 1180 nge_alloc_jumbo_mem(sc) 1181 struct nge_softc *sc; 1182 { 1183 caddr_t ptr; 1184 register int i; 1185 struct nge_jpool_entry *entry; 1186 1187 /* Grab a big chunk o' storage. */ 1188 sc->nge_cdata.nge_jumbo_buf = contigmalloc(NGE_JMEM, M_DEVBUF, 1189 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1190 1191 if (sc->nge_cdata.nge_jumbo_buf == NULL) { 1192 printf("nge%d: no memory for jumbo buffers!\n", sc->nge_unit); 1193 return(ENOBUFS); 1194 } 1195 1196 SLIST_INIT(&sc->nge_jfree_listhead); 1197 SLIST_INIT(&sc->nge_jinuse_listhead); 1198 1199 /* 1200 * Now divide it up into 9K pieces and save the addresses 1201 * in an array. 1202 */ 1203 ptr = sc->nge_cdata.nge_jumbo_buf; 1204 for (i = 0; i < NGE_JSLOTS; i++) { 1205 sc->nge_cdata.nge_jslots[i] = ptr; 1206 ptr += NGE_JLEN; 1207 entry = malloc(sizeof(struct nge_jpool_entry), 1208 M_DEVBUF, M_NOWAIT); 1209 if (entry == NULL) { 1210 printf("nge%d: no memory for jumbo " 1211 "buffer queue!\n", sc->nge_unit); 1212 return(ENOBUFS); 1213 } 1214 entry->slot = i; 1215 SLIST_INSERT_HEAD(&sc->nge_jfree_listhead, 1216 entry, jpool_entries); 1217 } 1218 1219 return(0); 1220 } 1221 1222 static void 1223 nge_free_jumbo_mem(sc) 1224 struct nge_softc *sc; 1225 { 1226 register int i; 1227 struct nge_jpool_entry *entry; 1228 1229 for (i = 0; i < NGE_JSLOTS; i++) { 1230 entry = SLIST_FIRST(&sc->nge_jfree_listhead); 1231 SLIST_REMOVE_HEAD(&sc->nge_jfree_listhead, jpool_entries); 1232 free(entry, M_DEVBUF); 1233 } 1234 1235 contigfree(sc->nge_cdata.nge_jumbo_buf, NGE_JMEM, M_DEVBUF); 1236 1237 return; 1238 } 1239 1240 /* 1241 * Allocate a jumbo buffer. 1242 */ 1243 static void * 1244 nge_jalloc(sc) 1245 struct nge_softc *sc; 1246 { 1247 struct nge_jpool_entry *entry; 1248 1249 entry = SLIST_FIRST(&sc->nge_jfree_listhead); 1250 1251 if (entry == NULL) { 1252 #ifdef NGE_VERBOSE 1253 printf("nge%d: no free jumbo buffers\n", sc->nge_unit); 1254 #endif 1255 return(NULL); 1256 } 1257 1258 SLIST_REMOVE_HEAD(&sc->nge_jfree_listhead, jpool_entries); 1259 SLIST_INSERT_HEAD(&sc->nge_jinuse_listhead, entry, jpool_entries); 1260 return(sc->nge_cdata.nge_jslots[entry->slot]); 1261 } 1262 1263 /* 1264 * Release a jumbo buffer. 1265 */ 1266 static void 1267 nge_jfree(buf, args) 1268 void *buf; 1269 void *args; 1270 { 1271 struct nge_softc *sc; 1272 int i; 1273 struct nge_jpool_entry *entry; 1274 1275 /* Extract the softc struct pointer. */ 1276 sc = args; 1277 1278 if (sc == NULL) 1279 panic("nge_jfree: can't find softc pointer!"); 1280 1281 /* calculate the slot this buffer belongs to */ 1282 i = ((vm_offset_t)buf 1283 - (vm_offset_t)sc->nge_cdata.nge_jumbo_buf) / NGE_JLEN; 1284 1285 if ((i < 0) || (i >= NGE_JSLOTS)) 1286 panic("nge_jfree: asked to free buffer that we don't manage!"); 1287 1288 entry = SLIST_FIRST(&sc->nge_jinuse_listhead); 1289 if (entry == NULL) 1290 panic("nge_jfree: buffer not in use!"); 1291 entry->slot = i; 1292 SLIST_REMOVE_HEAD(&sc->nge_jinuse_listhead, jpool_entries); 1293 SLIST_INSERT_HEAD(&sc->nge_jfree_listhead, entry, jpool_entries); 1294 1295 return; 1296 } 1297 /* 1298 * A frame has been uploaded: pass the resulting mbuf chain up to 1299 * the higher level protocols. 1300 */ 1301 static void 1302 nge_rxeof(sc) 1303 struct nge_softc *sc; 1304 { 1305 struct mbuf *m; 1306 struct ifnet *ifp; 1307 struct nge_desc *cur_rx; 1308 int i, total_len = 0; 1309 u_int32_t rxstat; 1310 1311 ifp = &sc->arpcom.ac_if; 1312 i = sc->nge_cdata.nge_rx_prod; 1313 1314 while(NGE_OWNDESC(&sc->nge_ldata->nge_rx_list[i])) { 1315 struct mbuf *m0 = NULL; 1316 u_int32_t extsts; 1317 1318 #ifdef DEVICE_POLLING 1319 if (ifp->if_ipending & IFF_POLLING) { 1320 if (sc->rxcycles <= 0) 1321 break; 1322 sc->rxcycles--; 1323 } 1324 #endif /* DEVICE_POLLING */ 1325 1326 cur_rx = &sc->nge_ldata->nge_rx_list[i]; 1327 rxstat = cur_rx->nge_rxstat; 1328 extsts = cur_rx->nge_extsts; 1329 m = cur_rx->nge_mbuf; 1330 cur_rx->nge_mbuf = NULL; 1331 total_len = NGE_RXBYTES(cur_rx); 1332 NGE_INC(i, NGE_RX_LIST_CNT); 1333 /* 1334 * If an error occurs, update stats, clear the 1335 * status word and leave the mbuf cluster in place: 1336 * it should simply get re-used next time this descriptor 1337 * comes up in the ring. 1338 */ 1339 if (!(rxstat & NGE_CMDSTS_PKT_OK)) { 1340 ifp->if_ierrors++; 1341 nge_newbuf(sc, cur_rx, m); 1342 continue; 1343 } 1344 1345 /* 1346 * Ok. NatSemi really screwed up here. This is the 1347 * only gigE chip I know of with alignment constraints 1348 * on receive buffers. RX buffers must be 64-bit aligned. 1349 */ 1350 #ifdef __i386__ 1351 /* 1352 * By popular demand, ignore the alignment problems 1353 * on the Intel x86 platform. The performance hit 1354 * incurred due to unaligned accesses is much smaller 1355 * than the hit produced by forcing buffer copies all 1356 * the time, especially with jumbo frames. We still 1357 * need to fix up the alignment everywhere else though. 1358 */ 1359 if (nge_newbuf(sc, cur_rx, NULL) == ENOBUFS) { 1360 #endif 1361 m0 = m_devget(mtod(m, char *), total_len, 1362 ETHER_ALIGN, ifp, NULL); 1363 nge_newbuf(sc, cur_rx, m); 1364 if (m0 == NULL) { 1365 printf("nge%d: no receive buffers " 1366 "available -- packet dropped!\n", 1367 sc->nge_unit); 1368 ifp->if_ierrors++; 1369 continue; 1370 } 1371 m = m0; 1372 #ifdef __i386__ 1373 } else { 1374 m->m_pkthdr.rcvif = ifp; 1375 m->m_pkthdr.len = m->m_len = total_len; 1376 } 1377 #endif 1378 1379 ifp->if_ipackets++; 1380 1381 /* Do IP checksum checking. */ 1382 if (extsts & NGE_RXEXTSTS_IPPKT) 1383 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1384 if (!(extsts & NGE_RXEXTSTS_IPCSUMERR)) 1385 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1386 if ((extsts & NGE_RXEXTSTS_TCPPKT && 1387 !(extsts & NGE_RXEXTSTS_TCPCSUMERR)) || 1388 (extsts & NGE_RXEXTSTS_UDPPKT && 1389 !(extsts & NGE_RXEXTSTS_UDPCSUMERR))) { 1390 m->m_pkthdr.csum_flags |= 1391 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1392 m->m_pkthdr.csum_data = 0xffff; 1393 } 1394 1395 /* 1396 * If we received a packet with a vlan tag, pass it 1397 * to vlan_input() instead of ether_input(). 1398 */ 1399 if (extsts & NGE_RXEXTSTS_VLANPKT) { 1400 VLAN_INPUT_TAG(ifp, m, 1401 extsts & NGE_RXEXTSTS_VTCI, continue); 1402 } 1403 1404 (*ifp->if_input)(ifp, m); 1405 } 1406 1407 sc->nge_cdata.nge_rx_prod = i; 1408 1409 return; 1410 } 1411 1412 /* 1413 * A frame was downloaded to the chip. It's safe for us to clean up 1414 * the list buffers. 1415 */ 1416 1417 static void 1418 nge_txeof(sc) 1419 struct nge_softc *sc; 1420 { 1421 struct nge_desc *cur_tx = NULL; 1422 struct ifnet *ifp; 1423 u_int32_t idx; 1424 1425 ifp = &sc->arpcom.ac_if; 1426 1427 /* Clear the timeout timer. */ 1428 ifp->if_timer = 0; 1429 1430 /* 1431 * Go through our tx list and free mbufs for those 1432 * frames that have been transmitted. 1433 */ 1434 idx = sc->nge_cdata.nge_tx_cons; 1435 while (idx != sc->nge_cdata.nge_tx_prod) { 1436 cur_tx = &sc->nge_ldata->nge_tx_list[idx]; 1437 1438 if (NGE_OWNDESC(cur_tx)) 1439 break; 1440 1441 if (cur_tx->nge_ctl & NGE_CMDSTS_MORE) { 1442 sc->nge_cdata.nge_tx_cnt--; 1443 NGE_INC(idx, NGE_TX_LIST_CNT); 1444 continue; 1445 } 1446 1447 if (!(cur_tx->nge_ctl & NGE_CMDSTS_PKT_OK)) { 1448 ifp->if_oerrors++; 1449 if (cur_tx->nge_txstat & NGE_TXSTAT_EXCESSCOLLS) 1450 ifp->if_collisions++; 1451 if (cur_tx->nge_txstat & NGE_TXSTAT_OUTOFWINCOLL) 1452 ifp->if_collisions++; 1453 } 1454 1455 ifp->if_collisions += 1456 (cur_tx->nge_txstat & NGE_TXSTAT_COLLCNT) >> 16; 1457 1458 ifp->if_opackets++; 1459 if (cur_tx->nge_mbuf != NULL) { 1460 m_freem(cur_tx->nge_mbuf); 1461 cur_tx->nge_mbuf = NULL; 1462 } 1463 1464 sc->nge_cdata.nge_tx_cnt--; 1465 NGE_INC(idx, NGE_TX_LIST_CNT); 1466 ifp->if_timer = 0; 1467 } 1468 1469 sc->nge_cdata.nge_tx_cons = idx; 1470 1471 if (cur_tx != NULL) 1472 ifp->if_flags &= ~IFF_OACTIVE; 1473 1474 return; 1475 } 1476 1477 static void 1478 nge_tick(xsc) 1479 void *xsc; 1480 { 1481 struct nge_softc *sc; 1482 struct mii_data *mii; 1483 struct ifnet *ifp; 1484 int s; 1485 1486 s = splimp(); 1487 1488 sc = xsc; 1489 ifp = &sc->arpcom.ac_if; 1490 1491 if (sc->nge_tbi) { 1492 if (!sc->nge_link) { 1493 if (CSR_READ_4(sc, NGE_TBI_BMSR) 1494 & NGE_TBIBMSR_ANEG_DONE) { 1495 printf("nge%d: gigabit link up\n", 1496 sc->nge_unit); 1497 nge_miibus_statchg(sc->nge_miibus); 1498 sc->nge_link++; 1499 if (ifp->if_snd.ifq_head != NULL) 1500 nge_start(ifp); 1501 } 1502 } 1503 } else { 1504 mii = device_get_softc(sc->nge_miibus); 1505 mii_tick(mii); 1506 1507 if (!sc->nge_link) { 1508 if (mii->mii_media_status & IFM_ACTIVE && 1509 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1510 sc->nge_link++; 1511 if (IFM_SUBTYPE(mii->mii_media_active) 1512 == IFM_1000_T) 1513 printf("nge%d: gigabit link up\n", 1514 sc->nge_unit); 1515 if (ifp->if_snd.ifq_head != NULL) 1516 nge_start(ifp); 1517 } 1518 } 1519 } 1520 sc->nge_stat_ch = timeout(nge_tick, sc, hz); 1521 1522 splx(s); 1523 1524 return; 1525 } 1526 1527 #ifdef DEVICE_POLLING 1528 static poll_handler_t nge_poll; 1529 1530 static void 1531 nge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1532 { 1533 struct nge_softc *sc = ifp->if_softc; 1534 1535 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 1536 CSR_WRITE_4(sc, NGE_IER, 1); 1537 return; 1538 } 1539 1540 /* 1541 * On the nge, reading the status register also clears it. 1542 * So before returning to intr mode we must make sure that all 1543 * possible pending sources of interrupts have been served. 1544 * In practice this means run to completion the *eof routines, 1545 * and then call the interrupt routine 1546 */ 1547 sc->rxcycles = count; 1548 nge_rxeof(sc); 1549 nge_txeof(sc); 1550 if (ifp->if_snd.ifq_head != NULL) 1551 nge_start(ifp); 1552 1553 if (sc->rxcycles > 0 || cmd == POLL_AND_CHECK_STATUS) { 1554 u_int32_t status; 1555 1556 /* Reading the ISR register clears all interrupts. */ 1557 status = CSR_READ_4(sc, NGE_ISR); 1558 1559 if (status & (NGE_ISR_RX_ERR|NGE_ISR_RX_OFLOW)) 1560 nge_rxeof(sc); 1561 1562 if (status & (NGE_ISR_RX_IDLE)) 1563 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE); 1564 1565 if (status & NGE_ISR_SYSERR) { 1566 nge_reset(sc); 1567 nge_init(sc); 1568 } 1569 } 1570 } 1571 #endif /* DEVICE_POLLING */ 1572 1573 static void 1574 nge_intr(arg) 1575 void *arg; 1576 { 1577 struct nge_softc *sc; 1578 struct ifnet *ifp; 1579 u_int32_t status; 1580 1581 sc = arg; 1582 ifp = &sc->arpcom.ac_if; 1583 1584 #ifdef DEVICE_POLLING 1585 if (ifp->if_ipending & IFF_POLLING) 1586 return; 1587 if (ether_poll_register(nge_poll, ifp)) { /* ok, disable interrupts */ 1588 CSR_WRITE_4(sc, NGE_IER, 0); 1589 nge_poll(ifp, 0, 1); 1590 return; 1591 } 1592 #endif /* DEVICE_POLLING */ 1593 1594 /* Supress unwanted interrupts */ 1595 if (!(ifp->if_flags & IFF_UP)) { 1596 nge_stop(sc); 1597 return; 1598 } 1599 1600 /* Disable interrupts. */ 1601 CSR_WRITE_4(sc, NGE_IER, 0); 1602 1603 /* Data LED on for TBI mode */ 1604 if(sc->nge_tbi) 1605 CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO) 1606 | NGE_GPIO_GP3_OUT); 1607 1608 for (;;) { 1609 /* Reading the ISR register clears all interrupts. */ 1610 status = CSR_READ_4(sc, NGE_ISR); 1611 1612 if ((status & NGE_INTRS) == 0) 1613 break; 1614 1615 if ((status & NGE_ISR_TX_DESC_OK) || 1616 (status & NGE_ISR_TX_ERR) || 1617 (status & NGE_ISR_TX_OK) || 1618 (status & NGE_ISR_TX_IDLE)) 1619 nge_txeof(sc); 1620 1621 if ((status & NGE_ISR_RX_DESC_OK) || 1622 (status & NGE_ISR_RX_ERR) || 1623 (status & NGE_ISR_RX_OFLOW) || 1624 (status & NGE_ISR_RX_FIFO_OFLOW) || 1625 (status & NGE_ISR_RX_IDLE) || 1626 (status & NGE_ISR_RX_OK)) 1627 nge_rxeof(sc); 1628 1629 if ((status & NGE_ISR_RX_IDLE)) 1630 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE); 1631 1632 if (status & NGE_ISR_SYSERR) { 1633 nge_reset(sc); 1634 ifp->if_flags &= ~IFF_RUNNING; 1635 nge_init(sc); 1636 } 1637 1638 #if 0 1639 /* 1640 * XXX: nge_tick() is not ready to be called this way 1641 * it screws up the aneg timeout because mii_tick() is 1642 * only to be called once per second. 1643 */ 1644 if (status & NGE_IMR_PHY_INTR) { 1645 sc->nge_link = 0; 1646 nge_tick(sc); 1647 } 1648 #endif 1649 } 1650 1651 /* Re-enable interrupts. */ 1652 CSR_WRITE_4(sc, NGE_IER, 1); 1653 1654 if (ifp->if_snd.ifq_head != NULL) 1655 nge_start(ifp); 1656 1657 /* Data LED off for TBI mode */ 1658 1659 if(sc->nge_tbi) 1660 CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO) 1661 & ~NGE_GPIO_GP3_OUT); 1662 1663 return; 1664 } 1665 1666 /* 1667 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1668 * pointers to the fragment pointers. 1669 */ 1670 static int 1671 nge_encap(sc, m_head, txidx) 1672 struct nge_softc *sc; 1673 struct mbuf *m_head; 1674 u_int32_t *txidx; 1675 { 1676 struct nge_desc *f = NULL; 1677 struct mbuf *m; 1678 int frag, cur, cnt = 0; 1679 struct m_tag *mtag; 1680 1681 /* 1682 * Start packing the mbufs in this chain into 1683 * the fragment pointers. Stop when we run out 1684 * of fragments or hit the end of the mbuf chain. 1685 */ 1686 m = m_head; 1687 cur = frag = *txidx; 1688 1689 for (m = m_head; m != NULL; m = m->m_next) { 1690 if (m->m_len != 0) { 1691 if ((NGE_TX_LIST_CNT - 1692 (sc->nge_cdata.nge_tx_cnt + cnt)) < 2) 1693 return(ENOBUFS); 1694 f = &sc->nge_ldata->nge_tx_list[frag]; 1695 f->nge_ctl = NGE_CMDSTS_MORE | m->m_len; 1696 f->nge_ptr = vtophys(mtod(m, vm_offset_t)); 1697 if (cnt != 0) 1698 f->nge_ctl |= NGE_CMDSTS_OWN; 1699 cur = frag; 1700 NGE_INC(frag, NGE_TX_LIST_CNT); 1701 cnt++; 1702 } 1703 } 1704 1705 if (m != NULL) 1706 return(ENOBUFS); 1707 1708 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts = 0; 1709 if (m_head->m_pkthdr.csum_flags) { 1710 if (m_head->m_pkthdr.csum_flags & CSUM_IP) 1711 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts |= 1712 NGE_TXEXTSTS_IPCSUM; 1713 if (m_head->m_pkthdr.csum_flags & CSUM_TCP) 1714 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts |= 1715 NGE_TXEXTSTS_TCPCSUM; 1716 if (m_head->m_pkthdr.csum_flags & CSUM_UDP) 1717 sc->nge_ldata->nge_tx_list[*txidx].nge_extsts |= 1718 NGE_TXEXTSTS_UDPCSUM; 1719 } 1720 1721 mtag = VLAN_OUTPUT_TAG(&sc->arpcom.ac_if, m); 1722 if (mtag != NULL) { 1723 sc->nge_ldata->nge_tx_list[cur].nge_extsts |= 1724 (NGE_TXEXTSTS_VLANPKT|VLAN_TAG_VALUE(mtag)); 1725 } 1726 1727 sc->nge_ldata->nge_tx_list[cur].nge_mbuf = m_head; 1728 sc->nge_ldata->nge_tx_list[cur].nge_ctl &= ~NGE_CMDSTS_MORE; 1729 sc->nge_ldata->nge_tx_list[*txidx].nge_ctl |= NGE_CMDSTS_OWN; 1730 sc->nge_cdata.nge_tx_cnt += cnt; 1731 *txidx = frag; 1732 1733 return(0); 1734 } 1735 1736 /* 1737 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1738 * to the mbuf data regions directly in the transmit lists. We also save a 1739 * copy of the pointers since the transmit list fragment pointers are 1740 * physical addresses. 1741 */ 1742 1743 static void 1744 nge_start(ifp) 1745 struct ifnet *ifp; 1746 { 1747 struct nge_softc *sc; 1748 struct mbuf *m_head = NULL; 1749 u_int32_t idx; 1750 1751 sc = ifp->if_softc; 1752 1753 if (!sc->nge_link) 1754 return; 1755 1756 idx = sc->nge_cdata.nge_tx_prod; 1757 1758 if (ifp->if_flags & IFF_OACTIVE) 1759 return; 1760 1761 while(sc->nge_ldata->nge_tx_list[idx].nge_mbuf == NULL) { 1762 IF_DEQUEUE(&ifp->if_snd, m_head); 1763 if (m_head == NULL) 1764 break; 1765 1766 if (nge_encap(sc, m_head, &idx)) { 1767 IF_PREPEND(&ifp->if_snd, m_head); 1768 ifp->if_flags |= IFF_OACTIVE; 1769 break; 1770 } 1771 1772 /* 1773 * If there's a BPF listener, bounce a copy of this frame 1774 * to him. 1775 */ 1776 BPF_MTAP(ifp, m_head); 1777 1778 } 1779 1780 /* Transmit */ 1781 sc->nge_cdata.nge_tx_prod = idx; 1782 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_TX_ENABLE); 1783 1784 /* 1785 * Set a timeout in case the chip goes out to lunch. 1786 */ 1787 ifp->if_timer = 5; 1788 1789 return; 1790 } 1791 1792 static void 1793 nge_init(xsc) 1794 void *xsc; 1795 { 1796 struct nge_softc *sc = xsc; 1797 struct ifnet *ifp = &sc->arpcom.ac_if; 1798 struct mii_data *mii; 1799 int s; 1800 1801 if (ifp->if_flags & IFF_RUNNING) 1802 return; 1803 1804 s = splimp(); 1805 1806 /* 1807 * Cancel pending I/O and free all RX/TX buffers. 1808 */ 1809 nge_stop(sc); 1810 1811 if (sc->nge_tbi) { 1812 mii = NULL; 1813 } else { 1814 mii = device_get_softc(sc->nge_miibus); 1815 } 1816 1817 /* Set MAC address */ 1818 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR0); 1819 CSR_WRITE_4(sc, NGE_RXFILT_DATA, 1820 ((u_int16_t *)sc->arpcom.ac_enaddr)[0]); 1821 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR1); 1822 CSR_WRITE_4(sc, NGE_RXFILT_DATA, 1823 ((u_int16_t *)sc->arpcom.ac_enaddr)[1]); 1824 CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR2); 1825 CSR_WRITE_4(sc, NGE_RXFILT_DATA, 1826 ((u_int16_t *)sc->arpcom.ac_enaddr)[2]); 1827 1828 /* Init circular RX list. */ 1829 if (nge_list_rx_init(sc) == ENOBUFS) { 1830 printf("nge%d: initialization failed: no " 1831 "memory for rx buffers\n", sc->nge_unit); 1832 nge_stop(sc); 1833 (void)splx(s); 1834 return; 1835 } 1836 1837 /* 1838 * Init tx descriptors. 1839 */ 1840 nge_list_tx_init(sc); 1841 1842 /* 1843 * For the NatSemi chip, we have to explicitly enable the 1844 * reception of ARP frames, as well as turn on the 'perfect 1845 * match' filter where we store the station address, otherwise 1846 * we won't receive unicasts meant for this host. 1847 */ 1848 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ARP); 1849 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_PERFECT); 1850 1851 /* If we want promiscuous mode, set the allframes bit. */ 1852 if (ifp->if_flags & IFF_PROMISC) { 1853 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLPHYS); 1854 } else { 1855 NGE_CLRBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLPHYS); 1856 } 1857 1858 /* 1859 * Set the capture broadcast bit to capture broadcast frames. 1860 */ 1861 if (ifp->if_flags & IFF_BROADCAST) { 1862 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_BROAD); 1863 } else { 1864 NGE_CLRBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_BROAD); 1865 } 1866 1867 /* 1868 * Load the multicast filter. 1869 */ 1870 nge_setmulti(sc); 1871 1872 /* Turn the receive filter on */ 1873 NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ENABLE); 1874 1875 /* 1876 * Load the address of the RX and TX lists. 1877 */ 1878 CSR_WRITE_4(sc, NGE_RX_LISTPTR, 1879 vtophys(&sc->nge_ldata->nge_rx_list[0])); 1880 CSR_WRITE_4(sc, NGE_TX_LISTPTR, 1881 vtophys(&sc->nge_ldata->nge_tx_list[0])); 1882 1883 /* Set RX configuration */ 1884 CSR_WRITE_4(sc, NGE_RX_CFG, NGE_RXCFG); 1885 /* 1886 * Enable hardware checksum validation for all IPv4 1887 * packets, do not reject packets with bad checksums. 1888 */ 1889 CSR_WRITE_4(sc, NGE_VLAN_IP_RXCTL, NGE_VIPRXCTL_IPCSUM_ENB); 1890 1891 /* 1892 * Tell the chip to detect and strip VLAN tag info from 1893 * received frames. The tag will be provided in the extsts 1894 * field in the RX descriptors. 1895 */ 1896 NGE_SETBIT(sc, NGE_VLAN_IP_RXCTL, 1897 NGE_VIPRXCTL_TAG_DETECT_ENB|NGE_VIPRXCTL_TAG_STRIP_ENB); 1898 1899 /* Set TX configuration */ 1900 CSR_WRITE_4(sc, NGE_TX_CFG, NGE_TXCFG); 1901 1902 /* 1903 * Enable TX IPv4 checksumming on a per-packet basis. 1904 */ 1905 CSR_WRITE_4(sc, NGE_VLAN_IP_TXCTL, NGE_VIPTXCTL_CSUM_PER_PKT); 1906 1907 /* 1908 * Tell the chip to insert VLAN tags on a per-packet basis as 1909 * dictated by the code in the frame encapsulation routine. 1910 */ 1911 NGE_SETBIT(sc, NGE_VLAN_IP_TXCTL, NGE_VIPTXCTL_TAG_PER_PKT); 1912 1913 /* Set full/half duplex mode. */ 1914 if (sc->nge_tbi) { 1915 if ((sc->nge_ifmedia.ifm_cur->ifm_media & IFM_GMASK) 1916 == IFM_FDX) { 1917 NGE_SETBIT(sc, NGE_TX_CFG, 1918 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 1919 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 1920 } else { 1921 NGE_CLRBIT(sc, NGE_TX_CFG, 1922 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 1923 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 1924 } 1925 } else { 1926 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 1927 NGE_SETBIT(sc, NGE_TX_CFG, 1928 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 1929 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 1930 } else { 1931 NGE_CLRBIT(sc, NGE_TX_CFG, 1932 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 1933 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 1934 } 1935 } 1936 1937 nge_tick(sc); 1938 1939 /* 1940 * Enable the delivery of PHY interrupts based on 1941 * link/speed/duplex status changes. Also enable the 1942 * extsts field in the DMA descriptors (needed for 1943 * TCP/IP checksum offload on transmit). 1944 */ 1945 NGE_SETBIT(sc, NGE_CFG, NGE_CFG_PHYINTR_SPD| 1946 NGE_CFG_PHYINTR_LNK|NGE_CFG_PHYINTR_DUP|NGE_CFG_EXTSTS_ENB); 1947 1948 /* 1949 * Configure interrupt holdoff (moderation). We can 1950 * have the chip delay interrupt delivery for a certain 1951 * period. Units are in 100us, and the max setting 1952 * is 25500us (0xFF x 100us). Default is a 100us holdoff. 1953 */ 1954 CSR_WRITE_4(sc, NGE_IHR, 0x01); 1955 1956 /* 1957 * Enable interrupts. 1958 */ 1959 CSR_WRITE_4(sc, NGE_IMR, NGE_INTRS); 1960 #ifdef DEVICE_POLLING 1961 /* 1962 * ... only enable interrupts if we are not polling, make sure 1963 * they are off otherwise. 1964 */ 1965 if (ifp->if_ipending & IFF_POLLING) 1966 CSR_WRITE_4(sc, NGE_IER, 0); 1967 else 1968 #endif /* DEVICE_POLLING */ 1969 CSR_WRITE_4(sc, NGE_IER, 1); 1970 1971 /* Enable receiver and transmitter. */ 1972 NGE_CLRBIT(sc, NGE_CSR, NGE_CSR_TX_DISABLE|NGE_CSR_RX_DISABLE); 1973 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE); 1974 1975 nge_ifmedia_upd(ifp); 1976 1977 ifp->if_flags |= IFF_RUNNING; 1978 ifp->if_flags &= ~IFF_OACTIVE; 1979 1980 (void)splx(s); 1981 1982 return; 1983 } 1984 1985 /* 1986 * Set media options. 1987 */ 1988 static int 1989 nge_ifmedia_upd(ifp) 1990 struct ifnet *ifp; 1991 { 1992 struct nge_softc *sc; 1993 struct mii_data *mii; 1994 1995 sc = ifp->if_softc; 1996 1997 if (sc->nge_tbi) { 1998 if (IFM_SUBTYPE(sc->nge_ifmedia.ifm_cur->ifm_media) 1999 == IFM_AUTO) { 2000 CSR_WRITE_4(sc, NGE_TBI_ANAR, 2001 CSR_READ_4(sc, NGE_TBI_ANAR) 2002 | NGE_TBIANAR_HDX | NGE_TBIANAR_FDX 2003 | NGE_TBIANAR_PS1 | NGE_TBIANAR_PS2); 2004 CSR_WRITE_4(sc, NGE_TBI_BMCR, NGE_TBIBMCR_ENABLE_ANEG 2005 | NGE_TBIBMCR_RESTART_ANEG); 2006 CSR_WRITE_4(sc, NGE_TBI_BMCR, NGE_TBIBMCR_ENABLE_ANEG); 2007 } else if ((sc->nge_ifmedia.ifm_cur->ifm_media 2008 & IFM_GMASK) == IFM_FDX) { 2009 NGE_SETBIT(sc, NGE_TX_CFG, 2010 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 2011 NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 2012 2013 CSR_WRITE_4(sc, NGE_TBI_ANAR, 0); 2014 CSR_WRITE_4(sc, NGE_TBI_BMCR, 0); 2015 } else { 2016 NGE_CLRBIT(sc, NGE_TX_CFG, 2017 (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR)); 2018 NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX); 2019 2020 CSR_WRITE_4(sc, NGE_TBI_ANAR, 0); 2021 CSR_WRITE_4(sc, NGE_TBI_BMCR, 0); 2022 } 2023 2024 CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO) 2025 & ~NGE_GPIO_GP3_OUT); 2026 } else { 2027 mii = device_get_softc(sc->nge_miibus); 2028 sc->nge_link = 0; 2029 if (mii->mii_instance) { 2030 struct mii_softc *miisc; 2031 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 2032 miisc = LIST_NEXT(miisc, mii_list)) 2033 mii_phy_reset(miisc); 2034 } 2035 mii_mediachg(mii); 2036 } 2037 2038 return(0); 2039 } 2040 2041 /* 2042 * Report current media status. 2043 */ 2044 static void 2045 nge_ifmedia_sts(ifp, ifmr) 2046 struct ifnet *ifp; 2047 struct ifmediareq *ifmr; 2048 { 2049 struct nge_softc *sc; 2050 struct mii_data *mii; 2051 2052 sc = ifp->if_softc; 2053 2054 if (sc->nge_tbi) { 2055 ifmr->ifm_status = IFM_AVALID; 2056 ifmr->ifm_active = IFM_ETHER; 2057 2058 if (CSR_READ_4(sc, NGE_TBI_BMSR) & NGE_TBIBMSR_ANEG_DONE) { 2059 ifmr->ifm_status |= IFM_ACTIVE; 2060 } 2061 if (CSR_READ_4(sc, NGE_TBI_BMCR) & NGE_TBIBMCR_LOOPBACK) 2062 ifmr->ifm_active |= IFM_LOOP; 2063 if (!CSR_READ_4(sc, NGE_TBI_BMSR) & NGE_TBIBMSR_ANEG_DONE) { 2064 ifmr->ifm_active |= IFM_NONE; 2065 ifmr->ifm_status = 0; 2066 return; 2067 } 2068 ifmr->ifm_active |= IFM_1000_SX; 2069 if (IFM_SUBTYPE(sc->nge_ifmedia.ifm_cur->ifm_media) 2070 == IFM_AUTO) { 2071 ifmr->ifm_active |= IFM_AUTO; 2072 if (CSR_READ_4(sc, NGE_TBI_ANLPAR) 2073 & NGE_TBIANAR_FDX) { 2074 ifmr->ifm_active |= IFM_FDX; 2075 }else if (CSR_READ_4(sc, NGE_TBI_ANLPAR) 2076 & NGE_TBIANAR_HDX) { 2077 ifmr->ifm_active |= IFM_HDX; 2078 } 2079 } else if ((sc->nge_ifmedia.ifm_cur->ifm_media & IFM_GMASK) 2080 == IFM_FDX) 2081 ifmr->ifm_active |= IFM_FDX; 2082 else 2083 ifmr->ifm_active |= IFM_HDX; 2084 2085 } else { 2086 mii = device_get_softc(sc->nge_miibus); 2087 mii_pollstat(mii); 2088 ifmr->ifm_active = mii->mii_media_active; 2089 ifmr->ifm_status = mii->mii_media_status; 2090 } 2091 2092 return; 2093 } 2094 2095 static int 2096 nge_ioctl(ifp, command, data) 2097 struct ifnet *ifp; 2098 u_long command; 2099 caddr_t data; 2100 { 2101 struct nge_softc *sc = ifp->if_softc; 2102 struct ifreq *ifr = (struct ifreq *) data; 2103 struct mii_data *mii; 2104 int s, error = 0; 2105 2106 s = splimp(); 2107 2108 switch(command) { 2109 case SIOCSIFMTU: 2110 if (ifr->ifr_mtu > NGE_JUMBO_MTU) 2111 error = EINVAL; 2112 else { 2113 ifp->if_mtu = ifr->ifr_mtu; 2114 /* 2115 * Workaround: if the MTU is larger than 2116 * 8152 (TX FIFO size minus 64 minus 18), turn off 2117 * TX checksum offloading. 2118 */ 2119 if (ifr->ifr_mtu >= 8152) 2120 ifp->if_hwassist = 0; 2121 else 2122 ifp->if_hwassist = NGE_CSUM_FEATURES; 2123 } 2124 break; 2125 case SIOCSIFFLAGS: 2126 if (ifp->if_flags & IFF_UP) { 2127 if (ifp->if_flags & IFF_RUNNING && 2128 ifp->if_flags & IFF_PROMISC && 2129 !(sc->nge_if_flags & IFF_PROMISC)) { 2130 NGE_SETBIT(sc, NGE_RXFILT_CTL, 2131 NGE_RXFILTCTL_ALLPHYS| 2132 NGE_RXFILTCTL_ALLMULTI); 2133 } else if (ifp->if_flags & IFF_RUNNING && 2134 !(ifp->if_flags & IFF_PROMISC) && 2135 sc->nge_if_flags & IFF_PROMISC) { 2136 NGE_CLRBIT(sc, NGE_RXFILT_CTL, 2137 NGE_RXFILTCTL_ALLPHYS); 2138 if (!(ifp->if_flags & IFF_ALLMULTI)) 2139 NGE_CLRBIT(sc, NGE_RXFILT_CTL, 2140 NGE_RXFILTCTL_ALLMULTI); 2141 } else { 2142 ifp->if_flags &= ~IFF_RUNNING; 2143 nge_init(sc); 2144 } 2145 } else { 2146 if (ifp->if_flags & IFF_RUNNING) 2147 nge_stop(sc); 2148 } 2149 sc->nge_if_flags = ifp->if_flags; 2150 error = 0; 2151 break; 2152 case SIOCADDMULTI: 2153 case SIOCDELMULTI: 2154 nge_setmulti(sc); 2155 error = 0; 2156 break; 2157 case SIOCGIFMEDIA: 2158 case SIOCSIFMEDIA: 2159 if (sc->nge_tbi) { 2160 error = ifmedia_ioctl(ifp, ifr, &sc->nge_ifmedia, 2161 command); 2162 } else { 2163 mii = device_get_softc(sc->nge_miibus); 2164 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 2165 command); 2166 } 2167 break; 2168 default: 2169 error = ether_ioctl(ifp, command, data); 2170 break; 2171 } 2172 2173 (void)splx(s); 2174 2175 return(error); 2176 } 2177 2178 static void 2179 nge_watchdog(ifp) 2180 struct ifnet *ifp; 2181 { 2182 struct nge_softc *sc; 2183 2184 sc = ifp->if_softc; 2185 2186 ifp->if_oerrors++; 2187 printf("nge%d: watchdog timeout\n", sc->nge_unit); 2188 2189 nge_stop(sc); 2190 nge_reset(sc); 2191 ifp->if_flags &= ~IFF_RUNNING; 2192 nge_init(sc); 2193 2194 if (ifp->if_snd.ifq_head != NULL) 2195 nge_start(ifp); 2196 2197 return; 2198 } 2199 2200 /* 2201 * Stop the adapter and free any mbufs allocated to the 2202 * RX and TX lists. 2203 */ 2204 static void 2205 nge_stop(sc) 2206 struct nge_softc *sc; 2207 { 2208 register int i; 2209 struct ifnet *ifp; 2210 struct mii_data *mii; 2211 2212 ifp = &sc->arpcom.ac_if; 2213 ifp->if_timer = 0; 2214 if (sc->nge_tbi) { 2215 mii = NULL; 2216 } else { 2217 mii = device_get_softc(sc->nge_miibus); 2218 } 2219 2220 untimeout(nge_tick, sc, sc->nge_stat_ch); 2221 #ifdef DEVICE_POLLING 2222 ether_poll_deregister(ifp); 2223 #endif 2224 CSR_WRITE_4(sc, NGE_IER, 0); 2225 CSR_WRITE_4(sc, NGE_IMR, 0); 2226 NGE_SETBIT(sc, NGE_CSR, NGE_CSR_TX_DISABLE|NGE_CSR_RX_DISABLE); 2227 DELAY(1000); 2228 CSR_WRITE_4(sc, NGE_TX_LISTPTR, 0); 2229 CSR_WRITE_4(sc, NGE_RX_LISTPTR, 0); 2230 2231 if (!sc->nge_tbi) 2232 mii_down(mii); 2233 2234 sc->nge_link = 0; 2235 2236 /* 2237 * Free data in the RX lists. 2238 */ 2239 for (i = 0; i < NGE_RX_LIST_CNT; i++) { 2240 if (sc->nge_ldata->nge_rx_list[i].nge_mbuf != NULL) { 2241 m_freem(sc->nge_ldata->nge_rx_list[i].nge_mbuf); 2242 sc->nge_ldata->nge_rx_list[i].nge_mbuf = NULL; 2243 } 2244 } 2245 bzero((char *)&sc->nge_ldata->nge_rx_list, 2246 sizeof(sc->nge_ldata->nge_rx_list)); 2247 2248 /* 2249 * Free the TX list buffers. 2250 */ 2251 for (i = 0; i < NGE_TX_LIST_CNT; i++) { 2252 if (sc->nge_ldata->nge_tx_list[i].nge_mbuf != NULL) { 2253 m_freem(sc->nge_ldata->nge_tx_list[i].nge_mbuf); 2254 sc->nge_ldata->nge_tx_list[i].nge_mbuf = NULL; 2255 } 2256 } 2257 2258 bzero((char *)&sc->nge_ldata->nge_tx_list, 2259 sizeof(sc->nge_ldata->nge_tx_list)); 2260 2261 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2262 2263 return; 2264 } 2265 2266 /* 2267 * Stop all chip I/O so that the kernel's probe routines don't 2268 * get confused by errant DMAs when rebooting. 2269 */ 2270 static void 2271 nge_shutdown(dev) 2272 device_t dev; 2273 { 2274 struct nge_softc *sc; 2275 2276 sc = device_get_softc(dev); 2277 2278 nge_reset(sc); 2279 nge_stop(sc); 2280 2281 return; 2282 } 2283