xref: /freebsd/sys/dev/nge/if_nge.c (revision 1e413cf93298b5b97441a21d9a50fdcd0ee9945e)
1 /*-
2  * Copyright (c) 2001 Wind River Systems
3  * Copyright (c) 1997, 1998, 1999, 2000, 2001
4  *	Bill Paul <wpaul@bsdi.com>.  All rights reserved.
5  *
6  * Redistribution and use in source and binary forms, with or without
7  * modification, are permitted provided that the following conditions
8  * are met:
9  * 1. Redistributions of source code must retain the above copyright
10  *    notice, this list of conditions and the following disclaimer.
11  * 2. Redistributions in binary form must reproduce the above copyright
12  *    notice, this list of conditions and the following disclaimer in the
13  *    documentation and/or other materials provided with the distribution.
14  * 3. All advertising materials mentioning features or use of this software
15  *    must display the following acknowledgement:
16  *	This product includes software developed by Bill Paul.
17  * 4. Neither the name of the author nor the names of any co-contributors
18  *    may be used to endorse or promote products derived from this software
19  *    without specific prior written permission.
20  *
21  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
22  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
25  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31  * THE POSSIBILITY OF SUCH DAMAGE.
32  */
33 
34 #include <sys/cdefs.h>
35 __FBSDID("$FreeBSD$");
36 
37 /*
38  * National Semiconductor DP83820/DP83821 gigabit ethernet driver
39  * for FreeBSD. Datasheets are available from:
40  *
41  * http://www.national.com/ds/DP/DP83820.pdf
42  * http://www.national.com/ds/DP/DP83821.pdf
43  *
44  * These chips are used on several low cost gigabit ethernet NICs
45  * sold by D-Link, Addtron, SMC and Asante. Both parts are
46  * virtually the same, except the 83820 is a 64-bit/32-bit part,
47  * while the 83821 is 32-bit only.
48  *
49  * Many cards also use National gigE transceivers, such as the
50  * DP83891, DP83861 and DP83862 gigPHYTER parts. The DP83861 datasheet
51  * contains a full register description that applies to all of these
52  * components:
53  *
54  * http://www.national.com/ds/DP/DP83861.pdf
55  *
56  * Written by Bill Paul <wpaul@bsdi.com>
57  * BSDi Open Source Solutions
58  */
59 
60 /*
61  * The NatSemi DP83820 and 83821 controllers are enhanced versions
62  * of the NatSemi MacPHYTER 10/100 devices. They support 10, 100
63  * and 1000Mbps speeds with 1000baseX (ten bit interface), MII and GMII
64  * ports. Other features include 8K TX FIFO and 32K RX FIFO, TCP/IP
65  * hardware checksum offload (IPv4 only), VLAN tagging and filtering,
66  * priority TX and RX queues, a 2048 bit multicast hash filter, 4 RX pattern
67  * matching buffers, one perfect address filter buffer and interrupt
68  * moderation. The 83820 supports both 64-bit and 32-bit addressing
69  * and data transfers: the 64-bit support can be toggled on or off
70  * via software. This affects the size of certain fields in the DMA
71  * descriptors.
72  *
73  * There are two bugs/misfeatures in the 83820/83821 that I have
74  * discovered so far:
75  *
76  * - Receive buffers must be aligned on 64-bit boundaries, which means
77  *   you must resort to copying data in order to fix up the payload
78  *   alignment.
79  *
80  * - In order to transmit jumbo frames larger than 8170 bytes, you have
81  *   to turn off transmit checksum offloading, because the chip can't
82  *   compute the checksum on an outgoing frame unless it fits entirely
83  *   within the TX FIFO, which is only 8192 bytes in size. If you have
84  *   TX checksum offload enabled and you transmit attempt to transmit a
85  *   frame larger than 8170 bytes, the transmitter will wedge.
86  *
87  * To work around the latter problem, TX checksum offload is disabled
88  * if the user selects an MTU larger than 8152 (8170 - 18).
89  */
90 
91 #ifdef HAVE_KERNEL_OPTION_HEADERS
92 #include "opt_device_polling.h"
93 #endif
94 
95 #include <sys/param.h>
96 #include <sys/systm.h>
97 #include <sys/sockio.h>
98 #include <sys/mbuf.h>
99 #include <sys/malloc.h>
100 #include <sys/module.h>
101 #include <sys/kernel.h>
102 #include <sys/socket.h>
103 
104 #include <net/if.h>
105 #include <net/if_arp.h>
106 #include <net/ethernet.h>
107 #include <net/if_dl.h>
108 #include <net/if_media.h>
109 #include <net/if_types.h>
110 #include <net/if_vlan_var.h>
111 
112 #include <net/bpf.h>
113 
114 #include <vm/vm.h>              /* for vtophys */
115 #include <vm/pmap.h>            /* for vtophys */
116 #include <machine/bus.h>
117 #include <machine/resource.h>
118 #include <sys/bus.h>
119 #include <sys/rman.h>
120 
121 #include <dev/mii/mii.h>
122 #include <dev/mii/miivar.h>
123 
124 #include <dev/pci/pcireg.h>
125 #include <dev/pci/pcivar.h>
126 
127 #define NGE_USEIOSPACE
128 
129 #include <dev/nge/if_ngereg.h>
130 
131 MODULE_DEPEND(nge, pci, 1, 1, 1);
132 MODULE_DEPEND(nge, ether, 1, 1, 1);
133 MODULE_DEPEND(nge, miibus, 1, 1, 1);
134 
135 /* "device miibus" required.  See GENERIC if you get errors here. */
136 #include "miibus_if.h"
137 
138 #define NGE_CSUM_FEATURES	(CSUM_IP | CSUM_TCP | CSUM_UDP)
139 
140 /*
141  * Various supported device vendors/types and their names.
142  */
143 static struct nge_type nge_devs[] = {
144 	{ NGE_VENDORID, NGE_DEVICEID,
145 	    "National Semiconductor Gigabit Ethernet" },
146 	{ 0, 0, NULL }
147 };
148 
149 static int nge_probe(device_t);
150 static int nge_attach(device_t);
151 static int nge_detach(device_t);
152 
153 static int nge_newbuf(struct nge_softc *, struct nge_desc *, struct mbuf *);
154 static int nge_encap(struct nge_softc *, struct mbuf *, u_int32_t *);
155 #ifdef NGE_FIXUP_RX
156 static __inline void nge_fixup_rx (struct mbuf *);
157 #endif
158 static void nge_rxeof(struct nge_softc *);
159 static void nge_txeof(struct nge_softc *);
160 static void nge_intr(void *);
161 static void nge_tick(void *);
162 static void nge_start(struct ifnet *);
163 static void nge_start_locked(struct ifnet *);
164 static int nge_ioctl(struct ifnet *, u_long, caddr_t);
165 static void nge_init(void *);
166 static void nge_init_locked(struct nge_softc *);
167 static void nge_stop(struct nge_softc *);
168 static void nge_watchdog(struct ifnet *);
169 static int nge_shutdown(device_t);
170 static int nge_ifmedia_upd(struct ifnet *);
171 static void nge_ifmedia_upd_locked(struct ifnet *);
172 static void nge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
173 
174 static void nge_delay(struct nge_softc *);
175 static void nge_eeprom_idle(struct nge_softc *);
176 static void nge_eeprom_putbyte(struct nge_softc *, int);
177 static void nge_eeprom_getword(struct nge_softc *, int, u_int16_t *);
178 static void nge_read_eeprom(struct nge_softc *, caddr_t, int, int, int);
179 
180 static void nge_mii_sync(struct nge_softc *);
181 static void nge_mii_send(struct nge_softc *, u_int32_t, int);
182 static int nge_mii_readreg(struct nge_softc *, struct nge_mii_frame *);
183 static int nge_mii_writereg(struct nge_softc *, struct nge_mii_frame *);
184 
185 static int nge_miibus_readreg(device_t, int, int);
186 static int nge_miibus_writereg(device_t, int, int, int);
187 static void nge_miibus_statchg(device_t);
188 
189 static void nge_setmulti(struct nge_softc *);
190 static void nge_reset(struct nge_softc *);
191 static int nge_list_rx_init(struct nge_softc *);
192 static int nge_list_tx_init(struct nge_softc *);
193 
194 #ifdef NGE_USEIOSPACE
195 #define NGE_RES			SYS_RES_IOPORT
196 #define NGE_RID			NGE_PCI_LOIO
197 #else
198 #define NGE_RES			SYS_RES_MEMORY
199 #define NGE_RID			NGE_PCI_LOMEM
200 #endif
201 
202 static device_method_t nge_methods[] = {
203 	/* Device interface */
204 	DEVMETHOD(device_probe,		nge_probe),
205 	DEVMETHOD(device_attach,	nge_attach),
206 	DEVMETHOD(device_detach,	nge_detach),
207 	DEVMETHOD(device_shutdown,	nge_shutdown),
208 
209 	/* bus interface */
210 	DEVMETHOD(bus_print_child,	bus_generic_print_child),
211 	DEVMETHOD(bus_driver_added,	bus_generic_driver_added),
212 
213 	/* MII interface */
214 	DEVMETHOD(miibus_readreg,	nge_miibus_readreg),
215 	DEVMETHOD(miibus_writereg,	nge_miibus_writereg),
216 	DEVMETHOD(miibus_statchg,	nge_miibus_statchg),
217 
218 	{ 0, 0 }
219 };
220 
221 static driver_t nge_driver = {
222 	"nge",
223 	nge_methods,
224 	sizeof(struct nge_softc)
225 };
226 
227 static devclass_t nge_devclass;
228 
229 DRIVER_MODULE(nge, pci, nge_driver, nge_devclass, 0, 0);
230 DRIVER_MODULE(miibus, nge, miibus_driver, miibus_devclass, 0, 0);
231 
232 #define NGE_SETBIT(sc, reg, x)				\
233 	CSR_WRITE_4(sc, reg,				\
234 		CSR_READ_4(sc, reg) | (x))
235 
236 #define NGE_CLRBIT(sc, reg, x)				\
237 	CSR_WRITE_4(sc, reg,				\
238 		CSR_READ_4(sc, reg) & ~(x))
239 
240 #define SIO_SET(x)					\
241 	CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) | (x))
242 
243 #define SIO_CLR(x)					\
244 	CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) & ~(x))
245 
246 static void
247 nge_delay(sc)
248 	struct nge_softc	*sc;
249 {
250 	int			idx;
251 
252 	for (idx = (300 / 33) + 1; idx > 0; idx--)
253 		CSR_READ_4(sc, NGE_CSR);
254 
255 	return;
256 }
257 
258 static void
259 nge_eeprom_idle(sc)
260 	struct nge_softc	*sc;
261 {
262 	register int		i;
263 
264 	SIO_SET(NGE_MEAR_EE_CSEL);
265 	nge_delay(sc);
266 	SIO_SET(NGE_MEAR_EE_CLK);
267 	nge_delay(sc);
268 
269 	for (i = 0; i < 25; i++) {
270 		SIO_CLR(NGE_MEAR_EE_CLK);
271 		nge_delay(sc);
272 		SIO_SET(NGE_MEAR_EE_CLK);
273 		nge_delay(sc);
274 	}
275 
276 	SIO_CLR(NGE_MEAR_EE_CLK);
277 	nge_delay(sc);
278 	SIO_CLR(NGE_MEAR_EE_CSEL);
279 	nge_delay(sc);
280 	CSR_WRITE_4(sc, NGE_MEAR, 0x00000000);
281 
282 	return;
283 }
284 
285 /*
286  * Send a read command and address to the EEPROM, check for ACK.
287  */
288 static void
289 nge_eeprom_putbyte(sc, addr)
290 	struct nge_softc	*sc;
291 	int			addr;
292 {
293 	register int		d, i;
294 
295 	d = addr | NGE_EECMD_READ;
296 
297 	/*
298 	 * Feed in each bit and stobe the clock.
299 	 */
300 	for (i = 0x400; i; i >>= 1) {
301 		if (d & i) {
302 			SIO_SET(NGE_MEAR_EE_DIN);
303 		} else {
304 			SIO_CLR(NGE_MEAR_EE_DIN);
305 		}
306 		nge_delay(sc);
307 		SIO_SET(NGE_MEAR_EE_CLK);
308 		nge_delay(sc);
309 		SIO_CLR(NGE_MEAR_EE_CLK);
310 		nge_delay(sc);
311 	}
312 
313 	return;
314 }
315 
316 /*
317  * Read a word of data stored in the EEPROM at address 'addr.'
318  */
319 static void
320 nge_eeprom_getword(sc, addr, dest)
321 	struct nge_softc	*sc;
322 	int			addr;
323 	u_int16_t		*dest;
324 {
325 	register int		i;
326 	u_int16_t		word = 0;
327 
328 	/* Force EEPROM to idle state. */
329 	nge_eeprom_idle(sc);
330 
331 	/* Enter EEPROM access mode. */
332 	nge_delay(sc);
333 	SIO_CLR(NGE_MEAR_EE_CLK);
334 	nge_delay(sc);
335 	SIO_SET(NGE_MEAR_EE_CSEL);
336 	nge_delay(sc);
337 
338 	/*
339 	 * Send address of word we want to read.
340 	 */
341 	nge_eeprom_putbyte(sc, addr);
342 
343 	/*
344 	 * Start reading bits from EEPROM.
345 	 */
346 	for (i = 0x8000; i; i >>= 1) {
347 		SIO_SET(NGE_MEAR_EE_CLK);
348 		nge_delay(sc);
349 		if (CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_EE_DOUT)
350 			word |= i;
351 		nge_delay(sc);
352 		SIO_CLR(NGE_MEAR_EE_CLK);
353 		nge_delay(sc);
354 	}
355 
356 	/* Turn off EEPROM access mode. */
357 	nge_eeprom_idle(sc);
358 
359 	*dest = word;
360 
361 	return;
362 }
363 
364 /*
365  * Read a sequence of words from the EEPROM.
366  */
367 static void
368 nge_read_eeprom(sc, dest, off, cnt, swap)
369 	struct nge_softc	*sc;
370 	caddr_t			dest;
371 	int			off;
372 	int			cnt;
373 	int			swap;
374 {
375 	int			i;
376 	u_int16_t		word = 0, *ptr;
377 
378 	for (i = 0; i < cnt; i++) {
379 		nge_eeprom_getword(sc, off + i, &word);
380 		ptr = (u_int16_t *)(dest + (i * 2));
381 		if (swap)
382 			*ptr = ntohs(word);
383 		else
384 			*ptr = word;
385 	}
386 
387 	return;
388 }
389 
390 /*
391  * Sync the PHYs by setting data bit and strobing the clock 32 times.
392  */
393 static void
394 nge_mii_sync(sc)
395 	struct nge_softc		*sc;
396 {
397 	register int		i;
398 
399 	SIO_SET(NGE_MEAR_MII_DIR|NGE_MEAR_MII_DATA);
400 
401 	for (i = 0; i < 32; i++) {
402 		SIO_SET(NGE_MEAR_MII_CLK);
403 		DELAY(1);
404 		SIO_CLR(NGE_MEAR_MII_CLK);
405 		DELAY(1);
406 	}
407 
408 	return;
409 }
410 
411 /*
412  * Clock a series of bits through the MII.
413  */
414 static void
415 nge_mii_send(sc, bits, cnt)
416 	struct nge_softc		*sc;
417 	u_int32_t		bits;
418 	int			cnt;
419 {
420 	int			i;
421 
422 	SIO_CLR(NGE_MEAR_MII_CLK);
423 
424 	for (i = (0x1 << (cnt - 1)); i; i >>= 1) {
425                 if (bits & i) {
426 			SIO_SET(NGE_MEAR_MII_DATA);
427                 } else {
428 			SIO_CLR(NGE_MEAR_MII_DATA);
429                 }
430 		DELAY(1);
431 		SIO_CLR(NGE_MEAR_MII_CLK);
432 		DELAY(1);
433 		SIO_SET(NGE_MEAR_MII_CLK);
434 	}
435 }
436 
437 /*
438  * Read an PHY register through the MII.
439  */
440 static int
441 nge_mii_readreg(sc, frame)
442 	struct nge_softc		*sc;
443 	struct nge_mii_frame	*frame;
444 
445 {
446 	int			i, ack;
447 
448 	/*
449 	 * Set up frame for RX.
450 	 */
451 	frame->mii_stdelim = NGE_MII_STARTDELIM;
452 	frame->mii_opcode = NGE_MII_READOP;
453 	frame->mii_turnaround = 0;
454 	frame->mii_data = 0;
455 
456 	CSR_WRITE_4(sc, NGE_MEAR, 0);
457 
458 	/*
459  	 * Turn on data xmit.
460 	 */
461 	SIO_SET(NGE_MEAR_MII_DIR);
462 
463 	nge_mii_sync(sc);
464 
465 	/*
466 	 * Send command/address info.
467 	 */
468 	nge_mii_send(sc, frame->mii_stdelim, 2);
469 	nge_mii_send(sc, frame->mii_opcode, 2);
470 	nge_mii_send(sc, frame->mii_phyaddr, 5);
471 	nge_mii_send(sc, frame->mii_regaddr, 5);
472 
473 	/* Idle bit */
474 	SIO_CLR((NGE_MEAR_MII_CLK|NGE_MEAR_MII_DATA));
475 	DELAY(1);
476 	SIO_SET(NGE_MEAR_MII_CLK);
477 	DELAY(1);
478 
479 	/* Turn off xmit. */
480 	SIO_CLR(NGE_MEAR_MII_DIR);
481 	/* Check for ack */
482 	SIO_CLR(NGE_MEAR_MII_CLK);
483 	DELAY(1);
484 	ack = CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_MII_DATA;
485 	SIO_SET(NGE_MEAR_MII_CLK);
486 	DELAY(1);
487 
488 	/*
489 	 * Now try reading data bits. If the ack failed, we still
490 	 * need to clock through 16 cycles to keep the PHY(s) in sync.
491 	 */
492 	if (ack) {
493 		for(i = 0; i < 16; i++) {
494 			SIO_CLR(NGE_MEAR_MII_CLK);
495 			DELAY(1);
496 			SIO_SET(NGE_MEAR_MII_CLK);
497 			DELAY(1);
498 		}
499 		goto fail;
500 	}
501 
502 	for (i = 0x8000; i; i >>= 1) {
503 		SIO_CLR(NGE_MEAR_MII_CLK);
504 		DELAY(1);
505 		if (!ack) {
506 			if (CSR_READ_4(sc, NGE_MEAR) & NGE_MEAR_MII_DATA)
507 				frame->mii_data |= i;
508 			DELAY(1);
509 		}
510 		SIO_SET(NGE_MEAR_MII_CLK);
511 		DELAY(1);
512 	}
513 
514 fail:
515 
516 	SIO_CLR(NGE_MEAR_MII_CLK);
517 	DELAY(1);
518 	SIO_SET(NGE_MEAR_MII_CLK);
519 	DELAY(1);
520 
521 	if (ack)
522 		return(1);
523 	return(0);
524 }
525 
526 /*
527  * Write to a PHY register through the MII.
528  */
529 static int
530 nge_mii_writereg(sc, frame)
531 	struct nge_softc		*sc;
532 	struct nge_mii_frame	*frame;
533 
534 {
535 
536 	/*
537 	 * Set up frame for TX.
538 	 */
539 
540 	frame->mii_stdelim = NGE_MII_STARTDELIM;
541 	frame->mii_opcode = NGE_MII_WRITEOP;
542 	frame->mii_turnaround = NGE_MII_TURNAROUND;
543 
544 	/*
545  	 * Turn on data output.
546 	 */
547 	SIO_SET(NGE_MEAR_MII_DIR);
548 
549 	nge_mii_sync(sc);
550 
551 	nge_mii_send(sc, frame->mii_stdelim, 2);
552 	nge_mii_send(sc, frame->mii_opcode, 2);
553 	nge_mii_send(sc, frame->mii_phyaddr, 5);
554 	nge_mii_send(sc, frame->mii_regaddr, 5);
555 	nge_mii_send(sc, frame->mii_turnaround, 2);
556 	nge_mii_send(sc, frame->mii_data, 16);
557 
558 	/* Idle bit. */
559 	SIO_SET(NGE_MEAR_MII_CLK);
560 	DELAY(1);
561 	SIO_CLR(NGE_MEAR_MII_CLK);
562 	DELAY(1);
563 
564 	/*
565 	 * Turn off xmit.
566 	 */
567 	SIO_CLR(NGE_MEAR_MII_DIR);
568 
569 	return(0);
570 }
571 
572 static int
573 nge_miibus_readreg(dev, phy, reg)
574 	device_t		dev;
575 	int			phy, reg;
576 {
577 	struct nge_softc	*sc;
578 	struct nge_mii_frame	frame;
579 
580 	sc = device_get_softc(dev);
581 
582 	bzero((char *)&frame, sizeof(frame));
583 
584 	frame.mii_phyaddr = phy;
585 	frame.mii_regaddr = reg;
586 	nge_mii_readreg(sc, &frame);
587 
588 	return(frame.mii_data);
589 }
590 
591 static int
592 nge_miibus_writereg(dev, phy, reg, data)
593 	device_t		dev;
594 	int			phy, reg, data;
595 {
596 	struct nge_softc	*sc;
597 	struct nge_mii_frame	frame;
598 
599 	sc = device_get_softc(dev);
600 
601 	bzero((char *)&frame, sizeof(frame));
602 
603 	frame.mii_phyaddr = phy;
604 	frame.mii_regaddr = reg;
605 	frame.mii_data = data;
606 	nge_mii_writereg(sc, &frame);
607 
608 	return(0);
609 }
610 
611 static void
612 nge_miibus_statchg(dev)
613 	device_t		dev;
614 {
615 	int			status;
616 	struct nge_softc	*sc;
617 	struct mii_data		*mii;
618 
619 	sc = device_get_softc(dev);
620 	if (sc->nge_tbi) {
621 		if (IFM_SUBTYPE(sc->nge_ifmedia.ifm_cur->ifm_media)
622 		    == IFM_AUTO) {
623 			status = CSR_READ_4(sc, NGE_TBI_ANLPAR);
624 			if (status == 0 || status & NGE_TBIANAR_FDX) {
625 				NGE_SETBIT(sc, NGE_TX_CFG,
626 				    (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR));
627 				NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
628 			} else {
629 				NGE_CLRBIT(sc, NGE_TX_CFG,
630 				    (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR));
631 				NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
632 			}
633 
634 		} else if ((sc->nge_ifmedia.ifm_cur->ifm_media & IFM_GMASK)
635 			!= IFM_FDX) {
636 			NGE_CLRBIT(sc, NGE_TX_CFG,
637 			    (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR));
638 			NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
639 		} else {
640 			NGE_SETBIT(sc, NGE_TX_CFG,
641 			    (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR));
642 			NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
643 		}
644 	} else {
645 		mii = device_get_softc(sc->nge_miibus);
646 
647 		if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
648 		        NGE_SETBIT(sc, NGE_TX_CFG,
649 			    (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR));
650 			NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
651 		} else {
652 			NGE_CLRBIT(sc, NGE_TX_CFG,
653 			    (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR));
654 			NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
655 		}
656 
657 		/* If we have a 1000Mbps link, set the mode_1000 bit. */
658 		if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
659 		    IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) {
660 			NGE_SETBIT(sc, NGE_CFG, NGE_CFG_MODE_1000);
661 		} else {
662 			NGE_CLRBIT(sc, NGE_CFG, NGE_CFG_MODE_1000);
663 		}
664 	}
665 	return;
666 }
667 
668 static void
669 nge_setmulti(sc)
670 	struct nge_softc	*sc;
671 {
672 	struct ifnet		*ifp;
673 	struct ifmultiaddr	*ifma;
674 	u_int32_t		h = 0, i, filtsave;
675 	int			bit, index;
676 
677 	NGE_LOCK_ASSERT(sc);
678 	ifp = sc->nge_ifp;
679 
680 	if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
681 		NGE_CLRBIT(sc, NGE_RXFILT_CTL,
682 		    NGE_RXFILTCTL_MCHASH|NGE_RXFILTCTL_UCHASH);
683 		NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLMULTI);
684 		return;
685 	}
686 
687 	/*
688 	 * We have to explicitly enable the multicast hash table
689 	 * on the NatSemi chip if we want to use it, which we do.
690 	 * We also have to tell it that we don't want to use the
691 	 * hash table for matching unicast addresses.
692 	 */
693 	NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_MCHASH);
694 	NGE_CLRBIT(sc, NGE_RXFILT_CTL,
695 	    NGE_RXFILTCTL_ALLMULTI|NGE_RXFILTCTL_UCHASH);
696 
697 	filtsave = CSR_READ_4(sc, NGE_RXFILT_CTL);
698 
699 	/* first, zot all the existing hash bits */
700 	for (i = 0; i < NGE_MCAST_FILTER_LEN; i += 2) {
701 		CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_MCAST_LO + i);
702 		CSR_WRITE_4(sc, NGE_RXFILT_DATA, 0);
703 	}
704 
705 	/*
706 	 * From the 11 bits returned by the crc routine, the top 7
707 	 * bits represent the 16-bit word in the mcast hash table
708 	 * that needs to be updated, and the lower 4 bits represent
709 	 * which bit within that byte needs to be set.
710 	 */
711 	IF_ADDR_LOCK(ifp);
712 	TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
713 		if (ifma->ifma_addr->sa_family != AF_LINK)
714 			continue;
715 		h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
716 		    ifma->ifma_addr), ETHER_ADDR_LEN) >> 21;
717 		index = (h >> 4) & 0x7F;
718 		bit = h & 0xF;
719 		CSR_WRITE_4(sc, NGE_RXFILT_CTL,
720 		    NGE_FILTADDR_MCAST_LO + (index * 2));
721 		NGE_SETBIT(sc, NGE_RXFILT_DATA, (1 << bit));
722 	}
723 	IF_ADDR_UNLOCK(ifp);
724 
725 	CSR_WRITE_4(sc, NGE_RXFILT_CTL, filtsave);
726 
727 	return;
728 }
729 
730 static void
731 nge_reset(sc)
732 	struct nge_softc	*sc;
733 {
734 	register int		i;
735 
736 	NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RESET);
737 
738 	for (i = 0; i < NGE_TIMEOUT; i++) {
739 		if (!(CSR_READ_4(sc, NGE_CSR) & NGE_CSR_RESET))
740 			break;
741 	}
742 
743 	if (i == NGE_TIMEOUT)
744 		device_printf(sc->nge_dev, "reset never completed\n");
745 
746 	/* Wait a little while for the chip to get its brains in order. */
747 	DELAY(1000);
748 
749 	/*
750 	 * If this is a NetSemi chip, make sure to clear
751 	 * PME mode.
752 	 */
753 	CSR_WRITE_4(sc, NGE_CLKRUN, NGE_CLKRUN_PMESTS);
754 	CSR_WRITE_4(sc, NGE_CLKRUN, 0);
755 
756         return;
757 }
758 
759 /*
760  * Probe for a NatSemi chip. Check the PCI vendor and device
761  * IDs against our list and return a device name if we find a match.
762  */
763 static int
764 nge_probe(dev)
765 	device_t		dev;
766 {
767 	struct nge_type		*t;
768 
769 	t = nge_devs;
770 
771 	while(t->nge_name != NULL) {
772 		if ((pci_get_vendor(dev) == t->nge_vid) &&
773 		    (pci_get_device(dev) == t->nge_did)) {
774 			device_set_desc(dev, t->nge_name);
775 			return(BUS_PROBE_DEFAULT);
776 		}
777 		t++;
778 	}
779 
780 	return(ENXIO);
781 }
782 
783 /*
784  * Attach the interface. Allocate softc structures, do ifmedia
785  * setup and ethernet/BPF attach.
786  */
787 static int
788 nge_attach(dev)
789 	device_t		dev;
790 {
791 	u_char			eaddr[ETHER_ADDR_LEN];
792 	struct nge_softc	*sc;
793 	struct ifnet		*ifp = NULL;
794 	int			error = 0, rid;
795 
796 	sc = device_get_softc(dev);
797 	sc->nge_dev = dev;
798 
799 	NGE_LOCK_INIT(sc, device_get_nameunit(dev));
800 	callout_init_mtx(&sc->nge_stat_ch, &sc->nge_mtx, 0);
801 
802 	/*
803 	 * Map control/status registers.
804 	 */
805 	pci_enable_busmaster(dev);
806 
807 	rid = NGE_RID;
808 	sc->nge_res = bus_alloc_resource_any(dev, NGE_RES, &rid, RF_ACTIVE);
809 
810 	if (sc->nge_res == NULL) {
811 		device_printf(dev, "couldn't map ports/memory\n");
812 		error = ENXIO;
813 		goto fail;
814 	}
815 
816 	sc->nge_btag = rman_get_bustag(sc->nge_res);
817 	sc->nge_bhandle = rman_get_bushandle(sc->nge_res);
818 
819 	/* Allocate interrupt */
820 	rid = 0;
821 	sc->nge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
822 	    RF_SHAREABLE | RF_ACTIVE);
823 
824 	if (sc->nge_irq == NULL) {
825 		device_printf(dev, "couldn't map interrupt\n");
826 		error = ENXIO;
827 		goto fail;
828 	}
829 
830 	/* Reset the adapter. */
831 	nge_reset(sc);
832 
833 	/*
834 	 * Get station address from the EEPROM.
835 	 */
836 	nge_read_eeprom(sc, (caddr_t)&eaddr[4], NGE_EE_NODEADDR, 1, 0);
837 	nge_read_eeprom(sc, (caddr_t)&eaddr[2], NGE_EE_NODEADDR + 1, 1, 0);
838 	nge_read_eeprom(sc, (caddr_t)&eaddr[0], NGE_EE_NODEADDR + 2, 1, 0);
839 
840 	sc->nge_ldata = contigmalloc(sizeof(struct nge_list_data), M_DEVBUF,
841 	    M_NOWAIT|M_ZERO, 0, 0xffffffff, PAGE_SIZE, 0);
842 
843 	if (sc->nge_ldata == NULL) {
844 		device_printf(dev, "no memory for list buffers!\n");
845 		error = ENXIO;
846 		goto fail;
847 	}
848 
849 	ifp = sc->nge_ifp = if_alloc(IFT_ETHER);
850 	if (ifp == NULL) {
851 		device_printf(dev, "can not if_alloc()\n");
852 		error = ENOSPC;
853 		goto fail;
854 	}
855 	ifp->if_softc = sc;
856 	if_initname(ifp, device_get_name(dev), device_get_unit(dev));
857 	ifp->if_mtu = ETHERMTU;
858 	ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
859 	ifp->if_ioctl = nge_ioctl;
860 	ifp->if_start = nge_start;
861 	ifp->if_watchdog = nge_watchdog;
862 	ifp->if_init = nge_init;
863 	ifp->if_snd.ifq_maxlen = NGE_TX_LIST_CNT - 1;
864 	ifp->if_hwassist = NGE_CSUM_FEATURES;
865 	ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING;
866 	ifp->if_capenable = ifp->if_capabilities;
867 #ifdef DEVICE_POLLING
868 	ifp->if_capabilities |= IFCAP_POLLING;
869 #endif
870 
871 	/*
872 	 * Do MII setup.
873 	 */
874 	/* XXX: leaked on error */
875 	if (mii_phy_probe(dev, &sc->nge_miibus,
876 			  nge_ifmedia_upd, nge_ifmedia_sts)) {
877 		if (CSR_READ_4(sc, NGE_CFG) & NGE_CFG_TBI_EN) {
878 			sc->nge_tbi = 1;
879 			device_printf(dev, "Using TBI\n");
880 
881 			sc->nge_miibus = dev;
882 
883 			ifmedia_init(&sc->nge_ifmedia, 0, nge_ifmedia_upd,
884 				nge_ifmedia_sts);
885 #define	ADD(m, c)	ifmedia_add(&sc->nge_ifmedia, (m), (c), NULL)
886 			ADD(IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, 0), 0);
887 			ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_SX, 0, 0), 0);
888 			ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_SX, IFM_FDX, 0),0);
889 			ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, 0), 0);
890 #undef ADD
891 			device_printf(dev, " 1000baseSX, 1000baseSX-FDX, auto\n");
892 
893 			ifmedia_set(&sc->nge_ifmedia,
894 				IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, 0));
895 
896 			CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO)
897 				| NGE_GPIO_GP4_OUT
898 				| NGE_GPIO_GP1_OUTENB | NGE_GPIO_GP2_OUTENB
899 				| NGE_GPIO_GP3_OUTENB
900 				| NGE_GPIO_GP3_IN | NGE_GPIO_GP4_IN);
901 
902 		} else {
903 			device_printf(dev, "MII without any PHY!\n");
904 			error = ENXIO;
905 			goto fail;
906 		}
907 	}
908 
909 	/*
910 	 * Call MI attach routine.
911 	 */
912 	ether_ifattach(ifp, eaddr);
913 
914 	/*
915 	 * Hookup IRQ last.
916 	 */
917 	error = bus_setup_intr(dev, sc->nge_irq, INTR_TYPE_NET | INTR_MPSAFE,
918 	    NULL, nge_intr, sc, &sc->nge_intrhand);
919 	if (error) {
920 		device_printf(dev, "couldn't set up irq\n");
921 		goto fail;
922 	}
923 
924 	return (0);
925 
926 fail:
927 	if (sc->nge_ldata)
928 		contigfree(sc->nge_ldata,
929 		  sizeof(struct nge_list_data), M_DEVBUF);
930 	if (ifp)
931 		if_free(ifp);
932 	if (sc->nge_irq)
933 		bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq);
934 	if (sc->nge_res)
935 		bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res);
936 	NGE_LOCK_DESTROY(sc);
937 	return(error);
938 }
939 
940 static int
941 nge_detach(dev)
942 	device_t		dev;
943 {
944 	struct nge_softc	*sc;
945 	struct ifnet		*ifp;
946 
947 	sc = device_get_softc(dev);
948 	ifp = sc->nge_ifp;
949 
950 #ifdef DEVICE_POLLING
951 	if (ifp->if_capenable & IFCAP_POLLING)
952 		ether_poll_deregister(ifp);
953 #endif
954 	NGE_LOCK(sc);
955 	nge_reset(sc);
956 	nge_stop(sc);
957 	NGE_UNLOCK(sc);
958 	callout_drain(&sc->nge_stat_ch);
959 	ether_ifdetach(ifp);
960 
961 	bus_generic_detach(dev);
962 	if (!sc->nge_tbi) {
963 		device_delete_child(dev, sc->nge_miibus);
964 	}
965 	bus_teardown_intr(dev, sc->nge_irq, sc->nge_intrhand);
966 	bus_release_resource(dev, SYS_RES_IRQ, 0, sc->nge_irq);
967 	bus_release_resource(dev, NGE_RES, NGE_RID, sc->nge_res);
968 
969 	contigfree(sc->nge_ldata, sizeof(struct nge_list_data), M_DEVBUF);
970 	if_free(ifp);
971 
972 	NGE_LOCK_DESTROY(sc);
973 
974 	return(0);
975 }
976 
977 /*
978  * Initialize the transmit descriptors.
979  */
980 static int
981 nge_list_tx_init(sc)
982 	struct nge_softc	*sc;
983 {
984 	struct nge_list_data	*ld;
985 	struct nge_ring_data	*cd;
986 	int			i;
987 
988 	cd = &sc->nge_cdata;
989 	ld = sc->nge_ldata;
990 
991 	for (i = 0; i < NGE_TX_LIST_CNT; i++) {
992 		if (i == (NGE_TX_LIST_CNT - 1)) {
993 			ld->nge_tx_list[i].nge_nextdesc =
994 			    &ld->nge_tx_list[0];
995 			ld->nge_tx_list[i].nge_next =
996 			    vtophys(&ld->nge_tx_list[0]);
997 		} else {
998 			ld->nge_tx_list[i].nge_nextdesc =
999 			    &ld->nge_tx_list[i + 1];
1000 			ld->nge_tx_list[i].nge_next =
1001 			    vtophys(&ld->nge_tx_list[i + 1]);
1002 		}
1003 		ld->nge_tx_list[i].nge_mbuf = NULL;
1004 		ld->nge_tx_list[i].nge_ptr = 0;
1005 		ld->nge_tx_list[i].nge_ctl = 0;
1006 	}
1007 
1008 	cd->nge_tx_prod = cd->nge_tx_cons = cd->nge_tx_cnt = 0;
1009 
1010 	return(0);
1011 }
1012 
1013 
1014 /*
1015  * Initialize the RX descriptors and allocate mbufs for them. Note that
1016  * we arrange the descriptors in a closed ring, so that the last descriptor
1017  * points back to the first.
1018  */
1019 static int
1020 nge_list_rx_init(sc)
1021 	struct nge_softc	*sc;
1022 {
1023 	struct nge_list_data	*ld;
1024 	struct nge_ring_data	*cd;
1025 	int			i;
1026 
1027 	ld = sc->nge_ldata;
1028 	cd = &sc->nge_cdata;
1029 
1030 	for (i = 0; i < NGE_RX_LIST_CNT; i++) {
1031 		if (nge_newbuf(sc, &ld->nge_rx_list[i], NULL) == ENOBUFS)
1032 			return(ENOBUFS);
1033 		if (i == (NGE_RX_LIST_CNT - 1)) {
1034 			ld->nge_rx_list[i].nge_nextdesc =
1035 			    &ld->nge_rx_list[0];
1036 			ld->nge_rx_list[i].nge_next =
1037 			    vtophys(&ld->nge_rx_list[0]);
1038 		} else {
1039 			ld->nge_rx_list[i].nge_nextdesc =
1040 			    &ld->nge_rx_list[i + 1];
1041 			ld->nge_rx_list[i].nge_next =
1042 			    vtophys(&ld->nge_rx_list[i + 1]);
1043 		}
1044 	}
1045 
1046 	cd->nge_rx_prod = 0;
1047 	sc->nge_head = sc->nge_tail = NULL;
1048 
1049 	return(0);
1050 }
1051 
1052 /*
1053  * Initialize an RX descriptor and attach an MBUF cluster.
1054  */
1055 static int
1056 nge_newbuf(sc, c, m)
1057 	struct nge_softc	*sc;
1058 	struct nge_desc		*c;
1059 	struct mbuf		*m;
1060 {
1061 
1062 	if (m == NULL) {
1063 		m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
1064 		if (m == NULL)
1065 			return (ENOBUFS);
1066 	} else
1067 		m->m_data = m->m_ext.ext_buf;
1068 
1069 	m->m_len = m->m_pkthdr.len = MCLBYTES;
1070 
1071 	m_adj(m, sizeof(u_int64_t));
1072 
1073 	c->nge_mbuf = m;
1074 	c->nge_ptr = vtophys(mtod(m, caddr_t));
1075 	c->nge_ctl = m->m_len;
1076 	c->nge_extsts = 0;
1077 
1078 	return(0);
1079 }
1080 
1081 #ifdef NGE_FIXUP_RX
1082 static __inline void
1083 nge_fixup_rx(m)
1084 	struct mbuf		*m;
1085 {
1086         int			i;
1087         uint16_t		*src, *dst;
1088 
1089 	src = mtod(m, uint16_t *);
1090 	dst = src - 1;
1091 
1092 	for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++)
1093 		*dst++ = *src++;
1094 
1095 	m->m_data -= ETHER_ALIGN;
1096 
1097 	return;
1098 }
1099 #endif
1100 
1101 /*
1102  * A frame has been uploaded: pass the resulting mbuf chain up to
1103  * the higher level protocols.
1104  */
1105 static void
1106 nge_rxeof(sc)
1107 	struct nge_softc	*sc;
1108 {
1109         struct mbuf		*m;
1110         struct ifnet		*ifp;
1111 	struct nge_desc		*cur_rx;
1112 	int			i, total_len = 0;
1113 	u_int32_t		rxstat;
1114 
1115 	NGE_LOCK_ASSERT(sc);
1116 	ifp = sc->nge_ifp;
1117 	i = sc->nge_cdata.nge_rx_prod;
1118 
1119 	while(NGE_OWNDESC(&sc->nge_ldata->nge_rx_list[i])) {
1120 		u_int32_t		extsts;
1121 
1122 #ifdef DEVICE_POLLING
1123 		if (ifp->if_capenable & IFCAP_POLLING) {
1124 			if (sc->rxcycles <= 0)
1125 				break;
1126 			sc->rxcycles--;
1127 		}
1128 #endif
1129 
1130 		cur_rx = &sc->nge_ldata->nge_rx_list[i];
1131 		rxstat = cur_rx->nge_rxstat;
1132 		extsts = cur_rx->nge_extsts;
1133 		m = cur_rx->nge_mbuf;
1134 		cur_rx->nge_mbuf = NULL;
1135 		total_len = NGE_RXBYTES(cur_rx);
1136 		NGE_INC(i, NGE_RX_LIST_CNT);
1137 
1138 		if (rxstat & NGE_CMDSTS_MORE) {
1139 			m->m_len = total_len;
1140 			if (sc->nge_head == NULL) {
1141 				m->m_pkthdr.len = total_len;
1142 				sc->nge_head = sc->nge_tail = m;
1143 			} else {
1144 				m->m_flags &= ~M_PKTHDR;
1145 				sc->nge_head->m_pkthdr.len += total_len;
1146 				sc->nge_tail->m_next = m;
1147 				sc->nge_tail = m;
1148 			}
1149 			nge_newbuf(sc, cur_rx, NULL);
1150 			continue;
1151 		}
1152 
1153 		/*
1154 		 * If an error occurs, update stats, clear the
1155 		 * status word and leave the mbuf cluster in place:
1156 		 * it should simply get re-used next time this descriptor
1157 	 	 * comes up in the ring.
1158 		 */
1159 		if (!(rxstat & NGE_CMDSTS_PKT_OK)) {
1160 			ifp->if_ierrors++;
1161 			if (sc->nge_head != NULL) {
1162 				m_freem(sc->nge_head);
1163 				sc->nge_head = sc->nge_tail = NULL;
1164 			}
1165 			nge_newbuf(sc, cur_rx, m);
1166 			continue;
1167 		}
1168 
1169 		/* Try conjure up a replacement mbuf. */
1170 
1171 		if (nge_newbuf(sc, cur_rx, NULL)) {
1172 			ifp->if_ierrors++;
1173 			if (sc->nge_head != NULL) {
1174 				m_freem(sc->nge_head);
1175 				sc->nge_head = sc->nge_tail = NULL;
1176 			}
1177 			nge_newbuf(sc, cur_rx, m);
1178 			continue;
1179 		}
1180 
1181 		if (sc->nge_head != NULL) {
1182 			m->m_len = total_len;
1183 			m->m_flags &= ~M_PKTHDR;
1184 			sc->nge_tail->m_next = m;
1185 			m = sc->nge_head;
1186 			m->m_pkthdr.len += total_len;
1187 			sc->nge_head = sc->nge_tail = NULL;
1188 		} else
1189 			m->m_pkthdr.len = m->m_len = total_len;
1190 
1191 		/*
1192 		 * Ok. NatSemi really screwed up here. This is the
1193 		 * only gigE chip I know of with alignment constraints
1194 		 * on receive buffers. RX buffers must be 64-bit aligned.
1195 		 */
1196 		/*
1197 		 * By popular demand, ignore the alignment problems
1198 		 * on the Intel x86 platform. The performance hit
1199 		 * incurred due to unaligned accesses is much smaller
1200 		 * than the hit produced by forcing buffer copies all
1201 		 * the time, especially with jumbo frames. We still
1202 		 * need to fix up the alignment everywhere else though.
1203 		 */
1204 #ifdef NGE_FIXUP_RX
1205 		nge_fixup_rx(m);
1206 #endif
1207 
1208 		ifp->if_ipackets++;
1209 		m->m_pkthdr.rcvif = ifp;
1210 
1211 		/* Do IP checksum checking. */
1212 		if (extsts & NGE_RXEXTSTS_IPPKT)
1213 			m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
1214 		if (!(extsts & NGE_RXEXTSTS_IPCSUMERR))
1215 			m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
1216 		if ((extsts & NGE_RXEXTSTS_TCPPKT &&
1217 		    !(extsts & NGE_RXEXTSTS_TCPCSUMERR)) ||
1218 		    (extsts & NGE_RXEXTSTS_UDPPKT &&
1219 		    !(extsts & NGE_RXEXTSTS_UDPCSUMERR))) {
1220 			m->m_pkthdr.csum_flags |=
1221 			    CSUM_DATA_VALID|CSUM_PSEUDO_HDR;
1222 			m->m_pkthdr.csum_data = 0xffff;
1223 		}
1224 
1225 		/*
1226 		 * If we received a packet with a vlan tag, pass it
1227 		 * to vlan_input() instead of ether_input().
1228 		 */
1229 		if (extsts & NGE_RXEXTSTS_VLANPKT) {
1230 			m->m_pkthdr.ether_vtag =
1231 			    ntohs(extsts & NGE_RXEXTSTS_VTCI);
1232 			m->m_flags |= M_VLANTAG;
1233 		}
1234 		NGE_UNLOCK(sc);
1235 		(*ifp->if_input)(ifp, m);
1236 		NGE_LOCK(sc);
1237 	}
1238 
1239 	sc->nge_cdata.nge_rx_prod = i;
1240 
1241 	return;
1242 }
1243 
1244 /*
1245  * A frame was downloaded to the chip. It's safe for us to clean up
1246  * the list buffers.
1247  */
1248 
1249 static void
1250 nge_txeof(sc)
1251 	struct nge_softc	*sc;
1252 {
1253 	struct nge_desc		*cur_tx;
1254 	struct ifnet		*ifp;
1255 	u_int32_t		idx;
1256 
1257 	NGE_LOCK_ASSERT(sc);
1258 	ifp = sc->nge_ifp;
1259 
1260 	/*
1261 	 * Go through our tx list and free mbufs for those
1262 	 * frames that have been transmitted.
1263 	 */
1264 	idx = sc->nge_cdata.nge_tx_cons;
1265 	while (idx != sc->nge_cdata.nge_tx_prod) {
1266 		cur_tx = &sc->nge_ldata->nge_tx_list[idx];
1267 
1268 		if (NGE_OWNDESC(cur_tx))
1269 			break;
1270 
1271 		if (cur_tx->nge_ctl & NGE_CMDSTS_MORE) {
1272 			sc->nge_cdata.nge_tx_cnt--;
1273 			NGE_INC(idx, NGE_TX_LIST_CNT);
1274 			continue;
1275 		}
1276 
1277 		if (!(cur_tx->nge_ctl & NGE_CMDSTS_PKT_OK)) {
1278 			ifp->if_oerrors++;
1279 			if (cur_tx->nge_txstat & NGE_TXSTAT_EXCESSCOLLS)
1280 				ifp->if_collisions++;
1281 			if (cur_tx->nge_txstat & NGE_TXSTAT_OUTOFWINCOLL)
1282 				ifp->if_collisions++;
1283 		}
1284 
1285 		ifp->if_collisions +=
1286 		    (cur_tx->nge_txstat & NGE_TXSTAT_COLLCNT) >> 16;
1287 
1288 		ifp->if_opackets++;
1289 		if (cur_tx->nge_mbuf != NULL) {
1290 			m_freem(cur_tx->nge_mbuf);
1291 			cur_tx->nge_mbuf = NULL;
1292 			ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1293 		}
1294 
1295 		sc->nge_cdata.nge_tx_cnt--;
1296 		NGE_INC(idx, NGE_TX_LIST_CNT);
1297 	}
1298 
1299 	sc->nge_cdata.nge_tx_cons = idx;
1300 
1301 	if (idx == sc->nge_cdata.nge_tx_prod)
1302 		ifp->if_timer = 0;
1303 
1304 	return;
1305 }
1306 
1307 static void
1308 nge_tick(xsc)
1309 	void			*xsc;
1310 {
1311 	struct nge_softc	*sc;
1312 	struct mii_data		*mii;
1313 	struct ifnet		*ifp;
1314 
1315 	sc = xsc;
1316 	NGE_LOCK_ASSERT(sc);
1317 	ifp = sc->nge_ifp;
1318 
1319 	if (sc->nge_tbi) {
1320 		if (!sc->nge_link) {
1321 			if (CSR_READ_4(sc, NGE_TBI_BMSR)
1322 			    & NGE_TBIBMSR_ANEG_DONE) {
1323 				if (bootverbose)
1324 					device_printf(sc->nge_dev,
1325 					    "gigabit link up\n");
1326 				nge_miibus_statchg(sc->nge_miibus);
1327 				sc->nge_link++;
1328 				if (ifp->if_snd.ifq_head != NULL)
1329 					nge_start_locked(ifp);
1330 			}
1331 		}
1332 	} else {
1333 		mii = device_get_softc(sc->nge_miibus);
1334 		mii_tick(mii);
1335 
1336 		if (!sc->nge_link) {
1337 			if (mii->mii_media_status & IFM_ACTIVE &&
1338 			    IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
1339 				sc->nge_link++;
1340 				if (IFM_SUBTYPE(mii->mii_media_active)
1341 				    == IFM_1000_T && bootverbose)
1342 					device_printf(sc->nge_dev,
1343 					    "gigabit link up\n");
1344 				if (ifp->if_snd.ifq_head != NULL)
1345 					nge_start_locked(ifp);
1346 			}
1347 		}
1348 	}
1349 	callout_reset(&sc->nge_stat_ch, hz, nge_tick, sc);
1350 
1351 	return;
1352 }
1353 
1354 #ifdef DEVICE_POLLING
1355 static poll_handler_t nge_poll;
1356 
1357 static void
1358 nge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1359 {
1360 	struct  nge_softc *sc = ifp->if_softc;
1361 
1362 	NGE_LOCK(sc);
1363 	if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
1364 		NGE_UNLOCK(sc);
1365 		return;
1366 	}
1367 
1368 	/*
1369 	 * On the nge, reading the status register also clears it.
1370 	 * So before returning to intr mode we must make sure that all
1371 	 * possible pending sources of interrupts have been served.
1372 	 * In practice this means run to completion the *eof routines,
1373 	 * and then call the interrupt routine
1374 	 */
1375 	sc->rxcycles = count;
1376 	nge_rxeof(sc);
1377 	nge_txeof(sc);
1378 	if (ifp->if_snd.ifq_head != NULL)
1379 		nge_start_locked(ifp);
1380 
1381 	if (sc->rxcycles > 0 || cmd == POLL_AND_CHECK_STATUS) {
1382 		u_int32_t	status;
1383 
1384 		/* Reading the ISR register clears all interrupts. */
1385 		status = CSR_READ_4(sc, NGE_ISR);
1386 
1387 		if (status & (NGE_ISR_RX_ERR|NGE_ISR_RX_OFLOW))
1388 			nge_rxeof(sc);
1389 
1390 		if (status & (NGE_ISR_RX_IDLE))
1391 			NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE);
1392 
1393 		if (status & NGE_ISR_SYSERR) {
1394 			nge_reset(sc);
1395 			nge_init_locked(sc);
1396 		}
1397 	}
1398 	NGE_UNLOCK(sc);
1399 }
1400 #endif /* DEVICE_POLLING */
1401 
1402 static void
1403 nge_intr(arg)
1404 	void			*arg;
1405 {
1406 	struct nge_softc	*sc;
1407 	struct ifnet		*ifp;
1408 	u_int32_t		status;
1409 
1410 	sc = arg;
1411 	ifp = sc->nge_ifp;
1412 
1413 	NGE_LOCK(sc);
1414 #ifdef DEVICE_POLLING
1415 	if (ifp->if_capenable & IFCAP_POLLING) {
1416 		NGE_UNLOCK(sc);
1417 		return;
1418 	}
1419 #endif
1420 
1421 	/* Supress unwanted interrupts */
1422 	if (!(ifp->if_flags & IFF_UP)) {
1423 		nge_stop(sc);
1424 		NGE_UNLOCK(sc);
1425 		return;
1426 	}
1427 
1428 	/* Disable interrupts. */
1429 	CSR_WRITE_4(sc, NGE_IER, 0);
1430 
1431 	/* Data LED on for TBI mode */
1432 	if(sc->nge_tbi)
1433 		 CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO)
1434 			     | NGE_GPIO_GP3_OUT);
1435 
1436 	for (;;) {
1437 		/* Reading the ISR register clears all interrupts. */
1438 		status = CSR_READ_4(sc, NGE_ISR);
1439 
1440 		if ((status & NGE_INTRS) == 0)
1441 			break;
1442 
1443 		if ((status & NGE_ISR_TX_DESC_OK) ||
1444 		    (status & NGE_ISR_TX_ERR) ||
1445 		    (status & NGE_ISR_TX_OK) ||
1446 		    (status & NGE_ISR_TX_IDLE))
1447 			nge_txeof(sc);
1448 
1449 		if ((status & NGE_ISR_RX_DESC_OK) ||
1450 		    (status & NGE_ISR_RX_ERR) ||
1451 		    (status & NGE_ISR_RX_OFLOW) ||
1452 		    (status & NGE_ISR_RX_FIFO_OFLOW) ||
1453 		    (status & NGE_ISR_RX_IDLE) ||
1454 		    (status & NGE_ISR_RX_OK))
1455 			nge_rxeof(sc);
1456 
1457 		if ((status & NGE_ISR_RX_IDLE))
1458 			NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE);
1459 
1460 		if (status & NGE_ISR_SYSERR) {
1461 			nge_reset(sc);
1462 			ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1463 			nge_init_locked(sc);
1464 		}
1465 
1466 #if 0
1467 		/*
1468 		 * XXX: nge_tick() is not ready to be called this way
1469 		 * it screws up the aneg timeout because mii_tick() is
1470 		 * only to be called once per second.
1471 		 */
1472 		if (status & NGE_IMR_PHY_INTR) {
1473 			sc->nge_link = 0;
1474 			nge_tick(sc);
1475 		}
1476 #endif
1477 	}
1478 
1479 	/* Re-enable interrupts. */
1480 	CSR_WRITE_4(sc, NGE_IER, 1);
1481 
1482 	if (ifp->if_snd.ifq_head != NULL)
1483 		nge_start_locked(ifp);
1484 
1485 	/* Data LED off for TBI mode */
1486 
1487 	if(sc->nge_tbi)
1488 		CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO)
1489 			    & ~NGE_GPIO_GP3_OUT);
1490 
1491 	NGE_UNLOCK(sc);
1492 
1493 	return;
1494 }
1495 
1496 /*
1497  * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1498  * pointers to the fragment pointers.
1499  */
1500 static int
1501 nge_encap(sc, m_head, txidx)
1502 	struct nge_softc	*sc;
1503 	struct mbuf		*m_head;
1504 	u_int32_t		*txidx;
1505 {
1506 	struct nge_desc		*f = NULL;
1507 	struct mbuf		*m;
1508 	int			frag, cur, cnt = 0;
1509 
1510 	/*
1511  	 * Start packing the mbufs in this chain into
1512 	 * the fragment pointers. Stop when we run out
1513  	 * of fragments or hit the end of the mbuf chain.
1514 	 */
1515 	m = m_head;
1516 	cur = frag = *txidx;
1517 
1518 	for (m = m_head; m != NULL; m = m->m_next) {
1519 		if (m->m_len != 0) {
1520 			if ((NGE_TX_LIST_CNT -
1521 			    (sc->nge_cdata.nge_tx_cnt + cnt)) < 2)
1522 				return(ENOBUFS);
1523 			f = &sc->nge_ldata->nge_tx_list[frag];
1524 			f->nge_ctl = NGE_CMDSTS_MORE | m->m_len;
1525 			f->nge_ptr = vtophys(mtod(m, vm_offset_t));
1526 			if (cnt != 0)
1527 				f->nge_ctl |= NGE_CMDSTS_OWN;
1528 			cur = frag;
1529 			NGE_INC(frag, NGE_TX_LIST_CNT);
1530 			cnt++;
1531 		}
1532 	}
1533 
1534 	if (m != NULL)
1535 		return(ENOBUFS);
1536 
1537 	sc->nge_ldata->nge_tx_list[*txidx].nge_extsts = 0;
1538 	if (m_head->m_pkthdr.csum_flags) {
1539 		if (m_head->m_pkthdr.csum_flags & CSUM_IP)
1540 			sc->nge_ldata->nge_tx_list[*txidx].nge_extsts |=
1541 			    NGE_TXEXTSTS_IPCSUM;
1542 		if (m_head->m_pkthdr.csum_flags & CSUM_TCP)
1543 			sc->nge_ldata->nge_tx_list[*txidx].nge_extsts |=
1544 			    NGE_TXEXTSTS_TCPCSUM;
1545 		if (m_head->m_pkthdr.csum_flags & CSUM_UDP)
1546 			sc->nge_ldata->nge_tx_list[*txidx].nge_extsts |=
1547 			    NGE_TXEXTSTS_UDPCSUM;
1548 	}
1549 
1550 	if (m_head->m_flags & M_VLANTAG) {
1551 		sc->nge_ldata->nge_tx_list[cur].nge_extsts |=
1552 		    (NGE_TXEXTSTS_VLANPKT|htons(m_head->m_pkthdr.ether_vtag));
1553 	}
1554 
1555 	sc->nge_ldata->nge_tx_list[cur].nge_mbuf = m_head;
1556 	sc->nge_ldata->nge_tx_list[cur].nge_ctl &= ~NGE_CMDSTS_MORE;
1557 	sc->nge_ldata->nge_tx_list[*txidx].nge_ctl |= NGE_CMDSTS_OWN;
1558 	sc->nge_cdata.nge_tx_cnt += cnt;
1559 	*txidx = frag;
1560 
1561 	return(0);
1562 }
1563 
1564 /*
1565  * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1566  * to the mbuf data regions directly in the transmit lists. We also save a
1567  * copy of the pointers since the transmit list fragment pointers are
1568  * physical addresses.
1569  */
1570 
1571 static void
1572 nge_start(ifp)
1573 	struct ifnet		*ifp;
1574 {
1575 	struct nge_softc	*sc;
1576 
1577 	sc = ifp->if_softc;
1578 	NGE_LOCK(sc);
1579 	nge_start_locked(ifp);
1580 	NGE_UNLOCK(sc);
1581 }
1582 
1583 static void
1584 nge_start_locked(ifp)
1585 	struct ifnet		*ifp;
1586 {
1587 	struct nge_softc	*sc;
1588 	struct mbuf		*m_head = NULL;
1589 	u_int32_t		idx;
1590 
1591 	sc = ifp->if_softc;
1592 
1593 	if (!sc->nge_link)
1594 		return;
1595 
1596 	idx = sc->nge_cdata.nge_tx_prod;
1597 
1598 	if (ifp->if_drv_flags & IFF_DRV_OACTIVE)
1599 		return;
1600 
1601 	while(sc->nge_ldata->nge_tx_list[idx].nge_mbuf == NULL) {
1602 		IF_DEQUEUE(&ifp->if_snd, m_head);
1603 		if (m_head == NULL)
1604 			break;
1605 
1606 		if (nge_encap(sc, m_head, &idx)) {
1607 			IF_PREPEND(&ifp->if_snd, m_head);
1608 			ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1609 			break;
1610 		}
1611 
1612 		/*
1613 		 * If there's a BPF listener, bounce a copy of this frame
1614 		 * to him.
1615 		 */
1616 		ETHER_BPF_MTAP(ifp, m_head);
1617 
1618 	}
1619 
1620 	/* Transmit */
1621 	sc->nge_cdata.nge_tx_prod = idx;
1622 	NGE_SETBIT(sc, NGE_CSR, NGE_CSR_TX_ENABLE);
1623 
1624 	/*
1625 	 * Set a timeout in case the chip goes out to lunch.
1626 	 */
1627 	ifp->if_timer = 5;
1628 
1629 	return;
1630 }
1631 
1632 static void
1633 nge_init(xsc)
1634 	void			*xsc;
1635 {
1636 	struct nge_softc	*sc = xsc;
1637 
1638 	NGE_LOCK(sc);
1639 	nge_init_locked(sc);
1640 	NGE_UNLOCK(sc);
1641 }
1642 
1643 static void
1644 nge_init_locked(sc)
1645 	struct nge_softc	*sc;
1646 {
1647 	struct ifnet		*ifp = sc->nge_ifp;
1648 	struct mii_data		*mii;
1649 
1650 	NGE_LOCK_ASSERT(sc);
1651 
1652 	if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1653 		return;
1654 
1655 	/*
1656 	 * Cancel pending I/O and free all RX/TX buffers.
1657 	 */
1658 	nge_stop(sc);
1659 
1660 	if (sc->nge_tbi) {
1661 		mii = NULL;
1662 	} else {
1663 		mii = device_get_softc(sc->nge_miibus);
1664 	}
1665 
1666 	/* Set MAC address */
1667 	CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR0);
1668 	CSR_WRITE_4(sc, NGE_RXFILT_DATA,
1669 	    ((u_int16_t *)IF_LLADDR(sc->nge_ifp))[0]);
1670 	CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR1);
1671 	CSR_WRITE_4(sc, NGE_RXFILT_DATA,
1672 	    ((u_int16_t *)IF_LLADDR(sc->nge_ifp))[1]);
1673 	CSR_WRITE_4(sc, NGE_RXFILT_CTL, NGE_FILTADDR_PAR2);
1674 	CSR_WRITE_4(sc, NGE_RXFILT_DATA,
1675 	    ((u_int16_t *)IF_LLADDR(sc->nge_ifp))[2]);
1676 
1677 	/* Init circular RX list. */
1678 	if (nge_list_rx_init(sc) == ENOBUFS) {
1679 		device_printf(sc->nge_dev, "initialization failed: no "
1680 			"memory for rx buffers\n");
1681 		nge_stop(sc);
1682 		return;
1683 	}
1684 
1685 	/*
1686 	 * Init tx descriptors.
1687 	 */
1688 	nge_list_tx_init(sc);
1689 
1690 	/*
1691 	 * For the NatSemi chip, we have to explicitly enable the
1692 	 * reception of ARP frames, as well as turn on the 'perfect
1693 	 * match' filter where we store the station address, otherwise
1694 	 * we won't receive unicasts meant for this host.
1695 	 */
1696 	NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ARP);
1697 	NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_PERFECT);
1698 
1699 	 /* If we want promiscuous mode, set the allframes bit. */
1700 	if (ifp->if_flags & IFF_PROMISC) {
1701 		NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLPHYS);
1702 	} else {
1703 		NGE_CLRBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ALLPHYS);
1704 	}
1705 
1706 	/*
1707 	 * Set the capture broadcast bit to capture broadcast frames.
1708 	 */
1709 	if (ifp->if_flags & IFF_BROADCAST) {
1710 		NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_BROAD);
1711 	} else {
1712 		NGE_CLRBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_BROAD);
1713 	}
1714 
1715 	/*
1716 	 * Load the multicast filter.
1717 	 */
1718 	nge_setmulti(sc);
1719 
1720 	/* Turn the receive filter on */
1721 	NGE_SETBIT(sc, NGE_RXFILT_CTL, NGE_RXFILTCTL_ENABLE);
1722 
1723 	/*
1724 	 * Load the address of the RX and TX lists.
1725 	 */
1726 	CSR_WRITE_4(sc, NGE_RX_LISTPTR,
1727 	    vtophys(&sc->nge_ldata->nge_rx_list[0]));
1728 	CSR_WRITE_4(sc, NGE_TX_LISTPTR,
1729 	    vtophys(&sc->nge_ldata->nge_tx_list[0]));
1730 
1731 	/* Set RX configuration */
1732 	CSR_WRITE_4(sc, NGE_RX_CFG, NGE_RXCFG);
1733 	/*
1734 	 * Enable hardware checksum validation for all IPv4
1735 	 * packets, do not reject packets with bad checksums.
1736 	 */
1737 	CSR_WRITE_4(sc, NGE_VLAN_IP_RXCTL, NGE_VIPRXCTL_IPCSUM_ENB);
1738 
1739 	/*
1740 	 * Tell the chip to detect and strip VLAN tag info from
1741 	 * received frames. The tag will be provided in the extsts
1742 	 * field in the RX descriptors.
1743 	 */
1744 	NGE_SETBIT(sc, NGE_VLAN_IP_RXCTL,
1745 	    NGE_VIPRXCTL_TAG_DETECT_ENB|NGE_VIPRXCTL_TAG_STRIP_ENB);
1746 
1747 	/* Set TX configuration */
1748 	CSR_WRITE_4(sc, NGE_TX_CFG, NGE_TXCFG);
1749 
1750 	/*
1751 	 * Enable TX IPv4 checksumming on a per-packet basis.
1752 	 */
1753 	CSR_WRITE_4(sc, NGE_VLAN_IP_TXCTL, NGE_VIPTXCTL_CSUM_PER_PKT);
1754 
1755 	/*
1756 	 * Tell the chip to insert VLAN tags on a per-packet basis as
1757 	 * dictated by the code in the frame encapsulation routine.
1758 	 */
1759 	NGE_SETBIT(sc, NGE_VLAN_IP_TXCTL, NGE_VIPTXCTL_TAG_PER_PKT);
1760 
1761 	/* Set full/half duplex mode. */
1762 	if (sc->nge_tbi) {
1763 		if ((sc->nge_ifmedia.ifm_cur->ifm_media & IFM_GMASK)
1764 		    == IFM_FDX) {
1765 			NGE_SETBIT(sc, NGE_TX_CFG,
1766 			    (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR));
1767 			NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
1768 		} else {
1769 			NGE_CLRBIT(sc, NGE_TX_CFG,
1770 			    (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR));
1771 			NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
1772 		}
1773 	} else {
1774 		if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
1775 			NGE_SETBIT(sc, NGE_TX_CFG,
1776 			    (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR));
1777 			NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
1778 		} else {
1779 			NGE_CLRBIT(sc, NGE_TX_CFG,
1780 			    (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR));
1781 			NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
1782 		}
1783 	}
1784 
1785 	nge_tick(sc);
1786 
1787 	/*
1788 	 * Enable the delivery of PHY interrupts based on
1789 	 * link/speed/duplex status changes. Also enable the
1790 	 * extsts field in the DMA descriptors (needed for
1791 	 * TCP/IP checksum offload on transmit).
1792 	 */
1793 	NGE_SETBIT(sc, NGE_CFG, NGE_CFG_PHYINTR_SPD|
1794 	    NGE_CFG_PHYINTR_LNK|NGE_CFG_PHYINTR_DUP|NGE_CFG_EXTSTS_ENB);
1795 
1796 	/*
1797 	 * Configure interrupt holdoff (moderation). We can
1798 	 * have the chip delay interrupt delivery for a certain
1799 	 * period. Units are in 100us, and the max setting
1800 	 * is 25500us (0xFF x 100us). Default is a 100us holdoff.
1801 	 */
1802 	CSR_WRITE_4(sc, NGE_IHR, 0x01);
1803 
1804 	/*
1805 	 * Enable interrupts.
1806 	 */
1807 	CSR_WRITE_4(sc, NGE_IMR, NGE_INTRS);
1808 #ifdef DEVICE_POLLING
1809 	/*
1810 	 * ... only enable interrupts if we are not polling, make sure
1811 	 * they are off otherwise.
1812 	 */
1813 	if (ifp->if_capenable & IFCAP_POLLING)
1814 		CSR_WRITE_4(sc, NGE_IER, 0);
1815 	else
1816 #endif
1817 	CSR_WRITE_4(sc, NGE_IER, 1);
1818 
1819 	/* Enable receiver and transmitter. */
1820 	NGE_CLRBIT(sc, NGE_CSR, NGE_CSR_TX_DISABLE|NGE_CSR_RX_DISABLE);
1821 	NGE_SETBIT(sc, NGE_CSR, NGE_CSR_RX_ENABLE);
1822 
1823 	nge_ifmedia_upd_locked(ifp);
1824 
1825 	ifp->if_drv_flags |= IFF_DRV_RUNNING;
1826 	ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1827 
1828 	return;
1829 }
1830 
1831 /*
1832  * Set media options.
1833  */
1834 static int
1835 nge_ifmedia_upd(ifp)
1836 	struct ifnet		*ifp;
1837 {
1838 	struct nge_softc	*sc;
1839 
1840 	sc = ifp->if_softc;
1841 	NGE_LOCK(sc);
1842 	nge_ifmedia_upd_locked(ifp);
1843 	NGE_UNLOCK(sc);
1844 	return (0);
1845 }
1846 
1847 static void
1848 nge_ifmedia_upd_locked(ifp)
1849 	struct ifnet		*ifp;
1850 {
1851 	struct nge_softc	*sc;
1852 	struct mii_data		*mii;
1853 
1854 	sc = ifp->if_softc;
1855 	NGE_LOCK_ASSERT(sc);
1856 
1857 	if (sc->nge_tbi) {
1858 		if (IFM_SUBTYPE(sc->nge_ifmedia.ifm_cur->ifm_media)
1859 		     == IFM_AUTO) {
1860 			CSR_WRITE_4(sc, NGE_TBI_ANAR,
1861 				CSR_READ_4(sc, NGE_TBI_ANAR)
1862 					| NGE_TBIANAR_HDX | NGE_TBIANAR_FDX
1863 					| NGE_TBIANAR_PS1 | NGE_TBIANAR_PS2);
1864 			CSR_WRITE_4(sc, NGE_TBI_BMCR, NGE_TBIBMCR_ENABLE_ANEG
1865 				| NGE_TBIBMCR_RESTART_ANEG);
1866 			CSR_WRITE_4(sc, NGE_TBI_BMCR, NGE_TBIBMCR_ENABLE_ANEG);
1867 		} else if ((sc->nge_ifmedia.ifm_cur->ifm_media
1868 			    & IFM_GMASK) == IFM_FDX) {
1869 			NGE_SETBIT(sc, NGE_TX_CFG,
1870 			    (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR));
1871 			NGE_SETBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
1872 
1873 			CSR_WRITE_4(sc, NGE_TBI_ANAR, 0);
1874 			CSR_WRITE_4(sc, NGE_TBI_BMCR, 0);
1875 		} else {
1876 			NGE_CLRBIT(sc, NGE_TX_CFG,
1877 			    (NGE_TXCFG_IGN_HBEAT|NGE_TXCFG_IGN_CARR));
1878 			NGE_CLRBIT(sc, NGE_RX_CFG, NGE_RXCFG_RX_FDX);
1879 
1880 			CSR_WRITE_4(sc, NGE_TBI_ANAR, 0);
1881 			CSR_WRITE_4(sc, NGE_TBI_BMCR, 0);
1882 		}
1883 
1884 		CSR_WRITE_4(sc, NGE_GPIO, CSR_READ_4(sc, NGE_GPIO)
1885 			    & ~NGE_GPIO_GP3_OUT);
1886 	} else {
1887 		mii = device_get_softc(sc->nge_miibus);
1888 		sc->nge_link = 0;
1889 		if (mii->mii_instance) {
1890 			struct mii_softc	*miisc;
1891 
1892 			LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
1893 				mii_phy_reset(miisc);
1894 		}
1895 		mii_mediachg(mii);
1896 	}
1897 }
1898 
1899 /*
1900  * Report current media status.
1901  */
1902 static void
1903 nge_ifmedia_sts(ifp, ifmr)
1904 	struct ifnet		*ifp;
1905 	struct ifmediareq	*ifmr;
1906 {
1907 	struct nge_softc	*sc;
1908 	struct mii_data		*mii;
1909 
1910 	sc = ifp->if_softc;
1911 
1912 	NGE_LOCK(sc);
1913 	if (sc->nge_tbi) {
1914 		ifmr->ifm_status = IFM_AVALID;
1915 		ifmr->ifm_active = IFM_ETHER;
1916 
1917 		if (CSR_READ_4(sc, NGE_TBI_BMSR) & NGE_TBIBMSR_ANEG_DONE) {
1918 			ifmr->ifm_status |= IFM_ACTIVE;
1919 		}
1920 		if (CSR_READ_4(sc, NGE_TBI_BMCR) & NGE_TBIBMCR_LOOPBACK)
1921 			ifmr->ifm_active |= IFM_LOOP;
1922 		if (!CSR_READ_4(sc, NGE_TBI_BMSR) & NGE_TBIBMSR_ANEG_DONE) {
1923 			ifmr->ifm_active |= IFM_NONE;
1924 			ifmr->ifm_status = 0;
1925 			NGE_UNLOCK(sc);
1926 			return;
1927 		}
1928 		ifmr->ifm_active |= IFM_1000_SX;
1929 		if (IFM_SUBTYPE(sc->nge_ifmedia.ifm_cur->ifm_media)
1930 		    == IFM_AUTO) {
1931 			ifmr->ifm_active |= IFM_AUTO;
1932 			if (CSR_READ_4(sc, NGE_TBI_ANLPAR)
1933 			    & NGE_TBIANAR_FDX) {
1934 				ifmr->ifm_active |= IFM_FDX;
1935 			}else if (CSR_READ_4(sc, NGE_TBI_ANLPAR)
1936 				  & NGE_TBIANAR_HDX) {
1937 				ifmr->ifm_active |= IFM_HDX;
1938 			}
1939 		} else if ((sc->nge_ifmedia.ifm_cur->ifm_media & IFM_GMASK)
1940 			== IFM_FDX)
1941 			ifmr->ifm_active |= IFM_FDX;
1942 		else
1943 			ifmr->ifm_active |= IFM_HDX;
1944 
1945 	} else {
1946 		mii = device_get_softc(sc->nge_miibus);
1947 		mii_pollstat(mii);
1948 		ifmr->ifm_active = mii->mii_media_active;
1949 		ifmr->ifm_status = mii->mii_media_status;
1950 	}
1951 	NGE_UNLOCK(sc);
1952 
1953 	return;
1954 }
1955 
1956 static int
1957 nge_ioctl(ifp, command, data)
1958 	struct ifnet		*ifp;
1959 	u_long			command;
1960 	caddr_t			data;
1961 {
1962 	struct nge_softc	*sc = ifp->if_softc;
1963 	struct ifreq		*ifr = (struct ifreq *) data;
1964 	struct mii_data		*mii;
1965 	int			error = 0;
1966 
1967 	switch(command) {
1968 	case SIOCSIFMTU:
1969 		if (ifr->ifr_mtu > NGE_JUMBO_MTU)
1970 			error = EINVAL;
1971 		else {
1972 			NGE_LOCK(sc);
1973 			ifp->if_mtu = ifr->ifr_mtu;
1974 			/*
1975 			 * Workaround: if the MTU is larger than
1976 			 * 8152 (TX FIFO size minus 64 minus 18), turn off
1977 			 * TX checksum offloading.
1978 			 */
1979 			if (ifr->ifr_mtu >= 8152) {
1980 				ifp->if_capenable &= ~IFCAP_TXCSUM;
1981 				ifp->if_hwassist = 0;
1982 			} else {
1983 				ifp->if_capenable |= IFCAP_TXCSUM;
1984 				ifp->if_hwassist = NGE_CSUM_FEATURES;
1985 			}
1986 			NGE_UNLOCK(sc);
1987 		}
1988 		break;
1989 	case SIOCSIFFLAGS:
1990 		NGE_LOCK(sc);
1991 		if (ifp->if_flags & IFF_UP) {
1992 			if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
1993 			    ifp->if_flags & IFF_PROMISC &&
1994 			    !(sc->nge_if_flags & IFF_PROMISC)) {
1995 				NGE_SETBIT(sc, NGE_RXFILT_CTL,
1996 				    NGE_RXFILTCTL_ALLPHYS|
1997 				    NGE_RXFILTCTL_ALLMULTI);
1998 			} else if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
1999 			    !(ifp->if_flags & IFF_PROMISC) &&
2000 			    sc->nge_if_flags & IFF_PROMISC) {
2001 				NGE_CLRBIT(sc, NGE_RXFILT_CTL,
2002 				    NGE_RXFILTCTL_ALLPHYS);
2003 				if (!(ifp->if_flags & IFF_ALLMULTI))
2004 					NGE_CLRBIT(sc, NGE_RXFILT_CTL,
2005 					    NGE_RXFILTCTL_ALLMULTI);
2006 			} else {
2007 				ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2008 				nge_init_locked(sc);
2009 			}
2010 		} else {
2011 			if (ifp->if_drv_flags & IFF_DRV_RUNNING)
2012 				nge_stop(sc);
2013 		}
2014 		sc->nge_if_flags = ifp->if_flags;
2015 		NGE_UNLOCK(sc);
2016 		error = 0;
2017 		break;
2018 	case SIOCADDMULTI:
2019 	case SIOCDELMULTI:
2020 		NGE_LOCK(sc);
2021 		nge_setmulti(sc);
2022 		NGE_UNLOCK(sc);
2023 		error = 0;
2024 		break;
2025 	case SIOCGIFMEDIA:
2026 	case SIOCSIFMEDIA:
2027 		if (sc->nge_tbi) {
2028 			error = ifmedia_ioctl(ifp, ifr, &sc->nge_ifmedia,
2029 					      command);
2030 		} else {
2031 			mii = device_get_softc(sc->nge_miibus);
2032 			error = ifmedia_ioctl(ifp, ifr, &mii->mii_media,
2033 					      command);
2034 		}
2035 		break;
2036 	case SIOCSIFCAP:
2037 #ifdef DEVICE_POLLING
2038 		if (ifr->ifr_reqcap & IFCAP_POLLING &&
2039 		    !(ifp->if_capenable & IFCAP_POLLING)) {
2040 			error = ether_poll_register(nge_poll, ifp);
2041 			if (error)
2042 				return(error);
2043 			NGE_LOCK(sc);
2044 			/* Disable interrupts */
2045 			CSR_WRITE_4(sc, NGE_IER, 0);
2046 			ifp->if_capenable |= IFCAP_POLLING;
2047 			NGE_UNLOCK(sc);
2048 			return (error);
2049 
2050 		}
2051 		if (!(ifr->ifr_reqcap & IFCAP_POLLING) &&
2052 		    ifp->if_capenable & IFCAP_POLLING) {
2053 			error = ether_poll_deregister(ifp);
2054 			/* Enable interrupts. */
2055 			NGE_LOCK(sc);
2056 			CSR_WRITE_4(sc, NGE_IER, 1);
2057 			ifp->if_capenable &= ~IFCAP_POLLING;
2058 			NGE_UNLOCK(sc);
2059 			return (error);
2060 		}
2061 #endif /* DEVICE_POLLING */
2062 		break;
2063 	default:
2064 		error = ether_ioctl(ifp, command, data);
2065 		break;
2066 	}
2067 
2068 	return(error);
2069 }
2070 
2071 static void
2072 nge_watchdog(ifp)
2073 	struct ifnet		*ifp;
2074 {
2075 	struct nge_softc	*sc;
2076 
2077 	sc = ifp->if_softc;
2078 
2079 	ifp->if_oerrors++;
2080 	if_printf(ifp, "watchdog timeout\n");
2081 
2082 	NGE_LOCK(sc);
2083 	nge_stop(sc);
2084 	nge_reset(sc);
2085 	ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2086 	nge_init_locked(sc);
2087 
2088 	if (ifp->if_snd.ifq_head != NULL)
2089 		nge_start_locked(ifp);
2090 
2091 	NGE_UNLOCK(sc);
2092 
2093 	return;
2094 }
2095 
2096 /*
2097  * Stop the adapter and free any mbufs allocated to the
2098  * RX and TX lists.
2099  */
2100 static void
2101 nge_stop(sc)
2102 	struct nge_softc	*sc;
2103 {
2104 	register int		i;
2105 	struct ifnet		*ifp;
2106 	struct mii_data		*mii;
2107 
2108 	NGE_LOCK_ASSERT(sc);
2109 	ifp = sc->nge_ifp;
2110 	ifp->if_timer = 0;
2111 	if (sc->nge_tbi) {
2112 		mii = NULL;
2113 	} else {
2114 		mii = device_get_softc(sc->nge_miibus);
2115 	}
2116 
2117 	callout_stop(&sc->nge_stat_ch);
2118 	CSR_WRITE_4(sc, NGE_IER, 0);
2119 	CSR_WRITE_4(sc, NGE_IMR, 0);
2120 	NGE_SETBIT(sc, NGE_CSR, NGE_CSR_TX_DISABLE|NGE_CSR_RX_DISABLE);
2121 	DELAY(1000);
2122 	CSR_WRITE_4(sc, NGE_TX_LISTPTR, 0);
2123 	CSR_WRITE_4(sc, NGE_RX_LISTPTR, 0);
2124 
2125 	if (!sc->nge_tbi)
2126 		mii_down(mii);
2127 
2128 	sc->nge_link = 0;
2129 
2130 	/*
2131 	 * Free data in the RX lists.
2132 	 */
2133 	for (i = 0; i < NGE_RX_LIST_CNT; i++) {
2134 		if (sc->nge_ldata->nge_rx_list[i].nge_mbuf != NULL) {
2135 			m_freem(sc->nge_ldata->nge_rx_list[i].nge_mbuf);
2136 			sc->nge_ldata->nge_rx_list[i].nge_mbuf = NULL;
2137 		}
2138 	}
2139 	bzero((char *)&sc->nge_ldata->nge_rx_list,
2140 		sizeof(sc->nge_ldata->nge_rx_list));
2141 
2142 	/*
2143 	 * Free the TX list buffers.
2144 	 */
2145 	for (i = 0; i < NGE_TX_LIST_CNT; i++) {
2146 		if (sc->nge_ldata->nge_tx_list[i].nge_mbuf != NULL) {
2147 			m_freem(sc->nge_ldata->nge_tx_list[i].nge_mbuf);
2148 			sc->nge_ldata->nge_tx_list[i].nge_mbuf = NULL;
2149 		}
2150 	}
2151 
2152 	bzero((char *)&sc->nge_ldata->nge_tx_list,
2153 		sizeof(sc->nge_ldata->nge_tx_list));
2154 
2155 	ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
2156 
2157 	return;
2158 }
2159 
2160 /*
2161  * Stop all chip I/O so that the kernel's probe routines don't
2162  * get confused by errant DMAs when rebooting.
2163  */
2164 static int
2165 nge_shutdown(dev)
2166 	device_t		dev;
2167 {
2168 	struct nge_softc	*sc;
2169 
2170 	sc = device_get_softc(dev);
2171 
2172 	NGE_LOCK(sc);
2173 	nge_reset(sc);
2174 	nge_stop(sc);
2175 	NGE_UNLOCK(sc);
2176 
2177 	return (0);
2178 }
2179