1 /* $OpenBSD: if_nfereg.h,v 1.16 2006/02/22 19:23:44 damien Exp $ */ 2 3 /*- 4 * Copyright (c) 2005 Jonathan Gray <jsg@openbsd.org> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 * 18 * $FreeBSD$ 19 */ 20 21 #define NFE_PCI_BA 0x10 22 23 #define NFE_RX_RING_COUNT 128 24 #define NFE_TX_RING_COUNT 256 25 26 /* RX/TX MAC addr + type + VLAN + align + slack */ 27 #define NFE_RX_HEADERS 64 28 29 /* Maximum MTU size. */ 30 #define NV_PKTLIMIT_1 ETH_DATA_LEN /* Hard limit not known. */ 31 #define NV_PKTLIMIT_2 9100 /* Actual limit according to NVidia:9202 */ 32 #define NFE_JBYTES (ETHER_MAX_LEN_JUMBO + ETHER_ALIGN) 33 #define NFE_JPOOL_COUNT (NFE_RX_RING_COUNT + NFE_RX_HEADERS) 34 35 #define NFE_MAX_SCATTER (NFE_TX_RING_COUNT - 2) 36 37 #define NFE_IRQ_STATUS 0x000 38 #define NFE_IRQ_MASK 0x004 39 #define NFE_SETUP_R6 0x008 40 #define NFE_IMTIMER 0x00c 41 #define NFE_MISC1 0x080 42 #define NFE_TX_CTL 0x084 43 #define NFE_TX_STATUS 0x088 44 #define NFE_RXFILTER 0x08c 45 #define NFE_RXBUFSZ 0x090 46 #define NFE_RX_CTL 0x094 47 #define NFE_RX_STATUS 0x098 48 #define NFE_RNDSEED 0x09c 49 #define NFE_SETUP_R1 0x0a0 50 #define NFE_SETUP_R2 0x0a4 51 #define NFE_MACADDR_HI 0x0a8 52 #define NFE_MACADDR_LO 0x0ac 53 #define NFE_MULTIADDR_HI 0x0b0 54 #define NFE_MULTIADDR_LO 0x0b4 55 #define NFE_MULTIMASK_HI 0x0b8 56 #define NFE_MULTIMASK_LO 0x0bc 57 #define NFE_PHY_IFACE 0x0c0 58 #define NFE_TX_RING_ADDR_LO 0x100 59 #define NFE_RX_RING_ADDR_LO 0x104 60 #define NFE_RING_SIZE 0x108 61 #define NFE_TX_UNK 0x10c 62 #define NFE_LINKSPEED 0x110 63 #define NFE_SETUP_R5 0x130 64 #define NFE_SETUP_R3 0x13C 65 #define NFE_SETUP_R7 0x140 66 #define NFE_RXTX_CTL 0x144 67 #define NFE_TX_RING_ADDR_HI 0x148 68 #define NFE_RX_RING_ADDR_HI 0x14c 69 #define NFE_PHY_STATUS 0x180 70 #define NFE_SETUP_R4 0x184 71 #define NFE_STATUS 0x188 72 #define NFE_PHY_SPEED 0x18c 73 #define NFE_PHY_CTL 0x190 74 #define NFE_PHY_DATA 0x194 75 #define NFE_WOL_CTL 0x200 76 #define NFE_PATTERN_CRC 0x204 77 #define NFE_PATTERN_MASK 0x208 78 #define NFE_PWR_CAP 0x268 79 #define NFE_PWR_STATE 0x26c 80 #define NFE_VTAG_CTL 0x300 81 82 #define NFE_PHY_ERROR 0x00001 83 #define NFE_PHY_WRITE 0x00400 84 #define NFE_PHY_BUSY 0x08000 85 #define NFE_PHYADD_SHIFT 5 86 87 #define NFE_STATUS_MAGIC 0x140000 88 89 #define NFE_R1_MAGIC 0x16070f 90 #define NFE_R2_MAGIC 0x16 91 #define NFE_R4_MAGIC 0x08 92 #define NFE_R6_MAGIC 0x03 93 #define NFE_WOL_MAGIC 0x1111 94 #define NFE_RX_START 0x01 95 #define NFE_TX_START 0x01 96 97 #define NFE_IRQ_RXERR 0x0001 98 #define NFE_IRQ_RX 0x0002 99 #define NFE_IRQ_RX_NOBUF 0x0004 100 #define NFE_IRQ_TXERR 0x0008 101 #define NFE_IRQ_TX_DONE 0x0010 102 #define NFE_IRQ_TIMER 0x0020 103 #define NFE_IRQ_LINK 0x0040 104 #define NFE_IRQ_TXERR2 0x0080 105 #define NFE_IRQ_TX1 0x0100 106 107 #define NFE_IRQ_WANTED \ 108 (NFE_IRQ_RXERR | NFE_IRQ_RX_NOBUF | NFE_IRQ_RX | \ 109 NFE_IRQ_TXERR | NFE_IRQ_TXERR2 | NFE_IRQ_TX_DONE | \ 110 NFE_IRQ_LINK) 111 112 #define NFE_RXTX_KICKTX 0x0001 113 #define NFE_RXTX_BIT1 0x0002 114 #define NFE_RXTX_BIT2 0x0004 115 #define NFE_RXTX_RESET 0x0010 116 #define NFE_RXTX_VTAG_STRIP 0x0040 117 #define NFE_RXTX_VTAG_INSERT 0x0080 118 #define NFE_RXTX_RXCSUM 0x0400 119 #define NFE_RXTX_V2MAGIC 0x2100 120 #define NFE_RXTX_V3MAGIC 0x2200 121 #define NFE_RXFILTER_MAGIC 0x007f0008 122 #define NFE_U2M (1 << 5) 123 #define NFE_PROMISC (1 << 7) 124 #define NFE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 125 126 /* default interrupt moderation timer of 128us */ 127 #define NFE_IM_DEFAULT ((128 * 100) / 1024) 128 129 #define NFE_VTAG_ENABLE (1 << 13) 130 131 #define NFE_PWR_VALID (1 << 8) 132 #define NFE_PWR_WAKEUP (1 << 15) 133 134 #define NFE_MEDIA_SET 0x10000 135 #define NFE_MEDIA_1000T 0x00032 136 #define NFE_MEDIA_100TX 0x00064 137 #define NFE_MEDIA_10T 0x003e8 138 139 #define NFE_PHY_100TX (1 << 0) 140 #define NFE_PHY_1000T (1 << 1) 141 #define NFE_PHY_HDX (1 << 8) 142 143 #define NFE_MISC1_MAGIC 0x003b0f3c 144 #define NFE_MISC1_HDX (1 << 1) 145 146 #define NFE_SEED_MASK 0x0003ff00 147 #define NFE_SEED_10T 0x00007f00 148 #define NFE_SEED_100TX 0x00002d00 149 #define NFE_SEED_1000T 0x00007400 150 151 /* Rx/Tx descriptor */ 152 struct nfe_desc32 { 153 uint32_t physaddr; 154 uint16_t length; 155 uint16_t flags; 156 #define NFE_RX_FIXME_V1 0x6004 157 #define NFE_RX_VALID_V1 (1 << 0) 158 #define NFE_TX_ERROR_V1 0x7808 159 #define NFE_TX_LASTFRAG_V1 (1 << 0) 160 #define NFE_RX_ERROR1_V1 (1<<7) 161 #define NFE_RX_ERROR2_V1 (1<<8) 162 #define NFE_RX_ERROR3_V1 (1<<9) 163 #define NFE_RX_ERROR4_V1 (1<<10) 164 } __packed; 165 166 #define NFE_V1_TXERR "\020" \ 167 "\14TXERROR\13UNDERFLOW\12LATECOLLISION\11LOSTCARRIER\10DEFERRED" \ 168 "\08FORCEDINT\03RETRY\00LASTPACKET" 169 170 /* V2 Rx/Tx descriptor */ 171 struct nfe_desc64 { 172 uint32_t physaddr[2]; 173 uint32_t vtag; 174 #define NFE_RX_VTAG (1 << 16) 175 #define NFE_TX_VTAG (1 << 18) 176 uint16_t length; 177 uint16_t flags; 178 #define NFE_RX_FIXME_V2 0x4300 179 #define NFE_RX_VALID_V2 (1 << 13) 180 #define NFE_TX_ERROR_V2 0x5c04 181 #define NFE_TX_LASTFRAG_V2 (1 << 13) 182 #define NFE_RX_IP_CSUMOK_V2 0x1000 183 #define NFE_RX_UDP_CSUMOK_V2 0x1400 184 #define NFE_RX_TCP_CSUMOK_V2 0x1800 185 #define NFE_RX_ERROR1_V2 (1<<2) 186 #define NFE_RX_ERROR2_V2 (1<<3) 187 #define NFE_RX_ERROR3_V2 (1<<4) 188 #define NFE_RX_ERROR4_V2 (1<<5) 189 } __packed; 190 191 #define NFE_V2_TXERR "\020" \ 192 "\14FORCEDINT\13LASTPACKET\12UNDERFLOW\10LOSTCARRIER\09DEFERRED\02RETRY" 193 194 /* flags common to V1/V2 descriptors */ 195 #define NFE_RX_CSUMOK 0x1c00 196 #define NFE_RX_ERROR (1 << 14) 197 #define NFE_RX_READY (1 << 15) 198 #define NFE_TX_TCP_CSUM (1 << 10) 199 #define NFE_TX_IP_CSUM (1 << 11) 200 #define NFE_TX_VALID (1 << 15) 201 202 #define NFE_READ(sc, reg) \ 203 bus_space_read_4((sc)->nfe_memt, (sc)->nfe_memh, (reg)) 204 205 #define NFE_WRITE(sc, reg, val) \ 206 bus_space_write_4((sc)->nfe_memt, (sc)->nfe_memh, (reg), (val)) 207 208 #ifndef PCI_VENDOR_NVIDIA 209 #define PCI_VENDOR_NVIDIA 0x10DE 210 #endif 211 212 #define PCI_PRODUCT_NVIDIA_NFORCE_LAN 0x01C3 213 #define PCI_PRODUCT_NVIDIA_NFORCE2_LAN 0x0066 214 #define PCI_PRODUCT_NVIDIA_NFORCE3_LAN1 0x00D6 215 #define PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN1 0x0086 216 #define PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN2 0x008C 217 #define PCI_PRODUCT_NVIDIA_NFORCE3_250_LAN 0x00E6 218 #define PCI_PRODUCT_NVIDIA_NFORCE3_LAN4 0x00DF 219 #define PCI_PRODUCT_NVIDIA_NFORCE4_LAN1 0x0056 220 #define PCI_PRODUCT_NVIDIA_NFORCE4_LAN2 0x0057 221 #define PCI_PRODUCT_NVIDIA_MCP04_LAN1 0x0037 222 #define PCI_PRODUCT_NVIDIA_MCP04_LAN2 0x0038 223 #define PCI_PRODUCT_NVIDIA_NFORCE430_LAN1 0x0268 224 #define PCI_PRODUCT_NVIDIA_NFORCE430_LAN2 0x0269 225 #define PCI_PRODUCT_NVIDIA_MCP55_LAN1 0x0372 226 #define PCI_PRODUCT_NVIDIA_MCP55_LAN2 0x0373 227 #define PCI_PRODUCT_NVIDIA_MCP61_LAN1 0x03e5 228 #define PCI_PRODUCT_NVIDIA_MCP61_LAN2 0x03e6 229 #define PCI_PRODUCT_NVIDIA_MCP61_LAN3 0x03ee 230 #define PCI_PRODUCT_NVIDIA_MCP61_LAN4 0x03ef 231 #define PCI_PRODUCT_NVIDIA_MCP65_LAN1 0x0450 232 #define PCI_PRODUCT_NVIDIA_MCP65_LAN2 0x0451 233 #define PCI_PRODUCT_NVIDIA_MCP65_LAN3 0x0452 234 #define PCI_PRODUCT_NVIDIA_MCP65_LAN4 0x0453 235 236 #define PCI_PRODUCT_NVIDIA_NFORCE3_LAN2 PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN1 237 #define PCI_PRODUCT_NVIDIA_NFORCE3_LAN3 PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN2 238 #define PCI_PRODUCT_NVIDIA_NFORCE3_LAN5 PCI_PRODUCT_NVIDIA_NFORCE3_250_LAN 239 #define PCI_PRODUCT_NVIDIA_CK804_LAN1 PCI_PRODUCT_NVIDIA_NFORCE4_LAN1 240 #define PCI_PRODUCT_NVIDIA_CK804_LAN2 PCI_PRODUCT_NVIDIA_NFORCE4_LAN2 241 #define PCI_PRODUCT_NVIDIA_MCP51_LAN1 PCI_PRODUCT_NVIDIA_NFORCE430_LAN1 242 #define PCI_PRODUCT_NVIDIA_MCP51_LAN2 PCI_PRODUCT_NVIDIA_NFORCE430_LAN2 243 244 #define NFE_DEBUG 0x0000 245 #define NFE_DEBUG_INIT 0x0001 246 #define NFE_DEBUG_RUNNING 0x0002 247 #define NFE_DEBUG_DEINIT 0x0004 248 #define NFE_DEBUG_IOCTL 0x0008 249 #define NFE_DEBUG_INTERRUPT 0x0010 250 #define NFE_DEBUG_API 0x0020 251 #define NFE_DEBUG_LOCK 0x0040 252 #define NFE_DEBUG_BROKEN 0x0080 253 #define NFE_DEBUG_MII 0x0100 254 #define NFE_DEBUG_ALL 0xFFFF 255