1 /* $OpenBSD: if_nfe.c,v 1.54 2006/04/07 12:38:12 jsg Exp $ */ 2 3 /*- 4 * Copyright (c) 2006 Shigeaki Tagashira <shigeaki@se.hiroshima-u.ac.jp> 5 * Copyright (c) 2006 Damien Bergamini <damien.bergamini@free.fr> 6 * Copyright (c) 2005, 2006 Jonathan Gray <jsg@openbsd.org> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 /* Driver for NVIDIA nForce MCP Fast Ethernet and Gigabit Ethernet */ 22 23 #include <sys/cdefs.h> 24 __FBSDID("$FreeBSD$"); 25 26 #ifdef HAVE_KERNEL_OPTION_HEADERS 27 #include "opt_device_polling.h" 28 #endif 29 30 #include <sys/param.h> 31 #include <sys/endian.h> 32 #include <sys/systm.h> 33 #include <sys/sockio.h> 34 #include <sys/mbuf.h> 35 #include <sys/malloc.h> 36 #include <sys/module.h> 37 #include <sys/kernel.h> 38 #include <sys/queue.h> 39 #include <sys/socket.h> 40 #include <sys/sysctl.h> 41 #include <sys/taskqueue.h> 42 43 #include <net/if.h> 44 #include <net/if_var.h> 45 #include <net/if_arp.h> 46 #include <net/ethernet.h> 47 #include <net/if_dl.h> 48 #include <net/if_media.h> 49 #include <net/if_types.h> 50 #include <net/if_vlan_var.h> 51 52 #include <net/bpf.h> 53 54 #include <machine/bus.h> 55 #include <machine/resource.h> 56 #include <sys/bus.h> 57 #include <sys/rman.h> 58 59 #include <dev/mii/mii.h> 60 #include <dev/mii/miivar.h> 61 62 #include <dev/pci/pcireg.h> 63 #include <dev/pci/pcivar.h> 64 65 #include <dev/nfe/if_nfereg.h> 66 #include <dev/nfe/if_nfevar.h> 67 68 MODULE_DEPEND(nfe, pci, 1, 1, 1); 69 MODULE_DEPEND(nfe, ether, 1, 1, 1); 70 MODULE_DEPEND(nfe, miibus, 1, 1, 1); 71 72 /* "device miibus" required. See GENERIC if you get errors here. */ 73 #include "miibus_if.h" 74 75 static int nfe_probe(device_t); 76 static int nfe_attach(device_t); 77 static int nfe_detach(device_t); 78 static int nfe_suspend(device_t); 79 static int nfe_resume(device_t); 80 static int nfe_shutdown(device_t); 81 static int nfe_can_use_msix(struct nfe_softc *); 82 static int nfe_detect_msik9(struct nfe_softc *); 83 static void nfe_power(struct nfe_softc *); 84 static int nfe_miibus_readreg(device_t, int, int); 85 static int nfe_miibus_writereg(device_t, int, int, int); 86 static void nfe_miibus_statchg(device_t); 87 static void nfe_mac_config(struct nfe_softc *, struct mii_data *); 88 static void nfe_set_intr(struct nfe_softc *); 89 static __inline void nfe_enable_intr(struct nfe_softc *); 90 static __inline void nfe_disable_intr(struct nfe_softc *); 91 static int nfe_ioctl(if_t, u_long, caddr_t); 92 static void nfe_alloc_msix(struct nfe_softc *, int); 93 static int nfe_intr(void *); 94 static void nfe_int_task(void *, int); 95 static __inline void nfe_discard_rxbuf(struct nfe_softc *, int); 96 static __inline void nfe_discard_jrxbuf(struct nfe_softc *, int); 97 static int nfe_newbuf(struct nfe_softc *, int); 98 static int nfe_jnewbuf(struct nfe_softc *, int); 99 static int nfe_rxeof(struct nfe_softc *, int, int *); 100 static int nfe_jrxeof(struct nfe_softc *, int, int *); 101 static void nfe_txeof(struct nfe_softc *); 102 static int nfe_encap(struct nfe_softc *, struct mbuf **); 103 static void nfe_setmulti(struct nfe_softc *); 104 static void nfe_start(if_t); 105 static void nfe_start_locked(if_t); 106 static void nfe_watchdog(if_t); 107 static void nfe_init(void *); 108 static void nfe_init_locked(void *); 109 static void nfe_stop(if_t); 110 static int nfe_alloc_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 111 static void nfe_alloc_jrx_ring(struct nfe_softc *, struct nfe_jrx_ring *); 112 static int nfe_init_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 113 static int nfe_init_jrx_ring(struct nfe_softc *, struct nfe_jrx_ring *); 114 static void nfe_free_rx_ring(struct nfe_softc *, struct nfe_rx_ring *); 115 static void nfe_free_jrx_ring(struct nfe_softc *, struct nfe_jrx_ring *); 116 static int nfe_alloc_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 117 static void nfe_init_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 118 static void nfe_free_tx_ring(struct nfe_softc *, struct nfe_tx_ring *); 119 static int nfe_ifmedia_upd(if_t); 120 static void nfe_ifmedia_sts(if_t, struct ifmediareq *); 121 static void nfe_tick(void *); 122 static void nfe_get_macaddr(struct nfe_softc *, uint8_t *); 123 static void nfe_set_macaddr(struct nfe_softc *, uint8_t *); 124 static void nfe_dma_map_segs(void *, bus_dma_segment_t *, int, int); 125 126 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int); 127 static int sysctl_hw_nfe_proc_limit(SYSCTL_HANDLER_ARGS); 128 static void nfe_sysctl_node(struct nfe_softc *); 129 static void nfe_stats_clear(struct nfe_softc *); 130 static void nfe_stats_update(struct nfe_softc *); 131 static void nfe_set_linkspeed(struct nfe_softc *); 132 static void nfe_set_wol(struct nfe_softc *); 133 134 #ifdef NFE_DEBUG 135 static int nfedebug = 0; 136 #define DPRINTF(sc, ...) do { \ 137 if (nfedebug) \ 138 device_printf((sc)->nfe_dev, __VA_ARGS__); \ 139 } while (0) 140 #define DPRINTFN(sc, n, ...) do { \ 141 if (nfedebug >= (n)) \ 142 device_printf((sc)->nfe_dev, __VA_ARGS__); \ 143 } while (0) 144 #else 145 #define DPRINTF(sc, ...) 146 #define DPRINTFN(sc, n, ...) 147 #endif 148 149 #define NFE_LOCK(_sc) mtx_lock(&(_sc)->nfe_mtx) 150 #define NFE_UNLOCK(_sc) mtx_unlock(&(_sc)->nfe_mtx) 151 #define NFE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->nfe_mtx, MA_OWNED) 152 153 /* Tunables. */ 154 static int msi_disable = 0; 155 static int msix_disable = 0; 156 static int jumbo_disable = 0; 157 TUNABLE_INT("hw.nfe.msi_disable", &msi_disable); 158 TUNABLE_INT("hw.nfe.msix_disable", &msix_disable); 159 TUNABLE_INT("hw.nfe.jumbo_disable", &jumbo_disable); 160 161 static device_method_t nfe_methods[] = { 162 /* Device interface */ 163 DEVMETHOD(device_probe, nfe_probe), 164 DEVMETHOD(device_attach, nfe_attach), 165 DEVMETHOD(device_detach, nfe_detach), 166 DEVMETHOD(device_suspend, nfe_suspend), 167 DEVMETHOD(device_resume, nfe_resume), 168 DEVMETHOD(device_shutdown, nfe_shutdown), 169 170 /* MII interface */ 171 DEVMETHOD(miibus_readreg, nfe_miibus_readreg), 172 DEVMETHOD(miibus_writereg, nfe_miibus_writereg), 173 DEVMETHOD(miibus_statchg, nfe_miibus_statchg), 174 175 DEVMETHOD_END 176 }; 177 178 static driver_t nfe_driver = { 179 "nfe", 180 nfe_methods, 181 sizeof(struct nfe_softc) 182 }; 183 184 static devclass_t nfe_devclass; 185 186 DRIVER_MODULE(nfe, pci, nfe_driver, nfe_devclass, 0, 0); 187 DRIVER_MODULE(miibus, nfe, miibus_driver, miibus_devclass, 0, 0); 188 189 static struct nfe_type nfe_devs[] = { 190 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE_LAN, 191 "NVIDIA nForce MCP Networking Adapter"}, 192 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE2_LAN, 193 "NVIDIA nForce2 MCP2 Networking Adapter"}, 194 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN1, 195 "NVIDIA nForce2 400 MCP4 Networking Adapter"}, 196 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE2_400_LAN2, 197 "NVIDIA nForce2 400 MCP5 Networking Adapter"}, 198 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN1, 199 "NVIDIA nForce3 MCP3 Networking Adapter"}, 200 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_250_LAN, 201 "NVIDIA nForce3 250 MCP6 Networking Adapter"}, 202 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE3_LAN4, 203 "NVIDIA nForce3 MCP7 Networking Adapter"}, 204 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE4_LAN1, 205 "NVIDIA nForce4 CK804 MCP8 Networking Adapter"}, 206 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE4_LAN2, 207 "NVIDIA nForce4 CK804 MCP9 Networking Adapter"}, 208 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_LAN1, 209 "NVIDIA nForce MCP04 Networking Adapter"}, /* MCP10 */ 210 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP04_LAN2, 211 "NVIDIA nForce MCP04 Networking Adapter"}, /* MCP11 */ 212 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE430_LAN1, 213 "NVIDIA nForce 430 MCP12 Networking Adapter"}, 214 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_NFORCE430_LAN2, 215 "NVIDIA nForce 430 MCP13 Networking Adapter"}, 216 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP55_LAN1, 217 "NVIDIA nForce MCP55 Networking Adapter"}, 218 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP55_LAN2, 219 "NVIDIA nForce MCP55 Networking Adapter"}, 220 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN1, 221 "NVIDIA nForce MCP61 Networking Adapter"}, 222 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN2, 223 "NVIDIA nForce MCP61 Networking Adapter"}, 224 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN3, 225 "NVIDIA nForce MCP61 Networking Adapter"}, 226 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP61_LAN4, 227 "NVIDIA nForce MCP61 Networking Adapter"}, 228 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN1, 229 "NVIDIA nForce MCP65 Networking Adapter"}, 230 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN2, 231 "NVIDIA nForce MCP65 Networking Adapter"}, 232 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN3, 233 "NVIDIA nForce MCP65 Networking Adapter"}, 234 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP65_LAN4, 235 "NVIDIA nForce MCP65 Networking Adapter"}, 236 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN1, 237 "NVIDIA nForce MCP67 Networking Adapter"}, 238 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN2, 239 "NVIDIA nForce MCP67 Networking Adapter"}, 240 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN3, 241 "NVIDIA nForce MCP67 Networking Adapter"}, 242 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP67_LAN4, 243 "NVIDIA nForce MCP67 Networking Adapter"}, 244 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN1, 245 "NVIDIA nForce MCP73 Networking Adapter"}, 246 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN2, 247 "NVIDIA nForce MCP73 Networking Adapter"}, 248 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN3, 249 "NVIDIA nForce MCP73 Networking Adapter"}, 250 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP73_LAN4, 251 "NVIDIA nForce MCP73 Networking Adapter"}, 252 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN1, 253 "NVIDIA nForce MCP77 Networking Adapter"}, 254 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN2, 255 "NVIDIA nForce MCP77 Networking Adapter"}, 256 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN3, 257 "NVIDIA nForce MCP77 Networking Adapter"}, 258 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP77_LAN4, 259 "NVIDIA nForce MCP77 Networking Adapter"}, 260 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN1, 261 "NVIDIA nForce MCP79 Networking Adapter"}, 262 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN2, 263 "NVIDIA nForce MCP79 Networking Adapter"}, 264 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN3, 265 "NVIDIA nForce MCP79 Networking Adapter"}, 266 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP79_LAN4, 267 "NVIDIA nForce MCP79 Networking Adapter"}, 268 {PCI_VENDOR_NVIDIA, PCI_PRODUCT_NVIDIA_MCP89_LAN, 269 "NVIDIA nForce MCP89 Networking Adapter"}, 270 {0, 0, NULL} 271 }; 272 273 /* Probe for supported hardware ID's */ 274 static int 275 nfe_probe(device_t dev) 276 { 277 struct nfe_type *t; 278 279 t = nfe_devs; 280 /* Check for matching PCI DEVICE ID's */ 281 while (t->name != NULL) { 282 if ((pci_get_vendor(dev) == t->vid_id) && 283 (pci_get_device(dev) == t->dev_id)) { 284 device_set_desc(dev, t->name); 285 return (BUS_PROBE_DEFAULT); 286 } 287 t++; 288 } 289 290 return (ENXIO); 291 } 292 293 static void 294 nfe_alloc_msix(struct nfe_softc *sc, int count) 295 { 296 int rid; 297 298 rid = PCIR_BAR(2); 299 sc->nfe_msix_res = bus_alloc_resource_any(sc->nfe_dev, SYS_RES_MEMORY, 300 &rid, RF_ACTIVE); 301 if (sc->nfe_msix_res == NULL) { 302 device_printf(sc->nfe_dev, 303 "couldn't allocate MSIX table resource\n"); 304 return; 305 } 306 rid = PCIR_BAR(3); 307 sc->nfe_msix_pba_res = bus_alloc_resource_any(sc->nfe_dev, 308 SYS_RES_MEMORY, &rid, RF_ACTIVE); 309 if (sc->nfe_msix_pba_res == NULL) { 310 device_printf(sc->nfe_dev, 311 "couldn't allocate MSIX PBA resource\n"); 312 bus_release_resource(sc->nfe_dev, SYS_RES_MEMORY, PCIR_BAR(2), 313 sc->nfe_msix_res); 314 sc->nfe_msix_res = NULL; 315 return; 316 } 317 318 if (pci_alloc_msix(sc->nfe_dev, &count) == 0) { 319 if (count == NFE_MSI_MESSAGES) { 320 if (bootverbose) 321 device_printf(sc->nfe_dev, 322 "Using %d MSIX messages\n", count); 323 sc->nfe_msix = 1; 324 } else { 325 if (bootverbose) 326 device_printf(sc->nfe_dev, 327 "couldn't allocate MSIX\n"); 328 pci_release_msi(sc->nfe_dev); 329 bus_release_resource(sc->nfe_dev, SYS_RES_MEMORY, 330 PCIR_BAR(3), sc->nfe_msix_pba_res); 331 bus_release_resource(sc->nfe_dev, SYS_RES_MEMORY, 332 PCIR_BAR(2), sc->nfe_msix_res); 333 sc->nfe_msix_pba_res = NULL; 334 sc->nfe_msix_res = NULL; 335 } 336 } 337 } 338 339 static int 340 nfe_detect_msik9(struct nfe_softc *sc) 341 { 342 static const char *maker = "MSI"; 343 static const char *product = "K9N6PGM2-V2 (MS-7309)"; 344 char *m, *p; 345 int found; 346 347 found = 0; 348 m = kern_getenv("smbios.planar.maker"); 349 p = kern_getenv("smbios.planar.product"); 350 if (m != NULL && p != NULL) { 351 if (strcmp(m, maker) == 0 && strcmp(p, product) == 0) 352 found = 1; 353 } 354 if (m != NULL) 355 freeenv(m); 356 if (p != NULL) 357 freeenv(p); 358 359 return (found); 360 } 361 362 static int 363 nfe_attach(device_t dev) 364 { 365 struct nfe_softc *sc; 366 if_t ifp; 367 bus_addr_t dma_addr_max; 368 int error = 0, i, msic, phyloc, reg, rid; 369 370 sc = device_get_softc(dev); 371 sc->nfe_dev = dev; 372 373 mtx_init(&sc->nfe_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 374 MTX_DEF); 375 callout_init_mtx(&sc->nfe_stat_ch, &sc->nfe_mtx, 0); 376 377 pci_enable_busmaster(dev); 378 379 rid = PCIR_BAR(0); 380 sc->nfe_res[0] = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 381 RF_ACTIVE); 382 if (sc->nfe_res[0] == NULL) { 383 device_printf(dev, "couldn't map memory resources\n"); 384 mtx_destroy(&sc->nfe_mtx); 385 return (ENXIO); 386 } 387 388 if (pci_find_cap(dev, PCIY_EXPRESS, ®) == 0) { 389 uint16_t v, width; 390 391 v = pci_read_config(dev, reg + 0x08, 2); 392 /* Change max. read request size to 4096. */ 393 v &= ~(7 << 12); 394 v |= (5 << 12); 395 pci_write_config(dev, reg + 0x08, v, 2); 396 397 v = pci_read_config(dev, reg + 0x0c, 2); 398 /* link capability */ 399 v = (v >> 4) & 0x0f; 400 width = pci_read_config(dev, reg + 0x12, 2); 401 /* negotiated link width */ 402 width = (width >> 4) & 0x3f; 403 if (v != width) 404 device_printf(sc->nfe_dev, 405 "warning, negotiated width of link(x%d) != " 406 "max. width of link(x%d)\n", width, v); 407 } 408 409 if (nfe_can_use_msix(sc) == 0) { 410 device_printf(sc->nfe_dev, 411 "MSI/MSI-X capability black-listed, will use INTx\n"); 412 msix_disable = 1; 413 msi_disable = 1; 414 } 415 416 /* Allocate interrupt */ 417 if (msix_disable == 0 || msi_disable == 0) { 418 if (msix_disable == 0 && 419 (msic = pci_msix_count(dev)) == NFE_MSI_MESSAGES) 420 nfe_alloc_msix(sc, msic); 421 if (msi_disable == 0 && sc->nfe_msix == 0 && 422 (msic = pci_msi_count(dev)) == NFE_MSI_MESSAGES && 423 pci_alloc_msi(dev, &msic) == 0) { 424 if (msic == NFE_MSI_MESSAGES) { 425 if (bootverbose) 426 device_printf(dev, 427 "Using %d MSI messages\n", msic); 428 sc->nfe_msi = 1; 429 } else 430 pci_release_msi(dev); 431 } 432 } 433 434 if (sc->nfe_msix == 0 && sc->nfe_msi == 0) { 435 rid = 0; 436 sc->nfe_irq[0] = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 437 RF_SHAREABLE | RF_ACTIVE); 438 if (sc->nfe_irq[0] == NULL) { 439 device_printf(dev, "couldn't allocate IRQ resources\n"); 440 error = ENXIO; 441 goto fail; 442 } 443 } else { 444 for (i = 0, rid = 1; i < NFE_MSI_MESSAGES; i++, rid++) { 445 sc->nfe_irq[i] = bus_alloc_resource_any(dev, 446 SYS_RES_IRQ, &rid, RF_ACTIVE); 447 if (sc->nfe_irq[i] == NULL) { 448 device_printf(dev, 449 "couldn't allocate IRQ resources for " 450 "message %d\n", rid); 451 error = ENXIO; 452 goto fail; 453 } 454 } 455 /* Map interrupts to vector 0. */ 456 if (sc->nfe_msix != 0) { 457 NFE_WRITE(sc, NFE_MSIX_MAP0, 0); 458 NFE_WRITE(sc, NFE_MSIX_MAP1, 0); 459 } else if (sc->nfe_msi != 0) { 460 NFE_WRITE(sc, NFE_MSI_MAP0, 0); 461 NFE_WRITE(sc, NFE_MSI_MAP1, 0); 462 } 463 } 464 465 /* Set IRQ status/mask register. */ 466 sc->nfe_irq_status = NFE_IRQ_STATUS; 467 sc->nfe_irq_mask = NFE_IRQ_MASK; 468 sc->nfe_intrs = NFE_IRQ_WANTED; 469 sc->nfe_nointrs = 0; 470 if (sc->nfe_msix != 0) { 471 sc->nfe_irq_status = NFE_MSIX_IRQ_STATUS; 472 sc->nfe_nointrs = NFE_IRQ_WANTED; 473 } else if (sc->nfe_msi != 0) { 474 sc->nfe_irq_mask = NFE_MSI_IRQ_MASK; 475 sc->nfe_intrs = NFE_MSI_VECTOR_0_ENABLED; 476 } 477 478 sc->nfe_devid = pci_get_device(dev); 479 sc->nfe_revid = pci_get_revid(dev); 480 sc->nfe_flags = 0; 481 482 switch (sc->nfe_devid) { 483 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN2: 484 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN3: 485 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN4: 486 case PCI_PRODUCT_NVIDIA_NFORCE3_LAN5: 487 sc->nfe_flags |= NFE_JUMBO_SUP | NFE_HW_CSUM; 488 break; 489 case PCI_PRODUCT_NVIDIA_MCP51_LAN1: 490 case PCI_PRODUCT_NVIDIA_MCP51_LAN2: 491 sc->nfe_flags |= NFE_40BIT_ADDR | NFE_PWR_MGMT | NFE_MIB_V1; 492 break; 493 case PCI_PRODUCT_NVIDIA_CK804_LAN1: 494 case PCI_PRODUCT_NVIDIA_CK804_LAN2: 495 case PCI_PRODUCT_NVIDIA_MCP04_LAN1: 496 case PCI_PRODUCT_NVIDIA_MCP04_LAN2: 497 sc->nfe_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | NFE_HW_CSUM | 498 NFE_MIB_V1; 499 break; 500 case PCI_PRODUCT_NVIDIA_MCP55_LAN1: 501 case PCI_PRODUCT_NVIDIA_MCP55_LAN2: 502 sc->nfe_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | NFE_HW_CSUM | 503 NFE_HW_VLAN | NFE_PWR_MGMT | NFE_TX_FLOW_CTRL | NFE_MIB_V2; 504 break; 505 506 case PCI_PRODUCT_NVIDIA_MCP61_LAN1: 507 case PCI_PRODUCT_NVIDIA_MCP61_LAN2: 508 case PCI_PRODUCT_NVIDIA_MCP61_LAN3: 509 case PCI_PRODUCT_NVIDIA_MCP61_LAN4: 510 case PCI_PRODUCT_NVIDIA_MCP67_LAN1: 511 case PCI_PRODUCT_NVIDIA_MCP67_LAN2: 512 case PCI_PRODUCT_NVIDIA_MCP67_LAN3: 513 case PCI_PRODUCT_NVIDIA_MCP67_LAN4: 514 case PCI_PRODUCT_NVIDIA_MCP73_LAN1: 515 case PCI_PRODUCT_NVIDIA_MCP73_LAN2: 516 case PCI_PRODUCT_NVIDIA_MCP73_LAN3: 517 case PCI_PRODUCT_NVIDIA_MCP73_LAN4: 518 sc->nfe_flags |= NFE_40BIT_ADDR | NFE_PWR_MGMT | 519 NFE_CORRECT_MACADDR | NFE_TX_FLOW_CTRL | NFE_MIB_V2; 520 break; 521 case PCI_PRODUCT_NVIDIA_MCP77_LAN1: 522 case PCI_PRODUCT_NVIDIA_MCP77_LAN2: 523 case PCI_PRODUCT_NVIDIA_MCP77_LAN3: 524 case PCI_PRODUCT_NVIDIA_MCP77_LAN4: 525 /* XXX flow control */ 526 sc->nfe_flags |= NFE_40BIT_ADDR | NFE_HW_CSUM | NFE_PWR_MGMT | 527 NFE_CORRECT_MACADDR | NFE_MIB_V3; 528 break; 529 case PCI_PRODUCT_NVIDIA_MCP79_LAN1: 530 case PCI_PRODUCT_NVIDIA_MCP79_LAN2: 531 case PCI_PRODUCT_NVIDIA_MCP79_LAN3: 532 case PCI_PRODUCT_NVIDIA_MCP79_LAN4: 533 case PCI_PRODUCT_NVIDIA_MCP89_LAN: 534 /* XXX flow control */ 535 sc->nfe_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | NFE_HW_CSUM | 536 NFE_PWR_MGMT | NFE_CORRECT_MACADDR | NFE_MIB_V3; 537 break; 538 case PCI_PRODUCT_NVIDIA_MCP65_LAN1: 539 case PCI_PRODUCT_NVIDIA_MCP65_LAN2: 540 case PCI_PRODUCT_NVIDIA_MCP65_LAN3: 541 case PCI_PRODUCT_NVIDIA_MCP65_LAN4: 542 sc->nfe_flags |= NFE_JUMBO_SUP | NFE_40BIT_ADDR | 543 NFE_PWR_MGMT | NFE_CORRECT_MACADDR | NFE_TX_FLOW_CTRL | 544 NFE_MIB_V2; 545 break; 546 } 547 548 nfe_power(sc); 549 /* Check for reversed ethernet address */ 550 if ((NFE_READ(sc, NFE_TX_UNK) & NFE_MAC_ADDR_INORDER) != 0) 551 sc->nfe_flags |= NFE_CORRECT_MACADDR; 552 nfe_get_macaddr(sc, sc->eaddr); 553 /* 554 * Allocate the parent bus DMA tag appropriate for PCI. 555 */ 556 dma_addr_max = BUS_SPACE_MAXADDR_32BIT; 557 if ((sc->nfe_flags & NFE_40BIT_ADDR) != 0) 558 dma_addr_max = NFE_DMA_MAXADDR; 559 error = bus_dma_tag_create( 560 bus_get_dma_tag(sc->nfe_dev), /* parent */ 561 1, 0, /* alignment, boundary */ 562 dma_addr_max, /* lowaddr */ 563 BUS_SPACE_MAXADDR, /* highaddr */ 564 NULL, NULL, /* filter, filterarg */ 565 BUS_SPACE_MAXSIZE_32BIT, 0, /* maxsize, nsegments */ 566 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 567 0, /* flags */ 568 NULL, NULL, /* lockfunc, lockarg */ 569 &sc->nfe_parent_tag); 570 if (error) 571 goto fail; 572 573 ifp = sc->nfe_ifp = if_gethandle(IFT_ETHER); 574 if (ifp == NULL) { 575 device_printf(dev, "can not if_gethandle()\n"); 576 error = ENOSPC; 577 goto fail; 578 } 579 580 /* 581 * Allocate Tx and Rx rings. 582 */ 583 if ((error = nfe_alloc_tx_ring(sc, &sc->txq)) != 0) 584 goto fail; 585 586 if ((error = nfe_alloc_rx_ring(sc, &sc->rxq)) != 0) 587 goto fail; 588 589 nfe_alloc_jrx_ring(sc, &sc->jrxq); 590 /* Create sysctl node. */ 591 nfe_sysctl_node(sc); 592 593 if_setsoftc(ifp, sc); 594 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 595 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 596 if_setioctlfn(ifp, nfe_ioctl); 597 if_setstartfn(ifp, nfe_start); 598 if_sethwassist(ifp, 0); 599 if_setcapabilities(ifp, 0); 600 if_setinitfn(ifp, nfe_init); 601 if_setsendqlen(ifp, NFE_TX_RING_COUNT - 1); 602 if_setsendqready(ifp); 603 604 if (sc->nfe_flags & NFE_HW_CSUM) { 605 if_setcapabilitiesbit(ifp, IFCAP_HWCSUM | IFCAP_TSO4, 0); 606 if_sethwassistbits(ifp, NFE_CSUM_FEATURES | CSUM_TSO, 0); 607 } 608 if_setcapenable(ifp, if_getcapabilities(ifp)); 609 610 sc->nfe_framesize = if_getmtu(ifp) + NFE_RX_HEADERS; 611 /* VLAN capability setup. */ 612 if_setcapabilitiesbit(ifp, IFCAP_VLAN_MTU, 0); 613 if ((sc->nfe_flags & NFE_HW_VLAN) != 0) { 614 if_setcapabilitiesbit(ifp, IFCAP_VLAN_HWTAGGING, 0); 615 if ((if_getcapabilities(ifp) & IFCAP_HWCSUM) != 0) 616 if_setcapabilitiesbit(ifp, 617 (IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO), 0); 618 } 619 620 if (pci_find_cap(dev, PCIY_PMG, ®) == 0) 621 if_setcapabilitiesbit(ifp, IFCAP_WOL_MAGIC, 0); 622 if_setcapenable(ifp, if_getcapabilities(ifp)); 623 624 /* 625 * Tell the upper layer(s) we support long frames. 626 * Must appear after the call to ether_ifattach() because 627 * ether_ifattach() sets ifi_hdrlen to the default value. 628 */ 629 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 630 631 #ifdef DEVICE_POLLING 632 if_setcapabilitiesbit(ifp, IFCAP_POLLING, 0); 633 #endif 634 635 /* Do MII setup */ 636 phyloc = MII_PHY_ANY; 637 if (sc->nfe_devid == PCI_PRODUCT_NVIDIA_MCP61_LAN1 || 638 sc->nfe_devid == PCI_PRODUCT_NVIDIA_MCP61_LAN2 || 639 sc->nfe_devid == PCI_PRODUCT_NVIDIA_MCP61_LAN3 || 640 sc->nfe_devid == PCI_PRODUCT_NVIDIA_MCP61_LAN4) { 641 if (nfe_detect_msik9(sc) != 0) 642 phyloc = 0; 643 } 644 error = mii_attach(dev, &sc->nfe_miibus, ifp, 645 (ifm_change_cb_t)nfe_ifmedia_upd, (ifm_stat_cb_t)nfe_ifmedia_sts, 646 BMSR_DEFCAPMASK, phyloc, MII_OFFSET_ANY, MIIF_DOPAUSE); 647 if (error != 0) { 648 device_printf(dev, "attaching PHYs failed\n"); 649 goto fail; 650 } 651 ether_ifattach(ifp, sc->eaddr); 652 653 NET_TASK_INIT(&sc->nfe_int_task, 0, nfe_int_task, sc); 654 sc->nfe_tq = taskqueue_create_fast("nfe_taskq", M_WAITOK, 655 taskqueue_thread_enqueue, &sc->nfe_tq); 656 taskqueue_start_threads(&sc->nfe_tq, 1, PI_NET, "%s taskq", 657 device_get_nameunit(sc->nfe_dev)); 658 error = 0; 659 if (sc->nfe_msi == 0 && sc->nfe_msix == 0) { 660 error = bus_setup_intr(dev, sc->nfe_irq[0], 661 INTR_TYPE_NET | INTR_MPSAFE, nfe_intr, NULL, sc, 662 &sc->nfe_intrhand[0]); 663 } else { 664 for (i = 0; i < NFE_MSI_MESSAGES; i++) { 665 error = bus_setup_intr(dev, sc->nfe_irq[i], 666 INTR_TYPE_NET | INTR_MPSAFE, nfe_intr, NULL, sc, 667 &sc->nfe_intrhand[i]); 668 if (error != 0) 669 break; 670 } 671 } 672 if (error) { 673 device_printf(dev, "couldn't set up irq\n"); 674 taskqueue_free(sc->nfe_tq); 675 sc->nfe_tq = NULL; 676 ether_ifdetach(ifp); 677 goto fail; 678 } 679 680 fail: 681 if (error) 682 nfe_detach(dev); 683 684 return (error); 685 } 686 687 static int 688 nfe_detach(device_t dev) 689 { 690 struct nfe_softc *sc; 691 if_t ifp; 692 uint8_t eaddr[ETHER_ADDR_LEN]; 693 int i, rid; 694 695 sc = device_get_softc(dev); 696 KASSERT(mtx_initialized(&sc->nfe_mtx), ("nfe mutex not initialized")); 697 ifp = sc->nfe_ifp; 698 699 #ifdef DEVICE_POLLING 700 if (ifp != NULL && if_getcapenable(ifp) & IFCAP_POLLING) 701 ether_poll_deregister(ifp); 702 #endif 703 if (device_is_attached(dev)) { 704 NFE_LOCK(sc); 705 nfe_stop(ifp); 706 if_setflagbits(ifp, 0, IFF_UP); 707 NFE_UNLOCK(sc); 708 callout_drain(&sc->nfe_stat_ch); 709 ether_ifdetach(ifp); 710 } 711 712 if (ifp) { 713 /* restore ethernet address */ 714 if ((sc->nfe_flags & NFE_CORRECT_MACADDR) == 0) { 715 for (i = 0; i < ETHER_ADDR_LEN; i++) { 716 eaddr[i] = sc->eaddr[5 - i]; 717 } 718 } else 719 bcopy(sc->eaddr, eaddr, ETHER_ADDR_LEN); 720 nfe_set_macaddr(sc, eaddr); 721 if_free(ifp); 722 } 723 if (sc->nfe_miibus) 724 device_delete_child(dev, sc->nfe_miibus); 725 bus_generic_detach(dev); 726 if (sc->nfe_tq != NULL) { 727 taskqueue_drain(sc->nfe_tq, &sc->nfe_int_task); 728 taskqueue_free(sc->nfe_tq); 729 sc->nfe_tq = NULL; 730 } 731 732 for (i = 0; i < NFE_MSI_MESSAGES; i++) { 733 if (sc->nfe_intrhand[i] != NULL) { 734 bus_teardown_intr(dev, sc->nfe_irq[i], 735 sc->nfe_intrhand[i]); 736 sc->nfe_intrhand[i] = NULL; 737 } 738 } 739 740 if (sc->nfe_msi == 0 && sc->nfe_msix == 0) { 741 if (sc->nfe_irq[0] != NULL) 742 bus_release_resource(dev, SYS_RES_IRQ, 0, 743 sc->nfe_irq[0]); 744 } else { 745 for (i = 0, rid = 1; i < NFE_MSI_MESSAGES; i++, rid++) { 746 if (sc->nfe_irq[i] != NULL) { 747 bus_release_resource(dev, SYS_RES_IRQ, rid, 748 sc->nfe_irq[i]); 749 sc->nfe_irq[i] = NULL; 750 } 751 } 752 pci_release_msi(dev); 753 } 754 if (sc->nfe_msix_pba_res != NULL) { 755 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(3), 756 sc->nfe_msix_pba_res); 757 sc->nfe_msix_pba_res = NULL; 758 } 759 if (sc->nfe_msix_res != NULL) { 760 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(2), 761 sc->nfe_msix_res); 762 sc->nfe_msix_res = NULL; 763 } 764 if (sc->nfe_res[0] != NULL) { 765 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(0), 766 sc->nfe_res[0]); 767 sc->nfe_res[0] = NULL; 768 } 769 770 nfe_free_tx_ring(sc, &sc->txq); 771 nfe_free_rx_ring(sc, &sc->rxq); 772 nfe_free_jrx_ring(sc, &sc->jrxq); 773 774 if (sc->nfe_parent_tag) { 775 bus_dma_tag_destroy(sc->nfe_parent_tag); 776 sc->nfe_parent_tag = NULL; 777 } 778 779 mtx_destroy(&sc->nfe_mtx); 780 781 return (0); 782 } 783 784 static int 785 nfe_suspend(device_t dev) 786 { 787 struct nfe_softc *sc; 788 789 sc = device_get_softc(dev); 790 791 NFE_LOCK(sc); 792 nfe_stop(sc->nfe_ifp); 793 nfe_set_wol(sc); 794 sc->nfe_suspended = 1; 795 NFE_UNLOCK(sc); 796 797 return (0); 798 } 799 800 static int 801 nfe_resume(device_t dev) 802 { 803 struct nfe_softc *sc; 804 if_t ifp; 805 806 sc = device_get_softc(dev); 807 808 NFE_LOCK(sc); 809 nfe_power(sc); 810 ifp = sc->nfe_ifp; 811 if (if_getflags(ifp) & IFF_UP) 812 nfe_init_locked(sc); 813 sc->nfe_suspended = 0; 814 NFE_UNLOCK(sc); 815 816 return (0); 817 } 818 819 static int 820 nfe_can_use_msix(struct nfe_softc *sc) 821 { 822 static struct msix_blacklist { 823 char *maker; 824 char *product; 825 } msix_blacklists[] = { 826 { "ASUSTeK Computer INC.", "P5N32-SLI PREMIUM" } 827 }; 828 829 struct msix_blacklist *mblp; 830 char *maker, *product; 831 int count, n, use_msix; 832 833 /* 834 * Search base board manufacturer and product name table 835 * to see this system has a known MSI/MSI-X issue. 836 */ 837 maker = kern_getenv("smbios.planar.maker"); 838 product = kern_getenv("smbios.planar.product"); 839 use_msix = 1; 840 if (maker != NULL && product != NULL) { 841 count = nitems(msix_blacklists); 842 mblp = msix_blacklists; 843 for (n = 0; n < count; n++) { 844 if (strcmp(maker, mblp->maker) == 0 && 845 strcmp(product, mblp->product) == 0) { 846 use_msix = 0; 847 break; 848 } 849 mblp++; 850 } 851 } 852 if (maker != NULL) 853 freeenv(maker); 854 if (product != NULL) 855 freeenv(product); 856 857 return (use_msix); 858 } 859 860 /* Take PHY/NIC out of powerdown, from Linux */ 861 static void 862 nfe_power(struct nfe_softc *sc) 863 { 864 uint32_t pwr; 865 866 if ((sc->nfe_flags & NFE_PWR_MGMT) == 0) 867 return; 868 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_RESET | NFE_RXTX_BIT2); 869 NFE_WRITE(sc, NFE_MAC_RESET, NFE_MAC_RESET_MAGIC); 870 DELAY(100); 871 NFE_WRITE(sc, NFE_MAC_RESET, 0); 872 DELAY(100); 873 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_BIT2); 874 pwr = NFE_READ(sc, NFE_PWR2_CTL); 875 pwr &= ~NFE_PWR2_WAKEUP_MASK; 876 if (sc->nfe_revid >= 0xa3 && 877 (sc->nfe_devid == PCI_PRODUCT_NVIDIA_NFORCE430_LAN1 || 878 sc->nfe_devid == PCI_PRODUCT_NVIDIA_NFORCE430_LAN2)) 879 pwr |= NFE_PWR2_REVA3; 880 NFE_WRITE(sc, NFE_PWR2_CTL, pwr); 881 } 882 883 static void 884 nfe_miibus_statchg(device_t dev) 885 { 886 struct nfe_softc *sc; 887 struct mii_data *mii; 888 if_t ifp; 889 uint32_t rxctl, txctl; 890 891 sc = device_get_softc(dev); 892 893 mii = device_get_softc(sc->nfe_miibus); 894 ifp = sc->nfe_ifp; 895 896 sc->nfe_link = 0; 897 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 898 (IFM_ACTIVE | IFM_AVALID)) { 899 switch (IFM_SUBTYPE(mii->mii_media_active)) { 900 case IFM_10_T: 901 case IFM_100_TX: 902 case IFM_1000_T: 903 sc->nfe_link = 1; 904 break; 905 default: 906 break; 907 } 908 } 909 910 nfe_mac_config(sc, mii); 911 txctl = NFE_READ(sc, NFE_TX_CTL); 912 rxctl = NFE_READ(sc, NFE_RX_CTL); 913 if (sc->nfe_link != 0 && (if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 914 txctl |= NFE_TX_START; 915 rxctl |= NFE_RX_START; 916 } else { 917 txctl &= ~NFE_TX_START; 918 rxctl &= ~NFE_RX_START; 919 } 920 NFE_WRITE(sc, NFE_TX_CTL, txctl); 921 NFE_WRITE(sc, NFE_RX_CTL, rxctl); 922 } 923 924 static void 925 nfe_mac_config(struct nfe_softc *sc, struct mii_data *mii) 926 { 927 uint32_t link, misc, phy, seed; 928 uint32_t val; 929 930 NFE_LOCK_ASSERT(sc); 931 932 phy = NFE_READ(sc, NFE_PHY_IFACE); 933 phy &= ~(NFE_PHY_HDX | NFE_PHY_100TX | NFE_PHY_1000T); 934 935 seed = NFE_READ(sc, NFE_RNDSEED); 936 seed &= ~NFE_SEED_MASK; 937 938 misc = NFE_MISC1_MAGIC; 939 link = NFE_MEDIA_SET; 940 941 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) == 0) { 942 phy |= NFE_PHY_HDX; /* half-duplex */ 943 misc |= NFE_MISC1_HDX; 944 } 945 946 switch (IFM_SUBTYPE(mii->mii_media_active)) { 947 case IFM_1000_T: /* full-duplex only */ 948 link |= NFE_MEDIA_1000T; 949 seed |= NFE_SEED_1000T; 950 phy |= NFE_PHY_1000T; 951 break; 952 case IFM_100_TX: 953 link |= NFE_MEDIA_100TX; 954 seed |= NFE_SEED_100TX; 955 phy |= NFE_PHY_100TX; 956 break; 957 case IFM_10_T: 958 link |= NFE_MEDIA_10T; 959 seed |= NFE_SEED_10T; 960 break; 961 } 962 963 if ((phy & 0x10000000) != 0) { 964 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) 965 val = NFE_R1_MAGIC_1000; 966 else 967 val = NFE_R1_MAGIC_10_100; 968 } else 969 val = NFE_R1_MAGIC_DEFAULT; 970 NFE_WRITE(sc, NFE_SETUP_R1, val); 971 972 NFE_WRITE(sc, NFE_RNDSEED, seed); /* XXX: gigabit NICs only? */ 973 974 NFE_WRITE(sc, NFE_PHY_IFACE, phy); 975 NFE_WRITE(sc, NFE_MISC1, misc); 976 NFE_WRITE(sc, NFE_LINKSPEED, link); 977 978 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 979 /* It seems all hardwares supports Rx pause frames. */ 980 val = NFE_READ(sc, NFE_RXFILTER); 981 if ((IFM_OPTIONS(mii->mii_media_active) & 982 IFM_ETH_RXPAUSE) != 0) 983 val |= NFE_PFF_RX_PAUSE; 984 else 985 val &= ~NFE_PFF_RX_PAUSE; 986 NFE_WRITE(sc, NFE_RXFILTER, val); 987 if ((sc->nfe_flags & NFE_TX_FLOW_CTRL) != 0) { 988 val = NFE_READ(sc, NFE_MISC1); 989 if ((IFM_OPTIONS(mii->mii_media_active) & 990 IFM_ETH_TXPAUSE) != 0) { 991 NFE_WRITE(sc, NFE_TX_PAUSE_FRAME, 992 NFE_TX_PAUSE_FRAME_ENABLE); 993 val |= NFE_MISC1_TX_PAUSE; 994 } else { 995 val &= ~NFE_MISC1_TX_PAUSE; 996 NFE_WRITE(sc, NFE_TX_PAUSE_FRAME, 997 NFE_TX_PAUSE_FRAME_DISABLE); 998 } 999 NFE_WRITE(sc, NFE_MISC1, val); 1000 } 1001 } else { 1002 /* disable rx/tx pause frames */ 1003 val = NFE_READ(sc, NFE_RXFILTER); 1004 val &= ~NFE_PFF_RX_PAUSE; 1005 NFE_WRITE(sc, NFE_RXFILTER, val); 1006 if ((sc->nfe_flags & NFE_TX_FLOW_CTRL) != 0) { 1007 NFE_WRITE(sc, NFE_TX_PAUSE_FRAME, 1008 NFE_TX_PAUSE_FRAME_DISABLE); 1009 val = NFE_READ(sc, NFE_MISC1); 1010 val &= ~NFE_MISC1_TX_PAUSE; 1011 NFE_WRITE(sc, NFE_MISC1, val); 1012 } 1013 } 1014 } 1015 1016 static int 1017 nfe_miibus_readreg(device_t dev, int phy, int reg) 1018 { 1019 struct nfe_softc *sc = device_get_softc(dev); 1020 uint32_t val; 1021 int ntries; 1022 1023 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 1024 1025 if (NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY) { 1026 NFE_WRITE(sc, NFE_PHY_CTL, NFE_PHY_BUSY); 1027 DELAY(100); 1028 } 1029 1030 NFE_WRITE(sc, NFE_PHY_CTL, (phy << NFE_PHYADD_SHIFT) | reg); 1031 1032 for (ntries = 0; ntries < NFE_TIMEOUT; ntries++) { 1033 DELAY(100); 1034 if (!(NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY)) 1035 break; 1036 } 1037 if (ntries == NFE_TIMEOUT) { 1038 DPRINTFN(sc, 2, "timeout waiting for PHY\n"); 1039 return 0; 1040 } 1041 1042 if (NFE_READ(sc, NFE_PHY_STATUS) & NFE_PHY_ERROR) { 1043 DPRINTFN(sc, 2, "could not read PHY\n"); 1044 return 0; 1045 } 1046 1047 val = NFE_READ(sc, NFE_PHY_DATA); 1048 if (val != 0xffffffff && val != 0) 1049 sc->mii_phyaddr = phy; 1050 1051 DPRINTFN(sc, 2, "mii read phy %d reg 0x%x ret 0x%x\n", phy, reg, val); 1052 1053 return (val); 1054 } 1055 1056 static int 1057 nfe_miibus_writereg(device_t dev, int phy, int reg, int val) 1058 { 1059 struct nfe_softc *sc = device_get_softc(dev); 1060 uint32_t ctl; 1061 int ntries; 1062 1063 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 1064 1065 if (NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY) { 1066 NFE_WRITE(sc, NFE_PHY_CTL, NFE_PHY_BUSY); 1067 DELAY(100); 1068 } 1069 1070 NFE_WRITE(sc, NFE_PHY_DATA, val); 1071 ctl = NFE_PHY_WRITE | (phy << NFE_PHYADD_SHIFT) | reg; 1072 NFE_WRITE(sc, NFE_PHY_CTL, ctl); 1073 1074 for (ntries = 0; ntries < NFE_TIMEOUT; ntries++) { 1075 DELAY(100); 1076 if (!(NFE_READ(sc, NFE_PHY_CTL) & NFE_PHY_BUSY)) 1077 break; 1078 } 1079 #ifdef NFE_DEBUG 1080 if (nfedebug >= 2 && ntries == NFE_TIMEOUT) 1081 device_printf(sc->nfe_dev, "could not write to PHY\n"); 1082 #endif 1083 return (0); 1084 } 1085 1086 struct nfe_dmamap_arg { 1087 bus_addr_t nfe_busaddr; 1088 }; 1089 1090 static int 1091 nfe_alloc_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1092 { 1093 struct nfe_dmamap_arg ctx; 1094 struct nfe_rx_data *data; 1095 void *desc; 1096 int i, error, descsize; 1097 1098 if (sc->nfe_flags & NFE_40BIT_ADDR) { 1099 desc = ring->desc64; 1100 descsize = sizeof (struct nfe_desc64); 1101 } else { 1102 desc = ring->desc32; 1103 descsize = sizeof (struct nfe_desc32); 1104 } 1105 1106 ring->cur = ring->next = 0; 1107 1108 error = bus_dma_tag_create(sc->nfe_parent_tag, 1109 NFE_RING_ALIGN, 0, /* alignment, boundary */ 1110 BUS_SPACE_MAXADDR, /* lowaddr */ 1111 BUS_SPACE_MAXADDR, /* highaddr */ 1112 NULL, NULL, /* filter, filterarg */ 1113 NFE_RX_RING_COUNT * descsize, 1, /* maxsize, nsegments */ 1114 NFE_RX_RING_COUNT * descsize, /* maxsegsize */ 1115 0, /* flags */ 1116 NULL, NULL, /* lockfunc, lockarg */ 1117 &ring->rx_desc_tag); 1118 if (error != 0) { 1119 device_printf(sc->nfe_dev, "could not create desc DMA tag\n"); 1120 goto fail; 1121 } 1122 1123 /* allocate memory to desc */ 1124 error = bus_dmamem_alloc(ring->rx_desc_tag, &desc, BUS_DMA_WAITOK | 1125 BUS_DMA_COHERENT | BUS_DMA_ZERO, &ring->rx_desc_map); 1126 if (error != 0) { 1127 device_printf(sc->nfe_dev, "could not create desc DMA map\n"); 1128 goto fail; 1129 } 1130 if (sc->nfe_flags & NFE_40BIT_ADDR) 1131 ring->desc64 = desc; 1132 else 1133 ring->desc32 = desc; 1134 1135 /* map desc to device visible address space */ 1136 ctx.nfe_busaddr = 0; 1137 error = bus_dmamap_load(ring->rx_desc_tag, ring->rx_desc_map, desc, 1138 NFE_RX_RING_COUNT * descsize, nfe_dma_map_segs, &ctx, 0); 1139 if (error != 0) { 1140 device_printf(sc->nfe_dev, "could not load desc DMA map\n"); 1141 goto fail; 1142 } 1143 ring->physaddr = ctx.nfe_busaddr; 1144 1145 error = bus_dma_tag_create(sc->nfe_parent_tag, 1146 1, 0, /* alignment, boundary */ 1147 BUS_SPACE_MAXADDR, /* lowaddr */ 1148 BUS_SPACE_MAXADDR, /* highaddr */ 1149 NULL, NULL, /* filter, filterarg */ 1150 MCLBYTES, 1, /* maxsize, nsegments */ 1151 MCLBYTES, /* maxsegsize */ 1152 0, /* flags */ 1153 NULL, NULL, /* lockfunc, lockarg */ 1154 &ring->rx_data_tag); 1155 if (error != 0) { 1156 device_printf(sc->nfe_dev, "could not create Rx DMA tag\n"); 1157 goto fail; 1158 } 1159 1160 error = bus_dmamap_create(ring->rx_data_tag, 0, &ring->rx_spare_map); 1161 if (error != 0) { 1162 device_printf(sc->nfe_dev, 1163 "could not create Rx DMA spare map\n"); 1164 goto fail; 1165 } 1166 1167 /* 1168 * Pre-allocate Rx buffers and populate Rx ring. 1169 */ 1170 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1171 data = &sc->rxq.data[i]; 1172 data->rx_data_map = NULL; 1173 data->m = NULL; 1174 error = bus_dmamap_create(ring->rx_data_tag, 0, 1175 &data->rx_data_map); 1176 if (error != 0) { 1177 device_printf(sc->nfe_dev, 1178 "could not create Rx DMA map\n"); 1179 goto fail; 1180 } 1181 } 1182 1183 fail: 1184 return (error); 1185 } 1186 1187 static void 1188 nfe_alloc_jrx_ring(struct nfe_softc *sc, struct nfe_jrx_ring *ring) 1189 { 1190 struct nfe_dmamap_arg ctx; 1191 struct nfe_rx_data *data; 1192 void *desc; 1193 int i, error, descsize; 1194 1195 if ((sc->nfe_flags & NFE_JUMBO_SUP) == 0) 1196 return; 1197 if (jumbo_disable != 0) { 1198 device_printf(sc->nfe_dev, "disabling jumbo frame support\n"); 1199 sc->nfe_jumbo_disable = 1; 1200 return; 1201 } 1202 1203 if (sc->nfe_flags & NFE_40BIT_ADDR) { 1204 desc = ring->jdesc64; 1205 descsize = sizeof (struct nfe_desc64); 1206 } else { 1207 desc = ring->jdesc32; 1208 descsize = sizeof (struct nfe_desc32); 1209 } 1210 1211 ring->jcur = ring->jnext = 0; 1212 1213 /* Create DMA tag for jumbo Rx ring. */ 1214 error = bus_dma_tag_create(sc->nfe_parent_tag, 1215 NFE_RING_ALIGN, 0, /* alignment, boundary */ 1216 BUS_SPACE_MAXADDR, /* lowaddr */ 1217 BUS_SPACE_MAXADDR, /* highaddr */ 1218 NULL, NULL, /* filter, filterarg */ 1219 NFE_JUMBO_RX_RING_COUNT * descsize, /* maxsize */ 1220 1, /* nsegments */ 1221 NFE_JUMBO_RX_RING_COUNT * descsize, /* maxsegsize */ 1222 0, /* flags */ 1223 NULL, NULL, /* lockfunc, lockarg */ 1224 &ring->jrx_desc_tag); 1225 if (error != 0) { 1226 device_printf(sc->nfe_dev, 1227 "could not create jumbo ring DMA tag\n"); 1228 goto fail; 1229 } 1230 1231 /* Create DMA tag for jumbo Rx buffers. */ 1232 error = bus_dma_tag_create(sc->nfe_parent_tag, 1233 1, 0, /* alignment, boundary */ 1234 BUS_SPACE_MAXADDR, /* lowaddr */ 1235 BUS_SPACE_MAXADDR, /* highaddr */ 1236 NULL, NULL, /* filter, filterarg */ 1237 MJUM9BYTES, /* maxsize */ 1238 1, /* nsegments */ 1239 MJUM9BYTES, /* maxsegsize */ 1240 0, /* flags */ 1241 NULL, NULL, /* lockfunc, lockarg */ 1242 &ring->jrx_data_tag); 1243 if (error != 0) { 1244 device_printf(sc->nfe_dev, 1245 "could not create jumbo Rx buffer DMA tag\n"); 1246 goto fail; 1247 } 1248 1249 /* Allocate DMA'able memory and load the DMA map for jumbo Rx ring. */ 1250 error = bus_dmamem_alloc(ring->jrx_desc_tag, &desc, BUS_DMA_WAITOK | 1251 BUS_DMA_COHERENT | BUS_DMA_ZERO, &ring->jrx_desc_map); 1252 if (error != 0) { 1253 device_printf(sc->nfe_dev, 1254 "could not allocate DMA'able memory for jumbo Rx ring\n"); 1255 goto fail; 1256 } 1257 if (sc->nfe_flags & NFE_40BIT_ADDR) 1258 ring->jdesc64 = desc; 1259 else 1260 ring->jdesc32 = desc; 1261 1262 ctx.nfe_busaddr = 0; 1263 error = bus_dmamap_load(ring->jrx_desc_tag, ring->jrx_desc_map, desc, 1264 NFE_JUMBO_RX_RING_COUNT * descsize, nfe_dma_map_segs, &ctx, 0); 1265 if (error != 0) { 1266 device_printf(sc->nfe_dev, 1267 "could not load DMA'able memory for jumbo Rx ring\n"); 1268 goto fail; 1269 } 1270 ring->jphysaddr = ctx.nfe_busaddr; 1271 1272 /* Create DMA maps for jumbo Rx buffers. */ 1273 error = bus_dmamap_create(ring->jrx_data_tag, 0, &ring->jrx_spare_map); 1274 if (error != 0) { 1275 device_printf(sc->nfe_dev, 1276 "could not create jumbo Rx DMA spare map\n"); 1277 goto fail; 1278 } 1279 1280 for (i = 0; i < NFE_JUMBO_RX_RING_COUNT; i++) { 1281 data = &sc->jrxq.jdata[i]; 1282 data->rx_data_map = NULL; 1283 data->m = NULL; 1284 error = bus_dmamap_create(ring->jrx_data_tag, 0, 1285 &data->rx_data_map); 1286 if (error != 0) { 1287 device_printf(sc->nfe_dev, 1288 "could not create jumbo Rx DMA map\n"); 1289 goto fail; 1290 } 1291 } 1292 1293 return; 1294 1295 fail: 1296 /* 1297 * Running without jumbo frame support is ok for most cases 1298 * so don't fail on creating dma tag/map for jumbo frame. 1299 */ 1300 nfe_free_jrx_ring(sc, ring); 1301 device_printf(sc->nfe_dev, "disabling jumbo frame support due to " 1302 "resource shortage\n"); 1303 sc->nfe_jumbo_disable = 1; 1304 } 1305 1306 static int 1307 nfe_init_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1308 { 1309 void *desc; 1310 size_t descsize; 1311 int i; 1312 1313 ring->cur = ring->next = 0; 1314 if (sc->nfe_flags & NFE_40BIT_ADDR) { 1315 desc = ring->desc64; 1316 descsize = sizeof (struct nfe_desc64); 1317 } else { 1318 desc = ring->desc32; 1319 descsize = sizeof (struct nfe_desc32); 1320 } 1321 bzero(desc, descsize * NFE_RX_RING_COUNT); 1322 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1323 if (nfe_newbuf(sc, i) != 0) 1324 return (ENOBUFS); 1325 } 1326 1327 bus_dmamap_sync(ring->rx_desc_tag, ring->rx_desc_map, 1328 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1329 1330 return (0); 1331 } 1332 1333 static int 1334 nfe_init_jrx_ring(struct nfe_softc *sc, struct nfe_jrx_ring *ring) 1335 { 1336 void *desc; 1337 size_t descsize; 1338 int i; 1339 1340 ring->jcur = ring->jnext = 0; 1341 if (sc->nfe_flags & NFE_40BIT_ADDR) { 1342 desc = ring->jdesc64; 1343 descsize = sizeof (struct nfe_desc64); 1344 } else { 1345 desc = ring->jdesc32; 1346 descsize = sizeof (struct nfe_desc32); 1347 } 1348 bzero(desc, descsize * NFE_JUMBO_RX_RING_COUNT); 1349 for (i = 0; i < NFE_JUMBO_RX_RING_COUNT; i++) { 1350 if (nfe_jnewbuf(sc, i) != 0) 1351 return (ENOBUFS); 1352 } 1353 1354 bus_dmamap_sync(ring->jrx_desc_tag, ring->jrx_desc_map, 1355 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1356 1357 return (0); 1358 } 1359 1360 static void 1361 nfe_free_rx_ring(struct nfe_softc *sc, struct nfe_rx_ring *ring) 1362 { 1363 struct nfe_rx_data *data; 1364 void *desc; 1365 int i; 1366 1367 if (sc->nfe_flags & NFE_40BIT_ADDR) 1368 desc = ring->desc64; 1369 else 1370 desc = ring->desc32; 1371 1372 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 1373 data = &ring->data[i]; 1374 if (data->rx_data_map != NULL) { 1375 bus_dmamap_destroy(ring->rx_data_tag, 1376 data->rx_data_map); 1377 data->rx_data_map = NULL; 1378 } 1379 if (data->m != NULL) { 1380 m_freem(data->m); 1381 data->m = NULL; 1382 } 1383 } 1384 if (ring->rx_data_tag != NULL) { 1385 if (ring->rx_spare_map != NULL) { 1386 bus_dmamap_destroy(ring->rx_data_tag, 1387 ring->rx_spare_map); 1388 ring->rx_spare_map = NULL; 1389 } 1390 bus_dma_tag_destroy(ring->rx_data_tag); 1391 ring->rx_data_tag = NULL; 1392 } 1393 1394 if (desc != NULL) { 1395 bus_dmamap_unload(ring->rx_desc_tag, ring->rx_desc_map); 1396 bus_dmamem_free(ring->rx_desc_tag, desc, ring->rx_desc_map); 1397 ring->desc64 = NULL; 1398 ring->desc32 = NULL; 1399 } 1400 if (ring->rx_desc_tag != NULL) { 1401 bus_dma_tag_destroy(ring->rx_desc_tag); 1402 ring->rx_desc_tag = NULL; 1403 } 1404 } 1405 1406 static void 1407 nfe_free_jrx_ring(struct nfe_softc *sc, struct nfe_jrx_ring *ring) 1408 { 1409 struct nfe_rx_data *data; 1410 void *desc; 1411 int i, descsize; 1412 1413 if ((sc->nfe_flags & NFE_JUMBO_SUP) == 0) 1414 return; 1415 1416 if (sc->nfe_flags & NFE_40BIT_ADDR) { 1417 desc = ring->jdesc64; 1418 descsize = sizeof (struct nfe_desc64); 1419 } else { 1420 desc = ring->jdesc32; 1421 descsize = sizeof (struct nfe_desc32); 1422 } 1423 1424 for (i = 0; i < NFE_JUMBO_RX_RING_COUNT; i++) { 1425 data = &ring->jdata[i]; 1426 if (data->rx_data_map != NULL) { 1427 bus_dmamap_destroy(ring->jrx_data_tag, 1428 data->rx_data_map); 1429 data->rx_data_map = NULL; 1430 } 1431 if (data->m != NULL) { 1432 m_freem(data->m); 1433 data->m = NULL; 1434 } 1435 } 1436 if (ring->jrx_data_tag != NULL) { 1437 if (ring->jrx_spare_map != NULL) { 1438 bus_dmamap_destroy(ring->jrx_data_tag, 1439 ring->jrx_spare_map); 1440 ring->jrx_spare_map = NULL; 1441 } 1442 bus_dma_tag_destroy(ring->jrx_data_tag); 1443 ring->jrx_data_tag = NULL; 1444 } 1445 1446 if (desc != NULL) { 1447 bus_dmamap_unload(ring->jrx_desc_tag, ring->jrx_desc_map); 1448 bus_dmamem_free(ring->jrx_desc_tag, desc, ring->jrx_desc_map); 1449 ring->jdesc64 = NULL; 1450 ring->jdesc32 = NULL; 1451 } 1452 1453 if (ring->jrx_desc_tag != NULL) { 1454 bus_dma_tag_destroy(ring->jrx_desc_tag); 1455 ring->jrx_desc_tag = NULL; 1456 } 1457 } 1458 1459 static int 1460 nfe_alloc_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1461 { 1462 struct nfe_dmamap_arg ctx; 1463 int i, error; 1464 void *desc; 1465 int descsize; 1466 1467 if (sc->nfe_flags & NFE_40BIT_ADDR) { 1468 desc = ring->desc64; 1469 descsize = sizeof (struct nfe_desc64); 1470 } else { 1471 desc = ring->desc32; 1472 descsize = sizeof (struct nfe_desc32); 1473 } 1474 1475 ring->queued = 0; 1476 ring->cur = ring->next = 0; 1477 1478 error = bus_dma_tag_create(sc->nfe_parent_tag, 1479 NFE_RING_ALIGN, 0, /* alignment, boundary */ 1480 BUS_SPACE_MAXADDR, /* lowaddr */ 1481 BUS_SPACE_MAXADDR, /* highaddr */ 1482 NULL, NULL, /* filter, filterarg */ 1483 NFE_TX_RING_COUNT * descsize, 1, /* maxsize, nsegments */ 1484 NFE_TX_RING_COUNT * descsize, /* maxsegsize */ 1485 0, /* flags */ 1486 NULL, NULL, /* lockfunc, lockarg */ 1487 &ring->tx_desc_tag); 1488 if (error != 0) { 1489 device_printf(sc->nfe_dev, "could not create desc DMA tag\n"); 1490 goto fail; 1491 } 1492 1493 error = bus_dmamem_alloc(ring->tx_desc_tag, &desc, BUS_DMA_WAITOK | 1494 BUS_DMA_COHERENT | BUS_DMA_ZERO, &ring->tx_desc_map); 1495 if (error != 0) { 1496 device_printf(sc->nfe_dev, "could not create desc DMA map\n"); 1497 goto fail; 1498 } 1499 if (sc->nfe_flags & NFE_40BIT_ADDR) 1500 ring->desc64 = desc; 1501 else 1502 ring->desc32 = desc; 1503 1504 ctx.nfe_busaddr = 0; 1505 error = bus_dmamap_load(ring->tx_desc_tag, ring->tx_desc_map, desc, 1506 NFE_TX_RING_COUNT * descsize, nfe_dma_map_segs, &ctx, 0); 1507 if (error != 0) { 1508 device_printf(sc->nfe_dev, "could not load desc DMA map\n"); 1509 goto fail; 1510 } 1511 ring->physaddr = ctx.nfe_busaddr; 1512 1513 error = bus_dma_tag_create(sc->nfe_parent_tag, 1514 1, 0, 1515 BUS_SPACE_MAXADDR, 1516 BUS_SPACE_MAXADDR, 1517 NULL, NULL, 1518 NFE_TSO_MAXSIZE, 1519 NFE_MAX_SCATTER, 1520 NFE_TSO_MAXSGSIZE, 1521 0, 1522 NULL, NULL, 1523 &ring->tx_data_tag); 1524 if (error != 0) { 1525 device_printf(sc->nfe_dev, "could not create Tx DMA tag\n"); 1526 goto fail; 1527 } 1528 1529 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1530 error = bus_dmamap_create(ring->tx_data_tag, 0, 1531 &ring->data[i].tx_data_map); 1532 if (error != 0) { 1533 device_printf(sc->nfe_dev, 1534 "could not create Tx DMA map\n"); 1535 goto fail; 1536 } 1537 } 1538 1539 fail: 1540 return (error); 1541 } 1542 1543 static void 1544 nfe_init_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1545 { 1546 void *desc; 1547 size_t descsize; 1548 1549 sc->nfe_force_tx = 0; 1550 ring->queued = 0; 1551 ring->cur = ring->next = 0; 1552 if (sc->nfe_flags & NFE_40BIT_ADDR) { 1553 desc = ring->desc64; 1554 descsize = sizeof (struct nfe_desc64); 1555 } else { 1556 desc = ring->desc32; 1557 descsize = sizeof (struct nfe_desc32); 1558 } 1559 bzero(desc, descsize * NFE_TX_RING_COUNT); 1560 1561 bus_dmamap_sync(ring->tx_desc_tag, ring->tx_desc_map, 1562 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1563 } 1564 1565 static void 1566 nfe_free_tx_ring(struct nfe_softc *sc, struct nfe_tx_ring *ring) 1567 { 1568 struct nfe_tx_data *data; 1569 void *desc; 1570 int i, descsize; 1571 1572 if (sc->nfe_flags & NFE_40BIT_ADDR) { 1573 desc = ring->desc64; 1574 descsize = sizeof (struct nfe_desc64); 1575 } else { 1576 desc = ring->desc32; 1577 descsize = sizeof (struct nfe_desc32); 1578 } 1579 1580 for (i = 0; i < NFE_TX_RING_COUNT; i++) { 1581 data = &ring->data[i]; 1582 1583 if (data->m != NULL) { 1584 bus_dmamap_sync(ring->tx_data_tag, data->tx_data_map, 1585 BUS_DMASYNC_POSTWRITE); 1586 bus_dmamap_unload(ring->tx_data_tag, data->tx_data_map); 1587 m_freem(data->m); 1588 data->m = NULL; 1589 } 1590 if (data->tx_data_map != NULL) { 1591 bus_dmamap_destroy(ring->tx_data_tag, 1592 data->tx_data_map); 1593 data->tx_data_map = NULL; 1594 } 1595 } 1596 1597 if (ring->tx_data_tag != NULL) { 1598 bus_dma_tag_destroy(ring->tx_data_tag); 1599 ring->tx_data_tag = NULL; 1600 } 1601 1602 if (desc != NULL) { 1603 bus_dmamap_sync(ring->tx_desc_tag, ring->tx_desc_map, 1604 BUS_DMASYNC_POSTWRITE); 1605 bus_dmamap_unload(ring->tx_desc_tag, ring->tx_desc_map); 1606 bus_dmamem_free(ring->tx_desc_tag, desc, ring->tx_desc_map); 1607 ring->desc64 = NULL; 1608 ring->desc32 = NULL; 1609 bus_dma_tag_destroy(ring->tx_desc_tag); 1610 ring->tx_desc_tag = NULL; 1611 } 1612 } 1613 1614 #ifdef DEVICE_POLLING 1615 static poll_handler_t nfe_poll; 1616 1617 static int 1618 nfe_poll(if_t ifp, enum poll_cmd cmd, int count) 1619 { 1620 struct nfe_softc *sc = if_getsoftc(ifp); 1621 uint32_t r; 1622 int rx_npkts = 0; 1623 1624 NFE_LOCK(sc); 1625 1626 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) { 1627 NFE_UNLOCK(sc); 1628 return (rx_npkts); 1629 } 1630 1631 if (sc->nfe_framesize > MCLBYTES - ETHER_HDR_LEN) 1632 rx_npkts = nfe_jrxeof(sc, count, &rx_npkts); 1633 else 1634 rx_npkts = nfe_rxeof(sc, count, &rx_npkts); 1635 nfe_txeof(sc); 1636 if (!if_sendq_empty(ifp)) 1637 nfe_start_locked(ifp); 1638 1639 if (cmd == POLL_AND_CHECK_STATUS) { 1640 if ((r = NFE_READ(sc, sc->nfe_irq_status)) == 0) { 1641 NFE_UNLOCK(sc); 1642 return (rx_npkts); 1643 } 1644 NFE_WRITE(sc, sc->nfe_irq_status, r); 1645 1646 if (r & NFE_IRQ_LINK) { 1647 NFE_READ(sc, NFE_PHY_STATUS); 1648 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 1649 DPRINTF(sc, "link state changed\n"); 1650 } 1651 } 1652 NFE_UNLOCK(sc); 1653 return (rx_npkts); 1654 } 1655 #endif /* DEVICE_POLLING */ 1656 1657 static void 1658 nfe_set_intr(struct nfe_softc *sc) 1659 { 1660 1661 if (sc->nfe_msi != 0) 1662 NFE_WRITE(sc, NFE_IRQ_MASK, NFE_IRQ_WANTED); 1663 } 1664 1665 /* In MSIX, a write to mask reegisters behaves as XOR. */ 1666 static __inline void 1667 nfe_enable_intr(struct nfe_softc *sc) 1668 { 1669 1670 if (sc->nfe_msix != 0) { 1671 /* XXX Should have a better way to enable interrupts! */ 1672 if (NFE_READ(sc, sc->nfe_irq_mask) == 0) 1673 NFE_WRITE(sc, sc->nfe_irq_mask, sc->nfe_intrs); 1674 } else 1675 NFE_WRITE(sc, sc->nfe_irq_mask, sc->nfe_intrs); 1676 } 1677 1678 static __inline void 1679 nfe_disable_intr(struct nfe_softc *sc) 1680 { 1681 1682 if (sc->nfe_msix != 0) { 1683 /* XXX Should have a better way to disable interrupts! */ 1684 if (NFE_READ(sc, sc->nfe_irq_mask) != 0) 1685 NFE_WRITE(sc, sc->nfe_irq_mask, sc->nfe_nointrs); 1686 } else 1687 NFE_WRITE(sc, sc->nfe_irq_mask, sc->nfe_nointrs); 1688 } 1689 1690 static int 1691 nfe_ioctl(if_t ifp, u_long cmd, caddr_t data) 1692 { 1693 struct nfe_softc *sc; 1694 struct ifreq *ifr; 1695 struct mii_data *mii; 1696 int error, init, mask; 1697 1698 sc = if_getsoftc(ifp); 1699 ifr = (struct ifreq *) data; 1700 error = 0; 1701 init = 0; 1702 switch (cmd) { 1703 case SIOCSIFMTU: 1704 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > NFE_JUMBO_MTU) 1705 error = EINVAL; 1706 else if (if_getmtu(ifp) != ifr->ifr_mtu) { 1707 if ((((sc->nfe_flags & NFE_JUMBO_SUP) == 0) || 1708 (sc->nfe_jumbo_disable != 0)) && 1709 ifr->ifr_mtu > ETHERMTU) 1710 error = EINVAL; 1711 else { 1712 NFE_LOCK(sc); 1713 if_setmtu(ifp, ifr->ifr_mtu); 1714 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 1715 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 1716 nfe_init_locked(sc); 1717 } 1718 NFE_UNLOCK(sc); 1719 } 1720 } 1721 break; 1722 case SIOCSIFFLAGS: 1723 NFE_LOCK(sc); 1724 if (if_getflags(ifp) & IFF_UP) { 1725 /* 1726 * If only the PROMISC or ALLMULTI flag changes, then 1727 * don't do a full re-init of the chip, just update 1728 * the Rx filter. 1729 */ 1730 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) && 1731 ((if_getflags(ifp) ^ sc->nfe_if_flags) & 1732 (IFF_ALLMULTI | IFF_PROMISC)) != 0) 1733 nfe_setmulti(sc); 1734 else 1735 nfe_init_locked(sc); 1736 } else { 1737 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 1738 nfe_stop(ifp); 1739 } 1740 sc->nfe_if_flags = if_getflags(ifp); 1741 NFE_UNLOCK(sc); 1742 error = 0; 1743 break; 1744 case SIOCADDMULTI: 1745 case SIOCDELMULTI: 1746 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 1747 NFE_LOCK(sc); 1748 nfe_setmulti(sc); 1749 NFE_UNLOCK(sc); 1750 error = 0; 1751 } 1752 break; 1753 case SIOCSIFMEDIA: 1754 case SIOCGIFMEDIA: 1755 mii = device_get_softc(sc->nfe_miibus); 1756 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 1757 break; 1758 case SIOCSIFCAP: 1759 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp); 1760 #ifdef DEVICE_POLLING 1761 if ((mask & IFCAP_POLLING) != 0) { 1762 if ((ifr->ifr_reqcap & IFCAP_POLLING) != 0) { 1763 error = ether_poll_register(nfe_poll, ifp); 1764 if (error) 1765 break; 1766 NFE_LOCK(sc); 1767 nfe_disable_intr(sc); 1768 if_setcapenablebit(ifp, IFCAP_POLLING, 0); 1769 NFE_UNLOCK(sc); 1770 } else { 1771 error = ether_poll_deregister(ifp); 1772 /* Enable interrupt even in error case */ 1773 NFE_LOCK(sc); 1774 nfe_enable_intr(sc); 1775 if_setcapenablebit(ifp, 0, IFCAP_POLLING); 1776 NFE_UNLOCK(sc); 1777 } 1778 } 1779 #endif /* DEVICE_POLLING */ 1780 if ((mask & IFCAP_WOL_MAGIC) != 0 && 1781 (if_getcapabilities(ifp) & IFCAP_WOL_MAGIC) != 0) 1782 if_togglecapenable(ifp, IFCAP_WOL_MAGIC); 1783 if ((mask & IFCAP_TXCSUM) != 0 && 1784 (if_getcapabilities(ifp) & IFCAP_TXCSUM) != 0) { 1785 if_togglecapenable(ifp, IFCAP_TXCSUM); 1786 if ((if_getcapenable(ifp) & IFCAP_TXCSUM) != 0) 1787 if_sethwassistbits(ifp, NFE_CSUM_FEATURES, 0); 1788 else 1789 if_sethwassistbits(ifp, 0, NFE_CSUM_FEATURES); 1790 } 1791 if ((mask & IFCAP_RXCSUM) != 0 && 1792 (if_getcapabilities(ifp) & IFCAP_RXCSUM) != 0) { 1793 if_togglecapenable(ifp, IFCAP_RXCSUM); 1794 init++; 1795 } 1796 if ((mask & IFCAP_TSO4) != 0 && 1797 (if_getcapabilities(ifp) & IFCAP_TSO4) != 0) { 1798 if_togglecapenable(ifp, IFCAP_TSO4); 1799 if ((IFCAP_TSO4 & if_getcapenable(ifp)) != 0) 1800 if_sethwassistbits(ifp, CSUM_TSO, 0); 1801 else 1802 if_sethwassistbits(ifp, 0, CSUM_TSO); 1803 } 1804 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 1805 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTSO) != 0) 1806 if_togglecapenable(ifp, IFCAP_VLAN_HWTSO); 1807 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 1808 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTAGGING) != 0) { 1809 if_togglecapenable(ifp, IFCAP_VLAN_HWTAGGING); 1810 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) == 0) 1811 if_setcapenablebit(ifp, 0, IFCAP_VLAN_HWTSO); 1812 init++; 1813 } 1814 /* 1815 * XXX 1816 * It seems that VLAN stripping requires Rx checksum offload. 1817 * Unfortunately FreeBSD has no way to disable only Rx side 1818 * VLAN stripping. So when we know Rx checksum offload is 1819 * disabled turn entire hardware VLAN assist off. 1820 */ 1821 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) == 0) { 1822 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0) 1823 init++; 1824 if_setcapenablebit(ifp, 0, 1825 (IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWTSO)); 1826 } 1827 if (init > 0 && (if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 1828 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 1829 nfe_init(sc); 1830 } 1831 if_vlancap(ifp); 1832 break; 1833 default: 1834 error = ether_ioctl(ifp, cmd, data); 1835 break; 1836 } 1837 1838 return (error); 1839 } 1840 1841 static int 1842 nfe_intr(void *arg) 1843 { 1844 struct nfe_softc *sc; 1845 uint32_t status; 1846 1847 sc = (struct nfe_softc *)arg; 1848 1849 status = NFE_READ(sc, sc->nfe_irq_status); 1850 if (status == 0 || status == 0xffffffff) 1851 return (FILTER_STRAY); 1852 nfe_disable_intr(sc); 1853 taskqueue_enqueue(sc->nfe_tq, &sc->nfe_int_task); 1854 1855 return (FILTER_HANDLED); 1856 } 1857 1858 static void 1859 nfe_int_task(void *arg, int pending) 1860 { 1861 struct nfe_softc *sc = arg; 1862 if_t ifp = sc->nfe_ifp; 1863 uint32_t r; 1864 int domore; 1865 1866 NFE_LOCK(sc); 1867 1868 if ((r = NFE_READ(sc, sc->nfe_irq_status)) == 0) { 1869 nfe_enable_intr(sc); 1870 NFE_UNLOCK(sc); 1871 return; /* not for us */ 1872 } 1873 NFE_WRITE(sc, sc->nfe_irq_status, r); 1874 1875 DPRINTFN(sc, 5, "nfe_intr: interrupt register %x\n", r); 1876 1877 #ifdef DEVICE_POLLING 1878 if (if_getcapenable(ifp) & IFCAP_POLLING) { 1879 NFE_UNLOCK(sc); 1880 return; 1881 } 1882 #endif 1883 1884 if (r & NFE_IRQ_LINK) { 1885 NFE_READ(sc, NFE_PHY_STATUS); 1886 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 1887 DPRINTF(sc, "link state changed\n"); 1888 } 1889 1890 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) { 1891 NFE_UNLOCK(sc); 1892 nfe_disable_intr(sc); 1893 return; 1894 } 1895 1896 domore = 0; 1897 /* check Rx ring */ 1898 if (sc->nfe_framesize > MCLBYTES - ETHER_HDR_LEN) 1899 domore = nfe_jrxeof(sc, sc->nfe_process_limit, NULL); 1900 else 1901 domore = nfe_rxeof(sc, sc->nfe_process_limit, NULL); 1902 /* check Tx ring */ 1903 nfe_txeof(sc); 1904 1905 if (!if_sendq_empty(ifp)) 1906 nfe_start_locked(ifp); 1907 1908 NFE_UNLOCK(sc); 1909 1910 if (domore || (NFE_READ(sc, sc->nfe_irq_status) != 0)) { 1911 taskqueue_enqueue(sc->nfe_tq, &sc->nfe_int_task); 1912 return; 1913 } 1914 1915 /* Reenable interrupts. */ 1916 nfe_enable_intr(sc); 1917 } 1918 1919 static __inline void 1920 nfe_discard_rxbuf(struct nfe_softc *sc, int idx) 1921 { 1922 struct nfe_desc32 *desc32; 1923 struct nfe_desc64 *desc64; 1924 struct nfe_rx_data *data; 1925 struct mbuf *m; 1926 1927 data = &sc->rxq.data[idx]; 1928 m = data->m; 1929 1930 if (sc->nfe_flags & NFE_40BIT_ADDR) { 1931 desc64 = &sc->rxq.desc64[idx]; 1932 /* VLAN packet may have overwritten it. */ 1933 desc64->physaddr[0] = htole32(NFE_ADDR_HI(data->paddr)); 1934 desc64->physaddr[1] = htole32(NFE_ADDR_LO(data->paddr)); 1935 desc64->length = htole16(m->m_len); 1936 desc64->flags = htole16(NFE_RX_READY); 1937 } else { 1938 desc32 = &sc->rxq.desc32[idx]; 1939 desc32->length = htole16(m->m_len); 1940 desc32->flags = htole16(NFE_RX_READY); 1941 } 1942 } 1943 1944 static __inline void 1945 nfe_discard_jrxbuf(struct nfe_softc *sc, int idx) 1946 { 1947 struct nfe_desc32 *desc32; 1948 struct nfe_desc64 *desc64; 1949 struct nfe_rx_data *data; 1950 struct mbuf *m; 1951 1952 data = &sc->jrxq.jdata[idx]; 1953 m = data->m; 1954 1955 if (sc->nfe_flags & NFE_40BIT_ADDR) { 1956 desc64 = &sc->jrxq.jdesc64[idx]; 1957 /* VLAN packet may have overwritten it. */ 1958 desc64->physaddr[0] = htole32(NFE_ADDR_HI(data->paddr)); 1959 desc64->physaddr[1] = htole32(NFE_ADDR_LO(data->paddr)); 1960 desc64->length = htole16(m->m_len); 1961 desc64->flags = htole16(NFE_RX_READY); 1962 } else { 1963 desc32 = &sc->jrxq.jdesc32[idx]; 1964 desc32->length = htole16(m->m_len); 1965 desc32->flags = htole16(NFE_RX_READY); 1966 } 1967 } 1968 1969 static int 1970 nfe_newbuf(struct nfe_softc *sc, int idx) 1971 { 1972 struct nfe_rx_data *data; 1973 struct nfe_desc32 *desc32; 1974 struct nfe_desc64 *desc64; 1975 struct mbuf *m; 1976 bus_dma_segment_t segs[1]; 1977 bus_dmamap_t map; 1978 int nsegs; 1979 1980 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 1981 if (m == NULL) 1982 return (ENOBUFS); 1983 1984 m->m_len = m->m_pkthdr.len = MCLBYTES; 1985 m_adj(m, ETHER_ALIGN); 1986 1987 if (bus_dmamap_load_mbuf_sg(sc->rxq.rx_data_tag, sc->rxq.rx_spare_map, 1988 m, segs, &nsegs, BUS_DMA_NOWAIT) != 0) { 1989 m_freem(m); 1990 return (ENOBUFS); 1991 } 1992 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1993 1994 data = &sc->rxq.data[idx]; 1995 if (data->m != NULL) { 1996 bus_dmamap_sync(sc->rxq.rx_data_tag, data->rx_data_map, 1997 BUS_DMASYNC_POSTREAD); 1998 bus_dmamap_unload(sc->rxq.rx_data_tag, data->rx_data_map); 1999 } 2000 map = data->rx_data_map; 2001 data->rx_data_map = sc->rxq.rx_spare_map; 2002 sc->rxq.rx_spare_map = map; 2003 bus_dmamap_sync(sc->rxq.rx_data_tag, data->rx_data_map, 2004 BUS_DMASYNC_PREREAD); 2005 data->paddr = segs[0].ds_addr; 2006 data->m = m; 2007 /* update mapping address in h/w descriptor */ 2008 if (sc->nfe_flags & NFE_40BIT_ADDR) { 2009 desc64 = &sc->rxq.desc64[idx]; 2010 desc64->physaddr[0] = htole32(NFE_ADDR_HI(segs[0].ds_addr)); 2011 desc64->physaddr[1] = htole32(NFE_ADDR_LO(segs[0].ds_addr)); 2012 desc64->length = htole16(segs[0].ds_len); 2013 desc64->flags = htole16(NFE_RX_READY); 2014 } else { 2015 desc32 = &sc->rxq.desc32[idx]; 2016 desc32->physaddr = htole32(NFE_ADDR_LO(segs[0].ds_addr)); 2017 desc32->length = htole16(segs[0].ds_len); 2018 desc32->flags = htole16(NFE_RX_READY); 2019 } 2020 2021 return (0); 2022 } 2023 2024 static int 2025 nfe_jnewbuf(struct nfe_softc *sc, int idx) 2026 { 2027 struct nfe_rx_data *data; 2028 struct nfe_desc32 *desc32; 2029 struct nfe_desc64 *desc64; 2030 struct mbuf *m; 2031 bus_dma_segment_t segs[1]; 2032 bus_dmamap_t map; 2033 int nsegs; 2034 2035 m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES); 2036 if (m == NULL) 2037 return (ENOBUFS); 2038 m->m_pkthdr.len = m->m_len = MJUM9BYTES; 2039 m_adj(m, ETHER_ALIGN); 2040 2041 if (bus_dmamap_load_mbuf_sg(sc->jrxq.jrx_data_tag, 2042 sc->jrxq.jrx_spare_map, m, segs, &nsegs, BUS_DMA_NOWAIT) != 0) { 2043 m_freem(m); 2044 return (ENOBUFS); 2045 } 2046 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 2047 2048 data = &sc->jrxq.jdata[idx]; 2049 if (data->m != NULL) { 2050 bus_dmamap_sync(sc->jrxq.jrx_data_tag, data->rx_data_map, 2051 BUS_DMASYNC_POSTREAD); 2052 bus_dmamap_unload(sc->jrxq.jrx_data_tag, data->rx_data_map); 2053 } 2054 map = data->rx_data_map; 2055 data->rx_data_map = sc->jrxq.jrx_spare_map; 2056 sc->jrxq.jrx_spare_map = map; 2057 bus_dmamap_sync(sc->jrxq.jrx_data_tag, data->rx_data_map, 2058 BUS_DMASYNC_PREREAD); 2059 data->paddr = segs[0].ds_addr; 2060 data->m = m; 2061 /* update mapping address in h/w descriptor */ 2062 if (sc->nfe_flags & NFE_40BIT_ADDR) { 2063 desc64 = &sc->jrxq.jdesc64[idx]; 2064 desc64->physaddr[0] = htole32(NFE_ADDR_HI(segs[0].ds_addr)); 2065 desc64->physaddr[1] = htole32(NFE_ADDR_LO(segs[0].ds_addr)); 2066 desc64->length = htole16(segs[0].ds_len); 2067 desc64->flags = htole16(NFE_RX_READY); 2068 } else { 2069 desc32 = &sc->jrxq.jdesc32[idx]; 2070 desc32->physaddr = htole32(NFE_ADDR_LO(segs[0].ds_addr)); 2071 desc32->length = htole16(segs[0].ds_len); 2072 desc32->flags = htole16(NFE_RX_READY); 2073 } 2074 2075 return (0); 2076 } 2077 2078 static int 2079 nfe_rxeof(struct nfe_softc *sc, int count, int *rx_npktsp) 2080 { 2081 if_t ifp = sc->nfe_ifp; 2082 struct nfe_desc32 *desc32; 2083 struct nfe_desc64 *desc64; 2084 struct nfe_rx_data *data; 2085 struct mbuf *m; 2086 uint16_t flags; 2087 int len, prog, rx_npkts; 2088 uint32_t vtag = 0; 2089 2090 rx_npkts = 0; 2091 NFE_LOCK_ASSERT(sc); 2092 2093 bus_dmamap_sync(sc->rxq.rx_desc_tag, sc->rxq.rx_desc_map, 2094 BUS_DMASYNC_POSTREAD); 2095 2096 for (prog = 0;;NFE_INC(sc->rxq.cur, NFE_RX_RING_COUNT), vtag = 0) { 2097 if (count <= 0) 2098 break; 2099 count--; 2100 2101 data = &sc->rxq.data[sc->rxq.cur]; 2102 2103 if (sc->nfe_flags & NFE_40BIT_ADDR) { 2104 desc64 = &sc->rxq.desc64[sc->rxq.cur]; 2105 vtag = le32toh(desc64->physaddr[1]); 2106 flags = le16toh(desc64->flags); 2107 len = le16toh(desc64->length) & NFE_RX_LEN_MASK; 2108 } else { 2109 desc32 = &sc->rxq.desc32[sc->rxq.cur]; 2110 flags = le16toh(desc32->flags); 2111 len = le16toh(desc32->length) & NFE_RX_LEN_MASK; 2112 } 2113 2114 if (flags & NFE_RX_READY) 2115 break; 2116 prog++; 2117 if ((sc->nfe_flags & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) { 2118 if (!(flags & NFE_RX_VALID_V1)) { 2119 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 2120 nfe_discard_rxbuf(sc, sc->rxq.cur); 2121 continue; 2122 } 2123 if ((flags & NFE_RX_FIXME_V1) == NFE_RX_FIXME_V1) { 2124 flags &= ~NFE_RX_ERROR; 2125 len--; /* fix buffer length */ 2126 } 2127 } else { 2128 if (!(flags & NFE_RX_VALID_V2)) { 2129 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 2130 nfe_discard_rxbuf(sc, sc->rxq.cur); 2131 continue; 2132 } 2133 2134 if ((flags & NFE_RX_FIXME_V2) == NFE_RX_FIXME_V2) { 2135 flags &= ~NFE_RX_ERROR; 2136 len--; /* fix buffer length */ 2137 } 2138 } 2139 2140 if (flags & NFE_RX_ERROR) { 2141 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 2142 nfe_discard_rxbuf(sc, sc->rxq.cur); 2143 continue; 2144 } 2145 2146 m = data->m; 2147 if (nfe_newbuf(sc, sc->rxq.cur) != 0) { 2148 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 2149 nfe_discard_rxbuf(sc, sc->rxq.cur); 2150 continue; 2151 } 2152 2153 if ((vtag & NFE_RX_VTAG) != 0 && 2154 (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0) { 2155 m->m_pkthdr.ether_vtag = vtag & 0xffff; 2156 m->m_flags |= M_VLANTAG; 2157 } 2158 2159 m->m_pkthdr.len = m->m_len = len; 2160 m->m_pkthdr.rcvif = ifp; 2161 2162 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0) { 2163 if ((flags & NFE_RX_IP_CSUMOK) != 0) { 2164 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 2165 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2166 if ((flags & NFE_RX_TCP_CSUMOK) != 0 || 2167 (flags & NFE_RX_UDP_CSUMOK) != 0) { 2168 m->m_pkthdr.csum_flags |= 2169 CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 2170 m->m_pkthdr.csum_data = 0xffff; 2171 } 2172 } 2173 } 2174 2175 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 2176 2177 NFE_UNLOCK(sc); 2178 if_input(ifp, m); 2179 NFE_LOCK(sc); 2180 rx_npkts++; 2181 } 2182 2183 if (prog > 0) 2184 bus_dmamap_sync(sc->rxq.rx_desc_tag, sc->rxq.rx_desc_map, 2185 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2186 2187 if (rx_npktsp != NULL) 2188 *rx_npktsp = rx_npkts; 2189 return (count > 0 ? 0 : EAGAIN); 2190 } 2191 2192 static int 2193 nfe_jrxeof(struct nfe_softc *sc, int count, int *rx_npktsp) 2194 { 2195 if_t ifp = sc->nfe_ifp; 2196 struct nfe_desc32 *desc32; 2197 struct nfe_desc64 *desc64; 2198 struct nfe_rx_data *data; 2199 struct mbuf *m; 2200 uint16_t flags; 2201 int len, prog, rx_npkts; 2202 uint32_t vtag = 0; 2203 2204 rx_npkts = 0; 2205 NFE_LOCK_ASSERT(sc); 2206 2207 bus_dmamap_sync(sc->jrxq.jrx_desc_tag, sc->jrxq.jrx_desc_map, 2208 BUS_DMASYNC_POSTREAD); 2209 2210 for (prog = 0;;NFE_INC(sc->jrxq.jcur, NFE_JUMBO_RX_RING_COUNT), 2211 vtag = 0) { 2212 if (count <= 0) 2213 break; 2214 count--; 2215 2216 data = &sc->jrxq.jdata[sc->jrxq.jcur]; 2217 2218 if (sc->nfe_flags & NFE_40BIT_ADDR) { 2219 desc64 = &sc->jrxq.jdesc64[sc->jrxq.jcur]; 2220 vtag = le32toh(desc64->physaddr[1]); 2221 flags = le16toh(desc64->flags); 2222 len = le16toh(desc64->length) & NFE_RX_LEN_MASK; 2223 } else { 2224 desc32 = &sc->jrxq.jdesc32[sc->jrxq.jcur]; 2225 flags = le16toh(desc32->flags); 2226 len = le16toh(desc32->length) & NFE_RX_LEN_MASK; 2227 } 2228 2229 if (flags & NFE_RX_READY) 2230 break; 2231 prog++; 2232 if ((sc->nfe_flags & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) { 2233 if (!(flags & NFE_RX_VALID_V1)) { 2234 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 2235 nfe_discard_jrxbuf(sc, sc->jrxq.jcur); 2236 continue; 2237 } 2238 if ((flags & NFE_RX_FIXME_V1) == NFE_RX_FIXME_V1) { 2239 flags &= ~NFE_RX_ERROR; 2240 len--; /* fix buffer length */ 2241 } 2242 } else { 2243 if (!(flags & NFE_RX_VALID_V2)) { 2244 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 2245 nfe_discard_jrxbuf(sc, sc->jrxq.jcur); 2246 continue; 2247 } 2248 2249 if ((flags & NFE_RX_FIXME_V2) == NFE_RX_FIXME_V2) { 2250 flags &= ~NFE_RX_ERROR; 2251 len--; /* fix buffer length */ 2252 } 2253 } 2254 2255 if (flags & NFE_RX_ERROR) { 2256 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 2257 nfe_discard_jrxbuf(sc, sc->jrxq.jcur); 2258 continue; 2259 } 2260 2261 m = data->m; 2262 if (nfe_jnewbuf(sc, sc->jrxq.jcur) != 0) { 2263 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 2264 nfe_discard_jrxbuf(sc, sc->jrxq.jcur); 2265 continue; 2266 } 2267 2268 if ((vtag & NFE_RX_VTAG) != 0 && 2269 (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0) { 2270 m->m_pkthdr.ether_vtag = vtag & 0xffff; 2271 m->m_flags |= M_VLANTAG; 2272 } 2273 2274 m->m_pkthdr.len = m->m_len = len; 2275 m->m_pkthdr.rcvif = ifp; 2276 2277 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0) { 2278 if ((flags & NFE_RX_IP_CSUMOK) != 0) { 2279 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 2280 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2281 if ((flags & NFE_RX_TCP_CSUMOK) != 0 || 2282 (flags & NFE_RX_UDP_CSUMOK) != 0) { 2283 m->m_pkthdr.csum_flags |= 2284 CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 2285 m->m_pkthdr.csum_data = 0xffff; 2286 } 2287 } 2288 } 2289 2290 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 2291 2292 NFE_UNLOCK(sc); 2293 if_input(ifp, m); 2294 NFE_LOCK(sc); 2295 rx_npkts++; 2296 } 2297 2298 if (prog > 0) 2299 bus_dmamap_sync(sc->jrxq.jrx_desc_tag, sc->jrxq.jrx_desc_map, 2300 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2301 2302 if (rx_npktsp != NULL) 2303 *rx_npktsp = rx_npkts; 2304 return (count > 0 ? 0 : EAGAIN); 2305 } 2306 2307 static void 2308 nfe_txeof(struct nfe_softc *sc) 2309 { 2310 if_t ifp = sc->nfe_ifp; 2311 struct nfe_desc32 *desc32; 2312 struct nfe_desc64 *desc64; 2313 struct nfe_tx_data *data = NULL; 2314 uint16_t flags; 2315 int cons, prog; 2316 2317 NFE_LOCK_ASSERT(sc); 2318 2319 bus_dmamap_sync(sc->txq.tx_desc_tag, sc->txq.tx_desc_map, 2320 BUS_DMASYNC_POSTREAD); 2321 2322 prog = 0; 2323 for (cons = sc->txq.next; cons != sc->txq.cur; 2324 NFE_INC(cons, NFE_TX_RING_COUNT)) { 2325 if (sc->nfe_flags & NFE_40BIT_ADDR) { 2326 desc64 = &sc->txq.desc64[cons]; 2327 flags = le16toh(desc64->flags); 2328 } else { 2329 desc32 = &sc->txq.desc32[cons]; 2330 flags = le16toh(desc32->flags); 2331 } 2332 2333 if (flags & NFE_TX_VALID) 2334 break; 2335 2336 prog++; 2337 sc->txq.queued--; 2338 data = &sc->txq.data[cons]; 2339 2340 if ((sc->nfe_flags & (NFE_JUMBO_SUP | NFE_40BIT_ADDR)) == 0) { 2341 if ((flags & NFE_TX_LASTFRAG_V1) == 0) 2342 continue; 2343 if ((flags & NFE_TX_ERROR_V1) != 0) { 2344 device_printf(sc->nfe_dev, 2345 "tx v1 error 0x%4b\n", flags, NFE_V1_TXERR); 2346 2347 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 2348 } else 2349 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 2350 } else { 2351 if ((flags & NFE_TX_LASTFRAG_V2) == 0) 2352 continue; 2353 if ((flags & NFE_TX_ERROR_V2) != 0) { 2354 device_printf(sc->nfe_dev, 2355 "tx v2 error 0x%4b\n", flags, NFE_V2_TXERR); 2356 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 2357 } else 2358 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 2359 } 2360 2361 /* last fragment of the mbuf chain transmitted */ 2362 KASSERT(data->m != NULL, ("%s: freeing NULL mbuf!", __func__)); 2363 bus_dmamap_sync(sc->txq.tx_data_tag, data->tx_data_map, 2364 BUS_DMASYNC_POSTWRITE); 2365 bus_dmamap_unload(sc->txq.tx_data_tag, data->tx_data_map); 2366 m_freem(data->m); 2367 data->m = NULL; 2368 } 2369 2370 if (prog > 0) { 2371 sc->nfe_force_tx = 0; 2372 sc->txq.next = cons; 2373 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 2374 if (sc->txq.queued == 0) 2375 sc->nfe_watchdog_timer = 0; 2376 } 2377 } 2378 2379 static int 2380 nfe_encap(struct nfe_softc *sc, struct mbuf **m_head) 2381 { 2382 struct nfe_desc32 *desc32 = NULL; 2383 struct nfe_desc64 *desc64 = NULL; 2384 bus_dmamap_t map; 2385 bus_dma_segment_t segs[NFE_MAX_SCATTER]; 2386 int error, i, nsegs, prod, si; 2387 uint32_t tsosegsz; 2388 uint16_t cflags, flags; 2389 struct mbuf *m; 2390 2391 prod = si = sc->txq.cur; 2392 map = sc->txq.data[prod].tx_data_map; 2393 2394 error = bus_dmamap_load_mbuf_sg(sc->txq.tx_data_tag, map, *m_head, segs, 2395 &nsegs, BUS_DMA_NOWAIT); 2396 if (error == EFBIG) { 2397 m = m_collapse(*m_head, M_NOWAIT, NFE_MAX_SCATTER); 2398 if (m == NULL) { 2399 m_freem(*m_head); 2400 *m_head = NULL; 2401 return (ENOBUFS); 2402 } 2403 *m_head = m; 2404 error = bus_dmamap_load_mbuf_sg(sc->txq.tx_data_tag, map, 2405 *m_head, segs, &nsegs, BUS_DMA_NOWAIT); 2406 if (error != 0) { 2407 m_freem(*m_head); 2408 *m_head = NULL; 2409 return (ENOBUFS); 2410 } 2411 } else if (error != 0) 2412 return (error); 2413 if (nsegs == 0) { 2414 m_freem(*m_head); 2415 *m_head = NULL; 2416 return (EIO); 2417 } 2418 2419 if (sc->txq.queued + nsegs >= NFE_TX_RING_COUNT - 2) { 2420 bus_dmamap_unload(sc->txq.tx_data_tag, map); 2421 return (ENOBUFS); 2422 } 2423 2424 m = *m_head; 2425 cflags = flags = 0; 2426 tsosegsz = 0; 2427 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 2428 tsosegsz = (uint32_t)m->m_pkthdr.tso_segsz << 2429 NFE_TX_TSO_SHIFT; 2430 cflags &= ~(NFE_TX_IP_CSUM | NFE_TX_TCP_UDP_CSUM); 2431 cflags |= NFE_TX_TSO; 2432 } else if ((m->m_pkthdr.csum_flags & NFE_CSUM_FEATURES) != 0) { 2433 if ((m->m_pkthdr.csum_flags & CSUM_IP) != 0) 2434 cflags |= NFE_TX_IP_CSUM; 2435 if ((m->m_pkthdr.csum_flags & CSUM_TCP) != 0) 2436 cflags |= NFE_TX_TCP_UDP_CSUM; 2437 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0) 2438 cflags |= NFE_TX_TCP_UDP_CSUM; 2439 } 2440 2441 for (i = 0; i < nsegs; i++) { 2442 if (sc->nfe_flags & NFE_40BIT_ADDR) { 2443 desc64 = &sc->txq.desc64[prod]; 2444 desc64->physaddr[0] = 2445 htole32(NFE_ADDR_HI(segs[i].ds_addr)); 2446 desc64->physaddr[1] = 2447 htole32(NFE_ADDR_LO(segs[i].ds_addr)); 2448 desc64->vtag = 0; 2449 desc64->length = htole16(segs[i].ds_len - 1); 2450 desc64->flags = htole16(flags); 2451 } else { 2452 desc32 = &sc->txq.desc32[prod]; 2453 desc32->physaddr = 2454 htole32(NFE_ADDR_LO(segs[i].ds_addr)); 2455 desc32->length = htole16(segs[i].ds_len - 1); 2456 desc32->flags = htole16(flags); 2457 } 2458 2459 /* 2460 * Setting of the valid bit in the first descriptor is 2461 * deferred until the whole chain is fully setup. 2462 */ 2463 flags |= NFE_TX_VALID; 2464 2465 sc->txq.queued++; 2466 NFE_INC(prod, NFE_TX_RING_COUNT); 2467 } 2468 2469 /* 2470 * the whole mbuf chain has been DMA mapped, fix last/first descriptor. 2471 * csum flags, vtag and TSO belong to the first fragment only. 2472 */ 2473 if (sc->nfe_flags & NFE_40BIT_ADDR) { 2474 desc64->flags |= htole16(NFE_TX_LASTFRAG_V2); 2475 desc64 = &sc->txq.desc64[si]; 2476 if ((m->m_flags & M_VLANTAG) != 0) 2477 desc64->vtag = htole32(NFE_TX_VTAG | 2478 m->m_pkthdr.ether_vtag); 2479 if (tsosegsz != 0) { 2480 /* 2481 * XXX 2482 * The following indicates the descriptor element 2483 * is a 32bit quantity. 2484 */ 2485 desc64->length |= htole16((uint16_t)tsosegsz); 2486 desc64->flags |= htole16(tsosegsz >> 16); 2487 } 2488 /* 2489 * finally, set the valid/checksum/TSO bit in the first 2490 * descriptor. 2491 */ 2492 desc64->flags |= htole16(NFE_TX_VALID | cflags); 2493 } else { 2494 if (sc->nfe_flags & NFE_JUMBO_SUP) 2495 desc32->flags |= htole16(NFE_TX_LASTFRAG_V2); 2496 else 2497 desc32->flags |= htole16(NFE_TX_LASTFRAG_V1); 2498 desc32 = &sc->txq.desc32[si]; 2499 if (tsosegsz != 0) { 2500 /* 2501 * XXX 2502 * The following indicates the descriptor element 2503 * is a 32bit quantity. 2504 */ 2505 desc32->length |= htole16((uint16_t)tsosegsz); 2506 desc32->flags |= htole16(tsosegsz >> 16); 2507 } 2508 /* 2509 * finally, set the valid/checksum/TSO bit in the first 2510 * descriptor. 2511 */ 2512 desc32->flags |= htole16(NFE_TX_VALID | cflags); 2513 } 2514 2515 sc->txq.cur = prod; 2516 prod = (prod + NFE_TX_RING_COUNT - 1) % NFE_TX_RING_COUNT; 2517 sc->txq.data[si].tx_data_map = sc->txq.data[prod].tx_data_map; 2518 sc->txq.data[prod].tx_data_map = map; 2519 sc->txq.data[prod].m = m; 2520 2521 bus_dmamap_sync(sc->txq.tx_data_tag, map, BUS_DMASYNC_PREWRITE); 2522 2523 return (0); 2524 } 2525 2526 struct nfe_hash_maddr_ctx { 2527 uint8_t addr[ETHER_ADDR_LEN]; 2528 uint8_t mask[ETHER_ADDR_LEN]; 2529 }; 2530 2531 static u_int 2532 nfe_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) 2533 { 2534 struct nfe_hash_maddr_ctx *ctx = arg; 2535 uint8_t *addrp, mcaddr; 2536 int j; 2537 2538 addrp = LLADDR(sdl); 2539 for (j = 0; j < ETHER_ADDR_LEN; j++) { 2540 mcaddr = addrp[j]; 2541 ctx->addr[j] &= mcaddr; 2542 ctx->mask[j] &= ~mcaddr; 2543 } 2544 2545 return (1); 2546 } 2547 2548 static void 2549 nfe_setmulti(struct nfe_softc *sc) 2550 { 2551 if_t ifp = sc->nfe_ifp; 2552 struct nfe_hash_maddr_ctx ctx; 2553 uint32_t filter; 2554 uint8_t etherbroadcastaddr[ETHER_ADDR_LEN] = { 2555 0xff, 0xff, 0xff, 0xff, 0xff, 0xff 2556 }; 2557 int i; 2558 2559 NFE_LOCK_ASSERT(sc); 2560 2561 if ((if_getflags(ifp) & (IFF_ALLMULTI | IFF_PROMISC)) != 0) { 2562 bzero(ctx.addr, ETHER_ADDR_LEN); 2563 bzero(ctx.mask, ETHER_ADDR_LEN); 2564 goto done; 2565 } 2566 2567 bcopy(etherbroadcastaddr, ctx.addr, ETHER_ADDR_LEN); 2568 bcopy(etherbroadcastaddr, ctx.mask, ETHER_ADDR_LEN); 2569 2570 if_foreach_llmaddr(ifp, nfe_hash_maddr, &ctx); 2571 2572 for (i = 0; i < ETHER_ADDR_LEN; i++) { 2573 ctx.mask[i] |= ctx.addr[i]; 2574 } 2575 2576 done: 2577 ctx.addr[0] |= 0x01; /* make sure multicast bit is set */ 2578 2579 NFE_WRITE(sc, NFE_MULTIADDR_HI, ctx.addr[3] << 24 | ctx.addr[2] << 16 | 2580 ctx.addr[1] << 8 | ctx.addr[0]); 2581 NFE_WRITE(sc, NFE_MULTIADDR_LO, 2582 ctx.addr[5] << 8 | ctx.addr[4]); 2583 NFE_WRITE(sc, NFE_MULTIMASK_HI, ctx.mask[3] << 24 | ctx.mask[2] << 16 | 2584 ctx.mask[1] << 8 | ctx.mask[0]); 2585 NFE_WRITE(sc, NFE_MULTIMASK_LO, 2586 ctx.mask[5] << 8 | ctx.mask[4]); 2587 2588 filter = NFE_READ(sc, NFE_RXFILTER); 2589 filter &= NFE_PFF_RX_PAUSE; 2590 filter |= NFE_RXFILTER_MAGIC; 2591 filter |= (if_getflags(ifp) & IFF_PROMISC) ? NFE_PFF_PROMISC : NFE_PFF_U2M; 2592 NFE_WRITE(sc, NFE_RXFILTER, filter); 2593 } 2594 2595 static void 2596 nfe_start(if_t ifp) 2597 { 2598 struct nfe_softc *sc = if_getsoftc(ifp); 2599 2600 NFE_LOCK(sc); 2601 nfe_start_locked(ifp); 2602 NFE_UNLOCK(sc); 2603 } 2604 2605 static void 2606 nfe_start_locked(if_t ifp) 2607 { 2608 struct nfe_softc *sc = if_getsoftc(ifp); 2609 struct mbuf *m0; 2610 int enq = 0; 2611 2612 NFE_LOCK_ASSERT(sc); 2613 2614 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2615 IFF_DRV_RUNNING || sc->nfe_link == 0) 2616 return; 2617 2618 while (!if_sendq_empty(ifp)) { 2619 m0 = if_dequeue(ifp); 2620 2621 if (m0 == NULL) 2622 break; 2623 2624 if (nfe_encap(sc, &m0) != 0) { 2625 if (m0 == NULL) 2626 break; 2627 if_sendq_prepend(ifp, m0); 2628 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); 2629 break; 2630 } 2631 enq++; 2632 if_etherbpfmtap(ifp, m0); 2633 } 2634 2635 if (enq > 0) { 2636 bus_dmamap_sync(sc->txq.tx_desc_tag, sc->txq.tx_desc_map, 2637 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2638 2639 /* kick Tx */ 2640 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_KICKTX | sc->rxtxctl); 2641 2642 /* 2643 * Set a timeout in case the chip goes out to lunch. 2644 */ 2645 sc->nfe_watchdog_timer = 5; 2646 } 2647 } 2648 2649 static void 2650 nfe_watchdog(if_t ifp) 2651 { 2652 struct nfe_softc *sc = if_getsoftc(ifp); 2653 2654 if (sc->nfe_watchdog_timer == 0 || --sc->nfe_watchdog_timer) 2655 return; 2656 2657 /* Check if we've lost Tx completion interrupt. */ 2658 nfe_txeof(sc); 2659 if (sc->txq.queued == 0) { 2660 if_printf(ifp, "watchdog timeout (missed Tx interrupts) " 2661 "-- recovering\n"); 2662 if (!if_sendq_empty(ifp)) 2663 nfe_start_locked(ifp); 2664 return; 2665 } 2666 /* Check if we've lost start Tx command. */ 2667 sc->nfe_force_tx++; 2668 if (sc->nfe_force_tx <= 3) { 2669 /* 2670 * If this is the case for watchdog timeout, the following 2671 * code should go to nfe_txeof(). 2672 */ 2673 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_KICKTX | sc->rxtxctl); 2674 return; 2675 } 2676 sc->nfe_force_tx = 0; 2677 2678 if_printf(ifp, "watchdog timeout\n"); 2679 2680 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 2681 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 2682 nfe_init_locked(sc); 2683 } 2684 2685 static void 2686 nfe_init(void *xsc) 2687 { 2688 struct nfe_softc *sc = xsc; 2689 2690 NFE_LOCK(sc); 2691 nfe_init_locked(sc); 2692 NFE_UNLOCK(sc); 2693 } 2694 2695 static void 2696 nfe_init_locked(void *xsc) 2697 { 2698 struct nfe_softc *sc = xsc; 2699 if_t ifp = sc->nfe_ifp; 2700 struct mii_data *mii; 2701 uint32_t val; 2702 int error; 2703 2704 NFE_LOCK_ASSERT(sc); 2705 2706 mii = device_get_softc(sc->nfe_miibus); 2707 2708 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 2709 return; 2710 2711 nfe_stop(ifp); 2712 2713 sc->nfe_framesize = if_getmtu(ifp) + NFE_RX_HEADERS; 2714 2715 nfe_init_tx_ring(sc, &sc->txq); 2716 if (sc->nfe_framesize > (MCLBYTES - ETHER_HDR_LEN)) 2717 error = nfe_init_jrx_ring(sc, &sc->jrxq); 2718 else 2719 error = nfe_init_rx_ring(sc, &sc->rxq); 2720 if (error != 0) { 2721 device_printf(sc->nfe_dev, 2722 "initialization failed: no memory for rx buffers\n"); 2723 nfe_stop(ifp); 2724 return; 2725 } 2726 2727 val = 0; 2728 if ((sc->nfe_flags & NFE_CORRECT_MACADDR) != 0) 2729 val |= NFE_MAC_ADDR_INORDER; 2730 NFE_WRITE(sc, NFE_TX_UNK, val); 2731 NFE_WRITE(sc, NFE_STATUS, 0); 2732 2733 if ((sc->nfe_flags & NFE_TX_FLOW_CTRL) != 0) 2734 NFE_WRITE(sc, NFE_TX_PAUSE_FRAME, NFE_TX_PAUSE_FRAME_DISABLE); 2735 2736 sc->rxtxctl = NFE_RXTX_BIT2; 2737 if (sc->nfe_flags & NFE_40BIT_ADDR) 2738 sc->rxtxctl |= NFE_RXTX_V3MAGIC; 2739 else if (sc->nfe_flags & NFE_JUMBO_SUP) 2740 sc->rxtxctl |= NFE_RXTX_V2MAGIC; 2741 2742 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0) 2743 sc->rxtxctl |= NFE_RXTX_RXCSUM; 2744 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0) 2745 sc->rxtxctl |= NFE_RXTX_VTAG_INSERT | NFE_RXTX_VTAG_STRIP; 2746 2747 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_RESET | sc->rxtxctl); 2748 DELAY(10); 2749 NFE_WRITE(sc, NFE_RXTX_CTL, sc->rxtxctl); 2750 2751 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0) 2752 NFE_WRITE(sc, NFE_VTAG_CTL, NFE_VTAG_ENABLE); 2753 else 2754 NFE_WRITE(sc, NFE_VTAG_CTL, 0); 2755 2756 NFE_WRITE(sc, NFE_SETUP_R6, 0); 2757 2758 /* set MAC address */ 2759 nfe_set_macaddr(sc, if_getlladdr(ifp)); 2760 2761 /* tell MAC where rings are in memory */ 2762 if (sc->nfe_framesize > MCLBYTES - ETHER_HDR_LEN) { 2763 NFE_WRITE(sc, NFE_RX_RING_ADDR_HI, 2764 NFE_ADDR_HI(sc->jrxq.jphysaddr)); 2765 NFE_WRITE(sc, NFE_RX_RING_ADDR_LO, 2766 NFE_ADDR_LO(sc->jrxq.jphysaddr)); 2767 } else { 2768 NFE_WRITE(sc, NFE_RX_RING_ADDR_HI, 2769 NFE_ADDR_HI(sc->rxq.physaddr)); 2770 NFE_WRITE(sc, NFE_RX_RING_ADDR_LO, 2771 NFE_ADDR_LO(sc->rxq.physaddr)); 2772 } 2773 NFE_WRITE(sc, NFE_TX_RING_ADDR_HI, NFE_ADDR_HI(sc->txq.physaddr)); 2774 NFE_WRITE(sc, NFE_TX_RING_ADDR_LO, NFE_ADDR_LO(sc->txq.physaddr)); 2775 2776 NFE_WRITE(sc, NFE_RING_SIZE, 2777 (NFE_RX_RING_COUNT - 1) << 16 | 2778 (NFE_TX_RING_COUNT - 1)); 2779 2780 NFE_WRITE(sc, NFE_RXBUFSZ, sc->nfe_framesize); 2781 2782 /* force MAC to wakeup */ 2783 val = NFE_READ(sc, NFE_PWR_STATE); 2784 if ((val & NFE_PWR_WAKEUP) == 0) 2785 NFE_WRITE(sc, NFE_PWR_STATE, val | NFE_PWR_WAKEUP); 2786 DELAY(10); 2787 val = NFE_READ(sc, NFE_PWR_STATE); 2788 NFE_WRITE(sc, NFE_PWR_STATE, val | NFE_PWR_VALID); 2789 2790 #if 1 2791 /* configure interrupts coalescing/mitigation */ 2792 NFE_WRITE(sc, NFE_IMTIMER, NFE_IM_DEFAULT); 2793 #else 2794 /* no interrupt mitigation: one interrupt per packet */ 2795 NFE_WRITE(sc, NFE_IMTIMER, 970); 2796 #endif 2797 2798 NFE_WRITE(sc, NFE_SETUP_R1, NFE_R1_MAGIC_10_100); 2799 NFE_WRITE(sc, NFE_SETUP_R2, NFE_R2_MAGIC); 2800 NFE_WRITE(sc, NFE_SETUP_R6, NFE_R6_MAGIC); 2801 2802 /* update MAC knowledge of PHY; generates a NFE_IRQ_LINK interrupt */ 2803 NFE_WRITE(sc, NFE_STATUS, sc->mii_phyaddr << 24 | NFE_STATUS_MAGIC); 2804 2805 NFE_WRITE(sc, NFE_SETUP_R4, NFE_R4_MAGIC); 2806 /* Disable WOL. */ 2807 NFE_WRITE(sc, NFE_WOL_CTL, 0); 2808 2809 sc->rxtxctl &= ~NFE_RXTX_BIT2; 2810 NFE_WRITE(sc, NFE_RXTX_CTL, sc->rxtxctl); 2811 DELAY(10); 2812 NFE_WRITE(sc, NFE_RXTX_CTL, NFE_RXTX_BIT1 | sc->rxtxctl); 2813 2814 /* set Rx filter */ 2815 nfe_setmulti(sc); 2816 2817 /* enable Rx */ 2818 NFE_WRITE(sc, NFE_RX_CTL, NFE_RX_START); 2819 2820 /* enable Tx */ 2821 NFE_WRITE(sc, NFE_TX_CTL, NFE_TX_START); 2822 2823 NFE_WRITE(sc, NFE_PHY_STATUS, 0xf); 2824 2825 /* Clear hardware stats. */ 2826 nfe_stats_clear(sc); 2827 2828 #ifdef DEVICE_POLLING 2829 if (if_getcapenable(ifp) & IFCAP_POLLING) 2830 nfe_disable_intr(sc); 2831 else 2832 #endif 2833 nfe_set_intr(sc); 2834 nfe_enable_intr(sc); /* enable interrupts */ 2835 2836 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0); 2837 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 2838 2839 sc->nfe_link = 0; 2840 mii_mediachg(mii); 2841 2842 callout_reset(&sc->nfe_stat_ch, hz, nfe_tick, sc); 2843 } 2844 2845 static void 2846 nfe_stop(if_t ifp) 2847 { 2848 struct nfe_softc *sc = if_getsoftc(ifp); 2849 struct nfe_rx_ring *rx_ring; 2850 struct nfe_jrx_ring *jrx_ring; 2851 struct nfe_tx_ring *tx_ring; 2852 struct nfe_rx_data *rdata; 2853 struct nfe_tx_data *tdata; 2854 int i; 2855 2856 NFE_LOCK_ASSERT(sc); 2857 2858 sc->nfe_watchdog_timer = 0; 2859 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)); 2860 2861 callout_stop(&sc->nfe_stat_ch); 2862 2863 /* abort Tx */ 2864 NFE_WRITE(sc, NFE_TX_CTL, 0); 2865 2866 /* disable Rx */ 2867 NFE_WRITE(sc, NFE_RX_CTL, 0); 2868 2869 /* disable interrupts */ 2870 nfe_disable_intr(sc); 2871 2872 sc->nfe_link = 0; 2873 2874 /* free Rx and Tx mbufs still in the queues. */ 2875 rx_ring = &sc->rxq; 2876 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 2877 rdata = &rx_ring->data[i]; 2878 if (rdata->m != NULL) { 2879 bus_dmamap_sync(rx_ring->rx_data_tag, 2880 rdata->rx_data_map, BUS_DMASYNC_POSTREAD); 2881 bus_dmamap_unload(rx_ring->rx_data_tag, 2882 rdata->rx_data_map); 2883 m_freem(rdata->m); 2884 rdata->m = NULL; 2885 } 2886 } 2887 2888 if ((sc->nfe_flags & NFE_JUMBO_SUP) != 0) { 2889 jrx_ring = &sc->jrxq; 2890 for (i = 0; i < NFE_JUMBO_RX_RING_COUNT; i++) { 2891 rdata = &jrx_ring->jdata[i]; 2892 if (rdata->m != NULL) { 2893 bus_dmamap_sync(jrx_ring->jrx_data_tag, 2894 rdata->rx_data_map, BUS_DMASYNC_POSTREAD); 2895 bus_dmamap_unload(jrx_ring->jrx_data_tag, 2896 rdata->rx_data_map); 2897 m_freem(rdata->m); 2898 rdata->m = NULL; 2899 } 2900 } 2901 } 2902 2903 tx_ring = &sc->txq; 2904 for (i = 0; i < NFE_RX_RING_COUNT; i++) { 2905 tdata = &tx_ring->data[i]; 2906 if (tdata->m != NULL) { 2907 bus_dmamap_sync(tx_ring->tx_data_tag, 2908 tdata->tx_data_map, BUS_DMASYNC_POSTWRITE); 2909 bus_dmamap_unload(tx_ring->tx_data_tag, 2910 tdata->tx_data_map); 2911 m_freem(tdata->m); 2912 tdata->m = NULL; 2913 } 2914 } 2915 /* Update hardware stats. */ 2916 nfe_stats_update(sc); 2917 } 2918 2919 static int 2920 nfe_ifmedia_upd(if_t ifp) 2921 { 2922 struct nfe_softc *sc = if_getsoftc(ifp); 2923 struct mii_data *mii; 2924 2925 NFE_LOCK(sc); 2926 mii = device_get_softc(sc->nfe_miibus); 2927 mii_mediachg(mii); 2928 NFE_UNLOCK(sc); 2929 2930 return (0); 2931 } 2932 2933 static void 2934 nfe_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr) 2935 { 2936 struct nfe_softc *sc; 2937 struct mii_data *mii; 2938 2939 sc = if_getsoftc(ifp); 2940 2941 NFE_LOCK(sc); 2942 mii = device_get_softc(sc->nfe_miibus); 2943 mii_pollstat(mii); 2944 2945 ifmr->ifm_active = mii->mii_media_active; 2946 ifmr->ifm_status = mii->mii_media_status; 2947 NFE_UNLOCK(sc); 2948 } 2949 2950 void 2951 nfe_tick(void *xsc) 2952 { 2953 struct nfe_softc *sc; 2954 struct mii_data *mii; 2955 if_t ifp; 2956 2957 sc = (struct nfe_softc *)xsc; 2958 2959 NFE_LOCK_ASSERT(sc); 2960 2961 ifp = sc->nfe_ifp; 2962 2963 mii = device_get_softc(sc->nfe_miibus); 2964 mii_tick(mii); 2965 nfe_stats_update(sc); 2966 nfe_watchdog(ifp); 2967 callout_reset(&sc->nfe_stat_ch, hz, nfe_tick, sc); 2968 } 2969 2970 static int 2971 nfe_shutdown(device_t dev) 2972 { 2973 2974 return (nfe_suspend(dev)); 2975 } 2976 2977 static void 2978 nfe_get_macaddr(struct nfe_softc *sc, uint8_t *addr) 2979 { 2980 uint32_t val; 2981 2982 if ((sc->nfe_flags & NFE_CORRECT_MACADDR) == 0) { 2983 val = NFE_READ(sc, NFE_MACADDR_LO); 2984 addr[0] = (val >> 8) & 0xff; 2985 addr[1] = (val & 0xff); 2986 2987 val = NFE_READ(sc, NFE_MACADDR_HI); 2988 addr[2] = (val >> 24) & 0xff; 2989 addr[3] = (val >> 16) & 0xff; 2990 addr[4] = (val >> 8) & 0xff; 2991 addr[5] = (val & 0xff); 2992 } else { 2993 val = NFE_READ(sc, NFE_MACADDR_LO); 2994 addr[5] = (val >> 8) & 0xff; 2995 addr[4] = (val & 0xff); 2996 2997 val = NFE_READ(sc, NFE_MACADDR_HI); 2998 addr[3] = (val >> 24) & 0xff; 2999 addr[2] = (val >> 16) & 0xff; 3000 addr[1] = (val >> 8) & 0xff; 3001 addr[0] = (val & 0xff); 3002 } 3003 } 3004 3005 static void 3006 nfe_set_macaddr(struct nfe_softc *sc, uint8_t *addr) 3007 { 3008 3009 NFE_WRITE(sc, NFE_MACADDR_LO, addr[5] << 8 | addr[4]); 3010 NFE_WRITE(sc, NFE_MACADDR_HI, addr[3] << 24 | addr[2] << 16 | 3011 addr[1] << 8 | addr[0]); 3012 } 3013 3014 /* 3015 * Map a single buffer address. 3016 */ 3017 3018 static void 3019 nfe_dma_map_segs(void *arg, bus_dma_segment_t *segs, int nseg, int error) 3020 { 3021 struct nfe_dmamap_arg *ctx; 3022 3023 if (error != 0) 3024 return; 3025 3026 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 3027 3028 ctx = (struct nfe_dmamap_arg *)arg; 3029 ctx->nfe_busaddr = segs[0].ds_addr; 3030 } 3031 3032 static int 3033 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 3034 { 3035 int error, value; 3036 3037 if (!arg1) 3038 return (EINVAL); 3039 value = *(int *)arg1; 3040 error = sysctl_handle_int(oidp, &value, 0, req); 3041 if (error || !req->newptr) 3042 return (error); 3043 if (value < low || value > high) 3044 return (EINVAL); 3045 *(int *)arg1 = value; 3046 3047 return (0); 3048 } 3049 3050 static int 3051 sysctl_hw_nfe_proc_limit(SYSCTL_HANDLER_ARGS) 3052 { 3053 3054 return (sysctl_int_range(oidp, arg1, arg2, req, NFE_PROC_MIN, 3055 NFE_PROC_MAX)); 3056 } 3057 3058 #define NFE_SYSCTL_STAT_ADD32(c, h, n, p, d) \ 3059 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d) 3060 #define NFE_SYSCTL_STAT_ADD64(c, h, n, p, d) \ 3061 SYSCTL_ADD_UQUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d) 3062 3063 static void 3064 nfe_sysctl_node(struct nfe_softc *sc) 3065 { 3066 struct sysctl_ctx_list *ctx; 3067 struct sysctl_oid_list *child, *parent; 3068 struct sysctl_oid *tree; 3069 struct nfe_hw_stats *stats; 3070 int error; 3071 3072 stats = &sc->nfe_stats; 3073 ctx = device_get_sysctl_ctx(sc->nfe_dev); 3074 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->nfe_dev)); 3075 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "process_limit", 3076 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 3077 &sc->nfe_process_limit, 0, sysctl_hw_nfe_proc_limit, "I", 3078 "max number of Rx events to process"); 3079 3080 sc->nfe_process_limit = NFE_PROC_DEFAULT; 3081 error = resource_int_value(device_get_name(sc->nfe_dev), 3082 device_get_unit(sc->nfe_dev), "process_limit", 3083 &sc->nfe_process_limit); 3084 if (error == 0) { 3085 if (sc->nfe_process_limit < NFE_PROC_MIN || 3086 sc->nfe_process_limit > NFE_PROC_MAX) { 3087 device_printf(sc->nfe_dev, 3088 "process_limit value out of range; " 3089 "using default: %d\n", NFE_PROC_DEFAULT); 3090 sc->nfe_process_limit = NFE_PROC_DEFAULT; 3091 } 3092 } 3093 3094 if ((sc->nfe_flags & (NFE_MIB_V1 | NFE_MIB_V2 | NFE_MIB_V3)) == 0) 3095 return; 3096 3097 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", 3098 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "NFE statistics"); 3099 parent = SYSCTL_CHILDREN(tree); 3100 3101 /* Rx statistics. */ 3102 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", 3103 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Rx MAC statistics"); 3104 child = SYSCTL_CHILDREN(tree); 3105 3106 NFE_SYSCTL_STAT_ADD32(ctx, child, "frame_errors", 3107 &stats->rx_frame_errors, "Framing Errors"); 3108 NFE_SYSCTL_STAT_ADD32(ctx, child, "extra_bytes", 3109 &stats->rx_extra_bytes, "Extra Bytes"); 3110 NFE_SYSCTL_STAT_ADD32(ctx, child, "late_cols", 3111 &stats->rx_late_cols, "Late Collisions"); 3112 NFE_SYSCTL_STAT_ADD32(ctx, child, "runts", 3113 &stats->rx_runts, "Runts"); 3114 NFE_SYSCTL_STAT_ADD32(ctx, child, "jumbos", 3115 &stats->rx_jumbos, "Jumbos"); 3116 NFE_SYSCTL_STAT_ADD32(ctx, child, "fifo_overuns", 3117 &stats->rx_fifo_overuns, "FIFO Overruns"); 3118 NFE_SYSCTL_STAT_ADD32(ctx, child, "crc_errors", 3119 &stats->rx_crc_errors, "CRC Errors"); 3120 NFE_SYSCTL_STAT_ADD32(ctx, child, "fae", 3121 &stats->rx_fae, "Frame Alignment Errors"); 3122 NFE_SYSCTL_STAT_ADD32(ctx, child, "len_errors", 3123 &stats->rx_len_errors, "Length Errors"); 3124 NFE_SYSCTL_STAT_ADD32(ctx, child, "unicast", 3125 &stats->rx_unicast, "Unicast Frames"); 3126 NFE_SYSCTL_STAT_ADD32(ctx, child, "multicast", 3127 &stats->rx_multicast, "Multicast Frames"); 3128 NFE_SYSCTL_STAT_ADD32(ctx, child, "broadcast", 3129 &stats->rx_broadcast, "Broadcast Frames"); 3130 if ((sc->nfe_flags & NFE_MIB_V2) != 0) { 3131 NFE_SYSCTL_STAT_ADD64(ctx, child, "octets", 3132 &stats->rx_octets, "Octets"); 3133 NFE_SYSCTL_STAT_ADD32(ctx, child, "pause", 3134 &stats->rx_pause, "Pause frames"); 3135 NFE_SYSCTL_STAT_ADD32(ctx, child, "drops", 3136 &stats->rx_drops, "Drop frames"); 3137 } 3138 3139 /* Tx statistics. */ 3140 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", 3141 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Tx MAC statistics"); 3142 child = SYSCTL_CHILDREN(tree); 3143 NFE_SYSCTL_STAT_ADD64(ctx, child, "octets", 3144 &stats->tx_octets, "Octets"); 3145 NFE_SYSCTL_STAT_ADD32(ctx, child, "zero_rexmits", 3146 &stats->tx_zero_rexmits, "Zero Retransmits"); 3147 NFE_SYSCTL_STAT_ADD32(ctx, child, "one_rexmits", 3148 &stats->tx_one_rexmits, "One Retransmits"); 3149 NFE_SYSCTL_STAT_ADD32(ctx, child, "multi_rexmits", 3150 &stats->tx_multi_rexmits, "Multiple Retransmits"); 3151 NFE_SYSCTL_STAT_ADD32(ctx, child, "late_cols", 3152 &stats->tx_late_cols, "Late Collisions"); 3153 NFE_SYSCTL_STAT_ADD32(ctx, child, "fifo_underuns", 3154 &stats->tx_fifo_underuns, "FIFO Underruns"); 3155 NFE_SYSCTL_STAT_ADD32(ctx, child, "carrier_losts", 3156 &stats->tx_carrier_losts, "Carrier Losts"); 3157 NFE_SYSCTL_STAT_ADD32(ctx, child, "excess_deferrals", 3158 &stats->tx_excess_deferals, "Excess Deferrals"); 3159 NFE_SYSCTL_STAT_ADD32(ctx, child, "retry_errors", 3160 &stats->tx_retry_errors, "Retry Errors"); 3161 if ((sc->nfe_flags & NFE_MIB_V2) != 0) { 3162 NFE_SYSCTL_STAT_ADD32(ctx, child, "deferrals", 3163 &stats->tx_deferals, "Deferrals"); 3164 NFE_SYSCTL_STAT_ADD32(ctx, child, "frames", 3165 &stats->tx_frames, "Frames"); 3166 NFE_SYSCTL_STAT_ADD32(ctx, child, "pause", 3167 &stats->tx_pause, "Pause Frames"); 3168 } 3169 if ((sc->nfe_flags & NFE_MIB_V3) != 0) { 3170 NFE_SYSCTL_STAT_ADD32(ctx, child, "unicast", 3171 &stats->tx_deferals, "Unicast Frames"); 3172 NFE_SYSCTL_STAT_ADD32(ctx, child, "multicast", 3173 &stats->tx_frames, "Multicast Frames"); 3174 NFE_SYSCTL_STAT_ADD32(ctx, child, "broadcast", 3175 &stats->tx_pause, "Broadcast Frames"); 3176 } 3177 } 3178 3179 #undef NFE_SYSCTL_STAT_ADD32 3180 #undef NFE_SYSCTL_STAT_ADD64 3181 3182 static void 3183 nfe_stats_clear(struct nfe_softc *sc) 3184 { 3185 int i, mib_cnt; 3186 3187 if ((sc->nfe_flags & NFE_MIB_V1) != 0) 3188 mib_cnt = NFE_NUM_MIB_STATV1; 3189 else if ((sc->nfe_flags & (NFE_MIB_V2 | NFE_MIB_V3)) != 0) 3190 mib_cnt = NFE_NUM_MIB_STATV2; 3191 else 3192 return; 3193 3194 for (i = 0; i < mib_cnt; i++) 3195 NFE_READ(sc, NFE_TX_OCTET + i * sizeof(uint32_t)); 3196 3197 if ((sc->nfe_flags & NFE_MIB_V3) != 0) { 3198 NFE_READ(sc, NFE_TX_UNICAST); 3199 NFE_READ(sc, NFE_TX_MULTICAST); 3200 NFE_READ(sc, NFE_TX_BROADCAST); 3201 } 3202 } 3203 3204 static void 3205 nfe_stats_update(struct nfe_softc *sc) 3206 { 3207 struct nfe_hw_stats *stats; 3208 3209 NFE_LOCK_ASSERT(sc); 3210 3211 if ((sc->nfe_flags & (NFE_MIB_V1 | NFE_MIB_V2 | NFE_MIB_V3)) == 0) 3212 return; 3213 3214 stats = &sc->nfe_stats; 3215 stats->tx_octets += NFE_READ(sc, NFE_TX_OCTET); 3216 stats->tx_zero_rexmits += NFE_READ(sc, NFE_TX_ZERO_REXMIT); 3217 stats->tx_one_rexmits += NFE_READ(sc, NFE_TX_ONE_REXMIT); 3218 stats->tx_multi_rexmits += NFE_READ(sc, NFE_TX_MULTI_REXMIT); 3219 stats->tx_late_cols += NFE_READ(sc, NFE_TX_LATE_COL); 3220 stats->tx_fifo_underuns += NFE_READ(sc, NFE_TX_FIFO_UNDERUN); 3221 stats->tx_carrier_losts += NFE_READ(sc, NFE_TX_CARRIER_LOST); 3222 stats->tx_excess_deferals += NFE_READ(sc, NFE_TX_EXCESS_DEFERRAL); 3223 stats->tx_retry_errors += NFE_READ(sc, NFE_TX_RETRY_ERROR); 3224 stats->rx_frame_errors += NFE_READ(sc, NFE_RX_FRAME_ERROR); 3225 stats->rx_extra_bytes += NFE_READ(sc, NFE_RX_EXTRA_BYTES); 3226 stats->rx_late_cols += NFE_READ(sc, NFE_RX_LATE_COL); 3227 stats->rx_runts += NFE_READ(sc, NFE_RX_RUNT); 3228 stats->rx_jumbos += NFE_READ(sc, NFE_RX_JUMBO); 3229 stats->rx_fifo_overuns += NFE_READ(sc, NFE_RX_FIFO_OVERUN); 3230 stats->rx_crc_errors += NFE_READ(sc, NFE_RX_CRC_ERROR); 3231 stats->rx_fae += NFE_READ(sc, NFE_RX_FAE); 3232 stats->rx_len_errors += NFE_READ(sc, NFE_RX_LEN_ERROR); 3233 stats->rx_unicast += NFE_READ(sc, NFE_RX_UNICAST); 3234 stats->rx_multicast += NFE_READ(sc, NFE_RX_MULTICAST); 3235 stats->rx_broadcast += NFE_READ(sc, NFE_RX_BROADCAST); 3236 3237 if ((sc->nfe_flags & NFE_MIB_V2) != 0) { 3238 stats->tx_deferals += NFE_READ(sc, NFE_TX_DEFERAL); 3239 stats->tx_frames += NFE_READ(sc, NFE_TX_FRAME); 3240 stats->rx_octets += NFE_READ(sc, NFE_RX_OCTET); 3241 stats->tx_pause += NFE_READ(sc, NFE_TX_PAUSE); 3242 stats->rx_pause += NFE_READ(sc, NFE_RX_PAUSE); 3243 stats->rx_drops += NFE_READ(sc, NFE_RX_DROP); 3244 } 3245 3246 if ((sc->nfe_flags & NFE_MIB_V3) != 0) { 3247 stats->tx_unicast += NFE_READ(sc, NFE_TX_UNICAST); 3248 stats->tx_multicast += NFE_READ(sc, NFE_TX_MULTICAST); 3249 stats->tx_broadcast += NFE_READ(sc, NFE_TX_BROADCAST); 3250 } 3251 } 3252 3253 static void 3254 nfe_set_linkspeed(struct nfe_softc *sc) 3255 { 3256 struct mii_softc *miisc; 3257 struct mii_data *mii; 3258 int aneg, i, phyno; 3259 3260 NFE_LOCK_ASSERT(sc); 3261 3262 mii = device_get_softc(sc->nfe_miibus); 3263 mii_pollstat(mii); 3264 aneg = 0; 3265 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 3266 (IFM_ACTIVE | IFM_AVALID)) { 3267 switch IFM_SUBTYPE(mii->mii_media_active) { 3268 case IFM_10_T: 3269 case IFM_100_TX: 3270 return; 3271 case IFM_1000_T: 3272 aneg++; 3273 break; 3274 default: 3275 break; 3276 } 3277 } 3278 miisc = LIST_FIRST(&mii->mii_phys); 3279 phyno = miisc->mii_phy; 3280 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 3281 PHY_RESET(miisc); 3282 nfe_miibus_writereg(sc->nfe_dev, phyno, MII_100T2CR, 0); 3283 nfe_miibus_writereg(sc->nfe_dev, phyno, 3284 MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA); 3285 nfe_miibus_writereg(sc->nfe_dev, phyno, 3286 MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG); 3287 DELAY(1000); 3288 if (aneg != 0) { 3289 /* 3290 * Poll link state until nfe(4) get a 10/100Mbps link. 3291 */ 3292 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) { 3293 mii_pollstat(mii); 3294 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) 3295 == (IFM_ACTIVE | IFM_AVALID)) { 3296 switch (IFM_SUBTYPE(mii->mii_media_active)) { 3297 case IFM_10_T: 3298 case IFM_100_TX: 3299 nfe_mac_config(sc, mii); 3300 return; 3301 default: 3302 break; 3303 } 3304 } 3305 NFE_UNLOCK(sc); 3306 pause("nfelnk", hz); 3307 NFE_LOCK(sc); 3308 } 3309 if (i == MII_ANEGTICKS_GIGE) 3310 device_printf(sc->nfe_dev, 3311 "establishing a link failed, WOL may not work!"); 3312 } 3313 /* 3314 * No link, force MAC to have 100Mbps, full-duplex link. 3315 * This is the last resort and may/may not work. 3316 */ 3317 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE; 3318 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 3319 nfe_mac_config(sc, mii); 3320 } 3321 3322 static void 3323 nfe_set_wol(struct nfe_softc *sc) 3324 { 3325 if_t ifp; 3326 uint32_t wolctl; 3327 int pmc; 3328 uint16_t pmstat; 3329 3330 NFE_LOCK_ASSERT(sc); 3331 3332 if (pci_find_cap(sc->nfe_dev, PCIY_PMG, &pmc) != 0) 3333 return; 3334 ifp = sc->nfe_ifp; 3335 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) != 0) 3336 wolctl = NFE_WOL_MAGIC; 3337 else 3338 wolctl = 0; 3339 NFE_WRITE(sc, NFE_WOL_CTL, wolctl); 3340 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) != 0) { 3341 nfe_set_linkspeed(sc); 3342 if ((sc->nfe_flags & NFE_PWR_MGMT) != 0) 3343 NFE_WRITE(sc, NFE_PWR2_CTL, 3344 NFE_READ(sc, NFE_PWR2_CTL) & ~NFE_PWR2_GATE_CLOCKS); 3345 /* Enable RX. */ 3346 NFE_WRITE(sc, NFE_RX_RING_ADDR_HI, 0); 3347 NFE_WRITE(sc, NFE_RX_RING_ADDR_LO, 0); 3348 NFE_WRITE(sc, NFE_RX_CTL, NFE_READ(sc, NFE_RX_CTL) | 3349 NFE_RX_START); 3350 } 3351 /* Request PME if WOL is requested. */ 3352 pmstat = pci_read_config(sc->nfe_dev, pmc + PCIR_POWER_STATUS, 2); 3353 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 3354 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) 3355 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 3356 pci_write_config(sc->nfe_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 3357 } 3358