1 /* 2 * Copyright (c) 2017 Stormshield. 3 * Copyright (c) 2017 Semihalf. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 24 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 * 27 */ 28 29 #ifndef _IF_MVNETAVAR_H_ 30 #define _IF_MVNETAVAR_H_ 31 #include <net/if.h> 32 33 #define MVNETA_HWHEADER_SIZE 2 /* Marvell Header */ 34 #define MVNETA_ETHER_SIZE 22 /* Maximum ether size */ 35 #define MVNETA_A370_MAX_CSUM_MTU 1600 /* Max frame len for TX csum */ 36 #define MVNETA_A3700_MAX_CSUM_MTU 9600 37 38 #define MVNETA_MAX_FRAME (MJUM9BYTES) 39 40 /* 41 * Default limit of queue length 42 * 43 * queue 0 is lowest priority and queue 7 is highest priority. 44 * IP packet is received on queue 7 by default. 45 */ 46 #define MVNETA_TX_RING_CNT 512 47 #define MVNETA_RX_RING_CNT 256 48 49 #define MVNETA_BUFRING_SIZE 1024 50 51 #define MVNETA_PACKET_OFFSET 64 52 53 #define MVNETA_RXTH_COUNT 128 54 #define MVNETA_RX_REFILL_COUNT 8 55 #define MVNETA_TX_RECLAIM_COUNT 32 56 57 /* 58 * Device Register access 59 */ 60 #define MVNETA_READ(sc, reg) \ 61 bus_read_4((sc)->res[0], (reg)) 62 #define MVNETA_WRITE(sc, reg, val) \ 63 bus_write_4((sc)->res[0], (reg), (val)) 64 65 #define MVNETA_READ_REGION(sc, reg, val, c) \ 66 bus_read_region_4((sc)->res[0], (reg), (val), (c)) 67 #define MVNETA_WRITE_REGION(sc, reg, val, c) \ 68 bus_write_region_4((sc)->res[0], (reg), (val), (c)) 69 70 #define MVNETA_READ_MIB(sc, reg) \ 71 bus_read_4((sc)->res[0], MVNETA_PORTMIB_BASE + (reg)) 72 73 #define MVNETA_IS_LINKUP(sc) \ 74 (MVNETA_READ((sc), MVNETA_PSR) & MVNETA_PSR_LINKUP) 75 76 #define MVNETA_IS_QUEUE_SET(queues, q) \ 77 ((((queues) >> (q)) & 0x1)) 78 79 /* 80 * EEE: Lower Power Idle config 81 * Default timer is duration of MTU sized frame transmission. 82 * The timer can be negotiated by LLDP protocol, but we have no 83 * support. 84 */ 85 #define MVNETA_LPI_TS (ETHERMTU * 8 / 1000) /* [us] */ 86 #define MVNETA_LPI_TW (ETHERMTU * 8 / 1000) /* [us] */ 87 #define MVNETA_LPI_LI (ETHERMTU * 8 / 1000) /* [us] */ 88 89 /* 90 * DMA Descriptor 91 * 92 * the ethernet device has 8 rx/tx DMA queues. each of queue has its own 93 * decriptor list. descriptors are simply index by counter inside the device. 94 */ 95 #define MVNETA_TX_SEGLIMIT 32 96 97 #define MVNETA_QUEUE_IDLE 1 98 #define MVNETA_QUEUE_WORKING 2 99 #define MVNETA_QUEUE_DISABLED 3 100 101 struct mvneta_buf { 102 struct mbuf * m; /* pointer to related mbuf */ 103 bus_dmamap_t dmap; 104 }; 105 106 struct mvneta_rx_ring { 107 int queue_status; 108 /* Real descriptors array. shared by RxDMA */ 109 struct mvneta_rx_desc *desc; 110 bus_dmamap_t desc_map; 111 bus_addr_t desc_pa; 112 113 /* Virtual address of the RX buffer */ 114 void *rxbuf_virt_addr[MVNETA_RX_RING_CNT]; 115 116 /* Managment entries for each of descritors */ 117 struct mvneta_buf rxbuf[MVNETA_RX_RING_CNT]; 118 119 /* locks */ 120 struct mtx ring_mtx; 121 122 /* Index */ 123 int dma; 124 int cpu; 125 126 /* Limit */ 127 int queue_th_received; 128 int queue_th_time; /* [Tclk] */ 129 130 /* LRO */ 131 struct lro_ctrl lro; 132 boolean_t lro_enabled; 133 /* Is this queue out of mbuf */ 134 boolean_t needs_refill; 135 } __aligned(CACHE_LINE_SIZE); 136 137 struct mvneta_tx_ring { 138 /* Index of this queue */ 139 int qidx; 140 /* IFNET pointer */ 141 if_t ifp; 142 /* Ring buffer for IFNET */ 143 struct buf_ring *br; 144 /* Real descriptors array. shared by TxDMA */ 145 struct mvneta_tx_desc *desc; 146 bus_dmamap_t desc_map; 147 bus_addr_t desc_pa; 148 149 /* Managment entries for each of descritors */ 150 struct mvneta_buf txbuf[MVNETA_TX_RING_CNT]; 151 152 /* locks */ 153 struct mtx ring_mtx; 154 155 /* Index */ 156 int used; 157 int dma; 158 int cpu; 159 160 /* watchdog */ 161 #define MVNETA_WATCHDOG_TXCOMP (hz / 10) /* 100ms */ 162 #define MVNETA_WATCHDOG (10 * hz) /* 10s */ 163 int watchdog_time; 164 int queue_status; 165 boolean_t queue_hung; 166 167 /* Task */ 168 struct task task; 169 struct taskqueue *taskq; 170 171 /* Stats */ 172 uint32_t drv_error; 173 } __aligned(CACHE_LINE_SIZE); 174 175 static __inline int 176 tx_counter_adv(int ctr, int n) 177 { 178 179 ctr += n; 180 while (__predict_false(ctr >= MVNETA_TX_RING_CNT)) 181 ctr -= MVNETA_TX_RING_CNT; 182 183 return (ctr); 184 } 185 186 static __inline int 187 rx_counter_adv(int ctr, int n) 188 { 189 190 ctr += n; 191 while (__predict_false(ctr >= MVNETA_RX_RING_CNT)) 192 ctr -= MVNETA_RX_RING_CNT; 193 194 return (ctr); 195 } 196 197 /* 198 * Timeout control 199 */ 200 #define MVNETA_PHY_TIMEOUT 10000 /* msec */ 201 #define RX_DISABLE_TIMEOUT 0x1000000 /* times */ 202 #define TX_DISABLE_TIMEOUT 0x1000000 /* times */ 203 #define TX_FIFO_EMPTY_TIMEOUT 0x1000000 /* times */ 204 205 /* 206 * Debug 207 */ 208 #define KASSERT_SC_MTX(sc) \ 209 KASSERT(mtx_owned(&(sc)->mtx), ("SC mutex not owned")) 210 #define KASSERT_BM_MTX(sc) \ 211 KASSERT(mtx_owned(&(sc)->bm.bm_mtx), ("BM mutex not owned")) 212 #define KASSERT_RX_MTX(sc, q) \ 213 KASSERT(mtx_owned(&(sc)->rx_ring[(q)].ring_mtx),\ 214 ("RX mutex not owned")) 215 #define KASSERT_TX_MTX(sc, q) \ 216 KASSERT(mtx_owned(&(sc)->tx_ring[(q)].ring_mtx),\ 217 ("TX mutex not owned")) 218 219 /* 220 * sysctl(9) parameters 221 */ 222 struct mvneta_sysctl_queue { 223 struct mvneta_softc *sc; 224 int rxtx; 225 int queue; 226 }; 227 #define MVNETA_SYSCTL_RX 0 228 #define MVNETA_SYSCTL_TX 1 229 230 struct mvneta_sysctl_mib { 231 struct mvneta_softc *sc; 232 int index; 233 uint64_t counter; 234 }; 235 236 enum mvneta_phy_mode { 237 MVNETA_PHY_QSGMII, 238 MVNETA_PHY_SGMII, 239 MVNETA_PHY_RGMII, 240 MVNETA_PHY_RGMII_ID 241 }; 242 243 /* 244 * Ethernet Device main context 245 */ 246 DECLARE_CLASS(mvneta_driver); 247 248 struct mvneta_softc { 249 device_t dev; 250 uint32_t version; 251 /* 252 * mtx must be held by interface functions to/from 253 * other frameworks. interrupt handler, sysctl handler, 254 * ioctl handler, and so on. 255 */ 256 struct mtx mtx; 257 struct resource *res[2]; 258 void *ih_cookie[1]; 259 260 uint64_t clk_freq; 261 262 if_t ifp; 263 uint32_t mvneta_if_flags; 264 uint32_t mvneta_media; 265 uint32_t tx_csum_limit; 266 uint32_t rx_frame_size; 267 268 int phy_attached; 269 enum mvneta_phy_mode phy_mode; 270 int phy_addr; 271 int phy_speed; /* PHY speed */ 272 boolean_t phy_fdx; /* Full duplex mode */ 273 boolean_t autoneg; /* Autonegotiation status */ 274 boolean_t use_inband_status; /* In-band link status */ 275 276 /* 277 * Link State control 278 */ 279 boolean_t linkup; 280 device_t miibus; 281 struct mii_data *mii; 282 uint8_t enaddr[ETHER_ADDR_LEN]; 283 struct ifmedia mvneta_ifmedia; 284 285 bus_dma_tag_t rx_dtag; 286 bus_dma_tag_t rxbuf_dtag; 287 bus_dma_tag_t tx_dtag; 288 bus_dma_tag_t txmbuf_dtag; 289 struct mvneta_rx_ring rx_ring[MVNETA_RX_QNUM_MAX]; 290 struct mvneta_tx_ring tx_ring[MVNETA_TX_QNUM_MAX]; 291 292 /* 293 * Maintance clock 294 */ 295 struct callout tick_ch; 296 297 int cf_lpi; 298 int cf_fc; 299 int debug; 300 301 /* 302 * Sysctl interfaces 303 */ 304 struct mvneta_sysctl_queue sysctl_rx_queue[MVNETA_RX_QNUM_MAX]; 305 struct mvneta_sysctl_queue sysctl_tx_queue[MVNETA_TX_QNUM_MAX]; 306 307 /* 308 * MIB counter 309 */ 310 struct mvneta_sysctl_mib sysctl_mib[MVNETA_PORTMIB_NOCOUNTER]; 311 uint64_t counter_pdfc; 312 uint64_t counter_pofc; 313 uint32_t counter_watchdog; /* manual reset when clearing mib */ 314 uint32_t counter_watchdog_mib; /* reset after each mib update */ 315 }; 316 #define MVNETA_RX_RING(sc, q) \ 317 (&(sc)->rx_ring[(q)]) 318 #define MVNETA_TX_RING(sc, q) \ 319 (&(sc)->tx_ring[(q)]) 320 321 int mvneta_attach(device_t); 322 323 #ifdef FDT 324 boolean_t mvneta_has_switch_fdt(device_t); 325 int mvneta_fdt_mac_address(struct mvneta_softc *, uint8_t *); 326 #endif 327 328 #endif /* _IF_MVNETAVAR_H_ */ 329