1 /* 2 * Copyright (c) 2017 Stormshield. 3 * Copyright (c) 2017 Semihalf. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 24 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include "opt_platform.h" 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/endian.h> 35 #include <sys/mbuf.h> 36 #include <sys/lock.h> 37 #include <sys/mutex.h> 38 #include <sys/kernel.h> 39 #include <sys/module.h> 40 #include <sys/socket.h> 41 #include <sys/sysctl.h> 42 #include <sys/smp.h> 43 #include <sys/taskqueue.h> 44 #ifdef MVNETA_KTR 45 #include <sys/ktr.h> 46 #endif 47 48 #include <net/ethernet.h> 49 #include <net/bpf.h> 50 #include <net/if.h> 51 #include <net/if_arp.h> 52 #include <net/if_dl.h> 53 #include <net/if_media.h> 54 #include <net/if_types.h> 55 #include <net/if_vlan_var.h> 56 57 #include <netinet/in_systm.h> 58 #include <netinet/in.h> 59 #include <netinet/ip.h> 60 #include <netinet/tcp_lro.h> 61 62 #include <sys/sockio.h> 63 #include <sys/bus.h> 64 #include <machine/bus.h> 65 #include <sys/rman.h> 66 #include <machine/resource.h> 67 68 #if defined(__aarch64__) 69 #include <dev/extres/clk/clk.h> 70 #endif 71 72 #include <dev/mii/mii.h> 73 #include <dev/mii/miivar.h> 74 75 #include <dev/mdio/mdio.h> 76 77 #include <arm/mv/mvvar.h> 78 79 #if !defined(__aarch64__) 80 #include <arm/mv/mvreg.h> 81 #include <arm/mv/mvwin.h> 82 #endif 83 84 #include "if_mvnetareg.h" 85 #include "if_mvnetavar.h" 86 87 #include "miibus_if.h" 88 #include "mdio_if.h" 89 90 #ifdef MVNETA_DEBUG 91 #define STATIC /* nothing */ 92 #else 93 #define STATIC static 94 #endif 95 96 #define DASSERT(x) KASSERT((x), (#x)) 97 98 #define A3700_TCLK_250MHZ 250000000 99 100 /* Device Register Initialization */ 101 STATIC int mvneta_initreg(struct ifnet *); 102 103 /* Descriptor Ring Control for each of queues */ 104 STATIC int mvneta_ring_alloc_rx_queue(struct mvneta_softc *, int); 105 STATIC int mvneta_ring_alloc_tx_queue(struct mvneta_softc *, int); 106 STATIC void mvneta_ring_dealloc_rx_queue(struct mvneta_softc *, int); 107 STATIC void mvneta_ring_dealloc_tx_queue(struct mvneta_softc *, int); 108 STATIC int mvneta_ring_init_rx_queue(struct mvneta_softc *, int); 109 STATIC int mvneta_ring_init_tx_queue(struct mvneta_softc *, int); 110 STATIC void mvneta_ring_flush_rx_queue(struct mvneta_softc *, int); 111 STATIC void mvneta_ring_flush_tx_queue(struct mvneta_softc *, int); 112 STATIC void mvneta_dmamap_cb(void *, bus_dma_segment_t *, int, int); 113 STATIC int mvneta_dma_create(struct mvneta_softc *); 114 115 /* Rx/Tx Queue Control */ 116 STATIC int mvneta_rx_queue_init(struct ifnet *, int); 117 STATIC int mvneta_tx_queue_init(struct ifnet *, int); 118 STATIC int mvneta_rx_queue_enable(struct ifnet *, int); 119 STATIC int mvneta_tx_queue_enable(struct ifnet *, int); 120 STATIC void mvneta_rx_lockq(struct mvneta_softc *, int); 121 STATIC void mvneta_rx_unlockq(struct mvneta_softc *, int); 122 STATIC void mvneta_tx_lockq(struct mvneta_softc *, int); 123 STATIC void mvneta_tx_unlockq(struct mvneta_softc *, int); 124 125 /* Interrupt Handlers */ 126 STATIC void mvneta_disable_intr(struct mvneta_softc *); 127 STATIC void mvneta_enable_intr(struct mvneta_softc *); 128 STATIC void mvneta_rxtxth_intr(void *); 129 STATIC int mvneta_misc_intr(struct mvneta_softc *); 130 STATIC void mvneta_tick(void *); 131 /* struct ifnet and mii callbacks*/ 132 STATIC int mvneta_xmitfast_locked(struct mvneta_softc *, int, struct mbuf **); 133 STATIC int mvneta_xmit_locked(struct mvneta_softc *, int); 134 #ifdef MVNETA_MULTIQUEUE 135 STATIC int mvneta_transmit(struct ifnet *, struct mbuf *); 136 #else /* !MVNETA_MULTIQUEUE */ 137 STATIC void mvneta_start(struct ifnet *); 138 #endif 139 STATIC void mvneta_qflush(struct ifnet *); 140 STATIC void mvneta_tx_task(void *, int); 141 STATIC int mvneta_ioctl(struct ifnet *, u_long, caddr_t); 142 STATIC void mvneta_init(void *); 143 STATIC void mvneta_init_locked(void *); 144 STATIC void mvneta_stop(struct mvneta_softc *); 145 STATIC void mvneta_stop_locked(struct mvneta_softc *); 146 STATIC int mvneta_mediachange(struct ifnet *); 147 STATIC void mvneta_mediastatus(struct ifnet *, struct ifmediareq *); 148 STATIC void mvneta_portup(struct mvneta_softc *); 149 STATIC void mvneta_portdown(struct mvneta_softc *); 150 151 /* Link State Notify */ 152 STATIC void mvneta_update_autoneg(struct mvneta_softc *, int); 153 STATIC int mvneta_update_media(struct mvneta_softc *, int); 154 STATIC void mvneta_adjust_link(struct mvneta_softc *); 155 STATIC void mvneta_update_eee(struct mvneta_softc *); 156 STATIC void mvneta_update_fc(struct mvneta_softc *); 157 STATIC void mvneta_link_isr(struct mvneta_softc *); 158 STATIC void mvneta_linkupdate(struct mvneta_softc *, boolean_t); 159 STATIC void mvneta_linkup(struct mvneta_softc *); 160 STATIC void mvneta_linkdown(struct mvneta_softc *); 161 STATIC void mvneta_linkreset(struct mvneta_softc *); 162 163 /* Tx Subroutines */ 164 STATIC int mvneta_tx_queue(struct mvneta_softc *, struct mbuf **, int); 165 STATIC void mvneta_tx_set_csumflag(struct ifnet *, 166 struct mvneta_tx_desc *, struct mbuf *); 167 STATIC void mvneta_tx_queue_complete(struct mvneta_softc *, int); 168 STATIC void mvneta_tx_drain(struct mvneta_softc *); 169 170 /* Rx Subroutines */ 171 STATIC int mvneta_rx(struct mvneta_softc *, int, int); 172 STATIC void mvneta_rx_queue(struct mvneta_softc *, int, int); 173 STATIC void mvneta_rx_queue_refill(struct mvneta_softc *, int); 174 STATIC void mvneta_rx_set_csumflag(struct ifnet *, 175 struct mvneta_rx_desc *, struct mbuf *); 176 STATIC void mvneta_rx_buf_free(struct mvneta_softc *, struct mvneta_buf *); 177 178 /* MAC address filter */ 179 STATIC void mvneta_filter_setup(struct mvneta_softc *); 180 181 /* sysctl(9) */ 182 STATIC int sysctl_read_mib(SYSCTL_HANDLER_ARGS); 183 STATIC int sysctl_clear_mib(SYSCTL_HANDLER_ARGS); 184 STATIC int sysctl_set_queue_rxthtime(SYSCTL_HANDLER_ARGS); 185 STATIC void sysctl_mvneta_init(struct mvneta_softc *); 186 187 /* MIB */ 188 STATIC void mvneta_clear_mib(struct mvneta_softc *); 189 STATIC uint64_t mvneta_read_mib(struct mvneta_softc *, int); 190 STATIC void mvneta_update_mib(struct mvneta_softc *); 191 192 /* Switch */ 193 STATIC boolean_t mvneta_has_switch(device_t); 194 195 #define mvneta_sc_lock(sc) mtx_lock(&sc->mtx) 196 #define mvneta_sc_unlock(sc) mtx_unlock(&sc->mtx) 197 198 STATIC struct mtx mii_mutex; 199 STATIC int mii_init = 0; 200 201 /* Device */ 202 STATIC int mvneta_detach(device_t); 203 /* MII */ 204 STATIC int mvneta_miibus_readreg(device_t, int, int); 205 STATIC int mvneta_miibus_writereg(device_t, int, int, int); 206 207 static device_method_t mvneta_methods[] = { 208 /* Device interface */ 209 DEVMETHOD(device_detach, mvneta_detach), 210 /* MII interface */ 211 DEVMETHOD(miibus_readreg, mvneta_miibus_readreg), 212 DEVMETHOD(miibus_writereg, mvneta_miibus_writereg), 213 /* MDIO interface */ 214 DEVMETHOD(mdio_readreg, mvneta_miibus_readreg), 215 DEVMETHOD(mdio_writereg, mvneta_miibus_writereg), 216 217 /* End */ 218 DEVMETHOD_END 219 }; 220 221 DEFINE_CLASS_0(mvneta, mvneta_driver, mvneta_methods, sizeof(struct mvneta_softc)); 222 223 DRIVER_MODULE(miibus, mvneta, miibus_driver, miibus_devclass, 0, 0); 224 DRIVER_MODULE(mdio, mvneta, mdio_driver, mdio_devclass, 0, 0); 225 MODULE_DEPEND(mvneta, mdio, 1, 1, 1); 226 MODULE_DEPEND(mvneta, ether, 1, 1, 1); 227 MODULE_DEPEND(mvneta, miibus, 1, 1, 1); 228 MODULE_DEPEND(mvneta, mvxpbm, 1, 1, 1); 229 230 /* 231 * List of MIB register and names 232 */ 233 enum mvneta_mib_idx 234 { 235 MVNETA_MIB_RX_GOOD_OCT_IDX, 236 MVNETA_MIB_RX_BAD_OCT_IDX, 237 MVNETA_MIB_TX_MAC_TRNS_ERR_IDX, 238 MVNETA_MIB_RX_GOOD_FRAME_IDX, 239 MVNETA_MIB_RX_BAD_FRAME_IDX, 240 MVNETA_MIB_RX_BCAST_FRAME_IDX, 241 MVNETA_MIB_RX_MCAST_FRAME_IDX, 242 MVNETA_MIB_RX_FRAME64_OCT_IDX, 243 MVNETA_MIB_RX_FRAME127_OCT_IDX, 244 MVNETA_MIB_RX_FRAME255_OCT_IDX, 245 MVNETA_MIB_RX_FRAME511_OCT_IDX, 246 MVNETA_MIB_RX_FRAME1023_OCT_IDX, 247 MVNETA_MIB_RX_FRAMEMAX_OCT_IDX, 248 MVNETA_MIB_TX_GOOD_OCT_IDX, 249 MVNETA_MIB_TX_GOOD_FRAME_IDX, 250 MVNETA_MIB_TX_EXCES_COL_IDX, 251 MVNETA_MIB_TX_MCAST_FRAME_IDX, 252 MVNETA_MIB_TX_BCAST_FRAME_IDX, 253 MVNETA_MIB_TX_MAC_CTL_ERR_IDX, 254 MVNETA_MIB_FC_SENT_IDX, 255 MVNETA_MIB_FC_GOOD_IDX, 256 MVNETA_MIB_FC_BAD_IDX, 257 MVNETA_MIB_PKT_UNDERSIZE_IDX, 258 MVNETA_MIB_PKT_FRAGMENT_IDX, 259 MVNETA_MIB_PKT_OVERSIZE_IDX, 260 MVNETA_MIB_PKT_JABBER_IDX, 261 MVNETA_MIB_MAC_RX_ERR_IDX, 262 MVNETA_MIB_MAC_CRC_ERR_IDX, 263 MVNETA_MIB_MAC_COL_IDX, 264 MVNETA_MIB_MAC_LATE_COL_IDX, 265 }; 266 267 STATIC struct mvneta_mib_def { 268 uint32_t regnum; 269 int reg64; 270 const char *sysctl_name; 271 const char *desc; 272 } mvneta_mib_list[] = { 273 [MVNETA_MIB_RX_GOOD_OCT_IDX] = {MVNETA_MIB_RX_GOOD_OCT, 1, 274 "rx_good_oct", "Good Octets Rx"}, 275 [MVNETA_MIB_RX_BAD_OCT_IDX] = {MVNETA_MIB_RX_BAD_OCT, 0, 276 "rx_bad_oct", "Bad Octets Rx"}, 277 [MVNETA_MIB_TX_MAC_TRNS_ERR_IDX] = {MVNETA_MIB_TX_MAC_TRNS_ERR, 0, 278 "tx_mac_err", "MAC Transmit Error"}, 279 [MVNETA_MIB_RX_GOOD_FRAME_IDX] = {MVNETA_MIB_RX_GOOD_FRAME, 0, 280 "rx_good_frame", "Good Frames Rx"}, 281 [MVNETA_MIB_RX_BAD_FRAME_IDX] = {MVNETA_MIB_RX_BAD_FRAME, 0, 282 "rx_bad_frame", "Bad Frames Rx"}, 283 [MVNETA_MIB_RX_BCAST_FRAME_IDX] = {MVNETA_MIB_RX_BCAST_FRAME, 0, 284 "rx_bcast_frame", "Broadcast Frames Rx"}, 285 [MVNETA_MIB_RX_MCAST_FRAME_IDX] = {MVNETA_MIB_RX_MCAST_FRAME, 0, 286 "rx_mcast_frame", "Multicast Frames Rx"}, 287 [MVNETA_MIB_RX_FRAME64_OCT_IDX] = {MVNETA_MIB_RX_FRAME64_OCT, 0, 288 "rx_frame_1_64", "Frame Size 1 - 64"}, 289 [MVNETA_MIB_RX_FRAME127_OCT_IDX] = {MVNETA_MIB_RX_FRAME127_OCT, 0, 290 "rx_frame_65_127", "Frame Size 65 - 127"}, 291 [MVNETA_MIB_RX_FRAME255_OCT_IDX] = {MVNETA_MIB_RX_FRAME255_OCT, 0, 292 "rx_frame_128_255", "Frame Size 128 - 255"}, 293 [MVNETA_MIB_RX_FRAME511_OCT_IDX] = {MVNETA_MIB_RX_FRAME511_OCT, 0, 294 "rx_frame_256_511", "Frame Size 256 - 511"}, 295 [MVNETA_MIB_RX_FRAME1023_OCT_IDX] = {MVNETA_MIB_RX_FRAME1023_OCT, 0, 296 "rx_frame_512_1023", "Frame Size 512 - 1023"}, 297 [MVNETA_MIB_RX_FRAMEMAX_OCT_IDX] = {MVNETA_MIB_RX_FRAMEMAX_OCT, 0, 298 "rx_fame_1024_max", "Frame Size 1024 - Max"}, 299 [MVNETA_MIB_TX_GOOD_OCT_IDX] = {MVNETA_MIB_TX_GOOD_OCT, 1, 300 "tx_good_oct", "Good Octets Tx"}, 301 [MVNETA_MIB_TX_GOOD_FRAME_IDX] = {MVNETA_MIB_TX_GOOD_FRAME, 0, 302 "tx_good_frame", "Good Frames Tx"}, 303 [MVNETA_MIB_TX_EXCES_COL_IDX] = {MVNETA_MIB_TX_EXCES_COL, 0, 304 "tx_exces_collision", "Excessive Collision"}, 305 [MVNETA_MIB_TX_MCAST_FRAME_IDX] = {MVNETA_MIB_TX_MCAST_FRAME, 0, 306 "tx_mcast_frame", "Multicast Frames Tx"}, 307 [MVNETA_MIB_TX_BCAST_FRAME_IDX] = {MVNETA_MIB_TX_BCAST_FRAME, 0, 308 "tx_bcast_frame", "Broadcast Frames Tx"}, 309 [MVNETA_MIB_TX_MAC_CTL_ERR_IDX] = {MVNETA_MIB_TX_MAC_CTL_ERR, 0, 310 "tx_mac_ctl_err", "Unknown MAC Control"}, 311 [MVNETA_MIB_FC_SENT_IDX] = {MVNETA_MIB_FC_SENT, 0, 312 "fc_tx", "Flow Control Tx"}, 313 [MVNETA_MIB_FC_GOOD_IDX] = {MVNETA_MIB_FC_GOOD, 0, 314 "fc_rx_good", "Good Flow Control Rx"}, 315 [MVNETA_MIB_FC_BAD_IDX] = {MVNETA_MIB_FC_BAD, 0, 316 "fc_rx_bad", "Bad Flow Control Rx"}, 317 [MVNETA_MIB_PKT_UNDERSIZE_IDX] = {MVNETA_MIB_PKT_UNDERSIZE, 0, 318 "pkt_undersize", "Undersized Packets Rx"}, 319 [MVNETA_MIB_PKT_FRAGMENT_IDX] = {MVNETA_MIB_PKT_FRAGMENT, 0, 320 "pkt_fragment", "Fragmented Packets Rx"}, 321 [MVNETA_MIB_PKT_OVERSIZE_IDX] = {MVNETA_MIB_PKT_OVERSIZE, 0, 322 "pkt_oversize", "Oversized Packets Rx"}, 323 [MVNETA_MIB_PKT_JABBER_IDX] = {MVNETA_MIB_PKT_JABBER, 0, 324 "pkt_jabber", "Jabber Packets Rx"}, 325 [MVNETA_MIB_MAC_RX_ERR_IDX] = {MVNETA_MIB_MAC_RX_ERR, 0, 326 "mac_rx_err", "MAC Rx Errors"}, 327 [MVNETA_MIB_MAC_CRC_ERR_IDX] = {MVNETA_MIB_MAC_CRC_ERR, 0, 328 "mac_crc_err", "MAC CRC Errors"}, 329 [MVNETA_MIB_MAC_COL_IDX] = {MVNETA_MIB_MAC_COL, 0, 330 "mac_collision", "MAC Collision"}, 331 [MVNETA_MIB_MAC_LATE_COL_IDX] = {MVNETA_MIB_MAC_LATE_COL, 0, 332 "mac_late_collision", "MAC Late Collision"}, 333 }; 334 335 static struct resource_spec res_spec[] = { 336 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 337 { SYS_RES_IRQ, 0, RF_ACTIVE }, 338 { -1, 0} 339 }; 340 341 static struct { 342 driver_intr_t *handler; 343 char * description; 344 } mvneta_intrs[] = { 345 { mvneta_rxtxth_intr, "MVNETA aggregated interrupt" }, 346 }; 347 348 static int 349 mvneta_set_mac_address(struct mvneta_softc *sc, uint8_t *addr) 350 { 351 unsigned int mac_h; 352 unsigned int mac_l; 353 354 mac_l = (addr[4] << 8) | (addr[5]); 355 mac_h = (addr[0] << 24) | (addr[1] << 16) | 356 (addr[2] << 8) | (addr[3] << 0); 357 358 MVNETA_WRITE(sc, MVNETA_MACAL, mac_l); 359 MVNETA_WRITE(sc, MVNETA_MACAH, mac_h); 360 return (0); 361 } 362 363 static int 364 mvneta_get_mac_address(struct mvneta_softc *sc, uint8_t *addr) 365 { 366 uint32_t mac_l, mac_h; 367 368 #ifdef FDT 369 if (mvneta_fdt_mac_address(sc, addr) == 0) 370 return (0); 371 #endif 372 /* 373 * Fall back -- use the currently programmed address. 374 */ 375 mac_l = MVNETA_READ(sc, MVNETA_MACAL); 376 mac_h = MVNETA_READ(sc, MVNETA_MACAH); 377 if (mac_l == 0 && mac_h == 0) { 378 /* 379 * Generate pseudo-random MAC. 380 * Set lower part to random number | unit number. 381 */ 382 mac_l = arc4random() & ~0xff; 383 mac_l |= device_get_unit(sc->dev) & 0xff; 384 mac_h = arc4random(); 385 mac_h &= ~(3 << 24); /* Clear multicast and LAA bits */ 386 if (bootverbose) { 387 device_printf(sc->dev, 388 "Could not acquire MAC address. " 389 "Using randomized one.\n"); 390 } 391 } 392 393 addr[0] = (mac_h & 0xff000000) >> 24; 394 addr[1] = (mac_h & 0x00ff0000) >> 16; 395 addr[2] = (mac_h & 0x0000ff00) >> 8; 396 addr[3] = (mac_h & 0x000000ff); 397 addr[4] = (mac_l & 0x0000ff00) >> 8; 398 addr[5] = (mac_l & 0x000000ff); 399 return (0); 400 } 401 402 STATIC boolean_t 403 mvneta_has_switch(device_t self) 404 { 405 #ifdef FDT 406 return (mvneta_has_switch_fdt(self)); 407 #endif 408 409 return (false); 410 } 411 412 STATIC int 413 mvneta_dma_create(struct mvneta_softc *sc) 414 { 415 size_t maxsize, maxsegsz; 416 size_t q; 417 int error; 418 419 /* 420 * Create Tx DMA 421 */ 422 maxsize = maxsegsz = sizeof(struct mvneta_tx_desc) * MVNETA_TX_RING_CNT; 423 424 error = bus_dma_tag_create( 425 bus_get_dma_tag(sc->dev), /* parent */ 426 16, 0, /* alignment, boundary */ 427 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 428 BUS_SPACE_MAXADDR, /* highaddr */ 429 NULL, NULL, /* filtfunc, filtfuncarg */ 430 maxsize, /* maxsize */ 431 1, /* nsegments */ 432 maxsegsz, /* maxsegsz */ 433 0, /* flags */ 434 NULL, NULL, /* lockfunc, lockfuncarg */ 435 &sc->tx_dtag); /* dmat */ 436 if (error != 0) { 437 device_printf(sc->dev, 438 "Failed to create DMA tag for Tx descriptors.\n"); 439 goto fail; 440 } 441 error = bus_dma_tag_create( 442 bus_get_dma_tag(sc->dev), /* parent */ 443 1, 0, /* alignment, boundary */ 444 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 445 BUS_SPACE_MAXADDR, /* highaddr */ 446 NULL, NULL, /* filtfunc, filtfuncarg */ 447 MVNETA_MAX_FRAME, /* maxsize */ 448 MVNETA_TX_SEGLIMIT, /* nsegments */ 449 MVNETA_MAX_FRAME, /* maxsegsz */ 450 BUS_DMA_ALLOCNOW, /* flags */ 451 NULL, NULL, /* lockfunc, lockfuncarg */ 452 &sc->txmbuf_dtag); 453 if (error != 0) { 454 device_printf(sc->dev, 455 "Failed to create DMA tag for Tx mbufs.\n"); 456 goto fail; 457 } 458 459 for (q = 0; q < MVNETA_TX_QNUM_MAX; q++) { 460 error = mvneta_ring_alloc_tx_queue(sc, q); 461 if (error != 0) { 462 device_printf(sc->dev, 463 "Failed to allocate DMA safe memory for TxQ: %zu\n", q); 464 goto fail; 465 } 466 } 467 468 /* 469 * Create Rx DMA. 470 */ 471 /* Create tag for Rx descripors */ 472 error = bus_dma_tag_create( 473 bus_get_dma_tag(sc->dev), /* parent */ 474 32, 0, /* alignment, boundary */ 475 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 476 BUS_SPACE_MAXADDR, /* highaddr */ 477 NULL, NULL, /* filtfunc, filtfuncarg */ 478 sizeof(struct mvneta_rx_desc) * MVNETA_RX_RING_CNT, /* maxsize */ 479 1, /* nsegments */ 480 sizeof(struct mvneta_rx_desc) * MVNETA_RX_RING_CNT, /* maxsegsz */ 481 0, /* flags */ 482 NULL, NULL, /* lockfunc, lockfuncarg */ 483 &sc->rx_dtag); /* dmat */ 484 if (error != 0) { 485 device_printf(sc->dev, 486 "Failed to create DMA tag for Rx descriptors.\n"); 487 goto fail; 488 } 489 490 /* Create tag for Rx buffers */ 491 error = bus_dma_tag_create( 492 bus_get_dma_tag(sc->dev), /* parent */ 493 32, 0, /* alignment, boundary */ 494 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 495 BUS_SPACE_MAXADDR, /* highaddr */ 496 NULL, NULL, /* filtfunc, filtfuncarg */ 497 MVNETA_MAX_FRAME, 1, /* maxsize, nsegments */ 498 MVNETA_MAX_FRAME, /* maxsegsz */ 499 0, /* flags */ 500 NULL, NULL, /* lockfunc, lockfuncarg */ 501 &sc->rxbuf_dtag); /* dmat */ 502 if (error != 0) { 503 device_printf(sc->dev, 504 "Failed to create DMA tag for Rx buffers.\n"); 505 goto fail; 506 } 507 508 for (q = 0; q < MVNETA_RX_QNUM_MAX; q++) { 509 if (mvneta_ring_alloc_rx_queue(sc, q) != 0) { 510 device_printf(sc->dev, 511 "Failed to allocate DMA safe memory for RxQ: %zu\n", q); 512 goto fail; 513 } 514 } 515 516 return (0); 517 fail: 518 mvneta_detach(sc->dev); 519 520 return (error); 521 } 522 523 /* ARGSUSED */ 524 int 525 mvneta_attach(device_t self) 526 { 527 struct mvneta_softc *sc; 528 struct ifnet *ifp; 529 device_t child; 530 int ifm_target; 531 int q, error; 532 #if !defined(__aarch64__) 533 uint32_t reg; 534 #endif 535 #if defined(__aarch64__) 536 clk_t clk; 537 #endif 538 sc = device_get_softc(self); 539 sc->dev = self; 540 541 mtx_init(&sc->mtx, "mvneta_sc", NULL, MTX_DEF); 542 543 error = bus_alloc_resources(self, res_spec, sc->res); 544 if (error) { 545 device_printf(self, "could not allocate resources\n"); 546 return (ENXIO); 547 } 548 549 sc->version = MVNETA_READ(sc, MVNETA_PV); 550 device_printf(self, "version is %x\n", sc->version); 551 callout_init(&sc->tick_ch, 0); 552 553 /* 554 * make sure DMA engines are in reset state 555 */ 556 MVNETA_WRITE(sc, MVNETA_PRXINIT, 0x00000001); 557 MVNETA_WRITE(sc, MVNETA_PTXINIT, 0x00000001); 558 559 #if defined(__aarch64__) 560 error = clk_get_by_ofw_index(sc->dev, ofw_bus_get_node(sc->dev), 0, 561 &clk); 562 if (error != 0) { 563 device_printf(sc->dev, 564 "Cannot get clock, using default frequency: %d\n", 565 A3700_TCLK_250MHZ); 566 sc->clk_freq = A3700_TCLK_250MHZ; 567 } else { 568 error = clk_get_freq(clk, &sc->clk_freq); 569 if (error != 0) { 570 device_printf(sc->dev, 571 "Cannot obtain frequency from parent clock\n"); 572 bus_release_resources(sc->dev, res_spec, sc->res); 573 return (error); 574 } 575 } 576 #else 577 sc->clk_freq = get_tclk(); 578 #endif 579 580 #if !defined(__aarch64__) 581 /* 582 * Disable port snoop for buffers and descriptors 583 * to avoid L2 caching of both without DRAM copy. 584 * Obtain coherency settings from the first MBUS 585 * window attribute. 586 */ 587 if ((MVNETA_READ(sc, MV_WIN_NETA_BASE(0)) & IO_WIN_COH_ATTR_MASK) == 0) { 588 reg = MVNETA_READ(sc, MVNETA_PSNPCFG); 589 reg &= ~MVNETA_PSNPCFG_DESCSNP_MASK; 590 reg &= ~MVNETA_PSNPCFG_BUFSNP_MASK; 591 MVNETA_WRITE(sc, MVNETA_PSNPCFG, reg); 592 } 593 #endif 594 595 error = bus_setup_intr(self, sc->res[1], 596 INTR_TYPE_NET | INTR_MPSAFE, NULL, mvneta_intrs[0].handler, sc, 597 &sc->ih_cookie[0]); 598 if (error) { 599 device_printf(self, "could not setup %s\n", 600 mvneta_intrs[0].description); 601 mvneta_detach(self); 602 return (error); 603 } 604 605 /* 606 * MAC address 607 */ 608 if (mvneta_get_mac_address(sc, sc->enaddr)) { 609 device_printf(self, "no mac address.\n"); 610 return (ENXIO); 611 } 612 mvneta_set_mac_address(sc, sc->enaddr); 613 614 mvneta_disable_intr(sc); 615 616 /* Allocate network interface */ 617 ifp = sc->ifp = if_alloc(IFT_ETHER); 618 if (ifp == NULL) { 619 device_printf(self, "if_alloc() failed\n"); 620 mvneta_detach(self); 621 return (ENOMEM); 622 } 623 if_initname(ifp, device_get_name(self), device_get_unit(self)); 624 625 /* 626 * We can support 802.1Q VLAN-sized frames and jumbo 627 * Ethernet frames. 628 */ 629 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_JUMBO_MTU; 630 631 ifp->if_softc = sc; 632 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 633 #ifdef MVNETA_MULTIQUEUE 634 ifp->if_transmit = mvneta_transmit; 635 ifp->if_qflush = mvneta_qflush; 636 #else /* !MVNETA_MULTIQUEUE */ 637 ifp->if_start = mvneta_start; 638 ifp->if_snd.ifq_drv_maxlen = MVNETA_TX_RING_CNT - 1; 639 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 640 IFQ_SET_READY(&ifp->if_snd); 641 #endif 642 ifp->if_init = mvneta_init; 643 ifp->if_ioctl = mvneta_ioctl; 644 645 /* 646 * We can do IPv4/TCPv4/UDPv4/TCPv6/UDPv6 checksums in hardware. 647 */ 648 ifp->if_capabilities |= IFCAP_HWCSUM; 649 650 /* 651 * As VLAN hardware tagging is not supported 652 * but is necessary to perform VLAN hardware checksums, 653 * it is done in the driver 654 */ 655 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWCSUM; 656 657 /* 658 * Currently IPv6 HW checksum is broken, so make sure it is disabled. 659 */ 660 ifp->if_capabilities &= ~IFCAP_HWCSUM_IPV6; 661 ifp->if_capenable = ifp->if_capabilities; 662 663 /* 664 * Disabled option(s): 665 * - Support for Large Receive Offload 666 */ 667 ifp->if_capabilities |= IFCAP_LRO; 668 669 ifp->if_hwassist = CSUM_IP | CSUM_TCP | CSUM_UDP; 670 671 sc->rx_frame_size = MCLBYTES; /* ether_ifattach() always sets normal mtu */ 672 673 /* 674 * Device DMA Buffer allocation. 675 * Handles resource deallocation in case of failure. 676 */ 677 error = mvneta_dma_create(sc); 678 if (error != 0) { 679 mvneta_detach(self); 680 return (error); 681 } 682 683 /* Initialize queues */ 684 for (q = 0; q < MVNETA_TX_QNUM_MAX; q++) { 685 error = mvneta_ring_init_tx_queue(sc, q); 686 if (error != 0) { 687 mvneta_detach(self); 688 return (error); 689 } 690 } 691 692 for (q = 0; q < MVNETA_RX_QNUM_MAX; q++) { 693 error = mvneta_ring_init_rx_queue(sc, q); 694 if (error != 0) { 695 mvneta_detach(self); 696 return (error); 697 } 698 } 699 700 /* 701 * Enable DMA engines and Initialize Device Registers. 702 */ 703 MVNETA_WRITE(sc, MVNETA_PRXINIT, 0x00000000); 704 MVNETA_WRITE(sc, MVNETA_PTXINIT, 0x00000000); 705 MVNETA_WRITE(sc, MVNETA_PACC, MVNETA_PACC_ACCELERATIONMODE_EDM); 706 mvneta_sc_lock(sc); 707 mvneta_filter_setup(sc); 708 mvneta_sc_unlock(sc); 709 mvneta_initreg(ifp); 710 711 /* 712 * Now MAC is working, setup MII. 713 */ 714 if (mii_init == 0) { 715 /* 716 * MII bus is shared by all MACs and all PHYs in SoC. 717 * serializing the bus access should be safe. 718 */ 719 mtx_init(&mii_mutex, "mvneta_mii", NULL, MTX_DEF); 720 mii_init = 1; 721 } 722 723 /* Attach PHY(s) */ 724 if ((sc->phy_addr != MII_PHY_ANY) && (!sc->use_inband_status)) { 725 error = mii_attach(self, &sc->miibus, ifp, mvneta_mediachange, 726 mvneta_mediastatus, BMSR_DEFCAPMASK, sc->phy_addr, 727 MII_OFFSET_ANY, 0); 728 if (error != 0) { 729 device_printf(self, "MII attach failed, error: %d\n", 730 error); 731 ether_ifdetach(sc->ifp); 732 mvneta_detach(self); 733 return (error); 734 } 735 sc->mii = device_get_softc(sc->miibus); 736 sc->phy_attached = 1; 737 738 /* Disable auto-negotiation in MAC - rely on PHY layer */ 739 mvneta_update_autoneg(sc, FALSE); 740 } else if (sc->use_inband_status == TRUE) { 741 /* In-band link status */ 742 ifmedia_init(&sc->mvneta_ifmedia, 0, mvneta_mediachange, 743 mvneta_mediastatus); 744 745 /* Configure media */ 746 ifmedia_add(&sc->mvneta_ifmedia, IFM_ETHER | IFM_1000_T | IFM_FDX, 747 0, NULL); 748 ifmedia_add(&sc->mvneta_ifmedia, IFM_ETHER | IFM_100_TX, 0, NULL); 749 ifmedia_add(&sc->mvneta_ifmedia, IFM_ETHER | IFM_100_TX | IFM_FDX, 750 0, NULL); 751 ifmedia_add(&sc->mvneta_ifmedia, IFM_ETHER | IFM_10_T, 0, NULL); 752 ifmedia_add(&sc->mvneta_ifmedia, IFM_ETHER | IFM_10_T | IFM_FDX, 753 0, NULL); 754 ifmedia_add(&sc->mvneta_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 755 ifmedia_set(&sc->mvneta_ifmedia, IFM_ETHER | IFM_AUTO); 756 757 /* Enable auto-negotiation */ 758 mvneta_update_autoneg(sc, TRUE); 759 760 mvneta_sc_lock(sc); 761 if (MVNETA_IS_LINKUP(sc)) 762 mvneta_linkup(sc); 763 else 764 mvneta_linkdown(sc); 765 mvneta_sc_unlock(sc); 766 767 } else { 768 /* Fixed-link, use predefined values */ 769 mvneta_update_autoneg(sc, FALSE); 770 ifmedia_init(&sc->mvneta_ifmedia, 0, mvneta_mediachange, 771 mvneta_mediastatus); 772 773 ifm_target = IFM_ETHER; 774 switch (sc->phy_speed) { 775 case 2500: 776 if (sc->phy_mode != MVNETA_PHY_SGMII && 777 sc->phy_mode != MVNETA_PHY_QSGMII) { 778 device_printf(self, 779 "2.5G speed can work only in (Q)SGMII mode\n"); 780 ether_ifdetach(sc->ifp); 781 mvneta_detach(self); 782 return (ENXIO); 783 } 784 ifm_target |= IFM_2500_T; 785 break; 786 case 1000: 787 ifm_target |= IFM_1000_T; 788 break; 789 case 100: 790 ifm_target |= IFM_100_TX; 791 break; 792 case 10: 793 ifm_target |= IFM_10_T; 794 break; 795 default: 796 ether_ifdetach(sc->ifp); 797 mvneta_detach(self); 798 return (ENXIO); 799 } 800 801 if (sc->phy_fdx) 802 ifm_target |= IFM_FDX; 803 else 804 ifm_target |= IFM_HDX; 805 806 ifmedia_add(&sc->mvneta_ifmedia, ifm_target, 0, NULL); 807 ifmedia_set(&sc->mvneta_ifmedia, ifm_target); 808 if_link_state_change(sc->ifp, LINK_STATE_UP); 809 810 if (mvneta_has_switch(self)) { 811 if (bootverbose) 812 device_printf(self, "This device is attached to a switch\n"); 813 child = device_add_child(sc->dev, "mdio", -1); 814 if (child == NULL) { 815 ether_ifdetach(sc->ifp); 816 mvneta_detach(self); 817 return (ENXIO); 818 } 819 bus_generic_attach(sc->dev); 820 bus_generic_attach(child); 821 } 822 823 /* Configure MAC media */ 824 mvneta_update_media(sc, ifm_target); 825 } 826 827 ether_ifattach(ifp, sc->enaddr); 828 829 callout_reset(&sc->tick_ch, 0, mvneta_tick, sc); 830 831 sysctl_mvneta_init(sc); 832 833 return (0); 834 } 835 836 STATIC int 837 mvneta_detach(device_t dev) 838 { 839 struct mvneta_softc *sc; 840 int q; 841 842 sc = device_get_softc(dev); 843 844 if (device_is_attached(dev)) { 845 mvneta_stop(sc); 846 callout_drain(&sc->tick_ch); 847 ether_ifdetach(sc->ifp); 848 } 849 850 for (q = 0; q < MVNETA_RX_QNUM_MAX; q++) 851 mvneta_ring_dealloc_rx_queue(sc, q); 852 for (q = 0; q < MVNETA_TX_QNUM_MAX; q++) 853 mvneta_ring_dealloc_tx_queue(sc, q); 854 855 device_delete_children(dev); 856 857 if (sc->ih_cookie[0] != NULL) 858 bus_teardown_intr(dev, sc->res[1], sc->ih_cookie[0]); 859 860 if (sc->tx_dtag != NULL) 861 bus_dma_tag_destroy(sc->tx_dtag); 862 if (sc->rx_dtag != NULL) 863 bus_dma_tag_destroy(sc->rx_dtag); 864 if (sc->txmbuf_dtag != NULL) 865 bus_dma_tag_destroy(sc->txmbuf_dtag); 866 if (sc->rxbuf_dtag != NULL) 867 bus_dma_tag_destroy(sc->rxbuf_dtag); 868 869 bus_release_resources(dev, res_spec, sc->res); 870 871 if (sc->ifp) 872 if_free(sc->ifp); 873 874 if (mtx_initialized(&sc->mtx)) 875 mtx_destroy(&sc->mtx); 876 877 return (0); 878 } 879 880 /* 881 * MII 882 */ 883 STATIC int 884 mvneta_miibus_readreg(device_t dev, int phy, int reg) 885 { 886 struct mvneta_softc *sc; 887 struct ifnet *ifp; 888 uint32_t smi, val; 889 int i; 890 891 sc = device_get_softc(dev); 892 ifp = sc->ifp; 893 894 mtx_lock(&mii_mutex); 895 896 for (i = 0; i < MVNETA_PHY_TIMEOUT; i++) { 897 if ((MVNETA_READ(sc, MVNETA_SMI) & MVNETA_SMI_BUSY) == 0) 898 break; 899 DELAY(1); 900 } 901 if (i == MVNETA_PHY_TIMEOUT) { 902 if_printf(ifp, "SMI busy timeout\n"); 903 mtx_unlock(&mii_mutex); 904 return (-1); 905 } 906 907 smi = MVNETA_SMI_PHYAD(phy) | 908 MVNETA_SMI_REGAD(reg) | MVNETA_SMI_OPCODE_READ; 909 MVNETA_WRITE(sc, MVNETA_SMI, smi); 910 911 for (i = 0; i < MVNETA_PHY_TIMEOUT; i++) { 912 if ((MVNETA_READ(sc, MVNETA_SMI) & MVNETA_SMI_BUSY) == 0) 913 break; 914 DELAY(1); 915 } 916 917 if (i == MVNETA_PHY_TIMEOUT) { 918 if_printf(ifp, "SMI busy timeout\n"); 919 mtx_unlock(&mii_mutex); 920 return (-1); 921 } 922 for (i = 0; i < MVNETA_PHY_TIMEOUT; i++) { 923 smi = MVNETA_READ(sc, MVNETA_SMI); 924 if (smi & MVNETA_SMI_READVALID) 925 break; 926 DELAY(1); 927 } 928 929 if (i == MVNETA_PHY_TIMEOUT) { 930 if_printf(ifp, "SMI busy timeout\n"); 931 mtx_unlock(&mii_mutex); 932 return (-1); 933 } 934 935 mtx_unlock(&mii_mutex); 936 937 #ifdef MVNETA_KTR 938 CTR3(KTR_SPARE2, "%s i=%d, timeout=%d\n", ifp->if_xname, i, 939 MVNETA_PHY_TIMEOUT); 940 #endif 941 942 val = smi & MVNETA_SMI_DATA_MASK; 943 944 #ifdef MVNETA_KTR 945 CTR4(KTR_SPARE2, "%s phy=%d, reg=%#x, val=%#x\n", ifp->if_xname, phy, 946 reg, val); 947 #endif 948 return (val); 949 } 950 951 STATIC int 952 mvneta_miibus_writereg(device_t dev, int phy, int reg, int val) 953 { 954 struct mvneta_softc *sc; 955 struct ifnet *ifp; 956 uint32_t smi; 957 int i; 958 959 sc = device_get_softc(dev); 960 ifp = sc->ifp; 961 #ifdef MVNETA_KTR 962 CTR4(KTR_SPARE2, "%s phy=%d, reg=%#x, val=%#x\n", ifp->if_xname, 963 phy, reg, val); 964 #endif 965 966 mtx_lock(&mii_mutex); 967 968 for (i = 0; i < MVNETA_PHY_TIMEOUT; i++) { 969 if ((MVNETA_READ(sc, MVNETA_SMI) & MVNETA_SMI_BUSY) == 0) 970 break; 971 DELAY(1); 972 } 973 if (i == MVNETA_PHY_TIMEOUT) { 974 if_printf(ifp, "SMI busy timeout\n"); 975 mtx_unlock(&mii_mutex); 976 return (0); 977 } 978 979 smi = MVNETA_SMI_PHYAD(phy) | MVNETA_SMI_REGAD(reg) | 980 MVNETA_SMI_OPCODE_WRITE | (val & MVNETA_SMI_DATA_MASK); 981 MVNETA_WRITE(sc, MVNETA_SMI, smi); 982 983 for (i = 0; i < MVNETA_PHY_TIMEOUT; i++) { 984 if ((MVNETA_READ(sc, MVNETA_SMI) & MVNETA_SMI_BUSY) == 0) 985 break; 986 DELAY(1); 987 } 988 989 mtx_unlock(&mii_mutex); 990 991 if (i == MVNETA_PHY_TIMEOUT) 992 if_printf(ifp, "phy write timed out\n"); 993 994 return (0); 995 } 996 997 STATIC void 998 mvneta_portup(struct mvneta_softc *sc) 999 { 1000 int q; 1001 1002 for (q = 0; q < MVNETA_RX_QNUM_MAX; q++) { 1003 mvneta_rx_lockq(sc, q); 1004 mvneta_rx_queue_enable(sc->ifp, q); 1005 mvneta_rx_unlockq(sc, q); 1006 } 1007 1008 for (q = 0; q < MVNETA_TX_QNUM_MAX; q++) { 1009 mvneta_tx_lockq(sc, q); 1010 mvneta_tx_queue_enable(sc->ifp, q); 1011 mvneta_tx_unlockq(sc, q); 1012 } 1013 1014 } 1015 1016 STATIC void 1017 mvneta_portdown(struct mvneta_softc *sc) 1018 { 1019 struct mvneta_rx_ring *rx; 1020 struct mvneta_tx_ring *tx; 1021 int q, cnt; 1022 uint32_t reg; 1023 1024 for (q = 0; q < MVNETA_RX_QNUM_MAX; q++) { 1025 rx = MVNETA_RX_RING(sc, q); 1026 mvneta_rx_lockq(sc, q); 1027 rx->queue_status = MVNETA_QUEUE_DISABLED; 1028 mvneta_rx_unlockq(sc, q); 1029 } 1030 1031 for (q = 0; q < MVNETA_TX_QNUM_MAX; q++) { 1032 tx = MVNETA_TX_RING(sc, q); 1033 mvneta_tx_lockq(sc, q); 1034 tx->queue_status = MVNETA_QUEUE_DISABLED; 1035 mvneta_tx_unlockq(sc, q); 1036 } 1037 1038 /* Wait for all Rx activity to terminate. */ 1039 reg = MVNETA_READ(sc, MVNETA_RQC) & MVNETA_RQC_EN_MASK; 1040 reg = MVNETA_RQC_DIS(reg); 1041 MVNETA_WRITE(sc, MVNETA_RQC, reg); 1042 cnt = 0; 1043 do { 1044 if (cnt >= RX_DISABLE_TIMEOUT) { 1045 if_printf(sc->ifp, 1046 "timeout for RX stopped. rqc 0x%x\n", reg); 1047 break; 1048 } 1049 cnt++; 1050 reg = MVNETA_READ(sc, MVNETA_RQC); 1051 } while ((reg & MVNETA_RQC_EN_MASK) != 0); 1052 1053 /* Wait for all Tx activity to terminate. */ 1054 reg = MVNETA_READ(sc, MVNETA_PIE); 1055 reg &= ~MVNETA_PIE_TXPKTINTRPTENB_MASK; 1056 MVNETA_WRITE(sc, MVNETA_PIE, reg); 1057 1058 reg = MVNETA_READ(sc, MVNETA_PRXTXTIM); 1059 reg &= ~MVNETA_PRXTXTI_TBTCQ_MASK; 1060 MVNETA_WRITE(sc, MVNETA_PRXTXTIM, reg); 1061 1062 reg = MVNETA_READ(sc, MVNETA_TQC) & MVNETA_TQC_EN_MASK; 1063 reg = MVNETA_TQC_DIS(reg); 1064 MVNETA_WRITE(sc, MVNETA_TQC, reg); 1065 cnt = 0; 1066 do { 1067 if (cnt >= TX_DISABLE_TIMEOUT) { 1068 if_printf(sc->ifp, 1069 "timeout for TX stopped. tqc 0x%x\n", reg); 1070 break; 1071 } 1072 cnt++; 1073 reg = MVNETA_READ(sc, MVNETA_TQC); 1074 } while ((reg & MVNETA_TQC_EN_MASK) != 0); 1075 1076 /* Wait for all Tx FIFO is empty */ 1077 cnt = 0; 1078 do { 1079 if (cnt >= TX_FIFO_EMPTY_TIMEOUT) { 1080 if_printf(sc->ifp, 1081 "timeout for TX FIFO drained. ps0 0x%x\n", reg); 1082 break; 1083 } 1084 cnt++; 1085 reg = MVNETA_READ(sc, MVNETA_PS0); 1086 } while (((reg & MVNETA_PS0_TXFIFOEMP) == 0) && 1087 ((reg & MVNETA_PS0_TXINPROG) != 0)); 1088 } 1089 1090 /* 1091 * Device Register Initialization 1092 * reset device registers to device driver default value. 1093 * the device is not enabled here. 1094 */ 1095 STATIC int 1096 mvneta_initreg(struct ifnet *ifp) 1097 { 1098 struct mvneta_softc *sc; 1099 int q; 1100 uint32_t reg; 1101 1102 sc = ifp->if_softc; 1103 #ifdef MVNETA_KTR 1104 CTR1(KTR_SPARE2, "%s initializing device register", ifp->if_xname); 1105 #endif 1106 1107 /* Disable Legacy WRR, Disable EJP, Release from reset. */ 1108 MVNETA_WRITE(sc, MVNETA_TQC_1, 0); 1109 /* Enable mbus retry. */ 1110 MVNETA_WRITE(sc, MVNETA_MBUS_CONF, MVNETA_MBUS_RETRY_EN); 1111 1112 /* Init TX/RX Queue Registers */ 1113 for (q = 0; q < MVNETA_RX_QNUM_MAX; q++) { 1114 mvneta_rx_lockq(sc, q); 1115 if (mvneta_rx_queue_init(ifp, q) != 0) { 1116 device_printf(sc->dev, 1117 "initialization failed: cannot initialize queue\n"); 1118 mvneta_rx_unlockq(sc, q); 1119 return (ENOBUFS); 1120 } 1121 mvneta_rx_unlockq(sc, q); 1122 } 1123 for (q = 0; q < MVNETA_TX_QNUM_MAX; q++) { 1124 mvneta_tx_lockq(sc, q); 1125 if (mvneta_tx_queue_init(ifp, q) != 0) { 1126 device_printf(sc->dev, 1127 "initialization failed: cannot initialize queue\n"); 1128 mvneta_tx_unlockq(sc, q); 1129 return (ENOBUFS); 1130 } 1131 mvneta_tx_unlockq(sc, q); 1132 } 1133 1134 /* 1135 * Ethernet Unit Control - disable automatic PHY management by HW. 1136 * In case the port uses SMI-controlled PHY, poll its status with 1137 * mii_tick() and update MAC settings accordingly. 1138 */ 1139 reg = MVNETA_READ(sc, MVNETA_EUC); 1140 reg &= ~MVNETA_EUC_POLLING; 1141 MVNETA_WRITE(sc, MVNETA_EUC, reg); 1142 1143 /* EEE: Low Power Idle */ 1144 reg = MVNETA_LPIC0_LILIMIT(MVNETA_LPI_LI); 1145 reg |= MVNETA_LPIC0_TSLIMIT(MVNETA_LPI_TS); 1146 MVNETA_WRITE(sc, MVNETA_LPIC0, reg); 1147 1148 reg = MVNETA_LPIC1_TWLIMIT(MVNETA_LPI_TW); 1149 MVNETA_WRITE(sc, MVNETA_LPIC1, reg); 1150 1151 reg = MVNETA_LPIC2_MUSTSET; 1152 MVNETA_WRITE(sc, MVNETA_LPIC2, reg); 1153 1154 /* Port MAC Control set 0 */ 1155 reg = MVNETA_PMACC0_MUSTSET; /* must write 0x1 */ 1156 reg &= ~MVNETA_PMACC0_PORTEN; /* port is still disabled */ 1157 reg |= MVNETA_PMACC0_FRAMESIZELIMIT(ifp->if_mtu + MVNETA_ETHER_SIZE); 1158 MVNETA_WRITE(sc, MVNETA_PMACC0, reg); 1159 1160 /* Port MAC Control set 2 */ 1161 reg = MVNETA_READ(sc, MVNETA_PMACC2); 1162 switch (sc->phy_mode) { 1163 case MVNETA_PHY_QSGMII: 1164 reg |= (MVNETA_PMACC2_PCSEN | MVNETA_PMACC2_RGMIIEN); 1165 MVNETA_WRITE(sc, MVNETA_PSERDESCFG, MVNETA_PSERDESCFG_QSGMII); 1166 break; 1167 case MVNETA_PHY_SGMII: 1168 reg |= (MVNETA_PMACC2_PCSEN | MVNETA_PMACC2_RGMIIEN); 1169 MVNETA_WRITE(sc, MVNETA_PSERDESCFG, MVNETA_PSERDESCFG_SGMII); 1170 break; 1171 case MVNETA_PHY_RGMII: 1172 case MVNETA_PHY_RGMII_ID: 1173 reg |= MVNETA_PMACC2_RGMIIEN; 1174 break; 1175 } 1176 reg |= MVNETA_PMACC2_MUSTSET; 1177 reg &= ~MVNETA_PMACC2_PORTMACRESET; 1178 MVNETA_WRITE(sc, MVNETA_PMACC2, reg); 1179 1180 /* Port Configuration Extended: enable Tx CRC generation */ 1181 reg = MVNETA_READ(sc, MVNETA_PXCX); 1182 reg &= ~MVNETA_PXCX_TXCRCDIS; 1183 MVNETA_WRITE(sc, MVNETA_PXCX, reg); 1184 1185 /* clear MIB counter registers(clear by read) */ 1186 mvneta_sc_lock(sc); 1187 mvneta_clear_mib(sc); 1188 mvneta_sc_unlock(sc); 1189 1190 /* Set SDC register except IPGINT bits */ 1191 reg = MVNETA_SDC_RXBSZ_16_64BITWORDS; 1192 reg |= MVNETA_SDC_TXBSZ_16_64BITWORDS; 1193 reg |= MVNETA_SDC_BLMR; 1194 reg |= MVNETA_SDC_BLMT; 1195 MVNETA_WRITE(sc, MVNETA_SDC, reg); 1196 1197 return (0); 1198 } 1199 1200 STATIC void 1201 mvneta_dmamap_cb(void *arg, bus_dma_segment_t * segs, int nseg, int error) 1202 { 1203 1204 if (error != 0) 1205 return; 1206 *(bus_addr_t *)arg = segs->ds_addr; 1207 } 1208 1209 STATIC int 1210 mvneta_ring_alloc_rx_queue(struct mvneta_softc *sc, int q) 1211 { 1212 struct mvneta_rx_ring *rx; 1213 struct mvneta_buf *rxbuf; 1214 bus_dmamap_t dmap; 1215 int i, error; 1216 1217 if (q >= MVNETA_RX_QNUM_MAX) 1218 return (EINVAL); 1219 1220 rx = MVNETA_RX_RING(sc, q); 1221 mtx_init(&rx->ring_mtx, "mvneta_rx", NULL, MTX_DEF); 1222 /* Allocate DMA memory for Rx descriptors */ 1223 error = bus_dmamem_alloc(sc->rx_dtag, 1224 (void**)&(rx->desc), 1225 BUS_DMA_NOWAIT | BUS_DMA_ZERO, 1226 &rx->desc_map); 1227 if (error != 0 || rx->desc == NULL) 1228 goto fail; 1229 error = bus_dmamap_load(sc->rx_dtag, rx->desc_map, 1230 rx->desc, 1231 sizeof(struct mvneta_rx_desc) * MVNETA_RX_RING_CNT, 1232 mvneta_dmamap_cb, &rx->desc_pa, BUS_DMA_NOWAIT); 1233 if (error != 0) 1234 goto fail; 1235 1236 for (i = 0; i < MVNETA_RX_RING_CNT; i++) { 1237 error = bus_dmamap_create(sc->rxbuf_dtag, 0, &dmap); 1238 if (error != 0) { 1239 device_printf(sc->dev, 1240 "Failed to create DMA map for Rx buffer num: %d\n", i); 1241 goto fail; 1242 } 1243 rxbuf = &rx->rxbuf[i]; 1244 rxbuf->dmap = dmap; 1245 rxbuf->m = NULL; 1246 } 1247 1248 return (0); 1249 fail: 1250 mvneta_rx_lockq(sc, q); 1251 mvneta_ring_flush_rx_queue(sc, q); 1252 mvneta_rx_unlockq(sc, q); 1253 mvneta_ring_dealloc_rx_queue(sc, q); 1254 device_printf(sc->dev, "DMA Ring buffer allocation failure.\n"); 1255 return (error); 1256 } 1257 1258 STATIC int 1259 mvneta_ring_alloc_tx_queue(struct mvneta_softc *sc, int q) 1260 { 1261 struct mvneta_tx_ring *tx; 1262 int error; 1263 1264 if (q >= MVNETA_TX_QNUM_MAX) 1265 return (EINVAL); 1266 tx = MVNETA_TX_RING(sc, q); 1267 mtx_init(&tx->ring_mtx, "mvneta_tx", NULL, MTX_DEF); 1268 error = bus_dmamem_alloc(sc->tx_dtag, 1269 (void**)&(tx->desc), 1270 BUS_DMA_NOWAIT | BUS_DMA_ZERO, 1271 &tx->desc_map); 1272 if (error != 0 || tx->desc == NULL) 1273 goto fail; 1274 error = bus_dmamap_load(sc->tx_dtag, tx->desc_map, 1275 tx->desc, 1276 sizeof(struct mvneta_tx_desc) * MVNETA_TX_RING_CNT, 1277 mvneta_dmamap_cb, &tx->desc_pa, BUS_DMA_NOWAIT); 1278 if (error != 0) 1279 goto fail; 1280 1281 #ifdef MVNETA_MULTIQUEUE 1282 tx->br = buf_ring_alloc(MVNETA_BUFRING_SIZE, M_DEVBUF, M_NOWAIT, 1283 &tx->ring_mtx); 1284 if (tx->br == NULL) { 1285 device_printf(sc->dev, 1286 "Could not setup buffer ring for TxQ(%d)\n", q); 1287 error = ENOMEM; 1288 goto fail; 1289 } 1290 #endif 1291 1292 return (0); 1293 fail: 1294 mvneta_tx_lockq(sc, q); 1295 mvneta_ring_flush_tx_queue(sc, q); 1296 mvneta_tx_unlockq(sc, q); 1297 mvneta_ring_dealloc_tx_queue(sc, q); 1298 device_printf(sc->dev, "DMA Ring buffer allocation failure.\n"); 1299 return (error); 1300 } 1301 1302 STATIC void 1303 mvneta_ring_dealloc_tx_queue(struct mvneta_softc *sc, int q) 1304 { 1305 struct mvneta_tx_ring *tx; 1306 struct mvneta_buf *txbuf; 1307 void *kva; 1308 int error; 1309 int i; 1310 1311 if (q >= MVNETA_TX_QNUM_MAX) 1312 return; 1313 tx = MVNETA_TX_RING(sc, q); 1314 1315 if (tx->taskq != NULL) { 1316 /* Remove task */ 1317 while (taskqueue_cancel(tx->taskq, &tx->task, NULL) != 0) 1318 taskqueue_drain(tx->taskq, &tx->task); 1319 } 1320 #ifdef MVNETA_MULTIQUEUE 1321 if (tx->br != NULL) 1322 drbr_free(tx->br, M_DEVBUF); 1323 #endif 1324 1325 if (sc->txmbuf_dtag != NULL) { 1326 for (i = 0; i < MVNETA_TX_RING_CNT; i++) { 1327 txbuf = &tx->txbuf[i]; 1328 if (txbuf->dmap != NULL) { 1329 error = bus_dmamap_destroy(sc->txmbuf_dtag, 1330 txbuf->dmap); 1331 if (error != 0) { 1332 panic("%s: map busy for Tx descriptor (Q%d, %d)", 1333 __func__, q, i); 1334 } 1335 } 1336 } 1337 } 1338 1339 if (tx->desc_pa != 0) 1340 bus_dmamap_unload(sc->tx_dtag, tx->desc_map); 1341 1342 kva = (void *)tx->desc; 1343 if (kva != NULL) 1344 bus_dmamem_free(sc->tx_dtag, tx->desc, tx->desc_map); 1345 1346 if (mtx_name(&tx->ring_mtx) != NULL) 1347 mtx_destroy(&tx->ring_mtx); 1348 1349 memset(tx, 0, sizeof(*tx)); 1350 } 1351 1352 STATIC void 1353 mvneta_ring_dealloc_rx_queue(struct mvneta_softc *sc, int q) 1354 { 1355 struct mvneta_rx_ring *rx; 1356 struct lro_ctrl *lro; 1357 void *kva; 1358 1359 if (q >= MVNETA_RX_QNUM_MAX) 1360 return; 1361 1362 rx = MVNETA_RX_RING(sc, q); 1363 1364 if (rx->desc_pa != 0) 1365 bus_dmamap_unload(sc->rx_dtag, rx->desc_map); 1366 1367 kva = (void *)rx->desc; 1368 if (kva != NULL) 1369 bus_dmamem_free(sc->rx_dtag, rx->desc, rx->desc_map); 1370 1371 lro = &rx->lro; 1372 tcp_lro_free(lro); 1373 1374 if (mtx_name(&rx->ring_mtx) != NULL) 1375 mtx_destroy(&rx->ring_mtx); 1376 1377 memset(rx, 0, sizeof(*rx)); 1378 } 1379 1380 STATIC int 1381 mvneta_ring_init_rx_queue(struct mvneta_softc *sc, int q) 1382 { 1383 struct mvneta_rx_ring *rx; 1384 struct lro_ctrl *lro; 1385 int error; 1386 1387 if (q >= MVNETA_RX_QNUM_MAX) 1388 return (0); 1389 1390 rx = MVNETA_RX_RING(sc, q); 1391 rx->dma = rx->cpu = 0; 1392 rx->queue_th_received = MVNETA_RXTH_COUNT; 1393 rx->queue_th_time = (sc->clk_freq / 1000) / 10; /* 0.1 [ms] */ 1394 1395 /* Initialize LRO */ 1396 rx->lro_enabled = FALSE; 1397 if ((sc->ifp->if_capenable & IFCAP_LRO) != 0) { 1398 lro = &rx->lro; 1399 error = tcp_lro_init(lro); 1400 if (error != 0) 1401 device_printf(sc->dev, "LRO Initialization failed!\n"); 1402 else { 1403 rx->lro_enabled = TRUE; 1404 lro->ifp = sc->ifp; 1405 } 1406 } 1407 1408 return (0); 1409 } 1410 1411 STATIC int 1412 mvneta_ring_init_tx_queue(struct mvneta_softc *sc, int q) 1413 { 1414 struct mvneta_tx_ring *tx; 1415 struct mvneta_buf *txbuf; 1416 int i, error; 1417 1418 if (q >= MVNETA_TX_QNUM_MAX) 1419 return (0); 1420 1421 tx = MVNETA_TX_RING(sc, q); 1422 1423 /* Tx handle */ 1424 for (i = 0; i < MVNETA_TX_RING_CNT; i++) { 1425 txbuf = &tx->txbuf[i]; 1426 txbuf->m = NULL; 1427 /* Tx handle needs DMA map for busdma_load_mbuf() */ 1428 error = bus_dmamap_create(sc->txmbuf_dtag, 0, 1429 &txbuf->dmap); 1430 if (error != 0) { 1431 device_printf(sc->dev, 1432 "can't create dma map (tx ring %d)\n", i); 1433 return (error); 1434 } 1435 } 1436 tx->dma = tx->cpu = 0; 1437 tx->used = 0; 1438 tx->drv_error = 0; 1439 tx->queue_status = MVNETA_QUEUE_DISABLED; 1440 tx->queue_hung = FALSE; 1441 1442 tx->ifp = sc->ifp; 1443 tx->qidx = q; 1444 TASK_INIT(&tx->task, 0, mvneta_tx_task, tx); 1445 tx->taskq = taskqueue_create_fast("mvneta_tx_taskq", M_WAITOK, 1446 taskqueue_thread_enqueue, &tx->taskq); 1447 taskqueue_start_threads(&tx->taskq, 1, PI_NET, "%s: tx_taskq(%d)", 1448 device_get_nameunit(sc->dev), q); 1449 1450 return (0); 1451 } 1452 1453 STATIC void 1454 mvneta_ring_flush_tx_queue(struct mvneta_softc *sc, int q) 1455 { 1456 struct mvneta_tx_ring *tx; 1457 struct mvneta_buf *txbuf; 1458 int i; 1459 1460 tx = MVNETA_TX_RING(sc, q); 1461 KASSERT_TX_MTX(sc, q); 1462 1463 /* Tx handle */ 1464 for (i = 0; i < MVNETA_TX_RING_CNT; i++) { 1465 txbuf = &tx->txbuf[i]; 1466 bus_dmamap_unload(sc->txmbuf_dtag, txbuf->dmap); 1467 if (txbuf->m != NULL) { 1468 m_freem(txbuf->m); 1469 txbuf->m = NULL; 1470 } 1471 } 1472 tx->dma = tx->cpu = 0; 1473 tx->used = 0; 1474 } 1475 1476 STATIC void 1477 mvneta_ring_flush_rx_queue(struct mvneta_softc *sc, int q) 1478 { 1479 struct mvneta_rx_ring *rx; 1480 struct mvneta_buf *rxbuf; 1481 int i; 1482 1483 rx = MVNETA_RX_RING(sc, q); 1484 KASSERT_RX_MTX(sc, q); 1485 1486 /* Rx handle */ 1487 for (i = 0; i < MVNETA_RX_RING_CNT; i++) { 1488 rxbuf = &rx->rxbuf[i]; 1489 mvneta_rx_buf_free(sc, rxbuf); 1490 } 1491 rx->dma = rx->cpu = 0; 1492 } 1493 1494 /* 1495 * Rx/Tx Queue Control 1496 */ 1497 STATIC int 1498 mvneta_rx_queue_init(struct ifnet *ifp, int q) 1499 { 1500 struct mvneta_softc *sc; 1501 struct mvneta_rx_ring *rx; 1502 uint32_t reg; 1503 1504 sc = ifp->if_softc; 1505 KASSERT_RX_MTX(sc, q); 1506 rx = MVNETA_RX_RING(sc, q); 1507 DASSERT(rx->desc_pa != 0); 1508 1509 /* descriptor address */ 1510 MVNETA_WRITE(sc, MVNETA_PRXDQA(q), rx->desc_pa); 1511 1512 /* Rx buffer size and descriptor ring size */ 1513 reg = MVNETA_PRXDQS_BUFFERSIZE(sc->rx_frame_size >> 3); 1514 reg |= MVNETA_PRXDQS_DESCRIPTORSQUEUESIZE(MVNETA_RX_RING_CNT); 1515 MVNETA_WRITE(sc, MVNETA_PRXDQS(q), reg); 1516 #ifdef MVNETA_KTR 1517 CTR3(KTR_SPARE2, "%s PRXDQS(%d): %#x", ifp->if_xname, q, 1518 MVNETA_READ(sc, MVNETA_PRXDQS(q))); 1519 #endif 1520 /* Rx packet offset address */ 1521 reg = MVNETA_PRXC_PACKETOFFSET(MVNETA_PACKET_OFFSET >> 3); 1522 MVNETA_WRITE(sc, MVNETA_PRXC(q), reg); 1523 #ifdef MVNETA_KTR 1524 CTR3(KTR_SPARE2, "%s PRXC(%d): %#x", ifp->if_xname, q, 1525 MVNETA_READ(sc, MVNETA_PRXC(q))); 1526 #endif 1527 1528 /* if DMA is not working, register is not updated */ 1529 DASSERT(MVNETA_READ(sc, MVNETA_PRXDQA(q)) == rx->desc_pa); 1530 return (0); 1531 } 1532 1533 STATIC int 1534 mvneta_tx_queue_init(struct ifnet *ifp, int q) 1535 { 1536 struct mvneta_softc *sc; 1537 struct mvneta_tx_ring *tx; 1538 uint32_t reg; 1539 1540 sc = ifp->if_softc; 1541 KASSERT_TX_MTX(sc, q); 1542 tx = MVNETA_TX_RING(sc, q); 1543 DASSERT(tx->desc_pa != 0); 1544 1545 /* descriptor address */ 1546 MVNETA_WRITE(sc, MVNETA_PTXDQA(q), tx->desc_pa); 1547 1548 /* descriptor ring size */ 1549 reg = MVNETA_PTXDQS_DQS(MVNETA_TX_RING_CNT); 1550 MVNETA_WRITE(sc, MVNETA_PTXDQS(q), reg); 1551 1552 /* if DMA is not working, register is not updated */ 1553 DASSERT(MVNETA_READ(sc, MVNETA_PTXDQA(q)) == tx->desc_pa); 1554 return (0); 1555 } 1556 1557 STATIC int 1558 mvneta_rx_queue_enable(struct ifnet *ifp, int q) 1559 { 1560 struct mvneta_softc *sc; 1561 struct mvneta_rx_ring *rx; 1562 uint32_t reg; 1563 1564 sc = ifp->if_softc; 1565 rx = MVNETA_RX_RING(sc, q); 1566 KASSERT_RX_MTX(sc, q); 1567 1568 /* Set Rx interrupt threshold */ 1569 reg = MVNETA_PRXDQTH_ODT(rx->queue_th_received); 1570 MVNETA_WRITE(sc, MVNETA_PRXDQTH(q), reg); 1571 1572 reg = MVNETA_PRXITTH_RITT(rx->queue_th_time); 1573 MVNETA_WRITE(sc, MVNETA_PRXITTH(q), reg); 1574 1575 /* Unmask RXTX_TH Intr. */ 1576 reg = MVNETA_READ(sc, MVNETA_PRXTXTIM); 1577 reg |= MVNETA_PRXTXTI_RBICTAPQ(q); /* Rx Buffer Interrupt Coalese */ 1578 MVNETA_WRITE(sc, MVNETA_PRXTXTIM, reg); 1579 1580 /* Enable Rx queue */ 1581 reg = MVNETA_READ(sc, MVNETA_RQC) & MVNETA_RQC_EN_MASK; 1582 reg |= MVNETA_RQC_ENQ(q); 1583 MVNETA_WRITE(sc, MVNETA_RQC, reg); 1584 1585 rx->queue_status = MVNETA_QUEUE_WORKING; 1586 return (0); 1587 } 1588 1589 STATIC int 1590 mvneta_tx_queue_enable(struct ifnet *ifp, int q) 1591 { 1592 struct mvneta_softc *sc; 1593 struct mvneta_tx_ring *tx; 1594 1595 sc = ifp->if_softc; 1596 tx = MVNETA_TX_RING(sc, q); 1597 KASSERT_TX_MTX(sc, q); 1598 1599 /* Enable Tx queue */ 1600 MVNETA_WRITE(sc, MVNETA_TQC, MVNETA_TQC_ENQ(q)); 1601 1602 tx->queue_status = MVNETA_QUEUE_IDLE; 1603 tx->queue_hung = FALSE; 1604 return (0); 1605 } 1606 1607 STATIC __inline void 1608 mvneta_rx_lockq(struct mvneta_softc *sc, int q) 1609 { 1610 1611 DASSERT(q >= 0); 1612 DASSERT(q < MVNETA_RX_QNUM_MAX); 1613 mtx_lock(&sc->rx_ring[q].ring_mtx); 1614 } 1615 1616 STATIC __inline void 1617 mvneta_rx_unlockq(struct mvneta_softc *sc, int q) 1618 { 1619 1620 DASSERT(q >= 0); 1621 DASSERT(q < MVNETA_RX_QNUM_MAX); 1622 mtx_unlock(&sc->rx_ring[q].ring_mtx); 1623 } 1624 1625 STATIC __inline int __unused 1626 mvneta_tx_trylockq(struct mvneta_softc *sc, int q) 1627 { 1628 1629 DASSERT(q >= 0); 1630 DASSERT(q < MVNETA_TX_QNUM_MAX); 1631 return (mtx_trylock(&sc->tx_ring[q].ring_mtx)); 1632 } 1633 1634 STATIC __inline void 1635 mvneta_tx_lockq(struct mvneta_softc *sc, int q) 1636 { 1637 1638 DASSERT(q >= 0); 1639 DASSERT(q < MVNETA_TX_QNUM_MAX); 1640 mtx_lock(&sc->tx_ring[q].ring_mtx); 1641 } 1642 1643 STATIC __inline void 1644 mvneta_tx_unlockq(struct mvneta_softc *sc, int q) 1645 { 1646 1647 DASSERT(q >= 0); 1648 DASSERT(q < MVNETA_TX_QNUM_MAX); 1649 mtx_unlock(&sc->tx_ring[q].ring_mtx); 1650 } 1651 1652 /* 1653 * Interrupt Handlers 1654 */ 1655 STATIC void 1656 mvneta_disable_intr(struct mvneta_softc *sc) 1657 { 1658 1659 MVNETA_WRITE(sc, MVNETA_EUIM, 0); 1660 MVNETA_WRITE(sc, MVNETA_EUIC, 0); 1661 MVNETA_WRITE(sc, MVNETA_PRXTXTIM, 0); 1662 MVNETA_WRITE(sc, MVNETA_PRXTXTIC, 0); 1663 MVNETA_WRITE(sc, MVNETA_PRXTXIM, 0); 1664 MVNETA_WRITE(sc, MVNETA_PRXTXIC, 0); 1665 MVNETA_WRITE(sc, MVNETA_PMIM, 0); 1666 MVNETA_WRITE(sc, MVNETA_PMIC, 0); 1667 MVNETA_WRITE(sc, MVNETA_PIE, 0); 1668 } 1669 1670 STATIC void 1671 mvneta_enable_intr(struct mvneta_softc *sc) 1672 { 1673 uint32_t reg; 1674 1675 /* Enable Summary Bit to check all interrupt cause. */ 1676 reg = MVNETA_READ(sc, MVNETA_PRXTXTIM); 1677 reg |= MVNETA_PRXTXTI_PMISCICSUMMARY; 1678 MVNETA_WRITE(sc, MVNETA_PRXTXTIM, reg); 1679 1680 if (!sc->phy_attached || sc->use_inband_status) { 1681 /* Enable Port MISC Intr. (via RXTX_TH_Summary bit) */ 1682 MVNETA_WRITE(sc, MVNETA_PMIM, MVNETA_PMI_PHYSTATUSCHNG | 1683 MVNETA_PMI_LINKCHANGE | MVNETA_PMI_PSCSYNCCHANGE); 1684 } 1685 1686 /* Enable All Queue Interrupt */ 1687 reg = MVNETA_READ(sc, MVNETA_PIE); 1688 reg |= MVNETA_PIE_RXPKTINTRPTENB_MASK; 1689 reg |= MVNETA_PIE_TXPKTINTRPTENB_MASK; 1690 MVNETA_WRITE(sc, MVNETA_PIE, reg); 1691 } 1692 1693 STATIC void 1694 mvneta_rxtxth_intr(void *arg) 1695 { 1696 struct mvneta_softc *sc; 1697 struct ifnet *ifp; 1698 uint32_t ic, queues; 1699 1700 sc = arg; 1701 ifp = sc->ifp; 1702 #ifdef MVNETA_KTR 1703 CTR1(KTR_SPARE2, "%s got RXTX_TH_Intr", ifp->if_xname); 1704 #endif 1705 ic = MVNETA_READ(sc, MVNETA_PRXTXTIC); 1706 if (ic == 0) 1707 return; 1708 MVNETA_WRITE(sc, MVNETA_PRXTXTIC, ~ic); 1709 1710 /* Ack maintance interrupt first */ 1711 if (__predict_false((ic & MVNETA_PRXTXTI_PMISCICSUMMARY) && 1712 (!sc->phy_attached || sc->use_inband_status))) { 1713 mvneta_sc_lock(sc); 1714 mvneta_misc_intr(sc); 1715 mvneta_sc_unlock(sc); 1716 } 1717 if (__predict_false(!(ifp->if_drv_flags & IFF_DRV_RUNNING))) 1718 return; 1719 /* RxTxTH interrupt */ 1720 queues = MVNETA_PRXTXTI_GET_RBICTAPQ(ic); 1721 if (__predict_true(queues)) { 1722 #ifdef MVNETA_KTR 1723 CTR1(KTR_SPARE2, "%s got PRXTXTIC: +RXEOF", ifp->if_xname); 1724 #endif 1725 /* At the moment the driver support only one RX queue. */ 1726 DASSERT(MVNETA_IS_QUEUE_SET(queues, 0)); 1727 mvneta_rx(sc, 0, 0); 1728 } 1729 } 1730 1731 STATIC int 1732 mvneta_misc_intr(struct mvneta_softc *sc) 1733 { 1734 uint32_t ic; 1735 int claimed = 0; 1736 1737 #ifdef MVNETA_KTR 1738 CTR1(KTR_SPARE2, "%s got MISC_INTR", sc->ifp->if_xname); 1739 #endif 1740 KASSERT_SC_MTX(sc); 1741 1742 for (;;) { 1743 ic = MVNETA_READ(sc, MVNETA_PMIC); 1744 ic &= MVNETA_READ(sc, MVNETA_PMIM); 1745 if (ic == 0) 1746 break; 1747 MVNETA_WRITE(sc, MVNETA_PMIC, ~ic); 1748 claimed = 1; 1749 1750 if (ic & (MVNETA_PMI_PHYSTATUSCHNG | 1751 MVNETA_PMI_LINKCHANGE | MVNETA_PMI_PSCSYNCCHANGE)) 1752 mvneta_link_isr(sc); 1753 } 1754 return (claimed); 1755 } 1756 1757 STATIC void 1758 mvneta_tick(void *arg) 1759 { 1760 struct mvneta_softc *sc; 1761 struct mvneta_tx_ring *tx; 1762 struct mvneta_rx_ring *rx; 1763 int q; 1764 uint32_t fc_prev, fc_curr; 1765 1766 sc = arg; 1767 1768 /* 1769 * This is done before mib update to get the right stats 1770 * for this tick. 1771 */ 1772 mvneta_tx_drain(sc); 1773 1774 /* Extract previous flow-control frame received counter. */ 1775 fc_prev = sc->sysctl_mib[MVNETA_MIB_FC_GOOD_IDX].counter; 1776 /* Read mib registers (clear by read). */ 1777 mvneta_update_mib(sc); 1778 /* Extract current flow-control frame received counter. */ 1779 fc_curr = sc->sysctl_mib[MVNETA_MIB_FC_GOOD_IDX].counter; 1780 1781 1782 if (sc->phy_attached && sc->ifp->if_flags & IFF_UP) { 1783 mvneta_sc_lock(sc); 1784 mii_tick(sc->mii); 1785 1786 /* Adjust MAC settings */ 1787 mvneta_adjust_link(sc); 1788 mvneta_sc_unlock(sc); 1789 } 1790 1791 /* 1792 * We were unable to refill the rx queue and left the rx func, leaving 1793 * the ring without mbuf and no way to call the refill func. 1794 */ 1795 for (q = 0; q < MVNETA_RX_QNUM_MAX; q++) { 1796 rx = MVNETA_RX_RING(sc, q); 1797 if (rx->needs_refill == TRUE) { 1798 mvneta_rx_lockq(sc, q); 1799 mvneta_rx_queue_refill(sc, q); 1800 mvneta_rx_unlockq(sc, q); 1801 } 1802 } 1803 1804 /* 1805 * Watchdog: 1806 * - check if queue is mark as hung. 1807 * - ignore hung status if we received some pause frame 1808 * as hardware may have paused packet transmit. 1809 */ 1810 for (q = 0; q < MVNETA_TX_QNUM_MAX; q++) { 1811 /* 1812 * We should take queue lock, but as we only read 1813 * queue status we can do it without lock, we may 1814 * only missdetect queue status for one tick. 1815 */ 1816 tx = MVNETA_TX_RING(sc, q); 1817 1818 if (tx->queue_hung && (fc_curr - fc_prev) == 0) 1819 goto timeout; 1820 } 1821 1822 callout_schedule(&sc->tick_ch, hz); 1823 return; 1824 1825 timeout: 1826 if_printf(sc->ifp, "watchdog timeout\n"); 1827 1828 mvneta_sc_lock(sc); 1829 sc->counter_watchdog++; 1830 sc->counter_watchdog_mib++; 1831 /* Trigger reinitialize sequence. */ 1832 mvneta_stop_locked(sc); 1833 mvneta_init_locked(sc); 1834 mvneta_sc_unlock(sc); 1835 } 1836 1837 STATIC void 1838 mvneta_qflush(struct ifnet *ifp) 1839 { 1840 #ifdef MVNETA_MULTIQUEUE 1841 struct mvneta_softc *sc; 1842 struct mvneta_tx_ring *tx; 1843 struct mbuf *m; 1844 size_t q; 1845 1846 sc = ifp->if_softc; 1847 1848 for (q = 0; q < MVNETA_TX_QNUM_MAX; q++) { 1849 tx = MVNETA_TX_RING(sc, q); 1850 mvneta_tx_lockq(sc, q); 1851 while ((m = buf_ring_dequeue_sc(tx->br)) != NULL) 1852 m_freem(m); 1853 mvneta_tx_unlockq(sc, q); 1854 } 1855 #endif 1856 if_qflush(ifp); 1857 } 1858 1859 STATIC void 1860 mvneta_tx_task(void *arg, int pending) 1861 { 1862 struct mvneta_softc *sc; 1863 struct mvneta_tx_ring *tx; 1864 struct ifnet *ifp; 1865 int error; 1866 1867 tx = arg; 1868 ifp = tx->ifp; 1869 sc = ifp->if_softc; 1870 1871 mvneta_tx_lockq(sc, tx->qidx); 1872 error = mvneta_xmit_locked(sc, tx->qidx); 1873 mvneta_tx_unlockq(sc, tx->qidx); 1874 1875 /* Try again */ 1876 if (__predict_false(error != 0 && error != ENETDOWN)) { 1877 pause("mvneta_tx_task_sleep", 1); 1878 taskqueue_enqueue(tx->taskq, &tx->task); 1879 } 1880 } 1881 1882 STATIC int 1883 mvneta_xmitfast_locked(struct mvneta_softc *sc, int q, struct mbuf **m) 1884 { 1885 struct mvneta_tx_ring *tx; 1886 struct ifnet *ifp; 1887 int error; 1888 1889 KASSERT_TX_MTX(sc, q); 1890 tx = MVNETA_TX_RING(sc, q); 1891 error = 0; 1892 1893 ifp = sc->ifp; 1894 1895 /* Dont enqueue packet if the queue is disabled. */ 1896 if (__predict_false(tx->queue_status == MVNETA_QUEUE_DISABLED)) { 1897 m_freem(*m); 1898 *m = NULL; 1899 return (ENETDOWN); 1900 } 1901 1902 /* Reclaim mbuf if above threshold. */ 1903 if (__predict_true(tx->used > MVNETA_TX_RECLAIM_COUNT)) 1904 mvneta_tx_queue_complete(sc, q); 1905 1906 /* Do not call transmit path if queue is already too full. */ 1907 if (__predict_false(tx->used > 1908 MVNETA_TX_RING_CNT - MVNETA_TX_SEGLIMIT)) 1909 return (ENOBUFS); 1910 1911 error = mvneta_tx_queue(sc, m, q); 1912 if (__predict_false(error != 0)) 1913 return (error); 1914 1915 /* Send a copy of the frame to the BPF listener */ 1916 ETHER_BPF_MTAP(ifp, *m); 1917 1918 /* Set watchdog on */ 1919 tx->watchdog_time = ticks; 1920 tx->queue_status = MVNETA_QUEUE_WORKING; 1921 1922 return (error); 1923 } 1924 1925 #ifdef MVNETA_MULTIQUEUE 1926 STATIC int 1927 mvneta_transmit(struct ifnet *ifp, struct mbuf *m) 1928 { 1929 struct mvneta_softc *sc; 1930 struct mvneta_tx_ring *tx; 1931 int error; 1932 int q; 1933 1934 sc = ifp->if_softc; 1935 1936 /* Use default queue if there is no flow id as thread can migrate. */ 1937 if (__predict_true(M_HASHTYPE_GET(m) != M_HASHTYPE_NONE)) 1938 q = m->m_pkthdr.flowid % MVNETA_TX_QNUM_MAX; 1939 else 1940 q = 0; 1941 1942 tx = MVNETA_TX_RING(sc, q); 1943 1944 /* If buf_ring is full start transmit immediately. */ 1945 if (buf_ring_full(tx->br)) { 1946 mvneta_tx_lockq(sc, q); 1947 mvneta_xmit_locked(sc, q); 1948 mvneta_tx_unlockq(sc, q); 1949 } 1950 1951 /* 1952 * If the buf_ring is empty we will not reorder packets. 1953 * If the lock is available transmit without using buf_ring. 1954 */ 1955 if (buf_ring_empty(tx->br) && mvneta_tx_trylockq(sc, q) != 0) { 1956 error = mvneta_xmitfast_locked(sc, q, &m); 1957 mvneta_tx_unlockq(sc, q); 1958 if (__predict_true(error == 0)) 1959 return (0); 1960 1961 /* Transmit can fail in fastpath. */ 1962 if (__predict_false(m == NULL)) 1963 return (error); 1964 } 1965 1966 /* Enqueue then schedule taskqueue. */ 1967 error = drbr_enqueue(ifp, tx->br, m); 1968 if (__predict_false(error != 0)) 1969 return (error); 1970 1971 taskqueue_enqueue(tx->taskq, &tx->task); 1972 return (0); 1973 } 1974 1975 STATIC int 1976 mvneta_xmit_locked(struct mvneta_softc *sc, int q) 1977 { 1978 struct ifnet *ifp; 1979 struct mvneta_tx_ring *tx; 1980 struct mbuf *m; 1981 int error; 1982 1983 KASSERT_TX_MTX(sc, q); 1984 ifp = sc->ifp; 1985 tx = MVNETA_TX_RING(sc, q); 1986 error = 0; 1987 1988 while ((m = drbr_peek(ifp, tx->br)) != NULL) { 1989 error = mvneta_xmitfast_locked(sc, q, &m); 1990 if (__predict_false(error != 0)) { 1991 if (m != NULL) 1992 drbr_putback(ifp, tx->br, m); 1993 else 1994 drbr_advance(ifp, tx->br); 1995 break; 1996 } 1997 drbr_advance(ifp, tx->br); 1998 } 1999 2000 return (error); 2001 } 2002 #else /* !MVNETA_MULTIQUEUE */ 2003 STATIC void 2004 mvneta_start(struct ifnet *ifp) 2005 { 2006 struct mvneta_softc *sc; 2007 struct mvneta_tx_ring *tx; 2008 int error; 2009 2010 sc = ifp->if_softc; 2011 tx = MVNETA_TX_RING(sc, 0); 2012 2013 mvneta_tx_lockq(sc, 0); 2014 error = mvneta_xmit_locked(sc, 0); 2015 mvneta_tx_unlockq(sc, 0); 2016 /* Handle retransmit in the background taskq. */ 2017 if (__predict_false(error != 0 && error != ENETDOWN)) 2018 taskqueue_enqueue(tx->taskq, &tx->task); 2019 } 2020 2021 STATIC int 2022 mvneta_xmit_locked(struct mvneta_softc *sc, int q) 2023 { 2024 struct ifnet *ifp; 2025 struct mvneta_tx_ring *tx; 2026 struct mbuf *m; 2027 int error; 2028 2029 KASSERT_TX_MTX(sc, q); 2030 ifp = sc->ifp; 2031 tx = MVNETA_TX_RING(sc, 0); 2032 error = 0; 2033 2034 while (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 2035 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 2036 if (m == NULL) 2037 break; 2038 2039 error = mvneta_xmitfast_locked(sc, q, &m); 2040 if (__predict_false(error != 0)) { 2041 if (m != NULL) 2042 IFQ_DRV_PREPEND(&ifp->if_snd, m); 2043 break; 2044 } 2045 } 2046 2047 return (error); 2048 } 2049 #endif 2050 2051 STATIC int 2052 mvneta_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 2053 { 2054 struct mvneta_softc *sc; 2055 struct mvneta_rx_ring *rx; 2056 struct ifreq *ifr; 2057 int error, mask; 2058 uint32_t flags; 2059 int q; 2060 2061 error = 0; 2062 sc = ifp->if_softc; 2063 ifr = (struct ifreq *)data; 2064 switch (cmd) { 2065 case SIOCSIFFLAGS: 2066 mvneta_sc_lock(sc); 2067 if (ifp->if_flags & IFF_UP) { 2068 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 2069 flags = ifp->if_flags ^ sc->mvneta_if_flags; 2070 2071 if (flags != 0) 2072 sc->mvneta_if_flags = ifp->if_flags; 2073 2074 if ((flags & IFF_PROMISC) != 0) 2075 mvneta_filter_setup(sc); 2076 } else { 2077 mvneta_init_locked(sc); 2078 sc->mvneta_if_flags = ifp->if_flags; 2079 if (sc->phy_attached) 2080 mii_mediachg(sc->mii); 2081 mvneta_sc_unlock(sc); 2082 break; 2083 } 2084 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2085 mvneta_stop_locked(sc); 2086 2087 sc->mvneta_if_flags = ifp->if_flags; 2088 mvneta_sc_unlock(sc); 2089 break; 2090 case SIOCSIFCAP: 2091 if (ifp->if_mtu > sc->tx_csum_limit && 2092 ifr->ifr_reqcap & IFCAP_TXCSUM) 2093 ifr->ifr_reqcap &= ~IFCAP_TXCSUM; 2094 mask = ifp->if_capenable ^ ifr->ifr_reqcap; 2095 if (mask & IFCAP_HWCSUM) { 2096 ifp->if_capenable &= ~IFCAP_HWCSUM; 2097 ifp->if_capenable |= IFCAP_HWCSUM & ifr->ifr_reqcap; 2098 if (ifp->if_capenable & IFCAP_TXCSUM) 2099 ifp->if_hwassist = CSUM_IP | CSUM_TCP | 2100 CSUM_UDP; 2101 else 2102 ifp->if_hwassist = 0; 2103 } 2104 if (mask & IFCAP_LRO) { 2105 mvneta_sc_lock(sc); 2106 ifp->if_capenable ^= IFCAP_LRO; 2107 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2108 for (q = 0; q < MVNETA_RX_QNUM_MAX; q++) { 2109 rx = MVNETA_RX_RING(sc, q); 2110 rx->lro_enabled = !rx->lro_enabled; 2111 } 2112 } 2113 mvneta_sc_unlock(sc); 2114 } 2115 VLAN_CAPABILITIES(ifp); 2116 break; 2117 case SIOCSIFMEDIA: 2118 if ((IFM_SUBTYPE(ifr->ifr_media) == IFM_1000_T || 2119 IFM_SUBTYPE(ifr->ifr_media) == IFM_2500_T) && 2120 (ifr->ifr_media & IFM_FDX) == 0) { 2121 device_printf(sc->dev, 2122 "%s half-duplex unsupported\n", 2123 IFM_SUBTYPE(ifr->ifr_media) == IFM_1000_T ? 2124 "1000Base-T" : 2125 "2500Base-T"); 2126 error = EINVAL; 2127 break; 2128 } 2129 case SIOCGIFMEDIA: /* FALLTHROUGH */ 2130 case SIOCGIFXMEDIA: 2131 if (!sc->phy_attached) 2132 error = ifmedia_ioctl(ifp, ifr, &sc->mvneta_ifmedia, 2133 cmd); 2134 else 2135 error = ifmedia_ioctl(ifp, ifr, &sc->mii->mii_media, 2136 cmd); 2137 break; 2138 case SIOCSIFMTU: 2139 if (ifr->ifr_mtu < 68 || ifr->ifr_mtu > MVNETA_MAX_FRAME - 2140 MVNETA_ETHER_SIZE) { 2141 error = EINVAL; 2142 } else { 2143 ifp->if_mtu = ifr->ifr_mtu; 2144 mvneta_sc_lock(sc); 2145 if (ifp->if_mtu + MVNETA_ETHER_SIZE <= MCLBYTES) { 2146 sc->rx_frame_size = MCLBYTES; 2147 } else { 2148 sc->rx_frame_size = MJUM9BYTES; 2149 } 2150 if (ifp->if_mtu > sc->tx_csum_limit) { 2151 ifp->if_capenable &= ~IFCAP_TXCSUM; 2152 ifp->if_hwassist = 0; 2153 } else { 2154 ifp->if_capenable |= IFCAP_TXCSUM; 2155 ifp->if_hwassist = CSUM_IP | CSUM_TCP | 2156 CSUM_UDP; 2157 } 2158 /* 2159 * Reinitialize RX queues. 2160 * We need to update RX descriptor size. 2161 */ 2162 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2163 mvneta_stop_locked(sc); 2164 2165 for (q = 0; q < MVNETA_RX_QNUM_MAX; q++) { 2166 mvneta_rx_lockq(sc, q); 2167 if (mvneta_rx_queue_init(ifp, q) != 0) { 2168 device_printf(sc->dev, 2169 "initialization failed:" 2170 " cannot initialize queue\n"); 2171 mvneta_rx_unlockq(sc, q); 2172 error = ENOBUFS; 2173 break; 2174 } 2175 mvneta_rx_unlockq(sc, q); 2176 } 2177 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2178 mvneta_init_locked(sc); 2179 2180 mvneta_sc_unlock(sc); 2181 } 2182 break; 2183 2184 default: 2185 error = ether_ioctl(ifp, cmd, data); 2186 break; 2187 } 2188 2189 return (error); 2190 } 2191 2192 STATIC void 2193 mvneta_init_locked(void *arg) 2194 { 2195 struct mvneta_softc *sc; 2196 struct ifnet *ifp; 2197 uint32_t reg; 2198 int q, cpu; 2199 2200 sc = arg; 2201 ifp = sc->ifp; 2202 2203 if (!device_is_attached(sc->dev) || 2204 (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2205 return; 2206 2207 mvneta_disable_intr(sc); 2208 callout_stop(&sc->tick_ch); 2209 2210 /* Get the latest mac address */ 2211 bcopy(IF_LLADDR(ifp), sc->enaddr, ETHER_ADDR_LEN); 2212 mvneta_set_mac_address(sc, sc->enaddr); 2213 mvneta_filter_setup(sc); 2214 2215 /* Start DMA Engine */ 2216 MVNETA_WRITE(sc, MVNETA_PRXINIT, 0x00000000); 2217 MVNETA_WRITE(sc, MVNETA_PTXINIT, 0x00000000); 2218 MVNETA_WRITE(sc, MVNETA_PACC, MVNETA_PACC_ACCELERATIONMODE_EDM); 2219 2220 /* Enable port */ 2221 reg = MVNETA_READ(sc, MVNETA_PMACC0); 2222 reg |= MVNETA_PMACC0_PORTEN; 2223 reg &= ~MVNETA_PMACC0_FRAMESIZELIMIT_MASK; 2224 reg |= MVNETA_PMACC0_FRAMESIZELIMIT(ifp->if_mtu + MVNETA_ETHER_SIZE); 2225 MVNETA_WRITE(sc, MVNETA_PMACC0, reg); 2226 2227 /* Allow access to each TXQ/RXQ from both CPU's */ 2228 for (cpu = 0; cpu < mp_ncpus; ++cpu) 2229 MVNETA_WRITE(sc, MVNETA_PCP2Q(cpu), 2230 MVNETA_PCP2Q_TXQEN_MASK | MVNETA_PCP2Q_RXQEN_MASK); 2231 2232 for (q = 0; q < MVNETA_RX_QNUM_MAX; q++) { 2233 mvneta_rx_lockq(sc, q); 2234 mvneta_rx_queue_refill(sc, q); 2235 mvneta_rx_unlockq(sc, q); 2236 } 2237 2238 if (!sc->phy_attached) 2239 mvneta_linkup(sc); 2240 2241 /* Enable interrupt */ 2242 mvneta_enable_intr(sc); 2243 2244 /* Set Counter */ 2245 callout_schedule(&sc->tick_ch, hz); 2246 2247 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2248 } 2249 2250 STATIC void 2251 mvneta_init(void *arg) 2252 { 2253 struct mvneta_softc *sc; 2254 2255 sc = arg; 2256 mvneta_sc_lock(sc); 2257 mvneta_init_locked(sc); 2258 if (sc->phy_attached) 2259 mii_mediachg(sc->mii); 2260 mvneta_sc_unlock(sc); 2261 } 2262 2263 /* ARGSUSED */ 2264 STATIC void 2265 mvneta_stop_locked(struct mvneta_softc *sc) 2266 { 2267 struct ifnet *ifp; 2268 struct mvneta_rx_ring *rx; 2269 struct mvneta_tx_ring *tx; 2270 uint32_t reg; 2271 int q; 2272 2273 ifp = sc->ifp; 2274 if (ifp == NULL || (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 2275 return; 2276 2277 mvneta_disable_intr(sc); 2278 2279 callout_stop(&sc->tick_ch); 2280 2281 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2282 2283 /* Link down */ 2284 if (sc->linkup == TRUE) 2285 mvneta_linkdown(sc); 2286 2287 /* Reset the MAC Port Enable bit */ 2288 reg = MVNETA_READ(sc, MVNETA_PMACC0); 2289 reg &= ~MVNETA_PMACC0_PORTEN; 2290 MVNETA_WRITE(sc, MVNETA_PMACC0, reg); 2291 2292 /* Disable each of queue */ 2293 for (q = 0; q < MVNETA_RX_QNUM_MAX; q++) { 2294 rx = MVNETA_RX_RING(sc, q); 2295 2296 mvneta_rx_lockq(sc, q); 2297 mvneta_ring_flush_rx_queue(sc, q); 2298 mvneta_rx_unlockq(sc, q); 2299 } 2300 2301 /* 2302 * Hold Reset state of DMA Engine 2303 * (must write 0x0 to restart it) 2304 */ 2305 MVNETA_WRITE(sc, MVNETA_PRXINIT, 0x00000001); 2306 MVNETA_WRITE(sc, MVNETA_PTXINIT, 0x00000001); 2307 2308 for (q = 0; q < MVNETA_TX_QNUM_MAX; q++) { 2309 tx = MVNETA_TX_RING(sc, q); 2310 2311 mvneta_tx_lockq(sc, q); 2312 mvneta_ring_flush_tx_queue(sc, q); 2313 mvneta_tx_unlockq(sc, q); 2314 } 2315 } 2316 2317 STATIC void 2318 mvneta_stop(struct mvneta_softc *sc) 2319 { 2320 2321 mvneta_sc_lock(sc); 2322 mvneta_stop_locked(sc); 2323 mvneta_sc_unlock(sc); 2324 } 2325 2326 STATIC int 2327 mvneta_mediachange(struct ifnet *ifp) 2328 { 2329 struct mvneta_softc *sc; 2330 2331 sc = ifp->if_softc; 2332 2333 if (!sc->phy_attached && !sc->use_inband_status) { 2334 /* We shouldn't be here */ 2335 if_printf(ifp, "Cannot change media in fixed-link mode!\n"); 2336 return (0); 2337 } 2338 2339 if (sc->use_inband_status) { 2340 mvneta_update_media(sc, sc->mvneta_ifmedia.ifm_media); 2341 return (0); 2342 } 2343 2344 mvneta_sc_lock(sc); 2345 2346 /* Update PHY */ 2347 mii_mediachg(sc->mii); 2348 2349 mvneta_sc_unlock(sc); 2350 2351 return (0); 2352 } 2353 2354 STATIC void 2355 mvneta_get_media(struct mvneta_softc *sc, struct ifmediareq *ifmr) 2356 { 2357 uint32_t psr; 2358 2359 psr = MVNETA_READ(sc, MVNETA_PSR); 2360 2361 /* Speed */ 2362 if (psr & MVNETA_PSR_GMIISPEED) 2363 ifmr->ifm_active = IFM_ETHER_SUBTYPE_SET(IFM_1000_T); 2364 else if (psr & MVNETA_PSR_MIISPEED) 2365 ifmr->ifm_active = IFM_ETHER_SUBTYPE_SET(IFM_100_TX); 2366 else if (psr & MVNETA_PSR_LINKUP) 2367 ifmr->ifm_active = IFM_ETHER_SUBTYPE_SET(IFM_10_T); 2368 2369 /* Duplex */ 2370 if (psr & MVNETA_PSR_FULLDX) 2371 ifmr->ifm_active |= IFM_FDX; 2372 2373 /* Link */ 2374 ifmr->ifm_status = IFM_AVALID; 2375 if (psr & MVNETA_PSR_LINKUP) 2376 ifmr->ifm_status |= IFM_ACTIVE; 2377 } 2378 2379 STATIC void 2380 mvneta_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 2381 { 2382 struct mvneta_softc *sc; 2383 struct mii_data *mii; 2384 2385 sc = ifp->if_softc; 2386 2387 if (!sc->phy_attached && !sc->use_inband_status) { 2388 ifmr->ifm_status = IFM_AVALID | IFM_ACTIVE; 2389 return; 2390 } 2391 2392 mvneta_sc_lock(sc); 2393 2394 if (sc->use_inband_status) { 2395 mvneta_get_media(sc, ifmr); 2396 mvneta_sc_unlock(sc); 2397 return; 2398 } 2399 2400 mii = sc->mii; 2401 mii_pollstat(mii); 2402 2403 ifmr->ifm_active = mii->mii_media_active; 2404 ifmr->ifm_status = mii->mii_media_status; 2405 2406 mvneta_sc_unlock(sc); 2407 } 2408 2409 /* 2410 * Link State Notify 2411 */ 2412 STATIC void 2413 mvneta_update_autoneg(struct mvneta_softc *sc, int enable) 2414 { 2415 int reg; 2416 2417 if (enable) { 2418 reg = MVNETA_READ(sc, MVNETA_PANC); 2419 reg &= ~(MVNETA_PANC_FORCELINKFAIL | MVNETA_PANC_FORCELINKPASS | 2420 MVNETA_PANC_ANFCEN); 2421 reg |= MVNETA_PANC_ANDUPLEXEN | MVNETA_PANC_ANSPEEDEN | 2422 MVNETA_PANC_INBANDANEN; 2423 MVNETA_WRITE(sc, MVNETA_PANC, reg); 2424 2425 reg = MVNETA_READ(sc, MVNETA_PMACC2); 2426 reg |= MVNETA_PMACC2_INBANDANMODE; 2427 MVNETA_WRITE(sc, MVNETA_PMACC2, reg); 2428 2429 reg = MVNETA_READ(sc, MVNETA_PSOMSCD); 2430 reg |= MVNETA_PSOMSCD_ENABLE; 2431 MVNETA_WRITE(sc, MVNETA_PSOMSCD, reg); 2432 } else { 2433 reg = MVNETA_READ(sc, MVNETA_PANC); 2434 reg &= ~(MVNETA_PANC_FORCELINKFAIL | MVNETA_PANC_FORCELINKPASS | 2435 MVNETA_PANC_ANDUPLEXEN | MVNETA_PANC_ANSPEEDEN | 2436 MVNETA_PANC_INBANDANEN); 2437 MVNETA_WRITE(sc, MVNETA_PANC, reg); 2438 2439 reg = MVNETA_READ(sc, MVNETA_PMACC2); 2440 reg &= ~MVNETA_PMACC2_INBANDANMODE; 2441 MVNETA_WRITE(sc, MVNETA_PMACC2, reg); 2442 2443 reg = MVNETA_READ(sc, MVNETA_PSOMSCD); 2444 reg &= ~MVNETA_PSOMSCD_ENABLE; 2445 MVNETA_WRITE(sc, MVNETA_PSOMSCD, reg); 2446 } 2447 } 2448 2449 STATIC int 2450 mvneta_update_media(struct mvneta_softc *sc, int media) 2451 { 2452 int reg, err; 2453 boolean_t running; 2454 2455 err = 0; 2456 2457 mvneta_sc_lock(sc); 2458 2459 mvneta_linkreset(sc); 2460 2461 running = (sc->ifp->if_drv_flags & IFF_DRV_RUNNING) != 0; 2462 if (running) 2463 mvneta_stop_locked(sc); 2464 2465 sc->autoneg = (IFM_SUBTYPE(media) == IFM_AUTO); 2466 2467 if (!sc->phy_attached || sc->use_inband_status) 2468 mvneta_update_autoneg(sc, IFM_SUBTYPE(media) == IFM_AUTO); 2469 2470 mvneta_update_eee(sc); 2471 mvneta_update_fc(sc); 2472 2473 if (IFM_SUBTYPE(media) != IFM_AUTO) { 2474 reg = MVNETA_READ(sc, MVNETA_PANC); 2475 reg &= ~(MVNETA_PANC_SETGMIISPEED | 2476 MVNETA_PANC_SETMIISPEED | 2477 MVNETA_PANC_SETFULLDX); 2478 if (IFM_SUBTYPE(media) == IFM_1000_T || 2479 IFM_SUBTYPE(media) == IFM_2500_T) { 2480 if ((media & IFM_FDX) == 0) { 2481 device_printf(sc->dev, 2482 "%s half-duplex unsupported\n", 2483 IFM_SUBTYPE(media) == IFM_1000_T ? 2484 "1000Base-T" : 2485 "2500Base-T"); 2486 err = EINVAL; 2487 goto out; 2488 } 2489 reg |= MVNETA_PANC_SETGMIISPEED; 2490 } else if (IFM_SUBTYPE(media) == IFM_100_TX) 2491 reg |= MVNETA_PANC_SETMIISPEED; 2492 2493 if (media & IFM_FDX) 2494 reg |= MVNETA_PANC_SETFULLDX; 2495 2496 MVNETA_WRITE(sc, MVNETA_PANC, reg); 2497 } 2498 out: 2499 if (running) 2500 mvneta_init_locked(sc); 2501 mvneta_sc_unlock(sc); 2502 return (err); 2503 } 2504 2505 STATIC void 2506 mvneta_adjust_link(struct mvneta_softc *sc) 2507 { 2508 boolean_t phy_linkup; 2509 int reg; 2510 2511 /* Update eee/fc */ 2512 mvneta_update_eee(sc); 2513 mvneta_update_fc(sc); 2514 2515 /* Check for link change */ 2516 phy_linkup = (sc->mii->mii_media_status & 2517 (IFM_AVALID | IFM_ACTIVE)) == (IFM_AVALID | IFM_ACTIVE); 2518 2519 if (sc->linkup != phy_linkup) 2520 mvneta_linkupdate(sc, phy_linkup); 2521 2522 /* Don't update media on disabled link */ 2523 if (!phy_linkup) 2524 return; 2525 2526 /* Check for media type change */ 2527 if (sc->mvneta_media != sc->mii->mii_media_active) { 2528 sc->mvneta_media = sc->mii->mii_media_active; 2529 2530 reg = MVNETA_READ(sc, MVNETA_PANC); 2531 reg &= ~(MVNETA_PANC_SETGMIISPEED | 2532 MVNETA_PANC_SETMIISPEED | 2533 MVNETA_PANC_SETFULLDX); 2534 if (IFM_SUBTYPE(sc->mvneta_media) == IFM_1000_T || 2535 IFM_SUBTYPE(sc->mvneta_media) == IFM_2500_T) { 2536 reg |= MVNETA_PANC_SETGMIISPEED; 2537 } else if (IFM_SUBTYPE(sc->mvneta_media) == IFM_100_TX) 2538 reg |= MVNETA_PANC_SETMIISPEED; 2539 2540 if (sc->mvneta_media & IFM_FDX) 2541 reg |= MVNETA_PANC_SETFULLDX; 2542 2543 MVNETA_WRITE(sc, MVNETA_PANC, reg); 2544 } 2545 } 2546 2547 STATIC void 2548 mvneta_link_isr(struct mvneta_softc *sc) 2549 { 2550 int linkup; 2551 2552 KASSERT_SC_MTX(sc); 2553 2554 linkup = MVNETA_IS_LINKUP(sc) ? TRUE : FALSE; 2555 if (sc->linkup == linkup) 2556 return; 2557 2558 if (linkup == TRUE) 2559 mvneta_linkup(sc); 2560 else 2561 mvneta_linkdown(sc); 2562 2563 #ifdef DEBUG 2564 device_printf(sc->dev, 2565 "%s: link %s\n", sc->ifp->if_xname, linkup ? "up" : "down"); 2566 #endif 2567 } 2568 2569 STATIC void 2570 mvneta_linkupdate(struct mvneta_softc *sc, boolean_t linkup) 2571 { 2572 2573 KASSERT_SC_MTX(sc); 2574 2575 if (linkup == TRUE) 2576 mvneta_linkup(sc); 2577 else 2578 mvneta_linkdown(sc); 2579 2580 #ifdef DEBUG 2581 device_printf(sc->dev, 2582 "%s: link %s\n", sc->ifp->if_xname, linkup ? "up" : "down"); 2583 #endif 2584 } 2585 2586 STATIC void 2587 mvneta_update_eee(struct mvneta_softc *sc) 2588 { 2589 uint32_t reg; 2590 2591 KASSERT_SC_MTX(sc); 2592 2593 /* set EEE parameters */ 2594 reg = MVNETA_READ(sc, MVNETA_LPIC1); 2595 if (sc->cf_lpi) 2596 reg |= MVNETA_LPIC1_LPIRE; 2597 else 2598 reg &= ~MVNETA_LPIC1_LPIRE; 2599 MVNETA_WRITE(sc, MVNETA_LPIC1, reg); 2600 } 2601 2602 STATIC void 2603 mvneta_update_fc(struct mvneta_softc *sc) 2604 { 2605 uint32_t reg; 2606 2607 KASSERT_SC_MTX(sc); 2608 2609 reg = MVNETA_READ(sc, MVNETA_PANC); 2610 if (sc->cf_fc) { 2611 /* Flow control negotiation */ 2612 reg |= MVNETA_PANC_PAUSEADV; 2613 reg |= MVNETA_PANC_ANFCEN; 2614 } else { 2615 /* Disable flow control negotiation */ 2616 reg &= ~MVNETA_PANC_PAUSEADV; 2617 reg &= ~MVNETA_PANC_ANFCEN; 2618 } 2619 2620 MVNETA_WRITE(sc, MVNETA_PANC, reg); 2621 } 2622 2623 STATIC void 2624 mvneta_linkup(struct mvneta_softc *sc) 2625 { 2626 uint32_t reg; 2627 2628 KASSERT_SC_MTX(sc); 2629 2630 if (!sc->phy_attached || !sc->use_inband_status) { 2631 reg = MVNETA_READ(sc, MVNETA_PANC); 2632 reg |= MVNETA_PANC_FORCELINKPASS; 2633 reg &= ~MVNETA_PANC_FORCELINKFAIL; 2634 MVNETA_WRITE(sc, MVNETA_PANC, reg); 2635 } 2636 2637 mvneta_qflush(sc->ifp); 2638 mvneta_portup(sc); 2639 sc->linkup = TRUE; 2640 if_link_state_change(sc->ifp, LINK_STATE_UP); 2641 } 2642 2643 STATIC void 2644 mvneta_linkdown(struct mvneta_softc *sc) 2645 { 2646 uint32_t reg; 2647 2648 KASSERT_SC_MTX(sc); 2649 2650 if (!sc->phy_attached || !sc->use_inband_status) { 2651 reg = MVNETA_READ(sc, MVNETA_PANC); 2652 reg &= ~MVNETA_PANC_FORCELINKPASS; 2653 reg |= MVNETA_PANC_FORCELINKFAIL; 2654 MVNETA_WRITE(sc, MVNETA_PANC, reg); 2655 } 2656 2657 mvneta_portdown(sc); 2658 mvneta_qflush(sc->ifp); 2659 sc->linkup = FALSE; 2660 if_link_state_change(sc->ifp, LINK_STATE_DOWN); 2661 } 2662 2663 STATIC void 2664 mvneta_linkreset(struct mvneta_softc *sc) 2665 { 2666 struct mii_softc *mii; 2667 2668 if (sc->phy_attached) { 2669 /* Force reset PHY */ 2670 mii = LIST_FIRST(&sc->mii->mii_phys); 2671 if (mii) 2672 mii_phy_reset(mii); 2673 } 2674 } 2675 2676 /* 2677 * Tx Subroutines 2678 */ 2679 STATIC int 2680 mvneta_tx_queue(struct mvneta_softc *sc, struct mbuf **mbufp, int q) 2681 { 2682 struct ifnet *ifp; 2683 bus_dma_segment_t txsegs[MVNETA_TX_SEGLIMIT]; 2684 struct mbuf *mtmp, *mbuf; 2685 struct mvneta_tx_ring *tx; 2686 struct mvneta_buf *txbuf; 2687 struct mvneta_tx_desc *t; 2688 uint32_t ptxsu; 2689 int start, used, error, i, txnsegs; 2690 2691 mbuf = *mbufp; 2692 tx = MVNETA_TX_RING(sc, q); 2693 DASSERT(tx->used >= 0); 2694 DASSERT(tx->used <= MVNETA_TX_RING_CNT); 2695 t = NULL; 2696 ifp = sc->ifp; 2697 2698 if (__predict_false(mbuf->m_flags & M_VLANTAG)) { 2699 mbuf = ether_vlanencap(mbuf, mbuf->m_pkthdr.ether_vtag); 2700 if (mbuf == NULL) { 2701 tx->drv_error++; 2702 *mbufp = NULL; 2703 return (ENOBUFS); 2704 } 2705 mbuf->m_flags &= ~M_VLANTAG; 2706 *mbufp = mbuf; 2707 } 2708 2709 if (__predict_false(mbuf->m_next != NULL && 2710 (mbuf->m_pkthdr.csum_flags & 2711 (CSUM_IP | CSUM_TCP | CSUM_UDP)) != 0)) { 2712 if (M_WRITABLE(mbuf) == 0) { 2713 mtmp = m_dup(mbuf, M_NOWAIT); 2714 m_freem(mbuf); 2715 if (mtmp == NULL) { 2716 tx->drv_error++; 2717 *mbufp = NULL; 2718 return (ENOBUFS); 2719 } 2720 *mbufp = mbuf = mtmp; 2721 } 2722 } 2723 2724 /* load mbuf using dmamap of 1st descriptor */ 2725 txbuf = &tx->txbuf[tx->cpu]; 2726 error = bus_dmamap_load_mbuf_sg(sc->txmbuf_dtag, 2727 txbuf->dmap, mbuf, txsegs, &txnsegs, 2728 BUS_DMA_NOWAIT); 2729 if (__predict_false(error != 0)) { 2730 #ifdef MVNETA_KTR 2731 CTR3(KTR_SPARE2, "%s:%u bus_dmamap_load_mbuf_sg error=%d", ifp->if_xname, q, error); 2732 #endif 2733 /* This is the only recoverable error (except EFBIG). */ 2734 if (error != ENOMEM) { 2735 tx->drv_error++; 2736 m_freem(mbuf); 2737 *mbufp = NULL; 2738 return (ENOBUFS); 2739 } 2740 return (error); 2741 } 2742 2743 if (__predict_false(txnsegs <= 0 2744 || (txnsegs + tx->used) > MVNETA_TX_RING_CNT)) { 2745 /* we have no enough descriptors or mbuf is broken */ 2746 #ifdef MVNETA_KTR 2747 CTR3(KTR_SPARE2, "%s:%u not enough descriptors txnsegs=%d", 2748 ifp->if_xname, q, txnsegs); 2749 #endif 2750 bus_dmamap_unload(sc->txmbuf_dtag, txbuf->dmap); 2751 return (ENOBUFS); 2752 } 2753 DASSERT(txbuf->m == NULL); 2754 2755 /* remember mbuf using 1st descriptor */ 2756 txbuf->m = mbuf; 2757 bus_dmamap_sync(sc->txmbuf_dtag, txbuf->dmap, 2758 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2759 2760 /* load to tx descriptors */ 2761 start = tx->cpu; 2762 used = 0; 2763 for (i = 0; i < txnsegs; i++) { 2764 t = &tx->desc[tx->cpu]; 2765 t->command = 0; 2766 t->l4ichk = 0; 2767 t->flags = 0; 2768 if (__predict_true(i == 0)) { 2769 /* 1st descriptor */ 2770 t->command |= MVNETA_TX_CMD_W_PACKET_OFFSET(0); 2771 t->command |= MVNETA_TX_CMD_F; 2772 mvneta_tx_set_csumflag(ifp, t, mbuf); 2773 } 2774 t->bufptr_pa = txsegs[i].ds_addr; 2775 t->bytecnt = txsegs[i].ds_len; 2776 tx->cpu = tx_counter_adv(tx->cpu, 1); 2777 2778 tx->used++; 2779 used++; 2780 } 2781 /* t is last descriptor here */ 2782 DASSERT(t != NULL); 2783 t->command |= MVNETA_TX_CMD_L|MVNETA_TX_CMD_PADDING; 2784 2785 bus_dmamap_sync(sc->tx_dtag, tx->desc_map, 2786 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2787 2788 while (__predict_false(used > 255)) { 2789 ptxsu = MVNETA_PTXSU_NOWD(255); 2790 MVNETA_WRITE(sc, MVNETA_PTXSU(q), ptxsu); 2791 used -= 255; 2792 } 2793 if (__predict_true(used > 0)) { 2794 ptxsu = MVNETA_PTXSU_NOWD(used); 2795 MVNETA_WRITE(sc, MVNETA_PTXSU(q), ptxsu); 2796 } 2797 return (0); 2798 } 2799 2800 STATIC void 2801 mvneta_tx_set_csumflag(struct ifnet *ifp, 2802 struct mvneta_tx_desc *t, struct mbuf *m) 2803 { 2804 struct ether_header *eh; 2805 struct ether_vlan_header *evh; 2806 int csum_flags; 2807 uint32_t iphl, ipoff; 2808 struct ip *ip; 2809 2810 iphl = ipoff = 0; 2811 csum_flags = ifp->if_hwassist & m->m_pkthdr.csum_flags; 2812 eh = mtod(m, struct ether_header *); 2813 2814 switch (ntohs(eh->ether_type)) { 2815 case ETHERTYPE_IP: 2816 ipoff = ETHER_HDR_LEN; 2817 break; 2818 case ETHERTYPE_VLAN: 2819 ipoff = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 2820 evh = mtod(m, struct ether_vlan_header *); 2821 if (ntohs(evh->evl_proto) == ETHERTYPE_VLAN) 2822 ipoff += ETHER_VLAN_ENCAP_LEN; 2823 break; 2824 default: 2825 csum_flags = 0; 2826 } 2827 2828 if (__predict_true(csum_flags & (CSUM_IP|CSUM_IP_TCP|CSUM_IP_UDP))) { 2829 ip = (struct ip *)(m->m_data + ipoff); 2830 iphl = ip->ip_hl<<2; 2831 t->command |= MVNETA_TX_CMD_L3_IP4; 2832 } else { 2833 t->command |= MVNETA_TX_CMD_L4_CHECKSUM_NONE; 2834 return; 2835 } 2836 2837 2838 /* L3 */ 2839 if (csum_flags & CSUM_IP) { 2840 t->command |= MVNETA_TX_CMD_IP4_CHECKSUM; 2841 } 2842 2843 /* L4 */ 2844 if (csum_flags & CSUM_IP_TCP) { 2845 t->command |= MVNETA_TX_CMD_L4_CHECKSUM_NOFRAG; 2846 t->command |= MVNETA_TX_CMD_L4_TCP; 2847 } else if (csum_flags & CSUM_IP_UDP) { 2848 t->command |= MVNETA_TX_CMD_L4_CHECKSUM_NOFRAG; 2849 t->command |= MVNETA_TX_CMD_L4_UDP; 2850 } else 2851 t->command |= MVNETA_TX_CMD_L4_CHECKSUM_NONE; 2852 2853 t->l4ichk = 0; 2854 t->command |= MVNETA_TX_CMD_IP_HEADER_LEN(iphl >> 2); 2855 t->command |= MVNETA_TX_CMD_L3_OFFSET(ipoff); 2856 } 2857 2858 STATIC void 2859 mvneta_tx_queue_complete(struct mvneta_softc *sc, int q) 2860 { 2861 struct mvneta_tx_ring *tx; 2862 struct mvneta_buf *txbuf; 2863 struct mvneta_tx_desc *t; 2864 uint32_t ptxs, ptxsu, ndesc; 2865 int i; 2866 2867 KASSERT_TX_MTX(sc, q); 2868 2869 tx = MVNETA_TX_RING(sc, q); 2870 if (__predict_false(tx->queue_status == MVNETA_QUEUE_DISABLED)) 2871 return; 2872 2873 ptxs = MVNETA_READ(sc, MVNETA_PTXS(q)); 2874 ndesc = MVNETA_PTXS_GET_TBC(ptxs); 2875 2876 if (__predict_false(ndesc == 0)) { 2877 if (tx->used == 0) 2878 tx->queue_status = MVNETA_QUEUE_IDLE; 2879 else if (tx->queue_status == MVNETA_QUEUE_WORKING && 2880 ((ticks - tx->watchdog_time) > MVNETA_WATCHDOG)) 2881 tx->queue_hung = TRUE; 2882 return; 2883 } 2884 2885 #ifdef MVNETA_KTR 2886 CTR3(KTR_SPARE2, "%s:%u tx_complete begin ndesc=%u", 2887 sc->ifp->if_xname, q, ndesc); 2888 #endif 2889 2890 bus_dmamap_sync(sc->tx_dtag, tx->desc_map, 2891 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2892 2893 for (i = 0; i < ndesc; i++) { 2894 t = &tx->desc[tx->dma]; 2895 #ifdef MVNETA_KTR 2896 if (t->flags & MVNETA_TX_F_ES) 2897 CTR3(KTR_SPARE2, "%s tx error queue %d desc %d", 2898 sc->ifp->if_xname, q, tx->dma); 2899 #endif 2900 txbuf = &tx->txbuf[tx->dma]; 2901 if (__predict_true(txbuf->m != NULL)) { 2902 DASSERT((t->command & MVNETA_TX_CMD_F) != 0); 2903 bus_dmamap_unload(sc->txmbuf_dtag, txbuf->dmap); 2904 m_freem(txbuf->m); 2905 txbuf->m = NULL; 2906 } 2907 else 2908 DASSERT((t->flags & MVNETA_TX_CMD_F) == 0); 2909 tx->dma = tx_counter_adv(tx->dma, 1); 2910 tx->used--; 2911 } 2912 DASSERT(tx->used >= 0); 2913 DASSERT(tx->used <= MVNETA_TX_RING_CNT); 2914 while (__predict_false(ndesc > 255)) { 2915 ptxsu = MVNETA_PTXSU_NORB(255); 2916 MVNETA_WRITE(sc, MVNETA_PTXSU(q), ptxsu); 2917 ndesc -= 255; 2918 } 2919 if (__predict_true(ndesc > 0)) { 2920 ptxsu = MVNETA_PTXSU_NORB(ndesc); 2921 MVNETA_WRITE(sc, MVNETA_PTXSU(q), ptxsu); 2922 } 2923 #ifdef MVNETA_KTR 2924 CTR5(KTR_SPARE2, "%s:%u tx_complete tx_cpu=%d tx_dma=%d tx_used=%d", 2925 sc->ifp->if_xname, q, tx->cpu, tx->dma, tx->used); 2926 #endif 2927 2928 tx->watchdog_time = ticks; 2929 2930 if (tx->used == 0) 2931 tx->queue_status = MVNETA_QUEUE_IDLE; 2932 } 2933 2934 /* 2935 * Do a final TX complete when TX is idle. 2936 */ 2937 STATIC void 2938 mvneta_tx_drain(struct mvneta_softc *sc) 2939 { 2940 struct mvneta_tx_ring *tx; 2941 int q; 2942 2943 /* 2944 * Handle trailing mbuf on TX queue. 2945 * Check is done lockess to avoid TX path contention. 2946 */ 2947 for (q = 0; q < MVNETA_TX_QNUM_MAX; q++) { 2948 tx = MVNETA_TX_RING(sc, q); 2949 if ((ticks - tx->watchdog_time) > MVNETA_WATCHDOG_TXCOMP && 2950 tx->used > 0) { 2951 mvneta_tx_lockq(sc, q); 2952 mvneta_tx_queue_complete(sc, q); 2953 mvneta_tx_unlockq(sc, q); 2954 } 2955 } 2956 } 2957 2958 /* 2959 * Rx Subroutines 2960 */ 2961 STATIC int 2962 mvneta_rx(struct mvneta_softc *sc, int q, int count) 2963 { 2964 uint32_t prxs, npkt; 2965 int more; 2966 2967 more = 0; 2968 mvneta_rx_lockq(sc, q); 2969 prxs = MVNETA_READ(sc, MVNETA_PRXS(q)); 2970 npkt = MVNETA_PRXS_GET_ODC(prxs); 2971 if (__predict_false(npkt == 0)) 2972 goto out; 2973 2974 if (count > 0 && npkt > count) { 2975 more = 1; 2976 npkt = count; 2977 } 2978 mvneta_rx_queue(sc, q, npkt); 2979 out: 2980 mvneta_rx_unlockq(sc, q); 2981 return more; 2982 } 2983 2984 /* 2985 * Helper routine for updating PRXSU register of a given queue. 2986 * Handles number of processed descriptors bigger than maximum acceptable value. 2987 */ 2988 STATIC __inline void 2989 mvneta_prxsu_update(struct mvneta_softc *sc, int q, int processed) 2990 { 2991 uint32_t prxsu; 2992 2993 while (__predict_false(processed > 255)) { 2994 prxsu = MVNETA_PRXSU_NOOFPROCESSEDDESCRIPTORS(255); 2995 MVNETA_WRITE(sc, MVNETA_PRXSU(q), prxsu); 2996 processed -= 255; 2997 } 2998 prxsu = MVNETA_PRXSU_NOOFPROCESSEDDESCRIPTORS(processed); 2999 MVNETA_WRITE(sc, MVNETA_PRXSU(q), prxsu); 3000 } 3001 3002 static __inline void 3003 mvneta_prefetch(void *p) 3004 { 3005 3006 __builtin_prefetch(p); 3007 } 3008 3009 STATIC void 3010 mvneta_rx_queue(struct mvneta_softc *sc, int q, int npkt) 3011 { 3012 struct ifnet *ifp; 3013 struct mvneta_rx_ring *rx; 3014 struct mvneta_rx_desc *r; 3015 struct mvneta_buf *rxbuf; 3016 struct mbuf *m; 3017 struct lro_ctrl *lro; 3018 struct lro_entry *queued; 3019 void *pktbuf; 3020 int i, pktlen, processed, ndma; 3021 3022 KASSERT_RX_MTX(sc, q); 3023 3024 ifp = sc->ifp; 3025 rx = MVNETA_RX_RING(sc, q); 3026 processed = 0; 3027 3028 if (__predict_false(rx->queue_status == MVNETA_QUEUE_DISABLED)) 3029 return; 3030 3031 bus_dmamap_sync(sc->rx_dtag, rx->desc_map, 3032 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3033 3034 for (i = 0; i < npkt; i++) { 3035 /* Prefetch next desc, rxbuf. */ 3036 ndma = rx_counter_adv(rx->dma, 1); 3037 mvneta_prefetch(&rx->desc[ndma]); 3038 mvneta_prefetch(&rx->rxbuf[ndma]); 3039 3040 /* get descriptor and packet */ 3041 r = &rx->desc[rx->dma]; 3042 rxbuf = &rx->rxbuf[rx->dma]; 3043 m = rxbuf->m; 3044 rxbuf->m = NULL; 3045 DASSERT(m != NULL); 3046 bus_dmamap_sync(sc->rxbuf_dtag, rxbuf->dmap, 3047 BUS_DMASYNC_POSTREAD); 3048 bus_dmamap_unload(sc->rxbuf_dtag, rxbuf->dmap); 3049 /* Prefetch mbuf header. */ 3050 mvneta_prefetch(m); 3051 3052 processed++; 3053 /* Drop desc with error status or not in a single buffer. */ 3054 DASSERT((r->status & (MVNETA_RX_F|MVNETA_RX_L)) == 3055 (MVNETA_RX_F|MVNETA_RX_L)); 3056 if (__predict_false((r->status & MVNETA_RX_ES) || 3057 (r->status & (MVNETA_RX_F|MVNETA_RX_L)) != 3058 (MVNETA_RX_F|MVNETA_RX_L))) 3059 goto rx_error; 3060 3061 /* 3062 * [ OFF | MH | PKT | CRC ] 3063 * bytecnt cover MH, PKT, CRC 3064 */ 3065 pktlen = r->bytecnt - ETHER_CRC_LEN - MVNETA_HWHEADER_SIZE; 3066 pktbuf = (uint8_t *)rx->rxbuf_virt_addr[rx->dma] + MVNETA_PACKET_OFFSET + 3067 MVNETA_HWHEADER_SIZE; 3068 3069 /* Prefetch mbuf data. */ 3070 mvneta_prefetch(pktbuf); 3071 3072 /* Write value to mbuf (avoid read). */ 3073 m->m_data = pktbuf; 3074 m->m_len = m->m_pkthdr.len = pktlen; 3075 m->m_pkthdr.rcvif = ifp; 3076 mvneta_rx_set_csumflag(ifp, r, m); 3077 3078 /* Increase rx_dma before releasing the lock. */ 3079 rx->dma = ndma; 3080 3081 if (__predict_false(rx->lro_enabled && 3082 ((r->status & MVNETA_RX_L3_IP) != 0) && 3083 ((r->status & MVNETA_RX_L4_MASK) == MVNETA_RX_L4_TCP) && 3084 (m->m_pkthdr.csum_flags & 3085 (CSUM_DATA_VALID | CSUM_PSEUDO_HDR)) == 3086 (CSUM_DATA_VALID | CSUM_PSEUDO_HDR))) { 3087 if (rx->lro.lro_cnt != 0) { 3088 if (tcp_lro_rx(&rx->lro, m, 0) == 0) 3089 goto rx_done; 3090 } 3091 } 3092 3093 mvneta_rx_unlockq(sc, q); 3094 (*ifp->if_input)(ifp, m); 3095 mvneta_rx_lockq(sc, q); 3096 /* 3097 * Check whether this queue has been disabled in the 3098 * meantime. If yes, then clear LRO and exit. 3099 */ 3100 if(__predict_false(rx->queue_status == MVNETA_QUEUE_DISABLED)) 3101 goto rx_lro; 3102 rx_done: 3103 /* Refresh receive ring to avoid stall and minimize jitter. */ 3104 if (processed >= MVNETA_RX_REFILL_COUNT) { 3105 mvneta_prxsu_update(sc, q, processed); 3106 mvneta_rx_queue_refill(sc, q); 3107 processed = 0; 3108 } 3109 continue; 3110 rx_error: 3111 m_freem(m); 3112 rx->dma = ndma; 3113 /* Refresh receive ring to avoid stall and minimize jitter. */ 3114 if (processed >= MVNETA_RX_REFILL_COUNT) { 3115 mvneta_prxsu_update(sc, q, processed); 3116 mvneta_rx_queue_refill(sc, q); 3117 processed = 0; 3118 } 3119 } 3120 #ifdef MVNETA_KTR 3121 CTR3(KTR_SPARE2, "%s:%u %u packets received", ifp->if_xname, q, npkt); 3122 #endif 3123 /* DMA status update */ 3124 mvneta_prxsu_update(sc, q, processed); 3125 /* Refill the rest of buffers if there are any to refill */ 3126 mvneta_rx_queue_refill(sc, q); 3127 3128 rx_lro: 3129 /* 3130 * Flush any outstanding LRO work 3131 */ 3132 lro = &rx->lro; 3133 while (__predict_false((queued = LIST_FIRST(&lro->lro_active)) != NULL)) { 3134 LIST_REMOVE(LIST_FIRST((&lro->lro_active)), next); 3135 tcp_lro_flush(lro, queued); 3136 } 3137 } 3138 3139 STATIC void 3140 mvneta_rx_buf_free(struct mvneta_softc *sc, struct mvneta_buf *rxbuf) 3141 { 3142 3143 bus_dmamap_unload(sc->rxbuf_dtag, rxbuf->dmap); 3144 /* This will remove all data at once */ 3145 m_freem(rxbuf->m); 3146 } 3147 3148 STATIC void 3149 mvneta_rx_queue_refill(struct mvneta_softc *sc, int q) 3150 { 3151 struct mvneta_rx_ring *rx; 3152 struct mvneta_rx_desc *r; 3153 struct mvneta_buf *rxbuf; 3154 bus_dma_segment_t segs; 3155 struct mbuf *m; 3156 uint32_t prxs, prxsu, ndesc; 3157 int npkt, refill, nsegs, error; 3158 3159 KASSERT_RX_MTX(sc, q); 3160 3161 rx = MVNETA_RX_RING(sc, q); 3162 prxs = MVNETA_READ(sc, MVNETA_PRXS(q)); 3163 ndesc = MVNETA_PRXS_GET_NODC(prxs) + MVNETA_PRXS_GET_ODC(prxs); 3164 refill = MVNETA_RX_RING_CNT - ndesc; 3165 #ifdef MVNETA_KTR 3166 CTR3(KTR_SPARE2, "%s:%u refill %u packets", sc->ifp->if_xname, q, 3167 refill); 3168 #endif 3169 if (__predict_false(refill <= 0)) 3170 return; 3171 3172 for (npkt = 0; npkt < refill; npkt++) { 3173 rxbuf = &rx->rxbuf[rx->cpu]; 3174 m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, sc->rx_frame_size); 3175 if (__predict_false(m == NULL)) { 3176 error = ENOBUFS; 3177 break; 3178 } 3179 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 3180 3181 error = bus_dmamap_load_mbuf_sg(sc->rxbuf_dtag, rxbuf->dmap, 3182 m, &segs, &nsegs, BUS_DMA_NOWAIT); 3183 if (__predict_false(error != 0 || nsegs != 1)) { 3184 KASSERT(1, ("Failed to load Rx mbuf DMA map")); 3185 m_freem(m); 3186 break; 3187 } 3188 3189 /* Add the packet to the ring */ 3190 rxbuf->m = m; 3191 r = &rx->desc[rx->cpu]; 3192 r->bufptr_pa = segs.ds_addr; 3193 rx->rxbuf_virt_addr[rx->cpu] = m->m_data; 3194 3195 rx->cpu = rx_counter_adv(rx->cpu, 1); 3196 } 3197 if (npkt == 0) { 3198 if (refill == MVNETA_RX_RING_CNT) 3199 rx->needs_refill = TRUE; 3200 return; 3201 } 3202 3203 rx->needs_refill = FALSE; 3204 bus_dmamap_sync(sc->rx_dtag, rx->desc_map, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3205 3206 while (__predict_false(npkt > 255)) { 3207 prxsu = MVNETA_PRXSU_NOOFNEWDESCRIPTORS(255); 3208 MVNETA_WRITE(sc, MVNETA_PRXSU(q), prxsu); 3209 npkt -= 255; 3210 } 3211 if (__predict_true(npkt > 0)) { 3212 prxsu = MVNETA_PRXSU_NOOFNEWDESCRIPTORS(npkt); 3213 MVNETA_WRITE(sc, MVNETA_PRXSU(q), prxsu); 3214 } 3215 } 3216 3217 STATIC __inline void 3218 mvneta_rx_set_csumflag(struct ifnet *ifp, 3219 struct mvneta_rx_desc *r, struct mbuf *m) 3220 { 3221 uint32_t csum_flags; 3222 3223 csum_flags = 0; 3224 if (__predict_false((r->status & 3225 (MVNETA_RX_IP_HEADER_OK|MVNETA_RX_L3_IP)) == 0)) 3226 return; /* not a IP packet */ 3227 3228 /* L3 */ 3229 if (__predict_true((r->status & MVNETA_RX_IP_HEADER_OK) == 3230 MVNETA_RX_IP_HEADER_OK)) 3231 csum_flags |= CSUM_L3_CALC|CSUM_L3_VALID; 3232 3233 if (__predict_true((r->status & (MVNETA_RX_IP_HEADER_OK|MVNETA_RX_L3_IP)) == 3234 (MVNETA_RX_IP_HEADER_OK|MVNETA_RX_L3_IP))) { 3235 /* L4 */ 3236 switch (r->status & MVNETA_RX_L4_MASK) { 3237 case MVNETA_RX_L4_TCP: 3238 case MVNETA_RX_L4_UDP: 3239 csum_flags |= CSUM_L4_CALC; 3240 if (__predict_true((r->status & 3241 MVNETA_RX_L4_CHECKSUM_OK) == MVNETA_RX_L4_CHECKSUM_OK)) { 3242 csum_flags |= CSUM_L4_VALID; 3243 m->m_pkthdr.csum_data = htons(0xffff); 3244 } 3245 break; 3246 case MVNETA_RX_L4_OTH: 3247 default: 3248 break; 3249 } 3250 } 3251 m->m_pkthdr.csum_flags = csum_flags; 3252 } 3253 3254 /* 3255 * MAC address filter 3256 */ 3257 STATIC void 3258 mvneta_filter_setup(struct mvneta_softc *sc) 3259 { 3260 struct ifnet *ifp; 3261 uint32_t dfut[MVNETA_NDFUT], dfsmt[MVNETA_NDFSMT], dfomt[MVNETA_NDFOMT]; 3262 uint32_t pxc; 3263 int i; 3264 3265 KASSERT_SC_MTX(sc); 3266 3267 memset(dfut, 0, sizeof(dfut)); 3268 memset(dfsmt, 0, sizeof(dfsmt)); 3269 memset(dfomt, 0, sizeof(dfomt)); 3270 3271 ifp = sc->ifp; 3272 ifp->if_flags |= IFF_ALLMULTI; 3273 if (ifp->if_flags & (IFF_ALLMULTI|IFF_PROMISC)) { 3274 for (i = 0; i < MVNETA_NDFSMT; i++) { 3275 dfsmt[i] = dfomt[i] = 3276 MVNETA_DF(0, MVNETA_DF_QUEUE(0) | MVNETA_DF_PASS) | 3277 MVNETA_DF(1, MVNETA_DF_QUEUE(0) | MVNETA_DF_PASS) | 3278 MVNETA_DF(2, MVNETA_DF_QUEUE(0) | MVNETA_DF_PASS) | 3279 MVNETA_DF(3, MVNETA_DF_QUEUE(0) | MVNETA_DF_PASS); 3280 } 3281 } 3282 3283 pxc = MVNETA_READ(sc, MVNETA_PXC); 3284 pxc &= ~(MVNETA_PXC_UPM | MVNETA_PXC_RXQ_MASK | MVNETA_PXC_RXQARP_MASK | 3285 MVNETA_PXC_TCPQ_MASK | MVNETA_PXC_UDPQ_MASK | MVNETA_PXC_BPDUQ_MASK); 3286 pxc |= MVNETA_PXC_RXQ(MVNETA_RX_QNUM_MAX-1); 3287 pxc |= MVNETA_PXC_RXQARP(MVNETA_RX_QNUM_MAX-1); 3288 pxc |= MVNETA_PXC_TCPQ(MVNETA_RX_QNUM_MAX-1); 3289 pxc |= MVNETA_PXC_UDPQ(MVNETA_RX_QNUM_MAX-1); 3290 pxc |= MVNETA_PXC_BPDUQ(MVNETA_RX_QNUM_MAX-1); 3291 pxc |= MVNETA_PXC_RB | MVNETA_PXC_RBIP | MVNETA_PXC_RBARP; 3292 if (ifp->if_flags & IFF_BROADCAST) { 3293 pxc &= ~(MVNETA_PXC_RB | MVNETA_PXC_RBIP | MVNETA_PXC_RBARP); 3294 } 3295 if (ifp->if_flags & IFF_PROMISC) { 3296 pxc |= MVNETA_PXC_UPM; 3297 } 3298 MVNETA_WRITE(sc, MVNETA_PXC, pxc); 3299 3300 /* Set Destination Address Filter Unicast Table */ 3301 if (ifp->if_flags & IFF_PROMISC) { 3302 /* pass all unicast addresses */ 3303 for (i = 0; i < MVNETA_NDFUT; i++) { 3304 dfut[i] = 3305 MVNETA_DF(0, MVNETA_DF_QUEUE(0) | MVNETA_DF_PASS) | 3306 MVNETA_DF(1, MVNETA_DF_QUEUE(0) | MVNETA_DF_PASS) | 3307 MVNETA_DF(2, MVNETA_DF_QUEUE(0) | MVNETA_DF_PASS) | 3308 MVNETA_DF(3, MVNETA_DF_QUEUE(0) | MVNETA_DF_PASS); 3309 } 3310 } else { 3311 i = sc->enaddr[5] & 0xf; /* last nibble */ 3312 dfut[i>>2] = MVNETA_DF(i&3, MVNETA_DF_QUEUE(0) | MVNETA_DF_PASS); 3313 } 3314 MVNETA_WRITE_REGION(sc, MVNETA_DFUT(0), dfut, MVNETA_NDFUT); 3315 3316 /* Set Destination Address Filter Multicast Tables */ 3317 MVNETA_WRITE_REGION(sc, MVNETA_DFSMT(0), dfsmt, MVNETA_NDFSMT); 3318 MVNETA_WRITE_REGION(sc, MVNETA_DFOMT(0), dfomt, MVNETA_NDFOMT); 3319 } 3320 3321 /* 3322 * sysctl(9) 3323 */ 3324 STATIC int 3325 sysctl_read_mib(SYSCTL_HANDLER_ARGS) 3326 { 3327 struct mvneta_sysctl_mib *arg; 3328 struct mvneta_softc *sc; 3329 uint64_t val; 3330 3331 arg = (struct mvneta_sysctl_mib *)arg1; 3332 if (arg == NULL) 3333 return (EINVAL); 3334 3335 sc = arg->sc; 3336 if (sc == NULL) 3337 return (EINVAL); 3338 if (arg->index < 0 || arg->index > MVNETA_PORTMIB_NOCOUNTER) 3339 return (EINVAL); 3340 3341 mvneta_sc_lock(sc); 3342 val = arg->counter; 3343 mvneta_sc_unlock(sc); 3344 return sysctl_handle_64(oidp, &val, 0, req); 3345 } 3346 3347 3348 STATIC int 3349 sysctl_clear_mib(SYSCTL_HANDLER_ARGS) 3350 { 3351 struct mvneta_softc *sc; 3352 int err, val; 3353 3354 val = 0; 3355 sc = (struct mvneta_softc *)arg1; 3356 if (sc == NULL) 3357 return (EINVAL); 3358 3359 err = sysctl_handle_int(oidp, &val, 0, req); 3360 if (err != 0) 3361 return (err); 3362 3363 if (val < 0 || val > 1) 3364 return (EINVAL); 3365 3366 if (val == 1) { 3367 mvneta_sc_lock(sc); 3368 mvneta_clear_mib(sc); 3369 mvneta_sc_unlock(sc); 3370 } 3371 3372 return (0); 3373 } 3374 3375 STATIC int 3376 sysctl_set_queue_rxthtime(SYSCTL_HANDLER_ARGS) 3377 { 3378 struct mvneta_sysctl_queue *arg; 3379 struct mvneta_rx_ring *rx; 3380 struct mvneta_softc *sc; 3381 uint32_t reg, time_mvtclk; 3382 int err, time_us; 3383 3384 rx = NULL; 3385 arg = (struct mvneta_sysctl_queue *)arg1; 3386 if (arg == NULL) 3387 return (EINVAL); 3388 if (arg->queue < 0 || arg->queue > MVNETA_RX_RING_CNT) 3389 return (EINVAL); 3390 if (arg->rxtx != MVNETA_SYSCTL_RX) 3391 return (EINVAL); 3392 3393 sc = arg->sc; 3394 if (sc == NULL) 3395 return (EINVAL); 3396 3397 /* read queue length */ 3398 mvneta_sc_lock(sc); 3399 mvneta_rx_lockq(sc, arg->queue); 3400 rx = MVNETA_RX_RING(sc, arg->queue); 3401 time_mvtclk = rx->queue_th_time; 3402 time_us = ((uint64_t)time_mvtclk * 1000ULL * 1000ULL) / sc->clk_freq; 3403 mvneta_rx_unlockq(sc, arg->queue); 3404 mvneta_sc_unlock(sc); 3405 3406 err = sysctl_handle_int(oidp, &time_us, 0, req); 3407 if (err != 0) 3408 return (err); 3409 3410 mvneta_sc_lock(sc); 3411 mvneta_rx_lockq(sc, arg->queue); 3412 3413 /* update queue length (0[sec] - 1[sec]) */ 3414 if (time_us < 0 || time_us > (1000 * 1000)) { 3415 mvneta_rx_unlockq(sc, arg->queue); 3416 mvneta_sc_unlock(sc); 3417 return (EINVAL); 3418 } 3419 time_mvtclk = sc->clk_freq * (uint64_t)time_us / (1000ULL * 1000ULL); 3420 rx->queue_th_time = time_mvtclk; 3421 reg = MVNETA_PRXITTH_RITT(rx->queue_th_time); 3422 MVNETA_WRITE(sc, MVNETA_PRXITTH(arg->queue), reg); 3423 mvneta_rx_unlockq(sc, arg->queue); 3424 mvneta_sc_unlock(sc); 3425 3426 return (0); 3427 } 3428 3429 STATIC void 3430 sysctl_mvneta_init(struct mvneta_softc *sc) 3431 { 3432 struct sysctl_ctx_list *ctx; 3433 struct sysctl_oid_list *children; 3434 struct sysctl_oid_list *rxchildren; 3435 struct sysctl_oid_list *qchildren, *mchildren; 3436 struct sysctl_oid *tree; 3437 int i, q; 3438 struct mvneta_sysctl_queue *rxarg; 3439 #define MVNETA_SYSCTL_NAME(num) "queue" # num 3440 static const char *sysctl_queue_names[] = { 3441 MVNETA_SYSCTL_NAME(0), MVNETA_SYSCTL_NAME(1), 3442 MVNETA_SYSCTL_NAME(2), MVNETA_SYSCTL_NAME(3), 3443 MVNETA_SYSCTL_NAME(4), MVNETA_SYSCTL_NAME(5), 3444 MVNETA_SYSCTL_NAME(6), MVNETA_SYSCTL_NAME(7), 3445 }; 3446 #undef MVNETA_SYSCTL_NAME 3447 3448 #ifndef NO_SYSCTL_DESCR 3449 #define MVNETA_SYSCTL_DESCR(num) "configuration parameters for queue " # num 3450 static const char *sysctl_queue_descrs[] = { 3451 MVNETA_SYSCTL_DESCR(0), MVNETA_SYSCTL_DESCR(1), 3452 MVNETA_SYSCTL_DESCR(2), MVNETA_SYSCTL_DESCR(3), 3453 MVNETA_SYSCTL_DESCR(4), MVNETA_SYSCTL_DESCR(5), 3454 MVNETA_SYSCTL_DESCR(6), MVNETA_SYSCTL_DESCR(7), 3455 }; 3456 #undef MVNETA_SYSCTL_DESCR 3457 #endif 3458 3459 3460 ctx = device_get_sysctl_ctx(sc->dev); 3461 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)); 3462 3463 tree = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "rx", 3464 CTLFLAG_RD | CTLFLAG_MPSAFE, 0, "NETA RX"); 3465 rxchildren = SYSCTL_CHILDREN(tree); 3466 tree = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "mib", 3467 CTLFLAG_RD | CTLFLAG_MPSAFE, 0, "NETA MIB"); 3468 mchildren = SYSCTL_CHILDREN(tree); 3469 3470 3471 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "flow_control", 3472 CTLFLAG_RW, &sc->cf_fc, 0, "flow control"); 3473 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "lpi", 3474 CTLFLAG_RW, &sc->cf_lpi, 0, "Low Power Idle"); 3475 3476 /* 3477 * MIB access 3478 */ 3479 /* dev.mvneta.[unit].mib.<mibs> */ 3480 for (i = 0; i < MVNETA_PORTMIB_NOCOUNTER; i++) { 3481 struct mvneta_sysctl_mib *mib_arg = &sc->sysctl_mib[i]; 3482 3483 mib_arg->sc = sc; 3484 mib_arg->index = i; 3485 SYSCTL_ADD_PROC(ctx, mchildren, OID_AUTO, 3486 mvneta_mib_list[i].sysctl_name, 3487 CTLTYPE_U64 | CTLFLAG_RD | CTLFLAG_NEEDGIANT, 3488 (void *)mib_arg, 0, sysctl_read_mib, "I", 3489 mvneta_mib_list[i].desc); 3490 } 3491 SYSCTL_ADD_UQUAD(ctx, mchildren, OID_AUTO, "rx_discard", 3492 CTLFLAG_RD, &sc->counter_pdfc, "Port Rx Discard Frame Counter"); 3493 SYSCTL_ADD_UQUAD(ctx, mchildren, OID_AUTO, "overrun", 3494 CTLFLAG_RD, &sc->counter_pofc, "Port Overrun Frame Counter"); 3495 SYSCTL_ADD_UINT(ctx, mchildren, OID_AUTO, "watchdog", 3496 CTLFLAG_RD, &sc->counter_watchdog, 0, "TX Watchdog Counter"); 3497 3498 SYSCTL_ADD_PROC(ctx, mchildren, OID_AUTO, "reset", 3499 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 3500 (void *)sc, 0, sysctl_clear_mib, "I", "Reset MIB counters"); 3501 3502 for (q = 0; q < MVNETA_RX_QNUM_MAX; q++) { 3503 rxarg = &sc->sysctl_rx_queue[q]; 3504 3505 rxarg->sc = sc; 3506 rxarg->queue = q; 3507 rxarg->rxtx = MVNETA_SYSCTL_RX; 3508 3509 /* hw.mvneta.mvneta[unit].rx.[queue] */ 3510 tree = SYSCTL_ADD_NODE(ctx, rxchildren, OID_AUTO, 3511 sysctl_queue_names[q], CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 3512 sysctl_queue_descrs[q]); 3513 qchildren = SYSCTL_CHILDREN(tree); 3514 3515 /* hw.mvneta.mvneta[unit].rx.[queue].threshold_timer_us */ 3516 SYSCTL_ADD_PROC(ctx, qchildren, OID_AUTO, "threshold_timer_us", 3517 CTLTYPE_UINT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, rxarg, 0, 3518 sysctl_set_queue_rxthtime, "I", 3519 "interrupt coalescing threshold timer [us]"); 3520 } 3521 } 3522 3523 /* 3524 * MIB 3525 */ 3526 STATIC uint64_t 3527 mvneta_read_mib(struct mvneta_softc *sc, int index) 3528 { 3529 struct mvneta_mib_def *mib; 3530 uint64_t val; 3531 3532 mib = &mvneta_mib_list[index]; 3533 val = MVNETA_READ_MIB(sc, mib->regnum); 3534 if (mib->reg64) 3535 val |= (uint64_t)MVNETA_READ_MIB(sc, mib->regnum + 4) << 32; 3536 return (val); 3537 } 3538 3539 STATIC void 3540 mvneta_clear_mib(struct mvneta_softc *sc) 3541 { 3542 int i; 3543 3544 KASSERT_SC_MTX(sc); 3545 3546 for (i = 0; i < nitems(mvneta_mib_list); i++) { 3547 (void)mvneta_read_mib(sc, i); 3548 sc->sysctl_mib[i].counter = 0; 3549 } 3550 MVNETA_READ(sc, MVNETA_PDFC); 3551 sc->counter_pdfc = 0; 3552 MVNETA_READ(sc, MVNETA_POFC); 3553 sc->counter_pofc = 0; 3554 sc->counter_watchdog = 0; 3555 } 3556 3557 STATIC void 3558 mvneta_update_mib(struct mvneta_softc *sc) 3559 { 3560 struct mvneta_tx_ring *tx; 3561 int i; 3562 uint64_t val; 3563 uint32_t reg; 3564 3565 for (i = 0; i < nitems(mvneta_mib_list); i++) { 3566 3567 val = mvneta_read_mib(sc, i); 3568 if (val == 0) 3569 continue; 3570 3571 sc->sysctl_mib[i].counter += val; 3572 switch (mvneta_mib_list[i].regnum) { 3573 case MVNETA_MIB_RX_GOOD_OCT: 3574 if_inc_counter(sc->ifp, IFCOUNTER_IBYTES, val); 3575 break; 3576 case MVNETA_MIB_RX_BAD_FRAME: 3577 if_inc_counter(sc->ifp, IFCOUNTER_IERRORS, val); 3578 break; 3579 case MVNETA_MIB_RX_GOOD_FRAME: 3580 if_inc_counter(sc->ifp, IFCOUNTER_IPACKETS, val); 3581 break; 3582 case MVNETA_MIB_RX_MCAST_FRAME: 3583 if_inc_counter(sc->ifp, IFCOUNTER_IMCASTS, val); 3584 break; 3585 case MVNETA_MIB_TX_GOOD_OCT: 3586 if_inc_counter(sc->ifp, IFCOUNTER_OBYTES, val); 3587 break; 3588 case MVNETA_MIB_TX_GOOD_FRAME: 3589 if_inc_counter(sc->ifp, IFCOUNTER_OPACKETS, val); 3590 break; 3591 case MVNETA_MIB_TX_MCAST_FRAME: 3592 if_inc_counter(sc->ifp, IFCOUNTER_OMCASTS, val); 3593 break; 3594 case MVNETA_MIB_MAC_COL: 3595 if_inc_counter(sc->ifp, IFCOUNTER_COLLISIONS, val); 3596 break; 3597 case MVNETA_MIB_TX_MAC_TRNS_ERR: 3598 case MVNETA_MIB_TX_EXCES_COL: 3599 case MVNETA_MIB_MAC_LATE_COL: 3600 if_inc_counter(sc->ifp, IFCOUNTER_OERRORS, val); 3601 break; 3602 } 3603 } 3604 3605 reg = MVNETA_READ(sc, MVNETA_PDFC); 3606 sc->counter_pdfc += reg; 3607 if_inc_counter(sc->ifp, IFCOUNTER_IQDROPS, reg); 3608 reg = MVNETA_READ(sc, MVNETA_POFC); 3609 sc->counter_pofc += reg; 3610 if_inc_counter(sc->ifp, IFCOUNTER_IQDROPS, reg); 3611 3612 /* TX watchdog. */ 3613 if (sc->counter_watchdog_mib > 0) { 3614 if_inc_counter(sc->ifp, IFCOUNTER_OERRORS, sc->counter_watchdog_mib); 3615 sc->counter_watchdog_mib = 0; 3616 } 3617 /* 3618 * TX driver errors: 3619 * We do not take queue locks to not disrupt TX path. 3620 * We may only miss one drv error which will be fixed at 3621 * next mib update. We may also clear counter when TX path 3622 * is incrementing it but we only do it if counter was not zero 3623 * thus we may only loose one error. 3624 */ 3625 for (i = 0; i < MVNETA_TX_QNUM_MAX; i++) { 3626 tx = MVNETA_TX_RING(sc, i); 3627 3628 if (tx->drv_error > 0) { 3629 if_inc_counter(sc->ifp, IFCOUNTER_OERRORS, tx->drv_error); 3630 tx->drv_error = 0; 3631 } 3632 } 3633 } 3634