1 /* 2 * Copyright (c) 2017 Stormshield. 3 * Copyright (c) 2017 Semihalf. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 24 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include "opt_platform.h" 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/endian.h> 35 #include <sys/mbuf.h> 36 #include <sys/lock.h> 37 #include <sys/mutex.h> 38 #include <sys/kernel.h> 39 #include <sys/module.h> 40 #include <sys/socket.h> 41 #include <sys/sysctl.h> 42 #include <sys/smp.h> 43 #include <sys/taskqueue.h> 44 #ifdef MVNETA_KTR 45 #include <sys/ktr.h> 46 #endif 47 48 #include <net/ethernet.h> 49 #include <net/bpf.h> 50 #include <net/if.h> 51 #include <net/if_arp.h> 52 #include <net/if_dl.h> 53 #include <net/if_media.h> 54 #include <net/if_types.h> 55 #include <net/if_vlan_var.h> 56 57 #include <netinet/in_systm.h> 58 #include <netinet/in.h> 59 #include <netinet/ip.h> 60 #include <netinet/tcp_lro.h> 61 62 #include <sys/sockio.h> 63 #include <sys/bus.h> 64 #include <machine/bus.h> 65 #include <sys/rman.h> 66 #include <machine/resource.h> 67 68 #include <dev/mii/mii.h> 69 #include <dev/mii/miivar.h> 70 71 #include <dev/mdio/mdio.h> 72 73 #include <arm/mv/mvvar.h> 74 75 #if !defined(__aarch64__) 76 #include <arm/mv/mvreg.h> 77 #include <arm/mv/mvwin.h> 78 #endif 79 80 #include "if_mvnetareg.h" 81 #include "if_mvnetavar.h" 82 83 #include "miibus_if.h" 84 #include "mdio_if.h" 85 86 #ifdef MVNETA_DEBUG 87 #define STATIC /* nothing */ 88 #else 89 #define STATIC static 90 #endif 91 92 #define DASSERT(x) KASSERT((x), (#x)) 93 94 #define A3700_TCLK_250MHZ 250000000 95 96 /* Device Register Initialization */ 97 STATIC int mvneta_initreg(struct ifnet *); 98 99 /* Descriptor Ring Control for each of queues */ 100 STATIC int mvneta_ring_alloc_rx_queue(struct mvneta_softc *, int); 101 STATIC int mvneta_ring_alloc_tx_queue(struct mvneta_softc *, int); 102 STATIC void mvneta_ring_dealloc_rx_queue(struct mvneta_softc *, int); 103 STATIC void mvneta_ring_dealloc_tx_queue(struct mvneta_softc *, int); 104 STATIC int mvneta_ring_init_rx_queue(struct mvneta_softc *, int); 105 STATIC int mvneta_ring_init_tx_queue(struct mvneta_softc *, int); 106 STATIC void mvneta_ring_flush_rx_queue(struct mvneta_softc *, int); 107 STATIC void mvneta_ring_flush_tx_queue(struct mvneta_softc *, int); 108 STATIC void mvneta_dmamap_cb(void *, bus_dma_segment_t *, int, int); 109 STATIC int mvneta_dma_create(struct mvneta_softc *); 110 111 /* Rx/Tx Queue Control */ 112 STATIC int mvneta_rx_queue_init(struct ifnet *, int); 113 STATIC int mvneta_tx_queue_init(struct ifnet *, int); 114 STATIC int mvneta_rx_queue_enable(struct ifnet *, int); 115 STATIC int mvneta_tx_queue_enable(struct ifnet *, int); 116 STATIC void mvneta_rx_lockq(struct mvneta_softc *, int); 117 STATIC void mvneta_rx_unlockq(struct mvneta_softc *, int); 118 STATIC void mvneta_tx_lockq(struct mvneta_softc *, int); 119 STATIC void mvneta_tx_unlockq(struct mvneta_softc *, int); 120 121 /* Interrupt Handlers */ 122 STATIC void mvneta_disable_intr(struct mvneta_softc *); 123 STATIC void mvneta_enable_intr(struct mvneta_softc *); 124 STATIC void mvneta_rxtxth_intr(void *); 125 STATIC int mvneta_misc_intr(struct mvneta_softc *); 126 STATIC void mvneta_tick(void *); 127 /* struct ifnet and mii callbacks*/ 128 STATIC int mvneta_xmitfast_locked(struct mvneta_softc *, int, struct mbuf **); 129 STATIC int mvneta_xmit_locked(struct mvneta_softc *, int); 130 #ifdef MVNETA_MULTIQUEUE 131 STATIC int mvneta_transmit(struct ifnet *, struct mbuf *); 132 #else /* !MVNETA_MULTIQUEUE */ 133 STATIC void mvneta_start(struct ifnet *); 134 #endif 135 STATIC void mvneta_qflush(struct ifnet *); 136 STATIC void mvneta_tx_task(void *, int); 137 STATIC int mvneta_ioctl(struct ifnet *, u_long, caddr_t); 138 STATIC void mvneta_init(void *); 139 STATIC void mvneta_init_locked(void *); 140 STATIC void mvneta_stop(struct mvneta_softc *); 141 STATIC void mvneta_stop_locked(struct mvneta_softc *); 142 STATIC int mvneta_mediachange(struct ifnet *); 143 STATIC void mvneta_mediastatus(struct ifnet *, struct ifmediareq *); 144 STATIC void mvneta_portup(struct mvneta_softc *); 145 STATIC void mvneta_portdown(struct mvneta_softc *); 146 147 /* Link State Notify */ 148 STATIC void mvneta_update_autoneg(struct mvneta_softc *, int); 149 STATIC int mvneta_update_media(struct mvneta_softc *, int); 150 STATIC void mvneta_adjust_link(struct mvneta_softc *); 151 STATIC void mvneta_update_eee(struct mvneta_softc *); 152 STATIC void mvneta_update_fc(struct mvneta_softc *); 153 STATIC void mvneta_link_isr(struct mvneta_softc *); 154 STATIC void mvneta_linkupdate(struct mvneta_softc *, boolean_t); 155 STATIC void mvneta_linkup(struct mvneta_softc *); 156 STATIC void mvneta_linkdown(struct mvneta_softc *); 157 STATIC void mvneta_linkreset(struct mvneta_softc *); 158 159 /* Tx Subroutines */ 160 STATIC int mvneta_tx_queue(struct mvneta_softc *, struct mbuf **, int); 161 STATIC void mvneta_tx_set_csumflag(struct ifnet *, 162 struct mvneta_tx_desc *, struct mbuf *); 163 STATIC void mvneta_tx_queue_complete(struct mvneta_softc *, int); 164 STATIC void mvneta_tx_drain(struct mvneta_softc *); 165 166 /* Rx Subroutines */ 167 STATIC int mvneta_rx(struct mvneta_softc *, int, int); 168 STATIC void mvneta_rx_queue(struct mvneta_softc *, int, int); 169 STATIC void mvneta_rx_queue_refill(struct mvneta_softc *, int); 170 STATIC void mvneta_rx_set_csumflag(struct ifnet *, 171 struct mvneta_rx_desc *, struct mbuf *); 172 STATIC void mvneta_rx_buf_free(struct mvneta_softc *, struct mvneta_buf *); 173 174 /* MAC address filter */ 175 STATIC void mvneta_filter_setup(struct mvneta_softc *); 176 177 /* sysctl(9) */ 178 STATIC int sysctl_read_mib(SYSCTL_HANDLER_ARGS); 179 STATIC int sysctl_clear_mib(SYSCTL_HANDLER_ARGS); 180 STATIC int sysctl_set_queue_rxthtime(SYSCTL_HANDLER_ARGS); 181 STATIC void sysctl_mvneta_init(struct mvneta_softc *); 182 183 /* MIB */ 184 STATIC void mvneta_clear_mib(struct mvneta_softc *); 185 STATIC uint64_t mvneta_read_mib(struct mvneta_softc *, int); 186 STATIC void mvneta_update_mib(struct mvneta_softc *); 187 188 /* Switch */ 189 STATIC boolean_t mvneta_find_ethernet_prop_switch(phandle_t, phandle_t); 190 STATIC boolean_t mvneta_has_switch(device_t); 191 192 #define mvneta_sc_lock(sc) mtx_lock(&sc->mtx) 193 #define mvneta_sc_unlock(sc) mtx_unlock(&sc->mtx) 194 195 STATIC struct mtx mii_mutex; 196 STATIC int mii_init = 0; 197 198 /* Device */ 199 STATIC int mvneta_detach(device_t); 200 /* MII */ 201 STATIC int mvneta_miibus_readreg(device_t, int, int); 202 STATIC int mvneta_miibus_writereg(device_t, int, int, int); 203 204 /* Clock */ 205 STATIC uint32_t mvneta_get_clk(void); 206 207 static device_method_t mvneta_methods[] = { 208 /* Device interface */ 209 DEVMETHOD(device_detach, mvneta_detach), 210 /* MII interface */ 211 DEVMETHOD(miibus_readreg, mvneta_miibus_readreg), 212 DEVMETHOD(miibus_writereg, mvneta_miibus_writereg), 213 /* MDIO interface */ 214 DEVMETHOD(mdio_readreg, mvneta_miibus_readreg), 215 DEVMETHOD(mdio_writereg, mvneta_miibus_writereg), 216 217 /* End */ 218 DEVMETHOD_END 219 }; 220 221 DEFINE_CLASS_0(mvneta, mvneta_driver, mvneta_methods, sizeof(struct mvneta_softc)); 222 223 DRIVER_MODULE(miibus, mvneta, miibus_driver, miibus_devclass, 0, 0); 224 DRIVER_MODULE(mdio, mvneta, mdio_driver, mdio_devclass, 0, 0); 225 MODULE_DEPEND(mvneta, mdio, 1, 1, 1); 226 MODULE_DEPEND(mvneta, ether, 1, 1, 1); 227 MODULE_DEPEND(mvneta, miibus, 1, 1, 1); 228 MODULE_DEPEND(mvneta, mvxpbm, 1, 1, 1); 229 230 /* 231 * List of MIB register and names 232 */ 233 enum mvneta_mib_idx 234 { 235 MVNETA_MIB_RX_GOOD_OCT_IDX, 236 MVNETA_MIB_RX_BAD_OCT_IDX, 237 MVNETA_MIB_TX_MAC_TRNS_ERR_IDX, 238 MVNETA_MIB_RX_GOOD_FRAME_IDX, 239 MVNETA_MIB_RX_BAD_FRAME_IDX, 240 MVNETA_MIB_RX_BCAST_FRAME_IDX, 241 MVNETA_MIB_RX_MCAST_FRAME_IDX, 242 MVNETA_MIB_RX_FRAME64_OCT_IDX, 243 MVNETA_MIB_RX_FRAME127_OCT_IDX, 244 MVNETA_MIB_RX_FRAME255_OCT_IDX, 245 MVNETA_MIB_RX_FRAME511_OCT_IDX, 246 MVNETA_MIB_RX_FRAME1023_OCT_IDX, 247 MVNETA_MIB_RX_FRAMEMAX_OCT_IDX, 248 MVNETA_MIB_TX_GOOD_OCT_IDX, 249 MVNETA_MIB_TX_GOOD_FRAME_IDX, 250 MVNETA_MIB_TX_EXCES_COL_IDX, 251 MVNETA_MIB_TX_MCAST_FRAME_IDX, 252 MVNETA_MIB_TX_BCAST_FRAME_IDX, 253 MVNETA_MIB_TX_MAC_CTL_ERR_IDX, 254 MVNETA_MIB_FC_SENT_IDX, 255 MVNETA_MIB_FC_GOOD_IDX, 256 MVNETA_MIB_FC_BAD_IDX, 257 MVNETA_MIB_PKT_UNDERSIZE_IDX, 258 MVNETA_MIB_PKT_FRAGMENT_IDX, 259 MVNETA_MIB_PKT_OVERSIZE_IDX, 260 MVNETA_MIB_PKT_JABBER_IDX, 261 MVNETA_MIB_MAC_RX_ERR_IDX, 262 MVNETA_MIB_MAC_CRC_ERR_IDX, 263 MVNETA_MIB_MAC_COL_IDX, 264 MVNETA_MIB_MAC_LATE_COL_IDX, 265 }; 266 267 STATIC struct mvneta_mib_def { 268 uint32_t regnum; 269 int reg64; 270 const char *sysctl_name; 271 const char *desc; 272 } mvneta_mib_list[] = { 273 [MVNETA_MIB_RX_GOOD_OCT_IDX] = {MVNETA_MIB_RX_GOOD_OCT, 1, 274 "rx_good_oct", "Good Octets Rx"}, 275 [MVNETA_MIB_RX_BAD_OCT_IDX] = {MVNETA_MIB_RX_BAD_OCT, 0, 276 "rx_bad_oct", "Bad Octets Rx"}, 277 [MVNETA_MIB_TX_MAC_TRNS_ERR_IDX] = {MVNETA_MIB_TX_MAC_TRNS_ERR, 0, 278 "tx_mac_err", "MAC Transmit Error"}, 279 [MVNETA_MIB_RX_GOOD_FRAME_IDX] = {MVNETA_MIB_RX_GOOD_FRAME, 0, 280 "rx_good_frame", "Good Frames Rx"}, 281 [MVNETA_MIB_RX_BAD_FRAME_IDX] = {MVNETA_MIB_RX_BAD_FRAME, 0, 282 "rx_bad_frame", "Bad Frames Rx"}, 283 [MVNETA_MIB_RX_BCAST_FRAME_IDX] = {MVNETA_MIB_RX_BCAST_FRAME, 0, 284 "rx_bcast_frame", "Broadcast Frames Rx"}, 285 [MVNETA_MIB_RX_MCAST_FRAME_IDX] = {MVNETA_MIB_RX_MCAST_FRAME, 0, 286 "rx_mcast_frame", "Multicast Frames Rx"}, 287 [MVNETA_MIB_RX_FRAME64_OCT_IDX] = {MVNETA_MIB_RX_FRAME64_OCT, 0, 288 "rx_frame_1_64", "Frame Size 1 - 64"}, 289 [MVNETA_MIB_RX_FRAME127_OCT_IDX] = {MVNETA_MIB_RX_FRAME127_OCT, 0, 290 "rx_frame_65_127", "Frame Size 65 - 127"}, 291 [MVNETA_MIB_RX_FRAME255_OCT_IDX] = {MVNETA_MIB_RX_FRAME255_OCT, 0, 292 "rx_frame_128_255", "Frame Size 128 - 255"}, 293 [MVNETA_MIB_RX_FRAME511_OCT_IDX] = {MVNETA_MIB_RX_FRAME511_OCT, 0, 294 "rx_frame_256_511", "Frame Size 256 - 511"}, 295 [MVNETA_MIB_RX_FRAME1023_OCT_IDX] = {MVNETA_MIB_RX_FRAME1023_OCT, 0, 296 "rx_frame_512_1023", "Frame Size 512 - 1023"}, 297 [MVNETA_MIB_RX_FRAMEMAX_OCT_IDX] = {MVNETA_MIB_RX_FRAMEMAX_OCT, 0, 298 "rx_fame_1024_max", "Frame Size 1024 - Max"}, 299 [MVNETA_MIB_TX_GOOD_OCT_IDX] = {MVNETA_MIB_TX_GOOD_OCT, 1, 300 "tx_good_oct", "Good Octets Tx"}, 301 [MVNETA_MIB_TX_GOOD_FRAME_IDX] = {MVNETA_MIB_TX_GOOD_FRAME, 0, 302 "tx_good_frame", "Good Frames Tx"}, 303 [MVNETA_MIB_TX_EXCES_COL_IDX] = {MVNETA_MIB_TX_EXCES_COL, 0, 304 "tx_exces_collision", "Excessive Collision"}, 305 [MVNETA_MIB_TX_MCAST_FRAME_IDX] = {MVNETA_MIB_TX_MCAST_FRAME, 0, 306 "tx_mcast_frame", "Multicast Frames Tx"}, 307 [MVNETA_MIB_TX_BCAST_FRAME_IDX] = {MVNETA_MIB_TX_BCAST_FRAME, 0, 308 "tx_bcast_frame", "Broadcast Frames Tx"}, 309 [MVNETA_MIB_TX_MAC_CTL_ERR_IDX] = {MVNETA_MIB_TX_MAC_CTL_ERR, 0, 310 "tx_mac_ctl_err", "Unknown MAC Control"}, 311 [MVNETA_MIB_FC_SENT_IDX] = {MVNETA_MIB_FC_SENT, 0, 312 "fc_tx", "Flow Control Tx"}, 313 [MVNETA_MIB_FC_GOOD_IDX] = {MVNETA_MIB_FC_GOOD, 0, 314 "fc_rx_good", "Good Flow Control Rx"}, 315 [MVNETA_MIB_FC_BAD_IDX] = {MVNETA_MIB_FC_BAD, 0, 316 "fc_rx_bad", "Bad Flow Control Rx"}, 317 [MVNETA_MIB_PKT_UNDERSIZE_IDX] = {MVNETA_MIB_PKT_UNDERSIZE, 0, 318 "pkt_undersize", "Undersized Packets Rx"}, 319 [MVNETA_MIB_PKT_FRAGMENT_IDX] = {MVNETA_MIB_PKT_FRAGMENT, 0, 320 "pkt_fragment", "Fragmented Packets Rx"}, 321 [MVNETA_MIB_PKT_OVERSIZE_IDX] = {MVNETA_MIB_PKT_OVERSIZE, 0, 322 "pkt_oversize", "Oversized Packets Rx"}, 323 [MVNETA_MIB_PKT_JABBER_IDX] = {MVNETA_MIB_PKT_JABBER, 0, 324 "pkt_jabber", "Jabber Packets Rx"}, 325 [MVNETA_MIB_MAC_RX_ERR_IDX] = {MVNETA_MIB_MAC_RX_ERR, 0, 326 "mac_rx_err", "MAC Rx Errors"}, 327 [MVNETA_MIB_MAC_CRC_ERR_IDX] = {MVNETA_MIB_MAC_CRC_ERR, 0, 328 "mac_crc_err", "MAC CRC Errors"}, 329 [MVNETA_MIB_MAC_COL_IDX] = {MVNETA_MIB_MAC_COL, 0, 330 "mac_collision", "MAC Collision"}, 331 [MVNETA_MIB_MAC_LATE_COL_IDX] = {MVNETA_MIB_MAC_LATE_COL, 0, 332 "mac_late_collision", "MAC Late Collision"}, 333 }; 334 335 static struct resource_spec res_spec[] = { 336 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 337 { SYS_RES_IRQ, 0, RF_ACTIVE }, 338 { -1, 0} 339 }; 340 341 static struct { 342 driver_intr_t *handler; 343 char * description; 344 } mvneta_intrs[] = { 345 { mvneta_rxtxth_intr, "MVNETA aggregated interrupt" }, 346 }; 347 348 STATIC uint32_t 349 mvneta_get_clk() 350 { 351 #if defined(__aarch64__) 352 return (A3700_TCLK_250MHZ); 353 #else 354 return (get_tclk()); 355 #endif 356 } 357 358 static int 359 mvneta_set_mac_address(struct mvneta_softc *sc, uint8_t *addr) 360 { 361 unsigned int mac_h; 362 unsigned int mac_l; 363 364 mac_l = (addr[4] << 8) | (addr[5]); 365 mac_h = (addr[0] << 24) | (addr[1] << 16) | 366 (addr[2] << 8) | (addr[3] << 0); 367 368 MVNETA_WRITE(sc, MVNETA_MACAL, mac_l); 369 MVNETA_WRITE(sc, MVNETA_MACAH, mac_h); 370 return (0); 371 } 372 373 static int 374 mvneta_get_mac_address(struct mvneta_softc *sc, uint8_t *addr) 375 { 376 uint32_t mac_l, mac_h; 377 378 #ifdef FDT 379 if (mvneta_fdt_mac_address(sc, addr) == 0) 380 return (0); 381 #endif 382 /* 383 * Fall back -- use the currently programmed address. 384 */ 385 mac_l = MVNETA_READ(sc, MVNETA_MACAL); 386 mac_h = MVNETA_READ(sc, MVNETA_MACAH); 387 if (mac_l == 0 && mac_h == 0) { 388 /* 389 * Generate pseudo-random MAC. 390 * Set lower part to random number | unit number. 391 */ 392 mac_l = arc4random() & ~0xff; 393 mac_l |= device_get_unit(sc->dev) & 0xff; 394 mac_h = arc4random(); 395 mac_h &= ~(3 << 24); /* Clear multicast and LAA bits */ 396 if (bootverbose) { 397 device_printf(sc->dev, 398 "Could not acquire MAC address. " 399 "Using randomized one.\n"); 400 } 401 } 402 403 addr[0] = (mac_h & 0xff000000) >> 24; 404 addr[1] = (mac_h & 0x00ff0000) >> 16; 405 addr[2] = (mac_h & 0x0000ff00) >> 8; 406 addr[3] = (mac_h & 0x000000ff); 407 addr[4] = (mac_l & 0x0000ff00) >> 8; 408 addr[5] = (mac_l & 0x000000ff); 409 return (0); 410 } 411 412 STATIC boolean_t 413 mvneta_has_switch(device_t self) 414 { 415 #ifdef FDT 416 return (mvneta_has_switch_fdt(self)); 417 #endif 418 419 return (false); 420 } 421 422 STATIC int 423 mvneta_dma_create(struct mvneta_softc *sc) 424 { 425 size_t maxsize, maxsegsz; 426 size_t q; 427 int error; 428 429 /* 430 * Create Tx DMA 431 */ 432 maxsize = maxsegsz = sizeof(struct mvneta_tx_desc) * MVNETA_TX_RING_CNT; 433 434 error = bus_dma_tag_create( 435 bus_get_dma_tag(sc->dev), /* parent */ 436 16, 0, /* alignment, boundary */ 437 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 438 BUS_SPACE_MAXADDR, /* highaddr */ 439 NULL, NULL, /* filtfunc, filtfuncarg */ 440 maxsize, /* maxsize */ 441 1, /* nsegments */ 442 maxsegsz, /* maxsegsz */ 443 0, /* flags */ 444 NULL, NULL, /* lockfunc, lockfuncarg */ 445 &sc->tx_dtag); /* dmat */ 446 if (error != 0) { 447 device_printf(sc->dev, 448 "Failed to create DMA tag for Tx descriptors.\n"); 449 goto fail; 450 } 451 error = bus_dma_tag_create( 452 bus_get_dma_tag(sc->dev), /* parent */ 453 1, 0, /* alignment, boundary */ 454 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 455 BUS_SPACE_MAXADDR, /* highaddr */ 456 NULL, NULL, /* filtfunc, filtfuncarg */ 457 MVNETA_MAX_FRAME, /* maxsize */ 458 MVNETA_TX_SEGLIMIT, /* nsegments */ 459 MVNETA_MAX_FRAME, /* maxsegsz */ 460 BUS_DMA_ALLOCNOW, /* flags */ 461 NULL, NULL, /* lockfunc, lockfuncarg */ 462 &sc->txmbuf_dtag); 463 if (error != 0) { 464 device_printf(sc->dev, 465 "Failed to create DMA tag for Tx mbufs.\n"); 466 goto fail; 467 } 468 469 for (q = 0; q < MVNETA_TX_QNUM_MAX; q++) { 470 error = mvneta_ring_alloc_tx_queue(sc, q); 471 if (error != 0) { 472 device_printf(sc->dev, 473 "Failed to allocate DMA safe memory for TxQ: %zu\n", q); 474 goto fail; 475 } 476 } 477 478 /* 479 * Create Rx DMA. 480 */ 481 /* Create tag for Rx descripors */ 482 error = bus_dma_tag_create( 483 bus_get_dma_tag(sc->dev), /* parent */ 484 32, 0, /* alignment, boundary */ 485 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 486 BUS_SPACE_MAXADDR, /* highaddr */ 487 NULL, NULL, /* filtfunc, filtfuncarg */ 488 sizeof(struct mvneta_rx_desc) * MVNETA_RX_RING_CNT, /* maxsize */ 489 1, /* nsegments */ 490 sizeof(struct mvneta_rx_desc) * MVNETA_RX_RING_CNT, /* maxsegsz */ 491 0, /* flags */ 492 NULL, NULL, /* lockfunc, lockfuncarg */ 493 &sc->rx_dtag); /* dmat */ 494 if (error != 0) { 495 device_printf(sc->dev, 496 "Failed to create DMA tag for Rx descriptors.\n"); 497 goto fail; 498 } 499 500 /* Create tag for Rx buffers */ 501 error = bus_dma_tag_create( 502 bus_get_dma_tag(sc->dev), /* parent */ 503 32, 0, /* alignment, boundary */ 504 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 505 BUS_SPACE_MAXADDR, /* highaddr */ 506 NULL, NULL, /* filtfunc, filtfuncarg */ 507 MVNETA_MAX_FRAME, 1, /* maxsize, nsegments */ 508 MVNETA_MAX_FRAME, /* maxsegsz */ 509 0, /* flags */ 510 NULL, NULL, /* lockfunc, lockfuncarg */ 511 &sc->rxbuf_dtag); /* dmat */ 512 if (error != 0) { 513 device_printf(sc->dev, 514 "Failed to create DMA tag for Rx buffers.\n"); 515 goto fail; 516 } 517 518 for (q = 0; q < MVNETA_RX_QNUM_MAX; q++) { 519 if (mvneta_ring_alloc_rx_queue(sc, q) != 0) { 520 device_printf(sc->dev, 521 "Failed to allocate DMA safe memory for RxQ: %zu\n", q); 522 goto fail; 523 } 524 } 525 526 return (0); 527 fail: 528 mvneta_detach(sc->dev); 529 530 return (error); 531 } 532 533 /* ARGSUSED */ 534 int 535 mvneta_attach(device_t self) 536 { 537 struct mvneta_softc *sc; 538 struct ifnet *ifp; 539 device_t child; 540 int ifm_target; 541 int q, error; 542 #if !defined(__aarch64__) 543 uint32_t reg; 544 #endif 545 546 sc = device_get_softc(self); 547 sc->dev = self; 548 549 mtx_init(&sc->mtx, "mvneta_sc", NULL, MTX_DEF); 550 551 error = bus_alloc_resources(self, res_spec, sc->res); 552 if (error) { 553 device_printf(self, "could not allocate resources\n"); 554 return (ENXIO); 555 } 556 557 sc->version = MVNETA_READ(sc, MVNETA_PV); 558 device_printf(self, "version is %x\n", sc->version); 559 callout_init(&sc->tick_ch, 0); 560 561 /* 562 * make sure DMA engines are in reset state 563 */ 564 MVNETA_WRITE(sc, MVNETA_PRXINIT, 0x00000001); 565 MVNETA_WRITE(sc, MVNETA_PTXINIT, 0x00000001); 566 567 #if !defined(__aarch64__) 568 /* 569 * Disable port snoop for buffers and descriptors 570 * to avoid L2 caching of both without DRAM copy. 571 * Obtain coherency settings from the first MBUS 572 * window attribute. 573 */ 574 if ((MVNETA_READ(sc, MV_WIN_NETA_BASE(0)) & IO_WIN_COH_ATTR_MASK) == 0) { 575 reg = MVNETA_READ(sc, MVNETA_PSNPCFG); 576 reg &= ~MVNETA_PSNPCFG_DESCSNP_MASK; 577 reg &= ~MVNETA_PSNPCFG_BUFSNP_MASK; 578 MVNETA_WRITE(sc, MVNETA_PSNPCFG, reg); 579 } 580 #endif 581 582 error = bus_setup_intr(self, sc->res[1], 583 INTR_TYPE_NET | INTR_MPSAFE, NULL, mvneta_intrs[0].handler, sc, 584 &sc->ih_cookie[0]); 585 if (error) { 586 device_printf(self, "could not setup %s\n", 587 mvneta_intrs[0].description); 588 mvneta_detach(self); 589 return (error); 590 } 591 592 /* 593 * MAC address 594 */ 595 if (mvneta_get_mac_address(sc, sc->enaddr)) { 596 device_printf(self, "no mac address.\n"); 597 return (ENXIO); 598 } 599 mvneta_set_mac_address(sc, sc->enaddr); 600 601 mvneta_disable_intr(sc); 602 603 /* Allocate network interface */ 604 ifp = sc->ifp = if_alloc(IFT_ETHER); 605 if (ifp == NULL) { 606 device_printf(self, "if_alloc() failed\n"); 607 mvneta_detach(self); 608 return (ENOMEM); 609 } 610 if_initname(ifp, device_get_name(self), device_get_unit(self)); 611 612 /* 613 * We can support 802.1Q VLAN-sized frames and jumbo 614 * Ethernet frames. 615 */ 616 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_JUMBO_MTU; 617 618 ifp->if_softc = sc; 619 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 620 #ifdef MVNETA_MULTIQUEUE 621 ifp->if_transmit = mvneta_transmit; 622 ifp->if_qflush = mvneta_qflush; 623 #else /* !MVNETA_MULTIQUEUE */ 624 ifp->if_start = mvneta_start; 625 ifp->if_snd.ifq_drv_maxlen = MVNETA_TX_RING_CNT - 1; 626 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 627 IFQ_SET_READY(&ifp->if_snd); 628 #endif 629 ifp->if_init = mvneta_init; 630 ifp->if_ioctl = mvneta_ioctl; 631 632 /* 633 * We can do IPv4/TCPv4/UDPv4/TCPv6/UDPv6 checksums in hardware. 634 */ 635 ifp->if_capabilities |= IFCAP_HWCSUM; 636 637 /* 638 * As VLAN hardware tagging is not supported 639 * but is necessary to perform VLAN hardware checksums, 640 * it is done in the driver 641 */ 642 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWCSUM; 643 644 /* 645 * Currently IPv6 HW checksum is broken, so make sure it is disabled. 646 */ 647 ifp->if_capabilities &= ~IFCAP_HWCSUM_IPV6; 648 ifp->if_capenable = ifp->if_capabilities; 649 650 /* 651 * Disabled option(s): 652 * - Support for Large Receive Offload 653 */ 654 ifp->if_capabilities |= IFCAP_LRO; 655 656 ifp->if_hwassist = CSUM_IP | CSUM_TCP | CSUM_UDP; 657 658 sc->rx_frame_size = MCLBYTES; /* ether_ifattach() always sets normal mtu */ 659 660 /* 661 * Device DMA Buffer allocation. 662 * Handles resource deallocation in case of failure. 663 */ 664 error = mvneta_dma_create(sc); 665 if (error != 0) { 666 mvneta_detach(self); 667 return (error); 668 } 669 670 /* Initialize queues */ 671 for (q = 0; q < MVNETA_TX_QNUM_MAX; q++) { 672 error = mvneta_ring_init_tx_queue(sc, q); 673 if (error != 0) { 674 mvneta_detach(self); 675 return (error); 676 } 677 } 678 679 for (q = 0; q < MVNETA_RX_QNUM_MAX; q++) { 680 error = mvneta_ring_init_rx_queue(sc, q); 681 if (error != 0) { 682 mvneta_detach(self); 683 return (error); 684 } 685 } 686 687 /* 688 * Enable DMA engines and Initialize Device Registers. 689 */ 690 MVNETA_WRITE(sc, MVNETA_PRXINIT, 0x00000000); 691 MVNETA_WRITE(sc, MVNETA_PTXINIT, 0x00000000); 692 MVNETA_WRITE(sc, MVNETA_PACC, MVNETA_PACC_ACCELERATIONMODE_EDM); 693 mvneta_sc_lock(sc); 694 mvneta_filter_setup(sc); 695 mvneta_sc_unlock(sc); 696 mvneta_initreg(ifp); 697 698 /* 699 * Now MAC is working, setup MII. 700 */ 701 if (mii_init == 0) { 702 /* 703 * MII bus is shared by all MACs and all PHYs in SoC. 704 * serializing the bus access should be safe. 705 */ 706 mtx_init(&mii_mutex, "mvneta_mii", NULL, MTX_DEF); 707 mii_init = 1; 708 } 709 710 /* Attach PHY(s) */ 711 if ((sc->phy_addr != MII_PHY_ANY) && (!sc->use_inband_status)) { 712 error = mii_attach(self, &sc->miibus, ifp, mvneta_mediachange, 713 mvneta_mediastatus, BMSR_DEFCAPMASK, sc->phy_addr, 714 MII_OFFSET_ANY, 0); 715 if (error != 0) { 716 if (bootverbose) { 717 device_printf(self, 718 "MII attach failed, error: %d\n", error); 719 } 720 ether_ifdetach(sc->ifp); 721 mvneta_detach(self); 722 return (error); 723 } 724 sc->mii = device_get_softc(sc->miibus); 725 sc->phy_attached = 1; 726 727 /* Disable auto-negotiation in MAC - rely on PHY layer */ 728 mvneta_update_autoneg(sc, FALSE); 729 } else if (sc->use_inband_status == TRUE) { 730 /* In-band link status */ 731 ifmedia_init(&sc->mvneta_ifmedia, 0, mvneta_mediachange, 732 mvneta_mediastatus); 733 734 /* Configure media */ 735 ifmedia_add(&sc->mvneta_ifmedia, IFM_ETHER | IFM_1000_T | IFM_FDX, 736 0, NULL); 737 ifmedia_add(&sc->mvneta_ifmedia, IFM_ETHER | IFM_100_TX, 0, NULL); 738 ifmedia_add(&sc->mvneta_ifmedia, IFM_ETHER | IFM_100_TX | IFM_FDX, 739 0, NULL); 740 ifmedia_add(&sc->mvneta_ifmedia, IFM_ETHER | IFM_10_T, 0, NULL); 741 ifmedia_add(&sc->mvneta_ifmedia, IFM_ETHER | IFM_10_T | IFM_FDX, 742 0, NULL); 743 ifmedia_add(&sc->mvneta_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 744 ifmedia_set(&sc->mvneta_ifmedia, IFM_ETHER | IFM_AUTO); 745 746 /* Enable auto-negotiation */ 747 mvneta_update_autoneg(sc, TRUE); 748 749 mvneta_sc_lock(sc); 750 if (MVNETA_IS_LINKUP(sc)) 751 mvneta_linkup(sc); 752 else 753 mvneta_linkdown(sc); 754 mvneta_sc_unlock(sc); 755 756 } else { 757 /* Fixed-link, use predefined values */ 758 mvneta_update_autoneg(sc, FALSE); 759 ifmedia_init(&sc->mvneta_ifmedia, 0, mvneta_mediachange, 760 mvneta_mediastatus); 761 762 ifm_target = IFM_ETHER; 763 switch (sc->phy_speed) { 764 case 2500: 765 if (sc->phy_mode != MVNETA_PHY_SGMII && 766 sc->phy_mode != MVNETA_PHY_QSGMII) { 767 device_printf(self, 768 "2.5G speed can work only in (Q)SGMII mode\n"); 769 ether_ifdetach(sc->ifp); 770 mvneta_detach(self); 771 return (ENXIO); 772 } 773 ifm_target |= IFM_2500_T; 774 break; 775 case 1000: 776 ifm_target |= IFM_1000_T; 777 break; 778 case 100: 779 ifm_target |= IFM_100_TX; 780 break; 781 case 10: 782 ifm_target |= IFM_10_T; 783 break; 784 default: 785 ether_ifdetach(sc->ifp); 786 mvneta_detach(self); 787 return (ENXIO); 788 } 789 790 if (sc->phy_fdx) 791 ifm_target |= IFM_FDX; 792 else 793 ifm_target |= IFM_HDX; 794 795 ifmedia_add(&sc->mvneta_ifmedia, ifm_target, 0, NULL); 796 ifmedia_set(&sc->mvneta_ifmedia, ifm_target); 797 if_link_state_change(sc->ifp, LINK_STATE_UP); 798 799 if (mvneta_has_switch(self)) { 800 if (bootverbose) 801 device_printf(self, "This device is attached to a switch\n"); 802 child = device_add_child(sc->dev, "mdio", -1); 803 if (child == NULL) { 804 ether_ifdetach(sc->ifp); 805 mvneta_detach(self); 806 return (ENXIO); 807 } 808 bus_generic_attach(sc->dev); 809 bus_generic_attach(child); 810 } 811 812 /* Configure MAC media */ 813 mvneta_update_media(sc, ifm_target); 814 } 815 816 ether_ifattach(ifp, sc->enaddr); 817 818 callout_reset(&sc->tick_ch, 0, mvneta_tick, sc); 819 820 sysctl_mvneta_init(sc); 821 822 return (0); 823 } 824 825 STATIC int 826 mvneta_detach(device_t dev) 827 { 828 struct mvneta_softc *sc; 829 struct ifnet *ifp; 830 int q; 831 832 sc = device_get_softc(dev); 833 ifp = sc->ifp; 834 835 if (device_is_attached(dev)) { 836 mvneta_stop(sc); 837 callout_drain(&sc->tick_ch); 838 ether_ifdetach(sc->ifp); 839 } 840 841 for (q = 0; q < MVNETA_RX_QNUM_MAX; q++) 842 mvneta_ring_dealloc_rx_queue(sc, q); 843 for (q = 0; q < MVNETA_TX_QNUM_MAX; q++) 844 mvneta_ring_dealloc_tx_queue(sc, q); 845 846 device_delete_children(dev); 847 848 if (sc->ih_cookie[0] != NULL) 849 bus_teardown_intr(dev, sc->res[1], sc->ih_cookie[0]); 850 851 if (sc->tx_dtag != NULL) 852 bus_dma_tag_destroy(sc->tx_dtag); 853 if (sc->rx_dtag != NULL) 854 bus_dma_tag_destroy(sc->rx_dtag); 855 if (sc->txmbuf_dtag != NULL) 856 bus_dma_tag_destroy(sc->txmbuf_dtag); 857 if (sc->rxbuf_dtag != NULL) 858 bus_dma_tag_destroy(sc->rxbuf_dtag); 859 860 bus_release_resources(dev, res_spec, sc->res); 861 862 if (sc->ifp) 863 if_free(sc->ifp); 864 865 if (mtx_initialized(&sc->mtx)) 866 mtx_destroy(&sc->mtx); 867 868 return (0); 869 } 870 871 /* 872 * MII 873 */ 874 STATIC int 875 mvneta_miibus_readreg(device_t dev, int phy, int reg) 876 { 877 struct mvneta_softc *sc; 878 struct ifnet *ifp; 879 uint32_t smi, val; 880 int i; 881 882 sc = device_get_softc(dev); 883 ifp = sc->ifp; 884 885 mtx_lock(&mii_mutex); 886 887 for (i = 0; i < MVNETA_PHY_TIMEOUT; i++) { 888 if ((MVNETA_READ(sc, MVNETA_SMI) & MVNETA_SMI_BUSY) == 0) 889 break; 890 DELAY(1); 891 } 892 if (i == MVNETA_PHY_TIMEOUT) { 893 if_printf(ifp, "SMI busy timeout\n"); 894 mtx_unlock(&mii_mutex); 895 return (-1); 896 } 897 898 smi = MVNETA_SMI_PHYAD(phy) | 899 MVNETA_SMI_REGAD(reg) | MVNETA_SMI_OPCODE_READ; 900 MVNETA_WRITE(sc, MVNETA_SMI, smi); 901 902 for (i = 0; i < MVNETA_PHY_TIMEOUT; i++) { 903 if ((MVNETA_READ(sc, MVNETA_SMI) & MVNETA_SMI_BUSY) == 0) 904 break; 905 DELAY(1); 906 } 907 908 if (i == MVNETA_PHY_TIMEOUT) { 909 if_printf(ifp, "SMI busy timeout\n"); 910 mtx_unlock(&mii_mutex); 911 return (-1); 912 } 913 for (i = 0; i < MVNETA_PHY_TIMEOUT; i++) { 914 smi = MVNETA_READ(sc, MVNETA_SMI); 915 if (smi & MVNETA_SMI_READVALID) 916 break; 917 DELAY(1); 918 } 919 920 if (i == MVNETA_PHY_TIMEOUT) { 921 if_printf(ifp, "SMI busy timeout\n"); 922 mtx_unlock(&mii_mutex); 923 return (-1); 924 } 925 926 mtx_unlock(&mii_mutex); 927 928 #ifdef MVNETA_KTR 929 CTR3(KTR_SPARE2, "%s i=%d, timeout=%d\n", ifp->if_xname, i, 930 MVNETA_PHY_TIMEOUT); 931 #endif 932 933 val = smi & MVNETA_SMI_DATA_MASK; 934 935 #ifdef MVNETA_KTR 936 CTR4(KTR_SPARE2, "%s phy=%d, reg=%#x, val=%#x\n", ifp->if_xname, phy, 937 reg, val); 938 #endif 939 return (val); 940 } 941 942 STATIC int 943 mvneta_miibus_writereg(device_t dev, int phy, int reg, int val) 944 { 945 struct mvneta_softc *sc; 946 struct ifnet *ifp; 947 uint32_t smi; 948 int i; 949 950 sc = device_get_softc(dev); 951 ifp = sc->ifp; 952 #ifdef MVNETA_KTR 953 CTR4(KTR_SPARE2, "%s phy=%d, reg=%#x, val=%#x\n", ifp->if_xname, 954 phy, reg, val); 955 #endif 956 957 mtx_lock(&mii_mutex); 958 959 for (i = 0; i < MVNETA_PHY_TIMEOUT; i++) { 960 if ((MVNETA_READ(sc, MVNETA_SMI) & MVNETA_SMI_BUSY) == 0) 961 break; 962 DELAY(1); 963 } 964 if (i == MVNETA_PHY_TIMEOUT) { 965 if_printf(ifp, "SMI busy timeout\n"); 966 mtx_unlock(&mii_mutex); 967 return (0); 968 } 969 970 smi = MVNETA_SMI_PHYAD(phy) | MVNETA_SMI_REGAD(reg) | 971 MVNETA_SMI_OPCODE_WRITE | (val & MVNETA_SMI_DATA_MASK); 972 MVNETA_WRITE(sc, MVNETA_SMI, smi); 973 974 for (i = 0; i < MVNETA_PHY_TIMEOUT; i++) { 975 if ((MVNETA_READ(sc, MVNETA_SMI) & MVNETA_SMI_BUSY) == 0) 976 break; 977 DELAY(1); 978 } 979 980 mtx_unlock(&mii_mutex); 981 982 if (i == MVNETA_PHY_TIMEOUT) 983 if_printf(ifp, "phy write timed out\n"); 984 985 return (0); 986 } 987 988 STATIC void 989 mvneta_portup(struct mvneta_softc *sc) 990 { 991 int q; 992 993 for (q = 0; q < MVNETA_RX_QNUM_MAX; q++) { 994 mvneta_rx_lockq(sc, q); 995 mvneta_rx_queue_enable(sc->ifp, q); 996 mvneta_rx_unlockq(sc, q); 997 } 998 999 for (q = 0; q < MVNETA_TX_QNUM_MAX; q++) { 1000 mvneta_tx_lockq(sc, q); 1001 mvneta_tx_queue_enable(sc->ifp, q); 1002 mvneta_tx_unlockq(sc, q); 1003 } 1004 1005 } 1006 1007 STATIC void 1008 mvneta_portdown(struct mvneta_softc *sc) 1009 { 1010 struct mvneta_rx_ring *rx; 1011 struct mvneta_tx_ring *tx; 1012 int q, cnt; 1013 uint32_t reg; 1014 1015 for (q = 0; q < MVNETA_RX_QNUM_MAX; q++) { 1016 rx = MVNETA_RX_RING(sc, q); 1017 mvneta_rx_lockq(sc, q); 1018 rx->queue_status = MVNETA_QUEUE_DISABLED; 1019 mvneta_rx_unlockq(sc, q); 1020 } 1021 1022 for (q = 0; q < MVNETA_TX_QNUM_MAX; q++) { 1023 tx = MVNETA_TX_RING(sc, q); 1024 mvneta_tx_lockq(sc, q); 1025 tx->queue_status = MVNETA_QUEUE_DISABLED; 1026 mvneta_tx_unlockq(sc, q); 1027 } 1028 1029 /* Wait for all Rx activity to terminate. */ 1030 reg = MVNETA_READ(sc, MVNETA_RQC) & MVNETA_RQC_EN_MASK; 1031 reg = MVNETA_RQC_DIS(reg); 1032 MVNETA_WRITE(sc, MVNETA_RQC, reg); 1033 cnt = 0; 1034 do { 1035 if (cnt >= RX_DISABLE_TIMEOUT) { 1036 if_printf(sc->ifp, 1037 "timeout for RX stopped. rqc 0x%x\n", reg); 1038 break; 1039 } 1040 cnt++; 1041 reg = MVNETA_READ(sc, MVNETA_RQC); 1042 } while ((reg & MVNETA_RQC_EN_MASK) != 0); 1043 1044 /* Wait for all Tx activity to terminate. */ 1045 reg = MVNETA_READ(sc, MVNETA_PIE); 1046 reg &= ~MVNETA_PIE_TXPKTINTRPTENB_MASK; 1047 MVNETA_WRITE(sc, MVNETA_PIE, reg); 1048 1049 reg = MVNETA_READ(sc, MVNETA_PRXTXTIM); 1050 reg &= ~MVNETA_PRXTXTI_TBTCQ_MASK; 1051 MVNETA_WRITE(sc, MVNETA_PRXTXTIM, reg); 1052 1053 reg = MVNETA_READ(sc, MVNETA_TQC) & MVNETA_TQC_EN_MASK; 1054 reg = MVNETA_TQC_DIS(reg); 1055 MVNETA_WRITE(sc, MVNETA_TQC, reg); 1056 cnt = 0; 1057 do { 1058 if (cnt >= TX_DISABLE_TIMEOUT) { 1059 if_printf(sc->ifp, 1060 "timeout for TX stopped. tqc 0x%x\n", reg); 1061 break; 1062 } 1063 cnt++; 1064 reg = MVNETA_READ(sc, MVNETA_TQC); 1065 } while ((reg & MVNETA_TQC_EN_MASK) != 0); 1066 1067 /* Wait for all Tx FIFO is empty */ 1068 cnt = 0; 1069 do { 1070 if (cnt >= TX_FIFO_EMPTY_TIMEOUT) { 1071 if_printf(sc->ifp, 1072 "timeout for TX FIFO drained. ps0 0x%x\n", reg); 1073 break; 1074 } 1075 cnt++; 1076 reg = MVNETA_READ(sc, MVNETA_PS0); 1077 } while (((reg & MVNETA_PS0_TXFIFOEMP) == 0) && 1078 ((reg & MVNETA_PS0_TXINPROG) != 0)); 1079 } 1080 1081 /* 1082 * Device Register Initialization 1083 * reset device registers to device driver default value. 1084 * the device is not enabled here. 1085 */ 1086 STATIC int 1087 mvneta_initreg(struct ifnet *ifp) 1088 { 1089 struct mvneta_softc *sc; 1090 int q; 1091 uint32_t reg; 1092 1093 sc = ifp->if_softc; 1094 #ifdef MVNETA_KTR 1095 CTR1(KTR_SPARE2, "%s initializing device register", ifp->if_xname); 1096 #endif 1097 1098 /* Disable Legacy WRR, Disable EJP, Release from reset. */ 1099 MVNETA_WRITE(sc, MVNETA_TQC_1, 0); 1100 /* Enable mbus retry. */ 1101 MVNETA_WRITE(sc, MVNETA_MBUS_CONF, MVNETA_MBUS_RETRY_EN); 1102 1103 /* Init TX/RX Queue Registers */ 1104 for (q = 0; q < MVNETA_RX_QNUM_MAX; q++) { 1105 mvneta_rx_lockq(sc, q); 1106 if (mvneta_rx_queue_init(ifp, q) != 0) { 1107 device_printf(sc->dev, 1108 "initialization failed: cannot initialize queue\n"); 1109 mvneta_rx_unlockq(sc, q); 1110 return (ENOBUFS); 1111 } 1112 mvneta_rx_unlockq(sc, q); 1113 } 1114 for (q = 0; q < MVNETA_TX_QNUM_MAX; q++) { 1115 mvneta_tx_lockq(sc, q); 1116 if (mvneta_tx_queue_init(ifp, q) != 0) { 1117 device_printf(sc->dev, 1118 "initialization failed: cannot initialize queue\n"); 1119 mvneta_tx_unlockq(sc, q); 1120 return (ENOBUFS); 1121 } 1122 mvneta_tx_unlockq(sc, q); 1123 } 1124 1125 /* 1126 * Ethernet Unit Control - disable automatic PHY management by HW. 1127 * In case the port uses SMI-controlled PHY, poll its status with 1128 * mii_tick() and update MAC settings accordingly. 1129 */ 1130 reg = MVNETA_READ(sc, MVNETA_EUC); 1131 reg &= ~MVNETA_EUC_POLLING; 1132 MVNETA_WRITE(sc, MVNETA_EUC, reg); 1133 1134 /* EEE: Low Power Idle */ 1135 reg = MVNETA_LPIC0_LILIMIT(MVNETA_LPI_LI); 1136 reg |= MVNETA_LPIC0_TSLIMIT(MVNETA_LPI_TS); 1137 MVNETA_WRITE(sc, MVNETA_LPIC0, reg); 1138 1139 reg = MVNETA_LPIC1_TWLIMIT(MVNETA_LPI_TW); 1140 MVNETA_WRITE(sc, MVNETA_LPIC1, reg); 1141 1142 reg = MVNETA_LPIC2_MUSTSET; 1143 MVNETA_WRITE(sc, MVNETA_LPIC2, reg); 1144 1145 /* Port MAC Control set 0 */ 1146 reg = MVNETA_PMACC0_MUSTSET; /* must write 0x1 */ 1147 reg &= ~MVNETA_PMACC0_PORTEN; /* port is still disabled */ 1148 reg |= MVNETA_PMACC0_FRAMESIZELIMIT(ifp->if_mtu + MVNETA_ETHER_SIZE); 1149 MVNETA_WRITE(sc, MVNETA_PMACC0, reg); 1150 1151 /* Port MAC Control set 2 */ 1152 reg = MVNETA_READ(sc, MVNETA_PMACC2); 1153 switch (sc->phy_mode) { 1154 case MVNETA_PHY_QSGMII: 1155 reg |= (MVNETA_PMACC2_PCSEN | MVNETA_PMACC2_RGMIIEN); 1156 MVNETA_WRITE(sc, MVNETA_PSERDESCFG, MVNETA_PSERDESCFG_QSGMII); 1157 break; 1158 case MVNETA_PHY_SGMII: 1159 reg |= (MVNETA_PMACC2_PCSEN | MVNETA_PMACC2_RGMIIEN); 1160 MVNETA_WRITE(sc, MVNETA_PSERDESCFG, MVNETA_PSERDESCFG_SGMII); 1161 break; 1162 case MVNETA_PHY_RGMII: 1163 case MVNETA_PHY_RGMII_ID: 1164 reg |= MVNETA_PMACC2_RGMIIEN; 1165 break; 1166 } 1167 reg |= MVNETA_PMACC2_MUSTSET; 1168 reg &= ~MVNETA_PMACC2_PORTMACRESET; 1169 MVNETA_WRITE(sc, MVNETA_PMACC2, reg); 1170 1171 /* Port Configuration Extended: enable Tx CRC generation */ 1172 reg = MVNETA_READ(sc, MVNETA_PXCX); 1173 reg &= ~MVNETA_PXCX_TXCRCDIS; 1174 MVNETA_WRITE(sc, MVNETA_PXCX, reg); 1175 1176 /* clear MIB counter registers(clear by read) */ 1177 mvneta_sc_lock(sc); 1178 mvneta_clear_mib(sc); 1179 mvneta_sc_unlock(sc); 1180 1181 /* Set SDC register except IPGINT bits */ 1182 reg = MVNETA_SDC_RXBSZ_16_64BITWORDS; 1183 reg |= MVNETA_SDC_TXBSZ_16_64BITWORDS; 1184 reg |= MVNETA_SDC_BLMR; 1185 reg |= MVNETA_SDC_BLMT; 1186 MVNETA_WRITE(sc, MVNETA_SDC, reg); 1187 1188 return (0); 1189 } 1190 1191 STATIC void 1192 mvneta_dmamap_cb(void *arg, bus_dma_segment_t * segs, int nseg, int error) 1193 { 1194 1195 if (error != 0) 1196 return; 1197 *(bus_addr_t *)arg = segs->ds_addr; 1198 } 1199 1200 STATIC int 1201 mvneta_ring_alloc_rx_queue(struct mvneta_softc *sc, int q) 1202 { 1203 struct mvneta_rx_ring *rx; 1204 struct mvneta_buf *rxbuf; 1205 bus_dmamap_t dmap; 1206 int i, error; 1207 1208 if (q >= MVNETA_RX_QNUM_MAX) 1209 return (EINVAL); 1210 1211 rx = MVNETA_RX_RING(sc, q); 1212 mtx_init(&rx->ring_mtx, "mvneta_rx", NULL, MTX_DEF); 1213 /* Allocate DMA memory for Rx descriptors */ 1214 error = bus_dmamem_alloc(sc->rx_dtag, 1215 (void**)&(rx->desc), 1216 BUS_DMA_NOWAIT | BUS_DMA_ZERO, 1217 &rx->desc_map); 1218 if (error != 0 || rx->desc == NULL) 1219 goto fail; 1220 error = bus_dmamap_load(sc->rx_dtag, rx->desc_map, 1221 rx->desc, 1222 sizeof(struct mvneta_rx_desc) * MVNETA_RX_RING_CNT, 1223 mvneta_dmamap_cb, &rx->desc_pa, BUS_DMA_NOWAIT); 1224 if (error != 0) 1225 goto fail; 1226 1227 for (i = 0; i < MVNETA_RX_RING_CNT; i++) { 1228 error = bus_dmamap_create(sc->rxbuf_dtag, 0, &dmap); 1229 if (error != 0) { 1230 device_printf(sc->dev, 1231 "Failed to create DMA map for Rx buffer num: %d\n", i); 1232 goto fail; 1233 } 1234 rxbuf = &rx->rxbuf[i]; 1235 rxbuf->dmap = dmap; 1236 rxbuf->m = NULL; 1237 } 1238 1239 return (0); 1240 fail: 1241 mvneta_rx_lockq(sc, q); 1242 mvneta_ring_flush_rx_queue(sc, q); 1243 mvneta_rx_unlockq(sc, q); 1244 mvneta_ring_dealloc_rx_queue(sc, q); 1245 device_printf(sc->dev, "DMA Ring buffer allocation failure.\n"); 1246 return (error); 1247 } 1248 1249 STATIC int 1250 mvneta_ring_alloc_tx_queue(struct mvneta_softc *sc, int q) 1251 { 1252 struct mvneta_tx_ring *tx; 1253 int error; 1254 1255 if (q >= MVNETA_TX_QNUM_MAX) 1256 return (EINVAL); 1257 tx = MVNETA_TX_RING(sc, q); 1258 mtx_init(&tx->ring_mtx, "mvneta_tx", NULL, MTX_DEF); 1259 error = bus_dmamem_alloc(sc->tx_dtag, 1260 (void**)&(tx->desc), 1261 BUS_DMA_NOWAIT | BUS_DMA_ZERO, 1262 &tx->desc_map); 1263 if (error != 0 || tx->desc == NULL) 1264 goto fail; 1265 error = bus_dmamap_load(sc->tx_dtag, tx->desc_map, 1266 tx->desc, 1267 sizeof(struct mvneta_tx_desc) * MVNETA_TX_RING_CNT, 1268 mvneta_dmamap_cb, &tx->desc_pa, BUS_DMA_NOWAIT); 1269 if (error != 0) 1270 goto fail; 1271 1272 #ifdef MVNETA_MULTIQUEUE 1273 tx->br = buf_ring_alloc(MVNETA_BUFRING_SIZE, M_DEVBUF, M_NOWAIT, 1274 &tx->ring_mtx); 1275 if (tx->br == NULL) { 1276 device_printf(sc->dev, 1277 "Could not setup buffer ring for TxQ(%d)\n", q); 1278 error = ENOMEM; 1279 goto fail; 1280 } 1281 #endif 1282 1283 return (0); 1284 fail: 1285 mvneta_tx_lockq(sc, q); 1286 mvneta_ring_flush_tx_queue(sc, q); 1287 mvneta_tx_unlockq(sc, q); 1288 mvneta_ring_dealloc_tx_queue(sc, q); 1289 device_printf(sc->dev, "DMA Ring buffer allocation failure.\n"); 1290 return (error); 1291 } 1292 1293 STATIC void 1294 mvneta_ring_dealloc_tx_queue(struct mvneta_softc *sc, int q) 1295 { 1296 struct mvneta_tx_ring *tx; 1297 struct mvneta_buf *txbuf; 1298 void *kva; 1299 int error; 1300 int i; 1301 1302 if (q >= MVNETA_TX_QNUM_MAX) 1303 return; 1304 tx = MVNETA_TX_RING(sc, q); 1305 1306 if (tx->taskq != NULL) { 1307 /* Remove task */ 1308 while (taskqueue_cancel(tx->taskq, &tx->task, NULL) != 0) 1309 taskqueue_drain(tx->taskq, &tx->task); 1310 } 1311 #ifdef MVNETA_MULTIQUEUE 1312 if (tx->br != NULL) 1313 drbr_free(tx->br, M_DEVBUF); 1314 #endif 1315 1316 if (sc->txmbuf_dtag != NULL) { 1317 for (i = 0; i < MVNETA_TX_RING_CNT; i++) { 1318 txbuf = &tx->txbuf[i]; 1319 if (txbuf->dmap != NULL) { 1320 error = bus_dmamap_destroy(sc->txmbuf_dtag, 1321 txbuf->dmap); 1322 if (error != 0) { 1323 panic("%s: map busy for Tx descriptor (Q%d, %d)", 1324 __func__, q, i); 1325 } 1326 } 1327 } 1328 } 1329 1330 if (tx->desc_pa != 0) 1331 bus_dmamap_unload(sc->tx_dtag, tx->desc_map); 1332 1333 kva = (void *)tx->desc; 1334 if (kva != NULL) 1335 bus_dmamem_free(sc->tx_dtag, tx->desc, tx->desc_map); 1336 1337 if (mtx_name(&tx->ring_mtx) != NULL) 1338 mtx_destroy(&tx->ring_mtx); 1339 1340 memset(tx, 0, sizeof(*tx)); 1341 } 1342 1343 STATIC void 1344 mvneta_ring_dealloc_rx_queue(struct mvneta_softc *sc, int q) 1345 { 1346 struct mvneta_rx_ring *rx; 1347 struct lro_ctrl *lro; 1348 void *kva; 1349 1350 if (q >= MVNETA_RX_QNUM_MAX) 1351 return; 1352 1353 rx = MVNETA_RX_RING(sc, q); 1354 1355 if (rx->desc_pa != 0) 1356 bus_dmamap_unload(sc->rx_dtag, rx->desc_map); 1357 1358 kva = (void *)rx->desc; 1359 if (kva != NULL) 1360 bus_dmamem_free(sc->rx_dtag, rx->desc, rx->desc_map); 1361 1362 lro = &rx->lro; 1363 tcp_lro_free(lro); 1364 1365 if (mtx_name(&rx->ring_mtx) != NULL) 1366 mtx_destroy(&rx->ring_mtx); 1367 1368 memset(rx, 0, sizeof(*rx)); 1369 } 1370 1371 STATIC int 1372 mvneta_ring_init_rx_queue(struct mvneta_softc *sc, int q) 1373 { 1374 struct mvneta_rx_ring *rx; 1375 struct lro_ctrl *lro; 1376 int error; 1377 1378 if (q >= MVNETA_RX_QNUM_MAX) 1379 return (0); 1380 1381 rx = MVNETA_RX_RING(sc, q); 1382 rx->dma = rx->cpu = 0; 1383 rx->queue_th_received = MVNETA_RXTH_COUNT; 1384 rx->queue_th_time = (mvneta_get_clk() / 1000) / 10; /* 0.1 [ms] */ 1385 1386 /* Initialize LRO */ 1387 rx->lro_enabled = FALSE; 1388 if ((sc->ifp->if_capenable & IFCAP_LRO) != 0) { 1389 lro = &rx->lro; 1390 error = tcp_lro_init(lro); 1391 if (error != 0) 1392 device_printf(sc->dev, "LRO Initialization failed!\n"); 1393 else { 1394 rx->lro_enabled = TRUE; 1395 lro->ifp = sc->ifp; 1396 } 1397 } 1398 1399 return (0); 1400 } 1401 1402 STATIC int 1403 mvneta_ring_init_tx_queue(struct mvneta_softc *sc, int q) 1404 { 1405 struct mvneta_tx_ring *tx; 1406 struct mvneta_buf *txbuf; 1407 int i, error; 1408 1409 if (q >= MVNETA_TX_QNUM_MAX) 1410 return (0); 1411 1412 tx = MVNETA_TX_RING(sc, q); 1413 1414 /* Tx handle */ 1415 for (i = 0; i < MVNETA_TX_RING_CNT; i++) { 1416 txbuf = &tx->txbuf[i]; 1417 txbuf->m = NULL; 1418 /* Tx handle needs DMA map for busdma_load_mbuf() */ 1419 error = bus_dmamap_create(sc->txmbuf_dtag, 0, 1420 &txbuf->dmap); 1421 if (error != 0) { 1422 device_printf(sc->dev, 1423 "can't create dma map (tx ring %d)\n", i); 1424 return (error); 1425 } 1426 } 1427 tx->dma = tx->cpu = 0; 1428 tx->used = 0; 1429 tx->drv_error = 0; 1430 tx->queue_status = MVNETA_QUEUE_DISABLED; 1431 tx->queue_hung = FALSE; 1432 1433 tx->ifp = sc->ifp; 1434 tx->qidx = q; 1435 TASK_INIT(&tx->task, 0, mvneta_tx_task, tx); 1436 tx->taskq = taskqueue_create_fast("mvneta_tx_taskq", M_WAITOK, 1437 taskqueue_thread_enqueue, &tx->taskq); 1438 taskqueue_start_threads(&tx->taskq, 1, PI_NET, "%s: tx_taskq(%d)", 1439 device_get_nameunit(sc->dev), q); 1440 1441 return (0); 1442 } 1443 1444 STATIC void 1445 mvneta_ring_flush_tx_queue(struct mvneta_softc *sc, int q) 1446 { 1447 struct mvneta_tx_ring *tx; 1448 struct mvneta_buf *txbuf; 1449 int i; 1450 1451 tx = MVNETA_TX_RING(sc, q); 1452 KASSERT_TX_MTX(sc, q); 1453 1454 /* Tx handle */ 1455 for (i = 0; i < MVNETA_TX_RING_CNT; i++) { 1456 txbuf = &tx->txbuf[i]; 1457 bus_dmamap_unload(sc->txmbuf_dtag, txbuf->dmap); 1458 if (txbuf->m != NULL) { 1459 m_freem(txbuf->m); 1460 txbuf->m = NULL; 1461 } 1462 } 1463 tx->dma = tx->cpu = 0; 1464 tx->used = 0; 1465 } 1466 1467 STATIC void 1468 mvneta_ring_flush_rx_queue(struct mvneta_softc *sc, int q) 1469 { 1470 struct mvneta_rx_ring *rx; 1471 struct mvneta_buf *rxbuf; 1472 int i; 1473 1474 rx = MVNETA_RX_RING(sc, q); 1475 KASSERT_RX_MTX(sc, q); 1476 1477 /* Rx handle */ 1478 for (i = 0; i < MVNETA_RX_RING_CNT; i++) { 1479 rxbuf = &rx->rxbuf[i]; 1480 mvneta_rx_buf_free(sc, rxbuf); 1481 } 1482 rx->dma = rx->cpu = 0; 1483 } 1484 1485 /* 1486 * Rx/Tx Queue Control 1487 */ 1488 STATIC int 1489 mvneta_rx_queue_init(struct ifnet *ifp, int q) 1490 { 1491 struct mvneta_softc *sc; 1492 struct mvneta_rx_ring *rx; 1493 uint32_t reg; 1494 1495 sc = ifp->if_softc; 1496 KASSERT_RX_MTX(sc, q); 1497 rx = MVNETA_RX_RING(sc, q); 1498 DASSERT(rx->desc_pa != 0); 1499 1500 /* descriptor address */ 1501 MVNETA_WRITE(sc, MVNETA_PRXDQA(q), rx->desc_pa); 1502 1503 /* Rx buffer size and descriptor ring size */ 1504 reg = MVNETA_PRXDQS_BUFFERSIZE(sc->rx_frame_size >> 3); 1505 reg |= MVNETA_PRXDQS_DESCRIPTORSQUEUESIZE(MVNETA_RX_RING_CNT); 1506 MVNETA_WRITE(sc, MVNETA_PRXDQS(q), reg); 1507 #ifdef MVNETA_KTR 1508 CTR3(KTR_SPARE2, "%s PRXDQS(%d): %#x", ifp->if_xname, q, 1509 MVNETA_READ(sc, MVNETA_PRXDQS(q))); 1510 #endif 1511 /* Rx packet offset address */ 1512 reg = MVNETA_PRXC_PACKETOFFSET(MVNETA_PACKET_OFFSET >> 3); 1513 MVNETA_WRITE(sc, MVNETA_PRXC(q), reg); 1514 #ifdef MVNETA_KTR 1515 CTR3(KTR_SPARE2, "%s PRXC(%d): %#x", ifp->if_xname, q, 1516 MVNETA_READ(sc, MVNETA_PRXC(q))); 1517 #endif 1518 1519 /* if DMA is not working, register is not updated */ 1520 DASSERT(MVNETA_READ(sc, MVNETA_PRXDQA(q)) == rx->desc_pa); 1521 return (0); 1522 } 1523 1524 STATIC int 1525 mvneta_tx_queue_init(struct ifnet *ifp, int q) 1526 { 1527 struct mvneta_softc *sc; 1528 struct mvneta_tx_ring *tx; 1529 uint32_t reg; 1530 1531 sc = ifp->if_softc; 1532 KASSERT_TX_MTX(sc, q); 1533 tx = MVNETA_TX_RING(sc, q); 1534 DASSERT(tx->desc_pa != 0); 1535 1536 /* descriptor address */ 1537 MVNETA_WRITE(sc, MVNETA_PTXDQA(q), tx->desc_pa); 1538 1539 /* descriptor ring size */ 1540 reg = MVNETA_PTXDQS_DQS(MVNETA_TX_RING_CNT); 1541 MVNETA_WRITE(sc, MVNETA_PTXDQS(q), reg); 1542 1543 /* if DMA is not working, register is not updated */ 1544 DASSERT(MVNETA_READ(sc, MVNETA_PTXDQA(q)) == tx->desc_pa); 1545 return (0); 1546 } 1547 1548 STATIC int 1549 mvneta_rx_queue_enable(struct ifnet *ifp, int q) 1550 { 1551 struct mvneta_softc *sc; 1552 struct mvneta_rx_ring *rx; 1553 uint32_t reg; 1554 1555 sc = ifp->if_softc; 1556 rx = MVNETA_RX_RING(sc, q); 1557 KASSERT_RX_MTX(sc, q); 1558 1559 /* Set Rx interrupt threshold */ 1560 reg = MVNETA_PRXDQTH_ODT(rx->queue_th_received); 1561 MVNETA_WRITE(sc, MVNETA_PRXDQTH(q), reg); 1562 1563 reg = MVNETA_PRXITTH_RITT(rx->queue_th_time); 1564 MVNETA_WRITE(sc, MVNETA_PRXITTH(q), reg); 1565 1566 /* Unmask RXTX_TH Intr. */ 1567 reg = MVNETA_READ(sc, MVNETA_PRXTXTIM); 1568 reg |= MVNETA_PRXTXTI_RBICTAPQ(q); /* Rx Buffer Interrupt Coalese */ 1569 MVNETA_WRITE(sc, MVNETA_PRXTXTIM, reg); 1570 1571 /* Enable Rx queue */ 1572 reg = MVNETA_READ(sc, MVNETA_RQC) & MVNETA_RQC_EN_MASK; 1573 reg |= MVNETA_RQC_ENQ(q); 1574 MVNETA_WRITE(sc, MVNETA_RQC, reg); 1575 1576 rx->queue_status = MVNETA_QUEUE_WORKING; 1577 return (0); 1578 } 1579 1580 STATIC int 1581 mvneta_tx_queue_enable(struct ifnet *ifp, int q) 1582 { 1583 struct mvneta_softc *sc; 1584 struct mvneta_tx_ring *tx; 1585 1586 sc = ifp->if_softc; 1587 tx = MVNETA_TX_RING(sc, q); 1588 KASSERT_TX_MTX(sc, q); 1589 1590 /* Enable Tx queue */ 1591 MVNETA_WRITE(sc, MVNETA_TQC, MVNETA_TQC_ENQ(q)); 1592 1593 tx->queue_status = MVNETA_QUEUE_IDLE; 1594 tx->queue_hung = FALSE; 1595 return (0); 1596 } 1597 1598 STATIC __inline void 1599 mvneta_rx_lockq(struct mvneta_softc *sc, int q) 1600 { 1601 1602 DASSERT(q >= 0); 1603 DASSERT(q < MVNETA_RX_QNUM_MAX); 1604 mtx_lock(&sc->rx_ring[q].ring_mtx); 1605 } 1606 1607 STATIC __inline void 1608 mvneta_rx_unlockq(struct mvneta_softc *sc, int q) 1609 { 1610 1611 DASSERT(q >= 0); 1612 DASSERT(q < MVNETA_RX_QNUM_MAX); 1613 mtx_unlock(&sc->rx_ring[q].ring_mtx); 1614 } 1615 1616 STATIC __inline int __unused 1617 mvneta_tx_trylockq(struct mvneta_softc *sc, int q) 1618 { 1619 1620 DASSERT(q >= 0); 1621 DASSERT(q < MVNETA_TX_QNUM_MAX); 1622 return (mtx_trylock(&sc->tx_ring[q].ring_mtx)); 1623 } 1624 1625 STATIC __inline void 1626 mvneta_tx_lockq(struct mvneta_softc *sc, int q) 1627 { 1628 1629 DASSERT(q >= 0); 1630 DASSERT(q < MVNETA_TX_QNUM_MAX); 1631 mtx_lock(&sc->tx_ring[q].ring_mtx); 1632 } 1633 1634 STATIC __inline void 1635 mvneta_tx_unlockq(struct mvneta_softc *sc, int q) 1636 { 1637 1638 DASSERT(q >= 0); 1639 DASSERT(q < MVNETA_TX_QNUM_MAX); 1640 mtx_unlock(&sc->tx_ring[q].ring_mtx); 1641 } 1642 1643 /* 1644 * Interrupt Handlers 1645 */ 1646 STATIC void 1647 mvneta_disable_intr(struct mvneta_softc *sc) 1648 { 1649 1650 MVNETA_WRITE(sc, MVNETA_EUIM, 0); 1651 MVNETA_WRITE(sc, MVNETA_EUIC, 0); 1652 MVNETA_WRITE(sc, MVNETA_PRXTXTIM, 0); 1653 MVNETA_WRITE(sc, MVNETA_PRXTXTIC, 0); 1654 MVNETA_WRITE(sc, MVNETA_PRXTXIM, 0); 1655 MVNETA_WRITE(sc, MVNETA_PRXTXIC, 0); 1656 MVNETA_WRITE(sc, MVNETA_PMIM, 0); 1657 MVNETA_WRITE(sc, MVNETA_PMIC, 0); 1658 MVNETA_WRITE(sc, MVNETA_PIE, 0); 1659 } 1660 1661 STATIC void 1662 mvneta_enable_intr(struct mvneta_softc *sc) 1663 { 1664 uint32_t reg; 1665 1666 /* Enable Summary Bit to check all interrupt cause. */ 1667 reg = MVNETA_READ(sc, MVNETA_PRXTXTIM); 1668 reg |= MVNETA_PRXTXTI_PMISCICSUMMARY; 1669 MVNETA_WRITE(sc, MVNETA_PRXTXTIM, reg); 1670 1671 if (sc->use_inband_status) { 1672 /* Enable Port MISC Intr. (via RXTX_TH_Summary bit) */ 1673 MVNETA_WRITE(sc, MVNETA_PMIM, MVNETA_PMI_PHYSTATUSCHNG | 1674 MVNETA_PMI_LINKCHANGE | MVNETA_PMI_PSCSYNCCHANGE); 1675 } 1676 1677 /* Enable All Queue Interrupt */ 1678 reg = MVNETA_READ(sc, MVNETA_PIE); 1679 reg |= MVNETA_PIE_RXPKTINTRPTENB_MASK; 1680 reg |= MVNETA_PIE_TXPKTINTRPTENB_MASK; 1681 MVNETA_WRITE(sc, MVNETA_PIE, reg); 1682 } 1683 1684 STATIC void 1685 mvneta_rxtxth_intr(void *arg) 1686 { 1687 struct mvneta_softc *sc; 1688 struct ifnet *ifp; 1689 uint32_t ic, queues; 1690 1691 sc = arg; 1692 ifp = sc->ifp; 1693 #ifdef MVNETA_KTR 1694 CTR1(KTR_SPARE2, "%s got RXTX_TH_Intr", ifp->if_xname); 1695 #endif 1696 ic = MVNETA_READ(sc, MVNETA_PRXTXTIC); 1697 if (ic == 0) 1698 return; 1699 MVNETA_WRITE(sc, MVNETA_PRXTXTIC, ~ic); 1700 1701 /* Ack maintance interrupt first */ 1702 if (__predict_false((ic & MVNETA_PRXTXTI_PMISCICSUMMARY) && 1703 sc->use_inband_status)) { 1704 mvneta_sc_lock(sc); 1705 mvneta_misc_intr(sc); 1706 mvneta_sc_unlock(sc); 1707 } 1708 if (__predict_false(!(ifp->if_drv_flags & IFF_DRV_RUNNING))) 1709 return; 1710 /* RxTxTH interrupt */ 1711 queues = MVNETA_PRXTXTI_GET_RBICTAPQ(ic); 1712 if (__predict_true(queues)) { 1713 #ifdef MVNETA_KTR 1714 CTR1(KTR_SPARE2, "%s got PRXTXTIC: +RXEOF", ifp->if_xname); 1715 #endif 1716 /* At the moment the driver support only one RX queue. */ 1717 DASSERT(MVNETA_IS_QUEUE_SET(queues, 0)); 1718 mvneta_rx(sc, 0, 0); 1719 } 1720 } 1721 1722 STATIC int 1723 mvneta_misc_intr(struct mvneta_softc *sc) 1724 { 1725 uint32_t ic; 1726 int claimed = 0; 1727 1728 #ifdef MVNETA_KTR 1729 CTR1(KTR_SPARE2, "%s got MISC_INTR", sc->ifp->if_xname); 1730 #endif 1731 KASSERT_SC_MTX(sc); 1732 1733 for (;;) { 1734 ic = MVNETA_READ(sc, MVNETA_PMIC); 1735 ic &= MVNETA_READ(sc, MVNETA_PMIM); 1736 if (ic == 0) 1737 break; 1738 MVNETA_WRITE(sc, MVNETA_PMIC, ~ic); 1739 claimed = 1; 1740 1741 if (ic & (MVNETA_PMI_PHYSTATUSCHNG | 1742 MVNETA_PMI_LINKCHANGE | MVNETA_PMI_PSCSYNCCHANGE)) 1743 mvneta_link_isr(sc); 1744 } 1745 return (claimed); 1746 } 1747 1748 STATIC void 1749 mvneta_tick(void *arg) 1750 { 1751 struct mvneta_softc *sc; 1752 struct mvneta_tx_ring *tx; 1753 struct mvneta_rx_ring *rx; 1754 int q; 1755 uint32_t fc_prev, fc_curr; 1756 1757 sc = arg; 1758 1759 /* 1760 * This is done before mib update to get the right stats 1761 * for this tick. 1762 */ 1763 mvneta_tx_drain(sc); 1764 1765 /* Extract previous flow-control frame received counter. */ 1766 fc_prev = sc->sysctl_mib[MVNETA_MIB_FC_GOOD_IDX].counter; 1767 /* Read mib registers (clear by read). */ 1768 mvneta_update_mib(sc); 1769 /* Extract current flow-control frame received counter. */ 1770 fc_curr = sc->sysctl_mib[MVNETA_MIB_FC_GOOD_IDX].counter; 1771 1772 1773 if (sc->phy_attached && sc->ifp->if_flags & IFF_UP) { 1774 mvneta_sc_lock(sc); 1775 mii_tick(sc->mii); 1776 1777 /* Adjust MAC settings */ 1778 mvneta_adjust_link(sc); 1779 mvneta_sc_unlock(sc); 1780 } 1781 1782 /* 1783 * We were unable to refill the rx queue and left the rx func, leaving 1784 * the ring without mbuf and no way to call the refill func. 1785 */ 1786 for (q = 0; q < MVNETA_RX_QNUM_MAX; q++) { 1787 rx = MVNETA_RX_RING(sc, q); 1788 if (rx->needs_refill == TRUE) { 1789 mvneta_rx_lockq(sc, q); 1790 mvneta_rx_queue_refill(sc, q); 1791 mvneta_rx_unlockq(sc, q); 1792 } 1793 } 1794 1795 /* 1796 * Watchdog: 1797 * - check if queue is mark as hung. 1798 * - ignore hung status if we received some pause frame 1799 * as hardware may have paused packet transmit. 1800 */ 1801 for (q = 0; q < MVNETA_TX_QNUM_MAX; q++) { 1802 /* 1803 * We should take queue lock, but as we only read 1804 * queue status we can do it without lock, we may 1805 * only missdetect queue status for one tick. 1806 */ 1807 tx = MVNETA_TX_RING(sc, q); 1808 1809 if (tx->queue_hung && (fc_curr - fc_prev) == 0) 1810 goto timeout; 1811 } 1812 1813 callout_schedule(&sc->tick_ch, hz); 1814 return; 1815 1816 timeout: 1817 if_printf(sc->ifp, "watchdog timeout\n"); 1818 1819 mvneta_sc_lock(sc); 1820 sc->counter_watchdog++; 1821 sc->counter_watchdog_mib++; 1822 /* Trigger reinitialize sequence. */ 1823 mvneta_stop_locked(sc); 1824 mvneta_init_locked(sc); 1825 mvneta_sc_unlock(sc); 1826 } 1827 1828 STATIC void 1829 mvneta_qflush(struct ifnet *ifp) 1830 { 1831 #ifdef MVNETA_MULTIQUEUE 1832 struct mvneta_softc *sc; 1833 struct mvneta_tx_ring *tx; 1834 struct mbuf *m; 1835 size_t q; 1836 1837 sc = ifp->if_softc; 1838 1839 for (q = 0; q < MVNETA_TX_QNUM_MAX; q++) { 1840 tx = MVNETA_TX_RING(sc, q); 1841 mvneta_tx_lockq(sc, q); 1842 while ((m = buf_ring_dequeue_sc(tx->br)) != NULL) 1843 m_freem(m); 1844 mvneta_tx_unlockq(sc, q); 1845 } 1846 #endif 1847 if_qflush(ifp); 1848 } 1849 1850 STATIC void 1851 mvneta_tx_task(void *arg, int pending) 1852 { 1853 struct mvneta_softc *sc; 1854 struct mvneta_tx_ring *tx; 1855 struct ifnet *ifp; 1856 int error; 1857 1858 tx = arg; 1859 ifp = tx->ifp; 1860 sc = ifp->if_softc; 1861 1862 mvneta_tx_lockq(sc, tx->qidx); 1863 error = mvneta_xmit_locked(sc, tx->qidx); 1864 mvneta_tx_unlockq(sc, tx->qidx); 1865 1866 /* Try again */ 1867 if (__predict_false(error != 0 && error != ENETDOWN)) { 1868 pause("mvneta_tx_task_sleep", 1); 1869 taskqueue_enqueue(tx->taskq, &tx->task); 1870 } 1871 } 1872 1873 STATIC int 1874 mvneta_xmitfast_locked(struct mvneta_softc *sc, int q, struct mbuf **m) 1875 { 1876 struct mvneta_tx_ring *tx; 1877 struct ifnet *ifp; 1878 int error; 1879 1880 KASSERT_TX_MTX(sc, q); 1881 tx = MVNETA_TX_RING(sc, q); 1882 error = 0; 1883 1884 ifp = sc->ifp; 1885 1886 /* Dont enqueue packet if the queue is disabled. */ 1887 if (__predict_false(tx->queue_status == MVNETA_QUEUE_DISABLED)) { 1888 m_freem(*m); 1889 *m = NULL; 1890 return (ENETDOWN); 1891 } 1892 1893 /* Reclaim mbuf if above threshold. */ 1894 if (__predict_true(tx->used > MVNETA_TX_RECLAIM_COUNT)) 1895 mvneta_tx_queue_complete(sc, q); 1896 1897 /* Do not call transmit path if queue is already too full. */ 1898 if (__predict_false(tx->used > 1899 MVNETA_TX_RING_CNT - MVNETA_TX_SEGLIMIT)) 1900 return (ENOBUFS); 1901 1902 error = mvneta_tx_queue(sc, m, q); 1903 if (__predict_false(error != 0)) 1904 return (error); 1905 1906 /* Send a copy of the frame to the BPF listener */ 1907 ETHER_BPF_MTAP(ifp, *m); 1908 1909 /* Set watchdog on */ 1910 tx->watchdog_time = ticks; 1911 tx->queue_status = MVNETA_QUEUE_WORKING; 1912 1913 return (error); 1914 } 1915 1916 #ifdef MVNETA_MULTIQUEUE 1917 STATIC int 1918 mvneta_transmit(struct ifnet *ifp, struct mbuf *m) 1919 { 1920 struct mvneta_softc *sc; 1921 struct mvneta_tx_ring *tx; 1922 int error; 1923 int q; 1924 1925 sc = ifp->if_softc; 1926 1927 /* Use default queue if there is no flow id as thread can migrate. */ 1928 if (__predict_true(M_HASHTYPE_GET(m) != M_HASHTYPE_NONE)) 1929 q = m->m_pkthdr.flowid % MVNETA_TX_QNUM_MAX; 1930 else 1931 q = 0; 1932 1933 tx = MVNETA_TX_RING(sc, q); 1934 1935 /* If buf_ring is full start transmit immediatly. */ 1936 if (buf_ring_full(tx->br)) { 1937 mvneta_tx_lockq(sc, q); 1938 mvneta_xmit_locked(sc, q); 1939 mvneta_tx_unlockq(sc, q); 1940 } 1941 1942 /* 1943 * If the buf_ring is empty we will not reorder packets. 1944 * If the lock is available transmit without using buf_ring. 1945 */ 1946 if (buf_ring_empty(tx->br) && mvneta_tx_trylockq(sc, q) != 0) { 1947 error = mvneta_xmitfast_locked(sc, q, &m); 1948 mvneta_tx_unlockq(sc, q); 1949 if (__predict_true(error == 0)) 1950 return (0); 1951 1952 /* Transmit can fail in fastpath. */ 1953 if (__predict_false(m == NULL)) 1954 return (error); 1955 } 1956 1957 /* Enqueue then schedule taskqueue. */ 1958 error = drbr_enqueue(ifp, tx->br, m); 1959 if (__predict_false(error != 0)) 1960 return (error); 1961 1962 taskqueue_enqueue(tx->taskq, &tx->task); 1963 return (0); 1964 } 1965 1966 STATIC int 1967 mvneta_xmit_locked(struct mvneta_softc *sc, int q) 1968 { 1969 struct ifnet *ifp; 1970 struct mvneta_tx_ring *tx; 1971 struct mbuf *m; 1972 int error; 1973 1974 KASSERT_TX_MTX(sc, q); 1975 ifp = sc->ifp; 1976 tx = MVNETA_TX_RING(sc, q); 1977 error = 0; 1978 1979 while ((m = drbr_peek(ifp, tx->br)) != NULL) { 1980 error = mvneta_xmitfast_locked(sc, q, &m); 1981 if (__predict_false(error != 0)) { 1982 if (m != NULL) 1983 drbr_putback(ifp, tx->br, m); 1984 else 1985 drbr_advance(ifp, tx->br); 1986 break; 1987 } 1988 drbr_advance(ifp, tx->br); 1989 } 1990 1991 return (error); 1992 } 1993 #else /* !MVNETA_MULTIQUEUE */ 1994 STATIC void 1995 mvneta_start(struct ifnet *ifp) 1996 { 1997 struct mvneta_softc *sc; 1998 struct mvneta_tx_ring *tx; 1999 int error; 2000 2001 sc = ifp->if_softc; 2002 tx = MVNETA_TX_RING(sc, 0); 2003 2004 mvneta_tx_lockq(sc, 0); 2005 error = mvneta_xmit_locked(sc, 0); 2006 mvneta_tx_unlockq(sc, 0); 2007 /* Handle retransmit in the background taskq. */ 2008 if (__predict_false(error != 0 && error != ENETDOWN)) 2009 taskqueue_enqueue(tx->taskq, &tx->task); 2010 } 2011 2012 STATIC int 2013 mvneta_xmit_locked(struct mvneta_softc *sc, int q) 2014 { 2015 struct ifnet *ifp; 2016 struct mvneta_tx_ring *tx; 2017 struct mbuf *m; 2018 int error; 2019 2020 KASSERT_TX_MTX(sc, q); 2021 ifp = sc->ifp; 2022 tx = MVNETA_TX_RING(sc, 0); 2023 error = 0; 2024 2025 while (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 2026 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 2027 if (m == NULL) 2028 break; 2029 2030 error = mvneta_xmitfast_locked(sc, q, &m); 2031 if (__predict_false(error != 0)) { 2032 if (m != NULL) 2033 IFQ_DRV_PREPEND(&ifp->if_snd, m); 2034 break; 2035 } 2036 } 2037 2038 return (error); 2039 } 2040 #endif 2041 2042 STATIC int 2043 mvneta_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 2044 { 2045 struct mvneta_softc *sc; 2046 struct mvneta_rx_ring *rx; 2047 struct ifreq *ifr; 2048 int error, mask; 2049 uint32_t flags; 2050 int q; 2051 2052 error = 0; 2053 sc = ifp->if_softc; 2054 ifr = (struct ifreq *)data; 2055 switch (cmd) { 2056 case SIOCSIFFLAGS: 2057 mvneta_sc_lock(sc); 2058 if (ifp->if_flags & IFF_UP) { 2059 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 2060 flags = ifp->if_flags ^ sc->mvneta_if_flags; 2061 2062 if (flags != 0) 2063 sc->mvneta_if_flags = ifp->if_flags; 2064 2065 if ((flags & IFF_PROMISC) != 0) 2066 mvneta_filter_setup(sc); 2067 } else { 2068 mvneta_init_locked(sc); 2069 sc->mvneta_if_flags = ifp->if_flags; 2070 if (sc->phy_attached) 2071 mii_mediachg(sc->mii); 2072 mvneta_sc_unlock(sc); 2073 break; 2074 } 2075 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2076 mvneta_stop_locked(sc); 2077 2078 sc->mvneta_if_flags = ifp->if_flags; 2079 mvneta_sc_unlock(sc); 2080 break; 2081 case SIOCSIFCAP: 2082 if (ifp->if_mtu > sc->tx_csum_limit && 2083 ifr->ifr_reqcap & IFCAP_TXCSUM) 2084 ifr->ifr_reqcap &= ~IFCAP_TXCSUM; 2085 mask = ifp->if_capenable ^ ifr->ifr_reqcap; 2086 if (mask & IFCAP_HWCSUM) { 2087 ifp->if_capenable &= ~IFCAP_HWCSUM; 2088 ifp->if_capenable |= IFCAP_HWCSUM & ifr->ifr_reqcap; 2089 if (ifp->if_capenable & IFCAP_TXCSUM) 2090 ifp->if_hwassist = CSUM_IP | CSUM_TCP | 2091 CSUM_UDP; 2092 else 2093 ifp->if_hwassist = 0; 2094 } 2095 if (mask & IFCAP_LRO) { 2096 mvneta_sc_lock(sc); 2097 ifp->if_capenable ^= IFCAP_LRO; 2098 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2099 for (q = 0; q < MVNETA_RX_QNUM_MAX; q++) { 2100 rx = MVNETA_RX_RING(sc, q); 2101 rx->lro_enabled = !rx->lro_enabled; 2102 } 2103 } 2104 mvneta_sc_unlock(sc); 2105 } 2106 VLAN_CAPABILITIES(ifp); 2107 break; 2108 case SIOCSIFMEDIA: 2109 if ((IFM_SUBTYPE(ifr->ifr_media) == IFM_1000_T || 2110 IFM_SUBTYPE(ifr->ifr_media) == IFM_2500_T) && 2111 (ifr->ifr_media & IFM_FDX) == 0) { 2112 device_printf(sc->dev, 2113 "%s half-duplex unsupported\n", 2114 IFM_SUBTYPE(ifr->ifr_media) == IFM_1000_T ? 2115 "1000Base-T" : 2116 "2500Base-T"); 2117 error = EINVAL; 2118 break; 2119 } 2120 case SIOCGIFMEDIA: /* FALLTHROUGH */ 2121 case SIOCGIFXMEDIA: 2122 if (!sc->phy_attached) 2123 error = ifmedia_ioctl(ifp, ifr, &sc->mvneta_ifmedia, 2124 cmd); 2125 else 2126 error = ifmedia_ioctl(ifp, ifr, &sc->mii->mii_media, 2127 cmd); 2128 break; 2129 case SIOCSIFMTU: 2130 if (ifr->ifr_mtu < 68 || ifr->ifr_mtu > MVNETA_MAX_FRAME - 2131 MVNETA_ETHER_SIZE) { 2132 error = EINVAL; 2133 } else { 2134 ifp->if_mtu = ifr->ifr_mtu; 2135 mvneta_sc_lock(sc); 2136 if (ifp->if_mtu + MVNETA_ETHER_SIZE <= MCLBYTES) { 2137 sc->rx_frame_size = MCLBYTES; 2138 } else { 2139 sc->rx_frame_size = MJUM9BYTES; 2140 } 2141 if (ifp->if_mtu > sc->tx_csum_limit) { 2142 ifp->if_capenable &= ~IFCAP_TXCSUM; 2143 ifp->if_hwassist = 0; 2144 } else { 2145 ifp->if_capenable |= IFCAP_TXCSUM; 2146 ifp->if_hwassist = CSUM_IP | CSUM_TCP | 2147 CSUM_UDP; 2148 } 2149 /* 2150 * Reinitialize RX queues. 2151 * We need to update RX descriptor size. 2152 */ 2153 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2154 mvneta_stop_locked(sc); 2155 2156 for (q = 0; q < MVNETA_RX_QNUM_MAX; q++) { 2157 mvneta_rx_lockq(sc, q); 2158 if (mvneta_rx_queue_init(ifp, q) != 0) { 2159 device_printf(sc->dev, 2160 "initialization failed:" 2161 " cannot initialize queue\n"); 2162 mvneta_rx_unlockq(sc, q); 2163 error = ENOBUFS; 2164 break; 2165 } 2166 mvneta_rx_unlockq(sc, q); 2167 } 2168 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2169 mvneta_init_locked(sc); 2170 2171 mvneta_sc_unlock(sc); 2172 } 2173 break; 2174 2175 default: 2176 error = ether_ioctl(ifp, cmd, data); 2177 break; 2178 } 2179 2180 return (error); 2181 } 2182 2183 STATIC void 2184 mvneta_init_locked(void *arg) 2185 { 2186 struct mvneta_softc *sc; 2187 struct ifnet *ifp; 2188 uint32_t reg; 2189 int q, cpu; 2190 2191 sc = arg; 2192 ifp = sc->ifp; 2193 2194 if (!device_is_attached(sc->dev) || 2195 (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2196 return; 2197 2198 mvneta_disable_intr(sc); 2199 callout_stop(&sc->tick_ch); 2200 2201 /* Get the latest mac address */ 2202 bcopy(IF_LLADDR(ifp), sc->enaddr, ETHER_ADDR_LEN); 2203 mvneta_set_mac_address(sc, sc->enaddr); 2204 mvneta_filter_setup(sc); 2205 2206 /* Start DMA Engine */ 2207 MVNETA_WRITE(sc, MVNETA_PRXINIT, 0x00000000); 2208 MVNETA_WRITE(sc, MVNETA_PTXINIT, 0x00000000); 2209 MVNETA_WRITE(sc, MVNETA_PACC, MVNETA_PACC_ACCELERATIONMODE_EDM); 2210 2211 /* Enable port */ 2212 reg = MVNETA_READ(sc, MVNETA_PMACC0); 2213 reg |= MVNETA_PMACC0_PORTEN; 2214 reg &= ~MVNETA_PMACC0_FRAMESIZELIMIT_MASK; 2215 reg |= MVNETA_PMACC0_FRAMESIZELIMIT(ifp->if_mtu + MVNETA_ETHER_SIZE); 2216 MVNETA_WRITE(sc, MVNETA_PMACC0, reg); 2217 2218 /* Allow access to each TXQ/RXQ from both CPU's */ 2219 for (cpu = 0; cpu < mp_ncpus; ++cpu) 2220 MVNETA_WRITE(sc, MVNETA_PCP2Q(cpu), 2221 MVNETA_PCP2Q_TXQEN_MASK | MVNETA_PCP2Q_RXQEN_MASK); 2222 2223 for (q = 0; q < MVNETA_RX_QNUM_MAX; q++) { 2224 mvneta_rx_lockq(sc, q); 2225 mvneta_rx_queue_refill(sc, q); 2226 mvneta_rx_unlockq(sc, q); 2227 } 2228 2229 if (!sc->phy_attached) 2230 mvneta_linkup(sc); 2231 2232 /* Enable interrupt */ 2233 mvneta_enable_intr(sc); 2234 2235 /* Set Counter */ 2236 callout_schedule(&sc->tick_ch, hz); 2237 2238 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2239 } 2240 2241 STATIC void 2242 mvneta_init(void *arg) 2243 { 2244 struct mvneta_softc *sc; 2245 2246 sc = arg; 2247 mvneta_sc_lock(sc); 2248 mvneta_init_locked(sc); 2249 if (sc->phy_attached) 2250 mii_mediachg(sc->mii); 2251 mvneta_sc_unlock(sc); 2252 } 2253 2254 /* ARGSUSED */ 2255 STATIC void 2256 mvneta_stop_locked(struct mvneta_softc *sc) 2257 { 2258 struct ifnet *ifp; 2259 struct mvneta_rx_ring *rx; 2260 struct mvneta_tx_ring *tx; 2261 uint32_t reg; 2262 int q; 2263 2264 ifp = sc->ifp; 2265 if (ifp == NULL || (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 2266 return; 2267 2268 mvneta_disable_intr(sc); 2269 2270 callout_stop(&sc->tick_ch); 2271 2272 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2273 2274 /* Link down */ 2275 if (sc->linkup == TRUE) 2276 mvneta_linkdown(sc); 2277 2278 /* Reset the MAC Port Enable bit */ 2279 reg = MVNETA_READ(sc, MVNETA_PMACC0); 2280 reg &= ~MVNETA_PMACC0_PORTEN; 2281 MVNETA_WRITE(sc, MVNETA_PMACC0, reg); 2282 2283 /* Disable each of queue */ 2284 for (q = 0; q < MVNETA_RX_QNUM_MAX; q++) { 2285 rx = MVNETA_RX_RING(sc, q); 2286 2287 mvneta_rx_lockq(sc, q); 2288 mvneta_ring_flush_rx_queue(sc, q); 2289 mvneta_rx_unlockq(sc, q); 2290 } 2291 2292 /* 2293 * Hold Reset state of DMA Engine 2294 * (must write 0x0 to restart it) 2295 */ 2296 MVNETA_WRITE(sc, MVNETA_PRXINIT, 0x00000001); 2297 MVNETA_WRITE(sc, MVNETA_PTXINIT, 0x00000001); 2298 2299 for (q = 0; q < MVNETA_TX_QNUM_MAX; q++) { 2300 tx = MVNETA_TX_RING(sc, q); 2301 2302 mvneta_tx_lockq(sc, q); 2303 mvneta_ring_flush_tx_queue(sc, q); 2304 mvneta_tx_unlockq(sc, q); 2305 } 2306 } 2307 2308 STATIC void 2309 mvneta_stop(struct mvneta_softc *sc) 2310 { 2311 2312 mvneta_sc_lock(sc); 2313 mvneta_stop_locked(sc); 2314 mvneta_sc_unlock(sc); 2315 } 2316 2317 STATIC int 2318 mvneta_mediachange(struct ifnet *ifp) 2319 { 2320 struct mvneta_softc *sc; 2321 2322 sc = ifp->if_softc; 2323 2324 if (!sc->phy_attached && !sc->use_inband_status) { 2325 /* We shouldn't be here */ 2326 if_printf(ifp, "Cannot change media in fixed-link mode!\n"); 2327 return (0); 2328 } 2329 2330 if (sc->use_inband_status) { 2331 mvneta_update_media(sc, sc->mvneta_ifmedia.ifm_media); 2332 return (0); 2333 } 2334 2335 mvneta_sc_lock(sc); 2336 2337 /* Update PHY */ 2338 mii_mediachg(sc->mii); 2339 2340 mvneta_sc_unlock(sc); 2341 2342 return (0); 2343 } 2344 2345 STATIC void 2346 mvneta_get_media(struct mvneta_softc *sc, struct ifmediareq *ifmr) 2347 { 2348 uint32_t psr; 2349 2350 psr = MVNETA_READ(sc, MVNETA_PSR); 2351 2352 /* Speed */ 2353 if (psr & MVNETA_PSR_GMIISPEED) 2354 ifmr->ifm_active = IFM_ETHER_SUBTYPE_SET(IFM_1000_T); 2355 else if (psr & MVNETA_PSR_MIISPEED) 2356 ifmr->ifm_active = IFM_ETHER_SUBTYPE_SET(IFM_100_TX); 2357 else if (psr & MVNETA_PSR_LINKUP) 2358 ifmr->ifm_active = IFM_ETHER_SUBTYPE_SET(IFM_10_T); 2359 2360 /* Duplex */ 2361 if (psr & MVNETA_PSR_FULLDX) 2362 ifmr->ifm_active |= IFM_FDX; 2363 2364 /* Link */ 2365 ifmr->ifm_status = IFM_AVALID; 2366 if (psr & MVNETA_PSR_LINKUP) 2367 ifmr->ifm_status |= IFM_ACTIVE; 2368 } 2369 2370 STATIC void 2371 mvneta_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 2372 { 2373 struct mvneta_softc *sc; 2374 struct mii_data *mii; 2375 2376 sc = ifp->if_softc; 2377 2378 if (!sc->phy_attached && !sc->use_inband_status) { 2379 ifmr->ifm_status = IFM_AVALID | IFM_ACTIVE; 2380 return; 2381 } 2382 2383 mvneta_sc_lock(sc); 2384 2385 if (sc->use_inband_status) { 2386 mvneta_get_media(sc, ifmr); 2387 mvneta_sc_unlock(sc); 2388 return; 2389 } 2390 2391 mii = sc->mii; 2392 mii_pollstat(mii); 2393 2394 ifmr->ifm_active = mii->mii_media_active; 2395 ifmr->ifm_status = mii->mii_media_status; 2396 2397 mvneta_sc_unlock(sc); 2398 } 2399 2400 /* 2401 * Link State Notify 2402 */ 2403 STATIC void 2404 mvneta_update_autoneg(struct mvneta_softc *sc, int enable) 2405 { 2406 int reg; 2407 2408 if (enable) { 2409 reg = MVNETA_READ(sc, MVNETA_PANC); 2410 reg &= ~(MVNETA_PANC_FORCELINKFAIL | MVNETA_PANC_FORCELINKPASS | 2411 MVNETA_PANC_ANFCEN); 2412 reg |= MVNETA_PANC_ANDUPLEXEN | MVNETA_PANC_ANSPEEDEN | 2413 MVNETA_PANC_INBANDANEN; 2414 MVNETA_WRITE(sc, MVNETA_PANC, reg); 2415 2416 reg = MVNETA_READ(sc, MVNETA_PMACC2); 2417 reg |= MVNETA_PMACC2_INBANDANMODE; 2418 MVNETA_WRITE(sc, MVNETA_PMACC2, reg); 2419 2420 reg = MVNETA_READ(sc, MVNETA_PSOMSCD); 2421 reg |= MVNETA_PSOMSCD_ENABLE; 2422 MVNETA_WRITE(sc, MVNETA_PSOMSCD, reg); 2423 } else { 2424 reg = MVNETA_READ(sc, MVNETA_PANC); 2425 reg &= ~(MVNETA_PANC_FORCELINKFAIL | MVNETA_PANC_FORCELINKPASS | 2426 MVNETA_PANC_ANDUPLEXEN | MVNETA_PANC_ANSPEEDEN | 2427 MVNETA_PANC_INBANDANEN); 2428 MVNETA_WRITE(sc, MVNETA_PANC, reg); 2429 2430 reg = MVNETA_READ(sc, MVNETA_PMACC2); 2431 reg &= ~MVNETA_PMACC2_INBANDANMODE; 2432 MVNETA_WRITE(sc, MVNETA_PMACC2, reg); 2433 2434 reg = MVNETA_READ(sc, MVNETA_PSOMSCD); 2435 reg &= ~MVNETA_PSOMSCD_ENABLE; 2436 MVNETA_WRITE(sc, MVNETA_PSOMSCD, reg); 2437 } 2438 } 2439 2440 STATIC int 2441 mvneta_update_media(struct mvneta_softc *sc, int media) 2442 { 2443 int reg, err; 2444 boolean_t running; 2445 2446 err = 0; 2447 2448 mvneta_sc_lock(sc); 2449 2450 mvneta_linkreset(sc); 2451 2452 running = (sc->ifp->if_drv_flags & IFF_DRV_RUNNING) != 0; 2453 if (running) 2454 mvneta_stop_locked(sc); 2455 2456 sc->autoneg = (IFM_SUBTYPE(media) == IFM_AUTO); 2457 2458 if (sc->use_inband_status) 2459 mvneta_update_autoneg(sc, IFM_SUBTYPE(media) == IFM_AUTO); 2460 2461 mvneta_update_eee(sc); 2462 mvneta_update_fc(sc); 2463 2464 if (IFM_SUBTYPE(media) != IFM_AUTO) { 2465 reg = MVNETA_READ(sc, MVNETA_PANC); 2466 reg &= ~(MVNETA_PANC_SETGMIISPEED | 2467 MVNETA_PANC_SETMIISPEED | 2468 MVNETA_PANC_SETFULLDX); 2469 if (IFM_SUBTYPE(media) == IFM_1000_T || 2470 IFM_SUBTYPE(media) == IFM_2500_T) { 2471 if ((media & IFM_FDX) == 0) { 2472 device_printf(sc->dev, 2473 "%s half-duplex unsupported\n", 2474 IFM_SUBTYPE(media) == IFM_1000_T ? 2475 "1000Base-T" : 2476 "2500Base-T"); 2477 err = EINVAL; 2478 goto out; 2479 } 2480 reg |= MVNETA_PANC_SETGMIISPEED; 2481 } else if (IFM_SUBTYPE(media) == IFM_100_TX) 2482 reg |= MVNETA_PANC_SETMIISPEED; 2483 2484 if (media & IFM_FDX) 2485 reg |= MVNETA_PANC_SETFULLDX; 2486 2487 MVNETA_WRITE(sc, MVNETA_PANC, reg); 2488 } 2489 out: 2490 if (running) 2491 mvneta_init_locked(sc); 2492 mvneta_sc_unlock(sc); 2493 return (err); 2494 } 2495 2496 STATIC void 2497 mvneta_adjust_link(struct mvneta_softc *sc) 2498 { 2499 boolean_t phy_linkup; 2500 int reg; 2501 2502 /* Update eee/fc */ 2503 mvneta_update_eee(sc); 2504 mvneta_update_fc(sc); 2505 2506 /* Check for link change */ 2507 phy_linkup = (sc->mii->mii_media_status & 2508 (IFM_AVALID | IFM_ACTIVE)) == (IFM_AVALID | IFM_ACTIVE); 2509 2510 if (sc->linkup != phy_linkup) 2511 mvneta_linkupdate(sc, phy_linkup); 2512 2513 /* Don't update media on disabled link */ 2514 if (!phy_linkup) 2515 return; 2516 2517 /* Check for media type change */ 2518 if (sc->mvneta_media != sc->mii->mii_media_active) { 2519 sc->mvneta_media = sc->mii->mii_media_active; 2520 2521 reg = MVNETA_READ(sc, MVNETA_PANC); 2522 reg &= ~(MVNETA_PANC_SETGMIISPEED | 2523 MVNETA_PANC_SETMIISPEED | 2524 MVNETA_PANC_SETFULLDX); 2525 if (IFM_SUBTYPE(sc->mvneta_media) == IFM_1000_T || 2526 IFM_SUBTYPE(sc->mvneta_media) == IFM_2500_T) { 2527 reg |= MVNETA_PANC_SETGMIISPEED; 2528 } else if (IFM_SUBTYPE(sc->mvneta_media) == IFM_100_TX) 2529 reg |= MVNETA_PANC_SETMIISPEED; 2530 2531 if (sc->mvneta_media & IFM_FDX) 2532 reg |= MVNETA_PANC_SETFULLDX; 2533 2534 MVNETA_WRITE(sc, MVNETA_PANC, reg); 2535 } 2536 } 2537 2538 STATIC void 2539 mvneta_link_isr(struct mvneta_softc *sc) 2540 { 2541 int linkup; 2542 2543 KASSERT_SC_MTX(sc); 2544 2545 linkup = MVNETA_IS_LINKUP(sc) ? TRUE : FALSE; 2546 if (sc->linkup == linkup) 2547 return; 2548 2549 if (linkup == TRUE) 2550 mvneta_linkup(sc); 2551 else 2552 mvneta_linkdown(sc); 2553 2554 #ifdef DEBUG 2555 device_printf(sc->dev, 2556 "%s: link %s\n", sc->ifp->if_xname, linkup ? "up" : "down"); 2557 #endif 2558 } 2559 2560 STATIC void 2561 mvneta_linkupdate(struct mvneta_softc *sc, boolean_t linkup) 2562 { 2563 2564 KASSERT_SC_MTX(sc); 2565 2566 if (linkup == TRUE) 2567 mvneta_linkup(sc); 2568 else 2569 mvneta_linkdown(sc); 2570 2571 #ifdef DEBUG 2572 device_printf(sc->dev, 2573 "%s: link %s\n", sc->ifp->if_xname, linkup ? "up" : "down"); 2574 #endif 2575 } 2576 2577 STATIC void 2578 mvneta_update_eee(struct mvneta_softc *sc) 2579 { 2580 uint32_t reg; 2581 2582 KASSERT_SC_MTX(sc); 2583 2584 /* set EEE parameters */ 2585 reg = MVNETA_READ(sc, MVNETA_LPIC1); 2586 if (sc->cf_lpi) 2587 reg |= MVNETA_LPIC1_LPIRE; 2588 else 2589 reg &= ~MVNETA_LPIC1_LPIRE; 2590 MVNETA_WRITE(sc, MVNETA_LPIC1, reg); 2591 } 2592 2593 STATIC void 2594 mvneta_update_fc(struct mvneta_softc *sc) 2595 { 2596 uint32_t reg; 2597 2598 KASSERT_SC_MTX(sc); 2599 2600 reg = MVNETA_READ(sc, MVNETA_PANC); 2601 if (sc->cf_fc) { 2602 /* Flow control negotiation */ 2603 reg |= MVNETA_PANC_PAUSEADV; 2604 reg |= MVNETA_PANC_ANFCEN; 2605 } else { 2606 /* Disable flow control negotiation */ 2607 reg &= ~MVNETA_PANC_PAUSEADV; 2608 reg &= ~MVNETA_PANC_ANFCEN; 2609 } 2610 2611 MVNETA_WRITE(sc, MVNETA_PANC, reg); 2612 } 2613 2614 STATIC void 2615 mvneta_linkup(struct mvneta_softc *sc) 2616 { 2617 uint32_t reg; 2618 2619 KASSERT_SC_MTX(sc); 2620 2621 if (!sc->use_inband_status) { 2622 reg = MVNETA_READ(sc, MVNETA_PANC); 2623 reg |= MVNETA_PANC_FORCELINKPASS; 2624 reg &= ~MVNETA_PANC_FORCELINKFAIL; 2625 MVNETA_WRITE(sc, MVNETA_PANC, reg); 2626 } 2627 2628 mvneta_qflush(sc->ifp); 2629 mvneta_portup(sc); 2630 sc->linkup = TRUE; 2631 if_link_state_change(sc->ifp, LINK_STATE_UP); 2632 } 2633 2634 STATIC void 2635 mvneta_linkdown(struct mvneta_softc *sc) 2636 { 2637 uint32_t reg; 2638 2639 KASSERT_SC_MTX(sc); 2640 2641 if (!sc->use_inband_status) { 2642 reg = MVNETA_READ(sc, MVNETA_PANC); 2643 reg &= ~MVNETA_PANC_FORCELINKPASS; 2644 reg |= MVNETA_PANC_FORCELINKFAIL; 2645 MVNETA_WRITE(sc, MVNETA_PANC, reg); 2646 } 2647 2648 mvneta_portdown(sc); 2649 mvneta_qflush(sc->ifp); 2650 sc->linkup = FALSE; 2651 if_link_state_change(sc->ifp, LINK_STATE_DOWN); 2652 } 2653 2654 STATIC void 2655 mvneta_linkreset(struct mvneta_softc *sc) 2656 { 2657 struct mii_softc *mii; 2658 2659 if (sc->phy_attached) { 2660 /* Force reset PHY */ 2661 mii = LIST_FIRST(&sc->mii->mii_phys); 2662 if (mii) 2663 mii_phy_reset(mii); 2664 } 2665 } 2666 2667 /* 2668 * Tx Subroutines 2669 */ 2670 STATIC int 2671 mvneta_tx_queue(struct mvneta_softc *sc, struct mbuf **mbufp, int q) 2672 { 2673 struct ifnet *ifp; 2674 bus_dma_segment_t txsegs[MVNETA_TX_SEGLIMIT]; 2675 struct mbuf *mtmp, *mbuf; 2676 struct mvneta_tx_ring *tx; 2677 struct mvneta_buf *txbuf; 2678 struct mvneta_tx_desc *t; 2679 uint32_t ptxsu; 2680 int start, used, error, i, txnsegs; 2681 2682 mbuf = *mbufp; 2683 tx = MVNETA_TX_RING(sc, q); 2684 DASSERT(tx->used >= 0); 2685 DASSERT(tx->used <= MVNETA_TX_RING_CNT); 2686 t = NULL; 2687 ifp = sc->ifp; 2688 2689 if (__predict_false(mbuf->m_flags & M_VLANTAG)) { 2690 mbuf = ether_vlanencap(mbuf, mbuf->m_pkthdr.ether_vtag); 2691 if (mbuf == NULL) { 2692 tx->drv_error++; 2693 *mbufp = NULL; 2694 return (ENOBUFS); 2695 } 2696 mbuf->m_flags &= ~M_VLANTAG; 2697 *mbufp = mbuf; 2698 } 2699 2700 if (__predict_false(mbuf->m_next != NULL && 2701 (mbuf->m_pkthdr.csum_flags & 2702 (CSUM_IP | CSUM_TCP | CSUM_UDP)) != 0)) { 2703 if (M_WRITABLE(mbuf) == 0) { 2704 mtmp = m_dup(mbuf, M_NOWAIT); 2705 m_freem(mbuf); 2706 if (mtmp == NULL) { 2707 tx->drv_error++; 2708 *mbufp = NULL; 2709 return (ENOBUFS); 2710 } 2711 *mbufp = mbuf = mtmp; 2712 } 2713 } 2714 2715 /* load mbuf using dmamap of 1st descriptor */ 2716 txbuf = &tx->txbuf[tx->cpu]; 2717 error = bus_dmamap_load_mbuf_sg(sc->txmbuf_dtag, 2718 txbuf->dmap, mbuf, txsegs, &txnsegs, 2719 BUS_DMA_NOWAIT); 2720 if (__predict_false(error != 0)) { 2721 #ifdef MVNETA_KTR 2722 CTR3(KTR_SPARE2, "%s:%u bus_dmamap_load_mbuf_sg error=%d", ifp->if_xname, q, error); 2723 #endif 2724 /* This is the only recoverable error (except EFBIG). */ 2725 if (error != ENOMEM) { 2726 tx->drv_error++; 2727 m_freem(mbuf); 2728 *mbufp = NULL; 2729 return (ENOBUFS); 2730 } 2731 return (error); 2732 } 2733 2734 if (__predict_false(txnsegs <= 0 2735 || (txnsegs + tx->used) > MVNETA_TX_RING_CNT)) { 2736 /* we have no enough descriptors or mbuf is broken */ 2737 #ifdef MVNETA_KTR 2738 CTR3(KTR_SPARE2, "%s:%u not enough descriptors txnsegs=%d", 2739 ifp->if_xname, q, txnsegs); 2740 #endif 2741 bus_dmamap_unload(sc->txmbuf_dtag, txbuf->dmap); 2742 return (ENOBUFS); 2743 } 2744 DASSERT(txbuf->m == NULL); 2745 2746 /* remember mbuf using 1st descriptor */ 2747 txbuf->m = mbuf; 2748 bus_dmamap_sync(sc->txmbuf_dtag, txbuf->dmap, 2749 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2750 2751 /* load to tx descriptors */ 2752 start = tx->cpu; 2753 used = 0; 2754 for (i = 0; i < txnsegs; i++) { 2755 t = &tx->desc[tx->cpu]; 2756 t->command = 0; 2757 t->l4ichk = 0; 2758 t->flags = 0; 2759 if (__predict_true(i == 0)) { 2760 /* 1st descriptor */ 2761 t->command |= MVNETA_TX_CMD_W_PACKET_OFFSET(0); 2762 t->command |= MVNETA_TX_CMD_F; 2763 mvneta_tx_set_csumflag(ifp, t, mbuf); 2764 } 2765 t->bufptr_pa = txsegs[i].ds_addr; 2766 t->bytecnt = txsegs[i].ds_len; 2767 tx->cpu = tx_counter_adv(tx->cpu, 1); 2768 2769 tx->used++; 2770 used++; 2771 } 2772 /* t is last descriptor here */ 2773 DASSERT(t != NULL); 2774 t->command |= MVNETA_TX_CMD_L|MVNETA_TX_CMD_PADDING; 2775 2776 bus_dmamap_sync(sc->tx_dtag, tx->desc_map, 2777 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2778 2779 while (__predict_false(used > 255)) { 2780 ptxsu = MVNETA_PTXSU_NOWD(255); 2781 MVNETA_WRITE(sc, MVNETA_PTXSU(q), ptxsu); 2782 used -= 255; 2783 } 2784 if (__predict_true(used > 0)) { 2785 ptxsu = MVNETA_PTXSU_NOWD(used); 2786 MVNETA_WRITE(sc, MVNETA_PTXSU(q), ptxsu); 2787 } 2788 return (0); 2789 } 2790 2791 STATIC void 2792 mvneta_tx_set_csumflag(struct ifnet *ifp, 2793 struct mvneta_tx_desc *t, struct mbuf *m) 2794 { 2795 struct ether_header *eh; 2796 int csum_flags; 2797 uint32_t iphl, ipoff; 2798 struct ip *ip; 2799 2800 iphl = ipoff = 0; 2801 csum_flags = ifp->if_hwassist & m->m_pkthdr.csum_flags; 2802 eh = mtod(m, struct ether_header *); 2803 2804 switch (ntohs(eh->ether_type)) { 2805 case ETHERTYPE_IP: 2806 ipoff = ETHER_HDR_LEN; 2807 break; 2808 case ETHERTYPE_VLAN: 2809 ipoff = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 2810 break; 2811 default: 2812 csum_flags = 0; 2813 } 2814 2815 if (__predict_true(csum_flags & (CSUM_IP|CSUM_IP_TCP|CSUM_IP_UDP))) { 2816 ip = (struct ip *)(m->m_data + ipoff); 2817 iphl = ip->ip_hl<<2; 2818 t->command |= MVNETA_TX_CMD_L3_IP4; 2819 } else { 2820 t->command |= MVNETA_TX_CMD_L4_CHECKSUM_NONE; 2821 return; 2822 } 2823 2824 2825 /* L3 */ 2826 if (csum_flags & CSUM_IP) { 2827 t->command |= MVNETA_TX_CMD_IP4_CHECKSUM; 2828 } 2829 2830 /* L4 */ 2831 if (csum_flags & CSUM_IP_TCP) { 2832 t->command |= MVNETA_TX_CMD_L4_CHECKSUM_NOFRAG; 2833 t->command |= MVNETA_TX_CMD_L4_TCP; 2834 } else if (csum_flags & CSUM_IP_UDP) { 2835 t->command |= MVNETA_TX_CMD_L4_CHECKSUM_NOFRAG; 2836 t->command |= MVNETA_TX_CMD_L4_UDP; 2837 } else 2838 t->command |= MVNETA_TX_CMD_L4_CHECKSUM_NONE; 2839 2840 t->l4ichk = 0; 2841 t->command |= MVNETA_TX_CMD_IP_HEADER_LEN(iphl >> 2); 2842 t->command |= MVNETA_TX_CMD_L3_OFFSET(ipoff); 2843 } 2844 2845 STATIC void 2846 mvneta_tx_queue_complete(struct mvneta_softc *sc, int q) 2847 { 2848 struct mvneta_tx_ring *tx; 2849 struct mvneta_buf *txbuf; 2850 struct mvneta_tx_desc *t; 2851 uint32_t ptxs, ptxsu, ndesc; 2852 int i; 2853 2854 KASSERT_TX_MTX(sc, q); 2855 2856 tx = MVNETA_TX_RING(sc, q); 2857 if (__predict_false(tx->queue_status == MVNETA_QUEUE_DISABLED)) 2858 return; 2859 2860 ptxs = MVNETA_READ(sc, MVNETA_PTXS(q)); 2861 ndesc = MVNETA_PTXS_GET_TBC(ptxs); 2862 2863 if (__predict_false(ndesc == 0)) { 2864 if (tx->used == 0) 2865 tx->queue_status = MVNETA_QUEUE_IDLE; 2866 else if (tx->queue_status == MVNETA_QUEUE_WORKING && 2867 ((ticks - tx->watchdog_time) > MVNETA_WATCHDOG)) 2868 tx->queue_hung = TRUE; 2869 return; 2870 } 2871 2872 #ifdef MVNETA_KTR 2873 CTR3(KTR_SPARE2, "%s:%u tx_complete begin ndesc=%u", 2874 sc->ifp->if_xname, q, ndesc); 2875 #endif 2876 2877 bus_dmamap_sync(sc->tx_dtag, tx->desc_map, 2878 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2879 2880 for (i = 0; i < ndesc; i++) { 2881 t = &tx->desc[tx->dma]; 2882 #ifdef MVNETA_KTR 2883 if (t->flags & MVNETA_TX_F_ES) 2884 CTR3(KTR_SPARE2, "%s tx error queue %d desc %d", 2885 sc->ifp->if_xname, q, tx->dma); 2886 #endif 2887 txbuf = &tx->txbuf[tx->dma]; 2888 if (__predict_true(txbuf->m != NULL)) { 2889 DASSERT((t->command & MVNETA_TX_CMD_F) != 0); 2890 bus_dmamap_unload(sc->txmbuf_dtag, txbuf->dmap); 2891 m_freem(txbuf->m); 2892 txbuf->m = NULL; 2893 } 2894 else 2895 DASSERT((t->flags & MVNETA_TX_CMD_F) == 0); 2896 tx->dma = tx_counter_adv(tx->dma, 1); 2897 tx->used--; 2898 } 2899 DASSERT(tx->used >= 0); 2900 DASSERT(tx->used <= MVNETA_TX_RING_CNT); 2901 while (__predict_false(ndesc > 255)) { 2902 ptxsu = MVNETA_PTXSU_NORB(255); 2903 MVNETA_WRITE(sc, MVNETA_PTXSU(q), ptxsu); 2904 ndesc -= 255; 2905 } 2906 if (__predict_true(ndesc > 0)) { 2907 ptxsu = MVNETA_PTXSU_NORB(ndesc); 2908 MVNETA_WRITE(sc, MVNETA_PTXSU(q), ptxsu); 2909 } 2910 #ifdef MVNETA_KTR 2911 CTR5(KTR_SPARE2, "%s:%u tx_complete tx_cpu=%d tx_dma=%d tx_used=%d", 2912 sc->ifp->if_xname, q, tx->cpu, tx->dma, tx->used); 2913 #endif 2914 2915 tx->watchdog_time = ticks; 2916 2917 if (tx->used == 0) 2918 tx->queue_status = MVNETA_QUEUE_IDLE; 2919 } 2920 2921 /* 2922 * Do a final TX complete when TX is idle. 2923 */ 2924 STATIC void 2925 mvneta_tx_drain(struct mvneta_softc *sc) 2926 { 2927 struct mvneta_tx_ring *tx; 2928 int q; 2929 2930 /* 2931 * Handle trailing mbuf on TX queue. 2932 * Check is done lockess to avoid TX path contention. 2933 */ 2934 for (q = 0; q < MVNETA_TX_QNUM_MAX; q++) { 2935 tx = MVNETA_TX_RING(sc, q); 2936 if ((ticks - tx->watchdog_time) > MVNETA_WATCHDOG_TXCOMP && 2937 tx->used > 0) { 2938 mvneta_tx_lockq(sc, q); 2939 mvneta_tx_queue_complete(sc, q); 2940 mvneta_tx_unlockq(sc, q); 2941 } 2942 } 2943 } 2944 2945 /* 2946 * Rx Subroutines 2947 */ 2948 STATIC int 2949 mvneta_rx(struct mvneta_softc *sc, int q, int count) 2950 { 2951 uint32_t prxs, npkt; 2952 int more; 2953 2954 more = 0; 2955 mvneta_rx_lockq(sc, q); 2956 prxs = MVNETA_READ(sc, MVNETA_PRXS(q)); 2957 npkt = MVNETA_PRXS_GET_ODC(prxs); 2958 if (__predict_false(npkt == 0)) 2959 goto out; 2960 2961 if (count > 0 && npkt > count) { 2962 more = 1; 2963 npkt = count; 2964 } 2965 mvneta_rx_queue(sc, q, npkt); 2966 out: 2967 mvneta_rx_unlockq(sc, q); 2968 return more; 2969 } 2970 2971 /* 2972 * Helper routine for updating PRXSU register of a given queue. 2973 * Handles number of processed descriptors bigger than maximum acceptable value. 2974 */ 2975 STATIC __inline void 2976 mvneta_prxsu_update(struct mvneta_softc *sc, int q, int processed) 2977 { 2978 uint32_t prxsu; 2979 2980 while (__predict_false(processed > 255)) { 2981 prxsu = MVNETA_PRXSU_NOOFPROCESSEDDESCRIPTORS(255); 2982 MVNETA_WRITE(sc, MVNETA_PRXSU(q), prxsu); 2983 processed -= 255; 2984 } 2985 prxsu = MVNETA_PRXSU_NOOFPROCESSEDDESCRIPTORS(processed); 2986 MVNETA_WRITE(sc, MVNETA_PRXSU(q), prxsu); 2987 } 2988 2989 static __inline void 2990 mvneta_prefetch(void *p) 2991 { 2992 2993 __builtin_prefetch(p); 2994 } 2995 2996 STATIC void 2997 mvneta_rx_queue(struct mvneta_softc *sc, int q, int npkt) 2998 { 2999 struct ifnet *ifp; 3000 struct mvneta_rx_ring *rx; 3001 struct mvneta_rx_desc *r; 3002 struct mvneta_buf *rxbuf; 3003 struct mbuf *m; 3004 struct lro_ctrl *lro; 3005 struct lro_entry *queued; 3006 void *pktbuf; 3007 int i, pktlen, processed, ndma; 3008 3009 KASSERT_RX_MTX(sc, q); 3010 3011 ifp = sc->ifp; 3012 rx = MVNETA_RX_RING(sc, q); 3013 processed = 0; 3014 3015 if (__predict_false(rx->queue_status == MVNETA_QUEUE_DISABLED)) 3016 return; 3017 3018 bus_dmamap_sync(sc->rx_dtag, rx->desc_map, 3019 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3020 3021 for (i = 0; i < npkt; i++) { 3022 /* Prefetch next desc, rxbuf. */ 3023 ndma = rx_counter_adv(rx->dma, 1); 3024 mvneta_prefetch(&rx->desc[ndma]); 3025 mvneta_prefetch(&rx->rxbuf[ndma]); 3026 3027 /* get descriptor and packet */ 3028 r = &rx->desc[rx->dma]; 3029 rxbuf = &rx->rxbuf[rx->dma]; 3030 m = rxbuf->m; 3031 rxbuf->m = NULL; 3032 DASSERT(m != NULL); 3033 bus_dmamap_sync(sc->rxbuf_dtag, rxbuf->dmap, 3034 BUS_DMASYNC_POSTREAD); 3035 bus_dmamap_unload(sc->rxbuf_dtag, rxbuf->dmap); 3036 /* Prefetch mbuf header. */ 3037 mvneta_prefetch(m); 3038 3039 processed++; 3040 /* Drop desc with error status or not in a single buffer. */ 3041 DASSERT((r->status & (MVNETA_RX_F|MVNETA_RX_L)) == 3042 (MVNETA_RX_F|MVNETA_RX_L)); 3043 if (__predict_false((r->status & MVNETA_RX_ES) || 3044 (r->status & (MVNETA_RX_F|MVNETA_RX_L)) != 3045 (MVNETA_RX_F|MVNETA_RX_L))) 3046 goto rx_error; 3047 3048 /* 3049 * [ OFF | MH | PKT | CRC ] 3050 * bytecnt cover MH, PKT, CRC 3051 */ 3052 pktlen = r->bytecnt - ETHER_CRC_LEN - MVNETA_HWHEADER_SIZE; 3053 pktbuf = (uint8_t *)rx->rxbuf_virt_addr[rx->dma] + MVNETA_PACKET_OFFSET + 3054 MVNETA_HWHEADER_SIZE; 3055 3056 /* Prefetch mbuf data. */ 3057 mvneta_prefetch(pktbuf); 3058 3059 /* Write value to mbuf (avoid read). */ 3060 m->m_data = pktbuf; 3061 m->m_len = m->m_pkthdr.len = pktlen; 3062 m->m_pkthdr.rcvif = ifp; 3063 mvneta_rx_set_csumflag(ifp, r, m); 3064 3065 /* Increase rx_dma before releasing the lock. */ 3066 rx->dma = ndma; 3067 3068 if (__predict_false(rx->lro_enabled && 3069 ((r->status & MVNETA_RX_L3_IP) != 0) && 3070 ((r->status & MVNETA_RX_L4_MASK) == MVNETA_RX_L4_TCP) && 3071 (m->m_pkthdr.csum_flags & 3072 (CSUM_DATA_VALID | CSUM_PSEUDO_HDR)) == 3073 (CSUM_DATA_VALID | CSUM_PSEUDO_HDR))) { 3074 if (rx->lro.lro_cnt != 0) { 3075 if (tcp_lro_rx(&rx->lro, m, 0) == 0) 3076 goto rx_done; 3077 } 3078 } 3079 3080 mvneta_rx_unlockq(sc, q); 3081 (*ifp->if_input)(ifp, m); 3082 mvneta_rx_lockq(sc, q); 3083 /* 3084 * Check whether this queue has been disabled in the 3085 * meantime. If yes, then clear LRO and exit. 3086 */ 3087 if(__predict_false(rx->queue_status == MVNETA_QUEUE_DISABLED)) 3088 goto rx_lro; 3089 rx_done: 3090 /* Refresh receive ring to avoid stall and minimize jitter. */ 3091 if (processed >= MVNETA_RX_REFILL_COUNT) { 3092 mvneta_prxsu_update(sc, q, processed); 3093 mvneta_rx_queue_refill(sc, q); 3094 processed = 0; 3095 } 3096 continue; 3097 rx_error: 3098 m_freem(m); 3099 rx->dma = ndma; 3100 /* Refresh receive ring to avoid stall and minimize jitter. */ 3101 if (processed >= MVNETA_RX_REFILL_COUNT) { 3102 mvneta_prxsu_update(sc, q, processed); 3103 mvneta_rx_queue_refill(sc, q); 3104 processed = 0; 3105 } 3106 } 3107 #ifdef MVNETA_KTR 3108 CTR3(KTR_SPARE2, "%s:%u %u packets received", ifp->if_xname, q, npkt); 3109 #endif 3110 /* DMA status update */ 3111 mvneta_prxsu_update(sc, q, processed); 3112 /* Refill the rest of buffers if there are any to refill */ 3113 mvneta_rx_queue_refill(sc, q); 3114 3115 rx_lro: 3116 /* 3117 * Flush any outstanding LRO work 3118 */ 3119 lro = &rx->lro; 3120 while (__predict_false((queued = LIST_FIRST(&lro->lro_active)) != NULL)) { 3121 LIST_REMOVE(LIST_FIRST((&lro->lro_active)), next); 3122 tcp_lro_flush(lro, queued); 3123 } 3124 } 3125 3126 STATIC void 3127 mvneta_rx_buf_free(struct mvneta_softc *sc, struct mvneta_buf *rxbuf) 3128 { 3129 3130 bus_dmamap_unload(sc->rxbuf_dtag, rxbuf->dmap); 3131 /* This will remove all data at once */ 3132 m_freem(rxbuf->m); 3133 } 3134 3135 STATIC void 3136 mvneta_rx_queue_refill(struct mvneta_softc *sc, int q) 3137 { 3138 struct mvneta_rx_ring *rx; 3139 struct mvneta_rx_desc *r; 3140 struct mvneta_buf *rxbuf; 3141 bus_dma_segment_t segs; 3142 struct mbuf *m; 3143 uint32_t prxs, prxsu, ndesc; 3144 int npkt, refill, nsegs, error; 3145 3146 KASSERT_RX_MTX(sc, q); 3147 3148 rx = MVNETA_RX_RING(sc, q); 3149 prxs = MVNETA_READ(sc, MVNETA_PRXS(q)); 3150 ndesc = MVNETA_PRXS_GET_NODC(prxs) + MVNETA_PRXS_GET_ODC(prxs); 3151 refill = MVNETA_RX_RING_CNT - ndesc; 3152 #ifdef MVNETA_KTR 3153 CTR3(KTR_SPARE2, "%s:%u refill %u packets", sc->ifp->if_xname, q, 3154 refill); 3155 #endif 3156 if (__predict_false(refill <= 0)) 3157 return; 3158 3159 for (npkt = 0; npkt < refill; npkt++) { 3160 rxbuf = &rx->rxbuf[rx->cpu]; 3161 m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, sc->rx_frame_size); 3162 if (__predict_false(m == NULL)) { 3163 error = ENOBUFS; 3164 break; 3165 } 3166 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 3167 3168 error = bus_dmamap_load_mbuf_sg(sc->rxbuf_dtag, rxbuf->dmap, 3169 m, &segs, &nsegs, BUS_DMA_NOWAIT); 3170 if (__predict_false(error != 0 || nsegs != 1)) { 3171 KASSERT(1, ("Failed to load Rx mbuf DMA map")); 3172 m_freem(m); 3173 break; 3174 } 3175 3176 /* Add the packet to the ring */ 3177 rxbuf->m = m; 3178 r = &rx->desc[rx->cpu]; 3179 r->bufptr_pa = segs.ds_addr; 3180 rx->rxbuf_virt_addr[rx->cpu] = m->m_data; 3181 3182 rx->cpu = rx_counter_adv(rx->cpu, 1); 3183 } 3184 if (npkt == 0) { 3185 if (refill == MVNETA_RX_RING_CNT) 3186 rx->needs_refill = TRUE; 3187 return; 3188 } 3189 3190 rx->needs_refill = FALSE; 3191 bus_dmamap_sync(sc->rx_dtag, rx->desc_map, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3192 3193 while (__predict_false(npkt > 255)) { 3194 prxsu = MVNETA_PRXSU_NOOFNEWDESCRIPTORS(255); 3195 MVNETA_WRITE(sc, MVNETA_PRXSU(q), prxsu); 3196 npkt -= 255; 3197 } 3198 if (__predict_true(npkt > 0)) { 3199 prxsu = MVNETA_PRXSU_NOOFNEWDESCRIPTORS(npkt); 3200 MVNETA_WRITE(sc, MVNETA_PRXSU(q), prxsu); 3201 } 3202 } 3203 3204 STATIC __inline void 3205 mvneta_rx_set_csumflag(struct ifnet *ifp, 3206 struct mvneta_rx_desc *r, struct mbuf *m) 3207 { 3208 uint32_t csum_flags; 3209 3210 csum_flags = 0; 3211 if (__predict_false((r->status & 3212 (MVNETA_RX_IP_HEADER_OK|MVNETA_RX_L3_IP)) == 0)) 3213 return; /* not a IP packet */ 3214 3215 /* L3 */ 3216 if (__predict_true((r->status & MVNETA_RX_IP_HEADER_OK) == 3217 MVNETA_RX_IP_HEADER_OK)) 3218 csum_flags |= CSUM_L3_CALC|CSUM_L3_VALID; 3219 3220 if (__predict_true((r->status & (MVNETA_RX_IP_HEADER_OK|MVNETA_RX_L3_IP)) == 3221 (MVNETA_RX_IP_HEADER_OK|MVNETA_RX_L3_IP))) { 3222 /* L4 */ 3223 switch (r->status & MVNETA_RX_L4_MASK) { 3224 case MVNETA_RX_L4_TCP: 3225 case MVNETA_RX_L4_UDP: 3226 csum_flags |= CSUM_L4_CALC; 3227 if (__predict_true((r->status & 3228 MVNETA_RX_L4_CHECKSUM_OK) == MVNETA_RX_L4_CHECKSUM_OK)) { 3229 csum_flags |= CSUM_L4_VALID; 3230 m->m_pkthdr.csum_data = htons(0xffff); 3231 } 3232 break; 3233 case MVNETA_RX_L4_OTH: 3234 default: 3235 break; 3236 } 3237 } 3238 m->m_pkthdr.csum_flags = csum_flags; 3239 } 3240 3241 /* 3242 * MAC address filter 3243 */ 3244 STATIC void 3245 mvneta_filter_setup(struct mvneta_softc *sc) 3246 { 3247 struct ifnet *ifp; 3248 uint32_t dfut[MVNETA_NDFUT], dfsmt[MVNETA_NDFSMT], dfomt[MVNETA_NDFOMT]; 3249 uint32_t pxc; 3250 int i; 3251 3252 KASSERT_SC_MTX(sc); 3253 3254 memset(dfut, 0, sizeof(dfut)); 3255 memset(dfsmt, 0, sizeof(dfsmt)); 3256 memset(dfomt, 0, sizeof(dfomt)); 3257 3258 ifp = sc->ifp; 3259 ifp->if_flags |= IFF_ALLMULTI; 3260 if (ifp->if_flags & (IFF_ALLMULTI|IFF_PROMISC)) { 3261 for (i = 0; i < MVNETA_NDFSMT; i++) { 3262 dfsmt[i] = dfomt[i] = 3263 MVNETA_DF(0, MVNETA_DF_QUEUE(0) | MVNETA_DF_PASS) | 3264 MVNETA_DF(1, MVNETA_DF_QUEUE(0) | MVNETA_DF_PASS) | 3265 MVNETA_DF(2, MVNETA_DF_QUEUE(0) | MVNETA_DF_PASS) | 3266 MVNETA_DF(3, MVNETA_DF_QUEUE(0) | MVNETA_DF_PASS); 3267 } 3268 } 3269 3270 pxc = MVNETA_READ(sc, MVNETA_PXC); 3271 pxc &= ~(MVNETA_PXC_UPM | MVNETA_PXC_RXQ_MASK | MVNETA_PXC_RXQARP_MASK | 3272 MVNETA_PXC_TCPQ_MASK | MVNETA_PXC_UDPQ_MASK | MVNETA_PXC_BPDUQ_MASK); 3273 pxc |= MVNETA_PXC_RXQ(MVNETA_RX_QNUM_MAX-1); 3274 pxc |= MVNETA_PXC_RXQARP(MVNETA_RX_QNUM_MAX-1); 3275 pxc |= MVNETA_PXC_TCPQ(MVNETA_RX_QNUM_MAX-1); 3276 pxc |= MVNETA_PXC_UDPQ(MVNETA_RX_QNUM_MAX-1); 3277 pxc |= MVNETA_PXC_BPDUQ(MVNETA_RX_QNUM_MAX-1); 3278 pxc |= MVNETA_PXC_RB | MVNETA_PXC_RBIP | MVNETA_PXC_RBARP; 3279 if (ifp->if_flags & IFF_BROADCAST) { 3280 pxc &= ~(MVNETA_PXC_RB | MVNETA_PXC_RBIP | MVNETA_PXC_RBARP); 3281 } 3282 if (ifp->if_flags & IFF_PROMISC) { 3283 pxc |= MVNETA_PXC_UPM; 3284 } 3285 MVNETA_WRITE(sc, MVNETA_PXC, pxc); 3286 3287 /* Set Destination Address Filter Unicast Table */ 3288 if (ifp->if_flags & IFF_PROMISC) { 3289 /* pass all unicast addresses */ 3290 for (i = 0; i < MVNETA_NDFUT; i++) { 3291 dfut[i] = 3292 MVNETA_DF(0, MVNETA_DF_QUEUE(0) | MVNETA_DF_PASS) | 3293 MVNETA_DF(1, MVNETA_DF_QUEUE(0) | MVNETA_DF_PASS) | 3294 MVNETA_DF(2, MVNETA_DF_QUEUE(0) | MVNETA_DF_PASS) | 3295 MVNETA_DF(3, MVNETA_DF_QUEUE(0) | MVNETA_DF_PASS); 3296 } 3297 } else { 3298 i = sc->enaddr[5] & 0xf; /* last nibble */ 3299 dfut[i>>2] = MVNETA_DF(i&3, MVNETA_DF_QUEUE(0) | MVNETA_DF_PASS); 3300 } 3301 MVNETA_WRITE_REGION(sc, MVNETA_DFUT(0), dfut, MVNETA_NDFUT); 3302 3303 /* Set Destination Address Filter Multicast Tables */ 3304 MVNETA_WRITE_REGION(sc, MVNETA_DFSMT(0), dfsmt, MVNETA_NDFSMT); 3305 MVNETA_WRITE_REGION(sc, MVNETA_DFOMT(0), dfomt, MVNETA_NDFOMT); 3306 } 3307 3308 /* 3309 * sysctl(9) 3310 */ 3311 STATIC int 3312 sysctl_read_mib(SYSCTL_HANDLER_ARGS) 3313 { 3314 struct mvneta_sysctl_mib *arg; 3315 struct mvneta_softc *sc; 3316 uint64_t val; 3317 3318 arg = (struct mvneta_sysctl_mib *)arg1; 3319 if (arg == NULL) 3320 return (EINVAL); 3321 3322 sc = arg->sc; 3323 if (sc == NULL) 3324 return (EINVAL); 3325 if (arg->index < 0 || arg->index > MVNETA_PORTMIB_NOCOUNTER) 3326 return (EINVAL); 3327 3328 mvneta_sc_lock(sc); 3329 val = arg->counter; 3330 mvneta_sc_unlock(sc); 3331 return sysctl_handle_64(oidp, &val, 0, req); 3332 } 3333 3334 3335 STATIC int 3336 sysctl_clear_mib(SYSCTL_HANDLER_ARGS) 3337 { 3338 struct mvneta_softc *sc; 3339 int err, val; 3340 3341 val = 0; 3342 sc = (struct mvneta_softc *)arg1; 3343 if (sc == NULL) 3344 return (EINVAL); 3345 3346 err = sysctl_handle_int(oidp, &val, 0, req); 3347 if (err != 0) 3348 return (err); 3349 3350 if (val < 0 || val > 1) 3351 return (EINVAL); 3352 3353 if (val == 1) { 3354 mvneta_sc_lock(sc); 3355 mvneta_clear_mib(sc); 3356 mvneta_sc_unlock(sc); 3357 } 3358 3359 return (0); 3360 } 3361 3362 STATIC int 3363 sysctl_set_queue_rxthtime(SYSCTL_HANDLER_ARGS) 3364 { 3365 struct mvneta_sysctl_queue *arg; 3366 struct mvneta_rx_ring *rx; 3367 struct mvneta_softc *sc; 3368 uint32_t reg, time_mvtclk; 3369 int err, time_us; 3370 3371 rx = NULL; 3372 arg = (struct mvneta_sysctl_queue *)arg1; 3373 if (arg == NULL) 3374 return (EINVAL); 3375 if (arg->queue < 0 || arg->queue > MVNETA_RX_RING_CNT) 3376 return (EINVAL); 3377 if (arg->rxtx != MVNETA_SYSCTL_RX) 3378 return (EINVAL); 3379 3380 sc = arg->sc; 3381 if (sc == NULL) 3382 return (EINVAL); 3383 3384 /* read queue length */ 3385 mvneta_sc_lock(sc); 3386 mvneta_rx_lockq(sc, arg->queue); 3387 rx = MVNETA_RX_RING(sc, arg->queue); 3388 time_mvtclk = rx->queue_th_time; 3389 time_us = ((uint64_t)time_mvtclk * 1000ULL * 1000ULL) / mvneta_get_clk(); 3390 mvneta_rx_unlockq(sc, arg->queue); 3391 mvneta_sc_unlock(sc); 3392 3393 err = sysctl_handle_int(oidp, &time_us, 0, req); 3394 if (err != 0) 3395 return (err); 3396 3397 mvneta_sc_lock(sc); 3398 mvneta_rx_lockq(sc, arg->queue); 3399 3400 /* update queue length (0[sec] - 1[sec]) */ 3401 if (time_us < 0 || time_us > (1000 * 1000)) { 3402 mvneta_rx_unlockq(sc, arg->queue); 3403 mvneta_sc_unlock(sc); 3404 return (EINVAL); 3405 } 3406 time_mvtclk = 3407 (uint64_t)mvneta_get_clk() * (uint64_t)time_us / (1000ULL * 1000ULL); 3408 rx->queue_th_time = time_mvtclk; 3409 reg = MVNETA_PRXITTH_RITT(rx->queue_th_time); 3410 MVNETA_WRITE(sc, MVNETA_PRXITTH(arg->queue), reg); 3411 mvneta_rx_unlockq(sc, arg->queue); 3412 mvneta_sc_unlock(sc); 3413 3414 return (0); 3415 } 3416 3417 STATIC void 3418 sysctl_mvneta_init(struct mvneta_softc *sc) 3419 { 3420 struct sysctl_ctx_list *ctx; 3421 struct sysctl_oid_list *children; 3422 struct sysctl_oid_list *rxchildren; 3423 struct sysctl_oid_list *qchildren, *mchildren; 3424 struct sysctl_oid *tree; 3425 int i, q; 3426 struct mvneta_sysctl_queue *rxarg; 3427 #define MVNETA_SYSCTL_NAME(num) "queue" # num 3428 static const char *sysctl_queue_names[] = { 3429 MVNETA_SYSCTL_NAME(0), MVNETA_SYSCTL_NAME(1), 3430 MVNETA_SYSCTL_NAME(2), MVNETA_SYSCTL_NAME(3), 3431 MVNETA_SYSCTL_NAME(4), MVNETA_SYSCTL_NAME(5), 3432 MVNETA_SYSCTL_NAME(6), MVNETA_SYSCTL_NAME(7), 3433 }; 3434 #undef MVNETA_SYSCTL_NAME 3435 3436 #ifndef NO_SYSCTL_DESCR 3437 #define MVNETA_SYSCTL_DESCR(num) "configuration parameters for queue " # num 3438 static const char *sysctl_queue_descrs[] = { 3439 MVNETA_SYSCTL_DESCR(0), MVNETA_SYSCTL_DESCR(1), 3440 MVNETA_SYSCTL_DESCR(2), MVNETA_SYSCTL_DESCR(3), 3441 MVNETA_SYSCTL_DESCR(4), MVNETA_SYSCTL_DESCR(5), 3442 MVNETA_SYSCTL_DESCR(6), MVNETA_SYSCTL_DESCR(7), 3443 }; 3444 #undef MVNETA_SYSCTL_DESCR 3445 #endif 3446 3447 3448 ctx = device_get_sysctl_ctx(sc->dev); 3449 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)); 3450 3451 tree = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "rx", 3452 CTLFLAG_RD | CTLFLAG_MPSAFE, 0, "NETA RX"); 3453 rxchildren = SYSCTL_CHILDREN(tree); 3454 tree = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "mib", 3455 CTLFLAG_RD | CTLFLAG_MPSAFE, 0, "NETA MIB"); 3456 mchildren = SYSCTL_CHILDREN(tree); 3457 3458 3459 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "flow_control", 3460 CTLFLAG_RW, &sc->cf_fc, 0, "flow control"); 3461 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "lpi", 3462 CTLFLAG_RW, &sc->cf_lpi, 0, "Low Power Idle"); 3463 3464 /* 3465 * MIB access 3466 */ 3467 /* dev.mvneta.[unit].mib.<mibs> */ 3468 for (i = 0; i < MVNETA_PORTMIB_NOCOUNTER; i++) { 3469 struct mvneta_sysctl_mib *mib_arg = &sc->sysctl_mib[i]; 3470 3471 mib_arg->sc = sc; 3472 mib_arg->index = i; 3473 SYSCTL_ADD_PROC(ctx, mchildren, OID_AUTO, 3474 mvneta_mib_list[i].sysctl_name, 3475 CTLTYPE_U64 | CTLFLAG_RD | CTLFLAG_NEEDGIANT, 3476 (void *)mib_arg, 0, sysctl_read_mib, "I", 3477 mvneta_mib_list[i].desc); 3478 } 3479 SYSCTL_ADD_UQUAD(ctx, mchildren, OID_AUTO, "rx_discard", 3480 CTLFLAG_RD, &sc->counter_pdfc, "Port Rx Discard Frame Counter"); 3481 SYSCTL_ADD_UQUAD(ctx, mchildren, OID_AUTO, "overrun", 3482 CTLFLAG_RD, &sc->counter_pofc, "Port Overrun Frame Counter"); 3483 SYSCTL_ADD_UINT(ctx, mchildren, OID_AUTO, "watchdog", 3484 CTLFLAG_RD, &sc->counter_watchdog, 0, "TX Watchdog Counter"); 3485 3486 SYSCTL_ADD_PROC(ctx, mchildren, OID_AUTO, "reset", 3487 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 3488 (void *)sc, 0, sysctl_clear_mib, "I", "Reset MIB counters"); 3489 3490 for (q = 0; q < MVNETA_RX_QNUM_MAX; q++) { 3491 rxarg = &sc->sysctl_rx_queue[q]; 3492 3493 rxarg->sc = sc; 3494 rxarg->queue = q; 3495 rxarg->rxtx = MVNETA_SYSCTL_RX; 3496 3497 /* hw.mvneta.mvneta[unit].rx.[queue] */ 3498 tree = SYSCTL_ADD_NODE(ctx, rxchildren, OID_AUTO, 3499 sysctl_queue_names[q], CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 3500 sysctl_queue_descrs[q]); 3501 qchildren = SYSCTL_CHILDREN(tree); 3502 3503 /* hw.mvneta.mvneta[unit].rx.[queue].threshold_timer_us */ 3504 SYSCTL_ADD_PROC(ctx, qchildren, OID_AUTO, "threshold_timer_us", 3505 CTLTYPE_UINT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, rxarg, 0, 3506 sysctl_set_queue_rxthtime, "I", 3507 "interrupt coalescing threshold timer [us]"); 3508 } 3509 } 3510 3511 /* 3512 * MIB 3513 */ 3514 STATIC uint64_t 3515 mvneta_read_mib(struct mvneta_softc *sc, int index) 3516 { 3517 struct mvneta_mib_def *mib; 3518 uint64_t val; 3519 3520 mib = &mvneta_mib_list[index]; 3521 val = MVNETA_READ_MIB(sc, mib->regnum); 3522 if (mib->reg64) 3523 val |= (uint64_t)MVNETA_READ_MIB(sc, mib->regnum + 4) << 32; 3524 return (val); 3525 } 3526 3527 STATIC void 3528 mvneta_clear_mib(struct mvneta_softc *sc) 3529 { 3530 int i; 3531 3532 KASSERT_SC_MTX(sc); 3533 3534 for (i = 0; i < nitems(mvneta_mib_list); i++) { 3535 (void)mvneta_read_mib(sc, i); 3536 sc->sysctl_mib[i].counter = 0; 3537 } 3538 MVNETA_READ(sc, MVNETA_PDFC); 3539 sc->counter_pdfc = 0; 3540 MVNETA_READ(sc, MVNETA_POFC); 3541 sc->counter_pofc = 0; 3542 sc->counter_watchdog = 0; 3543 } 3544 3545 STATIC void 3546 mvneta_update_mib(struct mvneta_softc *sc) 3547 { 3548 struct mvneta_tx_ring *tx; 3549 int i; 3550 uint64_t val; 3551 uint32_t reg; 3552 3553 for (i = 0; i < nitems(mvneta_mib_list); i++) { 3554 3555 val = mvneta_read_mib(sc, i); 3556 if (val == 0) 3557 continue; 3558 3559 sc->sysctl_mib[i].counter += val; 3560 switch (mvneta_mib_list[i].regnum) { 3561 case MVNETA_MIB_RX_GOOD_OCT: 3562 if_inc_counter(sc->ifp, IFCOUNTER_IBYTES, val); 3563 break; 3564 case MVNETA_MIB_RX_BAD_FRAME: 3565 if_inc_counter(sc->ifp, IFCOUNTER_IERRORS, val); 3566 break; 3567 case MVNETA_MIB_RX_GOOD_FRAME: 3568 if_inc_counter(sc->ifp, IFCOUNTER_IPACKETS, val); 3569 break; 3570 case MVNETA_MIB_RX_MCAST_FRAME: 3571 if_inc_counter(sc->ifp, IFCOUNTER_IMCASTS, val); 3572 break; 3573 case MVNETA_MIB_TX_GOOD_OCT: 3574 if_inc_counter(sc->ifp, IFCOUNTER_OBYTES, val); 3575 break; 3576 case MVNETA_MIB_TX_GOOD_FRAME: 3577 if_inc_counter(sc->ifp, IFCOUNTER_OPACKETS, val); 3578 break; 3579 case MVNETA_MIB_TX_MCAST_FRAME: 3580 if_inc_counter(sc->ifp, IFCOUNTER_OMCASTS, val); 3581 break; 3582 case MVNETA_MIB_MAC_COL: 3583 if_inc_counter(sc->ifp, IFCOUNTER_COLLISIONS, val); 3584 break; 3585 case MVNETA_MIB_TX_MAC_TRNS_ERR: 3586 case MVNETA_MIB_TX_EXCES_COL: 3587 case MVNETA_MIB_MAC_LATE_COL: 3588 if_inc_counter(sc->ifp, IFCOUNTER_OERRORS, val); 3589 break; 3590 } 3591 } 3592 3593 reg = MVNETA_READ(sc, MVNETA_PDFC); 3594 sc->counter_pdfc += reg; 3595 if_inc_counter(sc->ifp, IFCOUNTER_IQDROPS, reg); 3596 reg = MVNETA_READ(sc, MVNETA_POFC); 3597 sc->counter_pofc += reg; 3598 if_inc_counter(sc->ifp, IFCOUNTER_IQDROPS, reg); 3599 3600 /* TX watchdog. */ 3601 if (sc->counter_watchdog_mib > 0) { 3602 if_inc_counter(sc->ifp, IFCOUNTER_OERRORS, sc->counter_watchdog_mib); 3603 sc->counter_watchdog_mib = 0; 3604 } 3605 /* 3606 * TX driver errors: 3607 * We do not take queue locks to not disrupt TX path. 3608 * We may only miss one drv error which will be fixed at 3609 * next mib update. We may also clear counter when TX path 3610 * is incrementing it but we only do it if counter was not zero 3611 * thus we may only loose one error. 3612 */ 3613 for (i = 0; i < MVNETA_TX_QNUM_MAX; i++) { 3614 tx = MVNETA_TX_RING(sc, i); 3615 3616 if (tx->drv_error > 0) { 3617 if_inc_counter(sc->ifp, IFCOUNTER_OERRORS, tx->drv_error); 3618 tx->drv_error = 0; 3619 } 3620 } 3621 } 3622