1 /* 2 * Copyright (c) 2017 Stormshield. 3 * Copyright (c) 2017 Semihalf. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 24 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include "opt_platform.h" 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/endian.h> 35 #include <sys/mbuf.h> 36 #include <sys/lock.h> 37 #include <sys/mutex.h> 38 #include <sys/kernel.h> 39 #include <sys/module.h> 40 #include <sys/socket.h> 41 #include <sys/sysctl.h> 42 #include <sys/smp.h> 43 #include <sys/taskqueue.h> 44 #ifdef MVNETA_KTR 45 #include <sys/ktr.h> 46 #endif 47 48 #include <net/ethernet.h> 49 #include <net/bpf.h> 50 #include <net/if.h> 51 #include <net/if_arp.h> 52 #include <net/if_dl.h> 53 #include <net/if_media.h> 54 #include <net/if_types.h> 55 #include <net/if_vlan_var.h> 56 57 #include <netinet/in_systm.h> 58 #include <netinet/in.h> 59 #include <netinet/ip.h> 60 #include <netinet/tcp_lro.h> 61 62 #include <sys/sockio.h> 63 #include <sys/bus.h> 64 #include <machine/bus.h> 65 #include <sys/rman.h> 66 #include <machine/resource.h> 67 68 #include <dev/mii/mii.h> 69 #include <dev/mii/miivar.h> 70 71 #include <dev/ofw/openfirm.h> 72 #include <dev/ofw/ofw_bus.h> 73 #include <dev/ofw/ofw_bus_subr.h> 74 75 #include <dev/mdio/mdio.h> 76 77 #include <arm/mv/mvvar.h> 78 79 #if !defined(__aarch64__) 80 #include <arm/mv/mvreg.h> 81 #include <arm/mv/mvwin.h> 82 #endif 83 84 #include "if_mvnetareg.h" 85 #include "if_mvnetavar.h" 86 87 #include "miibus_if.h" 88 #include "mdio_if.h" 89 90 #ifdef MVNETA_DEBUG 91 #define STATIC /* nothing */ 92 #else 93 #define STATIC static 94 #endif 95 96 #define DASSERT(x) KASSERT((x), (#x)) 97 98 #define A3700_TCLK_250MHZ 250000000 99 100 /* Device Register Initialization */ 101 STATIC int mvneta_initreg(struct ifnet *); 102 103 /* Descriptor Ring Control for each of queues */ 104 STATIC int mvneta_ring_alloc_rx_queue(struct mvneta_softc *, int); 105 STATIC int mvneta_ring_alloc_tx_queue(struct mvneta_softc *, int); 106 STATIC void mvneta_ring_dealloc_rx_queue(struct mvneta_softc *, int); 107 STATIC void mvneta_ring_dealloc_tx_queue(struct mvneta_softc *, int); 108 STATIC int mvneta_ring_init_rx_queue(struct mvneta_softc *, int); 109 STATIC int mvneta_ring_init_tx_queue(struct mvneta_softc *, int); 110 STATIC void mvneta_ring_flush_rx_queue(struct mvneta_softc *, int); 111 STATIC void mvneta_ring_flush_tx_queue(struct mvneta_softc *, int); 112 STATIC void mvneta_dmamap_cb(void *, bus_dma_segment_t *, int, int); 113 STATIC int mvneta_dma_create(struct mvneta_softc *); 114 115 /* Rx/Tx Queue Control */ 116 STATIC int mvneta_rx_queue_init(struct ifnet *, int); 117 STATIC int mvneta_tx_queue_init(struct ifnet *, int); 118 STATIC int mvneta_rx_queue_enable(struct ifnet *, int); 119 STATIC int mvneta_tx_queue_enable(struct ifnet *, int); 120 STATIC void mvneta_rx_lockq(struct mvneta_softc *, int); 121 STATIC void mvneta_rx_unlockq(struct mvneta_softc *, int); 122 STATIC void mvneta_tx_lockq(struct mvneta_softc *, int); 123 STATIC void mvneta_tx_unlockq(struct mvneta_softc *, int); 124 125 /* Interrupt Handlers */ 126 STATIC void mvneta_disable_intr(struct mvneta_softc *); 127 STATIC void mvneta_enable_intr(struct mvneta_softc *); 128 STATIC void mvneta_rxtxth_intr(void *); 129 STATIC int mvneta_misc_intr(struct mvneta_softc *); 130 STATIC void mvneta_tick(void *); 131 /* struct ifnet and mii callbacks*/ 132 STATIC int mvneta_xmitfast_locked(struct mvneta_softc *, int, struct mbuf **); 133 STATIC int mvneta_xmit_locked(struct mvneta_softc *, int); 134 #ifdef MVNETA_MULTIQUEUE 135 STATIC int mvneta_transmit(struct ifnet *, struct mbuf *); 136 #else /* !MVNETA_MULTIQUEUE */ 137 STATIC void mvneta_start(struct ifnet *); 138 #endif 139 STATIC void mvneta_qflush(struct ifnet *); 140 STATIC void mvneta_tx_task(void *, int); 141 STATIC int mvneta_ioctl(struct ifnet *, u_long, caddr_t); 142 STATIC void mvneta_init(void *); 143 STATIC void mvneta_init_locked(void *); 144 STATIC void mvneta_stop(struct mvneta_softc *); 145 STATIC void mvneta_stop_locked(struct mvneta_softc *); 146 STATIC int mvneta_mediachange(struct ifnet *); 147 STATIC void mvneta_mediastatus(struct ifnet *, struct ifmediareq *); 148 STATIC void mvneta_portup(struct mvneta_softc *); 149 STATIC void mvneta_portdown(struct mvneta_softc *); 150 151 /* Link State Notify */ 152 STATIC void mvneta_update_autoneg(struct mvneta_softc *, int); 153 STATIC int mvneta_update_media(struct mvneta_softc *, int); 154 STATIC void mvneta_adjust_link(struct mvneta_softc *); 155 STATIC void mvneta_update_eee(struct mvneta_softc *); 156 STATIC void mvneta_update_fc(struct mvneta_softc *); 157 STATIC void mvneta_link_isr(struct mvneta_softc *); 158 STATIC void mvneta_linkupdate(struct mvneta_softc *, boolean_t); 159 STATIC void mvneta_linkup(struct mvneta_softc *); 160 STATIC void mvneta_linkdown(struct mvneta_softc *); 161 STATIC void mvneta_linkreset(struct mvneta_softc *); 162 163 /* Tx Subroutines */ 164 STATIC int mvneta_tx_queue(struct mvneta_softc *, struct mbuf **, int); 165 STATIC void mvneta_tx_set_csumflag(struct ifnet *, 166 struct mvneta_tx_desc *, struct mbuf *); 167 STATIC void mvneta_tx_queue_complete(struct mvneta_softc *, int); 168 STATIC void mvneta_tx_drain(struct mvneta_softc *); 169 170 /* Rx Subroutines */ 171 STATIC int mvneta_rx(struct mvneta_softc *, int, int); 172 STATIC void mvneta_rx_queue(struct mvneta_softc *, int, int); 173 STATIC void mvneta_rx_queue_refill(struct mvneta_softc *, int); 174 STATIC void mvneta_rx_set_csumflag(struct ifnet *, 175 struct mvneta_rx_desc *, struct mbuf *); 176 STATIC void mvneta_rx_buf_free(struct mvneta_softc *, struct mvneta_buf *); 177 178 /* MAC address filter */ 179 STATIC void mvneta_filter_setup(struct mvneta_softc *); 180 181 /* sysctl(9) */ 182 STATIC int sysctl_read_mib(SYSCTL_HANDLER_ARGS); 183 STATIC int sysctl_clear_mib(SYSCTL_HANDLER_ARGS); 184 STATIC int sysctl_set_queue_rxthtime(SYSCTL_HANDLER_ARGS); 185 STATIC void sysctl_mvneta_init(struct mvneta_softc *); 186 187 /* MIB */ 188 STATIC void mvneta_clear_mib(struct mvneta_softc *); 189 STATIC void mvneta_update_mib(struct mvneta_softc *); 190 191 /* Switch */ 192 STATIC boolean_t mvneta_find_ethernet_prop_switch(phandle_t, phandle_t); 193 STATIC boolean_t mvneta_has_switch(device_t); 194 195 #define mvneta_sc_lock(sc) mtx_lock(&sc->mtx) 196 #define mvneta_sc_unlock(sc) mtx_unlock(&sc->mtx) 197 198 STATIC struct mtx mii_mutex; 199 STATIC int mii_init = 0; 200 201 /* Device */ 202 STATIC int mvneta_detach(device_t); 203 /* MII */ 204 STATIC int mvneta_miibus_readreg(device_t, int, int); 205 STATIC int mvneta_miibus_writereg(device_t, int, int, int); 206 207 /* Clock */ 208 STATIC uint32_t mvneta_get_clk(void); 209 210 static device_method_t mvneta_methods[] = { 211 /* Device interface */ 212 DEVMETHOD(device_detach, mvneta_detach), 213 /* MII interface */ 214 DEVMETHOD(miibus_readreg, mvneta_miibus_readreg), 215 DEVMETHOD(miibus_writereg, mvneta_miibus_writereg), 216 /* MDIO interface */ 217 DEVMETHOD(mdio_readreg, mvneta_miibus_readreg), 218 DEVMETHOD(mdio_writereg, mvneta_miibus_writereg), 219 220 /* End */ 221 DEVMETHOD_END 222 }; 223 224 DEFINE_CLASS_0(mvneta, mvneta_driver, mvneta_methods, sizeof(struct mvneta_softc)); 225 226 DRIVER_MODULE(miibus, mvneta, miibus_driver, miibus_devclass, 0, 0); 227 DRIVER_MODULE(mdio, mvneta, mdio_driver, mdio_devclass, 0, 0); 228 MODULE_DEPEND(mvneta, mdio, 1, 1, 1); 229 MODULE_DEPEND(mvneta, ether, 1, 1, 1); 230 MODULE_DEPEND(mvneta, miibus, 1, 1, 1); 231 MODULE_DEPEND(mvneta, mvxpbm, 1, 1, 1); 232 233 /* 234 * List of MIB register and names 235 */ 236 enum mvneta_mib_idx 237 { 238 MVNETA_MIB_RX_GOOD_OCT_IDX, 239 MVNETA_MIB_RX_BAD_OCT_IDX, 240 MVNETA_MIB_TX_MAC_TRNS_ERR_IDX, 241 MVNETA_MIB_RX_GOOD_FRAME_IDX, 242 MVNETA_MIB_RX_BAD_FRAME_IDX, 243 MVNETA_MIB_RX_BCAST_FRAME_IDX, 244 MVNETA_MIB_RX_MCAST_FRAME_IDX, 245 MVNETA_MIB_RX_FRAME64_OCT_IDX, 246 MVNETA_MIB_RX_FRAME127_OCT_IDX, 247 MVNETA_MIB_RX_FRAME255_OCT_IDX, 248 MVNETA_MIB_RX_FRAME511_OCT_IDX, 249 MVNETA_MIB_RX_FRAME1023_OCT_IDX, 250 MVNETA_MIB_RX_FRAMEMAX_OCT_IDX, 251 MVNETA_MIB_TX_GOOD_OCT_IDX, 252 MVNETA_MIB_TX_GOOD_FRAME_IDX, 253 MVNETA_MIB_TX_EXCES_COL_IDX, 254 MVNETA_MIB_TX_MCAST_FRAME_IDX, 255 MVNETA_MIB_TX_BCAST_FRAME_IDX, 256 MVNETA_MIB_TX_MAC_CTL_ERR_IDX, 257 MVNETA_MIB_FC_SENT_IDX, 258 MVNETA_MIB_FC_GOOD_IDX, 259 MVNETA_MIB_FC_BAD_IDX, 260 MVNETA_MIB_PKT_UNDERSIZE_IDX, 261 MVNETA_MIB_PKT_FRAGMENT_IDX, 262 MVNETA_MIB_PKT_OVERSIZE_IDX, 263 MVNETA_MIB_PKT_JABBER_IDX, 264 MVNETA_MIB_MAC_RX_ERR_IDX, 265 MVNETA_MIB_MAC_CRC_ERR_IDX, 266 MVNETA_MIB_MAC_COL_IDX, 267 MVNETA_MIB_MAC_LATE_COL_IDX, 268 }; 269 270 STATIC struct mvneta_mib_def { 271 uint32_t regnum; 272 int reg64; 273 const char *sysctl_name; 274 const char *desc; 275 } mvneta_mib_list[] = { 276 [MVNETA_MIB_RX_GOOD_OCT_IDX] = {MVNETA_MIB_RX_GOOD_OCT, 1, 277 "rx_good_oct", "Good Octets Rx"}, 278 [MVNETA_MIB_RX_BAD_OCT_IDX] = {MVNETA_MIB_RX_BAD_OCT, 0, 279 "rx_bad_oct", "Bad Octets Rx"}, 280 [MVNETA_MIB_TX_MAC_TRNS_ERR_IDX] = {MVNETA_MIB_TX_MAC_TRNS_ERR, 0, 281 "tx_mac_err", "MAC Transmit Error"}, 282 [MVNETA_MIB_RX_GOOD_FRAME_IDX] = {MVNETA_MIB_RX_GOOD_FRAME, 0, 283 "rx_good_frame", "Good Frames Rx"}, 284 [MVNETA_MIB_RX_BAD_FRAME_IDX] = {MVNETA_MIB_RX_BAD_FRAME, 0, 285 "rx_bad_frame", "Bad Frames Rx"}, 286 [MVNETA_MIB_RX_BCAST_FRAME_IDX] = {MVNETA_MIB_RX_BCAST_FRAME, 0, 287 "rx_bcast_frame", "Broadcast Frames Rx"}, 288 [MVNETA_MIB_RX_MCAST_FRAME_IDX] = {MVNETA_MIB_RX_MCAST_FRAME, 0, 289 "rx_mcast_frame", "Multicast Frames Rx"}, 290 [MVNETA_MIB_RX_FRAME64_OCT_IDX] = {MVNETA_MIB_RX_FRAME64_OCT, 0, 291 "rx_frame_1_64", "Frame Size 1 - 64"}, 292 [MVNETA_MIB_RX_FRAME127_OCT_IDX] = {MVNETA_MIB_RX_FRAME127_OCT, 0, 293 "rx_frame_65_127", "Frame Size 65 - 127"}, 294 [MVNETA_MIB_RX_FRAME255_OCT_IDX] = {MVNETA_MIB_RX_FRAME255_OCT, 0, 295 "rx_frame_128_255", "Frame Size 128 - 255"}, 296 [MVNETA_MIB_RX_FRAME511_OCT_IDX] = {MVNETA_MIB_RX_FRAME511_OCT, 0, 297 "rx_frame_256_511", "Frame Size 256 - 511"}, 298 [MVNETA_MIB_RX_FRAME1023_OCT_IDX] = {MVNETA_MIB_RX_FRAME1023_OCT, 0, 299 "rx_frame_512_1023", "Frame Size 512 - 1023"}, 300 [MVNETA_MIB_RX_FRAMEMAX_OCT_IDX] = {MVNETA_MIB_RX_FRAMEMAX_OCT, 0, 301 "rx_fame_1024_max", "Frame Size 1024 - Max"}, 302 [MVNETA_MIB_TX_GOOD_OCT_IDX] = {MVNETA_MIB_TX_GOOD_OCT, 1, 303 "tx_good_oct", "Good Octets Tx"}, 304 [MVNETA_MIB_TX_GOOD_FRAME_IDX] = {MVNETA_MIB_TX_GOOD_FRAME, 0, 305 "tx_good_frame", "Good Frames Tx"}, 306 [MVNETA_MIB_TX_EXCES_COL_IDX] = {MVNETA_MIB_TX_EXCES_COL, 0, 307 "tx_exces_collision", "Excessive Collision"}, 308 [MVNETA_MIB_TX_MCAST_FRAME_IDX] = {MVNETA_MIB_TX_MCAST_FRAME, 0, 309 "tx_mcast_frame", "Multicast Frames Tx"}, 310 [MVNETA_MIB_TX_BCAST_FRAME_IDX] = {MVNETA_MIB_TX_BCAST_FRAME, 0, 311 "tx_bcast_frame", "Broadcast Frames Tx"}, 312 [MVNETA_MIB_TX_MAC_CTL_ERR_IDX] = {MVNETA_MIB_TX_MAC_CTL_ERR, 0, 313 "tx_mac_ctl_err", "Unknown MAC Control"}, 314 [MVNETA_MIB_FC_SENT_IDX] = {MVNETA_MIB_FC_SENT, 0, 315 "fc_tx", "Flow Control Tx"}, 316 [MVNETA_MIB_FC_GOOD_IDX] = {MVNETA_MIB_FC_GOOD, 0, 317 "fc_rx_good", "Good Flow Control Rx"}, 318 [MVNETA_MIB_FC_BAD_IDX] = {MVNETA_MIB_FC_BAD, 0, 319 "fc_rx_bad", "Bad Flow Control Rx"}, 320 [MVNETA_MIB_PKT_UNDERSIZE_IDX] = {MVNETA_MIB_PKT_UNDERSIZE, 0, 321 "pkt_undersize", "Undersized Packets Rx"}, 322 [MVNETA_MIB_PKT_FRAGMENT_IDX] = {MVNETA_MIB_PKT_FRAGMENT, 0, 323 "pkt_fragment", "Fragmented Packets Rx"}, 324 [MVNETA_MIB_PKT_OVERSIZE_IDX] = {MVNETA_MIB_PKT_OVERSIZE, 0, 325 "pkt_oversize", "Oversized Packets Rx"}, 326 [MVNETA_MIB_PKT_JABBER_IDX] = {MVNETA_MIB_PKT_JABBER, 0, 327 "pkt_jabber", "Jabber Packets Rx"}, 328 [MVNETA_MIB_MAC_RX_ERR_IDX] = {MVNETA_MIB_MAC_RX_ERR, 0, 329 "mac_rx_err", "MAC Rx Errors"}, 330 [MVNETA_MIB_MAC_CRC_ERR_IDX] = {MVNETA_MIB_MAC_CRC_ERR, 0, 331 "mac_crc_err", "MAC CRC Errors"}, 332 [MVNETA_MIB_MAC_COL_IDX] = {MVNETA_MIB_MAC_COL, 0, 333 "mac_collision", "MAC Collision"}, 334 [MVNETA_MIB_MAC_LATE_COL_IDX] = {MVNETA_MIB_MAC_LATE_COL, 0, 335 "mac_late_collision", "MAC Late Collision"}, 336 }; 337 338 static struct resource_spec res_spec[] = { 339 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 340 { SYS_RES_IRQ, 0, RF_ACTIVE }, 341 { -1, 0} 342 }; 343 344 static struct { 345 driver_intr_t *handler; 346 char * description; 347 } mvneta_intrs[] = { 348 { mvneta_rxtxth_intr, "MVNETA aggregated interrupt" }, 349 }; 350 351 STATIC uint32_t 352 mvneta_get_clk() 353 { 354 #if defined(__aarch64__) 355 return (A3700_TCLK_250MHZ); 356 #else 357 return (get_tclk()); 358 #endif 359 } 360 361 static int 362 mvneta_set_mac_address(struct mvneta_softc *sc, uint8_t *addr) 363 { 364 unsigned int mac_h; 365 unsigned int mac_l; 366 367 mac_l = (addr[4] << 8) | (addr[5]); 368 mac_h = (addr[0] << 24) | (addr[1] << 16) | 369 (addr[2] << 8) | (addr[3] << 0); 370 371 MVNETA_WRITE(sc, MVNETA_MACAL, mac_l); 372 MVNETA_WRITE(sc, MVNETA_MACAH, mac_h); 373 return (0); 374 } 375 376 static int 377 mvneta_get_mac_address(struct mvneta_softc *sc, uint8_t *addr) 378 { 379 uint32_t mac_l, mac_h; 380 381 #ifdef FDT 382 if (mvneta_fdt_mac_address(sc, addr) == 0) 383 return (0); 384 #endif 385 /* 386 * Fall back -- use the currently programmed address. 387 */ 388 mac_l = MVNETA_READ(sc, MVNETA_MACAL); 389 mac_h = MVNETA_READ(sc, MVNETA_MACAH); 390 if (mac_l == 0 && mac_h == 0) { 391 /* 392 * Generate pseudo-random MAC. 393 * Set lower part to random number | unit number. 394 */ 395 mac_l = arc4random() & ~0xff; 396 mac_l |= device_get_unit(sc->dev) & 0xff; 397 mac_h = arc4random(); 398 mac_h &= ~(3 << 24); /* Clear multicast and LAA bits */ 399 if (bootverbose) { 400 device_printf(sc->dev, 401 "Could not acquire MAC address. " 402 "Using randomized one.\n"); 403 } 404 } 405 406 addr[0] = (mac_h & 0xff000000) >> 24; 407 addr[1] = (mac_h & 0x00ff0000) >> 16; 408 addr[2] = (mac_h & 0x0000ff00) >> 8; 409 addr[3] = (mac_h & 0x000000ff); 410 addr[4] = (mac_l & 0x0000ff00) >> 8; 411 addr[5] = (mac_l & 0x000000ff); 412 return (0); 413 } 414 415 STATIC boolean_t 416 mvneta_find_ethernet_prop_switch(phandle_t ethernet, phandle_t node) 417 { 418 boolean_t ret; 419 phandle_t child, switch_eth_handle, switch_eth; 420 421 for (child = OF_child(node); child != 0; child = OF_peer(child)) { 422 if (OF_getencprop(child, "ethernet", (void*)&switch_eth_handle, 423 sizeof(switch_eth_handle)) > 0) { 424 if (switch_eth_handle > 0) { 425 switch_eth = OF_node_from_xref( 426 switch_eth_handle); 427 428 if (switch_eth == ethernet) 429 return (true); 430 } 431 } 432 433 ret = mvneta_find_ethernet_prop_switch(ethernet, child); 434 if (ret != 0) 435 return (ret); 436 } 437 438 return (false); 439 } 440 441 STATIC boolean_t 442 mvneta_has_switch(device_t self) 443 { 444 phandle_t node; 445 446 node = ofw_bus_get_node(self); 447 448 return mvneta_find_ethernet_prop_switch(node, OF_finddevice("/")); 449 } 450 451 STATIC int 452 mvneta_dma_create(struct mvneta_softc *sc) 453 { 454 size_t maxsize, maxsegsz; 455 size_t q; 456 int error; 457 458 /* 459 * Create Tx DMA 460 */ 461 maxsize = maxsegsz = sizeof(struct mvneta_tx_desc) * MVNETA_TX_RING_CNT; 462 463 error = bus_dma_tag_create( 464 bus_get_dma_tag(sc->dev), /* parent */ 465 16, 0, /* alignment, boundary */ 466 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 467 BUS_SPACE_MAXADDR, /* highaddr */ 468 NULL, NULL, /* filtfunc, filtfuncarg */ 469 maxsize, /* maxsize */ 470 1, /* nsegments */ 471 maxsegsz, /* maxsegsz */ 472 0, /* flags */ 473 NULL, NULL, /* lockfunc, lockfuncarg */ 474 &sc->tx_dtag); /* dmat */ 475 if (error != 0) { 476 device_printf(sc->dev, 477 "Failed to create DMA tag for Tx descriptors.\n"); 478 goto fail; 479 } 480 error = bus_dma_tag_create( 481 bus_get_dma_tag(sc->dev), /* parent */ 482 1, 0, /* alignment, boundary */ 483 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 484 BUS_SPACE_MAXADDR, /* highaddr */ 485 NULL, NULL, /* filtfunc, filtfuncarg */ 486 MVNETA_PACKET_SIZE, /* maxsize */ 487 MVNETA_TX_SEGLIMIT, /* nsegments */ 488 MVNETA_PACKET_SIZE, /* maxsegsz */ 489 BUS_DMA_ALLOCNOW, /* flags */ 490 NULL, NULL, /* lockfunc, lockfuncarg */ 491 &sc->txmbuf_dtag); 492 if (error != 0) { 493 device_printf(sc->dev, 494 "Failed to create DMA tag for Tx mbufs.\n"); 495 goto fail; 496 } 497 498 for (q = 0; q < MVNETA_TX_QNUM_MAX; q++) { 499 error = mvneta_ring_alloc_tx_queue(sc, q); 500 if (error != 0) { 501 device_printf(sc->dev, 502 "Failed to allocate DMA safe memory for TxQ: %zu\n", q); 503 goto fail; 504 } 505 } 506 507 /* 508 * Create Rx DMA. 509 */ 510 /* Create tag for Rx descripors */ 511 error = bus_dma_tag_create( 512 bus_get_dma_tag(sc->dev), /* parent */ 513 32, 0, /* alignment, boundary */ 514 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 515 BUS_SPACE_MAXADDR, /* highaddr */ 516 NULL, NULL, /* filtfunc, filtfuncarg */ 517 sizeof(struct mvneta_rx_desc) * MVNETA_RX_RING_CNT, /* maxsize */ 518 1, /* nsegments */ 519 sizeof(struct mvneta_rx_desc) * MVNETA_RX_RING_CNT, /* maxsegsz */ 520 0, /* flags */ 521 NULL, NULL, /* lockfunc, lockfuncarg */ 522 &sc->rx_dtag); /* dmat */ 523 if (error != 0) { 524 device_printf(sc->dev, 525 "Failed to create DMA tag for Rx descriptors.\n"); 526 goto fail; 527 } 528 529 /* Create tag for Rx buffers */ 530 error = bus_dma_tag_create( 531 bus_get_dma_tag(sc->dev), /* parent */ 532 32, 0, /* alignment, boundary */ 533 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 534 BUS_SPACE_MAXADDR, /* highaddr */ 535 NULL, NULL, /* filtfunc, filtfuncarg */ 536 MVNETA_PACKET_SIZE, 1, /* maxsize, nsegments */ 537 MVNETA_PACKET_SIZE, /* maxsegsz */ 538 0, /* flags */ 539 NULL, NULL, /* lockfunc, lockfuncarg */ 540 &sc->rxbuf_dtag); /* dmat */ 541 if (error != 0) { 542 device_printf(sc->dev, 543 "Failed to create DMA tag for Rx buffers.\n"); 544 goto fail; 545 } 546 547 for (q = 0; q < MVNETA_RX_QNUM_MAX; q++) { 548 if (mvneta_ring_alloc_rx_queue(sc, q) != 0) { 549 device_printf(sc->dev, 550 "Failed to allocate DMA safe memory for RxQ: %zu\n", q); 551 goto fail; 552 } 553 } 554 555 return (0); 556 fail: 557 mvneta_detach(sc->dev); 558 559 return (error); 560 } 561 562 /* ARGSUSED */ 563 int 564 mvneta_attach(device_t self) 565 { 566 struct mvneta_softc *sc; 567 struct ifnet *ifp; 568 device_t child; 569 int ifm_target; 570 int q, error; 571 #if !defined(__aarch64__) 572 uint32_t reg; 573 #endif 574 575 sc = device_get_softc(self); 576 sc->dev = self; 577 578 mtx_init(&sc->mtx, "mvneta_sc", NULL, MTX_DEF); 579 580 error = bus_alloc_resources(self, res_spec, sc->res); 581 if (error) { 582 device_printf(self, "could not allocate resources\n"); 583 return (ENXIO); 584 } 585 586 sc->version = MVNETA_READ(sc, MVNETA_PV); 587 device_printf(self, "version is %x\n", sc->version); 588 callout_init(&sc->tick_ch, 0); 589 590 /* 591 * make sure DMA engines are in reset state 592 */ 593 MVNETA_WRITE(sc, MVNETA_PRXINIT, 0x00000001); 594 MVNETA_WRITE(sc, MVNETA_PTXINIT, 0x00000001); 595 596 #if !defined(__aarch64__) 597 /* 598 * Disable port snoop for buffers and descriptors 599 * to avoid L2 caching of both without DRAM copy. 600 * Obtain coherency settings from the first MBUS 601 * window attribute. 602 */ 603 if ((MVNETA_READ(sc, MV_WIN_NETA_BASE(0)) & IO_WIN_COH_ATTR_MASK) == 0) { 604 reg = MVNETA_READ(sc, MVNETA_PSNPCFG); 605 reg &= ~MVNETA_PSNPCFG_DESCSNP_MASK; 606 reg &= ~MVNETA_PSNPCFG_BUFSNP_MASK; 607 MVNETA_WRITE(sc, MVNETA_PSNPCFG, reg); 608 } 609 #endif 610 611 /* 612 * MAC address 613 */ 614 if (mvneta_get_mac_address(sc, sc->enaddr)) { 615 device_printf(self, "no mac address.\n"); 616 return (ENXIO); 617 } 618 mvneta_set_mac_address(sc, sc->enaddr); 619 620 mvneta_disable_intr(sc); 621 622 /* Allocate network interface */ 623 ifp = sc->ifp = if_alloc(IFT_ETHER); 624 if (ifp == NULL) { 625 device_printf(self, "if_alloc() failed\n"); 626 mvneta_detach(self); 627 return (ENOMEM); 628 } 629 if_initname(ifp, device_get_name(self), device_get_unit(self)); 630 631 /* 632 * We can support 802.1Q VLAN-sized frames and jumbo 633 * Ethernet frames. 634 */ 635 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_JUMBO_MTU; 636 637 ifp->if_softc = sc; 638 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 639 #ifdef MVNETA_MULTIQUEUE 640 ifp->if_transmit = mvneta_transmit; 641 ifp->if_qflush = mvneta_qflush; 642 #else /* !MVNETA_MULTIQUEUE */ 643 ifp->if_start = mvneta_start; 644 ifp->if_snd.ifq_drv_maxlen = MVNETA_TX_RING_CNT - 1; 645 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 646 IFQ_SET_READY(&ifp->if_snd); 647 #endif 648 ifp->if_init = mvneta_init; 649 ifp->if_ioctl = mvneta_ioctl; 650 651 /* 652 * We can do IPv4/TCPv4/UDPv4/TCPv6/UDPv6 checksums in hardware. 653 */ 654 ifp->if_capabilities |= IFCAP_HWCSUM; 655 656 /* 657 * As VLAN hardware tagging is not supported 658 * but is necessary to perform VLAN hardware checksums, 659 * it is done in the driver 660 */ 661 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWCSUM; 662 663 /* 664 * Currently IPv6 HW checksum is broken, so make sure it is disabled. 665 */ 666 ifp->if_capabilities &= ~IFCAP_HWCSUM_IPV6; 667 ifp->if_capenable = ifp->if_capabilities; 668 669 /* 670 * Disabled option(s): 671 * - Support for Large Receive Offload 672 */ 673 ifp->if_capabilities |= IFCAP_LRO; 674 675 ifp->if_hwassist = CSUM_IP | CSUM_TCP | CSUM_UDP; 676 677 /* 678 * Device DMA Buffer allocation. 679 * Handles resource deallocation in case of failure. 680 */ 681 error = mvneta_dma_create(sc); 682 if (error != 0) { 683 mvneta_detach(self); 684 return (error); 685 } 686 687 /* Initialize queues */ 688 for (q = 0; q < MVNETA_TX_QNUM_MAX; q++) { 689 error = mvneta_ring_init_tx_queue(sc, q); 690 if (error != 0) { 691 mvneta_detach(self); 692 return (error); 693 } 694 } 695 696 for (q = 0; q < MVNETA_RX_QNUM_MAX; q++) { 697 error = mvneta_ring_init_rx_queue(sc, q); 698 if (error != 0) { 699 mvneta_detach(self); 700 return (error); 701 } 702 } 703 704 ether_ifattach(ifp, sc->enaddr); 705 706 /* 707 * Enable DMA engines and Initialize Device Registers. 708 */ 709 MVNETA_WRITE(sc, MVNETA_PRXINIT, 0x00000000); 710 MVNETA_WRITE(sc, MVNETA_PTXINIT, 0x00000000); 711 MVNETA_WRITE(sc, MVNETA_PACC, MVNETA_PACC_ACCELERATIONMODE_EDM); 712 mvneta_sc_lock(sc); 713 mvneta_filter_setup(sc); 714 mvneta_sc_unlock(sc); 715 mvneta_initreg(ifp); 716 717 /* 718 * Now MAC is working, setup MII. 719 */ 720 if (mii_init == 0) { 721 /* 722 * MII bus is shared by all MACs and all PHYs in SoC. 723 * serializing the bus access should be safe. 724 */ 725 mtx_init(&mii_mutex, "mvneta_mii", NULL, MTX_DEF); 726 mii_init = 1; 727 } 728 729 /* Attach PHY(s) */ 730 if ((sc->phy_addr != MII_PHY_ANY) && (!sc->use_inband_status)) { 731 error = mii_attach(self, &sc->miibus, ifp, mvneta_mediachange, 732 mvneta_mediastatus, BMSR_DEFCAPMASK, sc->phy_addr, 733 MII_OFFSET_ANY, 0); 734 if (error != 0) { 735 if (bootverbose) { 736 device_printf(self, 737 "MII attach failed, error: %d\n", error); 738 } 739 ether_ifdetach(sc->ifp); 740 mvneta_detach(self); 741 return (error); 742 } 743 sc->mii = device_get_softc(sc->miibus); 744 sc->phy_attached = 1; 745 746 /* Disable auto-negotiation in MAC - rely on PHY layer */ 747 mvneta_update_autoneg(sc, FALSE); 748 } else if (sc->use_inband_status == TRUE) { 749 /* In-band link status */ 750 ifmedia_init(&sc->mvneta_ifmedia, 0, mvneta_mediachange, 751 mvneta_mediastatus); 752 753 /* Configure media */ 754 ifmedia_add(&sc->mvneta_ifmedia, IFM_ETHER | IFM_1000_T | IFM_FDX, 755 0, NULL); 756 ifmedia_add(&sc->mvneta_ifmedia, IFM_ETHER | IFM_100_TX, 0, NULL); 757 ifmedia_add(&sc->mvneta_ifmedia, IFM_ETHER | IFM_100_TX | IFM_FDX, 758 0, NULL); 759 ifmedia_add(&sc->mvneta_ifmedia, IFM_ETHER | IFM_10_T, 0, NULL); 760 ifmedia_add(&sc->mvneta_ifmedia, IFM_ETHER | IFM_10_T | IFM_FDX, 761 0, NULL); 762 ifmedia_add(&sc->mvneta_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 763 ifmedia_set(&sc->mvneta_ifmedia, IFM_ETHER | IFM_AUTO); 764 765 /* Enable auto-negotiation */ 766 mvneta_update_autoneg(sc, TRUE); 767 768 mvneta_sc_lock(sc); 769 if (MVNETA_IS_LINKUP(sc)) 770 mvneta_linkup(sc); 771 else 772 mvneta_linkdown(sc); 773 mvneta_sc_unlock(sc); 774 775 } else { 776 /* Fixed-link, use predefined values */ 777 mvneta_update_autoneg(sc, FALSE); 778 ifmedia_init(&sc->mvneta_ifmedia, 0, mvneta_mediachange, 779 mvneta_mediastatus); 780 781 ifm_target = IFM_ETHER; 782 switch (sc->phy_speed) { 783 case 2500: 784 if (sc->phy_mode != MVNETA_PHY_SGMII && 785 sc->phy_mode != MVNETA_PHY_QSGMII) { 786 device_printf(self, 787 "2.5G speed can work only in (Q)SGMII mode\n"); 788 ether_ifdetach(sc->ifp); 789 mvneta_detach(self); 790 return (ENXIO); 791 } 792 ifm_target |= IFM_2500_T; 793 break; 794 case 1000: 795 ifm_target |= IFM_1000_T; 796 break; 797 case 100: 798 ifm_target |= IFM_100_TX; 799 break; 800 case 10: 801 ifm_target |= IFM_10_T; 802 break; 803 default: 804 ether_ifdetach(sc->ifp); 805 mvneta_detach(self); 806 return (ENXIO); 807 } 808 809 if (sc->phy_fdx) 810 ifm_target |= IFM_FDX; 811 else 812 ifm_target |= IFM_HDX; 813 814 ifmedia_add(&sc->mvneta_ifmedia, ifm_target, 0, NULL); 815 ifmedia_set(&sc->mvneta_ifmedia, ifm_target); 816 if_link_state_change(sc->ifp, LINK_STATE_UP); 817 818 if (mvneta_has_switch(self)) { 819 if (bootverbose) 820 device_printf(self, "This device is attached to a switch\n"); 821 child = device_add_child(sc->dev, "mdio", -1); 822 if (child == NULL) { 823 ether_ifdetach(sc->ifp); 824 mvneta_detach(self); 825 return (ENXIO); 826 } 827 bus_generic_attach(sc->dev); 828 bus_generic_attach(child); 829 } 830 831 /* Configure MAC media */ 832 mvneta_update_media(sc, ifm_target); 833 } 834 835 sysctl_mvneta_init(sc); 836 837 callout_reset(&sc->tick_ch, 0, mvneta_tick, sc); 838 839 error = bus_setup_intr(self, sc->res[1], 840 INTR_TYPE_NET | INTR_MPSAFE, NULL, mvneta_intrs[0].handler, sc, 841 &sc->ih_cookie[0]); 842 if (error) { 843 device_printf(self, "could not setup %s\n", 844 mvneta_intrs[0].description); 845 ether_ifdetach(sc->ifp); 846 mvneta_detach(self); 847 return (error); 848 } 849 850 return (0); 851 } 852 853 STATIC int 854 mvneta_detach(device_t dev) 855 { 856 struct mvneta_softc *sc; 857 int q; 858 859 sc = device_get_softc(dev); 860 861 mvneta_stop(sc); 862 /* Detach network interface */ 863 if (sc->ifp) 864 if_free(sc->ifp); 865 866 for (q = 0; q < MVNETA_RX_QNUM_MAX; q++) 867 mvneta_ring_dealloc_rx_queue(sc, q); 868 for (q = 0; q < MVNETA_TX_QNUM_MAX; q++) 869 mvneta_ring_dealloc_tx_queue(sc, q); 870 871 if (sc->tx_dtag != NULL) 872 bus_dma_tag_destroy(sc->tx_dtag); 873 if (sc->rx_dtag != NULL) 874 bus_dma_tag_destroy(sc->rx_dtag); 875 if (sc->txmbuf_dtag != NULL) 876 bus_dma_tag_destroy(sc->txmbuf_dtag); 877 878 bus_release_resources(dev, res_spec, sc->res); 879 return (0); 880 } 881 882 /* 883 * MII 884 */ 885 STATIC int 886 mvneta_miibus_readreg(device_t dev, int phy, int reg) 887 { 888 struct mvneta_softc *sc; 889 struct ifnet *ifp; 890 uint32_t smi, val; 891 int i; 892 893 sc = device_get_softc(dev); 894 ifp = sc->ifp; 895 896 mtx_lock(&mii_mutex); 897 898 for (i = 0; i < MVNETA_PHY_TIMEOUT; i++) { 899 if ((MVNETA_READ(sc, MVNETA_SMI) & MVNETA_SMI_BUSY) == 0) 900 break; 901 DELAY(1); 902 } 903 if (i == MVNETA_PHY_TIMEOUT) { 904 if_printf(ifp, "SMI busy timeout\n"); 905 mtx_unlock(&mii_mutex); 906 return (-1); 907 } 908 909 smi = MVNETA_SMI_PHYAD(phy) | 910 MVNETA_SMI_REGAD(reg) | MVNETA_SMI_OPCODE_READ; 911 MVNETA_WRITE(sc, MVNETA_SMI, smi); 912 913 for (i = 0; i < MVNETA_PHY_TIMEOUT; i++) { 914 if ((MVNETA_READ(sc, MVNETA_SMI) & MVNETA_SMI_BUSY) == 0) 915 break; 916 DELAY(1); 917 } 918 919 if (i == MVNETA_PHY_TIMEOUT) { 920 if_printf(ifp, "SMI busy timeout\n"); 921 mtx_unlock(&mii_mutex); 922 return (-1); 923 } 924 for (i = 0; i < MVNETA_PHY_TIMEOUT; i++) { 925 smi = MVNETA_READ(sc, MVNETA_SMI); 926 if (smi & MVNETA_SMI_READVALID) 927 break; 928 DELAY(1); 929 } 930 931 if (i == MVNETA_PHY_TIMEOUT) { 932 if_printf(ifp, "SMI busy timeout\n"); 933 mtx_unlock(&mii_mutex); 934 return (-1); 935 } 936 937 mtx_unlock(&mii_mutex); 938 939 #ifdef MVNETA_KTR 940 CTR3(KTR_SPARE2, "%s i=%d, timeout=%d\n", ifp->if_xname, i, 941 MVNETA_PHY_TIMEOUT); 942 #endif 943 944 val = smi & MVNETA_SMI_DATA_MASK; 945 946 #ifdef MVNETA_KTR 947 CTR4(KTR_SPARE2, "%s phy=%d, reg=%#x, val=%#x\n", ifp->if_xname, phy, 948 reg, val); 949 #endif 950 return (val); 951 } 952 953 STATIC int 954 mvneta_miibus_writereg(device_t dev, int phy, int reg, int val) 955 { 956 struct mvneta_softc *sc; 957 struct ifnet *ifp; 958 uint32_t smi; 959 int i; 960 961 sc = device_get_softc(dev); 962 ifp = sc->ifp; 963 #ifdef MVNETA_KTR 964 CTR4(KTR_SPARE2, "%s phy=%d, reg=%#x, val=%#x\n", ifp->if_xname, 965 phy, reg, val); 966 #endif 967 968 mtx_lock(&mii_mutex); 969 970 for (i = 0; i < MVNETA_PHY_TIMEOUT; i++) { 971 if ((MVNETA_READ(sc, MVNETA_SMI) & MVNETA_SMI_BUSY) == 0) 972 break; 973 DELAY(1); 974 } 975 if (i == MVNETA_PHY_TIMEOUT) { 976 if_printf(ifp, "SMI busy timeout\n"); 977 mtx_unlock(&mii_mutex); 978 return (0); 979 } 980 981 smi = MVNETA_SMI_PHYAD(phy) | MVNETA_SMI_REGAD(reg) | 982 MVNETA_SMI_OPCODE_WRITE | (val & MVNETA_SMI_DATA_MASK); 983 MVNETA_WRITE(sc, MVNETA_SMI, smi); 984 985 for (i = 0; i < MVNETA_PHY_TIMEOUT; i++) { 986 if ((MVNETA_READ(sc, MVNETA_SMI) & MVNETA_SMI_BUSY) == 0) 987 break; 988 DELAY(1); 989 } 990 991 mtx_unlock(&mii_mutex); 992 993 if (i == MVNETA_PHY_TIMEOUT) 994 if_printf(ifp, "phy write timed out\n"); 995 996 return (0); 997 } 998 999 STATIC void 1000 mvneta_portup(struct mvneta_softc *sc) 1001 { 1002 int q; 1003 1004 for (q = 0; q < MVNETA_RX_QNUM_MAX; q++) { 1005 mvneta_rx_lockq(sc, q); 1006 mvneta_rx_queue_enable(sc->ifp, q); 1007 mvneta_rx_unlockq(sc, q); 1008 } 1009 1010 for (q = 0; q < MVNETA_TX_QNUM_MAX; q++) { 1011 mvneta_tx_lockq(sc, q); 1012 mvneta_tx_queue_enable(sc->ifp, q); 1013 mvneta_tx_unlockq(sc, q); 1014 } 1015 1016 } 1017 1018 STATIC void 1019 mvneta_portdown(struct mvneta_softc *sc) 1020 { 1021 struct mvneta_rx_ring *rx; 1022 struct mvneta_tx_ring *tx; 1023 int q, cnt; 1024 uint32_t reg; 1025 1026 for (q = 0; q < MVNETA_RX_QNUM_MAX; q++) { 1027 rx = MVNETA_RX_RING(sc, q); 1028 mvneta_rx_lockq(sc, q); 1029 rx->queue_status = MVNETA_QUEUE_DISABLED; 1030 mvneta_rx_unlockq(sc, q); 1031 } 1032 1033 for (q = 0; q < MVNETA_TX_QNUM_MAX; q++) { 1034 tx = MVNETA_TX_RING(sc, q); 1035 mvneta_tx_lockq(sc, q); 1036 tx->queue_status = MVNETA_QUEUE_DISABLED; 1037 mvneta_tx_unlockq(sc, q); 1038 } 1039 1040 /* Wait for all Rx activity to terminate. */ 1041 reg = MVNETA_READ(sc, MVNETA_RQC) & MVNETA_RQC_EN_MASK; 1042 reg = MVNETA_RQC_DIS(reg); 1043 MVNETA_WRITE(sc, MVNETA_RQC, reg); 1044 cnt = 0; 1045 do { 1046 if (cnt >= RX_DISABLE_TIMEOUT) { 1047 if_printf(sc->ifp, 1048 "timeout for RX stopped. rqc 0x%x\n", reg); 1049 break; 1050 } 1051 cnt++; 1052 reg = MVNETA_READ(sc, MVNETA_RQC); 1053 } while ((reg & MVNETA_RQC_EN_MASK) != 0); 1054 1055 /* Wait for all Tx activity to terminate. */ 1056 reg = MVNETA_READ(sc, MVNETA_PIE); 1057 reg &= ~MVNETA_PIE_TXPKTINTRPTENB_MASK; 1058 MVNETA_WRITE(sc, MVNETA_PIE, reg); 1059 1060 reg = MVNETA_READ(sc, MVNETA_PRXTXTIM); 1061 reg &= ~MVNETA_PRXTXTI_TBTCQ_MASK; 1062 MVNETA_WRITE(sc, MVNETA_PRXTXTIM, reg); 1063 1064 reg = MVNETA_READ(sc, MVNETA_TQC) & MVNETA_TQC_EN_MASK; 1065 reg = MVNETA_TQC_DIS(reg); 1066 MVNETA_WRITE(sc, MVNETA_TQC, reg); 1067 cnt = 0; 1068 do { 1069 if (cnt >= TX_DISABLE_TIMEOUT) { 1070 if_printf(sc->ifp, 1071 "timeout for TX stopped. tqc 0x%x\n", reg); 1072 break; 1073 } 1074 cnt++; 1075 reg = MVNETA_READ(sc, MVNETA_TQC); 1076 } while ((reg & MVNETA_TQC_EN_MASK) != 0); 1077 1078 /* Wait for all Tx FIFO is empty */ 1079 cnt = 0; 1080 do { 1081 if (cnt >= TX_FIFO_EMPTY_TIMEOUT) { 1082 if_printf(sc->ifp, 1083 "timeout for TX FIFO drained. ps0 0x%x\n", reg); 1084 break; 1085 } 1086 cnt++; 1087 reg = MVNETA_READ(sc, MVNETA_PS0); 1088 } while (((reg & MVNETA_PS0_TXFIFOEMP) == 0) && 1089 ((reg & MVNETA_PS0_TXINPROG) != 0)); 1090 } 1091 1092 /* 1093 * Device Register Initialization 1094 * reset device registers to device driver default value. 1095 * the device is not enabled here. 1096 */ 1097 STATIC int 1098 mvneta_initreg(struct ifnet *ifp) 1099 { 1100 struct mvneta_softc *sc; 1101 int q, i; 1102 uint32_t reg; 1103 1104 sc = ifp->if_softc; 1105 #ifdef MVNETA_KTR 1106 CTR1(KTR_SPARE2, "%s initializing device register", ifp->if_xname); 1107 #endif 1108 1109 /* Disable Legacy WRR, Disable EJP, Release from reset. */ 1110 MVNETA_WRITE(sc, MVNETA_TQC_1, 0); 1111 /* Enable mbus retry. */ 1112 MVNETA_WRITE(sc, MVNETA_MBUS_CONF, MVNETA_MBUS_RETRY_EN); 1113 1114 /* Init TX/RX Queue Registers */ 1115 for (q = 0; q < MVNETA_RX_QNUM_MAX; q++) { 1116 mvneta_rx_lockq(sc, q); 1117 if (mvneta_rx_queue_init(ifp, q) != 0) { 1118 device_printf(sc->dev, 1119 "initialization failed: cannot initialize queue\n"); 1120 mvneta_rx_unlockq(sc, q); 1121 return (ENOBUFS); 1122 } 1123 mvneta_rx_unlockq(sc, q); 1124 } 1125 for (q = 0; q < MVNETA_TX_QNUM_MAX; q++) { 1126 mvneta_tx_lockq(sc, q); 1127 if (mvneta_tx_queue_init(ifp, q) != 0) { 1128 device_printf(sc->dev, 1129 "initialization failed: cannot initialize queue\n"); 1130 mvneta_tx_unlockq(sc, q); 1131 return (ENOBUFS); 1132 } 1133 mvneta_tx_unlockq(sc, q); 1134 } 1135 1136 /* 1137 * Ethernet Unit Control - disable automatic PHY management by HW. 1138 * In case the port uses SMI-controlled PHY, poll its status with 1139 * mii_tick() and update MAC settings accordingly. 1140 */ 1141 reg = MVNETA_READ(sc, MVNETA_EUC); 1142 reg &= ~MVNETA_EUC_POLLING; 1143 MVNETA_WRITE(sc, MVNETA_EUC, reg); 1144 1145 /* EEE: Low Power Idle */ 1146 reg = MVNETA_LPIC0_LILIMIT(MVNETA_LPI_LI); 1147 reg |= MVNETA_LPIC0_TSLIMIT(MVNETA_LPI_TS); 1148 MVNETA_WRITE(sc, MVNETA_LPIC0, reg); 1149 1150 reg = MVNETA_LPIC1_TWLIMIT(MVNETA_LPI_TW); 1151 MVNETA_WRITE(sc, MVNETA_LPIC1, reg); 1152 1153 reg = MVNETA_LPIC2_MUSTSET; 1154 MVNETA_WRITE(sc, MVNETA_LPIC2, reg); 1155 1156 /* Port MAC Control set 0 */ 1157 reg = MVNETA_PMACC0_MUSTSET; /* must write 0x1 */ 1158 reg &= ~MVNETA_PMACC0_PORTEN; /* port is still disabled */ 1159 reg |= MVNETA_PMACC0_FRAMESIZELIMIT(MVNETA_MAX_FRAME); 1160 MVNETA_WRITE(sc, MVNETA_PMACC0, reg); 1161 1162 /* Port MAC Control set 2 */ 1163 reg = MVNETA_READ(sc, MVNETA_PMACC2); 1164 switch (sc->phy_mode) { 1165 case MVNETA_PHY_QSGMII: 1166 reg |= (MVNETA_PMACC2_PCSEN | MVNETA_PMACC2_RGMIIEN); 1167 MVNETA_WRITE(sc, MVNETA_PSERDESCFG, MVNETA_PSERDESCFG_QSGMII); 1168 break; 1169 case MVNETA_PHY_SGMII: 1170 reg |= (MVNETA_PMACC2_PCSEN | MVNETA_PMACC2_RGMIIEN); 1171 MVNETA_WRITE(sc, MVNETA_PSERDESCFG, MVNETA_PSERDESCFG_SGMII); 1172 break; 1173 case MVNETA_PHY_RGMII: 1174 case MVNETA_PHY_RGMII_ID: 1175 reg |= MVNETA_PMACC2_RGMIIEN; 1176 break; 1177 } 1178 reg |= MVNETA_PMACC2_MUSTSET; 1179 reg &= ~MVNETA_PMACC2_PORTMACRESET; 1180 MVNETA_WRITE(sc, MVNETA_PMACC2, reg); 1181 1182 /* Port Configuration Extended: enable Tx CRC generation */ 1183 reg = MVNETA_READ(sc, MVNETA_PXCX); 1184 reg &= ~MVNETA_PXCX_TXCRCDIS; 1185 MVNETA_WRITE(sc, MVNETA_PXCX, reg); 1186 1187 /* clear MIB counter registers(clear by read) */ 1188 for (i = 0; i < nitems(mvneta_mib_list); i++) { 1189 if (mvneta_mib_list[i].reg64) 1190 MVNETA_READ_MIB_8(sc, mvneta_mib_list[i].regnum); 1191 else 1192 MVNETA_READ_MIB_4(sc, mvneta_mib_list[i].regnum); 1193 } 1194 MVNETA_READ(sc, MVNETA_PDFC); 1195 MVNETA_READ(sc, MVNETA_POFC); 1196 1197 /* Set SDC register except IPGINT bits */ 1198 reg = MVNETA_SDC_RXBSZ_16_64BITWORDS; 1199 reg |= MVNETA_SDC_TXBSZ_16_64BITWORDS; 1200 reg |= MVNETA_SDC_BLMR; 1201 reg |= MVNETA_SDC_BLMT; 1202 MVNETA_WRITE(sc, MVNETA_SDC, reg); 1203 1204 return (0); 1205 } 1206 1207 STATIC void 1208 mvneta_dmamap_cb(void *arg, bus_dma_segment_t * segs, int nseg, int error) 1209 { 1210 1211 if (error != 0) 1212 return; 1213 *(bus_addr_t *)arg = segs->ds_addr; 1214 } 1215 1216 STATIC int 1217 mvneta_ring_alloc_rx_queue(struct mvneta_softc *sc, int q) 1218 { 1219 struct mvneta_rx_ring *rx; 1220 struct mvneta_buf *rxbuf; 1221 bus_dmamap_t dmap; 1222 int i, error; 1223 1224 if (q >= MVNETA_RX_QNUM_MAX) 1225 return (EINVAL); 1226 1227 rx = MVNETA_RX_RING(sc, q); 1228 mtx_init(&rx->ring_mtx, "mvneta_rx", NULL, MTX_DEF); 1229 /* Allocate DMA memory for Rx descriptors */ 1230 error = bus_dmamem_alloc(sc->rx_dtag, 1231 (void**)&(rx->desc), 1232 BUS_DMA_NOWAIT | BUS_DMA_ZERO, 1233 &rx->desc_map); 1234 if (error != 0 || rx->desc == NULL) 1235 goto fail; 1236 error = bus_dmamap_load(sc->rx_dtag, rx->desc_map, 1237 rx->desc, 1238 sizeof(struct mvneta_rx_desc) * MVNETA_RX_RING_CNT, 1239 mvneta_dmamap_cb, &rx->desc_pa, BUS_DMA_NOWAIT); 1240 if (error != 0) 1241 goto fail; 1242 1243 for (i = 0; i < MVNETA_RX_RING_CNT; i++) { 1244 error = bus_dmamap_create(sc->rxbuf_dtag, 0, &dmap); 1245 if (error != 0) { 1246 device_printf(sc->dev, 1247 "Failed to create DMA map for Rx buffer num: %d\n", i); 1248 goto fail; 1249 } 1250 rxbuf = &rx->rxbuf[i]; 1251 rxbuf->dmap = dmap; 1252 rxbuf->m = NULL; 1253 } 1254 1255 return (0); 1256 fail: 1257 mvneta_ring_dealloc_rx_queue(sc, q); 1258 device_printf(sc->dev, "DMA Ring buffer allocation failure.\n"); 1259 return (error); 1260 } 1261 1262 STATIC int 1263 mvneta_ring_alloc_tx_queue(struct mvneta_softc *sc, int q) 1264 { 1265 struct mvneta_tx_ring *tx; 1266 int error; 1267 1268 if (q >= MVNETA_TX_QNUM_MAX) 1269 return (EINVAL); 1270 tx = MVNETA_TX_RING(sc, q); 1271 mtx_init(&tx->ring_mtx, "mvneta_tx", NULL, MTX_DEF); 1272 error = bus_dmamem_alloc(sc->tx_dtag, 1273 (void**)&(tx->desc), 1274 BUS_DMA_NOWAIT | BUS_DMA_ZERO, 1275 &tx->desc_map); 1276 if (error != 0 || tx->desc == NULL) 1277 goto fail; 1278 error = bus_dmamap_load(sc->tx_dtag, tx->desc_map, 1279 tx->desc, 1280 sizeof(struct mvneta_tx_desc) * MVNETA_TX_RING_CNT, 1281 mvneta_dmamap_cb, &tx->desc_pa, BUS_DMA_NOWAIT); 1282 if (error != 0) 1283 goto fail; 1284 1285 #ifdef MVNETA_MULTIQUEUE 1286 tx->br = buf_ring_alloc(MVNETA_BUFRING_SIZE, M_DEVBUF, M_NOWAIT, 1287 &tx->ring_mtx); 1288 if (tx->br == NULL) { 1289 device_printf(sc->dev, 1290 "Could not setup buffer ring for TxQ(%d)\n", q); 1291 error = ENOMEM; 1292 goto fail; 1293 } 1294 #endif 1295 1296 return (0); 1297 fail: 1298 mvneta_ring_dealloc_tx_queue(sc, q); 1299 device_printf(sc->dev, "DMA Ring buffer allocation failure.\n"); 1300 return (error); 1301 } 1302 1303 STATIC void 1304 mvneta_ring_dealloc_tx_queue(struct mvneta_softc *sc, int q) 1305 { 1306 struct mvneta_tx_ring *tx; 1307 struct mvneta_buf *txbuf; 1308 void *kva; 1309 int error; 1310 int i; 1311 1312 if (q >= MVNETA_TX_QNUM_MAX) 1313 return; 1314 tx = MVNETA_TX_RING(sc, q); 1315 1316 if (tx->taskq != NULL) { 1317 /* Remove task */ 1318 while (taskqueue_cancel(tx->taskq, &tx->task, NULL) != 0) 1319 taskqueue_drain(tx->taskq, &tx->task); 1320 } 1321 #ifdef MVNETA_MULTIQUEUE 1322 if (tx->br != NULL) 1323 drbr_free(tx->br, M_DEVBUF); 1324 #endif 1325 1326 if (sc->txmbuf_dtag != NULL) { 1327 if (mtx_name(&tx->ring_mtx) != NULL) { 1328 /* 1329 * It is assumed that maps are being loaded after mutex 1330 * is initialized. Therefore we can skip unloading maps 1331 * when mutex is empty. 1332 */ 1333 mvneta_tx_lockq(sc, q); 1334 mvneta_ring_flush_tx_queue(sc, q); 1335 mvneta_tx_unlockq(sc, q); 1336 } 1337 for (i = 0; i < MVNETA_TX_RING_CNT; i++) { 1338 txbuf = &tx->txbuf[i]; 1339 if (txbuf->dmap != NULL) { 1340 error = bus_dmamap_destroy(sc->txmbuf_dtag, 1341 txbuf->dmap); 1342 if (error != 0) { 1343 panic("%s: map busy for Tx descriptor (Q%d, %d)", 1344 __func__, q, i); 1345 } 1346 } 1347 } 1348 } 1349 1350 if (tx->desc_pa != 0) 1351 bus_dmamap_unload(sc->tx_dtag, tx->desc_map); 1352 1353 kva = (void *)tx->desc; 1354 if (kva != NULL) 1355 bus_dmamem_free(sc->tx_dtag, tx->desc, tx->desc_map); 1356 1357 if (mtx_name(&tx->ring_mtx) != NULL) 1358 mtx_destroy(&tx->ring_mtx); 1359 1360 memset(tx, 0, sizeof(*tx)); 1361 } 1362 1363 STATIC void 1364 mvneta_ring_dealloc_rx_queue(struct mvneta_softc *sc, int q) 1365 { 1366 struct mvneta_rx_ring *rx; 1367 struct lro_ctrl *lro; 1368 void *kva; 1369 1370 if (q >= MVNETA_RX_QNUM_MAX) 1371 return; 1372 1373 rx = MVNETA_RX_RING(sc, q); 1374 1375 mvneta_ring_flush_rx_queue(sc, q); 1376 1377 if (rx->desc_pa != 0) 1378 bus_dmamap_unload(sc->rx_dtag, rx->desc_map); 1379 1380 kva = (void *)rx->desc; 1381 if (kva != NULL) 1382 bus_dmamem_free(sc->rx_dtag, rx->desc, rx->desc_map); 1383 1384 lro = &rx->lro; 1385 tcp_lro_free(lro); 1386 1387 if (mtx_name(&rx->ring_mtx) != NULL) 1388 mtx_destroy(&rx->ring_mtx); 1389 1390 memset(rx, 0, sizeof(*rx)); 1391 } 1392 1393 STATIC int 1394 mvneta_ring_init_rx_queue(struct mvneta_softc *sc, int q) 1395 { 1396 struct mvneta_rx_ring *rx; 1397 struct lro_ctrl *lro; 1398 int error; 1399 1400 if (q >= MVNETA_RX_QNUM_MAX) 1401 return (0); 1402 1403 rx = MVNETA_RX_RING(sc, q); 1404 rx->dma = rx->cpu = 0; 1405 rx->queue_th_received = MVNETA_RXTH_COUNT; 1406 rx->queue_th_time = (mvneta_get_clk() / 1000) / 10; /* 0.1 [ms] */ 1407 1408 /* Initialize LRO */ 1409 rx->lro_enabled = FALSE; 1410 if ((sc->ifp->if_capenable & IFCAP_LRO) != 0) { 1411 lro = &rx->lro; 1412 error = tcp_lro_init(lro); 1413 if (error != 0) 1414 device_printf(sc->dev, "LRO Initialization failed!\n"); 1415 else { 1416 rx->lro_enabled = TRUE; 1417 lro->ifp = sc->ifp; 1418 } 1419 } 1420 1421 return (0); 1422 } 1423 1424 STATIC int 1425 mvneta_ring_init_tx_queue(struct mvneta_softc *sc, int q) 1426 { 1427 struct mvneta_tx_ring *tx; 1428 struct mvneta_buf *txbuf; 1429 int i, error; 1430 1431 if (q >= MVNETA_TX_QNUM_MAX) 1432 return (0); 1433 1434 tx = MVNETA_TX_RING(sc, q); 1435 1436 /* Tx handle */ 1437 for (i = 0; i < MVNETA_TX_RING_CNT; i++) { 1438 txbuf = &tx->txbuf[i]; 1439 txbuf->m = NULL; 1440 /* Tx handle needs DMA map for busdma_load_mbuf() */ 1441 error = bus_dmamap_create(sc->txmbuf_dtag, 0, 1442 &txbuf->dmap); 1443 if (error != 0) { 1444 device_printf(sc->dev, 1445 "can't create dma map (tx ring %d)\n", i); 1446 return (error); 1447 } 1448 } 1449 tx->dma = tx->cpu = 0; 1450 tx->used = 0; 1451 tx->drv_error = 0; 1452 tx->queue_status = MVNETA_QUEUE_DISABLED; 1453 tx->queue_hung = FALSE; 1454 1455 tx->ifp = sc->ifp; 1456 tx->qidx = q; 1457 TASK_INIT(&tx->task, 0, mvneta_tx_task, tx); 1458 tx->taskq = taskqueue_create_fast("mvneta_tx_taskq", M_WAITOK, 1459 taskqueue_thread_enqueue, &tx->taskq); 1460 taskqueue_start_threads(&tx->taskq, 1, PI_NET, "%s: tx_taskq(%d)", 1461 device_get_nameunit(sc->dev), q); 1462 1463 return (0); 1464 } 1465 1466 STATIC void 1467 mvneta_ring_flush_tx_queue(struct mvneta_softc *sc, int q) 1468 { 1469 struct mvneta_tx_ring *tx; 1470 struct mvneta_buf *txbuf; 1471 int i; 1472 1473 tx = MVNETA_TX_RING(sc, q); 1474 KASSERT_TX_MTX(sc, q); 1475 1476 /* Tx handle */ 1477 for (i = 0; i < MVNETA_TX_RING_CNT; i++) { 1478 txbuf = &tx->txbuf[i]; 1479 bus_dmamap_unload(sc->txmbuf_dtag, txbuf->dmap); 1480 if (txbuf->m != NULL) { 1481 m_freem(txbuf->m); 1482 txbuf->m = NULL; 1483 } 1484 } 1485 tx->dma = tx->cpu = 0; 1486 tx->used = 0; 1487 } 1488 1489 STATIC void 1490 mvneta_ring_flush_rx_queue(struct mvneta_softc *sc, int q) 1491 { 1492 struct mvneta_rx_ring *rx; 1493 struct mvneta_buf *rxbuf; 1494 int i; 1495 1496 rx = MVNETA_RX_RING(sc, q); 1497 KASSERT_RX_MTX(sc, q); 1498 1499 /* Rx handle */ 1500 for (i = 0; i < MVNETA_RX_RING_CNT; i++) { 1501 rxbuf = &rx->rxbuf[i]; 1502 mvneta_rx_buf_free(sc, rxbuf); 1503 } 1504 rx->dma = rx->cpu = 0; 1505 } 1506 1507 /* 1508 * Rx/Tx Queue Control 1509 */ 1510 STATIC int 1511 mvneta_rx_queue_init(struct ifnet *ifp, int q) 1512 { 1513 struct mvneta_softc *sc; 1514 struct mvneta_rx_ring *rx; 1515 uint32_t reg; 1516 1517 sc = ifp->if_softc; 1518 KASSERT_RX_MTX(sc, q); 1519 rx = MVNETA_RX_RING(sc, q); 1520 DASSERT(rx->desc_pa != 0); 1521 1522 /* descriptor address */ 1523 MVNETA_WRITE(sc, MVNETA_PRXDQA(q), rx->desc_pa); 1524 1525 /* Rx buffer size and descriptor ring size */ 1526 reg = MVNETA_PRXDQS_BUFFERSIZE(MVNETA_PACKET_SIZE >> 3); 1527 reg |= MVNETA_PRXDQS_DESCRIPTORSQUEUESIZE(MVNETA_RX_RING_CNT); 1528 MVNETA_WRITE(sc, MVNETA_PRXDQS(q), reg); 1529 #ifdef MVNETA_KTR 1530 CTR3(KTR_SPARE2, "%s PRXDQS(%d): %#x", ifp->if_xname, q, 1531 MVNETA_READ(sc, MVNETA_PRXDQS(q))); 1532 #endif 1533 /* Rx packet offset address */ 1534 reg = MVNETA_PRXC_PACKETOFFSET(MVNETA_PACKET_OFFSET >> 3); 1535 MVNETA_WRITE(sc, MVNETA_PRXC(q), reg); 1536 #ifdef MVNETA_KTR 1537 CTR3(KTR_SPARE2, "%s PRXC(%d): %#x", ifp->if_xname, q, 1538 MVNETA_READ(sc, MVNETA_PRXC(q))); 1539 #endif 1540 1541 /* if DMA is not working, register is not updated */ 1542 DASSERT(MVNETA_READ(sc, MVNETA_PRXDQA(q)) == rx->desc_pa); 1543 return (0); 1544 } 1545 1546 STATIC int 1547 mvneta_tx_queue_init(struct ifnet *ifp, int q) 1548 { 1549 struct mvneta_softc *sc; 1550 struct mvneta_tx_ring *tx; 1551 uint32_t reg; 1552 1553 sc = ifp->if_softc; 1554 KASSERT_TX_MTX(sc, q); 1555 tx = MVNETA_TX_RING(sc, q); 1556 DASSERT(tx->desc_pa != 0); 1557 1558 /* descriptor address */ 1559 MVNETA_WRITE(sc, MVNETA_PTXDQA(q), tx->desc_pa); 1560 1561 /* descriptor ring size */ 1562 reg = MVNETA_PTXDQS_DQS(MVNETA_TX_RING_CNT); 1563 MVNETA_WRITE(sc, MVNETA_PTXDQS(q), reg); 1564 1565 /* if DMA is not working, register is not updated */ 1566 DASSERT(MVNETA_READ(sc, MVNETA_PTXDQA(q)) == tx->desc_pa); 1567 return (0); 1568 } 1569 1570 STATIC int 1571 mvneta_rx_queue_enable(struct ifnet *ifp, int q) 1572 { 1573 struct mvneta_softc *sc; 1574 struct mvneta_rx_ring *rx; 1575 uint32_t reg; 1576 1577 sc = ifp->if_softc; 1578 rx = MVNETA_RX_RING(sc, q); 1579 KASSERT_RX_MTX(sc, q); 1580 1581 /* Set Rx interrupt threshold */ 1582 reg = MVNETA_PRXDQTH_ODT(rx->queue_th_received); 1583 MVNETA_WRITE(sc, MVNETA_PRXDQTH(q), reg); 1584 1585 reg = MVNETA_PRXITTH_RITT(rx->queue_th_time); 1586 MVNETA_WRITE(sc, MVNETA_PRXITTH(q), reg); 1587 1588 /* Unmask RXTX_TH Intr. */ 1589 reg = MVNETA_READ(sc, MVNETA_PRXTXTIM); 1590 reg |= MVNETA_PRXTXTI_RBICTAPQ(q); /* Rx Buffer Interrupt Coalese */ 1591 MVNETA_WRITE(sc, MVNETA_PRXTXTIM, reg); 1592 1593 /* Enable Rx queue */ 1594 reg = MVNETA_READ(sc, MVNETA_RQC) & MVNETA_RQC_EN_MASK; 1595 reg |= MVNETA_RQC_ENQ(q); 1596 MVNETA_WRITE(sc, MVNETA_RQC, reg); 1597 1598 rx->queue_status = MVNETA_QUEUE_WORKING; 1599 return (0); 1600 } 1601 1602 STATIC int 1603 mvneta_tx_queue_enable(struct ifnet *ifp, int q) 1604 { 1605 struct mvneta_softc *sc; 1606 struct mvneta_tx_ring *tx; 1607 1608 sc = ifp->if_softc; 1609 tx = MVNETA_TX_RING(sc, q); 1610 KASSERT_TX_MTX(sc, q); 1611 1612 /* Enable Tx queue */ 1613 MVNETA_WRITE(sc, MVNETA_TQC, MVNETA_TQC_ENQ(q)); 1614 1615 tx->queue_status = MVNETA_QUEUE_IDLE; 1616 tx->queue_hung = FALSE; 1617 return (0); 1618 } 1619 1620 STATIC __inline void 1621 mvneta_rx_lockq(struct mvneta_softc *sc, int q) 1622 { 1623 1624 DASSERT(q >= 0); 1625 DASSERT(q < MVNETA_RX_QNUM_MAX); 1626 mtx_lock(&sc->rx_ring[q].ring_mtx); 1627 } 1628 1629 STATIC __inline void 1630 mvneta_rx_unlockq(struct mvneta_softc *sc, int q) 1631 { 1632 1633 DASSERT(q >= 0); 1634 DASSERT(q < MVNETA_RX_QNUM_MAX); 1635 mtx_unlock(&sc->rx_ring[q].ring_mtx); 1636 } 1637 1638 STATIC __inline int __unused 1639 mvneta_tx_trylockq(struct mvneta_softc *sc, int q) 1640 { 1641 1642 DASSERT(q >= 0); 1643 DASSERT(q < MVNETA_TX_QNUM_MAX); 1644 return (mtx_trylock(&sc->tx_ring[q].ring_mtx)); 1645 } 1646 1647 STATIC __inline void 1648 mvneta_tx_lockq(struct mvneta_softc *sc, int q) 1649 { 1650 1651 DASSERT(q >= 0); 1652 DASSERT(q < MVNETA_TX_QNUM_MAX); 1653 mtx_lock(&sc->tx_ring[q].ring_mtx); 1654 } 1655 1656 STATIC __inline void 1657 mvneta_tx_unlockq(struct mvneta_softc *sc, int q) 1658 { 1659 1660 DASSERT(q >= 0); 1661 DASSERT(q < MVNETA_TX_QNUM_MAX); 1662 mtx_unlock(&sc->tx_ring[q].ring_mtx); 1663 } 1664 1665 /* 1666 * Interrupt Handlers 1667 */ 1668 STATIC void 1669 mvneta_disable_intr(struct mvneta_softc *sc) 1670 { 1671 1672 MVNETA_WRITE(sc, MVNETA_EUIM, 0); 1673 MVNETA_WRITE(sc, MVNETA_EUIC, 0); 1674 MVNETA_WRITE(sc, MVNETA_PRXTXTIM, 0); 1675 MVNETA_WRITE(sc, MVNETA_PRXTXTIC, 0); 1676 MVNETA_WRITE(sc, MVNETA_PRXTXIM, 0); 1677 MVNETA_WRITE(sc, MVNETA_PRXTXIC, 0); 1678 MVNETA_WRITE(sc, MVNETA_PMIM, 0); 1679 MVNETA_WRITE(sc, MVNETA_PMIC, 0); 1680 MVNETA_WRITE(sc, MVNETA_PIE, 0); 1681 } 1682 1683 STATIC void 1684 mvneta_enable_intr(struct mvneta_softc *sc) 1685 { 1686 uint32_t reg; 1687 1688 /* Enable Summary Bit to check all interrupt cause. */ 1689 reg = MVNETA_READ(sc, MVNETA_PRXTXTIM); 1690 reg |= MVNETA_PRXTXTI_PMISCICSUMMARY; 1691 MVNETA_WRITE(sc, MVNETA_PRXTXTIM, reg); 1692 1693 if (sc->use_inband_status) { 1694 /* Enable Port MISC Intr. (via RXTX_TH_Summary bit) */ 1695 MVNETA_WRITE(sc, MVNETA_PMIM, MVNETA_PMI_PHYSTATUSCHNG | 1696 MVNETA_PMI_LINKCHANGE | MVNETA_PMI_PSCSYNCCHANGE); 1697 } 1698 1699 /* Enable All Queue Interrupt */ 1700 reg = MVNETA_READ(sc, MVNETA_PIE); 1701 reg |= MVNETA_PIE_RXPKTINTRPTENB_MASK; 1702 reg |= MVNETA_PIE_TXPKTINTRPTENB_MASK; 1703 MVNETA_WRITE(sc, MVNETA_PIE, reg); 1704 } 1705 1706 STATIC void 1707 mvneta_rxtxth_intr(void *arg) 1708 { 1709 struct mvneta_softc *sc; 1710 struct ifnet *ifp; 1711 uint32_t ic, queues; 1712 1713 sc = arg; 1714 ifp = sc->ifp; 1715 #ifdef MVNETA_KTR 1716 CTR1(KTR_SPARE2, "%s got RXTX_TH_Intr", ifp->if_xname); 1717 #endif 1718 ic = MVNETA_READ(sc, MVNETA_PRXTXTIC); 1719 if (ic == 0) 1720 return; 1721 MVNETA_WRITE(sc, MVNETA_PRXTXTIC, ~ic); 1722 1723 /* Ack maintance interrupt first */ 1724 if (__predict_false((ic & MVNETA_PRXTXTI_PMISCICSUMMARY) && 1725 sc->use_inband_status)) { 1726 mvneta_sc_lock(sc); 1727 mvneta_misc_intr(sc); 1728 mvneta_sc_unlock(sc); 1729 } 1730 if (__predict_false(!(ifp->if_drv_flags & IFF_DRV_RUNNING))) 1731 return; 1732 /* RxTxTH interrupt */ 1733 queues = MVNETA_PRXTXTI_GET_RBICTAPQ(ic); 1734 if (__predict_true(queues)) { 1735 #ifdef MVNETA_KTR 1736 CTR1(KTR_SPARE2, "%s got PRXTXTIC: +RXEOF", ifp->if_xname); 1737 #endif 1738 /* At the moment the driver support only one RX queue. */ 1739 DASSERT(MVNETA_IS_QUEUE_SET(queues, 0)); 1740 mvneta_rx(sc, 0, 0); 1741 } 1742 } 1743 1744 STATIC int 1745 mvneta_misc_intr(struct mvneta_softc *sc) 1746 { 1747 uint32_t ic; 1748 int claimed = 0; 1749 1750 #ifdef MVNETA_KTR 1751 CTR1(KTR_SPARE2, "%s got MISC_INTR", sc->ifp->if_xname); 1752 #endif 1753 KASSERT_SC_MTX(sc); 1754 1755 for (;;) { 1756 ic = MVNETA_READ(sc, MVNETA_PMIC); 1757 ic &= MVNETA_READ(sc, MVNETA_PMIM); 1758 if (ic == 0) 1759 break; 1760 MVNETA_WRITE(sc, MVNETA_PMIC, ~ic); 1761 claimed = 1; 1762 1763 if (ic & (MVNETA_PMI_PHYSTATUSCHNG | 1764 MVNETA_PMI_LINKCHANGE | MVNETA_PMI_PSCSYNCCHANGE)) 1765 mvneta_link_isr(sc); 1766 } 1767 return (claimed); 1768 } 1769 1770 STATIC void 1771 mvneta_tick(void *arg) 1772 { 1773 struct mvneta_softc *sc; 1774 struct mvneta_tx_ring *tx; 1775 struct mvneta_rx_ring *rx; 1776 int q; 1777 uint32_t fc_prev, fc_curr; 1778 1779 sc = arg; 1780 1781 /* 1782 * This is done before mib update to get the right stats 1783 * for this tick. 1784 */ 1785 mvneta_tx_drain(sc); 1786 1787 /* Extract previous flow-control frame received counter. */ 1788 fc_prev = sc->sysctl_mib[MVNETA_MIB_FC_GOOD_IDX].counter; 1789 /* Read mib registers (clear by read). */ 1790 mvneta_update_mib(sc); 1791 /* Extract current flow-control frame received counter. */ 1792 fc_curr = sc->sysctl_mib[MVNETA_MIB_FC_GOOD_IDX].counter; 1793 1794 1795 if (sc->phy_attached && sc->ifp->if_flags & IFF_UP) { 1796 mvneta_sc_lock(sc); 1797 mii_tick(sc->mii); 1798 1799 /* Adjust MAC settings */ 1800 mvneta_adjust_link(sc); 1801 mvneta_sc_unlock(sc); 1802 } 1803 1804 /* 1805 * We were unable to refill the rx queue and left the rx func, leaving 1806 * the ring without mbuf and no way to call the refill func. 1807 */ 1808 for (q = 0; q < MVNETA_RX_QNUM_MAX; q++) { 1809 rx = MVNETA_RX_RING(sc, q); 1810 if (rx->needs_refill == TRUE) { 1811 mvneta_rx_lockq(sc, q); 1812 mvneta_rx_queue_refill(sc, q); 1813 mvneta_rx_unlockq(sc, q); 1814 } 1815 } 1816 1817 /* 1818 * Watchdog: 1819 * - check if queue is mark as hung. 1820 * - ignore hung status if we received some pause frame 1821 * as hardware may have paused packet transmit. 1822 */ 1823 for (q = 0; q < MVNETA_TX_QNUM_MAX; q++) { 1824 /* 1825 * We should take queue lock, but as we only read 1826 * queue status we can do it without lock, we may 1827 * only missdetect queue status for one tick. 1828 */ 1829 tx = MVNETA_TX_RING(sc, q); 1830 1831 if (tx->queue_hung && (fc_curr - fc_prev) == 0) 1832 goto timeout; 1833 } 1834 1835 callout_schedule(&sc->tick_ch, hz); 1836 return; 1837 1838 timeout: 1839 if_printf(sc->ifp, "watchdog timeout\n"); 1840 1841 mvneta_sc_lock(sc); 1842 sc->counter_watchdog++; 1843 sc->counter_watchdog_mib++; 1844 /* Trigger reinitialize sequence. */ 1845 mvneta_stop_locked(sc); 1846 mvneta_init_locked(sc); 1847 mvneta_sc_unlock(sc); 1848 } 1849 1850 STATIC void 1851 mvneta_qflush(struct ifnet *ifp) 1852 { 1853 #ifdef MVNETA_MULTIQUEUE 1854 struct mvneta_softc *sc; 1855 struct mvneta_tx_ring *tx; 1856 struct mbuf *m; 1857 size_t q; 1858 1859 sc = ifp->if_softc; 1860 1861 for (q = 0; q < MVNETA_TX_QNUM_MAX; q++) { 1862 tx = MVNETA_TX_RING(sc, q); 1863 mvneta_tx_lockq(sc, q); 1864 while ((m = buf_ring_dequeue_sc(tx->br)) != NULL) 1865 m_freem(m); 1866 mvneta_tx_unlockq(sc, q); 1867 } 1868 #endif 1869 if_qflush(ifp); 1870 } 1871 1872 STATIC void 1873 mvneta_tx_task(void *arg, int pending) 1874 { 1875 struct mvneta_softc *sc; 1876 struct mvneta_tx_ring *tx; 1877 struct ifnet *ifp; 1878 int error; 1879 1880 tx = arg; 1881 ifp = tx->ifp; 1882 sc = ifp->if_softc; 1883 1884 mvneta_tx_lockq(sc, tx->qidx); 1885 error = mvneta_xmit_locked(sc, tx->qidx); 1886 mvneta_tx_unlockq(sc, tx->qidx); 1887 1888 /* Try again */ 1889 if (__predict_false(error != 0 && error != ENETDOWN)) { 1890 pause("mvneta_tx_task_sleep", 1); 1891 taskqueue_enqueue(tx->taskq, &tx->task); 1892 } 1893 } 1894 1895 STATIC int 1896 mvneta_xmitfast_locked(struct mvneta_softc *sc, int q, struct mbuf **m) 1897 { 1898 struct mvneta_tx_ring *tx; 1899 struct ifnet *ifp; 1900 int error; 1901 1902 KASSERT_TX_MTX(sc, q); 1903 tx = MVNETA_TX_RING(sc, q); 1904 error = 0; 1905 1906 ifp = sc->ifp; 1907 1908 /* Dont enqueue packet if the queue is disabled. */ 1909 if (__predict_false(tx->queue_status == MVNETA_QUEUE_DISABLED)) { 1910 m_freem(*m); 1911 *m = NULL; 1912 return (ENETDOWN); 1913 } 1914 1915 /* Reclaim mbuf if above threshold. */ 1916 if (__predict_true(tx->used > MVNETA_TX_RECLAIM_COUNT)) 1917 mvneta_tx_queue_complete(sc, q); 1918 1919 /* Do not call transmit path if queue is already too full. */ 1920 if (__predict_false(tx->used > 1921 MVNETA_TX_RING_CNT - MVNETA_TX_SEGLIMIT)) 1922 return (ENOBUFS); 1923 1924 error = mvneta_tx_queue(sc, m, q); 1925 if (__predict_false(error != 0)) 1926 return (error); 1927 1928 /* Send a copy of the frame to the BPF listener */ 1929 ETHER_BPF_MTAP(ifp, *m); 1930 1931 /* Set watchdog on */ 1932 tx->watchdog_time = ticks; 1933 tx->queue_status = MVNETA_QUEUE_WORKING; 1934 1935 return (error); 1936 } 1937 1938 #ifdef MVNETA_MULTIQUEUE 1939 STATIC int 1940 mvneta_transmit(struct ifnet *ifp, struct mbuf *m) 1941 { 1942 struct mvneta_softc *sc; 1943 struct mvneta_tx_ring *tx; 1944 int error; 1945 int q; 1946 1947 sc = ifp->if_softc; 1948 1949 /* Use default queue if there is no flow id as thread can migrate. */ 1950 if (__predict_true(M_HASHTYPE_GET(m) != M_HASHTYPE_NONE)) 1951 q = m->m_pkthdr.flowid % MVNETA_TX_QNUM_MAX; 1952 else 1953 q = 0; 1954 1955 tx = MVNETA_TX_RING(sc, q); 1956 1957 /* If buf_ring is full start transmit immediatly. */ 1958 if (buf_ring_full(tx->br)) { 1959 mvneta_tx_lockq(sc, q); 1960 mvneta_xmit_locked(sc, q); 1961 mvneta_tx_unlockq(sc, q); 1962 } 1963 1964 /* 1965 * If the buf_ring is empty we will not reorder packets. 1966 * If the lock is available transmit without using buf_ring. 1967 */ 1968 if (buf_ring_empty(tx->br) && mvneta_tx_trylockq(sc, q) != 0) { 1969 error = mvneta_xmitfast_locked(sc, q, &m); 1970 mvneta_tx_unlockq(sc, q); 1971 if (__predict_true(error == 0)) 1972 return (0); 1973 1974 /* Transmit can fail in fastpath. */ 1975 if (__predict_false(m == NULL)) 1976 return (error); 1977 } 1978 1979 /* Enqueue then schedule taskqueue. */ 1980 error = drbr_enqueue(ifp, tx->br, m); 1981 if (__predict_false(error != 0)) 1982 return (error); 1983 1984 taskqueue_enqueue(tx->taskq, &tx->task); 1985 return (0); 1986 } 1987 1988 STATIC int 1989 mvneta_xmit_locked(struct mvneta_softc *sc, int q) 1990 { 1991 struct ifnet *ifp; 1992 struct mvneta_tx_ring *tx; 1993 struct mbuf *m; 1994 int error; 1995 1996 KASSERT_TX_MTX(sc, q); 1997 ifp = sc->ifp; 1998 tx = MVNETA_TX_RING(sc, q); 1999 error = 0; 2000 2001 while ((m = drbr_peek(ifp, tx->br)) != NULL) { 2002 error = mvneta_xmitfast_locked(sc, q, &m); 2003 if (__predict_false(error != 0)) { 2004 if (m != NULL) 2005 drbr_putback(ifp, tx->br, m); 2006 else 2007 drbr_advance(ifp, tx->br); 2008 break; 2009 } 2010 drbr_advance(ifp, tx->br); 2011 } 2012 2013 return (error); 2014 } 2015 #else /* !MVNETA_MULTIQUEUE */ 2016 STATIC void 2017 mvneta_start(struct ifnet *ifp) 2018 { 2019 struct mvneta_softc *sc; 2020 struct mvneta_tx_ring *tx; 2021 int error; 2022 2023 sc = ifp->if_softc; 2024 tx = MVNETA_TX_RING(sc, 0); 2025 2026 mvneta_tx_lockq(sc, 0); 2027 error = mvneta_xmit_locked(sc, 0); 2028 mvneta_tx_unlockq(sc, 0); 2029 /* Handle retransmit in the background taskq. */ 2030 if (__predict_false(error != 0 && error != ENETDOWN)) 2031 taskqueue_enqueue(tx->taskq, &tx->task); 2032 } 2033 2034 STATIC int 2035 mvneta_xmit_locked(struct mvneta_softc *sc, int q) 2036 { 2037 struct ifnet *ifp; 2038 struct mvneta_tx_ring *tx; 2039 struct mbuf *m; 2040 int error; 2041 2042 KASSERT_TX_MTX(sc, q); 2043 ifp = sc->ifp; 2044 tx = MVNETA_TX_RING(sc, 0); 2045 error = 0; 2046 2047 while (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 2048 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 2049 if (m == NULL) 2050 break; 2051 2052 error = mvneta_xmitfast_locked(sc, q, &m); 2053 if (__predict_false(error != 0)) { 2054 if (m != NULL) 2055 IFQ_DRV_PREPEND(&ifp->if_snd, m); 2056 break; 2057 } 2058 } 2059 2060 return (error); 2061 } 2062 #endif 2063 2064 STATIC int 2065 mvneta_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 2066 { 2067 struct mvneta_softc *sc; 2068 struct mvneta_rx_ring *rx; 2069 struct ifreq *ifr; 2070 int error, mask; 2071 uint32_t flags; 2072 int q; 2073 2074 error = 0; 2075 sc = ifp->if_softc; 2076 ifr = (struct ifreq *)data; 2077 switch (cmd) { 2078 case SIOCSIFFLAGS: 2079 mvneta_sc_lock(sc); 2080 if (ifp->if_flags & IFF_UP) { 2081 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 2082 flags = ifp->if_flags ^ sc->mvneta_if_flags; 2083 2084 if (flags != 0) 2085 sc->mvneta_if_flags = ifp->if_flags; 2086 2087 if ((flags & IFF_PROMISC) != 0) 2088 mvneta_filter_setup(sc); 2089 } else { 2090 mvneta_init_locked(sc); 2091 sc->mvneta_if_flags = ifp->if_flags; 2092 if (sc->phy_attached) 2093 mii_mediachg(sc->mii); 2094 mvneta_sc_unlock(sc); 2095 break; 2096 } 2097 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2098 mvneta_stop_locked(sc); 2099 2100 sc->mvneta_if_flags = ifp->if_flags; 2101 mvneta_sc_unlock(sc); 2102 break; 2103 case SIOCSIFCAP: 2104 if (ifp->if_mtu > MVNETA_MAX_CSUM_MTU && 2105 ifr->ifr_reqcap & IFCAP_TXCSUM) 2106 ifr->ifr_reqcap &= ~IFCAP_TXCSUM; 2107 mask = ifp->if_capenable ^ ifr->ifr_reqcap; 2108 if (mask & IFCAP_HWCSUM) { 2109 ifp->if_capenable &= ~IFCAP_HWCSUM; 2110 ifp->if_capenable |= IFCAP_HWCSUM & ifr->ifr_reqcap; 2111 if (ifp->if_capenable & IFCAP_TXCSUM) 2112 ifp->if_hwassist = CSUM_IP | CSUM_TCP | 2113 CSUM_UDP; 2114 else 2115 ifp->if_hwassist = 0; 2116 } 2117 if (mask & IFCAP_LRO) { 2118 mvneta_sc_lock(sc); 2119 ifp->if_capenable ^= IFCAP_LRO; 2120 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2121 for (q = 0; q < MVNETA_RX_QNUM_MAX; q++) { 2122 rx = MVNETA_RX_RING(sc, q); 2123 rx->lro_enabled = !rx->lro_enabled; 2124 } 2125 } 2126 mvneta_sc_unlock(sc); 2127 } 2128 VLAN_CAPABILITIES(ifp); 2129 break; 2130 case SIOCSIFMEDIA: 2131 if ((IFM_SUBTYPE(ifr->ifr_media) == IFM_1000_T || 2132 IFM_SUBTYPE(ifr->ifr_media) == IFM_2500_T) && 2133 (ifr->ifr_media & IFM_FDX) == 0) { 2134 device_printf(sc->dev, 2135 "%s half-duplex unsupported\n", 2136 IFM_SUBTYPE(ifr->ifr_media) == IFM_1000_T ? 2137 "1000Base-T" : 2138 "2500Base-T"); 2139 error = EINVAL; 2140 break; 2141 } 2142 case SIOCGIFMEDIA: /* FALLTHROUGH */ 2143 case SIOCGIFXMEDIA: 2144 if (!sc->phy_attached) 2145 error = ifmedia_ioctl(ifp, ifr, &sc->mvneta_ifmedia, 2146 cmd); 2147 else 2148 error = ifmedia_ioctl(ifp, ifr, &sc->mii->mii_media, 2149 cmd); 2150 break; 2151 case SIOCSIFMTU: 2152 if (ifr->ifr_mtu < 68 || ifr->ifr_mtu > MVNETA_MAX_FRAME - 2153 MVNETA_ETHER_SIZE) { 2154 error = EINVAL; 2155 } else { 2156 ifp->if_mtu = ifr->ifr_mtu; 2157 mvneta_sc_lock(sc); 2158 if (ifp->if_mtu > MVNETA_MAX_CSUM_MTU) { 2159 ifp->if_capenable &= ~IFCAP_TXCSUM; 2160 ifp->if_hwassist = 0; 2161 } else { 2162 ifp->if_capenable |= IFCAP_TXCSUM; 2163 ifp->if_hwassist = CSUM_IP | CSUM_TCP | 2164 CSUM_UDP; 2165 } 2166 2167 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 2168 /* Trigger reinitialize sequence */ 2169 mvneta_stop_locked(sc); 2170 mvneta_init_locked(sc); 2171 } 2172 mvneta_sc_unlock(sc); 2173 } 2174 break; 2175 2176 default: 2177 error = ether_ioctl(ifp, cmd, data); 2178 break; 2179 } 2180 2181 return (error); 2182 } 2183 2184 STATIC void 2185 mvneta_init_locked(void *arg) 2186 { 2187 struct mvneta_softc *sc; 2188 struct ifnet *ifp; 2189 uint32_t reg; 2190 int q, cpu; 2191 2192 sc = arg; 2193 ifp = sc->ifp; 2194 2195 if (!device_is_attached(sc->dev) || 2196 (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2197 return; 2198 2199 mvneta_disable_intr(sc); 2200 callout_stop(&sc->tick_ch); 2201 2202 /* Get the latest mac address */ 2203 bcopy(IF_LLADDR(ifp), sc->enaddr, ETHER_ADDR_LEN); 2204 mvneta_set_mac_address(sc, sc->enaddr); 2205 mvneta_filter_setup(sc); 2206 2207 /* Start DMA Engine */ 2208 MVNETA_WRITE(sc, MVNETA_PRXINIT, 0x00000000); 2209 MVNETA_WRITE(sc, MVNETA_PTXINIT, 0x00000000); 2210 MVNETA_WRITE(sc, MVNETA_PACC, MVNETA_PACC_ACCELERATIONMODE_EDM); 2211 2212 /* Enable port */ 2213 reg = MVNETA_READ(sc, MVNETA_PMACC0); 2214 reg |= MVNETA_PMACC0_PORTEN; 2215 MVNETA_WRITE(sc, MVNETA_PMACC0, reg); 2216 2217 /* Allow access to each TXQ/RXQ from both CPU's */ 2218 for (cpu = 0; cpu < mp_ncpus; ++cpu) 2219 MVNETA_WRITE(sc, MVNETA_PCP2Q(cpu), 2220 MVNETA_PCP2Q_TXQEN_MASK | MVNETA_PCP2Q_RXQEN_MASK); 2221 2222 for (q = 0; q < MVNETA_RX_QNUM_MAX; q++) { 2223 mvneta_rx_lockq(sc, q); 2224 mvneta_rx_queue_refill(sc, q); 2225 mvneta_rx_unlockq(sc, q); 2226 } 2227 2228 if (!sc->phy_attached) 2229 mvneta_linkup(sc); 2230 2231 /* Enable interrupt */ 2232 mvneta_enable_intr(sc); 2233 2234 /* Set Counter */ 2235 callout_schedule(&sc->tick_ch, hz); 2236 2237 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2238 } 2239 2240 STATIC void 2241 mvneta_init(void *arg) 2242 { 2243 struct mvneta_softc *sc; 2244 2245 sc = arg; 2246 mvneta_sc_lock(sc); 2247 mvneta_init_locked(sc); 2248 if (sc->phy_attached) 2249 mii_mediachg(sc->mii); 2250 mvneta_sc_unlock(sc); 2251 } 2252 2253 /* ARGSUSED */ 2254 STATIC void 2255 mvneta_stop_locked(struct mvneta_softc *sc) 2256 { 2257 struct ifnet *ifp; 2258 struct mvneta_rx_ring *rx; 2259 struct mvneta_tx_ring *tx; 2260 uint32_t reg; 2261 int q; 2262 2263 ifp = sc->ifp; 2264 if (ifp == NULL || (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 2265 return; 2266 2267 mvneta_disable_intr(sc); 2268 2269 callout_stop(&sc->tick_ch); 2270 2271 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2272 2273 /* Link down */ 2274 if (sc->linkup == TRUE) 2275 mvneta_linkdown(sc); 2276 2277 /* Reset the MAC Port Enable bit */ 2278 reg = MVNETA_READ(sc, MVNETA_PMACC0); 2279 reg &= ~MVNETA_PMACC0_PORTEN; 2280 MVNETA_WRITE(sc, MVNETA_PMACC0, reg); 2281 2282 /* Disable each of queue */ 2283 for (q = 0; q < MVNETA_RX_QNUM_MAX; q++) { 2284 rx = MVNETA_RX_RING(sc, q); 2285 2286 mvneta_rx_lockq(sc, q); 2287 mvneta_ring_flush_rx_queue(sc, q); 2288 mvneta_rx_unlockq(sc, q); 2289 } 2290 2291 /* 2292 * Hold Reset state of DMA Engine 2293 * (must write 0x0 to restart it) 2294 */ 2295 MVNETA_WRITE(sc, MVNETA_PRXINIT, 0x00000001); 2296 MVNETA_WRITE(sc, MVNETA_PTXINIT, 0x00000001); 2297 2298 for (q = 0; q < MVNETA_TX_QNUM_MAX; q++) { 2299 tx = MVNETA_TX_RING(sc, q); 2300 2301 mvneta_tx_lockq(sc, q); 2302 mvneta_ring_flush_tx_queue(sc, q); 2303 mvneta_tx_unlockq(sc, q); 2304 } 2305 } 2306 2307 STATIC void 2308 mvneta_stop(struct mvneta_softc *sc) 2309 { 2310 2311 mvneta_sc_lock(sc); 2312 mvneta_stop_locked(sc); 2313 mvneta_sc_unlock(sc); 2314 } 2315 2316 STATIC int 2317 mvneta_mediachange(struct ifnet *ifp) 2318 { 2319 struct mvneta_softc *sc; 2320 2321 sc = ifp->if_softc; 2322 2323 if (!sc->phy_attached && !sc->use_inband_status) { 2324 /* We shouldn't be here */ 2325 if_printf(ifp, "Cannot change media in fixed-link mode!\n"); 2326 return (0); 2327 } 2328 2329 if (sc->use_inband_status) { 2330 mvneta_update_media(sc, sc->mvneta_ifmedia.ifm_media); 2331 return (0); 2332 } 2333 2334 mvneta_sc_lock(sc); 2335 2336 /* Update PHY */ 2337 mii_mediachg(sc->mii); 2338 2339 mvneta_sc_unlock(sc); 2340 2341 return (0); 2342 } 2343 2344 STATIC void 2345 mvneta_get_media(struct mvneta_softc *sc, struct ifmediareq *ifmr) 2346 { 2347 uint32_t psr; 2348 2349 psr = MVNETA_READ(sc, MVNETA_PSR); 2350 2351 /* Speed */ 2352 if (psr & MVNETA_PSR_GMIISPEED) 2353 ifmr->ifm_active = IFM_ETHER_SUBTYPE_SET(IFM_1000_T); 2354 else if (psr & MVNETA_PSR_MIISPEED) 2355 ifmr->ifm_active = IFM_ETHER_SUBTYPE_SET(IFM_100_TX); 2356 else if (psr & MVNETA_PSR_LINKUP) 2357 ifmr->ifm_active = IFM_ETHER_SUBTYPE_SET(IFM_10_T); 2358 2359 /* Duplex */ 2360 if (psr & MVNETA_PSR_FULLDX) 2361 ifmr->ifm_active |= IFM_FDX; 2362 2363 /* Link */ 2364 ifmr->ifm_status = IFM_AVALID; 2365 if (psr & MVNETA_PSR_LINKUP) 2366 ifmr->ifm_status |= IFM_ACTIVE; 2367 } 2368 2369 STATIC void 2370 mvneta_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 2371 { 2372 struct mvneta_softc *sc; 2373 struct mii_data *mii; 2374 2375 sc = ifp->if_softc; 2376 2377 if (!sc->phy_attached && !sc->use_inband_status) { 2378 ifmr->ifm_status = IFM_AVALID | IFM_ACTIVE; 2379 return; 2380 } 2381 2382 mvneta_sc_lock(sc); 2383 2384 if (sc->use_inband_status) { 2385 mvneta_get_media(sc, ifmr); 2386 mvneta_sc_unlock(sc); 2387 return; 2388 } 2389 2390 mii = sc->mii; 2391 mii_pollstat(mii); 2392 2393 ifmr->ifm_active = mii->mii_media_active; 2394 ifmr->ifm_status = mii->mii_media_status; 2395 2396 mvneta_sc_unlock(sc); 2397 } 2398 2399 /* 2400 * Link State Notify 2401 */ 2402 STATIC void 2403 mvneta_update_autoneg(struct mvneta_softc *sc, int enable) 2404 { 2405 int reg; 2406 2407 if (enable) { 2408 reg = MVNETA_READ(sc, MVNETA_PANC); 2409 reg &= ~(MVNETA_PANC_FORCELINKFAIL | MVNETA_PANC_FORCELINKPASS | 2410 MVNETA_PANC_ANFCEN); 2411 reg |= MVNETA_PANC_ANDUPLEXEN | MVNETA_PANC_ANSPEEDEN | 2412 MVNETA_PANC_INBANDANEN; 2413 MVNETA_WRITE(sc, MVNETA_PANC, reg); 2414 2415 reg = MVNETA_READ(sc, MVNETA_PMACC2); 2416 reg |= MVNETA_PMACC2_INBANDANMODE; 2417 MVNETA_WRITE(sc, MVNETA_PMACC2, reg); 2418 2419 reg = MVNETA_READ(sc, MVNETA_PSOMSCD); 2420 reg |= MVNETA_PSOMSCD_ENABLE; 2421 MVNETA_WRITE(sc, MVNETA_PSOMSCD, reg); 2422 } else { 2423 reg = MVNETA_READ(sc, MVNETA_PANC); 2424 reg &= ~(MVNETA_PANC_FORCELINKFAIL | MVNETA_PANC_FORCELINKPASS | 2425 MVNETA_PANC_ANDUPLEXEN | MVNETA_PANC_ANSPEEDEN | 2426 MVNETA_PANC_INBANDANEN); 2427 MVNETA_WRITE(sc, MVNETA_PANC, reg); 2428 2429 reg = MVNETA_READ(sc, MVNETA_PMACC2); 2430 reg &= ~MVNETA_PMACC2_INBANDANMODE; 2431 MVNETA_WRITE(sc, MVNETA_PMACC2, reg); 2432 2433 reg = MVNETA_READ(sc, MVNETA_PSOMSCD); 2434 reg &= ~MVNETA_PSOMSCD_ENABLE; 2435 MVNETA_WRITE(sc, MVNETA_PSOMSCD, reg); 2436 } 2437 } 2438 2439 STATIC int 2440 mvneta_update_media(struct mvneta_softc *sc, int media) 2441 { 2442 int reg, err; 2443 boolean_t running; 2444 2445 err = 0; 2446 2447 mvneta_sc_lock(sc); 2448 2449 mvneta_linkreset(sc); 2450 2451 running = (sc->ifp->if_drv_flags & IFF_DRV_RUNNING) != 0; 2452 if (running) 2453 mvneta_stop_locked(sc); 2454 2455 sc->autoneg = (IFM_SUBTYPE(media) == IFM_AUTO); 2456 2457 if (sc->use_inband_status) 2458 mvneta_update_autoneg(sc, IFM_SUBTYPE(media) == IFM_AUTO); 2459 2460 mvneta_update_eee(sc); 2461 mvneta_update_fc(sc); 2462 2463 if (IFM_SUBTYPE(media) != IFM_AUTO) { 2464 reg = MVNETA_READ(sc, MVNETA_PANC); 2465 reg &= ~(MVNETA_PANC_SETGMIISPEED | 2466 MVNETA_PANC_SETMIISPEED | 2467 MVNETA_PANC_SETFULLDX); 2468 if (IFM_SUBTYPE(media) == IFM_1000_T || 2469 IFM_SUBTYPE(media) == IFM_2500_T) { 2470 if ((media & IFM_FDX) == 0) { 2471 device_printf(sc->dev, 2472 "%s half-duplex unsupported\n", 2473 IFM_SUBTYPE(media) == IFM_1000_T ? 2474 "1000Base-T" : 2475 "2500Base-T"); 2476 err = EINVAL; 2477 goto out; 2478 } 2479 reg |= MVNETA_PANC_SETGMIISPEED; 2480 } else if (IFM_SUBTYPE(media) == IFM_100_TX) 2481 reg |= MVNETA_PANC_SETMIISPEED; 2482 2483 if (media & IFM_FDX) 2484 reg |= MVNETA_PANC_SETFULLDX; 2485 2486 MVNETA_WRITE(sc, MVNETA_PANC, reg); 2487 } 2488 out: 2489 if (running) 2490 mvneta_init_locked(sc); 2491 mvneta_sc_unlock(sc); 2492 return (err); 2493 } 2494 2495 STATIC void 2496 mvneta_adjust_link(struct mvneta_softc *sc) 2497 { 2498 boolean_t phy_linkup; 2499 int reg; 2500 2501 /* Update eee/fc */ 2502 mvneta_update_eee(sc); 2503 mvneta_update_fc(sc); 2504 2505 /* Check for link change */ 2506 phy_linkup = (sc->mii->mii_media_status & 2507 (IFM_AVALID | IFM_ACTIVE)) == (IFM_AVALID | IFM_ACTIVE); 2508 2509 if (sc->linkup != phy_linkup) 2510 mvneta_linkupdate(sc, phy_linkup); 2511 2512 /* Don't update media on disabled link */ 2513 if (!phy_linkup) 2514 return; 2515 2516 /* Check for media type change */ 2517 if (sc->mvneta_media != sc->mii->mii_media_active) { 2518 sc->mvneta_media = sc->mii->mii_media_active; 2519 2520 reg = MVNETA_READ(sc, MVNETA_PANC); 2521 reg &= ~(MVNETA_PANC_SETGMIISPEED | 2522 MVNETA_PANC_SETMIISPEED | 2523 MVNETA_PANC_SETFULLDX); 2524 if (IFM_SUBTYPE(sc->mvneta_media) == IFM_1000_T || 2525 IFM_SUBTYPE(sc->mvneta_media) == IFM_2500_T) { 2526 reg |= MVNETA_PANC_SETGMIISPEED; 2527 } else if (IFM_SUBTYPE(sc->mvneta_media) == IFM_100_TX) 2528 reg |= MVNETA_PANC_SETMIISPEED; 2529 2530 if (sc->mvneta_media & IFM_FDX) 2531 reg |= MVNETA_PANC_SETFULLDX; 2532 2533 MVNETA_WRITE(sc, MVNETA_PANC, reg); 2534 } 2535 } 2536 2537 STATIC void 2538 mvneta_link_isr(struct mvneta_softc *sc) 2539 { 2540 int linkup; 2541 2542 KASSERT_SC_MTX(sc); 2543 2544 linkup = MVNETA_IS_LINKUP(sc) ? TRUE : FALSE; 2545 if (sc->linkup == linkup) 2546 return; 2547 2548 if (linkup == TRUE) 2549 mvneta_linkup(sc); 2550 else 2551 mvneta_linkdown(sc); 2552 2553 #ifdef DEBUG 2554 log(LOG_DEBUG, 2555 "%s: link %s\n", device_xname(sc->dev), linkup ? "up" : "down"); 2556 #endif 2557 } 2558 2559 STATIC void 2560 mvneta_linkupdate(struct mvneta_softc *sc, boolean_t linkup) 2561 { 2562 2563 KASSERT_SC_MTX(sc); 2564 2565 if (linkup == TRUE) 2566 mvneta_linkup(sc); 2567 else 2568 mvneta_linkdown(sc); 2569 2570 #ifdef DEBUG 2571 log(LOG_DEBUG, 2572 "%s: link %s\n", device_xname(sc->dev), linkup ? "up" : "down"); 2573 #endif 2574 } 2575 2576 STATIC void 2577 mvneta_update_eee(struct mvneta_softc *sc) 2578 { 2579 uint32_t reg; 2580 2581 KASSERT_SC_MTX(sc); 2582 2583 /* set EEE parameters */ 2584 reg = MVNETA_READ(sc, MVNETA_LPIC1); 2585 if (sc->cf_lpi) 2586 reg |= MVNETA_LPIC1_LPIRE; 2587 else 2588 reg &= ~MVNETA_LPIC1_LPIRE; 2589 MVNETA_WRITE(sc, MVNETA_LPIC1, reg); 2590 } 2591 2592 STATIC void 2593 mvneta_update_fc(struct mvneta_softc *sc) 2594 { 2595 uint32_t reg; 2596 2597 KASSERT_SC_MTX(sc); 2598 2599 reg = MVNETA_READ(sc, MVNETA_PANC); 2600 if (sc->cf_fc) { 2601 /* Flow control negotiation */ 2602 reg |= MVNETA_PANC_PAUSEADV; 2603 reg |= MVNETA_PANC_ANFCEN; 2604 } else { 2605 /* Disable flow control negotiation */ 2606 reg &= ~MVNETA_PANC_PAUSEADV; 2607 reg &= ~MVNETA_PANC_ANFCEN; 2608 } 2609 2610 MVNETA_WRITE(sc, MVNETA_PANC, reg); 2611 } 2612 2613 STATIC void 2614 mvneta_linkup(struct mvneta_softc *sc) 2615 { 2616 uint32_t reg; 2617 2618 KASSERT_SC_MTX(sc); 2619 2620 if (!sc->use_inband_status) { 2621 reg = MVNETA_READ(sc, MVNETA_PANC); 2622 reg |= MVNETA_PANC_FORCELINKPASS; 2623 reg &= ~MVNETA_PANC_FORCELINKFAIL; 2624 MVNETA_WRITE(sc, MVNETA_PANC, reg); 2625 } 2626 2627 mvneta_qflush(sc->ifp); 2628 mvneta_portup(sc); 2629 sc->linkup = TRUE; 2630 if_link_state_change(sc->ifp, LINK_STATE_UP); 2631 } 2632 2633 STATIC void 2634 mvneta_linkdown(struct mvneta_softc *sc) 2635 { 2636 uint32_t reg; 2637 2638 KASSERT_SC_MTX(sc); 2639 2640 if (!sc->use_inband_status) { 2641 reg = MVNETA_READ(sc, MVNETA_PANC); 2642 reg &= ~MVNETA_PANC_FORCELINKPASS; 2643 reg |= MVNETA_PANC_FORCELINKFAIL; 2644 MVNETA_WRITE(sc, MVNETA_PANC, reg); 2645 } 2646 2647 mvneta_portdown(sc); 2648 mvneta_qflush(sc->ifp); 2649 sc->linkup = FALSE; 2650 if_link_state_change(sc->ifp, LINK_STATE_DOWN); 2651 } 2652 2653 STATIC void 2654 mvneta_linkreset(struct mvneta_softc *sc) 2655 { 2656 struct mii_softc *mii; 2657 2658 if (sc->phy_attached) { 2659 /* Force reset PHY */ 2660 mii = LIST_FIRST(&sc->mii->mii_phys); 2661 if (mii) 2662 mii_phy_reset(mii); 2663 } 2664 } 2665 2666 /* 2667 * Tx Subroutines 2668 */ 2669 STATIC int 2670 mvneta_tx_queue(struct mvneta_softc *sc, struct mbuf **mbufp, int q) 2671 { 2672 struct ifnet *ifp; 2673 bus_dma_segment_t txsegs[MVNETA_TX_SEGLIMIT]; 2674 struct mbuf *mtmp, *mbuf; 2675 struct mvneta_tx_ring *tx; 2676 struct mvneta_buf *txbuf; 2677 struct mvneta_tx_desc *t; 2678 uint32_t ptxsu; 2679 int start, used, error, i, txnsegs; 2680 2681 mbuf = *mbufp; 2682 tx = MVNETA_TX_RING(sc, q); 2683 DASSERT(tx->used >= 0); 2684 DASSERT(tx->used <= MVNETA_TX_RING_CNT); 2685 t = NULL; 2686 ifp = sc->ifp; 2687 2688 if (__predict_false(mbuf->m_flags & M_VLANTAG)) { 2689 mbuf = ether_vlanencap(mbuf, mbuf->m_pkthdr.ether_vtag); 2690 if (mbuf == NULL) { 2691 tx->drv_error++; 2692 *mbufp = NULL; 2693 return (ENOBUFS); 2694 } 2695 mbuf->m_flags &= ~M_VLANTAG; 2696 *mbufp = mbuf; 2697 } 2698 2699 if (__predict_false(mbuf->m_next != NULL && 2700 (mbuf->m_pkthdr.csum_flags & 2701 (CSUM_IP | CSUM_TCP | CSUM_UDP)) != 0)) { 2702 if (M_WRITABLE(mbuf) == 0) { 2703 mtmp = m_dup(mbuf, M_NOWAIT); 2704 m_freem(mbuf); 2705 if (mtmp == NULL) { 2706 tx->drv_error++; 2707 *mbufp = NULL; 2708 return (ENOBUFS); 2709 } 2710 *mbufp = mbuf = mtmp; 2711 } 2712 } 2713 2714 /* load mbuf using dmamap of 1st descriptor */ 2715 txbuf = &tx->txbuf[tx->cpu]; 2716 error = bus_dmamap_load_mbuf_sg(sc->txmbuf_dtag, 2717 txbuf->dmap, mbuf, txsegs, &txnsegs, 2718 BUS_DMA_NOWAIT); 2719 if (__predict_false(error != 0)) { 2720 #ifdef MVNETA_KTR 2721 CTR3(KTR_SPARE2, "%s:%u bus_dmamap_load_mbuf_sg error=%d", ifp->if_xname, q, error); 2722 #endif 2723 /* This is the only recoverable error (except EFBIG). */ 2724 if (error != ENOMEM) { 2725 tx->drv_error++; 2726 m_freem(mbuf); 2727 *mbufp = NULL; 2728 return (ENOBUFS); 2729 } 2730 return (error); 2731 } 2732 2733 if (__predict_false(txnsegs <= 0 2734 || (txnsegs + tx->used) > MVNETA_TX_RING_CNT)) { 2735 /* we have no enough descriptors or mbuf is broken */ 2736 #ifdef MVNETA_KTR 2737 CTR3(KTR_SPARE2, "%s:%u not enough descriptors txnsegs=%d", 2738 ifp->if_xname, q, txnsegs); 2739 #endif 2740 bus_dmamap_unload(sc->txmbuf_dtag, txbuf->dmap); 2741 return (ENOBUFS); 2742 } 2743 DASSERT(txbuf->m == NULL); 2744 2745 /* remember mbuf using 1st descriptor */ 2746 txbuf->m = mbuf; 2747 bus_dmamap_sync(sc->txmbuf_dtag, txbuf->dmap, 2748 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2749 2750 /* load to tx descriptors */ 2751 start = tx->cpu; 2752 used = 0; 2753 for (i = 0; i < txnsegs; i++) { 2754 t = &tx->desc[tx->cpu]; 2755 t->command = 0; 2756 t->l4ichk = 0; 2757 t->flags = 0; 2758 if (__predict_true(i == 0)) { 2759 /* 1st descriptor */ 2760 t->command |= MVNETA_TX_CMD_W_PACKET_OFFSET(0); 2761 t->command |= MVNETA_TX_CMD_F; 2762 mvneta_tx_set_csumflag(ifp, t, mbuf); 2763 } 2764 t->bufptr_pa = txsegs[i].ds_addr; 2765 t->bytecnt = txsegs[i].ds_len; 2766 tx->cpu = tx_counter_adv(tx->cpu, 1); 2767 2768 tx->used++; 2769 used++; 2770 } 2771 /* t is last descriptor here */ 2772 DASSERT(t != NULL); 2773 t->command |= MVNETA_TX_CMD_L|MVNETA_TX_CMD_PADDING; 2774 2775 bus_dmamap_sync(sc->tx_dtag, tx->desc_map, 2776 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2777 2778 while (__predict_false(used > 255)) { 2779 ptxsu = MVNETA_PTXSU_NOWD(255); 2780 MVNETA_WRITE(sc, MVNETA_PTXSU(q), ptxsu); 2781 used -= 255; 2782 } 2783 if (__predict_true(used > 0)) { 2784 ptxsu = MVNETA_PTXSU_NOWD(used); 2785 MVNETA_WRITE(sc, MVNETA_PTXSU(q), ptxsu); 2786 } 2787 return (0); 2788 } 2789 2790 STATIC void 2791 mvneta_tx_set_csumflag(struct ifnet *ifp, 2792 struct mvneta_tx_desc *t, struct mbuf *m) 2793 { 2794 struct ether_header *eh; 2795 int csum_flags; 2796 uint32_t iphl, ipoff; 2797 struct ip *ip; 2798 2799 iphl = ipoff = 0; 2800 csum_flags = ifp->if_hwassist & m->m_pkthdr.csum_flags; 2801 eh = mtod(m, struct ether_header *); 2802 switch (ntohs(eh->ether_type)) { 2803 case ETHERTYPE_IP: 2804 ipoff = ETHER_HDR_LEN; 2805 break; 2806 case ETHERTYPE_IPV6: 2807 return; 2808 case ETHERTYPE_VLAN: 2809 ipoff = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 2810 break; 2811 } 2812 2813 if (__predict_true(csum_flags & (CSUM_IP|CSUM_IP_TCP|CSUM_IP_UDP))) { 2814 ip = (struct ip *)(m->m_data + ipoff); 2815 iphl = ip->ip_hl<<2; 2816 t->command |= MVNETA_TX_CMD_L3_IP4; 2817 } else { 2818 t->command |= MVNETA_TX_CMD_L4_CHECKSUM_NONE; 2819 return; 2820 } 2821 2822 2823 /* L3 */ 2824 if (csum_flags & CSUM_IP) { 2825 t->command |= MVNETA_TX_CMD_IP4_CHECKSUM; 2826 } 2827 2828 /* L4 */ 2829 if (csum_flags & CSUM_IP_TCP) { 2830 t->command |= MVNETA_TX_CMD_L4_CHECKSUM_NOFRAG; 2831 t->command |= MVNETA_TX_CMD_L4_TCP; 2832 } else if (csum_flags & CSUM_IP_UDP) { 2833 t->command |= MVNETA_TX_CMD_L4_CHECKSUM_NOFRAG; 2834 t->command |= MVNETA_TX_CMD_L4_UDP; 2835 } else 2836 t->command |= MVNETA_TX_CMD_L4_CHECKSUM_NONE; 2837 2838 t->l4ichk = 0; 2839 t->command |= MVNETA_TX_CMD_IP_HEADER_LEN(iphl >> 2); 2840 t->command |= MVNETA_TX_CMD_L3_OFFSET(ipoff); 2841 } 2842 2843 STATIC void 2844 mvneta_tx_queue_complete(struct mvneta_softc *sc, int q) 2845 { 2846 struct mvneta_tx_ring *tx; 2847 struct mvneta_buf *txbuf; 2848 struct mvneta_tx_desc *t; 2849 uint32_t ptxs, ptxsu, ndesc; 2850 int i; 2851 2852 KASSERT_TX_MTX(sc, q); 2853 2854 tx = MVNETA_TX_RING(sc, q); 2855 if (__predict_false(tx->queue_status == MVNETA_QUEUE_DISABLED)) 2856 return; 2857 2858 ptxs = MVNETA_READ(sc, MVNETA_PTXS(q)); 2859 ndesc = MVNETA_PTXS_GET_TBC(ptxs); 2860 2861 if (__predict_false(ndesc == 0)) { 2862 if (tx->used == 0) 2863 tx->queue_status = MVNETA_QUEUE_IDLE; 2864 else if (tx->queue_status == MVNETA_QUEUE_WORKING && 2865 ((ticks - tx->watchdog_time) > MVNETA_WATCHDOG)) 2866 tx->queue_hung = TRUE; 2867 return; 2868 } 2869 2870 #ifdef MVNETA_KTR 2871 CTR3(KTR_SPARE2, "%s:%u tx_complete begin ndesc=%u", 2872 sc->ifp->if_xname, q, ndesc); 2873 #endif 2874 2875 bus_dmamap_sync(sc->tx_dtag, tx->desc_map, 2876 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2877 2878 for (i = 0; i < ndesc; i++) { 2879 t = &tx->desc[tx->dma]; 2880 #ifdef MVNETA_KTR 2881 if (t->flags & MVNETA_TX_F_ES) 2882 CTR3(KTR_SPARE2, "%s tx error queue %d desc %d", 2883 sc->ifp->if_xname, q, tx->dma); 2884 #endif 2885 txbuf = &tx->txbuf[tx->dma]; 2886 if (__predict_true(txbuf->m != NULL)) { 2887 DASSERT((t->command & MVNETA_TX_CMD_F) != 0); 2888 bus_dmamap_unload(sc->txmbuf_dtag, txbuf->dmap); 2889 m_freem(txbuf->m); 2890 txbuf->m = NULL; 2891 } 2892 else 2893 DASSERT((t->flags & MVNETA_TX_CMD_F) == 0); 2894 tx->dma = tx_counter_adv(tx->dma, 1); 2895 tx->used--; 2896 } 2897 DASSERT(tx->used >= 0); 2898 DASSERT(tx->used <= MVNETA_TX_RING_CNT); 2899 while (__predict_false(ndesc > 255)) { 2900 ptxsu = MVNETA_PTXSU_NORB(255); 2901 MVNETA_WRITE(sc, MVNETA_PTXSU(q), ptxsu); 2902 ndesc -= 255; 2903 } 2904 if (__predict_true(ndesc > 0)) { 2905 ptxsu = MVNETA_PTXSU_NORB(ndesc); 2906 MVNETA_WRITE(sc, MVNETA_PTXSU(q), ptxsu); 2907 } 2908 #ifdef MVNETA_KTR 2909 CTR5(KTR_SPARE2, "%s:%u tx_complete tx_cpu=%d tx_dma=%d tx_used=%d", 2910 sc->ifp->if_xname, q, tx->cpu, tx->dma, tx->used); 2911 #endif 2912 2913 tx->watchdog_time = ticks; 2914 2915 if (tx->used == 0) 2916 tx->queue_status = MVNETA_QUEUE_IDLE; 2917 } 2918 2919 /* 2920 * Do a final TX complete when TX is idle. 2921 */ 2922 STATIC void 2923 mvneta_tx_drain(struct mvneta_softc *sc) 2924 { 2925 struct mvneta_tx_ring *tx; 2926 int q; 2927 2928 /* 2929 * Handle trailing mbuf on TX queue. 2930 * Check is done lockess to avoid TX path contention. 2931 */ 2932 for (q = 0; q < MVNETA_TX_QNUM_MAX; q++) { 2933 tx = MVNETA_TX_RING(sc, q); 2934 if ((ticks - tx->watchdog_time) > MVNETA_WATCHDOG_TXCOMP && 2935 tx->used > 0) { 2936 mvneta_tx_lockq(sc, q); 2937 mvneta_tx_queue_complete(sc, q); 2938 mvneta_tx_unlockq(sc, q); 2939 } 2940 } 2941 } 2942 2943 /* 2944 * Rx Subroutines 2945 */ 2946 STATIC int 2947 mvneta_rx(struct mvneta_softc *sc, int q, int count) 2948 { 2949 uint32_t prxs, npkt; 2950 int more; 2951 2952 more = 0; 2953 mvneta_rx_lockq(sc, q); 2954 prxs = MVNETA_READ(sc, MVNETA_PRXS(q)); 2955 npkt = MVNETA_PRXS_GET_ODC(prxs); 2956 if (__predict_false(npkt == 0)) 2957 goto out; 2958 2959 if (count > 0 && npkt > count) { 2960 more = 1; 2961 npkt = count; 2962 } 2963 mvneta_rx_queue(sc, q, npkt); 2964 out: 2965 mvneta_rx_unlockq(sc, q); 2966 return more; 2967 } 2968 2969 /* 2970 * Helper routine for updating PRXSU register of a given queue. 2971 * Handles number of processed descriptors bigger than maximum acceptable value. 2972 */ 2973 STATIC __inline void 2974 mvneta_prxsu_update(struct mvneta_softc *sc, int q, int processed) 2975 { 2976 uint32_t prxsu; 2977 2978 while (__predict_false(processed > 255)) { 2979 prxsu = MVNETA_PRXSU_NOOFPROCESSEDDESCRIPTORS(255); 2980 MVNETA_WRITE(sc, MVNETA_PRXSU(q), prxsu); 2981 processed -= 255; 2982 } 2983 prxsu = MVNETA_PRXSU_NOOFPROCESSEDDESCRIPTORS(processed); 2984 MVNETA_WRITE(sc, MVNETA_PRXSU(q), prxsu); 2985 } 2986 2987 static __inline void 2988 mvneta_prefetch(void *p) 2989 { 2990 2991 __builtin_prefetch(p); 2992 } 2993 2994 STATIC void 2995 mvneta_rx_queue(struct mvneta_softc *sc, int q, int npkt) 2996 { 2997 struct ifnet *ifp; 2998 struct mvneta_rx_ring *rx; 2999 struct mvneta_rx_desc *r; 3000 struct mvneta_buf *rxbuf; 3001 struct mbuf *m; 3002 struct lro_ctrl *lro; 3003 struct lro_entry *queued; 3004 void *pktbuf; 3005 int i, pktlen, processed, ndma; 3006 3007 KASSERT_RX_MTX(sc, q); 3008 3009 ifp = sc->ifp; 3010 rx = MVNETA_RX_RING(sc, q); 3011 processed = 0; 3012 3013 if (__predict_false(rx->queue_status == MVNETA_QUEUE_DISABLED)) 3014 return; 3015 3016 bus_dmamap_sync(sc->rx_dtag, rx->desc_map, 3017 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3018 3019 for (i = 0; i < npkt; i++) { 3020 /* Prefetch next desc, rxbuf. */ 3021 ndma = rx_counter_adv(rx->dma, 1); 3022 mvneta_prefetch(&rx->desc[ndma]); 3023 mvneta_prefetch(&rx->rxbuf[ndma]); 3024 3025 /* get descriptor and packet */ 3026 r = &rx->desc[rx->dma]; 3027 rxbuf = &rx->rxbuf[rx->dma]; 3028 m = rxbuf->m; 3029 rxbuf->m = NULL; 3030 DASSERT(m != NULL); 3031 bus_dmamap_sync(sc->rxbuf_dtag, rxbuf->dmap, 3032 BUS_DMASYNC_POSTREAD); 3033 bus_dmamap_unload(sc->rxbuf_dtag, rxbuf->dmap); 3034 /* Prefetch mbuf header. */ 3035 mvneta_prefetch(m); 3036 3037 processed++; 3038 /* Drop desc with error status or not in a single buffer. */ 3039 DASSERT((r->status & (MVNETA_RX_F|MVNETA_RX_L)) == 3040 (MVNETA_RX_F|MVNETA_RX_L)); 3041 if (__predict_false((r->status & MVNETA_RX_ES) || 3042 (r->status & (MVNETA_RX_F|MVNETA_RX_L)) != 3043 (MVNETA_RX_F|MVNETA_RX_L))) 3044 goto rx_error; 3045 3046 /* 3047 * [ OFF | MH | PKT | CRC ] 3048 * bytecnt cover MH, PKT, CRC 3049 */ 3050 pktlen = r->bytecnt - ETHER_CRC_LEN - MVNETA_HWHEADER_SIZE; 3051 pktbuf = (uint8_t *)rx->rxbuf_virt_addr[rx->dma] + MVNETA_PACKET_OFFSET + 3052 MVNETA_HWHEADER_SIZE; 3053 3054 /* Prefetch mbuf data. */ 3055 mvneta_prefetch(pktbuf); 3056 3057 /* Write value to mbuf (avoid read). */ 3058 m->m_data = pktbuf; 3059 m->m_len = m->m_pkthdr.len = pktlen; 3060 m->m_pkthdr.rcvif = ifp; 3061 mvneta_rx_set_csumflag(ifp, r, m); 3062 3063 /* Increase rx_dma before releasing the lock. */ 3064 rx->dma = ndma; 3065 3066 if (__predict_false(rx->lro_enabled && 3067 ((r->status & MVNETA_RX_L3_IP) != 0) && 3068 ((r->status & MVNETA_RX_L4_MASK) == MVNETA_RX_L4_TCP) && 3069 (m->m_pkthdr.csum_flags & 3070 (CSUM_DATA_VALID | CSUM_PSEUDO_HDR)) == 3071 (CSUM_DATA_VALID | CSUM_PSEUDO_HDR))) { 3072 if (rx->lro.lro_cnt != 0) { 3073 if (tcp_lro_rx(&rx->lro, m, 0) == 0) 3074 goto rx_done; 3075 } 3076 } 3077 3078 mvneta_rx_unlockq(sc, q); 3079 (*ifp->if_input)(ifp, m); 3080 mvneta_rx_lockq(sc, q); 3081 /* 3082 * Check whether this queue has been disabled in the 3083 * meantime. If yes, then clear LRO and exit. 3084 */ 3085 if(__predict_false(rx->queue_status == MVNETA_QUEUE_DISABLED)) 3086 goto rx_lro; 3087 rx_done: 3088 /* Refresh receive ring to avoid stall and minimize jitter. */ 3089 if (processed >= MVNETA_RX_REFILL_COUNT) { 3090 mvneta_prxsu_update(sc, q, processed); 3091 mvneta_rx_queue_refill(sc, q); 3092 processed = 0; 3093 } 3094 continue; 3095 rx_error: 3096 m_freem(m); 3097 rx->dma = ndma; 3098 /* Refresh receive ring to avoid stall and minimize jitter. */ 3099 if (processed >= MVNETA_RX_REFILL_COUNT) { 3100 mvneta_prxsu_update(sc, q, processed); 3101 mvneta_rx_queue_refill(sc, q); 3102 processed = 0; 3103 } 3104 } 3105 #ifdef MVNETA_KTR 3106 CTR3(KTR_SPARE2, "%s:%u %u packets received", ifp->if_xname, q, npkt); 3107 #endif 3108 /* DMA status update */ 3109 mvneta_prxsu_update(sc, q, processed); 3110 /* Refill the rest of buffers if there are any to refill */ 3111 mvneta_rx_queue_refill(sc, q); 3112 3113 rx_lro: 3114 /* 3115 * Flush any outstanding LRO work 3116 */ 3117 lro = &rx->lro; 3118 while (__predict_false((queued = LIST_FIRST(&lro->lro_active)) != NULL)) { 3119 LIST_REMOVE(LIST_FIRST((&lro->lro_active)), next); 3120 tcp_lro_flush(lro, queued); 3121 } 3122 } 3123 3124 STATIC void 3125 mvneta_rx_buf_free(struct mvneta_softc *sc, struct mvneta_buf *rxbuf) 3126 { 3127 3128 bus_dmamap_unload(sc->rxbuf_dtag, rxbuf->dmap); 3129 /* This will remove all data at once */ 3130 m_freem(rxbuf->m); 3131 } 3132 3133 STATIC void 3134 mvneta_rx_queue_refill(struct mvneta_softc *sc, int q) 3135 { 3136 struct mvneta_rx_ring *rx; 3137 struct mvneta_rx_desc *r; 3138 struct mvneta_buf *rxbuf; 3139 bus_dma_segment_t segs; 3140 struct mbuf *m; 3141 uint32_t prxs, prxsu, ndesc; 3142 int npkt, refill, nsegs, error; 3143 3144 KASSERT_RX_MTX(sc, q); 3145 3146 rx = MVNETA_RX_RING(sc, q); 3147 prxs = MVNETA_READ(sc, MVNETA_PRXS(q)); 3148 ndesc = MVNETA_PRXS_GET_NODC(prxs) + MVNETA_PRXS_GET_ODC(prxs); 3149 refill = MVNETA_RX_RING_CNT - ndesc; 3150 #ifdef MVNETA_KTR 3151 CTR3(KTR_SPARE2, "%s:%u refill %u packets", sc->ifp->if_xname, q, 3152 refill); 3153 #endif 3154 if (__predict_false(refill <= 0)) 3155 return; 3156 3157 for (npkt = 0; npkt < refill; npkt++) { 3158 rxbuf = &rx->rxbuf[rx->cpu]; 3159 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 3160 if (__predict_false(m == NULL)) { 3161 error = ENOBUFS; 3162 break; 3163 } 3164 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 3165 3166 error = bus_dmamap_load_mbuf_sg(sc->rxbuf_dtag, rxbuf->dmap, 3167 m, &segs, &nsegs, BUS_DMA_NOWAIT); 3168 if (__predict_false(error != 0 || nsegs != 1)) { 3169 KASSERT(1, ("Failed to load Rx mbuf DMA map")); 3170 m_freem(m); 3171 break; 3172 } 3173 3174 /* Add the packet to the ring */ 3175 rxbuf->m = m; 3176 r = &rx->desc[rx->cpu]; 3177 r->bufptr_pa = segs.ds_addr; 3178 rx->rxbuf_virt_addr[rx->cpu] = m->m_data; 3179 3180 rx->cpu = rx_counter_adv(rx->cpu, 1); 3181 } 3182 if (npkt == 0) { 3183 if (refill == MVNETA_RX_RING_CNT) 3184 rx->needs_refill = TRUE; 3185 return; 3186 } 3187 3188 rx->needs_refill = FALSE; 3189 bus_dmamap_sync(sc->rx_dtag, rx->desc_map, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3190 3191 while (__predict_false(npkt > 255)) { 3192 prxsu = MVNETA_PRXSU_NOOFNEWDESCRIPTORS(255); 3193 MVNETA_WRITE(sc, MVNETA_PRXSU(q), prxsu); 3194 npkt -= 255; 3195 } 3196 if (__predict_true(npkt > 0)) { 3197 prxsu = MVNETA_PRXSU_NOOFNEWDESCRIPTORS(npkt); 3198 MVNETA_WRITE(sc, MVNETA_PRXSU(q), prxsu); 3199 } 3200 } 3201 3202 STATIC __inline void 3203 mvneta_rx_set_csumflag(struct ifnet *ifp, 3204 struct mvneta_rx_desc *r, struct mbuf *m) 3205 { 3206 uint32_t csum_flags; 3207 3208 csum_flags = 0; 3209 if (__predict_false((r->status & 3210 (MVNETA_RX_IP_HEADER_OK|MVNETA_RX_L3_IP)) == 0)) 3211 return; /* not a IP packet */ 3212 3213 /* L3 */ 3214 if (__predict_true((r->status & MVNETA_RX_IP_HEADER_OK) == 3215 MVNETA_RX_IP_HEADER_OK)) 3216 csum_flags |= CSUM_L3_CALC|CSUM_L3_VALID; 3217 3218 if (__predict_true((r->status & (MVNETA_RX_IP_HEADER_OK|MVNETA_RX_L3_IP)) == 3219 (MVNETA_RX_IP_HEADER_OK|MVNETA_RX_L3_IP))) { 3220 /* L4 */ 3221 switch (r->status & MVNETA_RX_L4_MASK) { 3222 case MVNETA_RX_L4_TCP: 3223 case MVNETA_RX_L4_UDP: 3224 csum_flags |= CSUM_L4_CALC; 3225 if (__predict_true((r->status & 3226 MVNETA_RX_L4_CHECKSUM_OK) == MVNETA_RX_L4_CHECKSUM_OK)) { 3227 csum_flags |= CSUM_L4_VALID; 3228 m->m_pkthdr.csum_data = htons(0xffff); 3229 } 3230 break; 3231 case MVNETA_RX_L4_OTH: 3232 default: 3233 break; 3234 } 3235 } 3236 m->m_pkthdr.csum_flags = csum_flags; 3237 } 3238 3239 /* 3240 * MAC address filter 3241 */ 3242 STATIC void 3243 mvneta_filter_setup(struct mvneta_softc *sc) 3244 { 3245 struct ifnet *ifp; 3246 uint32_t dfut[MVNETA_NDFUT], dfsmt[MVNETA_NDFSMT], dfomt[MVNETA_NDFOMT]; 3247 uint32_t pxc; 3248 int i; 3249 3250 KASSERT_SC_MTX(sc); 3251 3252 memset(dfut, 0, sizeof(dfut)); 3253 memset(dfsmt, 0, sizeof(dfsmt)); 3254 memset(dfomt, 0, sizeof(dfomt)); 3255 3256 ifp = sc->ifp; 3257 ifp->if_flags |= IFF_ALLMULTI; 3258 if (ifp->if_flags & (IFF_ALLMULTI|IFF_PROMISC)) { 3259 for (i = 0; i < MVNETA_NDFSMT; i++) { 3260 dfsmt[i] = dfomt[i] = 3261 MVNETA_DF(0, MVNETA_DF_QUEUE(0) | MVNETA_DF_PASS) | 3262 MVNETA_DF(1, MVNETA_DF_QUEUE(0) | MVNETA_DF_PASS) | 3263 MVNETA_DF(2, MVNETA_DF_QUEUE(0) | MVNETA_DF_PASS) | 3264 MVNETA_DF(3, MVNETA_DF_QUEUE(0) | MVNETA_DF_PASS); 3265 } 3266 } 3267 3268 pxc = MVNETA_READ(sc, MVNETA_PXC); 3269 pxc &= ~(MVNETA_PXC_UPM | MVNETA_PXC_RXQ_MASK | MVNETA_PXC_RXQARP_MASK | 3270 MVNETA_PXC_TCPQ_MASK | MVNETA_PXC_UDPQ_MASK | MVNETA_PXC_BPDUQ_MASK); 3271 pxc |= MVNETA_PXC_RXQ(MVNETA_RX_QNUM_MAX-1); 3272 pxc |= MVNETA_PXC_RXQARP(MVNETA_RX_QNUM_MAX-1); 3273 pxc |= MVNETA_PXC_TCPQ(MVNETA_RX_QNUM_MAX-1); 3274 pxc |= MVNETA_PXC_UDPQ(MVNETA_RX_QNUM_MAX-1); 3275 pxc |= MVNETA_PXC_BPDUQ(MVNETA_RX_QNUM_MAX-1); 3276 pxc |= MVNETA_PXC_RB | MVNETA_PXC_RBIP | MVNETA_PXC_RBARP; 3277 if (ifp->if_flags & IFF_BROADCAST) { 3278 pxc &= ~(MVNETA_PXC_RB | MVNETA_PXC_RBIP | MVNETA_PXC_RBARP); 3279 } 3280 if (ifp->if_flags & IFF_PROMISC) { 3281 pxc |= MVNETA_PXC_UPM; 3282 } 3283 MVNETA_WRITE(sc, MVNETA_PXC, pxc); 3284 3285 /* Set Destination Address Filter Unicast Table */ 3286 if (ifp->if_flags & IFF_PROMISC) { 3287 /* pass all unicast addresses */ 3288 for (i = 0; i < MVNETA_NDFUT; i++) { 3289 dfut[i] = 3290 MVNETA_DF(0, MVNETA_DF_QUEUE(0) | MVNETA_DF_PASS) | 3291 MVNETA_DF(1, MVNETA_DF_QUEUE(0) | MVNETA_DF_PASS) | 3292 MVNETA_DF(2, MVNETA_DF_QUEUE(0) | MVNETA_DF_PASS) | 3293 MVNETA_DF(3, MVNETA_DF_QUEUE(0) | MVNETA_DF_PASS); 3294 } 3295 } else { 3296 i = sc->enaddr[5] & 0xf; /* last nibble */ 3297 dfut[i>>2] = MVNETA_DF(i&3, MVNETA_DF_QUEUE(0) | MVNETA_DF_PASS); 3298 } 3299 MVNETA_WRITE_REGION(sc, MVNETA_DFUT(0), dfut, MVNETA_NDFUT); 3300 3301 /* Set Destination Address Filter Multicast Tables */ 3302 MVNETA_WRITE_REGION(sc, MVNETA_DFSMT(0), dfsmt, MVNETA_NDFSMT); 3303 MVNETA_WRITE_REGION(sc, MVNETA_DFOMT(0), dfomt, MVNETA_NDFOMT); 3304 } 3305 3306 /* 3307 * sysctl(9) 3308 */ 3309 STATIC int 3310 sysctl_read_mib(SYSCTL_HANDLER_ARGS) 3311 { 3312 struct mvneta_sysctl_mib *arg; 3313 struct mvneta_softc *sc; 3314 uint64_t val; 3315 3316 arg = (struct mvneta_sysctl_mib *)arg1; 3317 if (arg == NULL) 3318 return (EINVAL); 3319 3320 sc = arg->sc; 3321 if (sc == NULL) 3322 return (EINVAL); 3323 if (arg->index < 0 || arg->index > MVNETA_PORTMIB_NOCOUNTER) 3324 return (EINVAL); 3325 3326 mvneta_sc_lock(sc); 3327 val = arg->counter; 3328 mvneta_sc_unlock(sc); 3329 return sysctl_handle_64(oidp, &val, 0, req); 3330 } 3331 3332 3333 STATIC int 3334 sysctl_clear_mib(SYSCTL_HANDLER_ARGS) 3335 { 3336 struct mvneta_softc *sc; 3337 int err, val; 3338 3339 val = 0; 3340 sc = (struct mvneta_softc *)arg1; 3341 if (sc == NULL) 3342 return (EINVAL); 3343 3344 err = sysctl_handle_int(oidp, &val, 0, req); 3345 if (err != 0) 3346 return (err); 3347 3348 if (val < 0 || val > 1) 3349 return (EINVAL); 3350 3351 if (val == 1) { 3352 mvneta_sc_lock(sc); 3353 mvneta_clear_mib(sc); 3354 mvneta_sc_unlock(sc); 3355 } 3356 3357 return (0); 3358 } 3359 3360 STATIC int 3361 sysctl_set_queue_rxthtime(SYSCTL_HANDLER_ARGS) 3362 { 3363 struct mvneta_sysctl_queue *arg; 3364 struct mvneta_rx_ring *rx; 3365 struct mvneta_softc *sc; 3366 uint32_t reg, time_mvtclk; 3367 int err, time_us; 3368 3369 rx = NULL; 3370 arg = (struct mvneta_sysctl_queue *)arg1; 3371 if (arg == NULL) 3372 return (EINVAL); 3373 if (arg->queue < 0 || arg->queue > MVNETA_RX_RING_CNT) 3374 return (EINVAL); 3375 if (arg->rxtx != MVNETA_SYSCTL_RX) 3376 return (EINVAL); 3377 3378 sc = arg->sc; 3379 if (sc == NULL) 3380 return (EINVAL); 3381 3382 /* read queue length */ 3383 mvneta_sc_lock(sc); 3384 mvneta_rx_lockq(sc, arg->queue); 3385 rx = MVNETA_RX_RING(sc, arg->queue); 3386 time_mvtclk = rx->queue_th_time; 3387 time_us = ((uint64_t)time_mvtclk * 1000ULL * 1000ULL) / mvneta_get_clk(); 3388 mvneta_rx_unlockq(sc, arg->queue); 3389 mvneta_sc_unlock(sc); 3390 3391 err = sysctl_handle_int(oidp, &time_us, 0, req); 3392 if (err != 0) 3393 return (err); 3394 3395 mvneta_sc_lock(sc); 3396 mvneta_rx_lockq(sc, arg->queue); 3397 3398 /* update queue length (0[sec] - 1[sec]) */ 3399 if (time_us < 0 || time_us > (1000 * 1000)) { 3400 mvneta_rx_unlockq(sc, arg->queue); 3401 mvneta_sc_unlock(sc); 3402 return (EINVAL); 3403 } 3404 time_mvtclk = 3405 (uint64_t)mvneta_get_clk() * (uint64_t)time_us / (1000ULL * 1000ULL); 3406 rx->queue_th_time = time_mvtclk; 3407 reg = MVNETA_PRXITTH_RITT(rx->queue_th_time); 3408 MVNETA_WRITE(sc, MVNETA_PRXITTH(arg->queue), reg); 3409 mvneta_rx_unlockq(sc, arg->queue); 3410 mvneta_sc_unlock(sc); 3411 3412 return (0); 3413 } 3414 3415 STATIC void 3416 sysctl_mvneta_init(struct mvneta_softc *sc) 3417 { 3418 struct sysctl_ctx_list *ctx; 3419 struct sysctl_oid_list *children; 3420 struct sysctl_oid_list *rxchildren; 3421 struct sysctl_oid_list *qchildren, *mchildren; 3422 struct sysctl_oid *tree; 3423 int i, q; 3424 struct mvneta_sysctl_queue *rxarg; 3425 #define MVNETA_SYSCTL_NAME(num) "queue" # num 3426 static const char *sysctl_queue_names[] = { 3427 MVNETA_SYSCTL_NAME(0), MVNETA_SYSCTL_NAME(1), 3428 MVNETA_SYSCTL_NAME(2), MVNETA_SYSCTL_NAME(3), 3429 MVNETA_SYSCTL_NAME(4), MVNETA_SYSCTL_NAME(5), 3430 MVNETA_SYSCTL_NAME(6), MVNETA_SYSCTL_NAME(7), 3431 }; 3432 #undef MVNETA_SYSCTL_NAME 3433 3434 #ifndef NO_SYSCTL_DESCR 3435 #define MVNETA_SYSCTL_DESCR(num) "configuration parameters for queue " # num 3436 static const char *sysctl_queue_descrs[] = { 3437 MVNETA_SYSCTL_DESCR(0), MVNETA_SYSCTL_DESCR(1), 3438 MVNETA_SYSCTL_DESCR(2), MVNETA_SYSCTL_DESCR(3), 3439 MVNETA_SYSCTL_DESCR(4), MVNETA_SYSCTL_DESCR(5), 3440 MVNETA_SYSCTL_DESCR(6), MVNETA_SYSCTL_DESCR(7), 3441 }; 3442 #undef MVNETA_SYSCTL_DESCR 3443 #endif 3444 3445 3446 ctx = device_get_sysctl_ctx(sc->dev); 3447 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)); 3448 3449 tree = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "rx", 3450 CTLFLAG_RD, 0, "NETA RX"); 3451 rxchildren = SYSCTL_CHILDREN(tree); 3452 tree = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "mib", 3453 CTLFLAG_RD, 0, "NETA MIB"); 3454 mchildren = SYSCTL_CHILDREN(tree); 3455 3456 3457 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "flow_control", 3458 CTLFLAG_RW, &sc->cf_fc, 0, "flow control"); 3459 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "lpi", 3460 CTLFLAG_RW, &sc->cf_lpi, 0, "Low Power Idle"); 3461 3462 /* 3463 * MIB access 3464 */ 3465 /* dev.mvneta.[unit].mib.<mibs> */ 3466 for (i = 0; i < MVNETA_PORTMIB_NOCOUNTER; i++) { 3467 struct mvneta_sysctl_mib *mib_arg = &sc->sysctl_mib[i]; 3468 3469 mib_arg->sc = sc; 3470 mib_arg->index = i; 3471 SYSCTL_ADD_PROC(ctx, mchildren, OID_AUTO, 3472 mvneta_mib_list[i].sysctl_name, 3473 CTLTYPE_U64|CTLFLAG_RD, (void *)mib_arg, 0, 3474 sysctl_read_mib, "I", mvneta_mib_list[i].desc); 3475 } 3476 SYSCTL_ADD_UQUAD(ctx, mchildren, OID_AUTO, "rx_discard", 3477 CTLFLAG_RD, &sc->counter_pdfc, "Port Rx Discard Frame Counter"); 3478 SYSCTL_ADD_UQUAD(ctx, mchildren, OID_AUTO, "overrun", 3479 CTLFLAG_RD, &sc->counter_pofc, "Port Overrun Frame Counter"); 3480 SYSCTL_ADD_UINT(ctx, mchildren, OID_AUTO, "watchdog", 3481 CTLFLAG_RD, &sc->counter_watchdog, 0, "TX Watchdog Counter"); 3482 3483 SYSCTL_ADD_PROC(ctx, mchildren, OID_AUTO, "reset", 3484 CTLTYPE_INT|CTLFLAG_RW, (void *)sc, 0, 3485 sysctl_clear_mib, "I", "Reset MIB counters"); 3486 3487 for (q = 0; q < MVNETA_RX_QNUM_MAX; q++) { 3488 rxarg = &sc->sysctl_rx_queue[q]; 3489 3490 rxarg->sc = sc; 3491 rxarg->queue = q; 3492 rxarg->rxtx = MVNETA_SYSCTL_RX; 3493 3494 /* hw.mvneta.mvneta[unit].rx.[queue] */ 3495 tree = SYSCTL_ADD_NODE(ctx, rxchildren, OID_AUTO, 3496 sysctl_queue_names[q], CTLFLAG_RD, 0, 3497 sysctl_queue_descrs[q]); 3498 qchildren = SYSCTL_CHILDREN(tree); 3499 3500 /* hw.mvneta.mvneta[unit].rx.[queue].threshold_timer_us */ 3501 SYSCTL_ADD_PROC(ctx, qchildren, OID_AUTO, "threshold_timer_us", 3502 CTLTYPE_UINT | CTLFLAG_RW, rxarg, 0, 3503 sysctl_set_queue_rxthtime, "I", 3504 "interrupt coalescing threshold timer [us]"); 3505 } 3506 } 3507 3508 /* 3509 * MIB 3510 */ 3511 STATIC void 3512 mvneta_clear_mib(struct mvneta_softc *sc) 3513 { 3514 int i; 3515 3516 KASSERT_SC_MTX(sc); 3517 3518 for (i = 0; i < nitems(mvneta_mib_list); i++) { 3519 if (mvneta_mib_list[i].reg64) 3520 MVNETA_READ_MIB_8(sc, mvneta_mib_list[i].regnum); 3521 else 3522 MVNETA_READ_MIB_4(sc, mvneta_mib_list[i].regnum); 3523 sc->sysctl_mib[i].counter = 0; 3524 } 3525 MVNETA_READ(sc, MVNETA_PDFC); 3526 sc->counter_pdfc = 0; 3527 MVNETA_READ(sc, MVNETA_POFC); 3528 sc->counter_pofc = 0; 3529 sc->counter_watchdog = 0; 3530 } 3531 3532 STATIC void 3533 mvneta_update_mib(struct mvneta_softc *sc) 3534 { 3535 struct mvneta_tx_ring *tx; 3536 int i; 3537 uint64_t val; 3538 uint32_t reg; 3539 3540 for (i = 0; i < nitems(mvneta_mib_list); i++) { 3541 3542 if (mvneta_mib_list[i].reg64) 3543 val = MVNETA_READ_MIB_8(sc, mvneta_mib_list[i].regnum); 3544 else 3545 val = MVNETA_READ_MIB_4(sc, mvneta_mib_list[i].regnum); 3546 3547 if (val == 0) 3548 continue; 3549 3550 sc->sysctl_mib[i].counter += val; 3551 switch (mvneta_mib_list[i].regnum) { 3552 case MVNETA_MIB_RX_GOOD_OCT: 3553 if_inc_counter(sc->ifp, IFCOUNTER_IBYTES, val); 3554 break; 3555 case MVNETA_MIB_RX_BAD_FRAME: 3556 if_inc_counter(sc->ifp, IFCOUNTER_IERRORS, val); 3557 break; 3558 case MVNETA_MIB_RX_GOOD_FRAME: 3559 if_inc_counter(sc->ifp, IFCOUNTER_IPACKETS, val); 3560 break; 3561 case MVNETA_MIB_RX_MCAST_FRAME: 3562 if_inc_counter(sc->ifp, IFCOUNTER_IMCASTS, val); 3563 break; 3564 case MVNETA_MIB_TX_GOOD_OCT: 3565 if_inc_counter(sc->ifp, IFCOUNTER_OBYTES, val); 3566 break; 3567 case MVNETA_MIB_TX_GOOD_FRAME: 3568 if_inc_counter(sc->ifp, IFCOUNTER_OPACKETS, val); 3569 break; 3570 case MVNETA_MIB_TX_MCAST_FRAME: 3571 if_inc_counter(sc->ifp, IFCOUNTER_OMCASTS, val); 3572 break; 3573 case MVNETA_MIB_MAC_COL: 3574 if_inc_counter(sc->ifp, IFCOUNTER_COLLISIONS, val); 3575 break; 3576 case MVNETA_MIB_TX_MAC_TRNS_ERR: 3577 case MVNETA_MIB_TX_EXCES_COL: 3578 case MVNETA_MIB_MAC_LATE_COL: 3579 if_inc_counter(sc->ifp, IFCOUNTER_OERRORS, val); 3580 break; 3581 } 3582 } 3583 3584 reg = MVNETA_READ(sc, MVNETA_PDFC); 3585 sc->counter_pdfc += reg; 3586 if_inc_counter(sc->ifp, IFCOUNTER_IQDROPS, reg); 3587 reg = MVNETA_READ(sc, MVNETA_POFC); 3588 sc->counter_pofc += reg; 3589 if_inc_counter(sc->ifp, IFCOUNTER_IQDROPS, reg); 3590 3591 /* TX watchdog. */ 3592 if (sc->counter_watchdog_mib > 0) { 3593 if_inc_counter(sc->ifp, IFCOUNTER_OERRORS, sc->counter_watchdog_mib); 3594 sc->counter_watchdog_mib = 0; 3595 } 3596 /* 3597 * TX driver errors: 3598 * We do not take queue locks to not disrupt TX path. 3599 * We may only miss one drv error which will be fixed at 3600 * next mib update. We may also clear counter when TX path 3601 * is incrementing it but we only do it if counter was not zero 3602 * thus we may only loose one error. 3603 */ 3604 for (i = 0; i < MVNETA_TX_QNUM_MAX; i++) { 3605 tx = MVNETA_TX_RING(sc, i); 3606 3607 if (tx->drv_error > 0) { 3608 if_inc_counter(sc->ifp, IFCOUNTER_OERRORS, tx->drv_error); 3609 tx->drv_error = 0; 3610 } 3611 } 3612 } 3613