1 /* 2 * Copyright (c) 2017 Stormshield. 3 * Copyright (c) 2017 Semihalf. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 24 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include "opt_platform.h" 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/endian.h> 35 #include <sys/mbuf.h> 36 #include <sys/lock.h> 37 #include <sys/mutex.h> 38 #include <sys/kernel.h> 39 #include <sys/module.h> 40 #include <sys/socket.h> 41 #include <sys/sysctl.h> 42 #include <sys/smp.h> 43 #include <sys/taskqueue.h> 44 #ifdef MVNETA_KTR 45 #include <sys/ktr.h> 46 #endif 47 48 #include <net/ethernet.h> 49 #include <net/bpf.h> 50 #include <net/if.h> 51 #include <net/if_arp.h> 52 #include <net/if_dl.h> 53 #include <net/if_media.h> 54 #include <net/if_types.h> 55 #include <net/if_vlan_var.h> 56 57 #include <netinet/in_systm.h> 58 #include <netinet/in.h> 59 #include <netinet/ip.h> 60 #include <netinet/tcp_lro.h> 61 62 #include <sys/sockio.h> 63 #include <sys/bus.h> 64 #include <machine/bus.h> 65 #include <sys/rman.h> 66 #include <machine/resource.h> 67 68 #if defined(__aarch64__) 69 #include <dev/extres/clk/clk.h> 70 #endif 71 72 #include <dev/mii/mii.h> 73 #include <dev/mii/miivar.h> 74 75 #include <dev/mdio/mdio.h> 76 77 #include <arm/mv/mvvar.h> 78 79 #if !defined(__aarch64__) 80 #include <arm/mv/mvreg.h> 81 #include <arm/mv/mvwin.h> 82 #endif 83 84 #include "if_mvnetareg.h" 85 #include "if_mvnetavar.h" 86 87 #include "miibus_if.h" 88 #include "mdio_if.h" 89 90 #ifdef MVNETA_DEBUG 91 #define STATIC /* nothing */ 92 #else 93 #define STATIC static 94 #endif 95 96 #define DASSERT(x) KASSERT((x), (#x)) 97 98 #define A3700_TCLK_250MHZ 250000000 99 100 /* Device Register Initialization */ 101 STATIC int mvneta_initreg(struct ifnet *); 102 103 /* Descriptor Ring Control for each of queues */ 104 STATIC int mvneta_ring_alloc_rx_queue(struct mvneta_softc *, int); 105 STATIC int mvneta_ring_alloc_tx_queue(struct mvneta_softc *, int); 106 STATIC void mvneta_ring_dealloc_rx_queue(struct mvneta_softc *, int); 107 STATIC void mvneta_ring_dealloc_tx_queue(struct mvneta_softc *, int); 108 STATIC int mvneta_ring_init_rx_queue(struct mvneta_softc *, int); 109 STATIC int mvneta_ring_init_tx_queue(struct mvneta_softc *, int); 110 STATIC void mvneta_ring_flush_rx_queue(struct mvneta_softc *, int); 111 STATIC void mvneta_ring_flush_tx_queue(struct mvneta_softc *, int); 112 STATIC void mvneta_dmamap_cb(void *, bus_dma_segment_t *, int, int); 113 STATIC int mvneta_dma_create(struct mvneta_softc *); 114 115 /* Rx/Tx Queue Control */ 116 STATIC int mvneta_rx_queue_init(struct ifnet *, int); 117 STATIC int mvneta_tx_queue_init(struct ifnet *, int); 118 STATIC int mvneta_rx_queue_enable(struct ifnet *, int); 119 STATIC int mvneta_tx_queue_enable(struct ifnet *, int); 120 STATIC void mvneta_rx_lockq(struct mvneta_softc *, int); 121 STATIC void mvneta_rx_unlockq(struct mvneta_softc *, int); 122 STATIC void mvneta_tx_lockq(struct mvneta_softc *, int); 123 STATIC void mvneta_tx_unlockq(struct mvneta_softc *, int); 124 125 /* Interrupt Handlers */ 126 STATIC void mvneta_disable_intr(struct mvneta_softc *); 127 STATIC void mvneta_enable_intr(struct mvneta_softc *); 128 STATIC void mvneta_rxtxth_intr(void *); 129 STATIC int mvneta_misc_intr(struct mvneta_softc *); 130 STATIC void mvneta_tick(void *); 131 /* struct ifnet and mii callbacks*/ 132 STATIC int mvneta_xmitfast_locked(struct mvneta_softc *, int, struct mbuf **); 133 STATIC int mvneta_xmit_locked(struct mvneta_softc *, int); 134 #ifdef MVNETA_MULTIQUEUE 135 STATIC int mvneta_transmit(struct ifnet *, struct mbuf *); 136 #else /* !MVNETA_MULTIQUEUE */ 137 STATIC void mvneta_start(struct ifnet *); 138 #endif 139 STATIC void mvneta_qflush(struct ifnet *); 140 STATIC void mvneta_tx_task(void *, int); 141 STATIC int mvneta_ioctl(struct ifnet *, u_long, caddr_t); 142 STATIC void mvneta_init(void *); 143 STATIC void mvneta_init_locked(void *); 144 STATIC void mvneta_stop(struct mvneta_softc *); 145 STATIC void mvneta_stop_locked(struct mvneta_softc *); 146 STATIC int mvneta_mediachange(struct ifnet *); 147 STATIC void mvneta_mediastatus(struct ifnet *, struct ifmediareq *); 148 STATIC void mvneta_portup(struct mvneta_softc *); 149 STATIC void mvneta_portdown(struct mvneta_softc *); 150 151 /* Link State Notify */ 152 STATIC void mvneta_update_autoneg(struct mvneta_softc *, int); 153 STATIC int mvneta_update_media(struct mvneta_softc *, int); 154 STATIC void mvneta_adjust_link(struct mvneta_softc *); 155 STATIC void mvneta_update_eee(struct mvneta_softc *); 156 STATIC void mvneta_update_fc(struct mvneta_softc *); 157 STATIC void mvneta_link_isr(struct mvneta_softc *); 158 STATIC void mvneta_linkupdate(struct mvneta_softc *, boolean_t); 159 STATIC void mvneta_linkup(struct mvneta_softc *); 160 STATIC void mvneta_linkdown(struct mvneta_softc *); 161 STATIC void mvneta_linkreset(struct mvneta_softc *); 162 163 /* Tx Subroutines */ 164 STATIC int mvneta_tx_queue(struct mvneta_softc *, struct mbuf **, int); 165 STATIC void mvneta_tx_set_csumflag(struct ifnet *, 166 struct mvneta_tx_desc *, struct mbuf *); 167 STATIC void mvneta_tx_queue_complete(struct mvneta_softc *, int); 168 STATIC void mvneta_tx_drain(struct mvneta_softc *); 169 170 /* Rx Subroutines */ 171 STATIC int mvneta_rx(struct mvneta_softc *, int, int); 172 STATIC void mvneta_rx_queue(struct mvneta_softc *, int, int); 173 STATIC void mvneta_rx_queue_refill(struct mvneta_softc *, int); 174 STATIC void mvneta_rx_set_csumflag(struct ifnet *, 175 struct mvneta_rx_desc *, struct mbuf *); 176 STATIC void mvneta_rx_buf_free(struct mvneta_softc *, struct mvneta_buf *); 177 178 /* MAC address filter */ 179 STATIC void mvneta_filter_setup(struct mvneta_softc *); 180 181 /* sysctl(9) */ 182 STATIC int sysctl_read_mib(SYSCTL_HANDLER_ARGS); 183 STATIC int sysctl_clear_mib(SYSCTL_HANDLER_ARGS); 184 STATIC int sysctl_set_queue_rxthtime(SYSCTL_HANDLER_ARGS); 185 STATIC void sysctl_mvneta_init(struct mvneta_softc *); 186 187 /* MIB */ 188 STATIC void mvneta_clear_mib(struct mvneta_softc *); 189 STATIC uint64_t mvneta_read_mib(struct mvneta_softc *, int); 190 STATIC void mvneta_update_mib(struct mvneta_softc *); 191 192 /* Switch */ 193 STATIC boolean_t mvneta_has_switch(device_t); 194 195 #define mvneta_sc_lock(sc) mtx_lock(&sc->mtx) 196 #define mvneta_sc_unlock(sc) mtx_unlock(&sc->mtx) 197 198 STATIC struct mtx mii_mutex; 199 STATIC int mii_init = 0; 200 201 /* Device */ 202 STATIC int mvneta_detach(device_t); 203 /* MII */ 204 STATIC int mvneta_miibus_readreg(device_t, int, int); 205 STATIC int mvneta_miibus_writereg(device_t, int, int, int); 206 207 static device_method_t mvneta_methods[] = { 208 /* Device interface */ 209 DEVMETHOD(device_detach, mvneta_detach), 210 /* MII interface */ 211 DEVMETHOD(miibus_readreg, mvneta_miibus_readreg), 212 DEVMETHOD(miibus_writereg, mvneta_miibus_writereg), 213 /* MDIO interface */ 214 DEVMETHOD(mdio_readreg, mvneta_miibus_readreg), 215 DEVMETHOD(mdio_writereg, mvneta_miibus_writereg), 216 217 /* End */ 218 DEVMETHOD_END 219 }; 220 221 DEFINE_CLASS_0(mvneta, mvneta_driver, mvneta_methods, sizeof(struct mvneta_softc)); 222 223 DRIVER_MODULE(miibus, mvneta, miibus_driver, miibus_devclass, 0, 0); 224 DRIVER_MODULE(mdio, mvneta, mdio_driver, mdio_devclass, 0, 0); 225 MODULE_DEPEND(mvneta, mdio, 1, 1, 1); 226 MODULE_DEPEND(mvneta, ether, 1, 1, 1); 227 MODULE_DEPEND(mvneta, miibus, 1, 1, 1); 228 MODULE_DEPEND(mvneta, mvxpbm, 1, 1, 1); 229 230 /* 231 * List of MIB register and names 232 */ 233 enum mvneta_mib_idx 234 { 235 MVNETA_MIB_RX_GOOD_OCT_IDX, 236 MVNETA_MIB_RX_BAD_OCT_IDX, 237 MVNETA_MIB_TX_MAC_TRNS_ERR_IDX, 238 MVNETA_MIB_RX_GOOD_FRAME_IDX, 239 MVNETA_MIB_RX_BAD_FRAME_IDX, 240 MVNETA_MIB_RX_BCAST_FRAME_IDX, 241 MVNETA_MIB_RX_MCAST_FRAME_IDX, 242 MVNETA_MIB_RX_FRAME64_OCT_IDX, 243 MVNETA_MIB_RX_FRAME127_OCT_IDX, 244 MVNETA_MIB_RX_FRAME255_OCT_IDX, 245 MVNETA_MIB_RX_FRAME511_OCT_IDX, 246 MVNETA_MIB_RX_FRAME1023_OCT_IDX, 247 MVNETA_MIB_RX_FRAMEMAX_OCT_IDX, 248 MVNETA_MIB_TX_GOOD_OCT_IDX, 249 MVNETA_MIB_TX_GOOD_FRAME_IDX, 250 MVNETA_MIB_TX_EXCES_COL_IDX, 251 MVNETA_MIB_TX_MCAST_FRAME_IDX, 252 MVNETA_MIB_TX_BCAST_FRAME_IDX, 253 MVNETA_MIB_TX_MAC_CTL_ERR_IDX, 254 MVNETA_MIB_FC_SENT_IDX, 255 MVNETA_MIB_FC_GOOD_IDX, 256 MVNETA_MIB_FC_BAD_IDX, 257 MVNETA_MIB_PKT_UNDERSIZE_IDX, 258 MVNETA_MIB_PKT_FRAGMENT_IDX, 259 MVNETA_MIB_PKT_OVERSIZE_IDX, 260 MVNETA_MIB_PKT_JABBER_IDX, 261 MVNETA_MIB_MAC_RX_ERR_IDX, 262 MVNETA_MIB_MAC_CRC_ERR_IDX, 263 MVNETA_MIB_MAC_COL_IDX, 264 MVNETA_MIB_MAC_LATE_COL_IDX, 265 }; 266 267 STATIC struct mvneta_mib_def { 268 uint32_t regnum; 269 int reg64; 270 const char *sysctl_name; 271 const char *desc; 272 } mvneta_mib_list[] = { 273 [MVNETA_MIB_RX_GOOD_OCT_IDX] = {MVNETA_MIB_RX_GOOD_OCT, 1, 274 "rx_good_oct", "Good Octets Rx"}, 275 [MVNETA_MIB_RX_BAD_OCT_IDX] = {MVNETA_MIB_RX_BAD_OCT, 0, 276 "rx_bad_oct", "Bad Octets Rx"}, 277 [MVNETA_MIB_TX_MAC_TRNS_ERR_IDX] = {MVNETA_MIB_TX_MAC_TRNS_ERR, 0, 278 "tx_mac_err", "MAC Transmit Error"}, 279 [MVNETA_MIB_RX_GOOD_FRAME_IDX] = {MVNETA_MIB_RX_GOOD_FRAME, 0, 280 "rx_good_frame", "Good Frames Rx"}, 281 [MVNETA_MIB_RX_BAD_FRAME_IDX] = {MVNETA_MIB_RX_BAD_FRAME, 0, 282 "rx_bad_frame", "Bad Frames Rx"}, 283 [MVNETA_MIB_RX_BCAST_FRAME_IDX] = {MVNETA_MIB_RX_BCAST_FRAME, 0, 284 "rx_bcast_frame", "Broadcast Frames Rx"}, 285 [MVNETA_MIB_RX_MCAST_FRAME_IDX] = {MVNETA_MIB_RX_MCAST_FRAME, 0, 286 "rx_mcast_frame", "Multicast Frames Rx"}, 287 [MVNETA_MIB_RX_FRAME64_OCT_IDX] = {MVNETA_MIB_RX_FRAME64_OCT, 0, 288 "rx_frame_1_64", "Frame Size 1 - 64"}, 289 [MVNETA_MIB_RX_FRAME127_OCT_IDX] = {MVNETA_MIB_RX_FRAME127_OCT, 0, 290 "rx_frame_65_127", "Frame Size 65 - 127"}, 291 [MVNETA_MIB_RX_FRAME255_OCT_IDX] = {MVNETA_MIB_RX_FRAME255_OCT, 0, 292 "rx_frame_128_255", "Frame Size 128 - 255"}, 293 [MVNETA_MIB_RX_FRAME511_OCT_IDX] = {MVNETA_MIB_RX_FRAME511_OCT, 0, 294 "rx_frame_256_511", "Frame Size 256 - 511"}, 295 [MVNETA_MIB_RX_FRAME1023_OCT_IDX] = {MVNETA_MIB_RX_FRAME1023_OCT, 0, 296 "rx_frame_512_1023", "Frame Size 512 - 1023"}, 297 [MVNETA_MIB_RX_FRAMEMAX_OCT_IDX] = {MVNETA_MIB_RX_FRAMEMAX_OCT, 0, 298 "rx_fame_1024_max", "Frame Size 1024 - Max"}, 299 [MVNETA_MIB_TX_GOOD_OCT_IDX] = {MVNETA_MIB_TX_GOOD_OCT, 1, 300 "tx_good_oct", "Good Octets Tx"}, 301 [MVNETA_MIB_TX_GOOD_FRAME_IDX] = {MVNETA_MIB_TX_GOOD_FRAME, 0, 302 "tx_good_frame", "Good Frames Tx"}, 303 [MVNETA_MIB_TX_EXCES_COL_IDX] = {MVNETA_MIB_TX_EXCES_COL, 0, 304 "tx_exces_collision", "Excessive Collision"}, 305 [MVNETA_MIB_TX_MCAST_FRAME_IDX] = {MVNETA_MIB_TX_MCAST_FRAME, 0, 306 "tx_mcast_frame", "Multicast Frames Tx"}, 307 [MVNETA_MIB_TX_BCAST_FRAME_IDX] = {MVNETA_MIB_TX_BCAST_FRAME, 0, 308 "tx_bcast_frame", "Broadcast Frames Tx"}, 309 [MVNETA_MIB_TX_MAC_CTL_ERR_IDX] = {MVNETA_MIB_TX_MAC_CTL_ERR, 0, 310 "tx_mac_ctl_err", "Unknown MAC Control"}, 311 [MVNETA_MIB_FC_SENT_IDX] = {MVNETA_MIB_FC_SENT, 0, 312 "fc_tx", "Flow Control Tx"}, 313 [MVNETA_MIB_FC_GOOD_IDX] = {MVNETA_MIB_FC_GOOD, 0, 314 "fc_rx_good", "Good Flow Control Rx"}, 315 [MVNETA_MIB_FC_BAD_IDX] = {MVNETA_MIB_FC_BAD, 0, 316 "fc_rx_bad", "Bad Flow Control Rx"}, 317 [MVNETA_MIB_PKT_UNDERSIZE_IDX] = {MVNETA_MIB_PKT_UNDERSIZE, 0, 318 "pkt_undersize", "Undersized Packets Rx"}, 319 [MVNETA_MIB_PKT_FRAGMENT_IDX] = {MVNETA_MIB_PKT_FRAGMENT, 0, 320 "pkt_fragment", "Fragmented Packets Rx"}, 321 [MVNETA_MIB_PKT_OVERSIZE_IDX] = {MVNETA_MIB_PKT_OVERSIZE, 0, 322 "pkt_oversize", "Oversized Packets Rx"}, 323 [MVNETA_MIB_PKT_JABBER_IDX] = {MVNETA_MIB_PKT_JABBER, 0, 324 "pkt_jabber", "Jabber Packets Rx"}, 325 [MVNETA_MIB_MAC_RX_ERR_IDX] = {MVNETA_MIB_MAC_RX_ERR, 0, 326 "mac_rx_err", "MAC Rx Errors"}, 327 [MVNETA_MIB_MAC_CRC_ERR_IDX] = {MVNETA_MIB_MAC_CRC_ERR, 0, 328 "mac_crc_err", "MAC CRC Errors"}, 329 [MVNETA_MIB_MAC_COL_IDX] = {MVNETA_MIB_MAC_COL, 0, 330 "mac_collision", "MAC Collision"}, 331 [MVNETA_MIB_MAC_LATE_COL_IDX] = {MVNETA_MIB_MAC_LATE_COL, 0, 332 "mac_late_collision", "MAC Late Collision"}, 333 }; 334 335 static struct resource_spec res_spec[] = { 336 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 337 { SYS_RES_IRQ, 0, RF_ACTIVE }, 338 { -1, 0} 339 }; 340 341 static struct { 342 driver_intr_t *handler; 343 char * description; 344 } mvneta_intrs[] = { 345 { mvneta_rxtxth_intr, "MVNETA aggregated interrupt" }, 346 }; 347 348 static int 349 mvneta_set_mac_address(struct mvneta_softc *sc, uint8_t *addr) 350 { 351 unsigned int mac_h; 352 unsigned int mac_l; 353 354 mac_l = (addr[4] << 8) | (addr[5]); 355 mac_h = (addr[0] << 24) | (addr[1] << 16) | 356 (addr[2] << 8) | (addr[3] << 0); 357 358 MVNETA_WRITE(sc, MVNETA_MACAL, mac_l); 359 MVNETA_WRITE(sc, MVNETA_MACAH, mac_h); 360 return (0); 361 } 362 363 static int 364 mvneta_get_mac_address(struct mvneta_softc *sc, uint8_t *addr) 365 { 366 uint32_t mac_l, mac_h; 367 368 #ifdef FDT 369 if (mvneta_fdt_mac_address(sc, addr) == 0) 370 return (0); 371 #endif 372 /* 373 * Fall back -- use the currently programmed address. 374 */ 375 mac_l = MVNETA_READ(sc, MVNETA_MACAL); 376 mac_h = MVNETA_READ(sc, MVNETA_MACAH); 377 if (mac_l == 0 && mac_h == 0) { 378 /* 379 * Generate pseudo-random MAC. 380 * Set lower part to random number | unit number. 381 */ 382 mac_l = arc4random() & ~0xff; 383 mac_l |= device_get_unit(sc->dev) & 0xff; 384 mac_h = arc4random(); 385 mac_h &= ~(3 << 24); /* Clear multicast and LAA bits */ 386 if (bootverbose) { 387 device_printf(sc->dev, 388 "Could not acquire MAC address. " 389 "Using randomized one.\n"); 390 } 391 } 392 393 addr[0] = (mac_h & 0xff000000) >> 24; 394 addr[1] = (mac_h & 0x00ff0000) >> 16; 395 addr[2] = (mac_h & 0x0000ff00) >> 8; 396 addr[3] = (mac_h & 0x000000ff); 397 addr[4] = (mac_l & 0x0000ff00) >> 8; 398 addr[5] = (mac_l & 0x000000ff); 399 return (0); 400 } 401 402 STATIC boolean_t 403 mvneta_has_switch(device_t self) 404 { 405 #ifdef FDT 406 return (mvneta_has_switch_fdt(self)); 407 #endif 408 409 return (false); 410 } 411 412 STATIC int 413 mvneta_dma_create(struct mvneta_softc *sc) 414 { 415 size_t maxsize, maxsegsz; 416 size_t q; 417 int error; 418 419 /* 420 * Create Tx DMA 421 */ 422 maxsize = maxsegsz = sizeof(struct mvneta_tx_desc) * MVNETA_TX_RING_CNT; 423 424 error = bus_dma_tag_create( 425 bus_get_dma_tag(sc->dev), /* parent */ 426 16, 0, /* alignment, boundary */ 427 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 428 BUS_SPACE_MAXADDR, /* highaddr */ 429 NULL, NULL, /* filtfunc, filtfuncarg */ 430 maxsize, /* maxsize */ 431 1, /* nsegments */ 432 maxsegsz, /* maxsegsz */ 433 0, /* flags */ 434 NULL, NULL, /* lockfunc, lockfuncarg */ 435 &sc->tx_dtag); /* dmat */ 436 if (error != 0) { 437 device_printf(sc->dev, 438 "Failed to create DMA tag for Tx descriptors.\n"); 439 goto fail; 440 } 441 error = bus_dma_tag_create( 442 bus_get_dma_tag(sc->dev), /* parent */ 443 1, 0, /* alignment, boundary */ 444 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 445 BUS_SPACE_MAXADDR, /* highaddr */ 446 NULL, NULL, /* filtfunc, filtfuncarg */ 447 MVNETA_MAX_FRAME, /* maxsize */ 448 MVNETA_TX_SEGLIMIT, /* nsegments */ 449 MVNETA_MAX_FRAME, /* maxsegsz */ 450 BUS_DMA_ALLOCNOW, /* flags */ 451 NULL, NULL, /* lockfunc, lockfuncarg */ 452 &sc->txmbuf_dtag); 453 if (error != 0) { 454 device_printf(sc->dev, 455 "Failed to create DMA tag for Tx mbufs.\n"); 456 goto fail; 457 } 458 459 for (q = 0; q < MVNETA_TX_QNUM_MAX; q++) { 460 error = mvneta_ring_alloc_tx_queue(sc, q); 461 if (error != 0) { 462 device_printf(sc->dev, 463 "Failed to allocate DMA safe memory for TxQ: %zu\n", q); 464 goto fail; 465 } 466 } 467 468 /* 469 * Create Rx DMA. 470 */ 471 /* Create tag for Rx descripors */ 472 error = bus_dma_tag_create( 473 bus_get_dma_tag(sc->dev), /* parent */ 474 32, 0, /* alignment, boundary */ 475 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 476 BUS_SPACE_MAXADDR, /* highaddr */ 477 NULL, NULL, /* filtfunc, filtfuncarg */ 478 sizeof(struct mvneta_rx_desc) * MVNETA_RX_RING_CNT, /* maxsize */ 479 1, /* nsegments */ 480 sizeof(struct mvneta_rx_desc) * MVNETA_RX_RING_CNT, /* maxsegsz */ 481 0, /* flags */ 482 NULL, NULL, /* lockfunc, lockfuncarg */ 483 &sc->rx_dtag); /* dmat */ 484 if (error != 0) { 485 device_printf(sc->dev, 486 "Failed to create DMA tag for Rx descriptors.\n"); 487 goto fail; 488 } 489 490 /* Create tag for Rx buffers */ 491 error = bus_dma_tag_create( 492 bus_get_dma_tag(sc->dev), /* parent */ 493 32, 0, /* alignment, boundary */ 494 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 495 BUS_SPACE_MAXADDR, /* highaddr */ 496 NULL, NULL, /* filtfunc, filtfuncarg */ 497 MVNETA_MAX_FRAME, 1, /* maxsize, nsegments */ 498 MVNETA_MAX_FRAME, /* maxsegsz */ 499 0, /* flags */ 500 NULL, NULL, /* lockfunc, lockfuncarg */ 501 &sc->rxbuf_dtag); /* dmat */ 502 if (error != 0) { 503 device_printf(sc->dev, 504 "Failed to create DMA tag for Rx buffers.\n"); 505 goto fail; 506 } 507 508 for (q = 0; q < MVNETA_RX_QNUM_MAX; q++) { 509 if (mvneta_ring_alloc_rx_queue(sc, q) != 0) { 510 device_printf(sc->dev, 511 "Failed to allocate DMA safe memory for RxQ: %zu\n", q); 512 goto fail; 513 } 514 } 515 516 return (0); 517 fail: 518 mvneta_detach(sc->dev); 519 520 return (error); 521 } 522 523 /* ARGSUSED */ 524 int 525 mvneta_attach(device_t self) 526 { 527 struct mvneta_softc *sc; 528 struct ifnet *ifp; 529 device_t child; 530 int ifm_target; 531 int q, error; 532 #if !defined(__aarch64__) 533 uint32_t reg; 534 #endif 535 #if defined(__aarch64__) 536 clk_t clk; 537 #endif 538 sc = device_get_softc(self); 539 sc->dev = self; 540 541 mtx_init(&sc->mtx, "mvneta_sc", NULL, MTX_DEF); 542 543 error = bus_alloc_resources(self, res_spec, sc->res); 544 if (error) { 545 device_printf(self, "could not allocate resources\n"); 546 return (ENXIO); 547 } 548 549 sc->version = MVNETA_READ(sc, MVNETA_PV); 550 device_printf(self, "version is %x\n", sc->version); 551 callout_init(&sc->tick_ch, 0); 552 553 /* 554 * make sure DMA engines are in reset state 555 */ 556 MVNETA_WRITE(sc, MVNETA_PRXINIT, 0x00000001); 557 MVNETA_WRITE(sc, MVNETA_PTXINIT, 0x00000001); 558 559 #if defined(__aarch64__) 560 error = clk_get_by_ofw_index(sc->dev, ofw_bus_get_node(sc->dev), 0, 561 &clk); 562 if (error != 0) { 563 device_printf(sc->dev, 564 "Cannot get clock, using default frequency: %d\n", 565 A3700_TCLK_250MHZ); 566 sc->clk_freq = A3700_TCLK_250MHZ; 567 } else { 568 error = clk_get_freq(clk, &sc->clk_freq); 569 if (error != 0) { 570 device_printf(sc->dev, 571 "Cannot obtain frequency from parent clock\n"); 572 bus_release_resources(sc->dev, res_spec, sc->res); 573 return (error); 574 } 575 } 576 #else 577 sc->clk_freq = get_tclk(); 578 #endif 579 580 #if !defined(__aarch64__) 581 /* 582 * Disable port snoop for buffers and descriptors 583 * to avoid L2 caching of both without DRAM copy. 584 * Obtain coherency settings from the first MBUS 585 * window attribute. 586 */ 587 if ((MVNETA_READ(sc, MV_WIN_NETA_BASE(0)) & IO_WIN_COH_ATTR_MASK) == 0) { 588 reg = MVNETA_READ(sc, MVNETA_PSNPCFG); 589 reg &= ~MVNETA_PSNPCFG_DESCSNP_MASK; 590 reg &= ~MVNETA_PSNPCFG_BUFSNP_MASK; 591 MVNETA_WRITE(sc, MVNETA_PSNPCFG, reg); 592 } 593 #endif 594 595 error = bus_setup_intr(self, sc->res[1], 596 INTR_TYPE_NET | INTR_MPSAFE, NULL, mvneta_intrs[0].handler, sc, 597 &sc->ih_cookie[0]); 598 if (error) { 599 device_printf(self, "could not setup %s\n", 600 mvneta_intrs[0].description); 601 mvneta_detach(self); 602 return (error); 603 } 604 605 /* 606 * MAC address 607 */ 608 if (mvneta_get_mac_address(sc, sc->enaddr)) { 609 device_printf(self, "no mac address.\n"); 610 return (ENXIO); 611 } 612 mvneta_set_mac_address(sc, sc->enaddr); 613 614 mvneta_disable_intr(sc); 615 616 /* Allocate network interface */ 617 ifp = sc->ifp = if_alloc(IFT_ETHER); 618 if (ifp == NULL) { 619 device_printf(self, "if_alloc() failed\n"); 620 mvneta_detach(self); 621 return (ENOMEM); 622 } 623 if_initname(ifp, device_get_name(self), device_get_unit(self)); 624 625 /* 626 * We can support 802.1Q VLAN-sized frames and jumbo 627 * Ethernet frames. 628 */ 629 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_JUMBO_MTU; 630 631 ifp->if_softc = sc; 632 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 633 #ifdef MVNETA_MULTIQUEUE 634 ifp->if_transmit = mvneta_transmit; 635 ifp->if_qflush = mvneta_qflush; 636 #else /* !MVNETA_MULTIQUEUE */ 637 ifp->if_start = mvneta_start; 638 ifp->if_snd.ifq_drv_maxlen = MVNETA_TX_RING_CNT - 1; 639 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 640 IFQ_SET_READY(&ifp->if_snd); 641 #endif 642 ifp->if_init = mvneta_init; 643 ifp->if_ioctl = mvneta_ioctl; 644 645 /* 646 * We can do IPv4/TCPv4/UDPv4/TCPv6/UDPv6 checksums in hardware. 647 */ 648 ifp->if_capabilities |= IFCAP_HWCSUM; 649 650 /* 651 * As VLAN hardware tagging is not supported 652 * but is necessary to perform VLAN hardware checksums, 653 * it is done in the driver 654 */ 655 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWCSUM; 656 657 /* 658 * Currently IPv6 HW checksum is broken, so make sure it is disabled. 659 */ 660 ifp->if_capabilities &= ~IFCAP_HWCSUM_IPV6; 661 ifp->if_capenable = ifp->if_capabilities; 662 663 /* 664 * Disabled option(s): 665 * - Support for Large Receive Offload 666 */ 667 ifp->if_capabilities |= IFCAP_LRO; 668 669 ifp->if_hwassist = CSUM_IP | CSUM_TCP | CSUM_UDP; 670 671 sc->rx_frame_size = MCLBYTES; /* ether_ifattach() always sets normal mtu */ 672 673 /* 674 * Device DMA Buffer allocation. 675 * Handles resource deallocation in case of failure. 676 */ 677 error = mvneta_dma_create(sc); 678 if (error != 0) { 679 mvneta_detach(self); 680 return (error); 681 } 682 683 /* Initialize queues */ 684 for (q = 0; q < MVNETA_TX_QNUM_MAX; q++) { 685 error = mvneta_ring_init_tx_queue(sc, q); 686 if (error != 0) { 687 mvneta_detach(self); 688 return (error); 689 } 690 } 691 692 for (q = 0; q < MVNETA_RX_QNUM_MAX; q++) { 693 error = mvneta_ring_init_rx_queue(sc, q); 694 if (error != 0) { 695 mvneta_detach(self); 696 return (error); 697 } 698 } 699 700 /* 701 * Enable DMA engines and Initialize Device Registers. 702 */ 703 MVNETA_WRITE(sc, MVNETA_PRXINIT, 0x00000000); 704 MVNETA_WRITE(sc, MVNETA_PTXINIT, 0x00000000); 705 MVNETA_WRITE(sc, MVNETA_PACC, MVNETA_PACC_ACCELERATIONMODE_EDM); 706 mvneta_sc_lock(sc); 707 mvneta_filter_setup(sc); 708 mvneta_sc_unlock(sc); 709 mvneta_initreg(ifp); 710 711 /* 712 * Now MAC is working, setup MII. 713 */ 714 if (mii_init == 0) { 715 /* 716 * MII bus is shared by all MACs and all PHYs in SoC. 717 * serializing the bus access should be safe. 718 */ 719 mtx_init(&mii_mutex, "mvneta_mii", NULL, MTX_DEF); 720 mii_init = 1; 721 } 722 723 /* Attach PHY(s) */ 724 if ((sc->phy_addr != MII_PHY_ANY) && (!sc->use_inband_status)) { 725 error = mii_attach(self, &sc->miibus, ifp, mvneta_mediachange, 726 mvneta_mediastatus, BMSR_DEFCAPMASK, sc->phy_addr, 727 MII_OFFSET_ANY, 0); 728 if (error != 0) { 729 device_printf(self, "MII attach failed, error: %d\n", 730 error); 731 ether_ifdetach(sc->ifp); 732 mvneta_detach(self); 733 return (error); 734 } 735 sc->mii = device_get_softc(sc->miibus); 736 sc->phy_attached = 1; 737 738 /* Disable auto-negotiation in MAC - rely on PHY layer */ 739 mvneta_update_autoneg(sc, FALSE); 740 } else if (sc->use_inband_status == TRUE) { 741 /* In-band link status */ 742 ifmedia_init(&sc->mvneta_ifmedia, 0, mvneta_mediachange, 743 mvneta_mediastatus); 744 745 /* Configure media */ 746 ifmedia_add(&sc->mvneta_ifmedia, IFM_ETHER | IFM_1000_T | IFM_FDX, 747 0, NULL); 748 ifmedia_add(&sc->mvneta_ifmedia, IFM_ETHER | IFM_100_TX, 0, NULL); 749 ifmedia_add(&sc->mvneta_ifmedia, IFM_ETHER | IFM_100_TX | IFM_FDX, 750 0, NULL); 751 ifmedia_add(&sc->mvneta_ifmedia, IFM_ETHER | IFM_10_T, 0, NULL); 752 ifmedia_add(&sc->mvneta_ifmedia, IFM_ETHER | IFM_10_T | IFM_FDX, 753 0, NULL); 754 ifmedia_add(&sc->mvneta_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 755 ifmedia_set(&sc->mvneta_ifmedia, IFM_ETHER | IFM_AUTO); 756 757 /* Enable auto-negotiation */ 758 mvneta_update_autoneg(sc, TRUE); 759 760 mvneta_sc_lock(sc); 761 if (MVNETA_IS_LINKUP(sc)) 762 mvneta_linkup(sc); 763 else 764 mvneta_linkdown(sc); 765 mvneta_sc_unlock(sc); 766 767 } else { 768 /* Fixed-link, use predefined values */ 769 mvneta_update_autoneg(sc, FALSE); 770 ifmedia_init(&sc->mvneta_ifmedia, 0, mvneta_mediachange, 771 mvneta_mediastatus); 772 773 ifm_target = IFM_ETHER; 774 switch (sc->phy_speed) { 775 case 2500: 776 if (sc->phy_mode != MVNETA_PHY_SGMII && 777 sc->phy_mode != MVNETA_PHY_QSGMII) { 778 device_printf(self, 779 "2.5G speed can work only in (Q)SGMII mode\n"); 780 ether_ifdetach(sc->ifp); 781 mvneta_detach(self); 782 return (ENXIO); 783 } 784 ifm_target |= IFM_2500_T; 785 break; 786 case 1000: 787 ifm_target |= IFM_1000_T; 788 break; 789 case 100: 790 ifm_target |= IFM_100_TX; 791 break; 792 case 10: 793 ifm_target |= IFM_10_T; 794 break; 795 default: 796 ether_ifdetach(sc->ifp); 797 mvneta_detach(self); 798 return (ENXIO); 799 } 800 801 if (sc->phy_fdx) 802 ifm_target |= IFM_FDX; 803 else 804 ifm_target |= IFM_HDX; 805 806 ifmedia_add(&sc->mvneta_ifmedia, ifm_target, 0, NULL); 807 ifmedia_set(&sc->mvneta_ifmedia, ifm_target); 808 if_link_state_change(sc->ifp, LINK_STATE_UP); 809 810 if (mvneta_has_switch(self)) { 811 if (bootverbose) 812 device_printf(self, "This device is attached to a switch\n"); 813 child = device_add_child(sc->dev, "mdio", -1); 814 if (child == NULL) { 815 ether_ifdetach(sc->ifp); 816 mvneta_detach(self); 817 return (ENXIO); 818 } 819 bus_generic_attach(sc->dev); 820 bus_generic_attach(child); 821 } 822 823 /* Configure MAC media */ 824 mvneta_update_media(sc, ifm_target); 825 } 826 827 ether_ifattach(ifp, sc->enaddr); 828 829 callout_reset(&sc->tick_ch, 0, mvneta_tick, sc); 830 831 sysctl_mvneta_init(sc); 832 833 return (0); 834 } 835 836 STATIC int 837 mvneta_detach(device_t dev) 838 { 839 struct mvneta_softc *sc; 840 struct ifnet *ifp; 841 int q; 842 843 sc = device_get_softc(dev); 844 ifp = sc->ifp; 845 846 if (device_is_attached(dev)) { 847 mvneta_stop(sc); 848 callout_drain(&sc->tick_ch); 849 ether_ifdetach(sc->ifp); 850 } 851 852 for (q = 0; q < MVNETA_RX_QNUM_MAX; q++) 853 mvneta_ring_dealloc_rx_queue(sc, q); 854 for (q = 0; q < MVNETA_TX_QNUM_MAX; q++) 855 mvneta_ring_dealloc_tx_queue(sc, q); 856 857 device_delete_children(dev); 858 859 if (sc->ih_cookie[0] != NULL) 860 bus_teardown_intr(dev, sc->res[1], sc->ih_cookie[0]); 861 862 if (sc->tx_dtag != NULL) 863 bus_dma_tag_destroy(sc->tx_dtag); 864 if (sc->rx_dtag != NULL) 865 bus_dma_tag_destroy(sc->rx_dtag); 866 if (sc->txmbuf_dtag != NULL) 867 bus_dma_tag_destroy(sc->txmbuf_dtag); 868 if (sc->rxbuf_dtag != NULL) 869 bus_dma_tag_destroy(sc->rxbuf_dtag); 870 871 bus_release_resources(dev, res_spec, sc->res); 872 873 if (sc->ifp) 874 if_free(sc->ifp); 875 876 if (mtx_initialized(&sc->mtx)) 877 mtx_destroy(&sc->mtx); 878 879 return (0); 880 } 881 882 /* 883 * MII 884 */ 885 STATIC int 886 mvneta_miibus_readreg(device_t dev, int phy, int reg) 887 { 888 struct mvneta_softc *sc; 889 struct ifnet *ifp; 890 uint32_t smi, val; 891 int i; 892 893 sc = device_get_softc(dev); 894 ifp = sc->ifp; 895 896 mtx_lock(&mii_mutex); 897 898 for (i = 0; i < MVNETA_PHY_TIMEOUT; i++) { 899 if ((MVNETA_READ(sc, MVNETA_SMI) & MVNETA_SMI_BUSY) == 0) 900 break; 901 DELAY(1); 902 } 903 if (i == MVNETA_PHY_TIMEOUT) { 904 if_printf(ifp, "SMI busy timeout\n"); 905 mtx_unlock(&mii_mutex); 906 return (-1); 907 } 908 909 smi = MVNETA_SMI_PHYAD(phy) | 910 MVNETA_SMI_REGAD(reg) | MVNETA_SMI_OPCODE_READ; 911 MVNETA_WRITE(sc, MVNETA_SMI, smi); 912 913 for (i = 0; i < MVNETA_PHY_TIMEOUT; i++) { 914 if ((MVNETA_READ(sc, MVNETA_SMI) & MVNETA_SMI_BUSY) == 0) 915 break; 916 DELAY(1); 917 } 918 919 if (i == MVNETA_PHY_TIMEOUT) { 920 if_printf(ifp, "SMI busy timeout\n"); 921 mtx_unlock(&mii_mutex); 922 return (-1); 923 } 924 for (i = 0; i < MVNETA_PHY_TIMEOUT; i++) { 925 smi = MVNETA_READ(sc, MVNETA_SMI); 926 if (smi & MVNETA_SMI_READVALID) 927 break; 928 DELAY(1); 929 } 930 931 if (i == MVNETA_PHY_TIMEOUT) { 932 if_printf(ifp, "SMI busy timeout\n"); 933 mtx_unlock(&mii_mutex); 934 return (-1); 935 } 936 937 mtx_unlock(&mii_mutex); 938 939 #ifdef MVNETA_KTR 940 CTR3(KTR_SPARE2, "%s i=%d, timeout=%d\n", ifp->if_xname, i, 941 MVNETA_PHY_TIMEOUT); 942 #endif 943 944 val = smi & MVNETA_SMI_DATA_MASK; 945 946 #ifdef MVNETA_KTR 947 CTR4(KTR_SPARE2, "%s phy=%d, reg=%#x, val=%#x\n", ifp->if_xname, phy, 948 reg, val); 949 #endif 950 return (val); 951 } 952 953 STATIC int 954 mvneta_miibus_writereg(device_t dev, int phy, int reg, int val) 955 { 956 struct mvneta_softc *sc; 957 struct ifnet *ifp; 958 uint32_t smi; 959 int i; 960 961 sc = device_get_softc(dev); 962 ifp = sc->ifp; 963 #ifdef MVNETA_KTR 964 CTR4(KTR_SPARE2, "%s phy=%d, reg=%#x, val=%#x\n", ifp->if_xname, 965 phy, reg, val); 966 #endif 967 968 mtx_lock(&mii_mutex); 969 970 for (i = 0; i < MVNETA_PHY_TIMEOUT; i++) { 971 if ((MVNETA_READ(sc, MVNETA_SMI) & MVNETA_SMI_BUSY) == 0) 972 break; 973 DELAY(1); 974 } 975 if (i == MVNETA_PHY_TIMEOUT) { 976 if_printf(ifp, "SMI busy timeout\n"); 977 mtx_unlock(&mii_mutex); 978 return (0); 979 } 980 981 smi = MVNETA_SMI_PHYAD(phy) | MVNETA_SMI_REGAD(reg) | 982 MVNETA_SMI_OPCODE_WRITE | (val & MVNETA_SMI_DATA_MASK); 983 MVNETA_WRITE(sc, MVNETA_SMI, smi); 984 985 for (i = 0; i < MVNETA_PHY_TIMEOUT; i++) { 986 if ((MVNETA_READ(sc, MVNETA_SMI) & MVNETA_SMI_BUSY) == 0) 987 break; 988 DELAY(1); 989 } 990 991 mtx_unlock(&mii_mutex); 992 993 if (i == MVNETA_PHY_TIMEOUT) 994 if_printf(ifp, "phy write timed out\n"); 995 996 return (0); 997 } 998 999 STATIC void 1000 mvneta_portup(struct mvneta_softc *sc) 1001 { 1002 int q; 1003 1004 for (q = 0; q < MVNETA_RX_QNUM_MAX; q++) { 1005 mvneta_rx_lockq(sc, q); 1006 mvneta_rx_queue_enable(sc->ifp, q); 1007 mvneta_rx_unlockq(sc, q); 1008 } 1009 1010 for (q = 0; q < MVNETA_TX_QNUM_MAX; q++) { 1011 mvneta_tx_lockq(sc, q); 1012 mvneta_tx_queue_enable(sc->ifp, q); 1013 mvneta_tx_unlockq(sc, q); 1014 } 1015 1016 } 1017 1018 STATIC void 1019 mvneta_portdown(struct mvneta_softc *sc) 1020 { 1021 struct mvneta_rx_ring *rx; 1022 struct mvneta_tx_ring *tx; 1023 int q, cnt; 1024 uint32_t reg; 1025 1026 for (q = 0; q < MVNETA_RX_QNUM_MAX; q++) { 1027 rx = MVNETA_RX_RING(sc, q); 1028 mvneta_rx_lockq(sc, q); 1029 rx->queue_status = MVNETA_QUEUE_DISABLED; 1030 mvneta_rx_unlockq(sc, q); 1031 } 1032 1033 for (q = 0; q < MVNETA_TX_QNUM_MAX; q++) { 1034 tx = MVNETA_TX_RING(sc, q); 1035 mvneta_tx_lockq(sc, q); 1036 tx->queue_status = MVNETA_QUEUE_DISABLED; 1037 mvneta_tx_unlockq(sc, q); 1038 } 1039 1040 /* Wait for all Rx activity to terminate. */ 1041 reg = MVNETA_READ(sc, MVNETA_RQC) & MVNETA_RQC_EN_MASK; 1042 reg = MVNETA_RQC_DIS(reg); 1043 MVNETA_WRITE(sc, MVNETA_RQC, reg); 1044 cnt = 0; 1045 do { 1046 if (cnt >= RX_DISABLE_TIMEOUT) { 1047 if_printf(sc->ifp, 1048 "timeout for RX stopped. rqc 0x%x\n", reg); 1049 break; 1050 } 1051 cnt++; 1052 reg = MVNETA_READ(sc, MVNETA_RQC); 1053 } while ((reg & MVNETA_RQC_EN_MASK) != 0); 1054 1055 /* Wait for all Tx activity to terminate. */ 1056 reg = MVNETA_READ(sc, MVNETA_PIE); 1057 reg &= ~MVNETA_PIE_TXPKTINTRPTENB_MASK; 1058 MVNETA_WRITE(sc, MVNETA_PIE, reg); 1059 1060 reg = MVNETA_READ(sc, MVNETA_PRXTXTIM); 1061 reg &= ~MVNETA_PRXTXTI_TBTCQ_MASK; 1062 MVNETA_WRITE(sc, MVNETA_PRXTXTIM, reg); 1063 1064 reg = MVNETA_READ(sc, MVNETA_TQC) & MVNETA_TQC_EN_MASK; 1065 reg = MVNETA_TQC_DIS(reg); 1066 MVNETA_WRITE(sc, MVNETA_TQC, reg); 1067 cnt = 0; 1068 do { 1069 if (cnt >= TX_DISABLE_TIMEOUT) { 1070 if_printf(sc->ifp, 1071 "timeout for TX stopped. tqc 0x%x\n", reg); 1072 break; 1073 } 1074 cnt++; 1075 reg = MVNETA_READ(sc, MVNETA_TQC); 1076 } while ((reg & MVNETA_TQC_EN_MASK) != 0); 1077 1078 /* Wait for all Tx FIFO is empty */ 1079 cnt = 0; 1080 do { 1081 if (cnt >= TX_FIFO_EMPTY_TIMEOUT) { 1082 if_printf(sc->ifp, 1083 "timeout for TX FIFO drained. ps0 0x%x\n", reg); 1084 break; 1085 } 1086 cnt++; 1087 reg = MVNETA_READ(sc, MVNETA_PS0); 1088 } while (((reg & MVNETA_PS0_TXFIFOEMP) == 0) && 1089 ((reg & MVNETA_PS0_TXINPROG) != 0)); 1090 } 1091 1092 /* 1093 * Device Register Initialization 1094 * reset device registers to device driver default value. 1095 * the device is not enabled here. 1096 */ 1097 STATIC int 1098 mvneta_initreg(struct ifnet *ifp) 1099 { 1100 struct mvneta_softc *sc; 1101 int q; 1102 uint32_t reg; 1103 1104 sc = ifp->if_softc; 1105 #ifdef MVNETA_KTR 1106 CTR1(KTR_SPARE2, "%s initializing device register", ifp->if_xname); 1107 #endif 1108 1109 /* Disable Legacy WRR, Disable EJP, Release from reset. */ 1110 MVNETA_WRITE(sc, MVNETA_TQC_1, 0); 1111 /* Enable mbus retry. */ 1112 MVNETA_WRITE(sc, MVNETA_MBUS_CONF, MVNETA_MBUS_RETRY_EN); 1113 1114 /* Init TX/RX Queue Registers */ 1115 for (q = 0; q < MVNETA_RX_QNUM_MAX; q++) { 1116 mvneta_rx_lockq(sc, q); 1117 if (mvneta_rx_queue_init(ifp, q) != 0) { 1118 device_printf(sc->dev, 1119 "initialization failed: cannot initialize queue\n"); 1120 mvneta_rx_unlockq(sc, q); 1121 return (ENOBUFS); 1122 } 1123 mvneta_rx_unlockq(sc, q); 1124 } 1125 for (q = 0; q < MVNETA_TX_QNUM_MAX; q++) { 1126 mvneta_tx_lockq(sc, q); 1127 if (mvneta_tx_queue_init(ifp, q) != 0) { 1128 device_printf(sc->dev, 1129 "initialization failed: cannot initialize queue\n"); 1130 mvneta_tx_unlockq(sc, q); 1131 return (ENOBUFS); 1132 } 1133 mvneta_tx_unlockq(sc, q); 1134 } 1135 1136 /* 1137 * Ethernet Unit Control - disable automatic PHY management by HW. 1138 * In case the port uses SMI-controlled PHY, poll its status with 1139 * mii_tick() and update MAC settings accordingly. 1140 */ 1141 reg = MVNETA_READ(sc, MVNETA_EUC); 1142 reg &= ~MVNETA_EUC_POLLING; 1143 MVNETA_WRITE(sc, MVNETA_EUC, reg); 1144 1145 /* EEE: Low Power Idle */ 1146 reg = MVNETA_LPIC0_LILIMIT(MVNETA_LPI_LI); 1147 reg |= MVNETA_LPIC0_TSLIMIT(MVNETA_LPI_TS); 1148 MVNETA_WRITE(sc, MVNETA_LPIC0, reg); 1149 1150 reg = MVNETA_LPIC1_TWLIMIT(MVNETA_LPI_TW); 1151 MVNETA_WRITE(sc, MVNETA_LPIC1, reg); 1152 1153 reg = MVNETA_LPIC2_MUSTSET; 1154 MVNETA_WRITE(sc, MVNETA_LPIC2, reg); 1155 1156 /* Port MAC Control set 0 */ 1157 reg = MVNETA_PMACC0_MUSTSET; /* must write 0x1 */ 1158 reg &= ~MVNETA_PMACC0_PORTEN; /* port is still disabled */ 1159 reg |= MVNETA_PMACC0_FRAMESIZELIMIT(ifp->if_mtu + MVNETA_ETHER_SIZE); 1160 MVNETA_WRITE(sc, MVNETA_PMACC0, reg); 1161 1162 /* Port MAC Control set 2 */ 1163 reg = MVNETA_READ(sc, MVNETA_PMACC2); 1164 switch (sc->phy_mode) { 1165 case MVNETA_PHY_QSGMII: 1166 reg |= (MVNETA_PMACC2_PCSEN | MVNETA_PMACC2_RGMIIEN); 1167 MVNETA_WRITE(sc, MVNETA_PSERDESCFG, MVNETA_PSERDESCFG_QSGMII); 1168 break; 1169 case MVNETA_PHY_SGMII: 1170 reg |= (MVNETA_PMACC2_PCSEN | MVNETA_PMACC2_RGMIIEN); 1171 MVNETA_WRITE(sc, MVNETA_PSERDESCFG, MVNETA_PSERDESCFG_SGMII); 1172 break; 1173 case MVNETA_PHY_RGMII: 1174 case MVNETA_PHY_RGMII_ID: 1175 reg |= MVNETA_PMACC2_RGMIIEN; 1176 break; 1177 } 1178 reg |= MVNETA_PMACC2_MUSTSET; 1179 reg &= ~MVNETA_PMACC2_PORTMACRESET; 1180 MVNETA_WRITE(sc, MVNETA_PMACC2, reg); 1181 1182 /* Port Configuration Extended: enable Tx CRC generation */ 1183 reg = MVNETA_READ(sc, MVNETA_PXCX); 1184 reg &= ~MVNETA_PXCX_TXCRCDIS; 1185 MVNETA_WRITE(sc, MVNETA_PXCX, reg); 1186 1187 /* clear MIB counter registers(clear by read) */ 1188 mvneta_sc_lock(sc); 1189 mvneta_clear_mib(sc); 1190 mvneta_sc_unlock(sc); 1191 1192 /* Set SDC register except IPGINT bits */ 1193 reg = MVNETA_SDC_RXBSZ_16_64BITWORDS; 1194 reg |= MVNETA_SDC_TXBSZ_16_64BITWORDS; 1195 reg |= MVNETA_SDC_BLMR; 1196 reg |= MVNETA_SDC_BLMT; 1197 MVNETA_WRITE(sc, MVNETA_SDC, reg); 1198 1199 return (0); 1200 } 1201 1202 STATIC void 1203 mvneta_dmamap_cb(void *arg, bus_dma_segment_t * segs, int nseg, int error) 1204 { 1205 1206 if (error != 0) 1207 return; 1208 *(bus_addr_t *)arg = segs->ds_addr; 1209 } 1210 1211 STATIC int 1212 mvneta_ring_alloc_rx_queue(struct mvneta_softc *sc, int q) 1213 { 1214 struct mvneta_rx_ring *rx; 1215 struct mvneta_buf *rxbuf; 1216 bus_dmamap_t dmap; 1217 int i, error; 1218 1219 if (q >= MVNETA_RX_QNUM_MAX) 1220 return (EINVAL); 1221 1222 rx = MVNETA_RX_RING(sc, q); 1223 mtx_init(&rx->ring_mtx, "mvneta_rx", NULL, MTX_DEF); 1224 /* Allocate DMA memory for Rx descriptors */ 1225 error = bus_dmamem_alloc(sc->rx_dtag, 1226 (void**)&(rx->desc), 1227 BUS_DMA_NOWAIT | BUS_DMA_ZERO, 1228 &rx->desc_map); 1229 if (error != 0 || rx->desc == NULL) 1230 goto fail; 1231 error = bus_dmamap_load(sc->rx_dtag, rx->desc_map, 1232 rx->desc, 1233 sizeof(struct mvneta_rx_desc) * MVNETA_RX_RING_CNT, 1234 mvneta_dmamap_cb, &rx->desc_pa, BUS_DMA_NOWAIT); 1235 if (error != 0) 1236 goto fail; 1237 1238 for (i = 0; i < MVNETA_RX_RING_CNT; i++) { 1239 error = bus_dmamap_create(sc->rxbuf_dtag, 0, &dmap); 1240 if (error != 0) { 1241 device_printf(sc->dev, 1242 "Failed to create DMA map for Rx buffer num: %d\n", i); 1243 goto fail; 1244 } 1245 rxbuf = &rx->rxbuf[i]; 1246 rxbuf->dmap = dmap; 1247 rxbuf->m = NULL; 1248 } 1249 1250 return (0); 1251 fail: 1252 mvneta_rx_lockq(sc, q); 1253 mvneta_ring_flush_rx_queue(sc, q); 1254 mvneta_rx_unlockq(sc, q); 1255 mvneta_ring_dealloc_rx_queue(sc, q); 1256 device_printf(sc->dev, "DMA Ring buffer allocation failure.\n"); 1257 return (error); 1258 } 1259 1260 STATIC int 1261 mvneta_ring_alloc_tx_queue(struct mvneta_softc *sc, int q) 1262 { 1263 struct mvneta_tx_ring *tx; 1264 int error; 1265 1266 if (q >= MVNETA_TX_QNUM_MAX) 1267 return (EINVAL); 1268 tx = MVNETA_TX_RING(sc, q); 1269 mtx_init(&tx->ring_mtx, "mvneta_tx", NULL, MTX_DEF); 1270 error = bus_dmamem_alloc(sc->tx_dtag, 1271 (void**)&(tx->desc), 1272 BUS_DMA_NOWAIT | BUS_DMA_ZERO, 1273 &tx->desc_map); 1274 if (error != 0 || tx->desc == NULL) 1275 goto fail; 1276 error = bus_dmamap_load(sc->tx_dtag, tx->desc_map, 1277 tx->desc, 1278 sizeof(struct mvneta_tx_desc) * MVNETA_TX_RING_CNT, 1279 mvneta_dmamap_cb, &tx->desc_pa, BUS_DMA_NOWAIT); 1280 if (error != 0) 1281 goto fail; 1282 1283 #ifdef MVNETA_MULTIQUEUE 1284 tx->br = buf_ring_alloc(MVNETA_BUFRING_SIZE, M_DEVBUF, M_NOWAIT, 1285 &tx->ring_mtx); 1286 if (tx->br == NULL) { 1287 device_printf(sc->dev, 1288 "Could not setup buffer ring for TxQ(%d)\n", q); 1289 error = ENOMEM; 1290 goto fail; 1291 } 1292 #endif 1293 1294 return (0); 1295 fail: 1296 mvneta_tx_lockq(sc, q); 1297 mvneta_ring_flush_tx_queue(sc, q); 1298 mvneta_tx_unlockq(sc, q); 1299 mvneta_ring_dealloc_tx_queue(sc, q); 1300 device_printf(sc->dev, "DMA Ring buffer allocation failure.\n"); 1301 return (error); 1302 } 1303 1304 STATIC void 1305 mvneta_ring_dealloc_tx_queue(struct mvneta_softc *sc, int q) 1306 { 1307 struct mvneta_tx_ring *tx; 1308 struct mvneta_buf *txbuf; 1309 void *kva; 1310 int error; 1311 int i; 1312 1313 if (q >= MVNETA_TX_QNUM_MAX) 1314 return; 1315 tx = MVNETA_TX_RING(sc, q); 1316 1317 if (tx->taskq != NULL) { 1318 /* Remove task */ 1319 while (taskqueue_cancel(tx->taskq, &tx->task, NULL) != 0) 1320 taskqueue_drain(tx->taskq, &tx->task); 1321 } 1322 #ifdef MVNETA_MULTIQUEUE 1323 if (tx->br != NULL) 1324 drbr_free(tx->br, M_DEVBUF); 1325 #endif 1326 1327 if (sc->txmbuf_dtag != NULL) { 1328 for (i = 0; i < MVNETA_TX_RING_CNT; i++) { 1329 txbuf = &tx->txbuf[i]; 1330 if (txbuf->dmap != NULL) { 1331 error = bus_dmamap_destroy(sc->txmbuf_dtag, 1332 txbuf->dmap); 1333 if (error != 0) { 1334 panic("%s: map busy for Tx descriptor (Q%d, %d)", 1335 __func__, q, i); 1336 } 1337 } 1338 } 1339 } 1340 1341 if (tx->desc_pa != 0) 1342 bus_dmamap_unload(sc->tx_dtag, tx->desc_map); 1343 1344 kva = (void *)tx->desc; 1345 if (kva != NULL) 1346 bus_dmamem_free(sc->tx_dtag, tx->desc, tx->desc_map); 1347 1348 if (mtx_name(&tx->ring_mtx) != NULL) 1349 mtx_destroy(&tx->ring_mtx); 1350 1351 memset(tx, 0, sizeof(*tx)); 1352 } 1353 1354 STATIC void 1355 mvneta_ring_dealloc_rx_queue(struct mvneta_softc *sc, int q) 1356 { 1357 struct mvneta_rx_ring *rx; 1358 struct lro_ctrl *lro; 1359 void *kva; 1360 1361 if (q >= MVNETA_RX_QNUM_MAX) 1362 return; 1363 1364 rx = MVNETA_RX_RING(sc, q); 1365 1366 if (rx->desc_pa != 0) 1367 bus_dmamap_unload(sc->rx_dtag, rx->desc_map); 1368 1369 kva = (void *)rx->desc; 1370 if (kva != NULL) 1371 bus_dmamem_free(sc->rx_dtag, rx->desc, rx->desc_map); 1372 1373 lro = &rx->lro; 1374 tcp_lro_free(lro); 1375 1376 if (mtx_name(&rx->ring_mtx) != NULL) 1377 mtx_destroy(&rx->ring_mtx); 1378 1379 memset(rx, 0, sizeof(*rx)); 1380 } 1381 1382 STATIC int 1383 mvneta_ring_init_rx_queue(struct mvneta_softc *sc, int q) 1384 { 1385 struct mvneta_rx_ring *rx; 1386 struct lro_ctrl *lro; 1387 int error; 1388 1389 if (q >= MVNETA_RX_QNUM_MAX) 1390 return (0); 1391 1392 rx = MVNETA_RX_RING(sc, q); 1393 rx->dma = rx->cpu = 0; 1394 rx->queue_th_received = MVNETA_RXTH_COUNT; 1395 rx->queue_th_time = (sc->clk_freq / 1000) / 10; /* 0.1 [ms] */ 1396 1397 /* Initialize LRO */ 1398 rx->lro_enabled = FALSE; 1399 if ((sc->ifp->if_capenable & IFCAP_LRO) != 0) { 1400 lro = &rx->lro; 1401 error = tcp_lro_init(lro); 1402 if (error != 0) 1403 device_printf(sc->dev, "LRO Initialization failed!\n"); 1404 else { 1405 rx->lro_enabled = TRUE; 1406 lro->ifp = sc->ifp; 1407 } 1408 } 1409 1410 return (0); 1411 } 1412 1413 STATIC int 1414 mvneta_ring_init_tx_queue(struct mvneta_softc *sc, int q) 1415 { 1416 struct mvneta_tx_ring *tx; 1417 struct mvneta_buf *txbuf; 1418 int i, error; 1419 1420 if (q >= MVNETA_TX_QNUM_MAX) 1421 return (0); 1422 1423 tx = MVNETA_TX_RING(sc, q); 1424 1425 /* Tx handle */ 1426 for (i = 0; i < MVNETA_TX_RING_CNT; i++) { 1427 txbuf = &tx->txbuf[i]; 1428 txbuf->m = NULL; 1429 /* Tx handle needs DMA map for busdma_load_mbuf() */ 1430 error = bus_dmamap_create(sc->txmbuf_dtag, 0, 1431 &txbuf->dmap); 1432 if (error != 0) { 1433 device_printf(sc->dev, 1434 "can't create dma map (tx ring %d)\n", i); 1435 return (error); 1436 } 1437 } 1438 tx->dma = tx->cpu = 0; 1439 tx->used = 0; 1440 tx->drv_error = 0; 1441 tx->queue_status = MVNETA_QUEUE_DISABLED; 1442 tx->queue_hung = FALSE; 1443 1444 tx->ifp = sc->ifp; 1445 tx->qidx = q; 1446 TASK_INIT(&tx->task, 0, mvneta_tx_task, tx); 1447 tx->taskq = taskqueue_create_fast("mvneta_tx_taskq", M_WAITOK, 1448 taskqueue_thread_enqueue, &tx->taskq); 1449 taskqueue_start_threads(&tx->taskq, 1, PI_NET, "%s: tx_taskq(%d)", 1450 device_get_nameunit(sc->dev), q); 1451 1452 return (0); 1453 } 1454 1455 STATIC void 1456 mvneta_ring_flush_tx_queue(struct mvneta_softc *sc, int q) 1457 { 1458 struct mvneta_tx_ring *tx; 1459 struct mvneta_buf *txbuf; 1460 int i; 1461 1462 tx = MVNETA_TX_RING(sc, q); 1463 KASSERT_TX_MTX(sc, q); 1464 1465 /* Tx handle */ 1466 for (i = 0; i < MVNETA_TX_RING_CNT; i++) { 1467 txbuf = &tx->txbuf[i]; 1468 bus_dmamap_unload(sc->txmbuf_dtag, txbuf->dmap); 1469 if (txbuf->m != NULL) { 1470 m_freem(txbuf->m); 1471 txbuf->m = NULL; 1472 } 1473 } 1474 tx->dma = tx->cpu = 0; 1475 tx->used = 0; 1476 } 1477 1478 STATIC void 1479 mvneta_ring_flush_rx_queue(struct mvneta_softc *sc, int q) 1480 { 1481 struct mvneta_rx_ring *rx; 1482 struct mvneta_buf *rxbuf; 1483 int i; 1484 1485 rx = MVNETA_RX_RING(sc, q); 1486 KASSERT_RX_MTX(sc, q); 1487 1488 /* Rx handle */ 1489 for (i = 0; i < MVNETA_RX_RING_CNT; i++) { 1490 rxbuf = &rx->rxbuf[i]; 1491 mvneta_rx_buf_free(sc, rxbuf); 1492 } 1493 rx->dma = rx->cpu = 0; 1494 } 1495 1496 /* 1497 * Rx/Tx Queue Control 1498 */ 1499 STATIC int 1500 mvneta_rx_queue_init(struct ifnet *ifp, int q) 1501 { 1502 struct mvneta_softc *sc; 1503 struct mvneta_rx_ring *rx; 1504 uint32_t reg; 1505 1506 sc = ifp->if_softc; 1507 KASSERT_RX_MTX(sc, q); 1508 rx = MVNETA_RX_RING(sc, q); 1509 DASSERT(rx->desc_pa != 0); 1510 1511 /* descriptor address */ 1512 MVNETA_WRITE(sc, MVNETA_PRXDQA(q), rx->desc_pa); 1513 1514 /* Rx buffer size and descriptor ring size */ 1515 reg = MVNETA_PRXDQS_BUFFERSIZE(sc->rx_frame_size >> 3); 1516 reg |= MVNETA_PRXDQS_DESCRIPTORSQUEUESIZE(MVNETA_RX_RING_CNT); 1517 MVNETA_WRITE(sc, MVNETA_PRXDQS(q), reg); 1518 #ifdef MVNETA_KTR 1519 CTR3(KTR_SPARE2, "%s PRXDQS(%d): %#x", ifp->if_xname, q, 1520 MVNETA_READ(sc, MVNETA_PRXDQS(q))); 1521 #endif 1522 /* Rx packet offset address */ 1523 reg = MVNETA_PRXC_PACKETOFFSET(MVNETA_PACKET_OFFSET >> 3); 1524 MVNETA_WRITE(sc, MVNETA_PRXC(q), reg); 1525 #ifdef MVNETA_KTR 1526 CTR3(KTR_SPARE2, "%s PRXC(%d): %#x", ifp->if_xname, q, 1527 MVNETA_READ(sc, MVNETA_PRXC(q))); 1528 #endif 1529 1530 /* if DMA is not working, register is not updated */ 1531 DASSERT(MVNETA_READ(sc, MVNETA_PRXDQA(q)) == rx->desc_pa); 1532 return (0); 1533 } 1534 1535 STATIC int 1536 mvneta_tx_queue_init(struct ifnet *ifp, int q) 1537 { 1538 struct mvneta_softc *sc; 1539 struct mvneta_tx_ring *tx; 1540 uint32_t reg; 1541 1542 sc = ifp->if_softc; 1543 KASSERT_TX_MTX(sc, q); 1544 tx = MVNETA_TX_RING(sc, q); 1545 DASSERT(tx->desc_pa != 0); 1546 1547 /* descriptor address */ 1548 MVNETA_WRITE(sc, MVNETA_PTXDQA(q), tx->desc_pa); 1549 1550 /* descriptor ring size */ 1551 reg = MVNETA_PTXDQS_DQS(MVNETA_TX_RING_CNT); 1552 MVNETA_WRITE(sc, MVNETA_PTXDQS(q), reg); 1553 1554 /* if DMA is not working, register is not updated */ 1555 DASSERT(MVNETA_READ(sc, MVNETA_PTXDQA(q)) == tx->desc_pa); 1556 return (0); 1557 } 1558 1559 STATIC int 1560 mvneta_rx_queue_enable(struct ifnet *ifp, int q) 1561 { 1562 struct mvneta_softc *sc; 1563 struct mvneta_rx_ring *rx; 1564 uint32_t reg; 1565 1566 sc = ifp->if_softc; 1567 rx = MVNETA_RX_RING(sc, q); 1568 KASSERT_RX_MTX(sc, q); 1569 1570 /* Set Rx interrupt threshold */ 1571 reg = MVNETA_PRXDQTH_ODT(rx->queue_th_received); 1572 MVNETA_WRITE(sc, MVNETA_PRXDQTH(q), reg); 1573 1574 reg = MVNETA_PRXITTH_RITT(rx->queue_th_time); 1575 MVNETA_WRITE(sc, MVNETA_PRXITTH(q), reg); 1576 1577 /* Unmask RXTX_TH Intr. */ 1578 reg = MVNETA_READ(sc, MVNETA_PRXTXTIM); 1579 reg |= MVNETA_PRXTXTI_RBICTAPQ(q); /* Rx Buffer Interrupt Coalese */ 1580 MVNETA_WRITE(sc, MVNETA_PRXTXTIM, reg); 1581 1582 /* Enable Rx queue */ 1583 reg = MVNETA_READ(sc, MVNETA_RQC) & MVNETA_RQC_EN_MASK; 1584 reg |= MVNETA_RQC_ENQ(q); 1585 MVNETA_WRITE(sc, MVNETA_RQC, reg); 1586 1587 rx->queue_status = MVNETA_QUEUE_WORKING; 1588 return (0); 1589 } 1590 1591 STATIC int 1592 mvneta_tx_queue_enable(struct ifnet *ifp, int q) 1593 { 1594 struct mvneta_softc *sc; 1595 struct mvneta_tx_ring *tx; 1596 1597 sc = ifp->if_softc; 1598 tx = MVNETA_TX_RING(sc, q); 1599 KASSERT_TX_MTX(sc, q); 1600 1601 /* Enable Tx queue */ 1602 MVNETA_WRITE(sc, MVNETA_TQC, MVNETA_TQC_ENQ(q)); 1603 1604 tx->queue_status = MVNETA_QUEUE_IDLE; 1605 tx->queue_hung = FALSE; 1606 return (0); 1607 } 1608 1609 STATIC __inline void 1610 mvneta_rx_lockq(struct mvneta_softc *sc, int q) 1611 { 1612 1613 DASSERT(q >= 0); 1614 DASSERT(q < MVNETA_RX_QNUM_MAX); 1615 mtx_lock(&sc->rx_ring[q].ring_mtx); 1616 } 1617 1618 STATIC __inline void 1619 mvneta_rx_unlockq(struct mvneta_softc *sc, int q) 1620 { 1621 1622 DASSERT(q >= 0); 1623 DASSERT(q < MVNETA_RX_QNUM_MAX); 1624 mtx_unlock(&sc->rx_ring[q].ring_mtx); 1625 } 1626 1627 STATIC __inline int __unused 1628 mvneta_tx_trylockq(struct mvneta_softc *sc, int q) 1629 { 1630 1631 DASSERT(q >= 0); 1632 DASSERT(q < MVNETA_TX_QNUM_MAX); 1633 return (mtx_trylock(&sc->tx_ring[q].ring_mtx)); 1634 } 1635 1636 STATIC __inline void 1637 mvneta_tx_lockq(struct mvneta_softc *sc, int q) 1638 { 1639 1640 DASSERT(q >= 0); 1641 DASSERT(q < MVNETA_TX_QNUM_MAX); 1642 mtx_lock(&sc->tx_ring[q].ring_mtx); 1643 } 1644 1645 STATIC __inline void 1646 mvneta_tx_unlockq(struct mvneta_softc *sc, int q) 1647 { 1648 1649 DASSERT(q >= 0); 1650 DASSERT(q < MVNETA_TX_QNUM_MAX); 1651 mtx_unlock(&sc->tx_ring[q].ring_mtx); 1652 } 1653 1654 /* 1655 * Interrupt Handlers 1656 */ 1657 STATIC void 1658 mvneta_disable_intr(struct mvneta_softc *sc) 1659 { 1660 1661 MVNETA_WRITE(sc, MVNETA_EUIM, 0); 1662 MVNETA_WRITE(sc, MVNETA_EUIC, 0); 1663 MVNETA_WRITE(sc, MVNETA_PRXTXTIM, 0); 1664 MVNETA_WRITE(sc, MVNETA_PRXTXTIC, 0); 1665 MVNETA_WRITE(sc, MVNETA_PRXTXIM, 0); 1666 MVNETA_WRITE(sc, MVNETA_PRXTXIC, 0); 1667 MVNETA_WRITE(sc, MVNETA_PMIM, 0); 1668 MVNETA_WRITE(sc, MVNETA_PMIC, 0); 1669 MVNETA_WRITE(sc, MVNETA_PIE, 0); 1670 } 1671 1672 STATIC void 1673 mvneta_enable_intr(struct mvneta_softc *sc) 1674 { 1675 uint32_t reg; 1676 1677 /* Enable Summary Bit to check all interrupt cause. */ 1678 reg = MVNETA_READ(sc, MVNETA_PRXTXTIM); 1679 reg |= MVNETA_PRXTXTI_PMISCICSUMMARY; 1680 MVNETA_WRITE(sc, MVNETA_PRXTXTIM, reg); 1681 1682 if (sc->use_inband_status) { 1683 /* Enable Port MISC Intr. (via RXTX_TH_Summary bit) */ 1684 MVNETA_WRITE(sc, MVNETA_PMIM, MVNETA_PMI_PHYSTATUSCHNG | 1685 MVNETA_PMI_LINKCHANGE | MVNETA_PMI_PSCSYNCCHANGE); 1686 } 1687 1688 /* Enable All Queue Interrupt */ 1689 reg = MVNETA_READ(sc, MVNETA_PIE); 1690 reg |= MVNETA_PIE_RXPKTINTRPTENB_MASK; 1691 reg |= MVNETA_PIE_TXPKTINTRPTENB_MASK; 1692 MVNETA_WRITE(sc, MVNETA_PIE, reg); 1693 } 1694 1695 STATIC void 1696 mvneta_rxtxth_intr(void *arg) 1697 { 1698 struct mvneta_softc *sc; 1699 struct ifnet *ifp; 1700 uint32_t ic, queues; 1701 1702 sc = arg; 1703 ifp = sc->ifp; 1704 #ifdef MVNETA_KTR 1705 CTR1(KTR_SPARE2, "%s got RXTX_TH_Intr", ifp->if_xname); 1706 #endif 1707 ic = MVNETA_READ(sc, MVNETA_PRXTXTIC); 1708 if (ic == 0) 1709 return; 1710 MVNETA_WRITE(sc, MVNETA_PRXTXTIC, ~ic); 1711 1712 /* Ack maintance interrupt first */ 1713 if (__predict_false((ic & MVNETA_PRXTXTI_PMISCICSUMMARY) && 1714 sc->use_inband_status)) { 1715 mvneta_sc_lock(sc); 1716 mvneta_misc_intr(sc); 1717 mvneta_sc_unlock(sc); 1718 } 1719 if (__predict_false(!(ifp->if_drv_flags & IFF_DRV_RUNNING))) 1720 return; 1721 /* RxTxTH interrupt */ 1722 queues = MVNETA_PRXTXTI_GET_RBICTAPQ(ic); 1723 if (__predict_true(queues)) { 1724 #ifdef MVNETA_KTR 1725 CTR1(KTR_SPARE2, "%s got PRXTXTIC: +RXEOF", ifp->if_xname); 1726 #endif 1727 /* At the moment the driver support only one RX queue. */ 1728 DASSERT(MVNETA_IS_QUEUE_SET(queues, 0)); 1729 mvneta_rx(sc, 0, 0); 1730 } 1731 } 1732 1733 STATIC int 1734 mvneta_misc_intr(struct mvneta_softc *sc) 1735 { 1736 uint32_t ic; 1737 int claimed = 0; 1738 1739 #ifdef MVNETA_KTR 1740 CTR1(KTR_SPARE2, "%s got MISC_INTR", sc->ifp->if_xname); 1741 #endif 1742 KASSERT_SC_MTX(sc); 1743 1744 for (;;) { 1745 ic = MVNETA_READ(sc, MVNETA_PMIC); 1746 ic &= MVNETA_READ(sc, MVNETA_PMIM); 1747 if (ic == 0) 1748 break; 1749 MVNETA_WRITE(sc, MVNETA_PMIC, ~ic); 1750 claimed = 1; 1751 1752 if (ic & (MVNETA_PMI_PHYSTATUSCHNG | 1753 MVNETA_PMI_LINKCHANGE | MVNETA_PMI_PSCSYNCCHANGE)) 1754 mvneta_link_isr(sc); 1755 } 1756 return (claimed); 1757 } 1758 1759 STATIC void 1760 mvneta_tick(void *arg) 1761 { 1762 struct mvneta_softc *sc; 1763 struct mvneta_tx_ring *tx; 1764 struct mvneta_rx_ring *rx; 1765 int q; 1766 uint32_t fc_prev, fc_curr; 1767 1768 sc = arg; 1769 1770 /* 1771 * This is done before mib update to get the right stats 1772 * for this tick. 1773 */ 1774 mvneta_tx_drain(sc); 1775 1776 /* Extract previous flow-control frame received counter. */ 1777 fc_prev = sc->sysctl_mib[MVNETA_MIB_FC_GOOD_IDX].counter; 1778 /* Read mib registers (clear by read). */ 1779 mvneta_update_mib(sc); 1780 /* Extract current flow-control frame received counter. */ 1781 fc_curr = sc->sysctl_mib[MVNETA_MIB_FC_GOOD_IDX].counter; 1782 1783 1784 if (sc->phy_attached && sc->ifp->if_flags & IFF_UP) { 1785 mvneta_sc_lock(sc); 1786 mii_tick(sc->mii); 1787 1788 /* Adjust MAC settings */ 1789 mvneta_adjust_link(sc); 1790 mvneta_sc_unlock(sc); 1791 } 1792 1793 /* 1794 * We were unable to refill the rx queue and left the rx func, leaving 1795 * the ring without mbuf and no way to call the refill func. 1796 */ 1797 for (q = 0; q < MVNETA_RX_QNUM_MAX; q++) { 1798 rx = MVNETA_RX_RING(sc, q); 1799 if (rx->needs_refill == TRUE) { 1800 mvneta_rx_lockq(sc, q); 1801 mvneta_rx_queue_refill(sc, q); 1802 mvneta_rx_unlockq(sc, q); 1803 } 1804 } 1805 1806 /* 1807 * Watchdog: 1808 * - check if queue is mark as hung. 1809 * - ignore hung status if we received some pause frame 1810 * as hardware may have paused packet transmit. 1811 */ 1812 for (q = 0; q < MVNETA_TX_QNUM_MAX; q++) { 1813 /* 1814 * We should take queue lock, but as we only read 1815 * queue status we can do it without lock, we may 1816 * only missdetect queue status for one tick. 1817 */ 1818 tx = MVNETA_TX_RING(sc, q); 1819 1820 if (tx->queue_hung && (fc_curr - fc_prev) == 0) 1821 goto timeout; 1822 } 1823 1824 callout_schedule(&sc->tick_ch, hz); 1825 return; 1826 1827 timeout: 1828 if_printf(sc->ifp, "watchdog timeout\n"); 1829 1830 mvneta_sc_lock(sc); 1831 sc->counter_watchdog++; 1832 sc->counter_watchdog_mib++; 1833 /* Trigger reinitialize sequence. */ 1834 mvneta_stop_locked(sc); 1835 mvneta_init_locked(sc); 1836 mvneta_sc_unlock(sc); 1837 } 1838 1839 STATIC void 1840 mvneta_qflush(struct ifnet *ifp) 1841 { 1842 #ifdef MVNETA_MULTIQUEUE 1843 struct mvneta_softc *sc; 1844 struct mvneta_tx_ring *tx; 1845 struct mbuf *m; 1846 size_t q; 1847 1848 sc = ifp->if_softc; 1849 1850 for (q = 0; q < MVNETA_TX_QNUM_MAX; q++) { 1851 tx = MVNETA_TX_RING(sc, q); 1852 mvneta_tx_lockq(sc, q); 1853 while ((m = buf_ring_dequeue_sc(tx->br)) != NULL) 1854 m_freem(m); 1855 mvneta_tx_unlockq(sc, q); 1856 } 1857 #endif 1858 if_qflush(ifp); 1859 } 1860 1861 STATIC void 1862 mvneta_tx_task(void *arg, int pending) 1863 { 1864 struct mvneta_softc *sc; 1865 struct mvneta_tx_ring *tx; 1866 struct ifnet *ifp; 1867 int error; 1868 1869 tx = arg; 1870 ifp = tx->ifp; 1871 sc = ifp->if_softc; 1872 1873 mvneta_tx_lockq(sc, tx->qidx); 1874 error = mvneta_xmit_locked(sc, tx->qidx); 1875 mvneta_tx_unlockq(sc, tx->qidx); 1876 1877 /* Try again */ 1878 if (__predict_false(error != 0 && error != ENETDOWN)) { 1879 pause("mvneta_tx_task_sleep", 1); 1880 taskqueue_enqueue(tx->taskq, &tx->task); 1881 } 1882 } 1883 1884 STATIC int 1885 mvneta_xmitfast_locked(struct mvneta_softc *sc, int q, struct mbuf **m) 1886 { 1887 struct mvneta_tx_ring *tx; 1888 struct ifnet *ifp; 1889 int error; 1890 1891 KASSERT_TX_MTX(sc, q); 1892 tx = MVNETA_TX_RING(sc, q); 1893 error = 0; 1894 1895 ifp = sc->ifp; 1896 1897 /* Dont enqueue packet if the queue is disabled. */ 1898 if (__predict_false(tx->queue_status == MVNETA_QUEUE_DISABLED)) { 1899 m_freem(*m); 1900 *m = NULL; 1901 return (ENETDOWN); 1902 } 1903 1904 /* Reclaim mbuf if above threshold. */ 1905 if (__predict_true(tx->used > MVNETA_TX_RECLAIM_COUNT)) 1906 mvneta_tx_queue_complete(sc, q); 1907 1908 /* Do not call transmit path if queue is already too full. */ 1909 if (__predict_false(tx->used > 1910 MVNETA_TX_RING_CNT - MVNETA_TX_SEGLIMIT)) 1911 return (ENOBUFS); 1912 1913 error = mvneta_tx_queue(sc, m, q); 1914 if (__predict_false(error != 0)) 1915 return (error); 1916 1917 /* Send a copy of the frame to the BPF listener */ 1918 ETHER_BPF_MTAP(ifp, *m); 1919 1920 /* Set watchdog on */ 1921 tx->watchdog_time = ticks; 1922 tx->queue_status = MVNETA_QUEUE_WORKING; 1923 1924 return (error); 1925 } 1926 1927 #ifdef MVNETA_MULTIQUEUE 1928 STATIC int 1929 mvneta_transmit(struct ifnet *ifp, struct mbuf *m) 1930 { 1931 struct mvneta_softc *sc; 1932 struct mvneta_tx_ring *tx; 1933 int error; 1934 int q; 1935 1936 sc = ifp->if_softc; 1937 1938 /* Use default queue if there is no flow id as thread can migrate. */ 1939 if (__predict_true(M_HASHTYPE_GET(m) != M_HASHTYPE_NONE)) 1940 q = m->m_pkthdr.flowid % MVNETA_TX_QNUM_MAX; 1941 else 1942 q = 0; 1943 1944 tx = MVNETA_TX_RING(sc, q); 1945 1946 /* If buf_ring is full start transmit immediatly. */ 1947 if (buf_ring_full(tx->br)) { 1948 mvneta_tx_lockq(sc, q); 1949 mvneta_xmit_locked(sc, q); 1950 mvneta_tx_unlockq(sc, q); 1951 } 1952 1953 /* 1954 * If the buf_ring is empty we will not reorder packets. 1955 * If the lock is available transmit without using buf_ring. 1956 */ 1957 if (buf_ring_empty(tx->br) && mvneta_tx_trylockq(sc, q) != 0) { 1958 error = mvneta_xmitfast_locked(sc, q, &m); 1959 mvneta_tx_unlockq(sc, q); 1960 if (__predict_true(error == 0)) 1961 return (0); 1962 1963 /* Transmit can fail in fastpath. */ 1964 if (__predict_false(m == NULL)) 1965 return (error); 1966 } 1967 1968 /* Enqueue then schedule taskqueue. */ 1969 error = drbr_enqueue(ifp, tx->br, m); 1970 if (__predict_false(error != 0)) 1971 return (error); 1972 1973 taskqueue_enqueue(tx->taskq, &tx->task); 1974 return (0); 1975 } 1976 1977 STATIC int 1978 mvneta_xmit_locked(struct mvneta_softc *sc, int q) 1979 { 1980 struct ifnet *ifp; 1981 struct mvneta_tx_ring *tx; 1982 struct mbuf *m; 1983 int error; 1984 1985 KASSERT_TX_MTX(sc, q); 1986 ifp = sc->ifp; 1987 tx = MVNETA_TX_RING(sc, q); 1988 error = 0; 1989 1990 while ((m = drbr_peek(ifp, tx->br)) != NULL) { 1991 error = mvneta_xmitfast_locked(sc, q, &m); 1992 if (__predict_false(error != 0)) { 1993 if (m != NULL) 1994 drbr_putback(ifp, tx->br, m); 1995 else 1996 drbr_advance(ifp, tx->br); 1997 break; 1998 } 1999 drbr_advance(ifp, tx->br); 2000 } 2001 2002 return (error); 2003 } 2004 #else /* !MVNETA_MULTIQUEUE */ 2005 STATIC void 2006 mvneta_start(struct ifnet *ifp) 2007 { 2008 struct mvneta_softc *sc; 2009 struct mvneta_tx_ring *tx; 2010 int error; 2011 2012 sc = ifp->if_softc; 2013 tx = MVNETA_TX_RING(sc, 0); 2014 2015 mvneta_tx_lockq(sc, 0); 2016 error = mvneta_xmit_locked(sc, 0); 2017 mvneta_tx_unlockq(sc, 0); 2018 /* Handle retransmit in the background taskq. */ 2019 if (__predict_false(error != 0 && error != ENETDOWN)) 2020 taskqueue_enqueue(tx->taskq, &tx->task); 2021 } 2022 2023 STATIC int 2024 mvneta_xmit_locked(struct mvneta_softc *sc, int q) 2025 { 2026 struct ifnet *ifp; 2027 struct mvneta_tx_ring *tx; 2028 struct mbuf *m; 2029 int error; 2030 2031 KASSERT_TX_MTX(sc, q); 2032 ifp = sc->ifp; 2033 tx = MVNETA_TX_RING(sc, 0); 2034 error = 0; 2035 2036 while (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 2037 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 2038 if (m == NULL) 2039 break; 2040 2041 error = mvneta_xmitfast_locked(sc, q, &m); 2042 if (__predict_false(error != 0)) { 2043 if (m != NULL) 2044 IFQ_DRV_PREPEND(&ifp->if_snd, m); 2045 break; 2046 } 2047 } 2048 2049 return (error); 2050 } 2051 #endif 2052 2053 STATIC int 2054 mvneta_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 2055 { 2056 struct mvneta_softc *sc; 2057 struct mvneta_rx_ring *rx; 2058 struct ifreq *ifr; 2059 int error, mask; 2060 uint32_t flags; 2061 int q; 2062 2063 error = 0; 2064 sc = ifp->if_softc; 2065 ifr = (struct ifreq *)data; 2066 switch (cmd) { 2067 case SIOCSIFFLAGS: 2068 mvneta_sc_lock(sc); 2069 if (ifp->if_flags & IFF_UP) { 2070 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 2071 flags = ifp->if_flags ^ sc->mvneta_if_flags; 2072 2073 if (flags != 0) 2074 sc->mvneta_if_flags = ifp->if_flags; 2075 2076 if ((flags & IFF_PROMISC) != 0) 2077 mvneta_filter_setup(sc); 2078 } else { 2079 mvneta_init_locked(sc); 2080 sc->mvneta_if_flags = ifp->if_flags; 2081 if (sc->phy_attached) 2082 mii_mediachg(sc->mii); 2083 mvneta_sc_unlock(sc); 2084 break; 2085 } 2086 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2087 mvneta_stop_locked(sc); 2088 2089 sc->mvneta_if_flags = ifp->if_flags; 2090 mvneta_sc_unlock(sc); 2091 break; 2092 case SIOCSIFCAP: 2093 if (ifp->if_mtu > sc->tx_csum_limit && 2094 ifr->ifr_reqcap & IFCAP_TXCSUM) 2095 ifr->ifr_reqcap &= ~IFCAP_TXCSUM; 2096 mask = ifp->if_capenable ^ ifr->ifr_reqcap; 2097 if (mask & IFCAP_HWCSUM) { 2098 ifp->if_capenable &= ~IFCAP_HWCSUM; 2099 ifp->if_capenable |= IFCAP_HWCSUM & ifr->ifr_reqcap; 2100 if (ifp->if_capenable & IFCAP_TXCSUM) 2101 ifp->if_hwassist = CSUM_IP | CSUM_TCP | 2102 CSUM_UDP; 2103 else 2104 ifp->if_hwassist = 0; 2105 } 2106 if (mask & IFCAP_LRO) { 2107 mvneta_sc_lock(sc); 2108 ifp->if_capenable ^= IFCAP_LRO; 2109 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2110 for (q = 0; q < MVNETA_RX_QNUM_MAX; q++) { 2111 rx = MVNETA_RX_RING(sc, q); 2112 rx->lro_enabled = !rx->lro_enabled; 2113 } 2114 } 2115 mvneta_sc_unlock(sc); 2116 } 2117 VLAN_CAPABILITIES(ifp); 2118 break; 2119 case SIOCSIFMEDIA: 2120 if ((IFM_SUBTYPE(ifr->ifr_media) == IFM_1000_T || 2121 IFM_SUBTYPE(ifr->ifr_media) == IFM_2500_T) && 2122 (ifr->ifr_media & IFM_FDX) == 0) { 2123 device_printf(sc->dev, 2124 "%s half-duplex unsupported\n", 2125 IFM_SUBTYPE(ifr->ifr_media) == IFM_1000_T ? 2126 "1000Base-T" : 2127 "2500Base-T"); 2128 error = EINVAL; 2129 break; 2130 } 2131 case SIOCGIFMEDIA: /* FALLTHROUGH */ 2132 case SIOCGIFXMEDIA: 2133 if (!sc->phy_attached) 2134 error = ifmedia_ioctl(ifp, ifr, &sc->mvneta_ifmedia, 2135 cmd); 2136 else 2137 error = ifmedia_ioctl(ifp, ifr, &sc->mii->mii_media, 2138 cmd); 2139 break; 2140 case SIOCSIFMTU: 2141 if (ifr->ifr_mtu < 68 || ifr->ifr_mtu > MVNETA_MAX_FRAME - 2142 MVNETA_ETHER_SIZE) { 2143 error = EINVAL; 2144 } else { 2145 ifp->if_mtu = ifr->ifr_mtu; 2146 mvneta_sc_lock(sc); 2147 if (ifp->if_mtu + MVNETA_ETHER_SIZE <= MCLBYTES) { 2148 sc->rx_frame_size = MCLBYTES; 2149 } else { 2150 sc->rx_frame_size = MJUM9BYTES; 2151 } 2152 if (ifp->if_mtu > sc->tx_csum_limit) { 2153 ifp->if_capenable &= ~IFCAP_TXCSUM; 2154 ifp->if_hwassist = 0; 2155 } else { 2156 ifp->if_capenable |= IFCAP_TXCSUM; 2157 ifp->if_hwassist = CSUM_IP | CSUM_TCP | 2158 CSUM_UDP; 2159 } 2160 /* 2161 * Reinitialize RX queues. 2162 * We need to update RX descriptor size. 2163 */ 2164 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2165 mvneta_stop_locked(sc); 2166 2167 for (q = 0; q < MVNETA_RX_QNUM_MAX; q++) { 2168 mvneta_rx_lockq(sc, q); 2169 if (mvneta_rx_queue_init(ifp, q) != 0) { 2170 device_printf(sc->dev, 2171 "initialization failed:" 2172 " cannot initialize queue\n"); 2173 mvneta_rx_unlockq(sc, q); 2174 error = ENOBUFS; 2175 break; 2176 } 2177 mvneta_rx_unlockq(sc, q); 2178 } 2179 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2180 mvneta_init_locked(sc); 2181 2182 mvneta_sc_unlock(sc); 2183 } 2184 break; 2185 2186 default: 2187 error = ether_ioctl(ifp, cmd, data); 2188 break; 2189 } 2190 2191 return (error); 2192 } 2193 2194 STATIC void 2195 mvneta_init_locked(void *arg) 2196 { 2197 struct mvneta_softc *sc; 2198 struct ifnet *ifp; 2199 uint32_t reg; 2200 int q, cpu; 2201 2202 sc = arg; 2203 ifp = sc->ifp; 2204 2205 if (!device_is_attached(sc->dev) || 2206 (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2207 return; 2208 2209 mvneta_disable_intr(sc); 2210 callout_stop(&sc->tick_ch); 2211 2212 /* Get the latest mac address */ 2213 bcopy(IF_LLADDR(ifp), sc->enaddr, ETHER_ADDR_LEN); 2214 mvneta_set_mac_address(sc, sc->enaddr); 2215 mvneta_filter_setup(sc); 2216 2217 /* Start DMA Engine */ 2218 MVNETA_WRITE(sc, MVNETA_PRXINIT, 0x00000000); 2219 MVNETA_WRITE(sc, MVNETA_PTXINIT, 0x00000000); 2220 MVNETA_WRITE(sc, MVNETA_PACC, MVNETA_PACC_ACCELERATIONMODE_EDM); 2221 2222 /* Enable port */ 2223 reg = MVNETA_READ(sc, MVNETA_PMACC0); 2224 reg |= MVNETA_PMACC0_PORTEN; 2225 reg &= ~MVNETA_PMACC0_FRAMESIZELIMIT_MASK; 2226 reg |= MVNETA_PMACC0_FRAMESIZELIMIT(ifp->if_mtu + MVNETA_ETHER_SIZE); 2227 MVNETA_WRITE(sc, MVNETA_PMACC0, reg); 2228 2229 /* Allow access to each TXQ/RXQ from both CPU's */ 2230 for (cpu = 0; cpu < mp_ncpus; ++cpu) 2231 MVNETA_WRITE(sc, MVNETA_PCP2Q(cpu), 2232 MVNETA_PCP2Q_TXQEN_MASK | MVNETA_PCP2Q_RXQEN_MASK); 2233 2234 for (q = 0; q < MVNETA_RX_QNUM_MAX; q++) { 2235 mvneta_rx_lockq(sc, q); 2236 mvneta_rx_queue_refill(sc, q); 2237 mvneta_rx_unlockq(sc, q); 2238 } 2239 2240 if (!sc->phy_attached) 2241 mvneta_linkup(sc); 2242 2243 /* Enable interrupt */ 2244 mvneta_enable_intr(sc); 2245 2246 /* Set Counter */ 2247 callout_schedule(&sc->tick_ch, hz); 2248 2249 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2250 } 2251 2252 STATIC void 2253 mvneta_init(void *arg) 2254 { 2255 struct mvneta_softc *sc; 2256 2257 sc = arg; 2258 mvneta_sc_lock(sc); 2259 mvneta_init_locked(sc); 2260 if (sc->phy_attached) 2261 mii_mediachg(sc->mii); 2262 mvneta_sc_unlock(sc); 2263 } 2264 2265 /* ARGSUSED */ 2266 STATIC void 2267 mvneta_stop_locked(struct mvneta_softc *sc) 2268 { 2269 struct ifnet *ifp; 2270 struct mvneta_rx_ring *rx; 2271 struct mvneta_tx_ring *tx; 2272 uint32_t reg; 2273 int q; 2274 2275 ifp = sc->ifp; 2276 if (ifp == NULL || (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 2277 return; 2278 2279 mvneta_disable_intr(sc); 2280 2281 callout_stop(&sc->tick_ch); 2282 2283 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2284 2285 /* Link down */ 2286 if (sc->linkup == TRUE) 2287 mvneta_linkdown(sc); 2288 2289 /* Reset the MAC Port Enable bit */ 2290 reg = MVNETA_READ(sc, MVNETA_PMACC0); 2291 reg &= ~MVNETA_PMACC0_PORTEN; 2292 MVNETA_WRITE(sc, MVNETA_PMACC0, reg); 2293 2294 /* Disable each of queue */ 2295 for (q = 0; q < MVNETA_RX_QNUM_MAX; q++) { 2296 rx = MVNETA_RX_RING(sc, q); 2297 2298 mvneta_rx_lockq(sc, q); 2299 mvneta_ring_flush_rx_queue(sc, q); 2300 mvneta_rx_unlockq(sc, q); 2301 } 2302 2303 /* 2304 * Hold Reset state of DMA Engine 2305 * (must write 0x0 to restart it) 2306 */ 2307 MVNETA_WRITE(sc, MVNETA_PRXINIT, 0x00000001); 2308 MVNETA_WRITE(sc, MVNETA_PTXINIT, 0x00000001); 2309 2310 for (q = 0; q < MVNETA_TX_QNUM_MAX; q++) { 2311 tx = MVNETA_TX_RING(sc, q); 2312 2313 mvneta_tx_lockq(sc, q); 2314 mvneta_ring_flush_tx_queue(sc, q); 2315 mvneta_tx_unlockq(sc, q); 2316 } 2317 } 2318 2319 STATIC void 2320 mvneta_stop(struct mvneta_softc *sc) 2321 { 2322 2323 mvneta_sc_lock(sc); 2324 mvneta_stop_locked(sc); 2325 mvneta_sc_unlock(sc); 2326 } 2327 2328 STATIC int 2329 mvneta_mediachange(struct ifnet *ifp) 2330 { 2331 struct mvneta_softc *sc; 2332 2333 sc = ifp->if_softc; 2334 2335 if (!sc->phy_attached && !sc->use_inband_status) { 2336 /* We shouldn't be here */ 2337 if_printf(ifp, "Cannot change media in fixed-link mode!\n"); 2338 return (0); 2339 } 2340 2341 if (sc->use_inband_status) { 2342 mvneta_update_media(sc, sc->mvneta_ifmedia.ifm_media); 2343 return (0); 2344 } 2345 2346 mvneta_sc_lock(sc); 2347 2348 /* Update PHY */ 2349 mii_mediachg(sc->mii); 2350 2351 mvneta_sc_unlock(sc); 2352 2353 return (0); 2354 } 2355 2356 STATIC void 2357 mvneta_get_media(struct mvneta_softc *sc, struct ifmediareq *ifmr) 2358 { 2359 uint32_t psr; 2360 2361 psr = MVNETA_READ(sc, MVNETA_PSR); 2362 2363 /* Speed */ 2364 if (psr & MVNETA_PSR_GMIISPEED) 2365 ifmr->ifm_active = IFM_ETHER_SUBTYPE_SET(IFM_1000_T); 2366 else if (psr & MVNETA_PSR_MIISPEED) 2367 ifmr->ifm_active = IFM_ETHER_SUBTYPE_SET(IFM_100_TX); 2368 else if (psr & MVNETA_PSR_LINKUP) 2369 ifmr->ifm_active = IFM_ETHER_SUBTYPE_SET(IFM_10_T); 2370 2371 /* Duplex */ 2372 if (psr & MVNETA_PSR_FULLDX) 2373 ifmr->ifm_active |= IFM_FDX; 2374 2375 /* Link */ 2376 ifmr->ifm_status = IFM_AVALID; 2377 if (psr & MVNETA_PSR_LINKUP) 2378 ifmr->ifm_status |= IFM_ACTIVE; 2379 } 2380 2381 STATIC void 2382 mvneta_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 2383 { 2384 struct mvneta_softc *sc; 2385 struct mii_data *mii; 2386 2387 sc = ifp->if_softc; 2388 2389 if (!sc->phy_attached && !sc->use_inband_status) { 2390 ifmr->ifm_status = IFM_AVALID | IFM_ACTIVE; 2391 return; 2392 } 2393 2394 mvneta_sc_lock(sc); 2395 2396 if (sc->use_inband_status) { 2397 mvneta_get_media(sc, ifmr); 2398 mvneta_sc_unlock(sc); 2399 return; 2400 } 2401 2402 mii = sc->mii; 2403 mii_pollstat(mii); 2404 2405 ifmr->ifm_active = mii->mii_media_active; 2406 ifmr->ifm_status = mii->mii_media_status; 2407 2408 mvneta_sc_unlock(sc); 2409 } 2410 2411 /* 2412 * Link State Notify 2413 */ 2414 STATIC void 2415 mvneta_update_autoneg(struct mvneta_softc *sc, int enable) 2416 { 2417 int reg; 2418 2419 if (enable) { 2420 reg = MVNETA_READ(sc, MVNETA_PANC); 2421 reg &= ~(MVNETA_PANC_FORCELINKFAIL | MVNETA_PANC_FORCELINKPASS | 2422 MVNETA_PANC_ANFCEN); 2423 reg |= MVNETA_PANC_ANDUPLEXEN | MVNETA_PANC_ANSPEEDEN | 2424 MVNETA_PANC_INBANDANEN; 2425 MVNETA_WRITE(sc, MVNETA_PANC, reg); 2426 2427 reg = MVNETA_READ(sc, MVNETA_PMACC2); 2428 reg |= MVNETA_PMACC2_INBANDANMODE; 2429 MVNETA_WRITE(sc, MVNETA_PMACC2, reg); 2430 2431 reg = MVNETA_READ(sc, MVNETA_PSOMSCD); 2432 reg |= MVNETA_PSOMSCD_ENABLE; 2433 MVNETA_WRITE(sc, MVNETA_PSOMSCD, reg); 2434 } else { 2435 reg = MVNETA_READ(sc, MVNETA_PANC); 2436 reg &= ~(MVNETA_PANC_FORCELINKFAIL | MVNETA_PANC_FORCELINKPASS | 2437 MVNETA_PANC_ANDUPLEXEN | MVNETA_PANC_ANSPEEDEN | 2438 MVNETA_PANC_INBANDANEN); 2439 MVNETA_WRITE(sc, MVNETA_PANC, reg); 2440 2441 reg = MVNETA_READ(sc, MVNETA_PMACC2); 2442 reg &= ~MVNETA_PMACC2_INBANDANMODE; 2443 MVNETA_WRITE(sc, MVNETA_PMACC2, reg); 2444 2445 reg = MVNETA_READ(sc, MVNETA_PSOMSCD); 2446 reg &= ~MVNETA_PSOMSCD_ENABLE; 2447 MVNETA_WRITE(sc, MVNETA_PSOMSCD, reg); 2448 } 2449 } 2450 2451 STATIC int 2452 mvneta_update_media(struct mvneta_softc *sc, int media) 2453 { 2454 int reg, err; 2455 boolean_t running; 2456 2457 err = 0; 2458 2459 mvneta_sc_lock(sc); 2460 2461 mvneta_linkreset(sc); 2462 2463 running = (sc->ifp->if_drv_flags & IFF_DRV_RUNNING) != 0; 2464 if (running) 2465 mvneta_stop_locked(sc); 2466 2467 sc->autoneg = (IFM_SUBTYPE(media) == IFM_AUTO); 2468 2469 if (sc->use_inband_status) 2470 mvneta_update_autoneg(sc, IFM_SUBTYPE(media) == IFM_AUTO); 2471 2472 mvneta_update_eee(sc); 2473 mvneta_update_fc(sc); 2474 2475 if (IFM_SUBTYPE(media) != IFM_AUTO) { 2476 reg = MVNETA_READ(sc, MVNETA_PANC); 2477 reg &= ~(MVNETA_PANC_SETGMIISPEED | 2478 MVNETA_PANC_SETMIISPEED | 2479 MVNETA_PANC_SETFULLDX); 2480 if (IFM_SUBTYPE(media) == IFM_1000_T || 2481 IFM_SUBTYPE(media) == IFM_2500_T) { 2482 if ((media & IFM_FDX) == 0) { 2483 device_printf(sc->dev, 2484 "%s half-duplex unsupported\n", 2485 IFM_SUBTYPE(media) == IFM_1000_T ? 2486 "1000Base-T" : 2487 "2500Base-T"); 2488 err = EINVAL; 2489 goto out; 2490 } 2491 reg |= MVNETA_PANC_SETGMIISPEED; 2492 } else if (IFM_SUBTYPE(media) == IFM_100_TX) 2493 reg |= MVNETA_PANC_SETMIISPEED; 2494 2495 if (media & IFM_FDX) 2496 reg |= MVNETA_PANC_SETFULLDX; 2497 2498 MVNETA_WRITE(sc, MVNETA_PANC, reg); 2499 } 2500 out: 2501 if (running) 2502 mvneta_init_locked(sc); 2503 mvneta_sc_unlock(sc); 2504 return (err); 2505 } 2506 2507 STATIC void 2508 mvneta_adjust_link(struct mvneta_softc *sc) 2509 { 2510 boolean_t phy_linkup; 2511 int reg; 2512 2513 /* Update eee/fc */ 2514 mvneta_update_eee(sc); 2515 mvneta_update_fc(sc); 2516 2517 /* Check for link change */ 2518 phy_linkup = (sc->mii->mii_media_status & 2519 (IFM_AVALID | IFM_ACTIVE)) == (IFM_AVALID | IFM_ACTIVE); 2520 2521 if (sc->linkup != phy_linkup) 2522 mvneta_linkupdate(sc, phy_linkup); 2523 2524 /* Don't update media on disabled link */ 2525 if (!phy_linkup) 2526 return; 2527 2528 /* Check for media type change */ 2529 if (sc->mvneta_media != sc->mii->mii_media_active) { 2530 sc->mvneta_media = sc->mii->mii_media_active; 2531 2532 reg = MVNETA_READ(sc, MVNETA_PANC); 2533 reg &= ~(MVNETA_PANC_SETGMIISPEED | 2534 MVNETA_PANC_SETMIISPEED | 2535 MVNETA_PANC_SETFULLDX); 2536 if (IFM_SUBTYPE(sc->mvneta_media) == IFM_1000_T || 2537 IFM_SUBTYPE(sc->mvneta_media) == IFM_2500_T) { 2538 reg |= MVNETA_PANC_SETGMIISPEED; 2539 } else if (IFM_SUBTYPE(sc->mvneta_media) == IFM_100_TX) 2540 reg |= MVNETA_PANC_SETMIISPEED; 2541 2542 if (sc->mvneta_media & IFM_FDX) 2543 reg |= MVNETA_PANC_SETFULLDX; 2544 2545 MVNETA_WRITE(sc, MVNETA_PANC, reg); 2546 } 2547 } 2548 2549 STATIC void 2550 mvneta_link_isr(struct mvneta_softc *sc) 2551 { 2552 int linkup; 2553 2554 KASSERT_SC_MTX(sc); 2555 2556 linkup = MVNETA_IS_LINKUP(sc) ? TRUE : FALSE; 2557 if (sc->linkup == linkup) 2558 return; 2559 2560 if (linkup == TRUE) 2561 mvneta_linkup(sc); 2562 else 2563 mvneta_linkdown(sc); 2564 2565 #ifdef DEBUG 2566 device_printf(sc->dev, 2567 "%s: link %s\n", sc->ifp->if_xname, linkup ? "up" : "down"); 2568 #endif 2569 } 2570 2571 STATIC void 2572 mvneta_linkupdate(struct mvneta_softc *sc, boolean_t linkup) 2573 { 2574 2575 KASSERT_SC_MTX(sc); 2576 2577 if (linkup == TRUE) 2578 mvneta_linkup(sc); 2579 else 2580 mvneta_linkdown(sc); 2581 2582 #ifdef DEBUG 2583 device_printf(sc->dev, 2584 "%s: link %s\n", sc->ifp->if_xname, linkup ? "up" : "down"); 2585 #endif 2586 } 2587 2588 STATIC void 2589 mvneta_update_eee(struct mvneta_softc *sc) 2590 { 2591 uint32_t reg; 2592 2593 KASSERT_SC_MTX(sc); 2594 2595 /* set EEE parameters */ 2596 reg = MVNETA_READ(sc, MVNETA_LPIC1); 2597 if (sc->cf_lpi) 2598 reg |= MVNETA_LPIC1_LPIRE; 2599 else 2600 reg &= ~MVNETA_LPIC1_LPIRE; 2601 MVNETA_WRITE(sc, MVNETA_LPIC1, reg); 2602 } 2603 2604 STATIC void 2605 mvneta_update_fc(struct mvneta_softc *sc) 2606 { 2607 uint32_t reg; 2608 2609 KASSERT_SC_MTX(sc); 2610 2611 reg = MVNETA_READ(sc, MVNETA_PANC); 2612 if (sc->cf_fc) { 2613 /* Flow control negotiation */ 2614 reg |= MVNETA_PANC_PAUSEADV; 2615 reg |= MVNETA_PANC_ANFCEN; 2616 } else { 2617 /* Disable flow control negotiation */ 2618 reg &= ~MVNETA_PANC_PAUSEADV; 2619 reg &= ~MVNETA_PANC_ANFCEN; 2620 } 2621 2622 MVNETA_WRITE(sc, MVNETA_PANC, reg); 2623 } 2624 2625 STATIC void 2626 mvneta_linkup(struct mvneta_softc *sc) 2627 { 2628 uint32_t reg; 2629 2630 KASSERT_SC_MTX(sc); 2631 2632 if (!sc->use_inband_status) { 2633 reg = MVNETA_READ(sc, MVNETA_PANC); 2634 reg |= MVNETA_PANC_FORCELINKPASS; 2635 reg &= ~MVNETA_PANC_FORCELINKFAIL; 2636 MVNETA_WRITE(sc, MVNETA_PANC, reg); 2637 } 2638 2639 mvneta_qflush(sc->ifp); 2640 mvneta_portup(sc); 2641 sc->linkup = TRUE; 2642 if_link_state_change(sc->ifp, LINK_STATE_UP); 2643 } 2644 2645 STATIC void 2646 mvneta_linkdown(struct mvneta_softc *sc) 2647 { 2648 uint32_t reg; 2649 2650 KASSERT_SC_MTX(sc); 2651 2652 if (!sc->use_inband_status) { 2653 reg = MVNETA_READ(sc, MVNETA_PANC); 2654 reg &= ~MVNETA_PANC_FORCELINKPASS; 2655 reg |= MVNETA_PANC_FORCELINKFAIL; 2656 MVNETA_WRITE(sc, MVNETA_PANC, reg); 2657 } 2658 2659 mvneta_portdown(sc); 2660 mvneta_qflush(sc->ifp); 2661 sc->linkup = FALSE; 2662 if_link_state_change(sc->ifp, LINK_STATE_DOWN); 2663 } 2664 2665 STATIC void 2666 mvneta_linkreset(struct mvneta_softc *sc) 2667 { 2668 struct mii_softc *mii; 2669 2670 if (sc->phy_attached) { 2671 /* Force reset PHY */ 2672 mii = LIST_FIRST(&sc->mii->mii_phys); 2673 if (mii) 2674 mii_phy_reset(mii); 2675 } 2676 } 2677 2678 /* 2679 * Tx Subroutines 2680 */ 2681 STATIC int 2682 mvneta_tx_queue(struct mvneta_softc *sc, struct mbuf **mbufp, int q) 2683 { 2684 struct ifnet *ifp; 2685 bus_dma_segment_t txsegs[MVNETA_TX_SEGLIMIT]; 2686 struct mbuf *mtmp, *mbuf; 2687 struct mvneta_tx_ring *tx; 2688 struct mvneta_buf *txbuf; 2689 struct mvneta_tx_desc *t; 2690 uint32_t ptxsu; 2691 int start, used, error, i, txnsegs; 2692 2693 mbuf = *mbufp; 2694 tx = MVNETA_TX_RING(sc, q); 2695 DASSERT(tx->used >= 0); 2696 DASSERT(tx->used <= MVNETA_TX_RING_CNT); 2697 t = NULL; 2698 ifp = sc->ifp; 2699 2700 if (__predict_false(mbuf->m_flags & M_VLANTAG)) { 2701 mbuf = ether_vlanencap(mbuf, mbuf->m_pkthdr.ether_vtag); 2702 if (mbuf == NULL) { 2703 tx->drv_error++; 2704 *mbufp = NULL; 2705 return (ENOBUFS); 2706 } 2707 mbuf->m_flags &= ~M_VLANTAG; 2708 *mbufp = mbuf; 2709 } 2710 2711 if (__predict_false(mbuf->m_next != NULL && 2712 (mbuf->m_pkthdr.csum_flags & 2713 (CSUM_IP | CSUM_TCP | CSUM_UDP)) != 0)) { 2714 if (M_WRITABLE(mbuf) == 0) { 2715 mtmp = m_dup(mbuf, M_NOWAIT); 2716 m_freem(mbuf); 2717 if (mtmp == NULL) { 2718 tx->drv_error++; 2719 *mbufp = NULL; 2720 return (ENOBUFS); 2721 } 2722 *mbufp = mbuf = mtmp; 2723 } 2724 } 2725 2726 /* load mbuf using dmamap of 1st descriptor */ 2727 txbuf = &tx->txbuf[tx->cpu]; 2728 error = bus_dmamap_load_mbuf_sg(sc->txmbuf_dtag, 2729 txbuf->dmap, mbuf, txsegs, &txnsegs, 2730 BUS_DMA_NOWAIT); 2731 if (__predict_false(error != 0)) { 2732 #ifdef MVNETA_KTR 2733 CTR3(KTR_SPARE2, "%s:%u bus_dmamap_load_mbuf_sg error=%d", ifp->if_xname, q, error); 2734 #endif 2735 /* This is the only recoverable error (except EFBIG). */ 2736 if (error != ENOMEM) { 2737 tx->drv_error++; 2738 m_freem(mbuf); 2739 *mbufp = NULL; 2740 return (ENOBUFS); 2741 } 2742 return (error); 2743 } 2744 2745 if (__predict_false(txnsegs <= 0 2746 || (txnsegs + tx->used) > MVNETA_TX_RING_CNT)) { 2747 /* we have no enough descriptors or mbuf is broken */ 2748 #ifdef MVNETA_KTR 2749 CTR3(KTR_SPARE2, "%s:%u not enough descriptors txnsegs=%d", 2750 ifp->if_xname, q, txnsegs); 2751 #endif 2752 bus_dmamap_unload(sc->txmbuf_dtag, txbuf->dmap); 2753 return (ENOBUFS); 2754 } 2755 DASSERT(txbuf->m == NULL); 2756 2757 /* remember mbuf using 1st descriptor */ 2758 txbuf->m = mbuf; 2759 bus_dmamap_sync(sc->txmbuf_dtag, txbuf->dmap, 2760 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2761 2762 /* load to tx descriptors */ 2763 start = tx->cpu; 2764 used = 0; 2765 for (i = 0; i < txnsegs; i++) { 2766 t = &tx->desc[tx->cpu]; 2767 t->command = 0; 2768 t->l4ichk = 0; 2769 t->flags = 0; 2770 if (__predict_true(i == 0)) { 2771 /* 1st descriptor */ 2772 t->command |= MVNETA_TX_CMD_W_PACKET_OFFSET(0); 2773 t->command |= MVNETA_TX_CMD_F; 2774 mvneta_tx_set_csumflag(ifp, t, mbuf); 2775 } 2776 t->bufptr_pa = txsegs[i].ds_addr; 2777 t->bytecnt = txsegs[i].ds_len; 2778 tx->cpu = tx_counter_adv(tx->cpu, 1); 2779 2780 tx->used++; 2781 used++; 2782 } 2783 /* t is last descriptor here */ 2784 DASSERT(t != NULL); 2785 t->command |= MVNETA_TX_CMD_L|MVNETA_TX_CMD_PADDING; 2786 2787 bus_dmamap_sync(sc->tx_dtag, tx->desc_map, 2788 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2789 2790 while (__predict_false(used > 255)) { 2791 ptxsu = MVNETA_PTXSU_NOWD(255); 2792 MVNETA_WRITE(sc, MVNETA_PTXSU(q), ptxsu); 2793 used -= 255; 2794 } 2795 if (__predict_true(used > 0)) { 2796 ptxsu = MVNETA_PTXSU_NOWD(used); 2797 MVNETA_WRITE(sc, MVNETA_PTXSU(q), ptxsu); 2798 } 2799 return (0); 2800 } 2801 2802 STATIC void 2803 mvneta_tx_set_csumflag(struct ifnet *ifp, 2804 struct mvneta_tx_desc *t, struct mbuf *m) 2805 { 2806 struct ether_header *eh; 2807 struct ether_vlan_header *evh; 2808 int csum_flags; 2809 uint32_t iphl, ipoff; 2810 struct ip *ip; 2811 2812 iphl = ipoff = 0; 2813 csum_flags = ifp->if_hwassist & m->m_pkthdr.csum_flags; 2814 eh = mtod(m, struct ether_header *); 2815 2816 switch (ntohs(eh->ether_type)) { 2817 case ETHERTYPE_IP: 2818 ipoff = ETHER_HDR_LEN; 2819 break; 2820 case ETHERTYPE_VLAN: 2821 ipoff = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 2822 evh = mtod(m, struct ether_vlan_header *); 2823 if (ntohs(evh->evl_proto) == ETHERTYPE_VLAN) 2824 ipoff += ETHER_VLAN_ENCAP_LEN; 2825 break; 2826 default: 2827 csum_flags = 0; 2828 } 2829 2830 if (__predict_true(csum_flags & (CSUM_IP|CSUM_IP_TCP|CSUM_IP_UDP))) { 2831 ip = (struct ip *)(m->m_data + ipoff); 2832 iphl = ip->ip_hl<<2; 2833 t->command |= MVNETA_TX_CMD_L3_IP4; 2834 } else { 2835 t->command |= MVNETA_TX_CMD_L4_CHECKSUM_NONE; 2836 return; 2837 } 2838 2839 2840 /* L3 */ 2841 if (csum_flags & CSUM_IP) { 2842 t->command |= MVNETA_TX_CMD_IP4_CHECKSUM; 2843 } 2844 2845 /* L4 */ 2846 if (csum_flags & CSUM_IP_TCP) { 2847 t->command |= MVNETA_TX_CMD_L4_CHECKSUM_NOFRAG; 2848 t->command |= MVNETA_TX_CMD_L4_TCP; 2849 } else if (csum_flags & CSUM_IP_UDP) { 2850 t->command |= MVNETA_TX_CMD_L4_CHECKSUM_NOFRAG; 2851 t->command |= MVNETA_TX_CMD_L4_UDP; 2852 } else 2853 t->command |= MVNETA_TX_CMD_L4_CHECKSUM_NONE; 2854 2855 t->l4ichk = 0; 2856 t->command |= MVNETA_TX_CMD_IP_HEADER_LEN(iphl >> 2); 2857 t->command |= MVNETA_TX_CMD_L3_OFFSET(ipoff); 2858 } 2859 2860 STATIC void 2861 mvneta_tx_queue_complete(struct mvneta_softc *sc, int q) 2862 { 2863 struct mvneta_tx_ring *tx; 2864 struct mvneta_buf *txbuf; 2865 struct mvneta_tx_desc *t; 2866 uint32_t ptxs, ptxsu, ndesc; 2867 int i; 2868 2869 KASSERT_TX_MTX(sc, q); 2870 2871 tx = MVNETA_TX_RING(sc, q); 2872 if (__predict_false(tx->queue_status == MVNETA_QUEUE_DISABLED)) 2873 return; 2874 2875 ptxs = MVNETA_READ(sc, MVNETA_PTXS(q)); 2876 ndesc = MVNETA_PTXS_GET_TBC(ptxs); 2877 2878 if (__predict_false(ndesc == 0)) { 2879 if (tx->used == 0) 2880 tx->queue_status = MVNETA_QUEUE_IDLE; 2881 else if (tx->queue_status == MVNETA_QUEUE_WORKING && 2882 ((ticks - tx->watchdog_time) > MVNETA_WATCHDOG)) 2883 tx->queue_hung = TRUE; 2884 return; 2885 } 2886 2887 #ifdef MVNETA_KTR 2888 CTR3(KTR_SPARE2, "%s:%u tx_complete begin ndesc=%u", 2889 sc->ifp->if_xname, q, ndesc); 2890 #endif 2891 2892 bus_dmamap_sync(sc->tx_dtag, tx->desc_map, 2893 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2894 2895 for (i = 0; i < ndesc; i++) { 2896 t = &tx->desc[tx->dma]; 2897 #ifdef MVNETA_KTR 2898 if (t->flags & MVNETA_TX_F_ES) 2899 CTR3(KTR_SPARE2, "%s tx error queue %d desc %d", 2900 sc->ifp->if_xname, q, tx->dma); 2901 #endif 2902 txbuf = &tx->txbuf[tx->dma]; 2903 if (__predict_true(txbuf->m != NULL)) { 2904 DASSERT((t->command & MVNETA_TX_CMD_F) != 0); 2905 bus_dmamap_unload(sc->txmbuf_dtag, txbuf->dmap); 2906 m_freem(txbuf->m); 2907 txbuf->m = NULL; 2908 } 2909 else 2910 DASSERT((t->flags & MVNETA_TX_CMD_F) == 0); 2911 tx->dma = tx_counter_adv(tx->dma, 1); 2912 tx->used--; 2913 } 2914 DASSERT(tx->used >= 0); 2915 DASSERT(tx->used <= MVNETA_TX_RING_CNT); 2916 while (__predict_false(ndesc > 255)) { 2917 ptxsu = MVNETA_PTXSU_NORB(255); 2918 MVNETA_WRITE(sc, MVNETA_PTXSU(q), ptxsu); 2919 ndesc -= 255; 2920 } 2921 if (__predict_true(ndesc > 0)) { 2922 ptxsu = MVNETA_PTXSU_NORB(ndesc); 2923 MVNETA_WRITE(sc, MVNETA_PTXSU(q), ptxsu); 2924 } 2925 #ifdef MVNETA_KTR 2926 CTR5(KTR_SPARE2, "%s:%u tx_complete tx_cpu=%d tx_dma=%d tx_used=%d", 2927 sc->ifp->if_xname, q, tx->cpu, tx->dma, tx->used); 2928 #endif 2929 2930 tx->watchdog_time = ticks; 2931 2932 if (tx->used == 0) 2933 tx->queue_status = MVNETA_QUEUE_IDLE; 2934 } 2935 2936 /* 2937 * Do a final TX complete when TX is idle. 2938 */ 2939 STATIC void 2940 mvneta_tx_drain(struct mvneta_softc *sc) 2941 { 2942 struct mvneta_tx_ring *tx; 2943 int q; 2944 2945 /* 2946 * Handle trailing mbuf on TX queue. 2947 * Check is done lockess to avoid TX path contention. 2948 */ 2949 for (q = 0; q < MVNETA_TX_QNUM_MAX; q++) { 2950 tx = MVNETA_TX_RING(sc, q); 2951 if ((ticks - tx->watchdog_time) > MVNETA_WATCHDOG_TXCOMP && 2952 tx->used > 0) { 2953 mvneta_tx_lockq(sc, q); 2954 mvneta_tx_queue_complete(sc, q); 2955 mvneta_tx_unlockq(sc, q); 2956 } 2957 } 2958 } 2959 2960 /* 2961 * Rx Subroutines 2962 */ 2963 STATIC int 2964 mvneta_rx(struct mvneta_softc *sc, int q, int count) 2965 { 2966 uint32_t prxs, npkt; 2967 int more; 2968 2969 more = 0; 2970 mvneta_rx_lockq(sc, q); 2971 prxs = MVNETA_READ(sc, MVNETA_PRXS(q)); 2972 npkt = MVNETA_PRXS_GET_ODC(prxs); 2973 if (__predict_false(npkt == 0)) 2974 goto out; 2975 2976 if (count > 0 && npkt > count) { 2977 more = 1; 2978 npkt = count; 2979 } 2980 mvneta_rx_queue(sc, q, npkt); 2981 out: 2982 mvneta_rx_unlockq(sc, q); 2983 return more; 2984 } 2985 2986 /* 2987 * Helper routine for updating PRXSU register of a given queue. 2988 * Handles number of processed descriptors bigger than maximum acceptable value. 2989 */ 2990 STATIC __inline void 2991 mvneta_prxsu_update(struct mvneta_softc *sc, int q, int processed) 2992 { 2993 uint32_t prxsu; 2994 2995 while (__predict_false(processed > 255)) { 2996 prxsu = MVNETA_PRXSU_NOOFPROCESSEDDESCRIPTORS(255); 2997 MVNETA_WRITE(sc, MVNETA_PRXSU(q), prxsu); 2998 processed -= 255; 2999 } 3000 prxsu = MVNETA_PRXSU_NOOFPROCESSEDDESCRIPTORS(processed); 3001 MVNETA_WRITE(sc, MVNETA_PRXSU(q), prxsu); 3002 } 3003 3004 static __inline void 3005 mvneta_prefetch(void *p) 3006 { 3007 3008 __builtin_prefetch(p); 3009 } 3010 3011 STATIC void 3012 mvneta_rx_queue(struct mvneta_softc *sc, int q, int npkt) 3013 { 3014 struct ifnet *ifp; 3015 struct mvneta_rx_ring *rx; 3016 struct mvneta_rx_desc *r; 3017 struct mvneta_buf *rxbuf; 3018 struct mbuf *m; 3019 struct lro_ctrl *lro; 3020 struct lro_entry *queued; 3021 void *pktbuf; 3022 int i, pktlen, processed, ndma; 3023 3024 KASSERT_RX_MTX(sc, q); 3025 3026 ifp = sc->ifp; 3027 rx = MVNETA_RX_RING(sc, q); 3028 processed = 0; 3029 3030 if (__predict_false(rx->queue_status == MVNETA_QUEUE_DISABLED)) 3031 return; 3032 3033 bus_dmamap_sync(sc->rx_dtag, rx->desc_map, 3034 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3035 3036 for (i = 0; i < npkt; i++) { 3037 /* Prefetch next desc, rxbuf. */ 3038 ndma = rx_counter_adv(rx->dma, 1); 3039 mvneta_prefetch(&rx->desc[ndma]); 3040 mvneta_prefetch(&rx->rxbuf[ndma]); 3041 3042 /* get descriptor and packet */ 3043 r = &rx->desc[rx->dma]; 3044 rxbuf = &rx->rxbuf[rx->dma]; 3045 m = rxbuf->m; 3046 rxbuf->m = NULL; 3047 DASSERT(m != NULL); 3048 bus_dmamap_sync(sc->rxbuf_dtag, rxbuf->dmap, 3049 BUS_DMASYNC_POSTREAD); 3050 bus_dmamap_unload(sc->rxbuf_dtag, rxbuf->dmap); 3051 /* Prefetch mbuf header. */ 3052 mvneta_prefetch(m); 3053 3054 processed++; 3055 /* Drop desc with error status or not in a single buffer. */ 3056 DASSERT((r->status & (MVNETA_RX_F|MVNETA_RX_L)) == 3057 (MVNETA_RX_F|MVNETA_RX_L)); 3058 if (__predict_false((r->status & MVNETA_RX_ES) || 3059 (r->status & (MVNETA_RX_F|MVNETA_RX_L)) != 3060 (MVNETA_RX_F|MVNETA_RX_L))) 3061 goto rx_error; 3062 3063 /* 3064 * [ OFF | MH | PKT | CRC ] 3065 * bytecnt cover MH, PKT, CRC 3066 */ 3067 pktlen = r->bytecnt - ETHER_CRC_LEN - MVNETA_HWHEADER_SIZE; 3068 pktbuf = (uint8_t *)rx->rxbuf_virt_addr[rx->dma] + MVNETA_PACKET_OFFSET + 3069 MVNETA_HWHEADER_SIZE; 3070 3071 /* Prefetch mbuf data. */ 3072 mvneta_prefetch(pktbuf); 3073 3074 /* Write value to mbuf (avoid read). */ 3075 m->m_data = pktbuf; 3076 m->m_len = m->m_pkthdr.len = pktlen; 3077 m->m_pkthdr.rcvif = ifp; 3078 mvneta_rx_set_csumflag(ifp, r, m); 3079 3080 /* Increase rx_dma before releasing the lock. */ 3081 rx->dma = ndma; 3082 3083 if (__predict_false(rx->lro_enabled && 3084 ((r->status & MVNETA_RX_L3_IP) != 0) && 3085 ((r->status & MVNETA_RX_L4_MASK) == MVNETA_RX_L4_TCP) && 3086 (m->m_pkthdr.csum_flags & 3087 (CSUM_DATA_VALID | CSUM_PSEUDO_HDR)) == 3088 (CSUM_DATA_VALID | CSUM_PSEUDO_HDR))) { 3089 if (rx->lro.lro_cnt != 0) { 3090 if (tcp_lro_rx(&rx->lro, m, 0) == 0) 3091 goto rx_done; 3092 } 3093 } 3094 3095 mvneta_rx_unlockq(sc, q); 3096 (*ifp->if_input)(ifp, m); 3097 mvneta_rx_lockq(sc, q); 3098 /* 3099 * Check whether this queue has been disabled in the 3100 * meantime. If yes, then clear LRO and exit. 3101 */ 3102 if(__predict_false(rx->queue_status == MVNETA_QUEUE_DISABLED)) 3103 goto rx_lro; 3104 rx_done: 3105 /* Refresh receive ring to avoid stall and minimize jitter. */ 3106 if (processed >= MVNETA_RX_REFILL_COUNT) { 3107 mvneta_prxsu_update(sc, q, processed); 3108 mvneta_rx_queue_refill(sc, q); 3109 processed = 0; 3110 } 3111 continue; 3112 rx_error: 3113 m_freem(m); 3114 rx->dma = ndma; 3115 /* Refresh receive ring to avoid stall and minimize jitter. */ 3116 if (processed >= MVNETA_RX_REFILL_COUNT) { 3117 mvneta_prxsu_update(sc, q, processed); 3118 mvneta_rx_queue_refill(sc, q); 3119 processed = 0; 3120 } 3121 } 3122 #ifdef MVNETA_KTR 3123 CTR3(KTR_SPARE2, "%s:%u %u packets received", ifp->if_xname, q, npkt); 3124 #endif 3125 /* DMA status update */ 3126 mvneta_prxsu_update(sc, q, processed); 3127 /* Refill the rest of buffers if there are any to refill */ 3128 mvneta_rx_queue_refill(sc, q); 3129 3130 rx_lro: 3131 /* 3132 * Flush any outstanding LRO work 3133 */ 3134 lro = &rx->lro; 3135 while (__predict_false((queued = LIST_FIRST(&lro->lro_active)) != NULL)) { 3136 LIST_REMOVE(LIST_FIRST((&lro->lro_active)), next); 3137 tcp_lro_flush(lro, queued); 3138 } 3139 } 3140 3141 STATIC void 3142 mvneta_rx_buf_free(struct mvneta_softc *sc, struct mvneta_buf *rxbuf) 3143 { 3144 3145 bus_dmamap_unload(sc->rxbuf_dtag, rxbuf->dmap); 3146 /* This will remove all data at once */ 3147 m_freem(rxbuf->m); 3148 } 3149 3150 STATIC void 3151 mvneta_rx_queue_refill(struct mvneta_softc *sc, int q) 3152 { 3153 struct mvneta_rx_ring *rx; 3154 struct mvneta_rx_desc *r; 3155 struct mvneta_buf *rxbuf; 3156 bus_dma_segment_t segs; 3157 struct mbuf *m; 3158 uint32_t prxs, prxsu, ndesc; 3159 int npkt, refill, nsegs, error; 3160 3161 KASSERT_RX_MTX(sc, q); 3162 3163 rx = MVNETA_RX_RING(sc, q); 3164 prxs = MVNETA_READ(sc, MVNETA_PRXS(q)); 3165 ndesc = MVNETA_PRXS_GET_NODC(prxs) + MVNETA_PRXS_GET_ODC(prxs); 3166 refill = MVNETA_RX_RING_CNT - ndesc; 3167 #ifdef MVNETA_KTR 3168 CTR3(KTR_SPARE2, "%s:%u refill %u packets", sc->ifp->if_xname, q, 3169 refill); 3170 #endif 3171 if (__predict_false(refill <= 0)) 3172 return; 3173 3174 for (npkt = 0; npkt < refill; npkt++) { 3175 rxbuf = &rx->rxbuf[rx->cpu]; 3176 m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, sc->rx_frame_size); 3177 if (__predict_false(m == NULL)) { 3178 error = ENOBUFS; 3179 break; 3180 } 3181 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 3182 3183 error = bus_dmamap_load_mbuf_sg(sc->rxbuf_dtag, rxbuf->dmap, 3184 m, &segs, &nsegs, BUS_DMA_NOWAIT); 3185 if (__predict_false(error != 0 || nsegs != 1)) { 3186 KASSERT(1, ("Failed to load Rx mbuf DMA map")); 3187 m_freem(m); 3188 break; 3189 } 3190 3191 /* Add the packet to the ring */ 3192 rxbuf->m = m; 3193 r = &rx->desc[rx->cpu]; 3194 r->bufptr_pa = segs.ds_addr; 3195 rx->rxbuf_virt_addr[rx->cpu] = m->m_data; 3196 3197 rx->cpu = rx_counter_adv(rx->cpu, 1); 3198 } 3199 if (npkt == 0) { 3200 if (refill == MVNETA_RX_RING_CNT) 3201 rx->needs_refill = TRUE; 3202 return; 3203 } 3204 3205 rx->needs_refill = FALSE; 3206 bus_dmamap_sync(sc->rx_dtag, rx->desc_map, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3207 3208 while (__predict_false(npkt > 255)) { 3209 prxsu = MVNETA_PRXSU_NOOFNEWDESCRIPTORS(255); 3210 MVNETA_WRITE(sc, MVNETA_PRXSU(q), prxsu); 3211 npkt -= 255; 3212 } 3213 if (__predict_true(npkt > 0)) { 3214 prxsu = MVNETA_PRXSU_NOOFNEWDESCRIPTORS(npkt); 3215 MVNETA_WRITE(sc, MVNETA_PRXSU(q), prxsu); 3216 } 3217 } 3218 3219 STATIC __inline void 3220 mvneta_rx_set_csumflag(struct ifnet *ifp, 3221 struct mvneta_rx_desc *r, struct mbuf *m) 3222 { 3223 uint32_t csum_flags; 3224 3225 csum_flags = 0; 3226 if (__predict_false((r->status & 3227 (MVNETA_RX_IP_HEADER_OK|MVNETA_RX_L3_IP)) == 0)) 3228 return; /* not a IP packet */ 3229 3230 /* L3 */ 3231 if (__predict_true((r->status & MVNETA_RX_IP_HEADER_OK) == 3232 MVNETA_RX_IP_HEADER_OK)) 3233 csum_flags |= CSUM_L3_CALC|CSUM_L3_VALID; 3234 3235 if (__predict_true((r->status & (MVNETA_RX_IP_HEADER_OK|MVNETA_RX_L3_IP)) == 3236 (MVNETA_RX_IP_HEADER_OK|MVNETA_RX_L3_IP))) { 3237 /* L4 */ 3238 switch (r->status & MVNETA_RX_L4_MASK) { 3239 case MVNETA_RX_L4_TCP: 3240 case MVNETA_RX_L4_UDP: 3241 csum_flags |= CSUM_L4_CALC; 3242 if (__predict_true((r->status & 3243 MVNETA_RX_L4_CHECKSUM_OK) == MVNETA_RX_L4_CHECKSUM_OK)) { 3244 csum_flags |= CSUM_L4_VALID; 3245 m->m_pkthdr.csum_data = htons(0xffff); 3246 } 3247 break; 3248 case MVNETA_RX_L4_OTH: 3249 default: 3250 break; 3251 } 3252 } 3253 m->m_pkthdr.csum_flags = csum_flags; 3254 } 3255 3256 /* 3257 * MAC address filter 3258 */ 3259 STATIC void 3260 mvneta_filter_setup(struct mvneta_softc *sc) 3261 { 3262 struct ifnet *ifp; 3263 uint32_t dfut[MVNETA_NDFUT], dfsmt[MVNETA_NDFSMT], dfomt[MVNETA_NDFOMT]; 3264 uint32_t pxc; 3265 int i; 3266 3267 KASSERT_SC_MTX(sc); 3268 3269 memset(dfut, 0, sizeof(dfut)); 3270 memset(dfsmt, 0, sizeof(dfsmt)); 3271 memset(dfomt, 0, sizeof(dfomt)); 3272 3273 ifp = sc->ifp; 3274 ifp->if_flags |= IFF_ALLMULTI; 3275 if (ifp->if_flags & (IFF_ALLMULTI|IFF_PROMISC)) { 3276 for (i = 0; i < MVNETA_NDFSMT; i++) { 3277 dfsmt[i] = dfomt[i] = 3278 MVNETA_DF(0, MVNETA_DF_QUEUE(0) | MVNETA_DF_PASS) | 3279 MVNETA_DF(1, MVNETA_DF_QUEUE(0) | MVNETA_DF_PASS) | 3280 MVNETA_DF(2, MVNETA_DF_QUEUE(0) | MVNETA_DF_PASS) | 3281 MVNETA_DF(3, MVNETA_DF_QUEUE(0) | MVNETA_DF_PASS); 3282 } 3283 } 3284 3285 pxc = MVNETA_READ(sc, MVNETA_PXC); 3286 pxc &= ~(MVNETA_PXC_UPM | MVNETA_PXC_RXQ_MASK | MVNETA_PXC_RXQARP_MASK | 3287 MVNETA_PXC_TCPQ_MASK | MVNETA_PXC_UDPQ_MASK | MVNETA_PXC_BPDUQ_MASK); 3288 pxc |= MVNETA_PXC_RXQ(MVNETA_RX_QNUM_MAX-1); 3289 pxc |= MVNETA_PXC_RXQARP(MVNETA_RX_QNUM_MAX-1); 3290 pxc |= MVNETA_PXC_TCPQ(MVNETA_RX_QNUM_MAX-1); 3291 pxc |= MVNETA_PXC_UDPQ(MVNETA_RX_QNUM_MAX-1); 3292 pxc |= MVNETA_PXC_BPDUQ(MVNETA_RX_QNUM_MAX-1); 3293 pxc |= MVNETA_PXC_RB | MVNETA_PXC_RBIP | MVNETA_PXC_RBARP; 3294 if (ifp->if_flags & IFF_BROADCAST) { 3295 pxc &= ~(MVNETA_PXC_RB | MVNETA_PXC_RBIP | MVNETA_PXC_RBARP); 3296 } 3297 if (ifp->if_flags & IFF_PROMISC) { 3298 pxc |= MVNETA_PXC_UPM; 3299 } 3300 MVNETA_WRITE(sc, MVNETA_PXC, pxc); 3301 3302 /* Set Destination Address Filter Unicast Table */ 3303 if (ifp->if_flags & IFF_PROMISC) { 3304 /* pass all unicast addresses */ 3305 for (i = 0; i < MVNETA_NDFUT; i++) { 3306 dfut[i] = 3307 MVNETA_DF(0, MVNETA_DF_QUEUE(0) | MVNETA_DF_PASS) | 3308 MVNETA_DF(1, MVNETA_DF_QUEUE(0) | MVNETA_DF_PASS) | 3309 MVNETA_DF(2, MVNETA_DF_QUEUE(0) | MVNETA_DF_PASS) | 3310 MVNETA_DF(3, MVNETA_DF_QUEUE(0) | MVNETA_DF_PASS); 3311 } 3312 } else { 3313 i = sc->enaddr[5] & 0xf; /* last nibble */ 3314 dfut[i>>2] = MVNETA_DF(i&3, MVNETA_DF_QUEUE(0) | MVNETA_DF_PASS); 3315 } 3316 MVNETA_WRITE_REGION(sc, MVNETA_DFUT(0), dfut, MVNETA_NDFUT); 3317 3318 /* Set Destination Address Filter Multicast Tables */ 3319 MVNETA_WRITE_REGION(sc, MVNETA_DFSMT(0), dfsmt, MVNETA_NDFSMT); 3320 MVNETA_WRITE_REGION(sc, MVNETA_DFOMT(0), dfomt, MVNETA_NDFOMT); 3321 } 3322 3323 /* 3324 * sysctl(9) 3325 */ 3326 STATIC int 3327 sysctl_read_mib(SYSCTL_HANDLER_ARGS) 3328 { 3329 struct mvneta_sysctl_mib *arg; 3330 struct mvneta_softc *sc; 3331 uint64_t val; 3332 3333 arg = (struct mvneta_sysctl_mib *)arg1; 3334 if (arg == NULL) 3335 return (EINVAL); 3336 3337 sc = arg->sc; 3338 if (sc == NULL) 3339 return (EINVAL); 3340 if (arg->index < 0 || arg->index > MVNETA_PORTMIB_NOCOUNTER) 3341 return (EINVAL); 3342 3343 mvneta_sc_lock(sc); 3344 val = arg->counter; 3345 mvneta_sc_unlock(sc); 3346 return sysctl_handle_64(oidp, &val, 0, req); 3347 } 3348 3349 3350 STATIC int 3351 sysctl_clear_mib(SYSCTL_HANDLER_ARGS) 3352 { 3353 struct mvneta_softc *sc; 3354 int err, val; 3355 3356 val = 0; 3357 sc = (struct mvneta_softc *)arg1; 3358 if (sc == NULL) 3359 return (EINVAL); 3360 3361 err = sysctl_handle_int(oidp, &val, 0, req); 3362 if (err != 0) 3363 return (err); 3364 3365 if (val < 0 || val > 1) 3366 return (EINVAL); 3367 3368 if (val == 1) { 3369 mvneta_sc_lock(sc); 3370 mvneta_clear_mib(sc); 3371 mvneta_sc_unlock(sc); 3372 } 3373 3374 return (0); 3375 } 3376 3377 STATIC int 3378 sysctl_set_queue_rxthtime(SYSCTL_HANDLER_ARGS) 3379 { 3380 struct mvneta_sysctl_queue *arg; 3381 struct mvneta_rx_ring *rx; 3382 struct mvneta_softc *sc; 3383 uint32_t reg, time_mvtclk; 3384 int err, time_us; 3385 3386 rx = NULL; 3387 arg = (struct mvneta_sysctl_queue *)arg1; 3388 if (arg == NULL) 3389 return (EINVAL); 3390 if (arg->queue < 0 || arg->queue > MVNETA_RX_RING_CNT) 3391 return (EINVAL); 3392 if (arg->rxtx != MVNETA_SYSCTL_RX) 3393 return (EINVAL); 3394 3395 sc = arg->sc; 3396 if (sc == NULL) 3397 return (EINVAL); 3398 3399 /* read queue length */ 3400 mvneta_sc_lock(sc); 3401 mvneta_rx_lockq(sc, arg->queue); 3402 rx = MVNETA_RX_RING(sc, arg->queue); 3403 time_mvtclk = rx->queue_th_time; 3404 time_us = ((uint64_t)time_mvtclk * 1000ULL * 1000ULL) / sc->clk_freq; 3405 mvneta_rx_unlockq(sc, arg->queue); 3406 mvneta_sc_unlock(sc); 3407 3408 err = sysctl_handle_int(oidp, &time_us, 0, req); 3409 if (err != 0) 3410 return (err); 3411 3412 mvneta_sc_lock(sc); 3413 mvneta_rx_lockq(sc, arg->queue); 3414 3415 /* update queue length (0[sec] - 1[sec]) */ 3416 if (time_us < 0 || time_us > (1000 * 1000)) { 3417 mvneta_rx_unlockq(sc, arg->queue); 3418 mvneta_sc_unlock(sc); 3419 return (EINVAL); 3420 } 3421 time_mvtclk = sc->clk_freq * (uint64_t)time_us / (1000ULL * 1000ULL); 3422 rx->queue_th_time = time_mvtclk; 3423 reg = MVNETA_PRXITTH_RITT(rx->queue_th_time); 3424 MVNETA_WRITE(sc, MVNETA_PRXITTH(arg->queue), reg); 3425 mvneta_rx_unlockq(sc, arg->queue); 3426 mvneta_sc_unlock(sc); 3427 3428 return (0); 3429 } 3430 3431 STATIC void 3432 sysctl_mvneta_init(struct mvneta_softc *sc) 3433 { 3434 struct sysctl_ctx_list *ctx; 3435 struct sysctl_oid_list *children; 3436 struct sysctl_oid_list *rxchildren; 3437 struct sysctl_oid_list *qchildren, *mchildren; 3438 struct sysctl_oid *tree; 3439 int i, q; 3440 struct mvneta_sysctl_queue *rxarg; 3441 #define MVNETA_SYSCTL_NAME(num) "queue" # num 3442 static const char *sysctl_queue_names[] = { 3443 MVNETA_SYSCTL_NAME(0), MVNETA_SYSCTL_NAME(1), 3444 MVNETA_SYSCTL_NAME(2), MVNETA_SYSCTL_NAME(3), 3445 MVNETA_SYSCTL_NAME(4), MVNETA_SYSCTL_NAME(5), 3446 MVNETA_SYSCTL_NAME(6), MVNETA_SYSCTL_NAME(7), 3447 }; 3448 #undef MVNETA_SYSCTL_NAME 3449 3450 #ifndef NO_SYSCTL_DESCR 3451 #define MVNETA_SYSCTL_DESCR(num) "configuration parameters for queue " # num 3452 static const char *sysctl_queue_descrs[] = { 3453 MVNETA_SYSCTL_DESCR(0), MVNETA_SYSCTL_DESCR(1), 3454 MVNETA_SYSCTL_DESCR(2), MVNETA_SYSCTL_DESCR(3), 3455 MVNETA_SYSCTL_DESCR(4), MVNETA_SYSCTL_DESCR(5), 3456 MVNETA_SYSCTL_DESCR(6), MVNETA_SYSCTL_DESCR(7), 3457 }; 3458 #undef MVNETA_SYSCTL_DESCR 3459 #endif 3460 3461 3462 ctx = device_get_sysctl_ctx(sc->dev); 3463 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)); 3464 3465 tree = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "rx", 3466 CTLFLAG_RD | CTLFLAG_MPSAFE, 0, "NETA RX"); 3467 rxchildren = SYSCTL_CHILDREN(tree); 3468 tree = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "mib", 3469 CTLFLAG_RD | CTLFLAG_MPSAFE, 0, "NETA MIB"); 3470 mchildren = SYSCTL_CHILDREN(tree); 3471 3472 3473 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "flow_control", 3474 CTLFLAG_RW, &sc->cf_fc, 0, "flow control"); 3475 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "lpi", 3476 CTLFLAG_RW, &sc->cf_lpi, 0, "Low Power Idle"); 3477 3478 /* 3479 * MIB access 3480 */ 3481 /* dev.mvneta.[unit].mib.<mibs> */ 3482 for (i = 0; i < MVNETA_PORTMIB_NOCOUNTER; i++) { 3483 struct mvneta_sysctl_mib *mib_arg = &sc->sysctl_mib[i]; 3484 3485 mib_arg->sc = sc; 3486 mib_arg->index = i; 3487 SYSCTL_ADD_PROC(ctx, mchildren, OID_AUTO, 3488 mvneta_mib_list[i].sysctl_name, 3489 CTLTYPE_U64 | CTLFLAG_RD | CTLFLAG_NEEDGIANT, 3490 (void *)mib_arg, 0, sysctl_read_mib, "I", 3491 mvneta_mib_list[i].desc); 3492 } 3493 SYSCTL_ADD_UQUAD(ctx, mchildren, OID_AUTO, "rx_discard", 3494 CTLFLAG_RD, &sc->counter_pdfc, "Port Rx Discard Frame Counter"); 3495 SYSCTL_ADD_UQUAD(ctx, mchildren, OID_AUTO, "overrun", 3496 CTLFLAG_RD, &sc->counter_pofc, "Port Overrun Frame Counter"); 3497 SYSCTL_ADD_UINT(ctx, mchildren, OID_AUTO, "watchdog", 3498 CTLFLAG_RD, &sc->counter_watchdog, 0, "TX Watchdog Counter"); 3499 3500 SYSCTL_ADD_PROC(ctx, mchildren, OID_AUTO, "reset", 3501 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 3502 (void *)sc, 0, sysctl_clear_mib, "I", "Reset MIB counters"); 3503 3504 for (q = 0; q < MVNETA_RX_QNUM_MAX; q++) { 3505 rxarg = &sc->sysctl_rx_queue[q]; 3506 3507 rxarg->sc = sc; 3508 rxarg->queue = q; 3509 rxarg->rxtx = MVNETA_SYSCTL_RX; 3510 3511 /* hw.mvneta.mvneta[unit].rx.[queue] */ 3512 tree = SYSCTL_ADD_NODE(ctx, rxchildren, OID_AUTO, 3513 sysctl_queue_names[q], CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 3514 sysctl_queue_descrs[q]); 3515 qchildren = SYSCTL_CHILDREN(tree); 3516 3517 /* hw.mvneta.mvneta[unit].rx.[queue].threshold_timer_us */ 3518 SYSCTL_ADD_PROC(ctx, qchildren, OID_AUTO, "threshold_timer_us", 3519 CTLTYPE_UINT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, rxarg, 0, 3520 sysctl_set_queue_rxthtime, "I", 3521 "interrupt coalescing threshold timer [us]"); 3522 } 3523 } 3524 3525 /* 3526 * MIB 3527 */ 3528 STATIC uint64_t 3529 mvneta_read_mib(struct mvneta_softc *sc, int index) 3530 { 3531 struct mvneta_mib_def *mib; 3532 uint64_t val; 3533 3534 mib = &mvneta_mib_list[index]; 3535 val = MVNETA_READ_MIB(sc, mib->regnum); 3536 if (mib->reg64) 3537 val |= (uint64_t)MVNETA_READ_MIB(sc, mib->regnum + 4) << 32; 3538 return (val); 3539 } 3540 3541 STATIC void 3542 mvneta_clear_mib(struct mvneta_softc *sc) 3543 { 3544 int i; 3545 3546 KASSERT_SC_MTX(sc); 3547 3548 for (i = 0; i < nitems(mvneta_mib_list); i++) { 3549 (void)mvneta_read_mib(sc, i); 3550 sc->sysctl_mib[i].counter = 0; 3551 } 3552 MVNETA_READ(sc, MVNETA_PDFC); 3553 sc->counter_pdfc = 0; 3554 MVNETA_READ(sc, MVNETA_POFC); 3555 sc->counter_pofc = 0; 3556 sc->counter_watchdog = 0; 3557 } 3558 3559 STATIC void 3560 mvneta_update_mib(struct mvneta_softc *sc) 3561 { 3562 struct mvneta_tx_ring *tx; 3563 int i; 3564 uint64_t val; 3565 uint32_t reg; 3566 3567 for (i = 0; i < nitems(mvneta_mib_list); i++) { 3568 3569 val = mvneta_read_mib(sc, i); 3570 if (val == 0) 3571 continue; 3572 3573 sc->sysctl_mib[i].counter += val; 3574 switch (mvneta_mib_list[i].regnum) { 3575 case MVNETA_MIB_RX_GOOD_OCT: 3576 if_inc_counter(sc->ifp, IFCOUNTER_IBYTES, val); 3577 break; 3578 case MVNETA_MIB_RX_BAD_FRAME: 3579 if_inc_counter(sc->ifp, IFCOUNTER_IERRORS, val); 3580 break; 3581 case MVNETA_MIB_RX_GOOD_FRAME: 3582 if_inc_counter(sc->ifp, IFCOUNTER_IPACKETS, val); 3583 break; 3584 case MVNETA_MIB_RX_MCAST_FRAME: 3585 if_inc_counter(sc->ifp, IFCOUNTER_IMCASTS, val); 3586 break; 3587 case MVNETA_MIB_TX_GOOD_OCT: 3588 if_inc_counter(sc->ifp, IFCOUNTER_OBYTES, val); 3589 break; 3590 case MVNETA_MIB_TX_GOOD_FRAME: 3591 if_inc_counter(sc->ifp, IFCOUNTER_OPACKETS, val); 3592 break; 3593 case MVNETA_MIB_TX_MCAST_FRAME: 3594 if_inc_counter(sc->ifp, IFCOUNTER_OMCASTS, val); 3595 break; 3596 case MVNETA_MIB_MAC_COL: 3597 if_inc_counter(sc->ifp, IFCOUNTER_COLLISIONS, val); 3598 break; 3599 case MVNETA_MIB_TX_MAC_TRNS_ERR: 3600 case MVNETA_MIB_TX_EXCES_COL: 3601 case MVNETA_MIB_MAC_LATE_COL: 3602 if_inc_counter(sc->ifp, IFCOUNTER_OERRORS, val); 3603 break; 3604 } 3605 } 3606 3607 reg = MVNETA_READ(sc, MVNETA_PDFC); 3608 sc->counter_pdfc += reg; 3609 if_inc_counter(sc->ifp, IFCOUNTER_IQDROPS, reg); 3610 reg = MVNETA_READ(sc, MVNETA_POFC); 3611 sc->counter_pofc += reg; 3612 if_inc_counter(sc->ifp, IFCOUNTER_IQDROPS, reg); 3613 3614 /* TX watchdog. */ 3615 if (sc->counter_watchdog_mib > 0) { 3616 if_inc_counter(sc->ifp, IFCOUNTER_OERRORS, sc->counter_watchdog_mib); 3617 sc->counter_watchdog_mib = 0; 3618 } 3619 /* 3620 * TX driver errors: 3621 * We do not take queue locks to not disrupt TX path. 3622 * We may only miss one drv error which will be fixed at 3623 * next mib update. We may also clear counter when TX path 3624 * is incrementing it but we only do it if counter was not zero 3625 * thus we may only loose one error. 3626 */ 3627 for (i = 0; i < MVNETA_TX_QNUM_MAX; i++) { 3628 tx = MVNETA_TX_RING(sc, i); 3629 3630 if (tx->drv_error > 0) { 3631 if_inc_counter(sc->ifp, IFCOUNTER_OERRORS, tx->drv_error); 3632 tx->drv_error = 0; 3633 } 3634 } 3635 } 3636