1 /* 2 * Copyright (c) 2017 Stormshield. 3 * Copyright (c) 2017 Semihalf. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 24 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include "opt_platform.h" 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/endian.h> 35 #include <sys/mbuf.h> 36 #include <sys/lock.h> 37 #include <sys/mutex.h> 38 #include <sys/kernel.h> 39 #include <sys/module.h> 40 #include <sys/socket.h> 41 #include <sys/sysctl.h> 42 #include <sys/smp.h> 43 #include <sys/taskqueue.h> 44 #ifdef MVNETA_KTR 45 #include <sys/ktr.h> 46 #endif 47 48 #include <net/ethernet.h> 49 #include <net/bpf.h> 50 #include <net/if.h> 51 #include <net/if_arp.h> 52 #include <net/if_dl.h> 53 #include <net/if_media.h> 54 #include <net/if_types.h> 55 #include <net/if_vlan_var.h> 56 57 #include <netinet/in_systm.h> 58 #include <netinet/in.h> 59 #include <netinet/ip.h> 60 #include <netinet/tcp_lro.h> 61 62 #include <sys/sockio.h> 63 #include <sys/bus.h> 64 #include <machine/bus.h> 65 #include <sys/rman.h> 66 #include <machine/resource.h> 67 68 #include <dev/mii/mii.h> 69 #include <dev/mii/miivar.h> 70 71 #include <dev/ofw/openfirm.h> 72 #include <dev/ofw/ofw_bus.h> 73 #include <dev/ofw/ofw_bus_subr.h> 74 75 #include <dev/mdio/mdio.h> 76 77 #include <arm/mv/mvvar.h> 78 79 #if !defined(__aarch64__) 80 #include <arm/mv/mvreg.h> 81 #include <arm/mv/mvwin.h> 82 #endif 83 84 #include "if_mvnetareg.h" 85 #include "if_mvnetavar.h" 86 87 #include "miibus_if.h" 88 #include "mdio_if.h" 89 90 #ifdef MVNETA_DEBUG 91 #define STATIC /* nothing */ 92 #else 93 #define STATIC static 94 #endif 95 96 #define DASSERT(x) KASSERT((x), (#x)) 97 98 #define A3700_TCLK_250MHZ 250000000 99 100 STATIC uint32_t 101 mvneta_get_clk() 102 { 103 #if defined(__aarch64__) 104 return (A3700_TCLK_250MHZ); 105 #else 106 return (get_tclk()); 107 #endif 108 } 109 110 /* Device Register Initialization */ 111 STATIC int mvneta_initreg(struct ifnet *); 112 113 /* Descriptor Ring Control for each of queues */ 114 STATIC int mvneta_ring_alloc_rx_queue(struct mvneta_softc *, int); 115 STATIC int mvneta_ring_alloc_tx_queue(struct mvneta_softc *, int); 116 STATIC void mvneta_ring_dealloc_rx_queue(struct mvneta_softc *, int); 117 STATIC void mvneta_ring_dealloc_tx_queue(struct mvneta_softc *, int); 118 STATIC int mvneta_ring_init_rx_queue(struct mvneta_softc *, int); 119 STATIC int mvneta_ring_init_tx_queue(struct mvneta_softc *, int); 120 STATIC void mvneta_ring_flush_rx_queue(struct mvneta_softc *, int); 121 STATIC void mvneta_ring_flush_tx_queue(struct mvneta_softc *, int); 122 STATIC void mvneta_dmamap_cb(void *, bus_dma_segment_t *, int, int); 123 STATIC int mvneta_dma_create(struct mvneta_softc *); 124 125 /* Rx/Tx Queue Control */ 126 STATIC int mvneta_rx_queue_init(struct ifnet *, int); 127 STATIC int mvneta_tx_queue_init(struct ifnet *, int); 128 STATIC int mvneta_rx_queue_enable(struct ifnet *, int); 129 STATIC int mvneta_tx_queue_enable(struct ifnet *, int); 130 STATIC void mvneta_rx_lockq(struct mvneta_softc *, int); 131 STATIC void mvneta_rx_unlockq(struct mvneta_softc *, int); 132 STATIC void mvneta_tx_lockq(struct mvneta_softc *, int); 133 STATIC void mvneta_tx_unlockq(struct mvneta_softc *, int); 134 135 /* Interrupt Handlers */ 136 STATIC void mvneta_disable_intr(struct mvneta_softc *); 137 STATIC void mvneta_enable_intr(struct mvneta_softc *); 138 STATIC void mvneta_rxtxth_intr(void *); 139 STATIC int mvneta_misc_intr(struct mvneta_softc *); 140 STATIC void mvneta_tick(void *); 141 /* struct ifnet and mii callbacks*/ 142 STATIC int mvneta_xmitfast_locked(struct mvneta_softc *, int, struct mbuf **); 143 STATIC int mvneta_xmit_locked(struct mvneta_softc *, int); 144 #ifdef MVNETA_MULTIQUEUE 145 STATIC int mvneta_transmit(struct ifnet *, struct mbuf *); 146 #else /* !MVNETA_MULTIQUEUE */ 147 STATIC void mvneta_start(struct ifnet *); 148 #endif 149 STATIC void mvneta_qflush(struct ifnet *); 150 STATIC void mvneta_tx_task(void *, int); 151 STATIC int mvneta_ioctl(struct ifnet *, u_long, caddr_t); 152 STATIC void mvneta_init(void *); 153 STATIC void mvneta_init_locked(void *); 154 STATIC void mvneta_stop(struct mvneta_softc *); 155 STATIC void mvneta_stop_locked(struct mvneta_softc *); 156 STATIC int mvneta_mediachange(struct ifnet *); 157 STATIC void mvneta_mediastatus(struct ifnet *, struct ifmediareq *); 158 STATIC void mvneta_portup(struct mvneta_softc *); 159 STATIC void mvneta_portdown(struct mvneta_softc *); 160 161 /* Link State Notify */ 162 STATIC void mvneta_update_autoneg(struct mvneta_softc *, int); 163 STATIC int mvneta_update_media(struct mvneta_softc *, int); 164 STATIC void mvneta_adjust_link(struct mvneta_softc *); 165 STATIC void mvneta_update_eee(struct mvneta_softc *); 166 STATIC void mvneta_update_fc(struct mvneta_softc *); 167 STATIC void mvneta_link_isr(struct mvneta_softc *); 168 STATIC void mvneta_linkupdate(struct mvneta_softc *, boolean_t); 169 STATIC void mvneta_linkup(struct mvneta_softc *); 170 STATIC void mvneta_linkdown(struct mvneta_softc *); 171 STATIC void mvneta_linkreset(struct mvneta_softc *); 172 173 /* Tx Subroutines */ 174 STATIC int mvneta_tx_queue(struct mvneta_softc *, struct mbuf **, int); 175 STATIC void mvneta_tx_set_csumflag(struct ifnet *, 176 struct mvneta_tx_desc *, struct mbuf *); 177 STATIC void mvneta_tx_queue_complete(struct mvneta_softc *, int); 178 STATIC void mvneta_tx_drain(struct mvneta_softc *); 179 180 /* Rx Subroutines */ 181 STATIC int mvneta_rx(struct mvneta_softc *, int, int); 182 STATIC void mvneta_rx_queue(struct mvneta_softc *, int, int); 183 STATIC void mvneta_rx_queue_refill(struct mvneta_softc *, int); 184 STATIC void mvneta_rx_set_csumflag(struct ifnet *, 185 struct mvneta_rx_desc *, struct mbuf *); 186 STATIC void mvneta_rx_buf_free(struct mvneta_softc *, struct mvneta_buf *); 187 188 /* MAC address filter */ 189 STATIC void mvneta_filter_setup(struct mvneta_softc *); 190 191 /* sysctl(9) */ 192 STATIC int sysctl_read_mib(SYSCTL_HANDLER_ARGS); 193 STATIC int sysctl_clear_mib(SYSCTL_HANDLER_ARGS); 194 STATIC int sysctl_set_queue_rxthtime(SYSCTL_HANDLER_ARGS); 195 STATIC void sysctl_mvneta_init(struct mvneta_softc *); 196 197 /* MIB */ 198 STATIC void mvneta_clear_mib(struct mvneta_softc *); 199 STATIC void mvneta_update_mib(struct mvneta_softc *); 200 201 /* Switch */ 202 STATIC boolean_t mvneta_has_switch(device_t); 203 204 #define mvneta_sc_lock(sc) mtx_lock(&sc->mtx) 205 #define mvneta_sc_unlock(sc) mtx_unlock(&sc->mtx) 206 207 STATIC struct mtx mii_mutex; 208 STATIC int mii_init = 0; 209 210 /* Device */ 211 STATIC int mvneta_detach(device_t); 212 /* MII */ 213 STATIC int mvneta_miibus_readreg(device_t, int, int); 214 STATIC int mvneta_miibus_writereg(device_t, int, int, int); 215 216 static device_method_t mvneta_methods[] = { 217 /* Device interface */ 218 DEVMETHOD(device_detach, mvneta_detach), 219 /* MII interface */ 220 DEVMETHOD(miibus_readreg, mvneta_miibus_readreg), 221 DEVMETHOD(miibus_writereg, mvneta_miibus_writereg), 222 /* MDIO interface */ 223 DEVMETHOD(mdio_readreg, mvneta_miibus_readreg), 224 DEVMETHOD(mdio_writereg, mvneta_miibus_writereg), 225 226 /* End */ 227 DEVMETHOD_END 228 }; 229 230 DEFINE_CLASS_0(mvneta, mvneta_driver, mvneta_methods, sizeof(struct mvneta_softc)); 231 232 DRIVER_MODULE(miibus, mvneta, miibus_driver, miibus_devclass, 0, 0); 233 DRIVER_MODULE(mdio, mvneta, mdio_driver, mdio_devclass, 0, 0); 234 MODULE_DEPEND(mvneta, mdio, 1, 1, 1); 235 MODULE_DEPEND(mvneta, ether, 1, 1, 1); 236 MODULE_DEPEND(mvneta, miibus, 1, 1, 1); 237 MODULE_DEPEND(mvneta, mvxpbm, 1, 1, 1); 238 239 /* 240 * List of MIB register and names 241 */ 242 enum mvneta_mib_idx 243 { 244 MVNETA_MIB_RX_GOOD_OCT_IDX, 245 MVNETA_MIB_RX_BAD_OCT_IDX, 246 MVNETA_MIB_TX_MAC_TRNS_ERR_IDX, 247 MVNETA_MIB_RX_GOOD_FRAME_IDX, 248 MVNETA_MIB_RX_BAD_FRAME_IDX, 249 MVNETA_MIB_RX_BCAST_FRAME_IDX, 250 MVNETA_MIB_RX_MCAST_FRAME_IDX, 251 MVNETA_MIB_RX_FRAME64_OCT_IDX, 252 MVNETA_MIB_RX_FRAME127_OCT_IDX, 253 MVNETA_MIB_RX_FRAME255_OCT_IDX, 254 MVNETA_MIB_RX_FRAME511_OCT_IDX, 255 MVNETA_MIB_RX_FRAME1023_OCT_IDX, 256 MVNETA_MIB_RX_FRAMEMAX_OCT_IDX, 257 MVNETA_MIB_TX_GOOD_OCT_IDX, 258 MVNETA_MIB_TX_GOOD_FRAME_IDX, 259 MVNETA_MIB_TX_EXCES_COL_IDX, 260 MVNETA_MIB_TX_MCAST_FRAME_IDX, 261 MVNETA_MIB_TX_BCAST_FRAME_IDX, 262 MVNETA_MIB_TX_MAC_CTL_ERR_IDX, 263 MVNETA_MIB_FC_SENT_IDX, 264 MVNETA_MIB_FC_GOOD_IDX, 265 MVNETA_MIB_FC_BAD_IDX, 266 MVNETA_MIB_PKT_UNDERSIZE_IDX, 267 MVNETA_MIB_PKT_FRAGMENT_IDX, 268 MVNETA_MIB_PKT_OVERSIZE_IDX, 269 MVNETA_MIB_PKT_JABBER_IDX, 270 MVNETA_MIB_MAC_RX_ERR_IDX, 271 MVNETA_MIB_MAC_CRC_ERR_IDX, 272 MVNETA_MIB_MAC_COL_IDX, 273 MVNETA_MIB_MAC_LATE_COL_IDX, 274 }; 275 276 STATIC struct mvneta_mib_def { 277 uint32_t regnum; 278 int reg64; 279 const char *sysctl_name; 280 const char *desc; 281 } mvneta_mib_list[] = { 282 [MVNETA_MIB_RX_GOOD_OCT_IDX] = {MVNETA_MIB_RX_GOOD_OCT, 1, 283 "rx_good_oct", "Good Octets Rx"}, 284 [MVNETA_MIB_RX_BAD_OCT_IDX] = {MVNETA_MIB_RX_BAD_OCT, 0, 285 "rx_bad_oct", "Bad Octets Rx"}, 286 [MVNETA_MIB_TX_MAC_TRNS_ERR_IDX] = {MVNETA_MIB_TX_MAC_TRNS_ERR, 0, 287 "tx_mac_err", "MAC Transmit Error"}, 288 [MVNETA_MIB_RX_GOOD_FRAME_IDX] = {MVNETA_MIB_RX_GOOD_FRAME, 0, 289 "rx_good_frame", "Good Frames Rx"}, 290 [MVNETA_MIB_RX_BAD_FRAME_IDX] = {MVNETA_MIB_RX_BAD_FRAME, 0, 291 "rx_bad_frame", "Bad Frames Rx"}, 292 [MVNETA_MIB_RX_BCAST_FRAME_IDX] = {MVNETA_MIB_RX_BCAST_FRAME, 0, 293 "rx_bcast_frame", "Broadcast Frames Rx"}, 294 [MVNETA_MIB_RX_MCAST_FRAME_IDX] = {MVNETA_MIB_RX_MCAST_FRAME, 0, 295 "rx_mcast_frame", "Multicast Frames Rx"}, 296 [MVNETA_MIB_RX_FRAME64_OCT_IDX] = {MVNETA_MIB_RX_FRAME64_OCT, 0, 297 "rx_frame_1_64", "Frame Size 1 - 64"}, 298 [MVNETA_MIB_RX_FRAME127_OCT_IDX] = {MVNETA_MIB_RX_FRAME127_OCT, 0, 299 "rx_frame_65_127", "Frame Size 65 - 127"}, 300 [MVNETA_MIB_RX_FRAME255_OCT_IDX] = {MVNETA_MIB_RX_FRAME255_OCT, 0, 301 "rx_frame_128_255", "Frame Size 128 - 255"}, 302 [MVNETA_MIB_RX_FRAME511_OCT_IDX] = {MVNETA_MIB_RX_FRAME511_OCT, 0, 303 "rx_frame_256_511", "Frame Size 256 - 511"}, 304 [MVNETA_MIB_RX_FRAME1023_OCT_IDX] = {MVNETA_MIB_RX_FRAME1023_OCT, 0, 305 "rx_frame_512_1023", "Frame Size 512 - 1023"}, 306 [MVNETA_MIB_RX_FRAMEMAX_OCT_IDX] = {MVNETA_MIB_RX_FRAMEMAX_OCT, 0, 307 "rx_fame_1024_max", "Frame Size 1024 - Max"}, 308 [MVNETA_MIB_TX_GOOD_OCT_IDX] = {MVNETA_MIB_TX_GOOD_OCT, 1, 309 "tx_good_oct", "Good Octets Tx"}, 310 [MVNETA_MIB_TX_GOOD_FRAME_IDX] = {MVNETA_MIB_TX_GOOD_FRAME, 0, 311 "tx_good_frame", "Good Frames Tx"}, 312 [MVNETA_MIB_TX_EXCES_COL_IDX] = {MVNETA_MIB_TX_EXCES_COL, 0, 313 "tx_exces_collision", "Excessive Collision"}, 314 [MVNETA_MIB_TX_MCAST_FRAME_IDX] = {MVNETA_MIB_TX_MCAST_FRAME, 0, 315 "tx_mcast_frame", "Multicast Frames Tx"}, 316 [MVNETA_MIB_TX_BCAST_FRAME_IDX] = {MVNETA_MIB_TX_BCAST_FRAME, 0, 317 "tx_bcast_frame", "Broadcast Frames Tx"}, 318 [MVNETA_MIB_TX_MAC_CTL_ERR_IDX] = {MVNETA_MIB_TX_MAC_CTL_ERR, 0, 319 "tx_mac_ctl_err", "Unknown MAC Control"}, 320 [MVNETA_MIB_FC_SENT_IDX] = {MVNETA_MIB_FC_SENT, 0, 321 "fc_tx", "Flow Control Tx"}, 322 [MVNETA_MIB_FC_GOOD_IDX] = {MVNETA_MIB_FC_GOOD, 0, 323 "fc_rx_good", "Good Flow Control Rx"}, 324 [MVNETA_MIB_FC_BAD_IDX] = {MVNETA_MIB_FC_BAD, 0, 325 "fc_rx_bad", "Bad Flow Control Rx"}, 326 [MVNETA_MIB_PKT_UNDERSIZE_IDX] = {MVNETA_MIB_PKT_UNDERSIZE, 0, 327 "pkt_undersize", "Undersized Packets Rx"}, 328 [MVNETA_MIB_PKT_FRAGMENT_IDX] = {MVNETA_MIB_PKT_FRAGMENT, 0, 329 "pkt_fragment", "Fragmented Packets Rx"}, 330 [MVNETA_MIB_PKT_OVERSIZE_IDX] = {MVNETA_MIB_PKT_OVERSIZE, 0, 331 "pkt_oversize", "Oversized Packets Rx"}, 332 [MVNETA_MIB_PKT_JABBER_IDX] = {MVNETA_MIB_PKT_JABBER, 0, 333 "pkt_jabber", "Jabber Packets Rx"}, 334 [MVNETA_MIB_MAC_RX_ERR_IDX] = {MVNETA_MIB_MAC_RX_ERR, 0, 335 "mac_rx_err", "MAC Rx Errors"}, 336 [MVNETA_MIB_MAC_CRC_ERR_IDX] = {MVNETA_MIB_MAC_CRC_ERR, 0, 337 "mac_crc_err", "MAC CRC Errors"}, 338 [MVNETA_MIB_MAC_COL_IDX] = {MVNETA_MIB_MAC_COL, 0, 339 "mac_collision", "MAC Collision"}, 340 [MVNETA_MIB_MAC_LATE_COL_IDX] = {MVNETA_MIB_MAC_LATE_COL, 0, 341 "mac_late_collision", "MAC Late Collision"}, 342 }; 343 344 static struct resource_spec res_spec[] = { 345 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 346 { SYS_RES_IRQ, 0, RF_ACTIVE }, 347 { -1, 0} 348 }; 349 350 static struct { 351 driver_intr_t *handler; 352 char * description; 353 } mvneta_intrs[] = { 354 { mvneta_rxtxth_intr, "MVNETA aggregated interrupt" }, 355 }; 356 357 static int 358 mvneta_set_mac_address(struct mvneta_softc *sc, uint8_t *addr) 359 { 360 unsigned int mac_h; 361 unsigned int mac_l; 362 363 mac_l = (addr[4] << 8) | (addr[5]); 364 mac_h = (addr[0] << 24) | (addr[1] << 16) | 365 (addr[2] << 8) | (addr[3] << 0); 366 367 MVNETA_WRITE(sc, MVNETA_MACAL, mac_l); 368 MVNETA_WRITE(sc, MVNETA_MACAH, mac_h); 369 return (0); 370 } 371 372 static int 373 mvneta_get_mac_address(struct mvneta_softc *sc, uint8_t *addr) 374 { 375 uint32_t mac_l, mac_h; 376 377 #ifdef FDT 378 if (mvneta_fdt_mac_address(sc, addr) == 0) 379 return (0); 380 #endif 381 /* 382 * Fall back -- use the currently programmed address. 383 */ 384 mac_l = MVNETA_READ(sc, MVNETA_MACAL); 385 mac_h = MVNETA_READ(sc, MVNETA_MACAH); 386 if (mac_l == 0 && mac_h == 0) { 387 /* 388 * Generate pseudo-random MAC. 389 * Set lower part to random number | unit number. 390 */ 391 mac_l = arc4random() & ~0xff; 392 mac_l |= device_get_unit(sc->dev) & 0xff; 393 mac_h = arc4random(); 394 mac_h &= ~(3 << 24); /* Clear multicast and LAA bits */ 395 if (bootverbose) { 396 device_printf(sc->dev, 397 "Could not acquire MAC address. " 398 "Using randomized one.\n"); 399 } 400 } 401 402 addr[0] = (mac_h & 0xff000000) >> 24; 403 addr[1] = (mac_h & 0x00ff0000) >> 16; 404 addr[2] = (mac_h & 0x0000ff00) >> 8; 405 addr[3] = (mac_h & 0x000000ff); 406 addr[4] = (mac_l & 0x0000ff00) >> 8; 407 addr[5] = (mac_l & 0x000000ff); 408 return (0); 409 } 410 411 STATIC boolean_t 412 mvneta_has_switch(device_t self) 413 { 414 phandle_t node, switch_node, switch_eth, switch_eth_handle; 415 416 node = ofw_bus_get_node(self); 417 switch_node = 418 ofw_bus_find_compatible(OF_finddevice("/"), "marvell,dsa"); 419 switch_eth = 0; 420 421 OF_getencprop(switch_node, "dsa,ethernet", 422 (void*)&switch_eth_handle, sizeof(switch_eth_handle)); 423 424 if (switch_eth_handle > 0) 425 switch_eth = OF_node_from_xref(switch_eth_handle); 426 427 /* Return true if dsa,ethernet cell points to us */ 428 return (node == switch_eth); 429 } 430 431 STATIC int 432 mvneta_dma_create(struct mvneta_softc *sc) 433 { 434 size_t maxsize, maxsegsz; 435 size_t q; 436 int error; 437 438 /* 439 * Create Tx DMA 440 */ 441 maxsize = maxsegsz = sizeof(struct mvneta_tx_desc) * MVNETA_TX_RING_CNT; 442 443 error = bus_dma_tag_create( 444 bus_get_dma_tag(sc->dev), /* parent */ 445 16, 0, /* alignment, boundary */ 446 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 447 BUS_SPACE_MAXADDR, /* highaddr */ 448 NULL, NULL, /* filtfunc, filtfuncarg */ 449 maxsize, /* maxsize */ 450 1, /* nsegments */ 451 maxsegsz, /* maxsegsz */ 452 0, /* flags */ 453 NULL, NULL, /* lockfunc, lockfuncarg */ 454 &sc->tx_dtag); /* dmat */ 455 if (error != 0) { 456 device_printf(sc->dev, 457 "Failed to create DMA tag for Tx descriptors.\n"); 458 goto fail; 459 } 460 error = bus_dma_tag_create( 461 bus_get_dma_tag(sc->dev), /* parent */ 462 1, 0, /* alignment, boundary */ 463 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 464 BUS_SPACE_MAXADDR, /* highaddr */ 465 NULL, NULL, /* filtfunc, filtfuncarg */ 466 MVNETA_PACKET_SIZE, /* maxsize */ 467 MVNETA_TX_SEGLIMIT, /* nsegments */ 468 MVNETA_PACKET_SIZE, /* maxsegsz */ 469 BUS_DMA_ALLOCNOW, /* flags */ 470 NULL, NULL, /* lockfunc, lockfuncarg */ 471 &sc->txmbuf_dtag); 472 if (error != 0) { 473 device_printf(sc->dev, 474 "Failed to create DMA tag for Tx mbufs.\n"); 475 goto fail; 476 } 477 478 for (q = 0; q < MVNETA_TX_QNUM_MAX; q++) { 479 error = mvneta_ring_alloc_tx_queue(sc, q); 480 if (error != 0) { 481 device_printf(sc->dev, 482 "Failed to allocate DMA safe memory for TxQ: %zu\n", q); 483 goto fail; 484 } 485 } 486 487 /* 488 * Create Rx DMA. 489 */ 490 /* Create tag for Rx descripors */ 491 error = bus_dma_tag_create( 492 bus_get_dma_tag(sc->dev), /* parent */ 493 32, 0, /* alignment, boundary */ 494 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 495 BUS_SPACE_MAXADDR, /* highaddr */ 496 NULL, NULL, /* filtfunc, filtfuncarg */ 497 sizeof(struct mvneta_rx_desc) * MVNETA_RX_RING_CNT, /* maxsize */ 498 1, /* nsegments */ 499 sizeof(struct mvneta_rx_desc) * MVNETA_RX_RING_CNT, /* maxsegsz */ 500 0, /* flags */ 501 NULL, NULL, /* lockfunc, lockfuncarg */ 502 &sc->rx_dtag); /* dmat */ 503 if (error != 0) { 504 device_printf(sc->dev, 505 "Failed to create DMA tag for Rx descriptors.\n"); 506 goto fail; 507 } 508 509 /* Create tag for Rx buffers */ 510 error = bus_dma_tag_create( 511 bus_get_dma_tag(sc->dev), /* parent */ 512 32, 0, /* alignment, boundary */ 513 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 514 BUS_SPACE_MAXADDR, /* highaddr */ 515 NULL, NULL, /* filtfunc, filtfuncarg */ 516 MVNETA_PACKET_SIZE, 1, /* maxsize, nsegments */ 517 MVNETA_PACKET_SIZE, /* maxsegsz */ 518 0, /* flags */ 519 NULL, NULL, /* lockfunc, lockfuncarg */ 520 &sc->rxbuf_dtag); /* dmat */ 521 if (error != 0) { 522 device_printf(sc->dev, 523 "Failed to create DMA tag for Rx buffers.\n"); 524 goto fail; 525 } 526 527 for (q = 0; q < MVNETA_RX_QNUM_MAX; q++) { 528 if (mvneta_ring_alloc_rx_queue(sc, q) != 0) { 529 device_printf(sc->dev, 530 "Failed to allocate DMA safe memory for RxQ: %zu\n", q); 531 goto fail; 532 } 533 } 534 535 return (0); 536 fail: 537 mvneta_detach(sc->dev); 538 539 return (error); 540 } 541 542 /* ARGSUSED */ 543 int 544 mvneta_attach(device_t self) 545 { 546 struct mvneta_softc *sc; 547 struct ifnet *ifp; 548 device_t child; 549 int ifm_target; 550 int q, error; 551 #if !defined(__aarch64__) 552 uint32_t reg; 553 #endif 554 555 sc = device_get_softc(self); 556 sc->dev = self; 557 558 mtx_init(&sc->mtx, "mvneta_sc", NULL, MTX_DEF); 559 560 error = bus_alloc_resources(self, res_spec, sc->res); 561 if (error) { 562 device_printf(self, "could not allocate resources\n"); 563 return (ENXIO); 564 } 565 566 sc->version = MVNETA_READ(sc, MVNETA_PV); 567 device_printf(self, "version is %x\n", sc->version); 568 callout_init(&sc->tick_ch, 0); 569 570 /* 571 * make sure DMA engines are in reset state 572 */ 573 MVNETA_WRITE(sc, MVNETA_PRXINIT, 0x00000001); 574 MVNETA_WRITE(sc, MVNETA_PTXINIT, 0x00000001); 575 576 #if !defined(__aarch64__) 577 /* 578 * Disable port snoop for buffers and descriptors 579 * to avoid L2 caching of both without DRAM copy. 580 * Obtain coherency settings from the first MBUS 581 * window attribute. 582 */ 583 if ((MVNETA_READ(sc, MV_WIN_NETA_BASE(0)) & IO_WIN_COH_ATTR_MASK) == 0) { 584 reg = MVNETA_READ(sc, MVNETA_PSNPCFG); 585 reg &= ~MVNETA_PSNPCFG_DESCSNP_MASK; 586 reg &= ~MVNETA_PSNPCFG_BUFSNP_MASK; 587 MVNETA_WRITE(sc, MVNETA_PSNPCFG, reg); 588 } 589 #endif 590 591 /* 592 * MAC address 593 */ 594 if (mvneta_get_mac_address(sc, sc->enaddr)) { 595 device_printf(self, "no mac address.\n"); 596 return (ENXIO); 597 } 598 mvneta_set_mac_address(sc, sc->enaddr); 599 600 mvneta_disable_intr(sc); 601 602 /* Allocate network interface */ 603 ifp = sc->ifp = if_alloc(IFT_ETHER); 604 if (ifp == NULL) { 605 device_printf(self, "if_alloc() failed\n"); 606 mvneta_detach(self); 607 return (ENOMEM); 608 } 609 if_initname(ifp, device_get_name(self), device_get_unit(self)); 610 611 /* 612 * We can support 802.1Q VLAN-sized frames and jumbo 613 * Ethernet frames. 614 */ 615 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_JUMBO_MTU; 616 617 ifp->if_softc = sc; 618 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 619 #ifdef MVNETA_MULTIQUEUE 620 ifp->if_transmit = mvneta_transmit; 621 ifp->if_qflush = mvneta_qflush; 622 #else /* !MVNETA_MULTIQUEUE */ 623 ifp->if_start = mvneta_start; 624 ifp->if_snd.ifq_drv_maxlen = MVNETA_TX_RING_CNT - 1; 625 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 626 IFQ_SET_READY(&ifp->if_snd); 627 #endif 628 ifp->if_init = mvneta_init; 629 ifp->if_ioctl = mvneta_ioctl; 630 631 /* 632 * We can do IPv4/TCPv4/UDPv4/TCPv6/UDPv6 checksums in hardware. 633 */ 634 ifp->if_capabilities |= IFCAP_HWCSUM; 635 636 /* 637 * As VLAN hardware tagging is not supported 638 * but is necessary to perform VLAN hardware checksums, 639 * it is done in the driver 640 */ 641 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWCSUM; 642 643 /* 644 * Currently IPv6 HW checksum is broken, so make sure it is disabled. 645 */ 646 ifp->if_capabilities &= ~IFCAP_HWCSUM_IPV6; 647 ifp->if_capenable = ifp->if_capabilities; 648 649 /* 650 * Disabled option(s): 651 * - Support for Large Receive Offload 652 */ 653 ifp->if_capabilities |= IFCAP_LRO; 654 655 ifp->if_hwassist = CSUM_IP | CSUM_TCP | CSUM_UDP; 656 657 /* 658 * Device DMA Buffer allocation. 659 * Handles resource deallocation in case of failure. 660 */ 661 error = mvneta_dma_create(sc); 662 if (error != 0) { 663 mvneta_detach(self); 664 return (error); 665 } 666 667 /* Initialize queues */ 668 for (q = 0; q < MVNETA_TX_QNUM_MAX; q++) { 669 error = mvneta_ring_init_tx_queue(sc, q); 670 if (error != 0) { 671 mvneta_detach(self); 672 return (error); 673 } 674 } 675 676 for (q = 0; q < MVNETA_RX_QNUM_MAX; q++) { 677 error = mvneta_ring_init_rx_queue(sc, q); 678 if (error != 0) { 679 mvneta_detach(self); 680 return (error); 681 } 682 } 683 684 ether_ifattach(ifp, sc->enaddr); 685 686 /* 687 * Enable DMA engines and Initialize Device Registers. 688 */ 689 MVNETA_WRITE(sc, MVNETA_PRXINIT, 0x00000000); 690 MVNETA_WRITE(sc, MVNETA_PTXINIT, 0x00000000); 691 MVNETA_WRITE(sc, MVNETA_PACC, MVNETA_PACC_ACCELERATIONMODE_EDM); 692 mvneta_sc_lock(sc); 693 mvneta_filter_setup(sc); 694 mvneta_sc_unlock(sc); 695 mvneta_initreg(ifp); 696 697 /* 698 * Now MAC is working, setup MII. 699 */ 700 if (mii_init == 0) { 701 /* 702 * MII bus is shared by all MACs and all PHYs in SoC. 703 * serializing the bus access should be safe. 704 */ 705 mtx_init(&mii_mutex, "mvneta_mii", NULL, MTX_DEF); 706 mii_init = 1; 707 } 708 709 /* Attach PHY(s) */ 710 if ((sc->phy_addr != MII_PHY_ANY) && (!sc->use_inband_status)) { 711 error = mii_attach(self, &sc->miibus, ifp, mvneta_mediachange, 712 mvneta_mediastatus, BMSR_DEFCAPMASK, sc->phy_addr, 713 MII_OFFSET_ANY, 0); 714 if (error != 0) { 715 if (bootverbose) { 716 device_printf(self, 717 "MII attach failed, error: %d\n", error); 718 } 719 ether_ifdetach(sc->ifp); 720 mvneta_detach(self); 721 return (error); 722 } 723 sc->mii = device_get_softc(sc->miibus); 724 sc->phy_attached = 1; 725 726 /* Disable auto-negotiation in MAC - rely on PHY layer */ 727 mvneta_update_autoneg(sc, FALSE); 728 } else if (sc->use_inband_status == TRUE) { 729 /* In-band link status */ 730 ifmedia_init(&sc->mvneta_ifmedia, 0, mvneta_mediachange, 731 mvneta_mediastatus); 732 733 /* Configure media */ 734 ifmedia_add(&sc->mvneta_ifmedia, IFM_ETHER | IFM_1000_T | IFM_FDX, 735 0, NULL); 736 ifmedia_add(&sc->mvneta_ifmedia, IFM_ETHER | IFM_100_TX, 0, NULL); 737 ifmedia_add(&sc->mvneta_ifmedia, IFM_ETHER | IFM_100_TX | IFM_FDX, 738 0, NULL); 739 ifmedia_add(&sc->mvneta_ifmedia, IFM_ETHER | IFM_10_T, 0, NULL); 740 ifmedia_add(&sc->mvneta_ifmedia, IFM_ETHER | IFM_10_T | IFM_FDX, 741 0, NULL); 742 ifmedia_add(&sc->mvneta_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 743 ifmedia_set(&sc->mvneta_ifmedia, IFM_ETHER | IFM_AUTO); 744 745 /* Enable auto-negotiation */ 746 mvneta_update_autoneg(sc, TRUE); 747 748 mvneta_sc_lock(sc); 749 if (MVNETA_IS_LINKUP(sc)) 750 mvneta_linkup(sc); 751 else 752 mvneta_linkdown(sc); 753 mvneta_sc_unlock(sc); 754 755 } else { 756 /* Fixed-link, use predefined values */ 757 ifmedia_init(&sc->mvneta_ifmedia, 0, mvneta_mediachange, 758 mvneta_mediastatus); 759 760 ifm_target = IFM_ETHER; 761 switch (sc->phy_speed) { 762 case 2500: 763 if (sc->phy_mode != MVNETA_PHY_SGMII && 764 sc->phy_mode != MVNETA_PHY_QSGMII) { 765 device_printf(self, 766 "2.5G speed can work only in (Q)SGMII mode\n"); 767 ether_ifdetach(sc->ifp); 768 mvneta_detach(self); 769 return (ENXIO); 770 } 771 ifm_target |= IFM_2500_T; 772 break; 773 case 1000: 774 ifm_target |= IFM_1000_T; 775 break; 776 case 100: 777 ifm_target |= IFM_100_TX; 778 break; 779 case 10: 780 ifm_target |= IFM_10_T; 781 break; 782 default: 783 ether_ifdetach(sc->ifp); 784 mvneta_detach(self); 785 return (ENXIO); 786 } 787 788 if (sc->phy_fdx) 789 ifm_target |= IFM_FDX; 790 else 791 ifm_target |= IFM_HDX; 792 793 ifmedia_add(&sc->mvneta_ifmedia, ifm_target, 0, NULL); 794 ifmedia_set(&sc->mvneta_ifmedia, ifm_target); 795 if_link_state_change(sc->ifp, LINK_STATE_UP); 796 797 if (mvneta_has_switch(self)) { 798 child = device_add_child(sc->dev, "mdio", -1); 799 if (child == NULL) { 800 ether_ifdetach(sc->ifp); 801 mvneta_detach(self); 802 return (ENXIO); 803 } 804 bus_generic_attach(sc->dev); 805 bus_generic_attach(child); 806 } 807 808 /* Configure MAC media */ 809 mvneta_update_media(sc, ifm_target); 810 } 811 812 sysctl_mvneta_init(sc); 813 814 callout_reset(&sc->tick_ch, 0, mvneta_tick, sc); 815 816 error = bus_setup_intr(self, sc->res[1], 817 INTR_TYPE_NET | INTR_MPSAFE, NULL, mvneta_intrs[0].handler, sc, 818 &sc->ih_cookie[0]); 819 if (error) { 820 device_printf(self, "could not setup %s\n", 821 mvneta_intrs[0].description); 822 ether_ifdetach(sc->ifp); 823 mvneta_detach(self); 824 return (error); 825 } 826 827 return (0); 828 } 829 830 STATIC int 831 mvneta_detach(device_t dev) 832 { 833 struct mvneta_softc *sc; 834 struct ifnet *ifp; 835 int q; 836 837 sc = device_get_softc(dev); 838 ifp = sc->ifp; 839 840 mvneta_stop(sc); 841 /* Detach network interface */ 842 if (sc->ifp) 843 if_free(sc->ifp); 844 845 for (q = 0; q < MVNETA_RX_QNUM_MAX; q++) 846 mvneta_ring_dealloc_rx_queue(sc, q); 847 for (q = 0; q < MVNETA_TX_QNUM_MAX; q++) 848 mvneta_ring_dealloc_tx_queue(sc, q); 849 850 if (sc->tx_dtag != NULL) 851 bus_dma_tag_destroy(sc->tx_dtag); 852 if (sc->rx_dtag != NULL) 853 bus_dma_tag_destroy(sc->rx_dtag); 854 if (sc->txmbuf_dtag != NULL) 855 bus_dma_tag_destroy(sc->txmbuf_dtag); 856 857 bus_release_resources(dev, res_spec, sc->res); 858 return (0); 859 } 860 861 /* 862 * MII 863 */ 864 STATIC int 865 mvneta_miibus_readreg(device_t dev, int phy, int reg) 866 { 867 struct mvneta_softc *sc; 868 struct ifnet *ifp; 869 uint32_t smi, val; 870 int i; 871 872 sc = device_get_softc(dev); 873 ifp = sc->ifp; 874 875 mtx_lock(&mii_mutex); 876 877 for (i = 0; i < MVNETA_PHY_TIMEOUT; i++) { 878 if ((MVNETA_READ(sc, MVNETA_SMI) & MVNETA_SMI_BUSY) == 0) 879 break; 880 DELAY(1); 881 } 882 if (i == MVNETA_PHY_TIMEOUT) { 883 if_printf(ifp, "SMI busy timeout\n"); 884 mtx_unlock(&mii_mutex); 885 return (-1); 886 } 887 888 smi = MVNETA_SMI_PHYAD(phy) | 889 MVNETA_SMI_REGAD(reg) | MVNETA_SMI_OPCODE_READ; 890 MVNETA_WRITE(sc, MVNETA_SMI, smi); 891 892 for (i = 0; i < MVNETA_PHY_TIMEOUT; i++) { 893 if ((MVNETA_READ(sc, MVNETA_SMI) & MVNETA_SMI_BUSY) == 0) 894 break; 895 DELAY(1); 896 } 897 898 if (i == MVNETA_PHY_TIMEOUT) { 899 if_printf(ifp, "SMI busy timeout\n"); 900 mtx_unlock(&mii_mutex); 901 return (-1); 902 } 903 for (i = 0; i < MVNETA_PHY_TIMEOUT; i++) { 904 smi = MVNETA_READ(sc, MVNETA_SMI); 905 if (smi & MVNETA_SMI_READVALID) 906 break; 907 DELAY(1); 908 } 909 910 if (i == MVNETA_PHY_TIMEOUT) { 911 if_printf(ifp, "SMI busy timeout\n"); 912 mtx_unlock(&mii_mutex); 913 return (-1); 914 } 915 916 mtx_unlock(&mii_mutex); 917 918 #ifdef MVNETA_KTR 919 CTR3(KTR_SPARE2, "%s i=%d, timeout=%d\n", ifp->if_xname, i, 920 MVNETA_PHY_TIMEOUT); 921 #endif 922 923 val = smi & MVNETA_SMI_DATA_MASK; 924 925 #ifdef MVNETA_KTR 926 CTR4(KTR_SPARE2, "%s phy=%d, reg=%#x, val=%#x\n", ifp->if_xname, phy, 927 reg, val); 928 #endif 929 return (val); 930 } 931 932 STATIC int 933 mvneta_miibus_writereg(device_t dev, int phy, int reg, int val) 934 { 935 struct mvneta_softc *sc; 936 struct ifnet *ifp; 937 uint32_t smi; 938 int i; 939 940 sc = device_get_softc(dev); 941 ifp = sc->ifp; 942 #ifdef MVNETA_KTR 943 CTR4(KTR_SPARE2, "%s phy=%d, reg=%#x, val=%#x\n", ifp->if_xname, 944 phy, reg, val); 945 #endif 946 947 mtx_lock(&mii_mutex); 948 949 for (i = 0; i < MVNETA_PHY_TIMEOUT; i++) { 950 if ((MVNETA_READ(sc, MVNETA_SMI) & MVNETA_SMI_BUSY) == 0) 951 break; 952 DELAY(1); 953 } 954 if (i == MVNETA_PHY_TIMEOUT) { 955 if_printf(ifp, "SMI busy timeout\n"); 956 mtx_unlock(&mii_mutex); 957 return (0); 958 } 959 960 smi = MVNETA_SMI_PHYAD(phy) | MVNETA_SMI_REGAD(reg) | 961 MVNETA_SMI_OPCODE_WRITE | (val & MVNETA_SMI_DATA_MASK); 962 MVNETA_WRITE(sc, MVNETA_SMI, smi); 963 964 for (i = 0; i < MVNETA_PHY_TIMEOUT; i++) { 965 if ((MVNETA_READ(sc, MVNETA_SMI) & MVNETA_SMI_BUSY) == 0) 966 break; 967 DELAY(1); 968 } 969 970 mtx_unlock(&mii_mutex); 971 972 if (i == MVNETA_PHY_TIMEOUT) 973 if_printf(ifp, "phy write timed out\n"); 974 975 return (0); 976 } 977 978 STATIC void 979 mvneta_portup(struct mvneta_softc *sc) 980 { 981 int q; 982 983 for (q = 0; q < MVNETA_RX_QNUM_MAX; q++) { 984 mvneta_rx_lockq(sc, q); 985 mvneta_rx_queue_enable(sc->ifp, q); 986 mvneta_rx_unlockq(sc, q); 987 } 988 989 for (q = 0; q < MVNETA_TX_QNUM_MAX; q++) { 990 mvneta_tx_lockq(sc, q); 991 mvneta_tx_queue_enable(sc->ifp, q); 992 mvneta_tx_unlockq(sc, q); 993 } 994 995 } 996 997 STATIC void 998 mvneta_portdown(struct mvneta_softc *sc) 999 { 1000 struct mvneta_rx_ring *rx; 1001 struct mvneta_tx_ring *tx; 1002 int q, cnt; 1003 uint32_t reg; 1004 1005 for (q = 0; q < MVNETA_RX_QNUM_MAX; q++) { 1006 rx = MVNETA_RX_RING(sc, q); 1007 mvneta_rx_lockq(sc, q); 1008 rx->queue_status = MVNETA_QUEUE_DISABLED; 1009 mvneta_rx_unlockq(sc, q); 1010 } 1011 1012 for (q = 0; q < MVNETA_TX_QNUM_MAX; q++) { 1013 tx = MVNETA_TX_RING(sc, q); 1014 mvneta_tx_lockq(sc, q); 1015 tx->queue_status = MVNETA_QUEUE_DISABLED; 1016 mvneta_tx_unlockq(sc, q); 1017 } 1018 1019 /* Wait for all Rx activity to terminate. */ 1020 reg = MVNETA_READ(sc, MVNETA_RQC) & MVNETA_RQC_EN_MASK; 1021 reg = MVNETA_RQC_DIS(reg); 1022 MVNETA_WRITE(sc, MVNETA_RQC, reg); 1023 cnt = 0; 1024 do { 1025 if (cnt >= RX_DISABLE_TIMEOUT) { 1026 if_printf(sc->ifp, 1027 "timeout for RX stopped. rqc 0x%x\n", reg); 1028 break; 1029 } 1030 cnt++; 1031 reg = MVNETA_READ(sc, MVNETA_RQC); 1032 } while ((reg & MVNETA_RQC_EN_MASK) != 0); 1033 1034 /* Wait for all Tx activity to terminate. */ 1035 reg = MVNETA_READ(sc, MVNETA_PIE); 1036 reg &= ~MVNETA_PIE_TXPKTINTRPTENB_MASK; 1037 MVNETA_WRITE(sc, MVNETA_PIE, reg); 1038 1039 reg = MVNETA_READ(sc, MVNETA_PRXTXTIM); 1040 reg &= ~MVNETA_PRXTXTI_TBTCQ_MASK; 1041 MVNETA_WRITE(sc, MVNETA_PRXTXTIM, reg); 1042 1043 reg = MVNETA_READ(sc, MVNETA_TQC) & MVNETA_TQC_EN_MASK; 1044 reg = MVNETA_TQC_DIS(reg); 1045 MVNETA_WRITE(sc, MVNETA_TQC, reg); 1046 cnt = 0; 1047 do { 1048 if (cnt >= TX_DISABLE_TIMEOUT) { 1049 if_printf(sc->ifp, 1050 "timeout for TX stopped. tqc 0x%x\n", reg); 1051 break; 1052 } 1053 cnt++; 1054 reg = MVNETA_READ(sc, MVNETA_TQC); 1055 } while ((reg & MVNETA_TQC_EN_MASK) != 0); 1056 1057 /* Wait for all Tx FIFO is empty */ 1058 cnt = 0; 1059 do { 1060 if (cnt >= TX_FIFO_EMPTY_TIMEOUT) { 1061 if_printf(sc->ifp, 1062 "timeout for TX FIFO drained. ps0 0x%x\n", reg); 1063 break; 1064 } 1065 cnt++; 1066 reg = MVNETA_READ(sc, MVNETA_PS0); 1067 } while (((reg & MVNETA_PS0_TXFIFOEMP) == 0) && 1068 ((reg & MVNETA_PS0_TXINPROG) != 0)); 1069 } 1070 1071 /* 1072 * Device Register Initialization 1073 * reset device registers to device driver default value. 1074 * the device is not enabled here. 1075 */ 1076 STATIC int 1077 mvneta_initreg(struct ifnet *ifp) 1078 { 1079 struct mvneta_softc *sc; 1080 int q, i; 1081 uint32_t reg; 1082 1083 sc = ifp->if_softc; 1084 #ifdef MVNETA_KTR 1085 CTR1(KTR_SPARE2, "%s initializing device register", ifp->if_xname); 1086 #endif 1087 1088 /* Disable Legacy WRR, Disable EJP, Release from reset. */ 1089 MVNETA_WRITE(sc, MVNETA_TQC_1, 0); 1090 /* Enable mbus retry. */ 1091 MVNETA_WRITE(sc, MVNETA_MBUS_CONF, MVNETA_MBUS_RETRY_EN); 1092 1093 /* Init TX/RX Queue Registers */ 1094 for (q = 0; q < MVNETA_RX_QNUM_MAX; q++) { 1095 mvneta_rx_lockq(sc, q); 1096 if (mvneta_rx_queue_init(ifp, q) != 0) { 1097 device_printf(sc->dev, 1098 "initialization failed: cannot initialize queue\n"); 1099 mvneta_rx_unlockq(sc, q); 1100 return (ENOBUFS); 1101 } 1102 mvneta_rx_unlockq(sc, q); 1103 } 1104 for (q = 0; q < MVNETA_TX_QNUM_MAX; q++) { 1105 mvneta_tx_lockq(sc, q); 1106 if (mvneta_tx_queue_init(ifp, q) != 0) { 1107 device_printf(sc->dev, 1108 "initialization failed: cannot initialize queue\n"); 1109 mvneta_tx_unlockq(sc, q); 1110 return (ENOBUFS); 1111 } 1112 mvneta_tx_unlockq(sc, q); 1113 } 1114 1115 /* 1116 * Ethernet Unit Control - disable automatic PHY management by HW. 1117 * In case the port uses SMI-controlled PHY, poll its status with 1118 * mii_tick() and update MAC settings accordingly. 1119 */ 1120 reg = MVNETA_READ(sc, MVNETA_EUC); 1121 reg &= ~MVNETA_EUC_POLLING; 1122 MVNETA_WRITE(sc, MVNETA_EUC, reg); 1123 1124 /* EEE: Low Power Idle */ 1125 reg = MVNETA_LPIC0_LILIMIT(MVNETA_LPI_LI); 1126 reg |= MVNETA_LPIC0_TSLIMIT(MVNETA_LPI_TS); 1127 MVNETA_WRITE(sc, MVNETA_LPIC0, reg); 1128 1129 reg = MVNETA_LPIC1_TWLIMIT(MVNETA_LPI_TW); 1130 MVNETA_WRITE(sc, MVNETA_LPIC1, reg); 1131 1132 reg = MVNETA_LPIC2_MUSTSET; 1133 MVNETA_WRITE(sc, MVNETA_LPIC2, reg); 1134 1135 /* Port MAC Control set 0 */ 1136 reg = MVNETA_PMACC0_MUSTSET; /* must write 0x1 */ 1137 reg &= ~MVNETA_PMACC0_PORTEN; /* port is still disabled */ 1138 reg |= MVNETA_PMACC0_FRAMESIZELIMIT(MVNETA_MAX_FRAME); 1139 MVNETA_WRITE(sc, MVNETA_PMACC0, reg); 1140 1141 /* Port MAC Control set 2 */ 1142 reg = MVNETA_READ(sc, MVNETA_PMACC2); 1143 switch (sc->phy_mode) { 1144 case MVNETA_PHY_QSGMII: 1145 reg |= (MVNETA_PMACC2_PCSEN | MVNETA_PMACC2_RGMIIEN); 1146 MVNETA_WRITE(sc, MVNETA_PSERDESCFG, MVNETA_PSERDESCFG_QSGMII); 1147 break; 1148 case MVNETA_PHY_SGMII: 1149 reg |= (MVNETA_PMACC2_PCSEN | MVNETA_PMACC2_RGMIIEN); 1150 MVNETA_WRITE(sc, MVNETA_PSERDESCFG, MVNETA_PSERDESCFG_SGMII); 1151 break; 1152 case MVNETA_PHY_RGMII: 1153 case MVNETA_PHY_RGMII_ID: 1154 reg |= MVNETA_PMACC2_RGMIIEN; 1155 break; 1156 } 1157 reg |= MVNETA_PMACC2_MUSTSET; 1158 reg &= ~MVNETA_PMACC2_PORTMACRESET; 1159 MVNETA_WRITE(sc, MVNETA_PMACC2, reg); 1160 1161 /* Port Configuration Extended: enable Tx CRC generation */ 1162 reg = MVNETA_READ(sc, MVNETA_PXCX); 1163 reg &= ~MVNETA_PXCX_TXCRCDIS; 1164 MVNETA_WRITE(sc, MVNETA_PXCX, reg); 1165 1166 /* clear MIB counter registers(clear by read) */ 1167 for (i = 0; i < nitems(mvneta_mib_list); i++) { 1168 if (mvneta_mib_list[i].reg64) 1169 MVNETA_READ_MIB_8(sc, mvneta_mib_list[i].regnum); 1170 else 1171 MVNETA_READ_MIB_4(sc, mvneta_mib_list[i].regnum); 1172 } 1173 MVNETA_READ(sc, MVNETA_PDFC); 1174 MVNETA_READ(sc, MVNETA_POFC); 1175 1176 /* Set SDC register except IPGINT bits */ 1177 reg = MVNETA_SDC_RXBSZ_16_64BITWORDS; 1178 reg |= MVNETA_SDC_TXBSZ_16_64BITWORDS; 1179 reg |= MVNETA_SDC_BLMR; 1180 reg |= MVNETA_SDC_BLMT; 1181 MVNETA_WRITE(sc, MVNETA_SDC, reg); 1182 1183 return (0); 1184 } 1185 1186 STATIC void 1187 mvneta_dmamap_cb(void *arg, bus_dma_segment_t * segs, int nseg, int error) 1188 { 1189 1190 if (error != 0) 1191 return; 1192 *(bus_addr_t *)arg = segs->ds_addr; 1193 } 1194 1195 STATIC int 1196 mvneta_ring_alloc_rx_queue(struct mvneta_softc *sc, int q) 1197 { 1198 struct mvneta_rx_ring *rx; 1199 struct mvneta_buf *rxbuf; 1200 bus_dmamap_t dmap; 1201 int i, error; 1202 1203 if (q >= MVNETA_RX_QNUM_MAX) 1204 return (EINVAL); 1205 1206 rx = MVNETA_RX_RING(sc, q); 1207 mtx_init(&rx->ring_mtx, "mvneta_rx", NULL, MTX_DEF); 1208 /* Allocate DMA memory for Rx descriptors */ 1209 error = bus_dmamem_alloc(sc->rx_dtag, 1210 (void**)&(rx->desc), 1211 BUS_DMA_NOWAIT | BUS_DMA_ZERO, 1212 &rx->desc_map); 1213 if (error != 0 || rx->desc == NULL) 1214 goto fail; 1215 error = bus_dmamap_load(sc->rx_dtag, rx->desc_map, 1216 rx->desc, 1217 sizeof(struct mvneta_rx_desc) * MVNETA_RX_RING_CNT, 1218 mvneta_dmamap_cb, &rx->desc_pa, BUS_DMA_NOWAIT); 1219 if (error != 0) 1220 goto fail; 1221 1222 for (i = 0; i < MVNETA_RX_RING_CNT; i++) { 1223 error = bus_dmamap_create(sc->rxbuf_dtag, 0, &dmap); 1224 if (error != 0) { 1225 device_printf(sc->dev, 1226 "Failed to create DMA map for Rx buffer num: %d\n", i); 1227 goto fail; 1228 } 1229 rxbuf = &rx->rxbuf[i]; 1230 rxbuf->dmap = dmap; 1231 rxbuf->m = NULL; 1232 } 1233 1234 return (0); 1235 fail: 1236 mvneta_ring_dealloc_rx_queue(sc, q); 1237 device_printf(sc->dev, "DMA Ring buffer allocation failure.\n"); 1238 return (error); 1239 } 1240 1241 STATIC int 1242 mvneta_ring_alloc_tx_queue(struct mvneta_softc *sc, int q) 1243 { 1244 struct mvneta_tx_ring *tx; 1245 int error; 1246 1247 if (q >= MVNETA_TX_QNUM_MAX) 1248 return (EINVAL); 1249 tx = MVNETA_TX_RING(sc, q); 1250 mtx_init(&tx->ring_mtx, "mvneta_tx", NULL, MTX_DEF); 1251 error = bus_dmamem_alloc(sc->tx_dtag, 1252 (void**)&(tx->desc), 1253 BUS_DMA_NOWAIT | BUS_DMA_ZERO, 1254 &tx->desc_map); 1255 if (error != 0 || tx->desc == NULL) 1256 goto fail; 1257 error = bus_dmamap_load(sc->tx_dtag, tx->desc_map, 1258 tx->desc, 1259 sizeof(struct mvneta_tx_desc) * MVNETA_TX_RING_CNT, 1260 mvneta_dmamap_cb, &tx->desc_pa, BUS_DMA_NOWAIT); 1261 if (error != 0) 1262 goto fail; 1263 1264 #ifdef MVNETA_MULTIQUEUE 1265 tx->br = buf_ring_alloc(MVNETA_BUFRING_SIZE, M_DEVBUF, M_NOWAIT, 1266 &tx->ring_mtx); 1267 if (tx->br == NULL) { 1268 device_printf(sc->dev, 1269 "Could not setup buffer ring for TxQ(%d)\n", q); 1270 error = ENOMEM; 1271 goto fail; 1272 } 1273 #endif 1274 1275 return (0); 1276 fail: 1277 mvneta_ring_dealloc_tx_queue(sc, q); 1278 device_printf(sc->dev, "DMA Ring buffer allocation failure.\n"); 1279 return (error); 1280 } 1281 1282 STATIC void 1283 mvneta_ring_dealloc_tx_queue(struct mvneta_softc *sc, int q) 1284 { 1285 struct mvneta_tx_ring *tx; 1286 struct mvneta_buf *txbuf; 1287 void *kva; 1288 int error; 1289 int i; 1290 1291 if (q >= MVNETA_TX_QNUM_MAX) 1292 return; 1293 tx = MVNETA_TX_RING(sc, q); 1294 1295 if (tx->taskq != NULL) { 1296 /* Remove task */ 1297 while (taskqueue_cancel(tx->taskq, &tx->task, NULL) != 0) 1298 taskqueue_drain(tx->taskq, &tx->task); 1299 } 1300 #ifdef MVNETA_MULTIQUEUE 1301 if (tx->br != NULL) 1302 drbr_free(tx->br, M_DEVBUF); 1303 #endif 1304 1305 if (sc->txmbuf_dtag != NULL) { 1306 if (mtx_name(&tx->ring_mtx) != NULL) { 1307 /* 1308 * It is assumed that maps are being loaded after mutex 1309 * is initialized. Therefore we can skip unloading maps 1310 * when mutex is empty. 1311 */ 1312 mvneta_tx_lockq(sc, q); 1313 mvneta_ring_flush_tx_queue(sc, q); 1314 mvneta_tx_unlockq(sc, q); 1315 } 1316 for (i = 0; i < MVNETA_TX_RING_CNT; i++) { 1317 txbuf = &tx->txbuf[i]; 1318 if (txbuf->dmap != NULL) { 1319 error = bus_dmamap_destroy(sc->txmbuf_dtag, 1320 txbuf->dmap); 1321 if (error != 0) { 1322 panic("%s: map busy for Tx descriptor (Q%d, %d)", 1323 __func__, q, i); 1324 } 1325 } 1326 } 1327 } 1328 1329 if (tx->desc_pa != 0) 1330 bus_dmamap_unload(sc->tx_dtag, tx->desc_map); 1331 1332 kva = (void *)tx->desc; 1333 if (kva != NULL) 1334 bus_dmamem_free(sc->tx_dtag, tx->desc, tx->desc_map); 1335 1336 if (mtx_name(&tx->ring_mtx) != NULL) 1337 mtx_destroy(&tx->ring_mtx); 1338 1339 memset(tx, 0, sizeof(*tx)); 1340 } 1341 1342 STATIC void 1343 mvneta_ring_dealloc_rx_queue(struct mvneta_softc *sc, int q) 1344 { 1345 struct mvneta_rx_ring *rx; 1346 struct lro_ctrl *lro; 1347 void *kva; 1348 1349 if (q >= MVNETA_RX_QNUM_MAX) 1350 return; 1351 1352 rx = MVNETA_RX_RING(sc, q); 1353 1354 mvneta_ring_flush_rx_queue(sc, q); 1355 1356 if (rx->desc_pa != 0) 1357 bus_dmamap_unload(sc->rx_dtag, rx->desc_map); 1358 1359 kva = (void *)rx->desc; 1360 if (kva != NULL) 1361 bus_dmamem_free(sc->rx_dtag, rx->desc, rx->desc_map); 1362 1363 lro = &rx->lro; 1364 tcp_lro_free(lro); 1365 1366 if (mtx_name(&rx->ring_mtx) != NULL) 1367 mtx_destroy(&rx->ring_mtx); 1368 1369 memset(rx, 0, sizeof(*rx)); 1370 } 1371 1372 STATIC int 1373 mvneta_ring_init_rx_queue(struct mvneta_softc *sc, int q) 1374 { 1375 struct mvneta_rx_ring *rx; 1376 struct lro_ctrl *lro; 1377 int error; 1378 1379 if (q >= MVNETA_RX_QNUM_MAX) 1380 return (0); 1381 1382 rx = MVNETA_RX_RING(sc, q); 1383 rx->dma = rx->cpu = 0; 1384 rx->queue_th_received = MVNETA_RXTH_COUNT; 1385 rx->queue_th_time = (mvneta_get_clk() / 1000) / 10; /* 0.1 [ms] */ 1386 1387 /* Initialize LRO */ 1388 rx->lro_enabled = FALSE; 1389 if ((sc->ifp->if_capenable & IFCAP_LRO) != 0) { 1390 lro = &rx->lro; 1391 error = tcp_lro_init(lro); 1392 if (error != 0) 1393 device_printf(sc->dev, "LRO Initialization failed!\n"); 1394 else { 1395 rx->lro_enabled = TRUE; 1396 lro->ifp = sc->ifp; 1397 } 1398 } 1399 1400 return (0); 1401 } 1402 1403 STATIC int 1404 mvneta_ring_init_tx_queue(struct mvneta_softc *sc, int q) 1405 { 1406 struct mvneta_tx_ring *tx; 1407 struct mvneta_buf *txbuf; 1408 int i, error; 1409 1410 if (q >= MVNETA_TX_QNUM_MAX) 1411 return (0); 1412 1413 tx = MVNETA_TX_RING(sc, q); 1414 1415 /* Tx handle */ 1416 for (i = 0; i < MVNETA_TX_RING_CNT; i++) { 1417 txbuf = &tx->txbuf[i]; 1418 txbuf->m = NULL; 1419 /* Tx handle needs DMA map for busdma_load_mbuf() */ 1420 error = bus_dmamap_create(sc->txmbuf_dtag, 0, 1421 &txbuf->dmap); 1422 if (error != 0) { 1423 device_printf(sc->dev, 1424 "can't create dma map (tx ring %d)\n", i); 1425 return (error); 1426 } 1427 } 1428 tx->dma = tx->cpu = 0; 1429 tx->used = 0; 1430 tx->drv_error = 0; 1431 tx->queue_status = MVNETA_QUEUE_DISABLED; 1432 tx->queue_hung = FALSE; 1433 1434 tx->ifp = sc->ifp; 1435 tx->qidx = q; 1436 TASK_INIT(&tx->task, 0, mvneta_tx_task, tx); 1437 tx->taskq = taskqueue_create_fast("mvneta_tx_taskq", M_WAITOK, 1438 taskqueue_thread_enqueue, &tx->taskq); 1439 taskqueue_start_threads(&tx->taskq, 1, PI_NET, "%s: tx_taskq(%d)", 1440 device_get_nameunit(sc->dev), q); 1441 1442 return (0); 1443 } 1444 1445 STATIC void 1446 mvneta_ring_flush_tx_queue(struct mvneta_softc *sc, int q) 1447 { 1448 struct mvneta_tx_ring *tx; 1449 struct mvneta_buf *txbuf; 1450 int i; 1451 1452 tx = MVNETA_TX_RING(sc, q); 1453 KASSERT_TX_MTX(sc, q); 1454 1455 /* Tx handle */ 1456 for (i = 0; i < MVNETA_TX_RING_CNT; i++) { 1457 txbuf = &tx->txbuf[i]; 1458 bus_dmamap_unload(sc->txmbuf_dtag, txbuf->dmap); 1459 if (txbuf->m != NULL) { 1460 m_freem(txbuf->m); 1461 txbuf->m = NULL; 1462 } 1463 } 1464 tx->dma = tx->cpu = 0; 1465 tx->used = 0; 1466 } 1467 1468 STATIC void 1469 mvneta_ring_flush_rx_queue(struct mvneta_softc *sc, int q) 1470 { 1471 struct mvneta_rx_ring *rx; 1472 struct mvneta_buf *rxbuf; 1473 int i; 1474 1475 rx = MVNETA_RX_RING(sc, q); 1476 KASSERT_RX_MTX(sc, q); 1477 1478 /* Rx handle */ 1479 for (i = 0; i < MVNETA_RX_RING_CNT; i++) { 1480 rxbuf = &rx->rxbuf[i]; 1481 mvneta_rx_buf_free(sc, rxbuf); 1482 } 1483 rx->dma = rx->cpu = 0; 1484 } 1485 1486 /* 1487 * Rx/Tx Queue Control 1488 */ 1489 STATIC int 1490 mvneta_rx_queue_init(struct ifnet *ifp, int q) 1491 { 1492 struct mvneta_softc *sc; 1493 struct mvneta_rx_ring *rx; 1494 uint32_t reg; 1495 1496 sc = ifp->if_softc; 1497 KASSERT_RX_MTX(sc, q); 1498 rx = MVNETA_RX_RING(sc, q); 1499 DASSERT(rx->desc_pa != 0); 1500 1501 /* descriptor address */ 1502 MVNETA_WRITE(sc, MVNETA_PRXDQA(q), rx->desc_pa); 1503 1504 /* Rx buffer size and descriptor ring size */ 1505 reg = MVNETA_PRXDQS_BUFFERSIZE(MVNETA_PACKET_SIZE >> 3); 1506 reg |= MVNETA_PRXDQS_DESCRIPTORSQUEUESIZE(MVNETA_RX_RING_CNT); 1507 MVNETA_WRITE(sc, MVNETA_PRXDQS(q), reg); 1508 #ifdef MVNETA_KTR 1509 CTR3(KTR_SPARE2, "%s PRXDQS(%d): %#x", ifp->if_xname, q, 1510 MVNETA_READ(sc, MVNETA_PRXDQS(q))); 1511 #endif 1512 /* Rx packet offset address */ 1513 reg = MVNETA_PRXC_PACKETOFFSET(MVNETA_PACKET_OFFSET >> 3); 1514 MVNETA_WRITE(sc, MVNETA_PRXC(q), reg); 1515 #ifdef MVNETA_KTR 1516 CTR3(KTR_SPARE2, "%s PRXC(%d): %#x", ifp->if_xname, q, 1517 MVNETA_READ(sc, MVNETA_PRXC(q))); 1518 #endif 1519 1520 /* if DMA is not working, register is not updated */ 1521 DASSERT(MVNETA_READ(sc, MVNETA_PRXDQA(q)) == rx->desc_pa); 1522 return (0); 1523 } 1524 1525 STATIC int 1526 mvneta_tx_queue_init(struct ifnet *ifp, int q) 1527 { 1528 struct mvneta_softc *sc; 1529 struct mvneta_tx_ring *tx; 1530 uint32_t reg; 1531 1532 sc = ifp->if_softc; 1533 KASSERT_TX_MTX(sc, q); 1534 tx = MVNETA_TX_RING(sc, q); 1535 DASSERT(tx->desc_pa != 0); 1536 1537 /* descriptor address */ 1538 MVNETA_WRITE(sc, MVNETA_PTXDQA(q), tx->desc_pa); 1539 1540 /* descriptor ring size */ 1541 reg = MVNETA_PTXDQS_DQS(MVNETA_TX_RING_CNT); 1542 MVNETA_WRITE(sc, MVNETA_PTXDQS(q), reg); 1543 1544 /* if DMA is not working, register is not updated */ 1545 DASSERT(MVNETA_READ(sc, MVNETA_PTXDQA(q)) == tx->desc_pa); 1546 return (0); 1547 } 1548 1549 STATIC int 1550 mvneta_rx_queue_enable(struct ifnet *ifp, int q) 1551 { 1552 struct mvneta_softc *sc; 1553 struct mvneta_rx_ring *rx; 1554 uint32_t reg; 1555 1556 sc = ifp->if_softc; 1557 rx = MVNETA_RX_RING(sc, q); 1558 KASSERT_RX_MTX(sc, q); 1559 1560 /* Set Rx interrupt threshold */ 1561 reg = MVNETA_PRXDQTH_ODT(rx->queue_th_received); 1562 MVNETA_WRITE(sc, MVNETA_PRXDQTH(q), reg); 1563 1564 reg = MVNETA_PRXITTH_RITT(rx->queue_th_time); 1565 MVNETA_WRITE(sc, MVNETA_PRXITTH(q), reg); 1566 1567 /* Unmask RXTX_TH Intr. */ 1568 reg = MVNETA_READ(sc, MVNETA_PRXTXTIM); 1569 reg |= MVNETA_PRXTXTI_RBICTAPQ(q); /* Rx Buffer Interrupt Coalese */ 1570 MVNETA_WRITE(sc, MVNETA_PRXTXTIM, reg); 1571 1572 /* Enable Rx queue */ 1573 reg = MVNETA_READ(sc, MVNETA_RQC) & MVNETA_RQC_EN_MASK; 1574 reg |= MVNETA_RQC_ENQ(q); 1575 MVNETA_WRITE(sc, MVNETA_RQC, reg); 1576 1577 rx->queue_status = MVNETA_QUEUE_WORKING; 1578 return (0); 1579 } 1580 1581 STATIC int 1582 mvneta_tx_queue_enable(struct ifnet *ifp, int q) 1583 { 1584 struct mvneta_softc *sc; 1585 struct mvneta_tx_ring *tx; 1586 1587 sc = ifp->if_softc; 1588 tx = MVNETA_TX_RING(sc, q); 1589 KASSERT_TX_MTX(sc, q); 1590 1591 /* Enable Tx queue */ 1592 MVNETA_WRITE(sc, MVNETA_TQC, MVNETA_TQC_ENQ(q)); 1593 1594 tx->queue_status = MVNETA_QUEUE_IDLE; 1595 tx->queue_hung = FALSE; 1596 return (0); 1597 } 1598 1599 STATIC __inline void 1600 mvneta_rx_lockq(struct mvneta_softc *sc, int q) 1601 { 1602 1603 DASSERT(q >= 0); 1604 DASSERT(q < MVNETA_RX_QNUM_MAX); 1605 mtx_lock(&sc->rx_ring[q].ring_mtx); 1606 } 1607 1608 STATIC __inline void 1609 mvneta_rx_unlockq(struct mvneta_softc *sc, int q) 1610 { 1611 1612 DASSERT(q >= 0); 1613 DASSERT(q < MVNETA_RX_QNUM_MAX); 1614 mtx_unlock(&sc->rx_ring[q].ring_mtx); 1615 } 1616 1617 STATIC __inline int __unused 1618 mvneta_tx_trylockq(struct mvneta_softc *sc, int q) 1619 { 1620 1621 DASSERT(q >= 0); 1622 DASSERT(q < MVNETA_TX_QNUM_MAX); 1623 return (mtx_trylock(&sc->tx_ring[q].ring_mtx)); 1624 } 1625 1626 STATIC __inline void 1627 mvneta_tx_lockq(struct mvneta_softc *sc, int q) 1628 { 1629 1630 DASSERT(q >= 0); 1631 DASSERT(q < MVNETA_TX_QNUM_MAX); 1632 mtx_lock(&sc->tx_ring[q].ring_mtx); 1633 } 1634 1635 STATIC __inline void 1636 mvneta_tx_unlockq(struct mvneta_softc *sc, int q) 1637 { 1638 1639 DASSERT(q >= 0); 1640 DASSERT(q < MVNETA_TX_QNUM_MAX); 1641 mtx_unlock(&sc->tx_ring[q].ring_mtx); 1642 } 1643 1644 /* 1645 * Interrupt Handlers 1646 */ 1647 STATIC void 1648 mvneta_disable_intr(struct mvneta_softc *sc) 1649 { 1650 1651 MVNETA_WRITE(sc, MVNETA_EUIM, 0); 1652 MVNETA_WRITE(sc, MVNETA_EUIC, 0); 1653 MVNETA_WRITE(sc, MVNETA_PRXTXTIM, 0); 1654 MVNETA_WRITE(sc, MVNETA_PRXTXTIC, 0); 1655 MVNETA_WRITE(sc, MVNETA_PRXTXIM, 0); 1656 MVNETA_WRITE(sc, MVNETA_PRXTXIC, 0); 1657 MVNETA_WRITE(sc, MVNETA_PMIM, 0); 1658 MVNETA_WRITE(sc, MVNETA_PMIC, 0); 1659 MVNETA_WRITE(sc, MVNETA_PIE, 0); 1660 } 1661 1662 STATIC void 1663 mvneta_enable_intr(struct mvneta_softc *sc) 1664 { 1665 uint32_t reg; 1666 1667 /* Enable Summary Bit to check all interrupt cause. */ 1668 reg = MVNETA_READ(sc, MVNETA_PRXTXTIM); 1669 reg |= MVNETA_PRXTXTI_PMISCICSUMMARY; 1670 MVNETA_WRITE(sc, MVNETA_PRXTXTIM, reg); 1671 1672 if (sc->use_inband_status) { 1673 /* Enable Port MISC Intr. (via RXTX_TH_Summary bit) */ 1674 MVNETA_WRITE(sc, MVNETA_PMIM, MVNETA_PMI_PHYSTATUSCHNG | 1675 MVNETA_PMI_LINKCHANGE | MVNETA_PMI_PSCSYNCCHANGE); 1676 } 1677 1678 /* Enable All Queue Interrupt */ 1679 reg = MVNETA_READ(sc, MVNETA_PIE); 1680 reg |= MVNETA_PIE_RXPKTINTRPTENB_MASK; 1681 reg |= MVNETA_PIE_TXPKTINTRPTENB_MASK; 1682 MVNETA_WRITE(sc, MVNETA_PIE, reg); 1683 } 1684 1685 STATIC void 1686 mvneta_rxtxth_intr(void *arg) 1687 { 1688 struct mvneta_softc *sc; 1689 struct ifnet *ifp; 1690 uint32_t ic, queues; 1691 1692 sc = arg; 1693 ifp = sc->ifp; 1694 #ifdef MVNETA_KTR 1695 CTR1(KTR_SPARE2, "%s got RXTX_TH_Intr", ifp->if_xname); 1696 #endif 1697 ic = MVNETA_READ(sc, MVNETA_PRXTXTIC); 1698 if (ic == 0) 1699 return; 1700 MVNETA_WRITE(sc, MVNETA_PRXTXTIC, ~ic); 1701 1702 /* Ack maintance interrupt first */ 1703 if (__predict_false((ic & MVNETA_PRXTXTI_PMISCICSUMMARY) && 1704 sc->use_inband_status)) { 1705 mvneta_sc_lock(sc); 1706 mvneta_misc_intr(sc); 1707 mvneta_sc_unlock(sc); 1708 } 1709 if (__predict_false(!(ifp->if_drv_flags & IFF_DRV_RUNNING))) 1710 return; 1711 /* RxTxTH interrupt */ 1712 queues = MVNETA_PRXTXTI_GET_RBICTAPQ(ic); 1713 if (__predict_true(queues)) { 1714 #ifdef MVNETA_KTR 1715 CTR1(KTR_SPARE2, "%s got PRXTXTIC: +RXEOF", ifp->if_xname); 1716 #endif 1717 /* At the moment the driver support only one RX queue. */ 1718 DASSERT(MVNETA_IS_QUEUE_SET(queues, 0)); 1719 mvneta_rx(sc, 0, 0); 1720 } 1721 } 1722 1723 STATIC int 1724 mvneta_misc_intr(struct mvneta_softc *sc) 1725 { 1726 uint32_t ic; 1727 int claimed = 0; 1728 1729 #ifdef MVNETA_KTR 1730 CTR1(KTR_SPARE2, "%s got MISC_INTR", sc->ifp->if_xname); 1731 #endif 1732 KASSERT_SC_MTX(sc); 1733 1734 for (;;) { 1735 ic = MVNETA_READ(sc, MVNETA_PMIC); 1736 ic &= MVNETA_READ(sc, MVNETA_PMIM); 1737 if (ic == 0) 1738 break; 1739 MVNETA_WRITE(sc, MVNETA_PMIC, ~ic); 1740 claimed = 1; 1741 1742 if (ic & (MVNETA_PMI_PHYSTATUSCHNG | 1743 MVNETA_PMI_LINKCHANGE | MVNETA_PMI_PSCSYNCCHANGE)) 1744 mvneta_link_isr(sc); 1745 } 1746 return (claimed); 1747 } 1748 1749 STATIC void 1750 mvneta_tick(void *arg) 1751 { 1752 struct mvneta_softc *sc; 1753 struct mvneta_tx_ring *tx; 1754 struct mvneta_rx_ring *rx; 1755 int q; 1756 uint32_t fc_prev, fc_curr; 1757 1758 sc = arg; 1759 1760 /* 1761 * This is done before mib update to get the right stats 1762 * for this tick. 1763 */ 1764 mvneta_tx_drain(sc); 1765 1766 /* Extract previous flow-control frame received counter. */ 1767 fc_prev = sc->sysctl_mib[MVNETA_MIB_FC_GOOD_IDX].counter; 1768 /* Read mib registers (clear by read). */ 1769 mvneta_update_mib(sc); 1770 /* Extract current flow-control frame received counter. */ 1771 fc_curr = sc->sysctl_mib[MVNETA_MIB_FC_GOOD_IDX].counter; 1772 1773 1774 if (sc->phy_attached && sc->ifp->if_flags & IFF_UP) { 1775 mvneta_sc_lock(sc); 1776 mii_tick(sc->mii); 1777 1778 /* Adjust MAC settings */ 1779 mvneta_adjust_link(sc); 1780 mvneta_sc_unlock(sc); 1781 } 1782 1783 /* 1784 * We were unable to refill the rx queue and left the rx func, leaving 1785 * the ring without mbuf and no way to call the refill func. 1786 */ 1787 for (q = 0; q < MVNETA_RX_QNUM_MAX; q++) { 1788 rx = MVNETA_RX_RING(sc, q); 1789 if (rx->needs_refill == TRUE) { 1790 mvneta_rx_lockq(sc, q); 1791 mvneta_rx_queue_refill(sc, q); 1792 mvneta_rx_unlockq(sc, q); 1793 } 1794 } 1795 1796 /* 1797 * Watchdog: 1798 * - check if queue is mark as hung. 1799 * - ignore hung status if we received some pause frame 1800 * as hardware may have paused packet transmit. 1801 */ 1802 for (q = 0; q < MVNETA_TX_QNUM_MAX; q++) { 1803 /* 1804 * We should take queue lock, but as we only read 1805 * queue status we can do it without lock, we may 1806 * only missdetect queue status for one tick. 1807 */ 1808 tx = MVNETA_TX_RING(sc, q); 1809 1810 if (tx->queue_hung && (fc_curr - fc_prev) == 0) 1811 goto timeout; 1812 } 1813 1814 callout_schedule(&sc->tick_ch, hz); 1815 return; 1816 1817 timeout: 1818 if_printf(sc->ifp, "watchdog timeout\n"); 1819 1820 mvneta_sc_lock(sc); 1821 sc->counter_watchdog++; 1822 sc->counter_watchdog_mib++; 1823 /* Trigger reinitialize sequence. */ 1824 mvneta_stop_locked(sc); 1825 mvneta_init_locked(sc); 1826 mvneta_sc_unlock(sc); 1827 } 1828 1829 STATIC void 1830 mvneta_qflush(struct ifnet *ifp) 1831 { 1832 #ifdef MVNETA_MULTIQUEUE 1833 struct mvneta_softc *sc; 1834 struct mvneta_tx_ring *tx; 1835 struct mbuf *m; 1836 size_t q; 1837 1838 sc = ifp->if_softc; 1839 1840 for (q = 0; q < MVNETA_TX_QNUM_MAX; q++) { 1841 tx = MVNETA_TX_RING(sc, q); 1842 mvneta_tx_lockq(sc, q); 1843 while ((m = buf_ring_dequeue_sc(tx->br)) != NULL) 1844 m_freem(m); 1845 mvneta_tx_unlockq(sc, q); 1846 } 1847 #endif 1848 if_qflush(ifp); 1849 } 1850 1851 STATIC void 1852 mvneta_tx_task(void *arg, int pending) 1853 { 1854 struct mvneta_softc *sc; 1855 struct mvneta_tx_ring *tx; 1856 struct ifnet *ifp; 1857 int error; 1858 1859 tx = arg; 1860 ifp = tx->ifp; 1861 sc = ifp->if_softc; 1862 1863 mvneta_tx_lockq(sc, tx->qidx); 1864 error = mvneta_xmit_locked(sc, tx->qidx); 1865 mvneta_tx_unlockq(sc, tx->qidx); 1866 1867 /* Try again */ 1868 if (__predict_false(error != 0 && error != ENETDOWN)) { 1869 pause("mvneta_tx_task_sleep", 1); 1870 taskqueue_enqueue(tx->taskq, &tx->task); 1871 } 1872 } 1873 1874 STATIC int 1875 mvneta_xmitfast_locked(struct mvneta_softc *sc, int q, struct mbuf **m) 1876 { 1877 struct mvneta_tx_ring *tx; 1878 struct ifnet *ifp; 1879 int error; 1880 1881 KASSERT_TX_MTX(sc, q); 1882 tx = MVNETA_TX_RING(sc, q); 1883 error = 0; 1884 1885 ifp = sc->ifp; 1886 1887 /* Dont enqueue packet if the queue is disabled. */ 1888 if (__predict_false(tx->queue_status == MVNETA_QUEUE_DISABLED)) { 1889 m_freem(*m); 1890 *m = NULL; 1891 return (ENETDOWN); 1892 } 1893 1894 /* Reclaim mbuf if above threshold. */ 1895 if (__predict_true(tx->used > MVNETA_TX_RECLAIM_COUNT)) 1896 mvneta_tx_queue_complete(sc, q); 1897 1898 /* Do not call transmit path if queue is already too full. */ 1899 if (__predict_false(tx->used > 1900 MVNETA_TX_RING_CNT - MVNETA_TX_SEGLIMIT)) 1901 return (ENOBUFS); 1902 1903 error = mvneta_tx_queue(sc, m, q); 1904 if (__predict_false(error != 0)) 1905 return (error); 1906 1907 /* Send a copy of the frame to the BPF listener */ 1908 ETHER_BPF_MTAP(ifp, *m); 1909 1910 /* Set watchdog on */ 1911 tx->watchdog_time = ticks; 1912 tx->queue_status = MVNETA_QUEUE_WORKING; 1913 1914 return (error); 1915 } 1916 1917 #ifdef MVNETA_MULTIQUEUE 1918 STATIC int 1919 mvneta_transmit(struct ifnet *ifp, struct mbuf *m) 1920 { 1921 struct mvneta_softc *sc; 1922 struct mvneta_tx_ring *tx; 1923 int error; 1924 int q; 1925 1926 sc = ifp->if_softc; 1927 1928 /* Use default queue if there is no flow id as thread can migrate. */ 1929 if (__predict_true(M_HASHTYPE_GET(m) != M_HASHTYPE_NONE)) 1930 q = m->m_pkthdr.flowid % MVNETA_TX_QNUM_MAX; 1931 else 1932 q = 0; 1933 1934 tx = MVNETA_TX_RING(sc, q); 1935 1936 /* If buf_ring is full start transmit immediatly. */ 1937 if (buf_ring_full(tx->br)) { 1938 mvneta_tx_lockq(sc, q); 1939 mvneta_xmit_locked(sc, q); 1940 mvneta_tx_unlockq(sc, q); 1941 } 1942 1943 /* 1944 * If the buf_ring is empty we will not reorder packets. 1945 * If the lock is available transmit without using buf_ring. 1946 */ 1947 if (buf_ring_empty(tx->br) && mvneta_tx_trylockq(sc, q) != 0) { 1948 error = mvneta_xmitfast_locked(sc, q, &m); 1949 mvneta_tx_unlockq(sc, q); 1950 if (__predict_true(error == 0)) 1951 return (0); 1952 1953 /* Transmit can fail in fastpath. */ 1954 if (__predict_false(m == NULL)) 1955 return (error); 1956 } 1957 1958 /* Enqueue then schedule taskqueue. */ 1959 error = drbr_enqueue(ifp, tx->br, m); 1960 if (__predict_false(error != 0)) 1961 return (error); 1962 1963 taskqueue_enqueue(tx->taskq, &tx->task); 1964 return (0); 1965 } 1966 1967 STATIC int 1968 mvneta_xmit_locked(struct mvneta_softc *sc, int q) 1969 { 1970 struct ifnet *ifp; 1971 struct mvneta_tx_ring *tx; 1972 struct mbuf *m; 1973 int error; 1974 1975 KASSERT_TX_MTX(sc, q); 1976 ifp = sc->ifp; 1977 tx = MVNETA_TX_RING(sc, q); 1978 error = 0; 1979 1980 while ((m = drbr_peek(ifp, tx->br)) != NULL) { 1981 error = mvneta_xmitfast_locked(sc, q, &m); 1982 if (__predict_false(error != 0)) { 1983 if (m != NULL) 1984 drbr_putback(ifp, tx->br, m); 1985 else 1986 drbr_advance(ifp, tx->br); 1987 break; 1988 } 1989 drbr_advance(ifp, tx->br); 1990 } 1991 1992 return (error); 1993 } 1994 #else /* !MVNETA_MULTIQUEUE */ 1995 STATIC void 1996 mvneta_start(struct ifnet *ifp) 1997 { 1998 struct mvneta_softc *sc; 1999 struct mvneta_tx_ring *tx; 2000 int error; 2001 2002 sc = ifp->if_softc; 2003 tx = MVNETA_TX_RING(sc, 0); 2004 2005 mvneta_tx_lockq(sc, 0); 2006 error = mvneta_xmit_locked(sc, 0); 2007 mvneta_tx_unlockq(sc, 0); 2008 /* Handle retransmit in the background taskq. */ 2009 if (__predict_false(error != 0 && error != ENETDOWN)) 2010 taskqueue_enqueue(tx->taskq, &tx->task); 2011 } 2012 2013 STATIC int 2014 mvneta_xmit_locked(struct mvneta_softc *sc, int q) 2015 { 2016 struct ifnet *ifp; 2017 struct mvneta_tx_ring *tx; 2018 struct mbuf *m; 2019 int error; 2020 2021 KASSERT_TX_MTX(sc, q); 2022 ifp = sc->ifp; 2023 tx = MVNETA_TX_RING(sc, 0); 2024 error = 0; 2025 2026 while (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 2027 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 2028 if (m == NULL) 2029 break; 2030 2031 error = mvneta_xmitfast_locked(sc, q, &m); 2032 if (__predict_false(error != 0)) { 2033 if (m != NULL) 2034 IFQ_DRV_PREPEND(&ifp->if_snd, m); 2035 break; 2036 } 2037 } 2038 2039 return (error); 2040 } 2041 #endif 2042 2043 STATIC int 2044 mvneta_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 2045 { 2046 struct mvneta_softc *sc; 2047 struct mvneta_rx_ring *rx; 2048 struct ifreq *ifr; 2049 int error, mask; 2050 uint32_t flags; 2051 int q; 2052 2053 error = 0; 2054 sc = ifp->if_softc; 2055 ifr = (struct ifreq *)data; 2056 switch (cmd) { 2057 case SIOCSIFFLAGS: 2058 mvneta_sc_lock(sc); 2059 if (ifp->if_flags & IFF_UP) { 2060 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 2061 flags = ifp->if_flags ^ sc->mvneta_if_flags; 2062 2063 if (flags != 0) 2064 sc->mvneta_if_flags = ifp->if_flags; 2065 2066 if ((flags & IFF_PROMISC) != 0) 2067 mvneta_filter_setup(sc); 2068 } else { 2069 mvneta_init_locked(sc); 2070 sc->mvneta_if_flags = ifp->if_flags; 2071 if (sc->phy_attached) 2072 mii_mediachg(sc->mii); 2073 mvneta_sc_unlock(sc); 2074 break; 2075 } 2076 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2077 mvneta_stop_locked(sc); 2078 2079 sc->mvneta_if_flags = ifp->if_flags; 2080 mvneta_sc_unlock(sc); 2081 break; 2082 case SIOCSIFCAP: 2083 if (ifp->if_mtu > MVNETA_MAX_CSUM_MTU && 2084 ifr->ifr_reqcap & IFCAP_TXCSUM) 2085 ifr->ifr_reqcap &= ~IFCAP_TXCSUM; 2086 mask = ifp->if_capenable ^ ifr->ifr_reqcap; 2087 if (mask & IFCAP_HWCSUM) { 2088 ifp->if_capenable &= ~IFCAP_HWCSUM; 2089 ifp->if_capenable |= IFCAP_HWCSUM & ifr->ifr_reqcap; 2090 if (ifp->if_capenable & IFCAP_TXCSUM) 2091 ifp->if_hwassist = CSUM_IP | CSUM_TCP | 2092 CSUM_UDP; 2093 else 2094 ifp->if_hwassist = 0; 2095 } 2096 if (mask & IFCAP_LRO) { 2097 mvneta_sc_lock(sc); 2098 ifp->if_capenable ^= IFCAP_LRO; 2099 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2100 for (q = 0; q < MVNETA_RX_QNUM_MAX; q++) { 2101 rx = MVNETA_RX_RING(sc, q); 2102 rx->lro_enabled = !rx->lro_enabled; 2103 } 2104 } 2105 mvneta_sc_unlock(sc); 2106 } 2107 VLAN_CAPABILITIES(ifp); 2108 break; 2109 case SIOCSIFMEDIA: 2110 if ((IFM_SUBTYPE(ifr->ifr_media) == IFM_1000_T || 2111 IFM_SUBTYPE(ifr->ifr_media) == IFM_2500_T) && 2112 (ifr->ifr_media & IFM_FDX) == 0) { 2113 device_printf(sc->dev, 2114 "%s half-duplex unsupported\n", 2115 IFM_SUBTYPE(ifr->ifr_media) == IFM_1000_T ? 2116 "1000Base-T" : 2117 "2500Base-T"); 2118 error = EINVAL; 2119 break; 2120 } 2121 case SIOCGIFMEDIA: /* FALLTHROUGH */ 2122 case SIOCGIFXMEDIA: 2123 if (!sc->phy_attached) 2124 error = ifmedia_ioctl(ifp, ifr, &sc->mvneta_ifmedia, 2125 cmd); 2126 else 2127 error = ifmedia_ioctl(ifp, ifr, &sc->mii->mii_media, 2128 cmd); 2129 break; 2130 case SIOCSIFMTU: 2131 if (ifr->ifr_mtu < 68 || ifr->ifr_mtu > MVNETA_MAX_FRAME - 2132 MVNETA_ETHER_SIZE) { 2133 error = EINVAL; 2134 } else { 2135 ifp->if_mtu = ifr->ifr_mtu; 2136 mvneta_sc_lock(sc); 2137 if (ifp->if_mtu > MVNETA_MAX_CSUM_MTU) { 2138 ifp->if_capenable &= ~IFCAP_TXCSUM; 2139 ifp->if_hwassist = 0; 2140 } else { 2141 ifp->if_capenable |= IFCAP_TXCSUM; 2142 ifp->if_hwassist = CSUM_IP | CSUM_TCP | 2143 CSUM_UDP; 2144 } 2145 2146 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 2147 /* Trigger reinitialize sequence */ 2148 mvneta_stop_locked(sc); 2149 mvneta_init_locked(sc); 2150 } 2151 mvneta_sc_unlock(sc); 2152 } 2153 break; 2154 2155 default: 2156 error = ether_ioctl(ifp, cmd, data); 2157 break; 2158 } 2159 2160 return (error); 2161 } 2162 2163 STATIC void 2164 mvneta_init_locked(void *arg) 2165 { 2166 struct mvneta_softc *sc; 2167 struct ifnet *ifp; 2168 uint32_t reg; 2169 int q, cpu; 2170 2171 sc = arg; 2172 ifp = sc->ifp; 2173 2174 if (!device_is_attached(sc->dev) || 2175 (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2176 return; 2177 2178 mvneta_disable_intr(sc); 2179 callout_stop(&sc->tick_ch); 2180 2181 /* Get the latest mac address */ 2182 bcopy(IF_LLADDR(ifp), sc->enaddr, ETHER_ADDR_LEN); 2183 mvneta_set_mac_address(sc, sc->enaddr); 2184 mvneta_filter_setup(sc); 2185 2186 /* Start DMA Engine */ 2187 MVNETA_WRITE(sc, MVNETA_PRXINIT, 0x00000000); 2188 MVNETA_WRITE(sc, MVNETA_PTXINIT, 0x00000000); 2189 MVNETA_WRITE(sc, MVNETA_PACC, MVNETA_PACC_ACCELERATIONMODE_EDM); 2190 2191 /* Enable port */ 2192 reg = MVNETA_READ(sc, MVNETA_PMACC0); 2193 reg |= MVNETA_PMACC0_PORTEN; 2194 MVNETA_WRITE(sc, MVNETA_PMACC0, reg); 2195 2196 /* Allow access to each TXQ/RXQ from both CPU's */ 2197 for (cpu = 0; cpu < mp_ncpus; ++cpu) 2198 MVNETA_WRITE(sc, MVNETA_PCP2Q(cpu), 2199 MVNETA_PCP2Q_TXQEN_MASK | MVNETA_PCP2Q_RXQEN_MASK); 2200 2201 for (q = 0; q < MVNETA_RX_QNUM_MAX; q++) { 2202 mvneta_rx_lockq(sc, q); 2203 mvneta_rx_queue_refill(sc, q); 2204 mvneta_rx_unlockq(sc, q); 2205 } 2206 2207 if (!sc->phy_attached) 2208 mvneta_linkup(sc); 2209 2210 /* Enable interrupt */ 2211 mvneta_enable_intr(sc); 2212 2213 /* Set Counter */ 2214 callout_schedule(&sc->tick_ch, hz); 2215 2216 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2217 } 2218 2219 STATIC void 2220 mvneta_init(void *arg) 2221 { 2222 struct mvneta_softc *sc; 2223 2224 sc = arg; 2225 mvneta_sc_lock(sc); 2226 mvneta_init_locked(sc); 2227 if (sc->phy_attached) 2228 mii_mediachg(sc->mii); 2229 mvneta_sc_unlock(sc); 2230 } 2231 2232 /* ARGSUSED */ 2233 STATIC void 2234 mvneta_stop_locked(struct mvneta_softc *sc) 2235 { 2236 struct ifnet *ifp; 2237 struct mvneta_rx_ring *rx; 2238 struct mvneta_tx_ring *tx; 2239 uint32_t reg; 2240 int q; 2241 2242 ifp = sc->ifp; 2243 if (ifp == NULL || (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 2244 return; 2245 2246 mvneta_disable_intr(sc); 2247 2248 callout_stop(&sc->tick_ch); 2249 2250 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2251 2252 /* Link down */ 2253 if (sc->linkup == TRUE) 2254 mvneta_linkdown(sc); 2255 2256 /* Reset the MAC Port Enable bit */ 2257 reg = MVNETA_READ(sc, MVNETA_PMACC0); 2258 reg &= ~MVNETA_PMACC0_PORTEN; 2259 MVNETA_WRITE(sc, MVNETA_PMACC0, reg); 2260 2261 /* Disable each of queue */ 2262 for (q = 0; q < MVNETA_RX_QNUM_MAX; q++) { 2263 rx = MVNETA_RX_RING(sc, q); 2264 2265 mvneta_rx_lockq(sc, q); 2266 mvneta_ring_flush_rx_queue(sc, q); 2267 mvneta_rx_unlockq(sc, q); 2268 } 2269 2270 /* 2271 * Hold Reset state of DMA Engine 2272 * (must write 0x0 to restart it) 2273 */ 2274 MVNETA_WRITE(sc, MVNETA_PRXINIT, 0x00000001); 2275 MVNETA_WRITE(sc, MVNETA_PTXINIT, 0x00000001); 2276 2277 for (q = 0; q < MVNETA_TX_QNUM_MAX; q++) { 2278 tx = MVNETA_TX_RING(sc, q); 2279 2280 mvneta_tx_lockq(sc, q); 2281 mvneta_ring_flush_tx_queue(sc, q); 2282 mvneta_tx_unlockq(sc, q); 2283 } 2284 } 2285 2286 STATIC void 2287 mvneta_stop(struct mvneta_softc *sc) 2288 { 2289 2290 mvneta_sc_lock(sc); 2291 mvneta_stop_locked(sc); 2292 mvneta_sc_unlock(sc); 2293 } 2294 2295 STATIC int 2296 mvneta_mediachange(struct ifnet *ifp) 2297 { 2298 struct mvneta_softc *sc; 2299 2300 sc = ifp->if_softc; 2301 2302 if (!sc->phy_attached && !sc->use_inband_status) { 2303 /* We shouldn't be here */ 2304 if_printf(ifp, "Cannot change media in fixed-link mode!\n"); 2305 return (0); 2306 } 2307 2308 if (sc->use_inband_status) { 2309 mvneta_update_media(sc, sc->mvneta_ifmedia.ifm_media); 2310 return (0); 2311 } 2312 2313 mvneta_sc_lock(sc); 2314 2315 /* Update PHY */ 2316 mii_mediachg(sc->mii); 2317 2318 mvneta_sc_unlock(sc); 2319 2320 return (0); 2321 } 2322 2323 STATIC void 2324 mvneta_get_media(struct mvneta_softc *sc, struct ifmediareq *ifmr) 2325 { 2326 uint32_t psr; 2327 2328 psr = MVNETA_READ(sc, MVNETA_PSR); 2329 2330 /* Speed */ 2331 if (psr & MVNETA_PSR_GMIISPEED) 2332 ifmr->ifm_active = IFM_ETHER_SUBTYPE_SET(IFM_1000_T); 2333 else if (psr & MVNETA_PSR_MIISPEED) 2334 ifmr->ifm_active = IFM_ETHER_SUBTYPE_SET(IFM_100_TX); 2335 else if (psr & MVNETA_PSR_LINKUP) 2336 ifmr->ifm_active = IFM_ETHER_SUBTYPE_SET(IFM_10_T); 2337 2338 /* Duplex */ 2339 if (psr & MVNETA_PSR_FULLDX) 2340 ifmr->ifm_active |= IFM_FDX; 2341 2342 /* Link */ 2343 ifmr->ifm_status = IFM_AVALID; 2344 if (psr & MVNETA_PSR_LINKUP) 2345 ifmr->ifm_status |= IFM_ACTIVE; 2346 } 2347 2348 STATIC void 2349 mvneta_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 2350 { 2351 struct mvneta_softc *sc; 2352 struct mii_data *mii; 2353 2354 sc = ifp->if_softc; 2355 2356 if (!sc->phy_attached && !sc->use_inband_status) { 2357 ifmr->ifm_status = IFM_AVALID | IFM_ACTIVE; 2358 return; 2359 } 2360 2361 mvneta_sc_lock(sc); 2362 2363 if (sc->use_inband_status) { 2364 mvneta_get_media(sc, ifmr); 2365 mvneta_sc_unlock(sc); 2366 return; 2367 } 2368 2369 mii = sc->mii; 2370 mii_pollstat(mii); 2371 2372 ifmr->ifm_active = mii->mii_media_active; 2373 ifmr->ifm_status = mii->mii_media_status; 2374 2375 mvneta_sc_unlock(sc); 2376 } 2377 2378 /* 2379 * Link State Notify 2380 */ 2381 STATIC void 2382 mvneta_update_autoneg(struct mvneta_softc *sc, int enable) 2383 { 2384 int reg; 2385 2386 if (enable) { 2387 reg = MVNETA_READ(sc, MVNETA_PANC); 2388 reg &= ~(MVNETA_PANC_FORCELINKFAIL | MVNETA_PANC_FORCELINKPASS | 2389 MVNETA_PANC_ANFCEN); 2390 reg |= MVNETA_PANC_ANDUPLEXEN | MVNETA_PANC_ANSPEEDEN | 2391 MVNETA_PANC_INBANDANEN; 2392 MVNETA_WRITE(sc, MVNETA_PANC, reg); 2393 2394 reg = MVNETA_READ(sc, MVNETA_PMACC2); 2395 reg |= MVNETA_PMACC2_INBANDANMODE; 2396 MVNETA_WRITE(sc, MVNETA_PMACC2, reg); 2397 2398 reg = MVNETA_READ(sc, MVNETA_PSOMSCD); 2399 reg |= MVNETA_PSOMSCD_ENABLE; 2400 MVNETA_WRITE(sc, MVNETA_PSOMSCD, reg); 2401 } else { 2402 reg = MVNETA_READ(sc, MVNETA_PANC); 2403 reg &= ~(MVNETA_PANC_FORCELINKFAIL | MVNETA_PANC_FORCELINKPASS | 2404 MVNETA_PANC_ANDUPLEXEN | MVNETA_PANC_ANSPEEDEN | 2405 MVNETA_PANC_INBANDANEN); 2406 MVNETA_WRITE(sc, MVNETA_PANC, reg); 2407 2408 reg = MVNETA_READ(sc, MVNETA_PMACC2); 2409 reg &= ~MVNETA_PMACC2_INBANDANMODE; 2410 MVNETA_WRITE(sc, MVNETA_PMACC2, reg); 2411 2412 reg = MVNETA_READ(sc, MVNETA_PSOMSCD); 2413 reg &= ~MVNETA_PSOMSCD_ENABLE; 2414 MVNETA_WRITE(sc, MVNETA_PSOMSCD, reg); 2415 } 2416 } 2417 2418 STATIC int 2419 mvneta_update_media(struct mvneta_softc *sc, int media) 2420 { 2421 int reg, err; 2422 boolean_t running; 2423 2424 err = 0; 2425 2426 mvneta_sc_lock(sc); 2427 2428 mvneta_linkreset(sc); 2429 2430 running = (sc->ifp->if_drv_flags & IFF_DRV_RUNNING) != 0; 2431 if (running) 2432 mvneta_stop_locked(sc); 2433 2434 sc->autoneg = (IFM_SUBTYPE(media) == IFM_AUTO); 2435 2436 if (sc->use_inband_status) 2437 mvneta_update_autoneg(sc, IFM_SUBTYPE(media) == IFM_AUTO); 2438 2439 mvneta_update_eee(sc); 2440 mvneta_update_fc(sc); 2441 2442 if (IFM_SUBTYPE(media) != IFM_AUTO) { 2443 reg = MVNETA_READ(sc, MVNETA_PANC); 2444 reg &= ~(MVNETA_PANC_SETGMIISPEED | 2445 MVNETA_PANC_SETMIISPEED | 2446 MVNETA_PANC_SETFULLDX); 2447 if (IFM_SUBTYPE(media) == IFM_1000_T || 2448 IFM_SUBTYPE(media) == IFM_2500_T) { 2449 if ((media & IFM_FDX) == 0) { 2450 device_printf(sc->dev, 2451 "%s half-duplex unsupported\n", 2452 IFM_SUBTYPE(media) == IFM_1000_T ? 2453 "1000Base-T" : 2454 "2500Base-T"); 2455 err = EINVAL; 2456 goto out; 2457 } 2458 reg |= MVNETA_PANC_SETGMIISPEED; 2459 } else if (IFM_SUBTYPE(media) == IFM_100_TX) 2460 reg |= MVNETA_PANC_SETMIISPEED; 2461 2462 if (media & IFM_FDX) 2463 reg |= MVNETA_PANC_SETFULLDX; 2464 2465 MVNETA_WRITE(sc, MVNETA_PANC, reg); 2466 } 2467 out: 2468 if (running) 2469 mvneta_init_locked(sc); 2470 mvneta_sc_unlock(sc); 2471 return (err); 2472 } 2473 2474 STATIC void 2475 mvneta_adjust_link(struct mvneta_softc *sc) 2476 { 2477 boolean_t phy_linkup; 2478 int reg; 2479 2480 /* Update eee/fc */ 2481 mvneta_update_eee(sc); 2482 mvneta_update_fc(sc); 2483 2484 /* Check for link change */ 2485 phy_linkup = (sc->mii->mii_media_status & 2486 (IFM_AVALID | IFM_ACTIVE)) == (IFM_AVALID | IFM_ACTIVE); 2487 2488 if (sc->linkup != phy_linkup) 2489 mvneta_linkupdate(sc, phy_linkup); 2490 2491 /* Don't update media on disabled link */ 2492 if (!phy_linkup) 2493 return; 2494 2495 /* Check for media type change */ 2496 if (sc->mvneta_media != sc->mii->mii_media_active) { 2497 sc->mvneta_media = sc->mii->mii_media_active; 2498 2499 reg = MVNETA_READ(sc, MVNETA_PANC); 2500 reg &= ~(MVNETA_PANC_SETGMIISPEED | 2501 MVNETA_PANC_SETMIISPEED | 2502 MVNETA_PANC_SETFULLDX); 2503 if (IFM_SUBTYPE(sc->mvneta_media) == IFM_1000_T || 2504 IFM_SUBTYPE(sc->mvneta_media) == IFM_2500_T) { 2505 reg |= MVNETA_PANC_SETGMIISPEED; 2506 } else if (IFM_SUBTYPE(sc->mvneta_media) == IFM_100_TX) 2507 reg |= MVNETA_PANC_SETMIISPEED; 2508 2509 if (sc->mvneta_media & IFM_FDX) 2510 reg |= MVNETA_PANC_SETFULLDX; 2511 2512 MVNETA_WRITE(sc, MVNETA_PANC, reg); 2513 } 2514 } 2515 2516 STATIC void 2517 mvneta_link_isr(struct mvneta_softc *sc) 2518 { 2519 int linkup; 2520 2521 KASSERT_SC_MTX(sc); 2522 2523 linkup = MVNETA_IS_LINKUP(sc) ? TRUE : FALSE; 2524 if (sc->linkup == linkup) 2525 return; 2526 2527 if (linkup == TRUE) 2528 mvneta_linkup(sc); 2529 else 2530 mvneta_linkdown(sc); 2531 2532 #ifdef DEBUG 2533 log(LOG_DEBUG, 2534 "%s: link %s\n", device_xname(sc->dev), linkup ? "up" : "down"); 2535 #endif 2536 } 2537 2538 STATIC void 2539 mvneta_linkupdate(struct mvneta_softc *sc, boolean_t linkup) 2540 { 2541 2542 KASSERT_SC_MTX(sc); 2543 2544 if (linkup == TRUE) 2545 mvneta_linkup(sc); 2546 else 2547 mvneta_linkdown(sc); 2548 2549 #ifdef DEBUG 2550 log(LOG_DEBUG, 2551 "%s: link %s\n", device_xname(sc->dev), linkup ? "up" : "down"); 2552 #endif 2553 } 2554 2555 STATIC void 2556 mvneta_update_eee(struct mvneta_softc *sc) 2557 { 2558 uint32_t reg; 2559 2560 KASSERT_SC_MTX(sc); 2561 2562 /* set EEE parameters */ 2563 reg = MVNETA_READ(sc, MVNETA_LPIC1); 2564 if (sc->cf_lpi) 2565 reg |= MVNETA_LPIC1_LPIRE; 2566 else 2567 reg &= ~MVNETA_LPIC1_LPIRE; 2568 MVNETA_WRITE(sc, MVNETA_LPIC1, reg); 2569 } 2570 2571 STATIC void 2572 mvneta_update_fc(struct mvneta_softc *sc) 2573 { 2574 uint32_t reg; 2575 2576 KASSERT_SC_MTX(sc); 2577 2578 reg = MVNETA_READ(sc, MVNETA_PANC); 2579 if (sc->cf_fc) { 2580 /* Flow control negotiation */ 2581 reg |= MVNETA_PANC_PAUSEADV; 2582 reg |= MVNETA_PANC_ANFCEN; 2583 } else { 2584 /* Disable flow control negotiation */ 2585 reg &= ~MVNETA_PANC_PAUSEADV; 2586 reg &= ~MVNETA_PANC_ANFCEN; 2587 } 2588 2589 MVNETA_WRITE(sc, MVNETA_PANC, reg); 2590 } 2591 2592 STATIC void 2593 mvneta_linkup(struct mvneta_softc *sc) 2594 { 2595 uint32_t reg; 2596 2597 KASSERT_SC_MTX(sc); 2598 2599 if (!sc->use_inband_status) { 2600 reg = MVNETA_READ(sc, MVNETA_PANC); 2601 reg |= MVNETA_PANC_FORCELINKPASS; 2602 reg &= ~MVNETA_PANC_FORCELINKFAIL; 2603 MVNETA_WRITE(sc, MVNETA_PANC, reg); 2604 } 2605 2606 mvneta_qflush(sc->ifp); 2607 mvneta_portup(sc); 2608 sc->linkup = TRUE; 2609 if_link_state_change(sc->ifp, LINK_STATE_UP); 2610 } 2611 2612 STATIC void 2613 mvneta_linkdown(struct mvneta_softc *sc) 2614 { 2615 uint32_t reg; 2616 2617 KASSERT_SC_MTX(sc); 2618 2619 if (!sc->use_inband_status) { 2620 reg = MVNETA_READ(sc, MVNETA_PANC); 2621 reg &= ~MVNETA_PANC_FORCELINKPASS; 2622 reg |= MVNETA_PANC_FORCELINKFAIL; 2623 MVNETA_WRITE(sc, MVNETA_PANC, reg); 2624 } 2625 2626 mvneta_portdown(sc); 2627 mvneta_qflush(sc->ifp); 2628 sc->linkup = FALSE; 2629 if_link_state_change(sc->ifp, LINK_STATE_DOWN); 2630 } 2631 2632 STATIC void 2633 mvneta_linkreset(struct mvneta_softc *sc) 2634 { 2635 struct mii_softc *mii; 2636 2637 if (sc->phy_attached) { 2638 /* Force reset PHY */ 2639 mii = LIST_FIRST(&sc->mii->mii_phys); 2640 if (mii) 2641 mii_phy_reset(mii); 2642 } 2643 } 2644 2645 /* 2646 * Tx Subroutines 2647 */ 2648 STATIC int 2649 mvneta_tx_queue(struct mvneta_softc *sc, struct mbuf **mbufp, int q) 2650 { 2651 struct ifnet *ifp; 2652 bus_dma_segment_t txsegs[MVNETA_TX_SEGLIMIT]; 2653 struct mbuf *mtmp, *mbuf; 2654 struct mvneta_tx_ring *tx; 2655 struct mvneta_buf *txbuf; 2656 struct mvneta_tx_desc *t; 2657 uint32_t ptxsu; 2658 int start, used, error, i, txnsegs; 2659 2660 mbuf = *mbufp; 2661 tx = MVNETA_TX_RING(sc, q); 2662 DASSERT(tx->used >= 0); 2663 DASSERT(tx->used <= MVNETA_TX_RING_CNT); 2664 t = NULL; 2665 ifp = sc->ifp; 2666 2667 if (__predict_false(mbuf->m_flags & M_VLANTAG)) { 2668 mbuf = ether_vlanencap(mbuf, mbuf->m_pkthdr.ether_vtag); 2669 if (mbuf == NULL) { 2670 tx->drv_error++; 2671 *mbufp = NULL; 2672 return (ENOBUFS); 2673 } 2674 mbuf->m_flags &= ~M_VLANTAG; 2675 *mbufp = mbuf; 2676 } 2677 2678 if (__predict_false(mbuf->m_next != NULL && 2679 (mbuf->m_pkthdr.csum_flags & 2680 (CSUM_IP | CSUM_TCP | CSUM_UDP)) != 0)) { 2681 if (M_WRITABLE(mbuf) == 0) { 2682 mtmp = m_dup(mbuf, M_NOWAIT); 2683 m_freem(mbuf); 2684 if (mtmp == NULL) { 2685 tx->drv_error++; 2686 *mbufp = NULL; 2687 return (ENOBUFS); 2688 } 2689 *mbufp = mbuf = mtmp; 2690 } 2691 } 2692 2693 /* load mbuf using dmamap of 1st descriptor */ 2694 txbuf = &tx->txbuf[tx->cpu]; 2695 error = bus_dmamap_load_mbuf_sg(sc->txmbuf_dtag, 2696 txbuf->dmap, mbuf, txsegs, &txnsegs, 2697 BUS_DMA_NOWAIT); 2698 if (__predict_false(error != 0)) { 2699 #ifdef MVNETA_KTR 2700 CTR3(KTR_SPARE2, "%s:%u bus_dmamap_load_mbuf_sg error=%d", ifp->if_xname, q, error); 2701 #endif 2702 /* This is the only recoverable error (except EFBIG). */ 2703 if (error != ENOMEM) { 2704 tx->drv_error++; 2705 m_freem(mbuf); 2706 *mbufp = NULL; 2707 return (ENOBUFS); 2708 } 2709 return (error); 2710 } 2711 2712 if (__predict_false(txnsegs <= 0 2713 || (txnsegs + tx->used) > MVNETA_TX_RING_CNT)) { 2714 /* we have no enough descriptors or mbuf is broken */ 2715 #ifdef MVNETA_KTR 2716 CTR3(KTR_SPARE2, "%s:%u not enough descriptors txnsegs=%d", 2717 ifp->if_xname, q, txnsegs); 2718 #endif 2719 bus_dmamap_unload(sc->txmbuf_dtag, txbuf->dmap); 2720 return (ENOBUFS); 2721 } 2722 DASSERT(txbuf->m == NULL); 2723 2724 /* remember mbuf using 1st descriptor */ 2725 txbuf->m = mbuf; 2726 bus_dmamap_sync(sc->txmbuf_dtag, txbuf->dmap, 2727 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2728 2729 /* load to tx descriptors */ 2730 start = tx->cpu; 2731 used = 0; 2732 for (i = 0; i < txnsegs; i++) { 2733 t = &tx->desc[tx->cpu]; 2734 t->command = 0; 2735 t->l4ichk = 0; 2736 t->flags = 0; 2737 if (__predict_true(i == 0)) { 2738 /* 1st descriptor */ 2739 t->command |= MVNETA_TX_CMD_W_PACKET_OFFSET(0); 2740 t->command |= MVNETA_TX_CMD_F; 2741 mvneta_tx_set_csumflag(ifp, t, mbuf); 2742 } 2743 t->bufptr_pa = txsegs[i].ds_addr; 2744 t->bytecnt = txsegs[i].ds_len; 2745 tx->cpu = tx_counter_adv(tx->cpu, 1); 2746 2747 tx->used++; 2748 used++; 2749 } 2750 /* t is last descriptor here */ 2751 DASSERT(t != NULL); 2752 t->command |= MVNETA_TX_CMD_L|MVNETA_TX_CMD_PADDING; 2753 2754 bus_dmamap_sync(sc->tx_dtag, tx->desc_map, 2755 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2756 2757 while (__predict_false(used > 255)) { 2758 ptxsu = MVNETA_PTXSU_NOWD(255); 2759 MVNETA_WRITE(sc, MVNETA_PTXSU(q), ptxsu); 2760 used -= 255; 2761 } 2762 if (__predict_true(used > 0)) { 2763 ptxsu = MVNETA_PTXSU_NOWD(used); 2764 MVNETA_WRITE(sc, MVNETA_PTXSU(q), ptxsu); 2765 } 2766 return (0); 2767 } 2768 2769 STATIC void 2770 mvneta_tx_set_csumflag(struct ifnet *ifp, 2771 struct mvneta_tx_desc *t, struct mbuf *m) 2772 { 2773 struct ether_header *eh; 2774 int csum_flags; 2775 uint32_t iphl, ipoff; 2776 struct ip *ip; 2777 2778 iphl = ipoff = 0; 2779 csum_flags = ifp->if_hwassist & m->m_pkthdr.csum_flags; 2780 eh = mtod(m, struct ether_header *); 2781 switch (ntohs(eh->ether_type)) { 2782 case ETHERTYPE_IP: 2783 ipoff = ETHER_HDR_LEN; 2784 break; 2785 case ETHERTYPE_IPV6: 2786 return; 2787 case ETHERTYPE_VLAN: 2788 ipoff = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 2789 break; 2790 } 2791 2792 if (__predict_true(csum_flags & (CSUM_IP|CSUM_IP_TCP|CSUM_IP_UDP))) { 2793 ip = (struct ip *)(m->m_data + ipoff); 2794 iphl = ip->ip_hl<<2; 2795 t->command |= MVNETA_TX_CMD_L3_IP4; 2796 } else { 2797 t->command |= MVNETA_TX_CMD_L4_CHECKSUM_NONE; 2798 return; 2799 } 2800 2801 2802 /* L3 */ 2803 if (csum_flags & CSUM_IP) { 2804 t->command |= MVNETA_TX_CMD_IP4_CHECKSUM; 2805 } 2806 2807 /* L4 */ 2808 if (csum_flags & CSUM_IP_TCP) { 2809 t->command |= MVNETA_TX_CMD_L4_CHECKSUM_NOFRAG; 2810 t->command |= MVNETA_TX_CMD_L4_TCP; 2811 } else if (csum_flags & CSUM_IP_UDP) { 2812 t->command |= MVNETA_TX_CMD_L4_CHECKSUM_NOFRAG; 2813 t->command |= MVNETA_TX_CMD_L4_UDP; 2814 } else 2815 t->command |= MVNETA_TX_CMD_L4_CHECKSUM_NONE; 2816 2817 t->l4ichk = 0; 2818 t->command |= MVNETA_TX_CMD_IP_HEADER_LEN(iphl >> 2); 2819 t->command |= MVNETA_TX_CMD_L3_OFFSET(ipoff); 2820 } 2821 2822 STATIC void 2823 mvneta_tx_queue_complete(struct mvneta_softc *sc, int q) 2824 { 2825 struct mvneta_tx_ring *tx; 2826 struct mvneta_buf *txbuf; 2827 struct mvneta_tx_desc *t; 2828 uint32_t ptxs, ptxsu, ndesc; 2829 int i; 2830 2831 KASSERT_TX_MTX(sc, q); 2832 2833 tx = MVNETA_TX_RING(sc, q); 2834 if (__predict_false(tx->queue_status == MVNETA_QUEUE_DISABLED)) 2835 return; 2836 2837 ptxs = MVNETA_READ(sc, MVNETA_PTXS(q)); 2838 ndesc = MVNETA_PTXS_GET_TBC(ptxs); 2839 2840 if (__predict_false(ndesc == 0)) { 2841 if (tx->used == 0) 2842 tx->queue_status = MVNETA_QUEUE_IDLE; 2843 else if (tx->queue_status == MVNETA_QUEUE_WORKING && 2844 ((ticks - tx->watchdog_time) > MVNETA_WATCHDOG)) 2845 tx->queue_hung = TRUE; 2846 return; 2847 } 2848 2849 #ifdef MVNETA_KTR 2850 CTR3(KTR_SPARE2, "%s:%u tx_complete begin ndesc=%u", 2851 sc->ifp->if_xname, q, ndesc); 2852 #endif 2853 2854 bus_dmamap_sync(sc->tx_dtag, tx->desc_map, 2855 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2856 2857 for (i = 0; i < ndesc; i++) { 2858 t = &tx->desc[tx->dma]; 2859 #ifdef MVNETA_KTR 2860 if (t->flags & MVNETA_TX_F_ES) 2861 CTR3(KTR_SPARE2, "%s tx error queue %d desc %d", 2862 sc->ifp->if_xname, q, tx->dma); 2863 #endif 2864 txbuf = &tx->txbuf[tx->dma]; 2865 if (__predict_true(txbuf->m != NULL)) { 2866 DASSERT((t->command & MVNETA_TX_CMD_F) != 0); 2867 bus_dmamap_unload(sc->txmbuf_dtag, txbuf->dmap); 2868 m_freem(txbuf->m); 2869 txbuf->m = NULL; 2870 } 2871 else 2872 DASSERT((t->flags & MVNETA_TX_CMD_F) == 0); 2873 tx->dma = tx_counter_adv(tx->dma, 1); 2874 tx->used--; 2875 } 2876 DASSERT(tx->used >= 0); 2877 DASSERT(tx->used <= MVNETA_TX_RING_CNT); 2878 while (__predict_false(ndesc > 255)) { 2879 ptxsu = MVNETA_PTXSU_NORB(255); 2880 MVNETA_WRITE(sc, MVNETA_PTXSU(q), ptxsu); 2881 ndesc -= 255; 2882 } 2883 if (__predict_true(ndesc > 0)) { 2884 ptxsu = MVNETA_PTXSU_NORB(ndesc); 2885 MVNETA_WRITE(sc, MVNETA_PTXSU(q), ptxsu); 2886 } 2887 #ifdef MVNETA_KTR 2888 CTR5(KTR_SPARE2, "%s:%u tx_complete tx_cpu=%d tx_dma=%d tx_used=%d", 2889 sc->ifp->if_xname, q, tx->cpu, tx->dma, tx->used); 2890 #endif 2891 2892 tx->watchdog_time = ticks; 2893 2894 if (tx->used == 0) 2895 tx->queue_status = MVNETA_QUEUE_IDLE; 2896 } 2897 2898 /* 2899 * Do a final TX complete when TX is idle. 2900 */ 2901 STATIC void 2902 mvneta_tx_drain(struct mvneta_softc *sc) 2903 { 2904 struct mvneta_tx_ring *tx; 2905 int q; 2906 2907 /* 2908 * Handle trailing mbuf on TX queue. 2909 * Check is done lockess to avoid TX path contention. 2910 */ 2911 for (q = 0; q < MVNETA_TX_QNUM_MAX; q++) { 2912 tx = MVNETA_TX_RING(sc, q); 2913 if ((ticks - tx->watchdog_time) > MVNETA_WATCHDOG_TXCOMP && 2914 tx->used > 0) { 2915 mvneta_tx_lockq(sc, q); 2916 mvneta_tx_queue_complete(sc, q); 2917 mvneta_tx_unlockq(sc, q); 2918 } 2919 } 2920 } 2921 2922 /* 2923 * Rx Subroutines 2924 */ 2925 STATIC int 2926 mvneta_rx(struct mvneta_softc *sc, int q, int count) 2927 { 2928 uint32_t prxs, npkt; 2929 int more; 2930 2931 more = 0; 2932 mvneta_rx_lockq(sc, q); 2933 prxs = MVNETA_READ(sc, MVNETA_PRXS(q)); 2934 npkt = MVNETA_PRXS_GET_ODC(prxs); 2935 if (__predict_false(npkt == 0)) 2936 goto out; 2937 2938 if (count > 0 && npkt > count) { 2939 more = 1; 2940 npkt = count; 2941 } 2942 mvneta_rx_queue(sc, q, npkt); 2943 out: 2944 mvneta_rx_unlockq(sc, q); 2945 return more; 2946 } 2947 2948 /* 2949 * Helper routine for updating PRXSU register of a given queue. 2950 * Handles number of processed descriptors bigger than maximum acceptable value. 2951 */ 2952 STATIC __inline void 2953 mvneta_prxsu_update(struct mvneta_softc *sc, int q, int processed) 2954 { 2955 uint32_t prxsu; 2956 2957 while (__predict_false(processed > 255)) { 2958 prxsu = MVNETA_PRXSU_NOOFPROCESSEDDESCRIPTORS(255); 2959 MVNETA_WRITE(sc, MVNETA_PRXSU(q), prxsu); 2960 processed -= 255; 2961 } 2962 prxsu = MVNETA_PRXSU_NOOFPROCESSEDDESCRIPTORS(processed); 2963 MVNETA_WRITE(sc, MVNETA_PRXSU(q), prxsu); 2964 } 2965 2966 static __inline void 2967 mvneta_prefetch(void *p) 2968 { 2969 2970 __builtin_prefetch(p); 2971 } 2972 2973 STATIC void 2974 mvneta_rx_queue(struct mvneta_softc *sc, int q, int npkt) 2975 { 2976 struct ifnet *ifp; 2977 struct mvneta_rx_ring *rx; 2978 struct mvneta_rx_desc *r; 2979 struct mvneta_buf *rxbuf; 2980 struct mbuf *m; 2981 struct lro_ctrl *lro; 2982 struct lro_entry *queued; 2983 void *pktbuf; 2984 int i, pktlen, processed, ndma; 2985 2986 KASSERT_RX_MTX(sc, q); 2987 2988 ifp = sc->ifp; 2989 rx = MVNETA_RX_RING(sc, q); 2990 processed = 0; 2991 2992 if (__predict_false(rx->queue_status == MVNETA_QUEUE_DISABLED)) 2993 return; 2994 2995 bus_dmamap_sync(sc->rx_dtag, rx->desc_map, 2996 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2997 2998 for (i = 0; i < npkt; i++) { 2999 /* Prefetch next desc, rxbuf. */ 3000 ndma = rx_counter_adv(rx->dma, 1); 3001 mvneta_prefetch(&rx->desc[ndma]); 3002 mvneta_prefetch(&rx->rxbuf[ndma]); 3003 3004 /* get descriptor and packet */ 3005 r = &rx->desc[rx->dma]; 3006 rxbuf = &rx->rxbuf[rx->dma]; 3007 m = rxbuf->m; 3008 rxbuf->m = NULL; 3009 DASSERT(m != NULL); 3010 bus_dmamap_sync(sc->rxbuf_dtag, rxbuf->dmap, 3011 BUS_DMASYNC_POSTREAD); 3012 bus_dmamap_unload(sc->rxbuf_dtag, rxbuf->dmap); 3013 /* Prefetch mbuf header. */ 3014 mvneta_prefetch(m); 3015 3016 processed++; 3017 /* Drop desc with error status or not in a single buffer. */ 3018 DASSERT((r->status & (MVNETA_RX_F|MVNETA_RX_L)) == 3019 (MVNETA_RX_F|MVNETA_RX_L)); 3020 if (__predict_false((r->status & MVNETA_RX_ES) || 3021 (r->status & (MVNETA_RX_F|MVNETA_RX_L)) != 3022 (MVNETA_RX_F|MVNETA_RX_L))) 3023 goto rx_error; 3024 3025 /* 3026 * [ OFF | MH | PKT | CRC ] 3027 * bytecnt cover MH, PKT, CRC 3028 */ 3029 pktlen = r->bytecnt - ETHER_CRC_LEN - MVNETA_HWHEADER_SIZE; 3030 pktbuf = (uint8_t *)rx->rxbuf_virt_addr[rx->dma] + MVNETA_PACKET_OFFSET + 3031 MVNETA_HWHEADER_SIZE; 3032 3033 /* Prefetch mbuf data. */ 3034 mvneta_prefetch(pktbuf); 3035 3036 /* Write value to mbuf (avoid read). */ 3037 m->m_data = pktbuf; 3038 m->m_len = m->m_pkthdr.len = pktlen; 3039 m->m_pkthdr.rcvif = ifp; 3040 mvneta_rx_set_csumflag(ifp, r, m); 3041 3042 /* Increase rx_dma before releasing the lock. */ 3043 rx->dma = ndma; 3044 3045 if (__predict_false(rx->lro_enabled && 3046 ((r->status & MVNETA_RX_L3_IP) != 0) && 3047 ((r->status & MVNETA_RX_L4_MASK) == MVNETA_RX_L4_TCP) && 3048 (m->m_pkthdr.csum_flags & 3049 (CSUM_DATA_VALID | CSUM_PSEUDO_HDR)) == 3050 (CSUM_DATA_VALID | CSUM_PSEUDO_HDR))) { 3051 if (rx->lro.lro_cnt != 0) { 3052 if (tcp_lro_rx(&rx->lro, m, 0) == 0) 3053 goto rx_done; 3054 } 3055 } 3056 3057 mvneta_rx_unlockq(sc, q); 3058 (*ifp->if_input)(ifp, m); 3059 mvneta_rx_lockq(sc, q); 3060 /* 3061 * Check whether this queue has been disabled in the 3062 * meantime. If yes, then clear LRO and exit. 3063 */ 3064 if(__predict_false(rx->queue_status == MVNETA_QUEUE_DISABLED)) 3065 goto rx_lro; 3066 rx_done: 3067 /* Refresh receive ring to avoid stall and minimize jitter. */ 3068 if (processed >= MVNETA_RX_REFILL_COUNT) { 3069 mvneta_prxsu_update(sc, q, processed); 3070 mvneta_rx_queue_refill(sc, q); 3071 processed = 0; 3072 } 3073 continue; 3074 rx_error: 3075 m_freem(m); 3076 rx->dma = ndma; 3077 /* Refresh receive ring to avoid stall and minimize jitter. */ 3078 if (processed >= MVNETA_RX_REFILL_COUNT) { 3079 mvneta_prxsu_update(sc, q, processed); 3080 mvneta_rx_queue_refill(sc, q); 3081 processed = 0; 3082 } 3083 } 3084 #ifdef MVNETA_KTR 3085 CTR3(KTR_SPARE2, "%s:%u %u packets received", ifp->if_xname, q, npkt); 3086 #endif 3087 /* DMA status update */ 3088 mvneta_prxsu_update(sc, q, processed); 3089 /* Refill the rest of buffers if there are any to refill */ 3090 mvneta_rx_queue_refill(sc, q); 3091 3092 rx_lro: 3093 /* 3094 * Flush any outstanding LRO work 3095 */ 3096 lro = &rx->lro; 3097 while (__predict_false((queued = LIST_FIRST(&lro->lro_active)) != NULL)) { 3098 LIST_REMOVE(LIST_FIRST((&lro->lro_active)), next); 3099 tcp_lro_flush(lro, queued); 3100 } 3101 } 3102 3103 STATIC void 3104 mvneta_rx_buf_free(struct mvneta_softc *sc, struct mvneta_buf *rxbuf) 3105 { 3106 3107 bus_dmamap_unload(sc->rxbuf_dtag, rxbuf->dmap); 3108 /* This will remove all data at once */ 3109 m_freem(rxbuf->m); 3110 } 3111 3112 STATIC void 3113 mvneta_rx_queue_refill(struct mvneta_softc *sc, int q) 3114 { 3115 struct mvneta_rx_ring *rx; 3116 struct mvneta_rx_desc *r; 3117 struct mvneta_buf *rxbuf; 3118 bus_dma_segment_t segs; 3119 struct mbuf *m; 3120 uint32_t prxs, prxsu, ndesc; 3121 int npkt, refill, nsegs, error; 3122 3123 KASSERT_RX_MTX(sc, q); 3124 3125 rx = MVNETA_RX_RING(sc, q); 3126 prxs = MVNETA_READ(sc, MVNETA_PRXS(q)); 3127 ndesc = MVNETA_PRXS_GET_NODC(prxs) + MVNETA_PRXS_GET_ODC(prxs); 3128 refill = MVNETA_RX_RING_CNT - ndesc; 3129 #ifdef MVNETA_KTR 3130 CTR3(KTR_SPARE2, "%s:%u refill %u packets", sc->ifp->if_xname, q, 3131 refill); 3132 #endif 3133 if (__predict_false(refill <= 0)) 3134 return; 3135 3136 for (npkt = 0; npkt < refill; npkt++) { 3137 rxbuf = &rx->rxbuf[rx->cpu]; 3138 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 3139 if (__predict_false(m == NULL)) { 3140 error = ENOBUFS; 3141 break; 3142 } 3143 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 3144 3145 error = bus_dmamap_load_mbuf_sg(sc->rxbuf_dtag, rxbuf->dmap, 3146 m, &segs, &nsegs, BUS_DMA_NOWAIT); 3147 if (__predict_false(error != 0 || nsegs != 1)) { 3148 KASSERT(1, ("Failed to load Rx mbuf DMA map")); 3149 m_freem(m); 3150 break; 3151 } 3152 3153 /* Add the packet to the ring */ 3154 rxbuf->m = m; 3155 r = &rx->desc[rx->cpu]; 3156 r->bufptr_pa = segs.ds_addr; 3157 rx->rxbuf_virt_addr[rx->cpu] = m->m_data; 3158 3159 rx->cpu = rx_counter_adv(rx->cpu, 1); 3160 } 3161 if (npkt == 0) { 3162 if (refill == MVNETA_RX_RING_CNT) 3163 rx->needs_refill = TRUE; 3164 return; 3165 } 3166 3167 rx->needs_refill = FALSE; 3168 bus_dmamap_sync(sc->rx_dtag, rx->desc_map, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3169 3170 while (__predict_false(npkt > 255)) { 3171 prxsu = MVNETA_PRXSU_NOOFNEWDESCRIPTORS(255); 3172 MVNETA_WRITE(sc, MVNETA_PRXSU(q), prxsu); 3173 npkt -= 255; 3174 } 3175 if (__predict_true(npkt > 0)) { 3176 prxsu = MVNETA_PRXSU_NOOFNEWDESCRIPTORS(npkt); 3177 MVNETA_WRITE(sc, MVNETA_PRXSU(q), prxsu); 3178 } 3179 } 3180 3181 STATIC __inline void 3182 mvneta_rx_set_csumflag(struct ifnet *ifp, 3183 struct mvneta_rx_desc *r, struct mbuf *m) 3184 { 3185 uint32_t csum_flags; 3186 3187 csum_flags = 0; 3188 if (__predict_false((r->status & 3189 (MVNETA_RX_IP_HEADER_OK|MVNETA_RX_L3_IP)) == 0)) 3190 return; /* not a IP packet */ 3191 3192 /* L3 */ 3193 if (__predict_true((r->status & MVNETA_RX_IP_HEADER_OK) == 3194 MVNETA_RX_IP_HEADER_OK)) 3195 csum_flags |= CSUM_L3_CALC|CSUM_L3_VALID; 3196 3197 if (__predict_true((r->status & (MVNETA_RX_IP_HEADER_OK|MVNETA_RX_L3_IP)) == 3198 (MVNETA_RX_IP_HEADER_OK|MVNETA_RX_L3_IP))) { 3199 /* L4 */ 3200 switch (r->status & MVNETA_RX_L4_MASK) { 3201 case MVNETA_RX_L4_TCP: 3202 case MVNETA_RX_L4_UDP: 3203 csum_flags |= CSUM_L4_CALC; 3204 if (__predict_true((r->status & 3205 MVNETA_RX_L4_CHECKSUM_OK) == MVNETA_RX_L4_CHECKSUM_OK)) { 3206 csum_flags |= CSUM_L4_VALID; 3207 m->m_pkthdr.csum_data = htons(0xffff); 3208 } 3209 break; 3210 case MVNETA_RX_L4_OTH: 3211 default: 3212 break; 3213 } 3214 } 3215 m->m_pkthdr.csum_flags = csum_flags; 3216 } 3217 3218 /* 3219 * MAC address filter 3220 */ 3221 STATIC void 3222 mvneta_filter_setup(struct mvneta_softc *sc) 3223 { 3224 struct ifnet *ifp; 3225 uint32_t dfut[MVNETA_NDFUT], dfsmt[MVNETA_NDFSMT], dfomt[MVNETA_NDFOMT]; 3226 uint32_t pxc; 3227 int i; 3228 3229 KASSERT_SC_MTX(sc); 3230 3231 memset(dfut, 0, sizeof(dfut)); 3232 memset(dfsmt, 0, sizeof(dfsmt)); 3233 memset(dfomt, 0, sizeof(dfomt)); 3234 3235 ifp = sc->ifp; 3236 ifp->if_flags |= IFF_ALLMULTI; 3237 if (ifp->if_flags & (IFF_ALLMULTI|IFF_PROMISC)) { 3238 for (i = 0; i < MVNETA_NDFSMT; i++) { 3239 dfsmt[i] = dfomt[i] = 3240 MVNETA_DF(0, MVNETA_DF_QUEUE(0) | MVNETA_DF_PASS) | 3241 MVNETA_DF(1, MVNETA_DF_QUEUE(0) | MVNETA_DF_PASS) | 3242 MVNETA_DF(2, MVNETA_DF_QUEUE(0) | MVNETA_DF_PASS) | 3243 MVNETA_DF(3, MVNETA_DF_QUEUE(0) | MVNETA_DF_PASS); 3244 } 3245 } 3246 3247 pxc = MVNETA_READ(sc, MVNETA_PXC); 3248 pxc &= ~(MVNETA_PXC_UPM | MVNETA_PXC_RXQ_MASK | MVNETA_PXC_RXQARP_MASK | 3249 MVNETA_PXC_TCPQ_MASK | MVNETA_PXC_UDPQ_MASK | MVNETA_PXC_BPDUQ_MASK); 3250 pxc |= MVNETA_PXC_RXQ(MVNETA_RX_QNUM_MAX-1); 3251 pxc |= MVNETA_PXC_RXQARP(MVNETA_RX_QNUM_MAX-1); 3252 pxc |= MVNETA_PXC_TCPQ(MVNETA_RX_QNUM_MAX-1); 3253 pxc |= MVNETA_PXC_UDPQ(MVNETA_RX_QNUM_MAX-1); 3254 pxc |= MVNETA_PXC_BPDUQ(MVNETA_RX_QNUM_MAX-1); 3255 pxc |= MVNETA_PXC_RB | MVNETA_PXC_RBIP | MVNETA_PXC_RBARP; 3256 if (ifp->if_flags & IFF_BROADCAST) { 3257 pxc &= ~(MVNETA_PXC_RB | MVNETA_PXC_RBIP | MVNETA_PXC_RBARP); 3258 } 3259 if (ifp->if_flags & IFF_PROMISC) { 3260 pxc |= MVNETA_PXC_UPM; 3261 } 3262 MVNETA_WRITE(sc, MVNETA_PXC, pxc); 3263 3264 /* Set Destination Address Filter Unicast Table */ 3265 if (ifp->if_flags & IFF_PROMISC) { 3266 /* pass all unicast addresses */ 3267 for (i = 0; i < MVNETA_NDFUT; i++) { 3268 dfut[i] = 3269 MVNETA_DF(0, MVNETA_DF_QUEUE(0) | MVNETA_DF_PASS) | 3270 MVNETA_DF(1, MVNETA_DF_QUEUE(0) | MVNETA_DF_PASS) | 3271 MVNETA_DF(2, MVNETA_DF_QUEUE(0) | MVNETA_DF_PASS) | 3272 MVNETA_DF(3, MVNETA_DF_QUEUE(0) | MVNETA_DF_PASS); 3273 } 3274 } else { 3275 i = sc->enaddr[5] & 0xf; /* last nibble */ 3276 dfut[i>>2] = MVNETA_DF(i&3, MVNETA_DF_QUEUE(0) | MVNETA_DF_PASS); 3277 } 3278 MVNETA_WRITE_REGION(sc, MVNETA_DFUT(0), dfut, MVNETA_NDFUT); 3279 3280 /* Set Destination Address Filter Multicast Tables */ 3281 MVNETA_WRITE_REGION(sc, MVNETA_DFSMT(0), dfsmt, MVNETA_NDFSMT); 3282 MVNETA_WRITE_REGION(sc, MVNETA_DFOMT(0), dfomt, MVNETA_NDFOMT); 3283 } 3284 3285 /* 3286 * sysctl(9) 3287 */ 3288 STATIC int 3289 sysctl_read_mib(SYSCTL_HANDLER_ARGS) 3290 { 3291 struct mvneta_sysctl_mib *arg; 3292 struct mvneta_softc *sc; 3293 uint64_t val; 3294 3295 arg = (struct mvneta_sysctl_mib *)arg1; 3296 if (arg == NULL) 3297 return (EINVAL); 3298 3299 sc = arg->sc; 3300 if (sc == NULL) 3301 return (EINVAL); 3302 if (arg->index < 0 || arg->index > MVNETA_PORTMIB_NOCOUNTER) 3303 return (EINVAL); 3304 3305 mvneta_sc_lock(sc); 3306 val = arg->counter; 3307 mvneta_sc_unlock(sc); 3308 return sysctl_handle_64(oidp, &val, 0, req); 3309 } 3310 3311 3312 STATIC int 3313 sysctl_clear_mib(SYSCTL_HANDLER_ARGS) 3314 { 3315 struct mvneta_softc *sc; 3316 int err, val; 3317 3318 val = 0; 3319 sc = (struct mvneta_softc *)arg1; 3320 if (sc == NULL) 3321 return (EINVAL); 3322 3323 err = sysctl_handle_int(oidp, &val, 0, req); 3324 if (err != 0) 3325 return (err); 3326 3327 if (val < 0 || val > 1) 3328 return (EINVAL); 3329 3330 if (val == 1) { 3331 mvneta_sc_lock(sc); 3332 mvneta_clear_mib(sc); 3333 mvneta_sc_unlock(sc); 3334 } 3335 3336 return (0); 3337 } 3338 3339 STATIC int 3340 sysctl_set_queue_rxthtime(SYSCTL_HANDLER_ARGS) 3341 { 3342 struct mvneta_sysctl_queue *arg; 3343 struct mvneta_rx_ring *rx; 3344 struct mvneta_softc *sc; 3345 uint32_t reg, time_mvtclk; 3346 int err, time_us; 3347 3348 rx = NULL; 3349 arg = (struct mvneta_sysctl_queue *)arg1; 3350 if (arg == NULL) 3351 return (EINVAL); 3352 if (arg->queue < 0 || arg->queue > MVNETA_RX_RING_CNT) 3353 return (EINVAL); 3354 if (arg->rxtx != MVNETA_SYSCTL_RX) 3355 return (EINVAL); 3356 3357 sc = arg->sc; 3358 if (sc == NULL) 3359 return (EINVAL); 3360 3361 /* read queue length */ 3362 mvneta_sc_lock(sc); 3363 mvneta_rx_lockq(sc, arg->queue); 3364 rx = MVNETA_RX_RING(sc, arg->queue); 3365 time_mvtclk = rx->queue_th_time; 3366 time_us = ((uint64_t)time_mvtclk * 1000ULL * 1000ULL) / mvneta_get_clk(); 3367 mvneta_rx_unlockq(sc, arg->queue); 3368 mvneta_sc_unlock(sc); 3369 3370 err = sysctl_handle_int(oidp, &time_us, 0, req); 3371 if (err != 0) 3372 return (err); 3373 3374 mvneta_sc_lock(sc); 3375 mvneta_rx_lockq(sc, arg->queue); 3376 3377 /* update queue length (0[sec] - 1[sec]) */ 3378 if (time_us < 0 || time_us > (1000 * 1000)) { 3379 mvneta_rx_unlockq(sc, arg->queue); 3380 mvneta_sc_unlock(sc); 3381 return (EINVAL); 3382 } 3383 time_mvtclk = 3384 (uint64_t)mvneta_get_clk() * (uint64_t)time_us / (1000ULL * 1000ULL); 3385 rx->queue_th_time = time_mvtclk; 3386 reg = MVNETA_PRXITTH_RITT(rx->queue_th_time); 3387 MVNETA_WRITE(sc, MVNETA_PRXITTH(arg->queue), reg); 3388 mvneta_rx_unlockq(sc, arg->queue); 3389 mvneta_sc_unlock(sc); 3390 3391 return (0); 3392 } 3393 3394 STATIC void 3395 sysctl_mvneta_init(struct mvneta_softc *sc) 3396 { 3397 struct sysctl_ctx_list *ctx; 3398 struct sysctl_oid_list *children; 3399 struct sysctl_oid_list *rxchildren; 3400 struct sysctl_oid_list *qchildren, *mchildren; 3401 struct sysctl_oid *tree; 3402 int i, q; 3403 struct mvneta_sysctl_queue *rxarg; 3404 #define MVNETA_SYSCTL_NAME(num) "queue" # num 3405 static const char *sysctl_queue_names[] = { 3406 MVNETA_SYSCTL_NAME(0), MVNETA_SYSCTL_NAME(1), 3407 MVNETA_SYSCTL_NAME(2), MVNETA_SYSCTL_NAME(3), 3408 MVNETA_SYSCTL_NAME(4), MVNETA_SYSCTL_NAME(5), 3409 MVNETA_SYSCTL_NAME(6), MVNETA_SYSCTL_NAME(7), 3410 }; 3411 #undef MVNETA_SYSCTL_NAME 3412 3413 #define MVNETA_SYSCTL_DESCR(num) "configuration parameters for queue " # num 3414 static const char *sysctl_queue_descrs[] = { 3415 MVNETA_SYSCTL_DESCR(0), MVNETA_SYSCTL_DESCR(1), 3416 MVNETA_SYSCTL_DESCR(2), MVNETA_SYSCTL_DESCR(3), 3417 MVNETA_SYSCTL_DESCR(4), MVNETA_SYSCTL_DESCR(5), 3418 MVNETA_SYSCTL_DESCR(6), MVNETA_SYSCTL_DESCR(7), 3419 }; 3420 #undef MVNETA_SYSCTL_DESCR 3421 3422 3423 ctx = device_get_sysctl_ctx(sc->dev); 3424 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)); 3425 3426 tree = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "rx", 3427 CTLFLAG_RD, 0, "NETA RX"); 3428 rxchildren = SYSCTL_CHILDREN(tree); 3429 tree = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "mib", 3430 CTLFLAG_RD, 0, "NETA MIB"); 3431 mchildren = SYSCTL_CHILDREN(tree); 3432 3433 3434 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "flow_control", 3435 CTLFLAG_RW, &sc->cf_fc, 0, "flow control"); 3436 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "lpi", 3437 CTLFLAG_RW, &sc->cf_lpi, 0, "Low Power Idle"); 3438 3439 /* 3440 * MIB access 3441 */ 3442 /* dev.mvneta.[unit].mib.<mibs> */ 3443 for (i = 0; i < MVNETA_PORTMIB_NOCOUNTER; i++) { 3444 const char *name = mvneta_mib_list[i].sysctl_name; 3445 const char *desc = mvneta_mib_list[i].desc; 3446 struct mvneta_sysctl_mib *mib_arg = &sc->sysctl_mib[i]; 3447 3448 mib_arg->sc = sc; 3449 mib_arg->index = i; 3450 SYSCTL_ADD_PROC(ctx, mchildren, OID_AUTO, name, 3451 CTLTYPE_U64|CTLFLAG_RD, (void *)mib_arg, 0, 3452 sysctl_read_mib, "I", desc); 3453 } 3454 SYSCTL_ADD_UQUAD(ctx, mchildren, OID_AUTO, "rx_discard", 3455 CTLFLAG_RD, &sc->counter_pdfc, "Port Rx Discard Frame Counter"); 3456 SYSCTL_ADD_UQUAD(ctx, mchildren, OID_AUTO, "overrun", 3457 CTLFLAG_RD, &sc->counter_pofc, "Port Overrun Frame Counter"); 3458 SYSCTL_ADD_UINT(ctx, mchildren, OID_AUTO, "watchdog", 3459 CTLFLAG_RD, &sc->counter_watchdog, 0, "TX Watchdog Counter"); 3460 3461 SYSCTL_ADD_PROC(ctx, mchildren, OID_AUTO, "reset", 3462 CTLTYPE_INT|CTLFLAG_RW, (void *)sc, 0, 3463 sysctl_clear_mib, "I", "Reset MIB counters"); 3464 3465 for (q = 0; q < MVNETA_RX_QNUM_MAX; q++) { 3466 rxarg = &sc->sysctl_rx_queue[q]; 3467 3468 rxarg->sc = sc; 3469 rxarg->queue = q; 3470 rxarg->rxtx = MVNETA_SYSCTL_RX; 3471 3472 /* hw.mvneta.mvneta[unit].rx.[queue] */ 3473 tree = SYSCTL_ADD_NODE(ctx, rxchildren, OID_AUTO, 3474 sysctl_queue_names[q], CTLFLAG_RD, 0, 3475 sysctl_queue_descrs[q]); 3476 qchildren = SYSCTL_CHILDREN(tree); 3477 3478 /* hw.mvneta.mvneta[unit].rx.[queue].threshold_timer_us */ 3479 SYSCTL_ADD_PROC(ctx, qchildren, OID_AUTO, "threshold_timer_us", 3480 CTLTYPE_UINT | CTLFLAG_RW, rxarg, 0, 3481 sysctl_set_queue_rxthtime, "I", 3482 "interrupt coalescing threshold timer [us]"); 3483 } 3484 } 3485 3486 /* 3487 * MIB 3488 */ 3489 STATIC void 3490 mvneta_clear_mib(struct mvneta_softc *sc) 3491 { 3492 int i; 3493 3494 KASSERT_SC_MTX(sc); 3495 3496 for (i = 0; i < nitems(mvneta_mib_list); i++) { 3497 if (mvneta_mib_list[i].reg64) 3498 MVNETA_READ_MIB_8(sc, mvneta_mib_list[i].regnum); 3499 else 3500 MVNETA_READ_MIB_4(sc, mvneta_mib_list[i].regnum); 3501 sc->sysctl_mib[i].counter = 0; 3502 } 3503 MVNETA_READ(sc, MVNETA_PDFC); 3504 sc->counter_pdfc = 0; 3505 MVNETA_READ(sc, MVNETA_POFC); 3506 sc->counter_pofc = 0; 3507 sc->counter_watchdog = 0; 3508 } 3509 3510 STATIC void 3511 mvneta_update_mib(struct mvneta_softc *sc) 3512 { 3513 struct mvneta_tx_ring *tx; 3514 int i; 3515 uint64_t val; 3516 uint32_t reg; 3517 3518 for (i = 0; i < nitems(mvneta_mib_list); i++) { 3519 3520 if (mvneta_mib_list[i].reg64) 3521 val = MVNETA_READ_MIB_8(sc, mvneta_mib_list[i].regnum); 3522 else 3523 val = MVNETA_READ_MIB_4(sc, mvneta_mib_list[i].regnum); 3524 3525 if (val == 0) 3526 continue; 3527 3528 sc->sysctl_mib[i].counter += val; 3529 switch (mvneta_mib_list[i].regnum) { 3530 case MVNETA_MIB_RX_GOOD_OCT: 3531 if_inc_counter(sc->ifp, IFCOUNTER_IBYTES, val); 3532 break; 3533 case MVNETA_MIB_RX_BAD_FRAME: 3534 if_inc_counter(sc->ifp, IFCOUNTER_IERRORS, val); 3535 break; 3536 case MVNETA_MIB_RX_GOOD_FRAME: 3537 if_inc_counter(sc->ifp, IFCOUNTER_IPACKETS, val); 3538 break; 3539 case MVNETA_MIB_RX_MCAST_FRAME: 3540 if_inc_counter(sc->ifp, IFCOUNTER_IMCASTS, val); 3541 break; 3542 case MVNETA_MIB_TX_GOOD_OCT: 3543 if_inc_counter(sc->ifp, IFCOUNTER_OBYTES, val); 3544 break; 3545 case MVNETA_MIB_TX_GOOD_FRAME: 3546 if_inc_counter(sc->ifp, IFCOUNTER_OPACKETS, val); 3547 break; 3548 case MVNETA_MIB_TX_MCAST_FRAME: 3549 if_inc_counter(sc->ifp, IFCOUNTER_OMCASTS, val); 3550 break; 3551 case MVNETA_MIB_MAC_COL: 3552 if_inc_counter(sc->ifp, IFCOUNTER_COLLISIONS, val); 3553 break; 3554 case MVNETA_MIB_TX_MAC_TRNS_ERR: 3555 case MVNETA_MIB_TX_EXCES_COL: 3556 case MVNETA_MIB_MAC_LATE_COL: 3557 if_inc_counter(sc->ifp, IFCOUNTER_OERRORS, val); 3558 break; 3559 } 3560 } 3561 3562 reg = MVNETA_READ(sc, MVNETA_PDFC); 3563 sc->counter_pdfc += reg; 3564 if_inc_counter(sc->ifp, IFCOUNTER_IQDROPS, reg); 3565 reg = MVNETA_READ(sc, MVNETA_POFC); 3566 sc->counter_pofc += reg; 3567 if_inc_counter(sc->ifp, IFCOUNTER_IQDROPS, reg); 3568 3569 /* TX watchdog. */ 3570 if (sc->counter_watchdog_mib > 0) { 3571 if_inc_counter(sc->ifp, IFCOUNTER_OERRORS, sc->counter_watchdog_mib); 3572 sc->counter_watchdog_mib = 0; 3573 } 3574 /* 3575 * TX driver errors: 3576 * We do not take queue locks to not disrupt TX path. 3577 * We may only miss one drv error which will be fixed at 3578 * next mib update. We may also clear counter when TX path 3579 * is incrementing it but we only do it if counter was not zero 3580 * thus we may only loose one error. 3581 */ 3582 for (i = 0; i < MVNETA_TX_QNUM_MAX; i++) { 3583 tx = MVNETA_TX_RING(sc, i); 3584 3585 if (tx->drv_error > 0) { 3586 if_inc_counter(sc->ifp, IFCOUNTER_OERRORS, tx->drv_error); 3587 tx->drv_error = 0; 3588 } 3589 } 3590 } 3591