1 /* 2 * Copyright (c) 2017 Stormshield. 3 * Copyright (c) 2017 Semihalf. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 17 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 24 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #include "opt_platform.h" 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/endian.h> 35 #include <sys/mbuf.h> 36 #include <sys/lock.h> 37 #include <sys/mutex.h> 38 #include <sys/kernel.h> 39 #include <sys/module.h> 40 #include <sys/socket.h> 41 #include <sys/sysctl.h> 42 #include <sys/smp.h> 43 #include <sys/taskqueue.h> 44 #ifdef MVNETA_KTR 45 #include <sys/ktr.h> 46 #endif 47 48 #include <net/ethernet.h> 49 #include <net/bpf.h> 50 #include <net/if.h> 51 #include <net/if_arp.h> 52 #include <net/if_dl.h> 53 #include <net/if_media.h> 54 #include <net/if_types.h> 55 #include <net/if_vlan_var.h> 56 57 #include <netinet/in_systm.h> 58 #include <netinet/in.h> 59 #include <netinet/ip.h> 60 #include <netinet/tcp_lro.h> 61 62 #include <sys/sockio.h> 63 #include <sys/bus.h> 64 #include <machine/bus.h> 65 #include <sys/rman.h> 66 #include <machine/resource.h> 67 68 #include <dev/mii/mii.h> 69 #include <dev/mii/miivar.h> 70 71 #include <dev/ofw/openfirm.h> 72 #include <dev/ofw/ofw_bus.h> 73 #include <dev/ofw/ofw_bus_subr.h> 74 75 #include <dev/mdio/mdio.h> 76 77 #include <arm/mv/mvvar.h> 78 79 #if !defined(__aarch64__) 80 #include <arm/mv/mvreg.h> 81 #include <arm/mv/mvwin.h> 82 #endif 83 84 #include "if_mvnetareg.h" 85 #include "if_mvnetavar.h" 86 87 #include "miibus_if.h" 88 #include "mdio_if.h" 89 90 #ifdef MVNETA_DEBUG 91 #define STATIC /* nothing */ 92 #else 93 #define STATIC static 94 #endif 95 96 #define DASSERT(x) KASSERT((x), (#x)) 97 98 #define A3700_TCLK_250MHZ 250000000 99 100 /* Device Register Initialization */ 101 STATIC int mvneta_initreg(struct ifnet *); 102 103 /* Descriptor Ring Control for each of queues */ 104 STATIC int mvneta_ring_alloc_rx_queue(struct mvneta_softc *, int); 105 STATIC int mvneta_ring_alloc_tx_queue(struct mvneta_softc *, int); 106 STATIC void mvneta_ring_dealloc_rx_queue(struct mvneta_softc *, int); 107 STATIC void mvneta_ring_dealloc_tx_queue(struct mvneta_softc *, int); 108 STATIC int mvneta_ring_init_rx_queue(struct mvneta_softc *, int); 109 STATIC int mvneta_ring_init_tx_queue(struct mvneta_softc *, int); 110 STATIC void mvneta_ring_flush_rx_queue(struct mvneta_softc *, int); 111 STATIC void mvneta_ring_flush_tx_queue(struct mvneta_softc *, int); 112 STATIC void mvneta_dmamap_cb(void *, bus_dma_segment_t *, int, int); 113 STATIC int mvneta_dma_create(struct mvneta_softc *); 114 115 /* Rx/Tx Queue Control */ 116 STATIC int mvneta_rx_queue_init(struct ifnet *, int); 117 STATIC int mvneta_tx_queue_init(struct ifnet *, int); 118 STATIC int mvneta_rx_queue_enable(struct ifnet *, int); 119 STATIC int mvneta_tx_queue_enable(struct ifnet *, int); 120 STATIC void mvneta_rx_lockq(struct mvneta_softc *, int); 121 STATIC void mvneta_rx_unlockq(struct mvneta_softc *, int); 122 STATIC void mvneta_tx_lockq(struct mvneta_softc *, int); 123 STATIC void mvneta_tx_unlockq(struct mvneta_softc *, int); 124 125 /* Interrupt Handlers */ 126 STATIC void mvneta_disable_intr(struct mvneta_softc *); 127 STATIC void mvneta_enable_intr(struct mvneta_softc *); 128 STATIC void mvneta_rxtxth_intr(void *); 129 STATIC int mvneta_misc_intr(struct mvneta_softc *); 130 STATIC void mvneta_tick(void *); 131 /* struct ifnet and mii callbacks*/ 132 STATIC int mvneta_xmitfast_locked(struct mvneta_softc *, int, struct mbuf **); 133 STATIC int mvneta_xmit_locked(struct mvneta_softc *, int); 134 #ifdef MVNETA_MULTIQUEUE 135 STATIC int mvneta_transmit(struct ifnet *, struct mbuf *); 136 #else /* !MVNETA_MULTIQUEUE */ 137 STATIC void mvneta_start(struct ifnet *); 138 #endif 139 STATIC void mvneta_qflush(struct ifnet *); 140 STATIC void mvneta_tx_task(void *, int); 141 STATIC int mvneta_ioctl(struct ifnet *, u_long, caddr_t); 142 STATIC void mvneta_init(void *); 143 STATIC void mvneta_init_locked(void *); 144 STATIC void mvneta_stop(struct mvneta_softc *); 145 STATIC void mvneta_stop_locked(struct mvneta_softc *); 146 STATIC int mvneta_mediachange(struct ifnet *); 147 STATIC void mvneta_mediastatus(struct ifnet *, struct ifmediareq *); 148 STATIC void mvneta_portup(struct mvneta_softc *); 149 STATIC void mvneta_portdown(struct mvneta_softc *); 150 151 /* Link State Notify */ 152 STATIC void mvneta_update_autoneg(struct mvneta_softc *, int); 153 STATIC int mvneta_update_media(struct mvneta_softc *, int); 154 STATIC void mvneta_adjust_link(struct mvneta_softc *); 155 STATIC void mvneta_update_eee(struct mvneta_softc *); 156 STATIC void mvneta_update_fc(struct mvneta_softc *); 157 STATIC void mvneta_link_isr(struct mvneta_softc *); 158 STATIC void mvneta_linkupdate(struct mvneta_softc *, boolean_t); 159 STATIC void mvneta_linkup(struct mvneta_softc *); 160 STATIC void mvneta_linkdown(struct mvneta_softc *); 161 STATIC void mvneta_linkreset(struct mvneta_softc *); 162 163 /* Tx Subroutines */ 164 STATIC int mvneta_tx_queue(struct mvneta_softc *, struct mbuf **, int); 165 STATIC void mvneta_tx_set_csumflag(struct ifnet *, 166 struct mvneta_tx_desc *, struct mbuf *); 167 STATIC void mvneta_tx_queue_complete(struct mvneta_softc *, int); 168 STATIC void mvneta_tx_drain(struct mvneta_softc *); 169 170 /* Rx Subroutines */ 171 STATIC int mvneta_rx(struct mvneta_softc *, int, int); 172 STATIC void mvneta_rx_queue(struct mvneta_softc *, int, int); 173 STATIC void mvneta_rx_queue_refill(struct mvneta_softc *, int); 174 STATIC void mvneta_rx_set_csumflag(struct ifnet *, 175 struct mvneta_rx_desc *, struct mbuf *); 176 STATIC void mvneta_rx_buf_free(struct mvneta_softc *, struct mvneta_buf *); 177 178 /* MAC address filter */ 179 STATIC void mvneta_filter_setup(struct mvneta_softc *); 180 181 /* sysctl(9) */ 182 STATIC int sysctl_read_mib(SYSCTL_HANDLER_ARGS); 183 STATIC int sysctl_clear_mib(SYSCTL_HANDLER_ARGS); 184 STATIC int sysctl_set_queue_rxthtime(SYSCTL_HANDLER_ARGS); 185 STATIC void sysctl_mvneta_init(struct mvneta_softc *); 186 187 /* MIB */ 188 STATIC void mvneta_clear_mib(struct mvneta_softc *); 189 STATIC uint64_t mvneta_read_mib(struct mvneta_softc *, int); 190 STATIC void mvneta_update_mib(struct mvneta_softc *); 191 192 /* Switch */ 193 STATIC boolean_t mvneta_find_ethernet_prop_switch(phandle_t, phandle_t); 194 STATIC boolean_t mvneta_has_switch(device_t); 195 196 #define mvneta_sc_lock(sc) mtx_lock(&sc->mtx) 197 #define mvneta_sc_unlock(sc) mtx_unlock(&sc->mtx) 198 199 STATIC struct mtx mii_mutex; 200 STATIC int mii_init = 0; 201 202 /* Device */ 203 STATIC int mvneta_detach(device_t); 204 /* MII */ 205 STATIC int mvneta_miibus_readreg(device_t, int, int); 206 STATIC int mvneta_miibus_writereg(device_t, int, int, int); 207 208 /* Clock */ 209 STATIC uint32_t mvneta_get_clk(void); 210 211 static device_method_t mvneta_methods[] = { 212 /* Device interface */ 213 DEVMETHOD(device_detach, mvneta_detach), 214 /* MII interface */ 215 DEVMETHOD(miibus_readreg, mvneta_miibus_readreg), 216 DEVMETHOD(miibus_writereg, mvneta_miibus_writereg), 217 /* MDIO interface */ 218 DEVMETHOD(mdio_readreg, mvneta_miibus_readreg), 219 DEVMETHOD(mdio_writereg, mvneta_miibus_writereg), 220 221 /* End */ 222 DEVMETHOD_END 223 }; 224 225 DEFINE_CLASS_0(mvneta, mvneta_driver, mvneta_methods, sizeof(struct mvneta_softc)); 226 227 DRIVER_MODULE(miibus, mvneta, miibus_driver, miibus_devclass, 0, 0); 228 DRIVER_MODULE(mdio, mvneta, mdio_driver, mdio_devclass, 0, 0); 229 MODULE_DEPEND(mvneta, mdio, 1, 1, 1); 230 MODULE_DEPEND(mvneta, ether, 1, 1, 1); 231 MODULE_DEPEND(mvneta, miibus, 1, 1, 1); 232 MODULE_DEPEND(mvneta, mvxpbm, 1, 1, 1); 233 234 /* 235 * List of MIB register and names 236 */ 237 enum mvneta_mib_idx 238 { 239 MVNETA_MIB_RX_GOOD_OCT_IDX, 240 MVNETA_MIB_RX_BAD_OCT_IDX, 241 MVNETA_MIB_TX_MAC_TRNS_ERR_IDX, 242 MVNETA_MIB_RX_GOOD_FRAME_IDX, 243 MVNETA_MIB_RX_BAD_FRAME_IDX, 244 MVNETA_MIB_RX_BCAST_FRAME_IDX, 245 MVNETA_MIB_RX_MCAST_FRAME_IDX, 246 MVNETA_MIB_RX_FRAME64_OCT_IDX, 247 MVNETA_MIB_RX_FRAME127_OCT_IDX, 248 MVNETA_MIB_RX_FRAME255_OCT_IDX, 249 MVNETA_MIB_RX_FRAME511_OCT_IDX, 250 MVNETA_MIB_RX_FRAME1023_OCT_IDX, 251 MVNETA_MIB_RX_FRAMEMAX_OCT_IDX, 252 MVNETA_MIB_TX_GOOD_OCT_IDX, 253 MVNETA_MIB_TX_GOOD_FRAME_IDX, 254 MVNETA_MIB_TX_EXCES_COL_IDX, 255 MVNETA_MIB_TX_MCAST_FRAME_IDX, 256 MVNETA_MIB_TX_BCAST_FRAME_IDX, 257 MVNETA_MIB_TX_MAC_CTL_ERR_IDX, 258 MVNETA_MIB_FC_SENT_IDX, 259 MVNETA_MIB_FC_GOOD_IDX, 260 MVNETA_MIB_FC_BAD_IDX, 261 MVNETA_MIB_PKT_UNDERSIZE_IDX, 262 MVNETA_MIB_PKT_FRAGMENT_IDX, 263 MVNETA_MIB_PKT_OVERSIZE_IDX, 264 MVNETA_MIB_PKT_JABBER_IDX, 265 MVNETA_MIB_MAC_RX_ERR_IDX, 266 MVNETA_MIB_MAC_CRC_ERR_IDX, 267 MVNETA_MIB_MAC_COL_IDX, 268 MVNETA_MIB_MAC_LATE_COL_IDX, 269 }; 270 271 STATIC struct mvneta_mib_def { 272 uint32_t regnum; 273 int reg64; 274 const char *sysctl_name; 275 const char *desc; 276 } mvneta_mib_list[] = { 277 [MVNETA_MIB_RX_GOOD_OCT_IDX] = {MVNETA_MIB_RX_GOOD_OCT, 1, 278 "rx_good_oct", "Good Octets Rx"}, 279 [MVNETA_MIB_RX_BAD_OCT_IDX] = {MVNETA_MIB_RX_BAD_OCT, 0, 280 "rx_bad_oct", "Bad Octets Rx"}, 281 [MVNETA_MIB_TX_MAC_TRNS_ERR_IDX] = {MVNETA_MIB_TX_MAC_TRNS_ERR, 0, 282 "tx_mac_err", "MAC Transmit Error"}, 283 [MVNETA_MIB_RX_GOOD_FRAME_IDX] = {MVNETA_MIB_RX_GOOD_FRAME, 0, 284 "rx_good_frame", "Good Frames Rx"}, 285 [MVNETA_MIB_RX_BAD_FRAME_IDX] = {MVNETA_MIB_RX_BAD_FRAME, 0, 286 "rx_bad_frame", "Bad Frames Rx"}, 287 [MVNETA_MIB_RX_BCAST_FRAME_IDX] = {MVNETA_MIB_RX_BCAST_FRAME, 0, 288 "rx_bcast_frame", "Broadcast Frames Rx"}, 289 [MVNETA_MIB_RX_MCAST_FRAME_IDX] = {MVNETA_MIB_RX_MCAST_FRAME, 0, 290 "rx_mcast_frame", "Multicast Frames Rx"}, 291 [MVNETA_MIB_RX_FRAME64_OCT_IDX] = {MVNETA_MIB_RX_FRAME64_OCT, 0, 292 "rx_frame_1_64", "Frame Size 1 - 64"}, 293 [MVNETA_MIB_RX_FRAME127_OCT_IDX] = {MVNETA_MIB_RX_FRAME127_OCT, 0, 294 "rx_frame_65_127", "Frame Size 65 - 127"}, 295 [MVNETA_MIB_RX_FRAME255_OCT_IDX] = {MVNETA_MIB_RX_FRAME255_OCT, 0, 296 "rx_frame_128_255", "Frame Size 128 - 255"}, 297 [MVNETA_MIB_RX_FRAME511_OCT_IDX] = {MVNETA_MIB_RX_FRAME511_OCT, 0, 298 "rx_frame_256_511", "Frame Size 256 - 511"}, 299 [MVNETA_MIB_RX_FRAME1023_OCT_IDX] = {MVNETA_MIB_RX_FRAME1023_OCT, 0, 300 "rx_frame_512_1023", "Frame Size 512 - 1023"}, 301 [MVNETA_MIB_RX_FRAMEMAX_OCT_IDX] = {MVNETA_MIB_RX_FRAMEMAX_OCT, 0, 302 "rx_fame_1024_max", "Frame Size 1024 - Max"}, 303 [MVNETA_MIB_TX_GOOD_OCT_IDX] = {MVNETA_MIB_TX_GOOD_OCT, 1, 304 "tx_good_oct", "Good Octets Tx"}, 305 [MVNETA_MIB_TX_GOOD_FRAME_IDX] = {MVNETA_MIB_TX_GOOD_FRAME, 0, 306 "tx_good_frame", "Good Frames Tx"}, 307 [MVNETA_MIB_TX_EXCES_COL_IDX] = {MVNETA_MIB_TX_EXCES_COL, 0, 308 "tx_exces_collision", "Excessive Collision"}, 309 [MVNETA_MIB_TX_MCAST_FRAME_IDX] = {MVNETA_MIB_TX_MCAST_FRAME, 0, 310 "tx_mcast_frame", "Multicast Frames Tx"}, 311 [MVNETA_MIB_TX_BCAST_FRAME_IDX] = {MVNETA_MIB_TX_BCAST_FRAME, 0, 312 "tx_bcast_frame", "Broadcast Frames Tx"}, 313 [MVNETA_MIB_TX_MAC_CTL_ERR_IDX] = {MVNETA_MIB_TX_MAC_CTL_ERR, 0, 314 "tx_mac_ctl_err", "Unknown MAC Control"}, 315 [MVNETA_MIB_FC_SENT_IDX] = {MVNETA_MIB_FC_SENT, 0, 316 "fc_tx", "Flow Control Tx"}, 317 [MVNETA_MIB_FC_GOOD_IDX] = {MVNETA_MIB_FC_GOOD, 0, 318 "fc_rx_good", "Good Flow Control Rx"}, 319 [MVNETA_MIB_FC_BAD_IDX] = {MVNETA_MIB_FC_BAD, 0, 320 "fc_rx_bad", "Bad Flow Control Rx"}, 321 [MVNETA_MIB_PKT_UNDERSIZE_IDX] = {MVNETA_MIB_PKT_UNDERSIZE, 0, 322 "pkt_undersize", "Undersized Packets Rx"}, 323 [MVNETA_MIB_PKT_FRAGMENT_IDX] = {MVNETA_MIB_PKT_FRAGMENT, 0, 324 "pkt_fragment", "Fragmented Packets Rx"}, 325 [MVNETA_MIB_PKT_OVERSIZE_IDX] = {MVNETA_MIB_PKT_OVERSIZE, 0, 326 "pkt_oversize", "Oversized Packets Rx"}, 327 [MVNETA_MIB_PKT_JABBER_IDX] = {MVNETA_MIB_PKT_JABBER, 0, 328 "pkt_jabber", "Jabber Packets Rx"}, 329 [MVNETA_MIB_MAC_RX_ERR_IDX] = {MVNETA_MIB_MAC_RX_ERR, 0, 330 "mac_rx_err", "MAC Rx Errors"}, 331 [MVNETA_MIB_MAC_CRC_ERR_IDX] = {MVNETA_MIB_MAC_CRC_ERR, 0, 332 "mac_crc_err", "MAC CRC Errors"}, 333 [MVNETA_MIB_MAC_COL_IDX] = {MVNETA_MIB_MAC_COL, 0, 334 "mac_collision", "MAC Collision"}, 335 [MVNETA_MIB_MAC_LATE_COL_IDX] = {MVNETA_MIB_MAC_LATE_COL, 0, 336 "mac_late_collision", "MAC Late Collision"}, 337 }; 338 339 static struct resource_spec res_spec[] = { 340 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 341 { SYS_RES_IRQ, 0, RF_ACTIVE }, 342 { -1, 0} 343 }; 344 345 static struct { 346 driver_intr_t *handler; 347 char * description; 348 } mvneta_intrs[] = { 349 { mvneta_rxtxth_intr, "MVNETA aggregated interrupt" }, 350 }; 351 352 STATIC uint32_t 353 mvneta_get_clk() 354 { 355 #if defined(__aarch64__) 356 return (A3700_TCLK_250MHZ); 357 #else 358 return (get_tclk()); 359 #endif 360 } 361 362 static int 363 mvneta_set_mac_address(struct mvneta_softc *sc, uint8_t *addr) 364 { 365 unsigned int mac_h; 366 unsigned int mac_l; 367 368 mac_l = (addr[4] << 8) | (addr[5]); 369 mac_h = (addr[0] << 24) | (addr[1] << 16) | 370 (addr[2] << 8) | (addr[3] << 0); 371 372 MVNETA_WRITE(sc, MVNETA_MACAL, mac_l); 373 MVNETA_WRITE(sc, MVNETA_MACAH, mac_h); 374 return (0); 375 } 376 377 static int 378 mvneta_get_mac_address(struct mvneta_softc *sc, uint8_t *addr) 379 { 380 uint32_t mac_l, mac_h; 381 382 #ifdef FDT 383 if (mvneta_fdt_mac_address(sc, addr) == 0) 384 return (0); 385 #endif 386 /* 387 * Fall back -- use the currently programmed address. 388 */ 389 mac_l = MVNETA_READ(sc, MVNETA_MACAL); 390 mac_h = MVNETA_READ(sc, MVNETA_MACAH); 391 if (mac_l == 0 && mac_h == 0) { 392 /* 393 * Generate pseudo-random MAC. 394 * Set lower part to random number | unit number. 395 */ 396 mac_l = arc4random() & ~0xff; 397 mac_l |= device_get_unit(sc->dev) & 0xff; 398 mac_h = arc4random(); 399 mac_h &= ~(3 << 24); /* Clear multicast and LAA bits */ 400 if (bootverbose) { 401 device_printf(sc->dev, 402 "Could not acquire MAC address. " 403 "Using randomized one.\n"); 404 } 405 } 406 407 addr[0] = (mac_h & 0xff000000) >> 24; 408 addr[1] = (mac_h & 0x00ff0000) >> 16; 409 addr[2] = (mac_h & 0x0000ff00) >> 8; 410 addr[3] = (mac_h & 0x000000ff); 411 addr[4] = (mac_l & 0x0000ff00) >> 8; 412 addr[5] = (mac_l & 0x000000ff); 413 return (0); 414 } 415 416 STATIC boolean_t 417 mvneta_find_ethernet_prop_switch(phandle_t ethernet, phandle_t node) 418 { 419 boolean_t ret; 420 phandle_t child, switch_eth_handle, switch_eth; 421 422 for (child = OF_child(node); child != 0; child = OF_peer(child)) { 423 if (OF_getencprop(child, "ethernet", (void*)&switch_eth_handle, 424 sizeof(switch_eth_handle)) > 0) { 425 if (switch_eth_handle > 0) { 426 switch_eth = OF_node_from_xref( 427 switch_eth_handle); 428 429 if (switch_eth == ethernet) 430 return (true); 431 } 432 } 433 434 ret = mvneta_find_ethernet_prop_switch(ethernet, child); 435 if (ret != 0) 436 return (ret); 437 } 438 439 return (false); 440 } 441 442 STATIC boolean_t 443 mvneta_has_switch(device_t self) 444 { 445 phandle_t node; 446 447 node = ofw_bus_get_node(self); 448 449 return mvneta_find_ethernet_prop_switch(node, OF_finddevice("/")); 450 } 451 452 STATIC int 453 mvneta_dma_create(struct mvneta_softc *sc) 454 { 455 size_t maxsize, maxsegsz; 456 size_t q; 457 int error; 458 459 /* 460 * Create Tx DMA 461 */ 462 maxsize = maxsegsz = sizeof(struct mvneta_tx_desc) * MVNETA_TX_RING_CNT; 463 464 error = bus_dma_tag_create( 465 bus_get_dma_tag(sc->dev), /* parent */ 466 16, 0, /* alignment, boundary */ 467 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 468 BUS_SPACE_MAXADDR, /* highaddr */ 469 NULL, NULL, /* filtfunc, filtfuncarg */ 470 maxsize, /* maxsize */ 471 1, /* nsegments */ 472 maxsegsz, /* maxsegsz */ 473 0, /* flags */ 474 NULL, NULL, /* lockfunc, lockfuncarg */ 475 &sc->tx_dtag); /* dmat */ 476 if (error != 0) { 477 device_printf(sc->dev, 478 "Failed to create DMA tag for Tx descriptors.\n"); 479 goto fail; 480 } 481 error = bus_dma_tag_create( 482 bus_get_dma_tag(sc->dev), /* parent */ 483 1, 0, /* alignment, boundary */ 484 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 485 BUS_SPACE_MAXADDR, /* highaddr */ 486 NULL, NULL, /* filtfunc, filtfuncarg */ 487 MVNETA_MAX_FRAME, /* maxsize */ 488 MVNETA_TX_SEGLIMIT, /* nsegments */ 489 MVNETA_MAX_FRAME, /* maxsegsz */ 490 BUS_DMA_ALLOCNOW, /* flags */ 491 NULL, NULL, /* lockfunc, lockfuncarg */ 492 &sc->txmbuf_dtag); 493 if (error != 0) { 494 device_printf(sc->dev, 495 "Failed to create DMA tag for Tx mbufs.\n"); 496 goto fail; 497 } 498 499 for (q = 0; q < MVNETA_TX_QNUM_MAX; q++) { 500 error = mvneta_ring_alloc_tx_queue(sc, q); 501 if (error != 0) { 502 device_printf(sc->dev, 503 "Failed to allocate DMA safe memory for TxQ: %zu\n", q); 504 goto fail; 505 } 506 } 507 508 /* 509 * Create Rx DMA. 510 */ 511 /* Create tag for Rx descripors */ 512 error = bus_dma_tag_create( 513 bus_get_dma_tag(sc->dev), /* parent */ 514 32, 0, /* alignment, boundary */ 515 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 516 BUS_SPACE_MAXADDR, /* highaddr */ 517 NULL, NULL, /* filtfunc, filtfuncarg */ 518 sizeof(struct mvneta_rx_desc) * MVNETA_RX_RING_CNT, /* maxsize */ 519 1, /* nsegments */ 520 sizeof(struct mvneta_rx_desc) * MVNETA_RX_RING_CNT, /* maxsegsz */ 521 0, /* flags */ 522 NULL, NULL, /* lockfunc, lockfuncarg */ 523 &sc->rx_dtag); /* dmat */ 524 if (error != 0) { 525 device_printf(sc->dev, 526 "Failed to create DMA tag for Rx descriptors.\n"); 527 goto fail; 528 } 529 530 /* Create tag for Rx buffers */ 531 error = bus_dma_tag_create( 532 bus_get_dma_tag(sc->dev), /* parent */ 533 32, 0, /* alignment, boundary */ 534 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 535 BUS_SPACE_MAXADDR, /* highaddr */ 536 NULL, NULL, /* filtfunc, filtfuncarg */ 537 MVNETA_MAX_FRAME, 1, /* maxsize, nsegments */ 538 MVNETA_MAX_FRAME, /* maxsegsz */ 539 0, /* flags */ 540 NULL, NULL, /* lockfunc, lockfuncarg */ 541 &sc->rxbuf_dtag); /* dmat */ 542 if (error != 0) { 543 device_printf(sc->dev, 544 "Failed to create DMA tag for Rx buffers.\n"); 545 goto fail; 546 } 547 548 for (q = 0; q < MVNETA_RX_QNUM_MAX; q++) { 549 if (mvneta_ring_alloc_rx_queue(sc, q) != 0) { 550 device_printf(sc->dev, 551 "Failed to allocate DMA safe memory for RxQ: %zu\n", q); 552 goto fail; 553 } 554 } 555 556 return (0); 557 fail: 558 mvneta_detach(sc->dev); 559 560 return (error); 561 } 562 563 /* ARGSUSED */ 564 int 565 mvneta_attach(device_t self) 566 { 567 struct mvneta_softc *sc; 568 struct ifnet *ifp; 569 device_t child; 570 int ifm_target; 571 int q, error; 572 #if !defined(__aarch64__) 573 uint32_t reg; 574 #endif 575 576 sc = device_get_softc(self); 577 sc->dev = self; 578 579 mtx_init(&sc->mtx, "mvneta_sc", NULL, MTX_DEF); 580 581 error = bus_alloc_resources(self, res_spec, sc->res); 582 if (error) { 583 device_printf(self, "could not allocate resources\n"); 584 return (ENXIO); 585 } 586 587 sc->version = MVNETA_READ(sc, MVNETA_PV); 588 device_printf(self, "version is %x\n", sc->version); 589 callout_init(&sc->tick_ch, 0); 590 591 /* 592 * make sure DMA engines are in reset state 593 */ 594 MVNETA_WRITE(sc, MVNETA_PRXINIT, 0x00000001); 595 MVNETA_WRITE(sc, MVNETA_PTXINIT, 0x00000001); 596 597 #if !defined(__aarch64__) 598 /* 599 * Disable port snoop for buffers and descriptors 600 * to avoid L2 caching of both without DRAM copy. 601 * Obtain coherency settings from the first MBUS 602 * window attribute. 603 */ 604 if ((MVNETA_READ(sc, MV_WIN_NETA_BASE(0)) & IO_WIN_COH_ATTR_MASK) == 0) { 605 reg = MVNETA_READ(sc, MVNETA_PSNPCFG); 606 reg &= ~MVNETA_PSNPCFG_DESCSNP_MASK; 607 reg &= ~MVNETA_PSNPCFG_BUFSNP_MASK; 608 MVNETA_WRITE(sc, MVNETA_PSNPCFG, reg); 609 } 610 #endif 611 612 /* 613 * MAC address 614 */ 615 if (mvneta_get_mac_address(sc, sc->enaddr)) { 616 device_printf(self, "no mac address.\n"); 617 return (ENXIO); 618 } 619 mvneta_set_mac_address(sc, sc->enaddr); 620 621 mvneta_disable_intr(sc); 622 623 /* Allocate network interface */ 624 ifp = sc->ifp = if_alloc(IFT_ETHER); 625 if (ifp == NULL) { 626 device_printf(self, "if_alloc() failed\n"); 627 mvneta_detach(self); 628 return (ENOMEM); 629 } 630 if_initname(ifp, device_get_name(self), device_get_unit(self)); 631 632 /* 633 * We can support 802.1Q VLAN-sized frames and jumbo 634 * Ethernet frames. 635 */ 636 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_JUMBO_MTU; 637 638 ifp->if_softc = sc; 639 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 640 #ifdef MVNETA_MULTIQUEUE 641 ifp->if_transmit = mvneta_transmit; 642 ifp->if_qflush = mvneta_qflush; 643 #else /* !MVNETA_MULTIQUEUE */ 644 ifp->if_start = mvneta_start; 645 ifp->if_snd.ifq_drv_maxlen = MVNETA_TX_RING_CNT - 1; 646 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 647 IFQ_SET_READY(&ifp->if_snd); 648 #endif 649 ifp->if_init = mvneta_init; 650 ifp->if_ioctl = mvneta_ioctl; 651 652 /* 653 * We can do IPv4/TCPv4/UDPv4/TCPv6/UDPv6 checksums in hardware. 654 */ 655 ifp->if_capabilities |= IFCAP_HWCSUM; 656 657 /* 658 * As VLAN hardware tagging is not supported 659 * but is necessary to perform VLAN hardware checksums, 660 * it is done in the driver 661 */ 662 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWCSUM; 663 664 /* 665 * Currently IPv6 HW checksum is broken, so make sure it is disabled. 666 */ 667 ifp->if_capabilities &= ~IFCAP_HWCSUM_IPV6; 668 ifp->if_capenable = ifp->if_capabilities; 669 670 /* 671 * Disabled option(s): 672 * - Support for Large Receive Offload 673 */ 674 ifp->if_capabilities |= IFCAP_LRO; 675 676 ifp->if_hwassist = CSUM_IP | CSUM_TCP | CSUM_UDP; 677 678 sc->rx_frame_size = MCLBYTES; /* ether_ifattach() always sets normal mtu */ 679 680 /* 681 * Device DMA Buffer allocation. 682 * Handles resource deallocation in case of failure. 683 */ 684 error = mvneta_dma_create(sc); 685 if (error != 0) { 686 mvneta_detach(self); 687 return (error); 688 } 689 690 /* Initialize queues */ 691 for (q = 0; q < MVNETA_TX_QNUM_MAX; q++) { 692 error = mvneta_ring_init_tx_queue(sc, q); 693 if (error != 0) { 694 mvneta_detach(self); 695 return (error); 696 } 697 } 698 699 for (q = 0; q < MVNETA_RX_QNUM_MAX; q++) { 700 error = mvneta_ring_init_rx_queue(sc, q); 701 if (error != 0) { 702 mvneta_detach(self); 703 return (error); 704 } 705 } 706 707 ether_ifattach(ifp, sc->enaddr); 708 709 /* 710 * Enable DMA engines and Initialize Device Registers. 711 */ 712 MVNETA_WRITE(sc, MVNETA_PRXINIT, 0x00000000); 713 MVNETA_WRITE(sc, MVNETA_PTXINIT, 0x00000000); 714 MVNETA_WRITE(sc, MVNETA_PACC, MVNETA_PACC_ACCELERATIONMODE_EDM); 715 mvneta_sc_lock(sc); 716 mvneta_filter_setup(sc); 717 mvneta_sc_unlock(sc); 718 mvneta_initreg(ifp); 719 720 /* 721 * Now MAC is working, setup MII. 722 */ 723 if (mii_init == 0) { 724 /* 725 * MII bus is shared by all MACs and all PHYs in SoC. 726 * serializing the bus access should be safe. 727 */ 728 mtx_init(&mii_mutex, "mvneta_mii", NULL, MTX_DEF); 729 mii_init = 1; 730 } 731 732 /* Attach PHY(s) */ 733 if ((sc->phy_addr != MII_PHY_ANY) && (!sc->use_inband_status)) { 734 error = mii_attach(self, &sc->miibus, ifp, mvneta_mediachange, 735 mvneta_mediastatus, BMSR_DEFCAPMASK, sc->phy_addr, 736 MII_OFFSET_ANY, 0); 737 if (error != 0) { 738 if (bootverbose) { 739 device_printf(self, 740 "MII attach failed, error: %d\n", error); 741 } 742 ether_ifdetach(sc->ifp); 743 mvneta_detach(self); 744 return (error); 745 } 746 sc->mii = device_get_softc(sc->miibus); 747 sc->phy_attached = 1; 748 749 /* Disable auto-negotiation in MAC - rely on PHY layer */ 750 mvneta_update_autoneg(sc, FALSE); 751 } else if (sc->use_inband_status == TRUE) { 752 /* In-band link status */ 753 ifmedia_init(&sc->mvneta_ifmedia, 0, mvneta_mediachange, 754 mvneta_mediastatus); 755 756 /* Configure media */ 757 ifmedia_add(&sc->mvneta_ifmedia, IFM_ETHER | IFM_1000_T | IFM_FDX, 758 0, NULL); 759 ifmedia_add(&sc->mvneta_ifmedia, IFM_ETHER | IFM_100_TX, 0, NULL); 760 ifmedia_add(&sc->mvneta_ifmedia, IFM_ETHER | IFM_100_TX | IFM_FDX, 761 0, NULL); 762 ifmedia_add(&sc->mvneta_ifmedia, IFM_ETHER | IFM_10_T, 0, NULL); 763 ifmedia_add(&sc->mvneta_ifmedia, IFM_ETHER | IFM_10_T | IFM_FDX, 764 0, NULL); 765 ifmedia_add(&sc->mvneta_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 766 ifmedia_set(&sc->mvneta_ifmedia, IFM_ETHER | IFM_AUTO); 767 768 /* Enable auto-negotiation */ 769 mvneta_update_autoneg(sc, TRUE); 770 771 mvneta_sc_lock(sc); 772 if (MVNETA_IS_LINKUP(sc)) 773 mvneta_linkup(sc); 774 else 775 mvneta_linkdown(sc); 776 mvneta_sc_unlock(sc); 777 778 } else { 779 /* Fixed-link, use predefined values */ 780 mvneta_update_autoneg(sc, FALSE); 781 ifmedia_init(&sc->mvneta_ifmedia, 0, mvneta_mediachange, 782 mvneta_mediastatus); 783 784 ifm_target = IFM_ETHER; 785 switch (sc->phy_speed) { 786 case 2500: 787 if (sc->phy_mode != MVNETA_PHY_SGMII && 788 sc->phy_mode != MVNETA_PHY_QSGMII) { 789 device_printf(self, 790 "2.5G speed can work only in (Q)SGMII mode\n"); 791 ether_ifdetach(sc->ifp); 792 mvneta_detach(self); 793 return (ENXIO); 794 } 795 ifm_target |= IFM_2500_T; 796 break; 797 case 1000: 798 ifm_target |= IFM_1000_T; 799 break; 800 case 100: 801 ifm_target |= IFM_100_TX; 802 break; 803 case 10: 804 ifm_target |= IFM_10_T; 805 break; 806 default: 807 ether_ifdetach(sc->ifp); 808 mvneta_detach(self); 809 return (ENXIO); 810 } 811 812 if (sc->phy_fdx) 813 ifm_target |= IFM_FDX; 814 else 815 ifm_target |= IFM_HDX; 816 817 ifmedia_add(&sc->mvneta_ifmedia, ifm_target, 0, NULL); 818 ifmedia_set(&sc->mvneta_ifmedia, ifm_target); 819 if_link_state_change(sc->ifp, LINK_STATE_UP); 820 821 if (mvneta_has_switch(self)) { 822 if (bootverbose) 823 device_printf(self, "This device is attached to a switch\n"); 824 child = device_add_child(sc->dev, "mdio", -1); 825 if (child == NULL) { 826 ether_ifdetach(sc->ifp); 827 mvneta_detach(self); 828 return (ENXIO); 829 } 830 bus_generic_attach(sc->dev); 831 bus_generic_attach(child); 832 } 833 834 /* Configure MAC media */ 835 mvneta_update_media(sc, ifm_target); 836 } 837 838 sysctl_mvneta_init(sc); 839 840 callout_reset(&sc->tick_ch, 0, mvneta_tick, sc); 841 842 error = bus_setup_intr(self, sc->res[1], 843 INTR_TYPE_NET | INTR_MPSAFE, NULL, mvneta_intrs[0].handler, sc, 844 &sc->ih_cookie[0]); 845 if (error) { 846 device_printf(self, "could not setup %s\n", 847 mvneta_intrs[0].description); 848 ether_ifdetach(sc->ifp); 849 mvneta_detach(self); 850 return (error); 851 } 852 853 return (0); 854 } 855 856 STATIC int 857 mvneta_detach(device_t dev) 858 { 859 struct mvneta_softc *sc; 860 int q; 861 862 sc = device_get_softc(dev); 863 864 mvneta_stop(sc); 865 /* Detach network interface */ 866 if (sc->ifp) 867 if_free(sc->ifp); 868 869 for (q = 0; q < MVNETA_RX_QNUM_MAX; q++) 870 mvneta_ring_dealloc_rx_queue(sc, q); 871 for (q = 0; q < MVNETA_TX_QNUM_MAX; q++) 872 mvneta_ring_dealloc_tx_queue(sc, q); 873 874 if (sc->tx_dtag != NULL) 875 bus_dma_tag_destroy(sc->tx_dtag); 876 if (sc->rx_dtag != NULL) 877 bus_dma_tag_destroy(sc->rx_dtag); 878 if (sc->txmbuf_dtag != NULL) 879 bus_dma_tag_destroy(sc->txmbuf_dtag); 880 if (sc->rxbuf_dtag != NULL) 881 bus_dma_tag_destroy(sc->rxbuf_dtag); 882 883 bus_release_resources(dev, res_spec, sc->res); 884 return (0); 885 } 886 887 /* 888 * MII 889 */ 890 STATIC int 891 mvneta_miibus_readreg(device_t dev, int phy, int reg) 892 { 893 struct mvneta_softc *sc; 894 struct ifnet *ifp; 895 uint32_t smi, val; 896 int i; 897 898 sc = device_get_softc(dev); 899 ifp = sc->ifp; 900 901 mtx_lock(&mii_mutex); 902 903 for (i = 0; i < MVNETA_PHY_TIMEOUT; i++) { 904 if ((MVNETA_READ(sc, MVNETA_SMI) & MVNETA_SMI_BUSY) == 0) 905 break; 906 DELAY(1); 907 } 908 if (i == MVNETA_PHY_TIMEOUT) { 909 if_printf(ifp, "SMI busy timeout\n"); 910 mtx_unlock(&mii_mutex); 911 return (-1); 912 } 913 914 smi = MVNETA_SMI_PHYAD(phy) | 915 MVNETA_SMI_REGAD(reg) | MVNETA_SMI_OPCODE_READ; 916 MVNETA_WRITE(sc, MVNETA_SMI, smi); 917 918 for (i = 0; i < MVNETA_PHY_TIMEOUT; i++) { 919 if ((MVNETA_READ(sc, MVNETA_SMI) & MVNETA_SMI_BUSY) == 0) 920 break; 921 DELAY(1); 922 } 923 924 if (i == MVNETA_PHY_TIMEOUT) { 925 if_printf(ifp, "SMI busy timeout\n"); 926 mtx_unlock(&mii_mutex); 927 return (-1); 928 } 929 for (i = 0; i < MVNETA_PHY_TIMEOUT; i++) { 930 smi = MVNETA_READ(sc, MVNETA_SMI); 931 if (smi & MVNETA_SMI_READVALID) 932 break; 933 DELAY(1); 934 } 935 936 if (i == MVNETA_PHY_TIMEOUT) { 937 if_printf(ifp, "SMI busy timeout\n"); 938 mtx_unlock(&mii_mutex); 939 return (-1); 940 } 941 942 mtx_unlock(&mii_mutex); 943 944 #ifdef MVNETA_KTR 945 CTR3(KTR_SPARE2, "%s i=%d, timeout=%d\n", ifp->if_xname, i, 946 MVNETA_PHY_TIMEOUT); 947 #endif 948 949 val = smi & MVNETA_SMI_DATA_MASK; 950 951 #ifdef MVNETA_KTR 952 CTR4(KTR_SPARE2, "%s phy=%d, reg=%#x, val=%#x\n", ifp->if_xname, phy, 953 reg, val); 954 #endif 955 return (val); 956 } 957 958 STATIC int 959 mvneta_miibus_writereg(device_t dev, int phy, int reg, int val) 960 { 961 struct mvneta_softc *sc; 962 struct ifnet *ifp; 963 uint32_t smi; 964 int i; 965 966 sc = device_get_softc(dev); 967 ifp = sc->ifp; 968 #ifdef MVNETA_KTR 969 CTR4(KTR_SPARE2, "%s phy=%d, reg=%#x, val=%#x\n", ifp->if_xname, 970 phy, reg, val); 971 #endif 972 973 mtx_lock(&mii_mutex); 974 975 for (i = 0; i < MVNETA_PHY_TIMEOUT; i++) { 976 if ((MVNETA_READ(sc, MVNETA_SMI) & MVNETA_SMI_BUSY) == 0) 977 break; 978 DELAY(1); 979 } 980 if (i == MVNETA_PHY_TIMEOUT) { 981 if_printf(ifp, "SMI busy timeout\n"); 982 mtx_unlock(&mii_mutex); 983 return (0); 984 } 985 986 smi = MVNETA_SMI_PHYAD(phy) | MVNETA_SMI_REGAD(reg) | 987 MVNETA_SMI_OPCODE_WRITE | (val & MVNETA_SMI_DATA_MASK); 988 MVNETA_WRITE(sc, MVNETA_SMI, smi); 989 990 for (i = 0; i < MVNETA_PHY_TIMEOUT; i++) { 991 if ((MVNETA_READ(sc, MVNETA_SMI) & MVNETA_SMI_BUSY) == 0) 992 break; 993 DELAY(1); 994 } 995 996 mtx_unlock(&mii_mutex); 997 998 if (i == MVNETA_PHY_TIMEOUT) 999 if_printf(ifp, "phy write timed out\n"); 1000 1001 return (0); 1002 } 1003 1004 STATIC void 1005 mvneta_portup(struct mvneta_softc *sc) 1006 { 1007 int q; 1008 1009 for (q = 0; q < MVNETA_RX_QNUM_MAX; q++) { 1010 mvneta_rx_lockq(sc, q); 1011 mvneta_rx_queue_enable(sc->ifp, q); 1012 mvneta_rx_unlockq(sc, q); 1013 } 1014 1015 for (q = 0; q < MVNETA_TX_QNUM_MAX; q++) { 1016 mvneta_tx_lockq(sc, q); 1017 mvneta_tx_queue_enable(sc->ifp, q); 1018 mvneta_tx_unlockq(sc, q); 1019 } 1020 1021 } 1022 1023 STATIC void 1024 mvneta_portdown(struct mvneta_softc *sc) 1025 { 1026 struct mvneta_rx_ring *rx; 1027 struct mvneta_tx_ring *tx; 1028 int q, cnt; 1029 uint32_t reg; 1030 1031 for (q = 0; q < MVNETA_RX_QNUM_MAX; q++) { 1032 rx = MVNETA_RX_RING(sc, q); 1033 mvneta_rx_lockq(sc, q); 1034 rx->queue_status = MVNETA_QUEUE_DISABLED; 1035 mvneta_rx_unlockq(sc, q); 1036 } 1037 1038 for (q = 0; q < MVNETA_TX_QNUM_MAX; q++) { 1039 tx = MVNETA_TX_RING(sc, q); 1040 mvneta_tx_lockq(sc, q); 1041 tx->queue_status = MVNETA_QUEUE_DISABLED; 1042 mvneta_tx_unlockq(sc, q); 1043 } 1044 1045 /* Wait for all Rx activity to terminate. */ 1046 reg = MVNETA_READ(sc, MVNETA_RQC) & MVNETA_RQC_EN_MASK; 1047 reg = MVNETA_RQC_DIS(reg); 1048 MVNETA_WRITE(sc, MVNETA_RQC, reg); 1049 cnt = 0; 1050 do { 1051 if (cnt >= RX_DISABLE_TIMEOUT) { 1052 if_printf(sc->ifp, 1053 "timeout for RX stopped. rqc 0x%x\n", reg); 1054 break; 1055 } 1056 cnt++; 1057 reg = MVNETA_READ(sc, MVNETA_RQC); 1058 } while ((reg & MVNETA_RQC_EN_MASK) != 0); 1059 1060 /* Wait for all Tx activity to terminate. */ 1061 reg = MVNETA_READ(sc, MVNETA_PIE); 1062 reg &= ~MVNETA_PIE_TXPKTINTRPTENB_MASK; 1063 MVNETA_WRITE(sc, MVNETA_PIE, reg); 1064 1065 reg = MVNETA_READ(sc, MVNETA_PRXTXTIM); 1066 reg &= ~MVNETA_PRXTXTI_TBTCQ_MASK; 1067 MVNETA_WRITE(sc, MVNETA_PRXTXTIM, reg); 1068 1069 reg = MVNETA_READ(sc, MVNETA_TQC) & MVNETA_TQC_EN_MASK; 1070 reg = MVNETA_TQC_DIS(reg); 1071 MVNETA_WRITE(sc, MVNETA_TQC, reg); 1072 cnt = 0; 1073 do { 1074 if (cnt >= TX_DISABLE_TIMEOUT) { 1075 if_printf(sc->ifp, 1076 "timeout for TX stopped. tqc 0x%x\n", reg); 1077 break; 1078 } 1079 cnt++; 1080 reg = MVNETA_READ(sc, MVNETA_TQC); 1081 } while ((reg & MVNETA_TQC_EN_MASK) != 0); 1082 1083 /* Wait for all Tx FIFO is empty */ 1084 cnt = 0; 1085 do { 1086 if (cnt >= TX_FIFO_EMPTY_TIMEOUT) { 1087 if_printf(sc->ifp, 1088 "timeout for TX FIFO drained. ps0 0x%x\n", reg); 1089 break; 1090 } 1091 cnt++; 1092 reg = MVNETA_READ(sc, MVNETA_PS0); 1093 } while (((reg & MVNETA_PS0_TXFIFOEMP) == 0) && 1094 ((reg & MVNETA_PS0_TXINPROG) != 0)); 1095 } 1096 1097 /* 1098 * Device Register Initialization 1099 * reset device registers to device driver default value. 1100 * the device is not enabled here. 1101 */ 1102 STATIC int 1103 mvneta_initreg(struct ifnet *ifp) 1104 { 1105 struct mvneta_softc *sc; 1106 int q; 1107 uint32_t reg; 1108 1109 sc = ifp->if_softc; 1110 #ifdef MVNETA_KTR 1111 CTR1(KTR_SPARE2, "%s initializing device register", ifp->if_xname); 1112 #endif 1113 1114 /* Disable Legacy WRR, Disable EJP, Release from reset. */ 1115 MVNETA_WRITE(sc, MVNETA_TQC_1, 0); 1116 /* Enable mbus retry. */ 1117 MVNETA_WRITE(sc, MVNETA_MBUS_CONF, MVNETA_MBUS_RETRY_EN); 1118 1119 /* Init TX/RX Queue Registers */ 1120 for (q = 0; q < MVNETA_RX_QNUM_MAX; q++) { 1121 mvneta_rx_lockq(sc, q); 1122 if (mvneta_rx_queue_init(ifp, q) != 0) { 1123 device_printf(sc->dev, 1124 "initialization failed: cannot initialize queue\n"); 1125 mvneta_rx_unlockq(sc, q); 1126 return (ENOBUFS); 1127 } 1128 mvneta_rx_unlockq(sc, q); 1129 } 1130 for (q = 0; q < MVNETA_TX_QNUM_MAX; q++) { 1131 mvneta_tx_lockq(sc, q); 1132 if (mvneta_tx_queue_init(ifp, q) != 0) { 1133 device_printf(sc->dev, 1134 "initialization failed: cannot initialize queue\n"); 1135 mvneta_tx_unlockq(sc, q); 1136 return (ENOBUFS); 1137 } 1138 mvneta_tx_unlockq(sc, q); 1139 } 1140 1141 /* 1142 * Ethernet Unit Control - disable automatic PHY management by HW. 1143 * In case the port uses SMI-controlled PHY, poll its status with 1144 * mii_tick() and update MAC settings accordingly. 1145 */ 1146 reg = MVNETA_READ(sc, MVNETA_EUC); 1147 reg &= ~MVNETA_EUC_POLLING; 1148 MVNETA_WRITE(sc, MVNETA_EUC, reg); 1149 1150 /* EEE: Low Power Idle */ 1151 reg = MVNETA_LPIC0_LILIMIT(MVNETA_LPI_LI); 1152 reg |= MVNETA_LPIC0_TSLIMIT(MVNETA_LPI_TS); 1153 MVNETA_WRITE(sc, MVNETA_LPIC0, reg); 1154 1155 reg = MVNETA_LPIC1_TWLIMIT(MVNETA_LPI_TW); 1156 MVNETA_WRITE(sc, MVNETA_LPIC1, reg); 1157 1158 reg = MVNETA_LPIC2_MUSTSET; 1159 MVNETA_WRITE(sc, MVNETA_LPIC2, reg); 1160 1161 /* Port MAC Control set 0 */ 1162 reg = MVNETA_PMACC0_MUSTSET; /* must write 0x1 */ 1163 reg &= ~MVNETA_PMACC0_PORTEN; /* port is still disabled */ 1164 reg |= MVNETA_PMACC0_FRAMESIZELIMIT(ifp->if_mtu + MVNETA_ETHER_SIZE); 1165 MVNETA_WRITE(sc, MVNETA_PMACC0, reg); 1166 1167 /* Port MAC Control set 2 */ 1168 reg = MVNETA_READ(sc, MVNETA_PMACC2); 1169 switch (sc->phy_mode) { 1170 case MVNETA_PHY_QSGMII: 1171 reg |= (MVNETA_PMACC2_PCSEN | MVNETA_PMACC2_RGMIIEN); 1172 MVNETA_WRITE(sc, MVNETA_PSERDESCFG, MVNETA_PSERDESCFG_QSGMII); 1173 break; 1174 case MVNETA_PHY_SGMII: 1175 reg |= (MVNETA_PMACC2_PCSEN | MVNETA_PMACC2_RGMIIEN); 1176 MVNETA_WRITE(sc, MVNETA_PSERDESCFG, MVNETA_PSERDESCFG_SGMII); 1177 break; 1178 case MVNETA_PHY_RGMII: 1179 case MVNETA_PHY_RGMII_ID: 1180 reg |= MVNETA_PMACC2_RGMIIEN; 1181 break; 1182 } 1183 reg |= MVNETA_PMACC2_MUSTSET; 1184 reg &= ~MVNETA_PMACC2_PORTMACRESET; 1185 MVNETA_WRITE(sc, MVNETA_PMACC2, reg); 1186 1187 /* Port Configuration Extended: enable Tx CRC generation */ 1188 reg = MVNETA_READ(sc, MVNETA_PXCX); 1189 reg &= ~MVNETA_PXCX_TXCRCDIS; 1190 MVNETA_WRITE(sc, MVNETA_PXCX, reg); 1191 1192 /* clear MIB counter registers(clear by read) */ 1193 mvneta_clear_mib(sc); 1194 1195 /* Set SDC register except IPGINT bits */ 1196 reg = MVNETA_SDC_RXBSZ_16_64BITWORDS; 1197 reg |= MVNETA_SDC_TXBSZ_16_64BITWORDS; 1198 reg |= MVNETA_SDC_BLMR; 1199 reg |= MVNETA_SDC_BLMT; 1200 MVNETA_WRITE(sc, MVNETA_SDC, reg); 1201 1202 return (0); 1203 } 1204 1205 STATIC void 1206 mvneta_dmamap_cb(void *arg, bus_dma_segment_t * segs, int nseg, int error) 1207 { 1208 1209 if (error != 0) 1210 return; 1211 *(bus_addr_t *)arg = segs->ds_addr; 1212 } 1213 1214 STATIC int 1215 mvneta_ring_alloc_rx_queue(struct mvneta_softc *sc, int q) 1216 { 1217 struct mvneta_rx_ring *rx; 1218 struct mvneta_buf *rxbuf; 1219 bus_dmamap_t dmap; 1220 int i, error; 1221 1222 if (q >= MVNETA_RX_QNUM_MAX) 1223 return (EINVAL); 1224 1225 rx = MVNETA_RX_RING(sc, q); 1226 mtx_init(&rx->ring_mtx, "mvneta_rx", NULL, MTX_DEF); 1227 /* Allocate DMA memory for Rx descriptors */ 1228 error = bus_dmamem_alloc(sc->rx_dtag, 1229 (void**)&(rx->desc), 1230 BUS_DMA_NOWAIT | BUS_DMA_ZERO, 1231 &rx->desc_map); 1232 if (error != 0 || rx->desc == NULL) 1233 goto fail; 1234 error = bus_dmamap_load(sc->rx_dtag, rx->desc_map, 1235 rx->desc, 1236 sizeof(struct mvneta_rx_desc) * MVNETA_RX_RING_CNT, 1237 mvneta_dmamap_cb, &rx->desc_pa, BUS_DMA_NOWAIT); 1238 if (error != 0) 1239 goto fail; 1240 1241 for (i = 0; i < MVNETA_RX_RING_CNT; i++) { 1242 error = bus_dmamap_create(sc->rxbuf_dtag, 0, &dmap); 1243 if (error != 0) { 1244 device_printf(sc->dev, 1245 "Failed to create DMA map for Rx buffer num: %d\n", i); 1246 goto fail; 1247 } 1248 rxbuf = &rx->rxbuf[i]; 1249 rxbuf->dmap = dmap; 1250 rxbuf->m = NULL; 1251 } 1252 1253 return (0); 1254 fail: 1255 mvneta_ring_dealloc_rx_queue(sc, q); 1256 device_printf(sc->dev, "DMA Ring buffer allocation failure.\n"); 1257 return (error); 1258 } 1259 1260 STATIC int 1261 mvneta_ring_alloc_tx_queue(struct mvneta_softc *sc, int q) 1262 { 1263 struct mvneta_tx_ring *tx; 1264 int error; 1265 1266 if (q >= MVNETA_TX_QNUM_MAX) 1267 return (EINVAL); 1268 tx = MVNETA_TX_RING(sc, q); 1269 mtx_init(&tx->ring_mtx, "mvneta_tx", NULL, MTX_DEF); 1270 error = bus_dmamem_alloc(sc->tx_dtag, 1271 (void**)&(tx->desc), 1272 BUS_DMA_NOWAIT | BUS_DMA_ZERO, 1273 &tx->desc_map); 1274 if (error != 0 || tx->desc == NULL) 1275 goto fail; 1276 error = bus_dmamap_load(sc->tx_dtag, tx->desc_map, 1277 tx->desc, 1278 sizeof(struct mvneta_tx_desc) * MVNETA_TX_RING_CNT, 1279 mvneta_dmamap_cb, &tx->desc_pa, BUS_DMA_NOWAIT); 1280 if (error != 0) 1281 goto fail; 1282 1283 #ifdef MVNETA_MULTIQUEUE 1284 tx->br = buf_ring_alloc(MVNETA_BUFRING_SIZE, M_DEVBUF, M_NOWAIT, 1285 &tx->ring_mtx); 1286 if (tx->br == NULL) { 1287 device_printf(sc->dev, 1288 "Could not setup buffer ring for TxQ(%d)\n", q); 1289 error = ENOMEM; 1290 goto fail; 1291 } 1292 #endif 1293 1294 return (0); 1295 fail: 1296 mvneta_ring_dealloc_tx_queue(sc, q); 1297 device_printf(sc->dev, "DMA Ring buffer allocation failure.\n"); 1298 return (error); 1299 } 1300 1301 STATIC void 1302 mvneta_ring_dealloc_tx_queue(struct mvneta_softc *sc, int q) 1303 { 1304 struct mvneta_tx_ring *tx; 1305 struct mvneta_buf *txbuf; 1306 void *kva; 1307 int error; 1308 int i; 1309 1310 if (q >= MVNETA_TX_QNUM_MAX) 1311 return; 1312 tx = MVNETA_TX_RING(sc, q); 1313 1314 if (tx->taskq != NULL) { 1315 /* Remove task */ 1316 while (taskqueue_cancel(tx->taskq, &tx->task, NULL) != 0) 1317 taskqueue_drain(tx->taskq, &tx->task); 1318 } 1319 #ifdef MVNETA_MULTIQUEUE 1320 if (tx->br != NULL) 1321 drbr_free(tx->br, M_DEVBUF); 1322 #endif 1323 1324 if (sc->txmbuf_dtag != NULL) { 1325 if (mtx_name(&tx->ring_mtx) != NULL) { 1326 /* 1327 * It is assumed that maps are being loaded after mutex 1328 * is initialized. Therefore we can skip unloading maps 1329 * when mutex is empty. 1330 */ 1331 mvneta_tx_lockq(sc, q); 1332 mvneta_ring_flush_tx_queue(sc, q); 1333 mvneta_tx_unlockq(sc, q); 1334 } 1335 for (i = 0; i < MVNETA_TX_RING_CNT; i++) { 1336 txbuf = &tx->txbuf[i]; 1337 if (txbuf->dmap != NULL) { 1338 error = bus_dmamap_destroy(sc->txmbuf_dtag, 1339 txbuf->dmap); 1340 if (error != 0) { 1341 panic("%s: map busy for Tx descriptor (Q%d, %d)", 1342 __func__, q, i); 1343 } 1344 } 1345 } 1346 } 1347 1348 if (tx->desc_pa != 0) 1349 bus_dmamap_unload(sc->tx_dtag, tx->desc_map); 1350 1351 kva = (void *)tx->desc; 1352 if (kva != NULL) 1353 bus_dmamem_free(sc->tx_dtag, tx->desc, tx->desc_map); 1354 1355 if (mtx_name(&tx->ring_mtx) != NULL) 1356 mtx_destroy(&tx->ring_mtx); 1357 1358 memset(tx, 0, sizeof(*tx)); 1359 } 1360 1361 STATIC void 1362 mvneta_ring_dealloc_rx_queue(struct mvneta_softc *sc, int q) 1363 { 1364 struct mvneta_rx_ring *rx; 1365 struct lro_ctrl *lro; 1366 void *kva; 1367 1368 if (q >= MVNETA_RX_QNUM_MAX) 1369 return; 1370 1371 rx = MVNETA_RX_RING(sc, q); 1372 1373 mvneta_ring_flush_rx_queue(sc, q); 1374 1375 if (rx->desc_pa != 0) 1376 bus_dmamap_unload(sc->rx_dtag, rx->desc_map); 1377 1378 kva = (void *)rx->desc; 1379 if (kva != NULL) 1380 bus_dmamem_free(sc->rx_dtag, rx->desc, rx->desc_map); 1381 1382 lro = &rx->lro; 1383 tcp_lro_free(lro); 1384 1385 if (mtx_name(&rx->ring_mtx) != NULL) 1386 mtx_destroy(&rx->ring_mtx); 1387 1388 memset(rx, 0, sizeof(*rx)); 1389 } 1390 1391 STATIC int 1392 mvneta_ring_init_rx_queue(struct mvneta_softc *sc, int q) 1393 { 1394 struct mvneta_rx_ring *rx; 1395 struct lro_ctrl *lro; 1396 int error; 1397 1398 if (q >= MVNETA_RX_QNUM_MAX) 1399 return (0); 1400 1401 rx = MVNETA_RX_RING(sc, q); 1402 rx->dma = rx->cpu = 0; 1403 rx->queue_th_received = MVNETA_RXTH_COUNT; 1404 rx->queue_th_time = (mvneta_get_clk() / 1000) / 10; /* 0.1 [ms] */ 1405 1406 /* Initialize LRO */ 1407 rx->lro_enabled = FALSE; 1408 if ((sc->ifp->if_capenable & IFCAP_LRO) != 0) { 1409 lro = &rx->lro; 1410 error = tcp_lro_init(lro); 1411 if (error != 0) 1412 device_printf(sc->dev, "LRO Initialization failed!\n"); 1413 else { 1414 rx->lro_enabled = TRUE; 1415 lro->ifp = sc->ifp; 1416 } 1417 } 1418 1419 return (0); 1420 } 1421 1422 STATIC int 1423 mvneta_ring_init_tx_queue(struct mvneta_softc *sc, int q) 1424 { 1425 struct mvneta_tx_ring *tx; 1426 struct mvneta_buf *txbuf; 1427 int i, error; 1428 1429 if (q >= MVNETA_TX_QNUM_MAX) 1430 return (0); 1431 1432 tx = MVNETA_TX_RING(sc, q); 1433 1434 /* Tx handle */ 1435 for (i = 0; i < MVNETA_TX_RING_CNT; i++) { 1436 txbuf = &tx->txbuf[i]; 1437 txbuf->m = NULL; 1438 /* Tx handle needs DMA map for busdma_load_mbuf() */ 1439 error = bus_dmamap_create(sc->txmbuf_dtag, 0, 1440 &txbuf->dmap); 1441 if (error != 0) { 1442 device_printf(sc->dev, 1443 "can't create dma map (tx ring %d)\n", i); 1444 return (error); 1445 } 1446 } 1447 tx->dma = tx->cpu = 0; 1448 tx->used = 0; 1449 tx->drv_error = 0; 1450 tx->queue_status = MVNETA_QUEUE_DISABLED; 1451 tx->queue_hung = FALSE; 1452 1453 tx->ifp = sc->ifp; 1454 tx->qidx = q; 1455 TASK_INIT(&tx->task, 0, mvneta_tx_task, tx); 1456 tx->taskq = taskqueue_create_fast("mvneta_tx_taskq", M_WAITOK, 1457 taskqueue_thread_enqueue, &tx->taskq); 1458 taskqueue_start_threads(&tx->taskq, 1, PI_NET, "%s: tx_taskq(%d)", 1459 device_get_nameunit(sc->dev), q); 1460 1461 return (0); 1462 } 1463 1464 STATIC void 1465 mvneta_ring_flush_tx_queue(struct mvneta_softc *sc, int q) 1466 { 1467 struct mvneta_tx_ring *tx; 1468 struct mvneta_buf *txbuf; 1469 int i; 1470 1471 tx = MVNETA_TX_RING(sc, q); 1472 KASSERT_TX_MTX(sc, q); 1473 1474 /* Tx handle */ 1475 for (i = 0; i < MVNETA_TX_RING_CNT; i++) { 1476 txbuf = &tx->txbuf[i]; 1477 bus_dmamap_unload(sc->txmbuf_dtag, txbuf->dmap); 1478 if (txbuf->m != NULL) { 1479 m_freem(txbuf->m); 1480 txbuf->m = NULL; 1481 } 1482 } 1483 tx->dma = tx->cpu = 0; 1484 tx->used = 0; 1485 } 1486 1487 STATIC void 1488 mvneta_ring_flush_rx_queue(struct mvneta_softc *sc, int q) 1489 { 1490 struct mvneta_rx_ring *rx; 1491 struct mvneta_buf *rxbuf; 1492 int i; 1493 1494 rx = MVNETA_RX_RING(sc, q); 1495 KASSERT_RX_MTX(sc, q); 1496 1497 /* Rx handle */ 1498 for (i = 0; i < MVNETA_RX_RING_CNT; i++) { 1499 rxbuf = &rx->rxbuf[i]; 1500 mvneta_rx_buf_free(sc, rxbuf); 1501 } 1502 rx->dma = rx->cpu = 0; 1503 } 1504 1505 /* 1506 * Rx/Tx Queue Control 1507 */ 1508 STATIC int 1509 mvneta_rx_queue_init(struct ifnet *ifp, int q) 1510 { 1511 struct mvneta_softc *sc; 1512 struct mvneta_rx_ring *rx; 1513 uint32_t reg; 1514 1515 sc = ifp->if_softc; 1516 KASSERT_RX_MTX(sc, q); 1517 rx = MVNETA_RX_RING(sc, q); 1518 DASSERT(rx->desc_pa != 0); 1519 1520 /* descriptor address */ 1521 MVNETA_WRITE(sc, MVNETA_PRXDQA(q), rx->desc_pa); 1522 1523 /* Rx buffer size and descriptor ring size */ 1524 reg = MVNETA_PRXDQS_BUFFERSIZE(sc->rx_frame_size >> 3); 1525 reg |= MVNETA_PRXDQS_DESCRIPTORSQUEUESIZE(MVNETA_RX_RING_CNT); 1526 MVNETA_WRITE(sc, MVNETA_PRXDQS(q), reg); 1527 #ifdef MVNETA_KTR 1528 CTR3(KTR_SPARE2, "%s PRXDQS(%d): %#x", ifp->if_xname, q, 1529 MVNETA_READ(sc, MVNETA_PRXDQS(q))); 1530 #endif 1531 /* Rx packet offset address */ 1532 reg = MVNETA_PRXC_PACKETOFFSET(MVNETA_PACKET_OFFSET >> 3); 1533 MVNETA_WRITE(sc, MVNETA_PRXC(q), reg); 1534 #ifdef MVNETA_KTR 1535 CTR3(KTR_SPARE2, "%s PRXC(%d): %#x", ifp->if_xname, q, 1536 MVNETA_READ(sc, MVNETA_PRXC(q))); 1537 #endif 1538 1539 /* if DMA is not working, register is not updated */ 1540 DASSERT(MVNETA_READ(sc, MVNETA_PRXDQA(q)) == rx->desc_pa); 1541 return (0); 1542 } 1543 1544 STATIC int 1545 mvneta_tx_queue_init(struct ifnet *ifp, int q) 1546 { 1547 struct mvneta_softc *sc; 1548 struct mvneta_tx_ring *tx; 1549 uint32_t reg; 1550 1551 sc = ifp->if_softc; 1552 KASSERT_TX_MTX(sc, q); 1553 tx = MVNETA_TX_RING(sc, q); 1554 DASSERT(tx->desc_pa != 0); 1555 1556 /* descriptor address */ 1557 MVNETA_WRITE(sc, MVNETA_PTXDQA(q), tx->desc_pa); 1558 1559 /* descriptor ring size */ 1560 reg = MVNETA_PTXDQS_DQS(MVNETA_TX_RING_CNT); 1561 MVNETA_WRITE(sc, MVNETA_PTXDQS(q), reg); 1562 1563 /* if DMA is not working, register is not updated */ 1564 DASSERT(MVNETA_READ(sc, MVNETA_PTXDQA(q)) == tx->desc_pa); 1565 return (0); 1566 } 1567 1568 STATIC int 1569 mvneta_rx_queue_enable(struct ifnet *ifp, int q) 1570 { 1571 struct mvneta_softc *sc; 1572 struct mvneta_rx_ring *rx; 1573 uint32_t reg; 1574 1575 sc = ifp->if_softc; 1576 rx = MVNETA_RX_RING(sc, q); 1577 KASSERT_RX_MTX(sc, q); 1578 1579 /* Set Rx interrupt threshold */ 1580 reg = MVNETA_PRXDQTH_ODT(rx->queue_th_received); 1581 MVNETA_WRITE(sc, MVNETA_PRXDQTH(q), reg); 1582 1583 reg = MVNETA_PRXITTH_RITT(rx->queue_th_time); 1584 MVNETA_WRITE(sc, MVNETA_PRXITTH(q), reg); 1585 1586 /* Unmask RXTX_TH Intr. */ 1587 reg = MVNETA_READ(sc, MVNETA_PRXTXTIM); 1588 reg |= MVNETA_PRXTXTI_RBICTAPQ(q); /* Rx Buffer Interrupt Coalese */ 1589 MVNETA_WRITE(sc, MVNETA_PRXTXTIM, reg); 1590 1591 /* Enable Rx queue */ 1592 reg = MVNETA_READ(sc, MVNETA_RQC) & MVNETA_RQC_EN_MASK; 1593 reg |= MVNETA_RQC_ENQ(q); 1594 MVNETA_WRITE(sc, MVNETA_RQC, reg); 1595 1596 rx->queue_status = MVNETA_QUEUE_WORKING; 1597 return (0); 1598 } 1599 1600 STATIC int 1601 mvneta_tx_queue_enable(struct ifnet *ifp, int q) 1602 { 1603 struct mvneta_softc *sc; 1604 struct mvneta_tx_ring *tx; 1605 1606 sc = ifp->if_softc; 1607 tx = MVNETA_TX_RING(sc, q); 1608 KASSERT_TX_MTX(sc, q); 1609 1610 /* Enable Tx queue */ 1611 MVNETA_WRITE(sc, MVNETA_TQC, MVNETA_TQC_ENQ(q)); 1612 1613 tx->queue_status = MVNETA_QUEUE_IDLE; 1614 tx->queue_hung = FALSE; 1615 return (0); 1616 } 1617 1618 STATIC __inline void 1619 mvneta_rx_lockq(struct mvneta_softc *sc, int q) 1620 { 1621 1622 DASSERT(q >= 0); 1623 DASSERT(q < MVNETA_RX_QNUM_MAX); 1624 mtx_lock(&sc->rx_ring[q].ring_mtx); 1625 } 1626 1627 STATIC __inline void 1628 mvneta_rx_unlockq(struct mvneta_softc *sc, int q) 1629 { 1630 1631 DASSERT(q >= 0); 1632 DASSERT(q < MVNETA_RX_QNUM_MAX); 1633 mtx_unlock(&sc->rx_ring[q].ring_mtx); 1634 } 1635 1636 STATIC __inline int __unused 1637 mvneta_tx_trylockq(struct mvneta_softc *sc, int q) 1638 { 1639 1640 DASSERT(q >= 0); 1641 DASSERT(q < MVNETA_TX_QNUM_MAX); 1642 return (mtx_trylock(&sc->tx_ring[q].ring_mtx)); 1643 } 1644 1645 STATIC __inline void 1646 mvneta_tx_lockq(struct mvneta_softc *sc, int q) 1647 { 1648 1649 DASSERT(q >= 0); 1650 DASSERT(q < MVNETA_TX_QNUM_MAX); 1651 mtx_lock(&sc->tx_ring[q].ring_mtx); 1652 } 1653 1654 STATIC __inline void 1655 mvneta_tx_unlockq(struct mvneta_softc *sc, int q) 1656 { 1657 1658 DASSERT(q >= 0); 1659 DASSERT(q < MVNETA_TX_QNUM_MAX); 1660 mtx_unlock(&sc->tx_ring[q].ring_mtx); 1661 } 1662 1663 /* 1664 * Interrupt Handlers 1665 */ 1666 STATIC void 1667 mvneta_disable_intr(struct mvneta_softc *sc) 1668 { 1669 1670 MVNETA_WRITE(sc, MVNETA_EUIM, 0); 1671 MVNETA_WRITE(sc, MVNETA_EUIC, 0); 1672 MVNETA_WRITE(sc, MVNETA_PRXTXTIM, 0); 1673 MVNETA_WRITE(sc, MVNETA_PRXTXTIC, 0); 1674 MVNETA_WRITE(sc, MVNETA_PRXTXIM, 0); 1675 MVNETA_WRITE(sc, MVNETA_PRXTXIC, 0); 1676 MVNETA_WRITE(sc, MVNETA_PMIM, 0); 1677 MVNETA_WRITE(sc, MVNETA_PMIC, 0); 1678 MVNETA_WRITE(sc, MVNETA_PIE, 0); 1679 } 1680 1681 STATIC void 1682 mvneta_enable_intr(struct mvneta_softc *sc) 1683 { 1684 uint32_t reg; 1685 1686 /* Enable Summary Bit to check all interrupt cause. */ 1687 reg = MVNETA_READ(sc, MVNETA_PRXTXTIM); 1688 reg |= MVNETA_PRXTXTI_PMISCICSUMMARY; 1689 MVNETA_WRITE(sc, MVNETA_PRXTXTIM, reg); 1690 1691 if (sc->use_inband_status) { 1692 /* Enable Port MISC Intr. (via RXTX_TH_Summary bit) */ 1693 MVNETA_WRITE(sc, MVNETA_PMIM, MVNETA_PMI_PHYSTATUSCHNG | 1694 MVNETA_PMI_LINKCHANGE | MVNETA_PMI_PSCSYNCCHANGE); 1695 } 1696 1697 /* Enable All Queue Interrupt */ 1698 reg = MVNETA_READ(sc, MVNETA_PIE); 1699 reg |= MVNETA_PIE_RXPKTINTRPTENB_MASK; 1700 reg |= MVNETA_PIE_TXPKTINTRPTENB_MASK; 1701 MVNETA_WRITE(sc, MVNETA_PIE, reg); 1702 } 1703 1704 STATIC void 1705 mvneta_rxtxth_intr(void *arg) 1706 { 1707 struct mvneta_softc *sc; 1708 struct ifnet *ifp; 1709 uint32_t ic, queues; 1710 1711 sc = arg; 1712 ifp = sc->ifp; 1713 #ifdef MVNETA_KTR 1714 CTR1(KTR_SPARE2, "%s got RXTX_TH_Intr", ifp->if_xname); 1715 #endif 1716 ic = MVNETA_READ(sc, MVNETA_PRXTXTIC); 1717 if (ic == 0) 1718 return; 1719 MVNETA_WRITE(sc, MVNETA_PRXTXTIC, ~ic); 1720 1721 /* Ack maintance interrupt first */ 1722 if (__predict_false((ic & MVNETA_PRXTXTI_PMISCICSUMMARY) && 1723 sc->use_inband_status)) { 1724 mvneta_sc_lock(sc); 1725 mvneta_misc_intr(sc); 1726 mvneta_sc_unlock(sc); 1727 } 1728 if (__predict_false(!(ifp->if_drv_flags & IFF_DRV_RUNNING))) 1729 return; 1730 /* RxTxTH interrupt */ 1731 queues = MVNETA_PRXTXTI_GET_RBICTAPQ(ic); 1732 if (__predict_true(queues)) { 1733 #ifdef MVNETA_KTR 1734 CTR1(KTR_SPARE2, "%s got PRXTXTIC: +RXEOF", ifp->if_xname); 1735 #endif 1736 /* At the moment the driver support only one RX queue. */ 1737 DASSERT(MVNETA_IS_QUEUE_SET(queues, 0)); 1738 mvneta_rx(sc, 0, 0); 1739 } 1740 } 1741 1742 STATIC int 1743 mvneta_misc_intr(struct mvneta_softc *sc) 1744 { 1745 uint32_t ic; 1746 int claimed = 0; 1747 1748 #ifdef MVNETA_KTR 1749 CTR1(KTR_SPARE2, "%s got MISC_INTR", sc->ifp->if_xname); 1750 #endif 1751 KASSERT_SC_MTX(sc); 1752 1753 for (;;) { 1754 ic = MVNETA_READ(sc, MVNETA_PMIC); 1755 ic &= MVNETA_READ(sc, MVNETA_PMIM); 1756 if (ic == 0) 1757 break; 1758 MVNETA_WRITE(sc, MVNETA_PMIC, ~ic); 1759 claimed = 1; 1760 1761 if (ic & (MVNETA_PMI_PHYSTATUSCHNG | 1762 MVNETA_PMI_LINKCHANGE | MVNETA_PMI_PSCSYNCCHANGE)) 1763 mvneta_link_isr(sc); 1764 } 1765 return (claimed); 1766 } 1767 1768 STATIC void 1769 mvneta_tick(void *arg) 1770 { 1771 struct mvneta_softc *sc; 1772 struct mvneta_tx_ring *tx; 1773 struct mvneta_rx_ring *rx; 1774 int q; 1775 uint32_t fc_prev, fc_curr; 1776 1777 sc = arg; 1778 1779 /* 1780 * This is done before mib update to get the right stats 1781 * for this tick. 1782 */ 1783 mvneta_tx_drain(sc); 1784 1785 /* Extract previous flow-control frame received counter. */ 1786 fc_prev = sc->sysctl_mib[MVNETA_MIB_FC_GOOD_IDX].counter; 1787 /* Read mib registers (clear by read). */ 1788 mvneta_update_mib(sc); 1789 /* Extract current flow-control frame received counter. */ 1790 fc_curr = sc->sysctl_mib[MVNETA_MIB_FC_GOOD_IDX].counter; 1791 1792 1793 if (sc->phy_attached && sc->ifp->if_flags & IFF_UP) { 1794 mvneta_sc_lock(sc); 1795 mii_tick(sc->mii); 1796 1797 /* Adjust MAC settings */ 1798 mvneta_adjust_link(sc); 1799 mvneta_sc_unlock(sc); 1800 } 1801 1802 /* 1803 * We were unable to refill the rx queue and left the rx func, leaving 1804 * the ring without mbuf and no way to call the refill func. 1805 */ 1806 for (q = 0; q < MVNETA_RX_QNUM_MAX; q++) { 1807 rx = MVNETA_RX_RING(sc, q); 1808 if (rx->needs_refill == TRUE) { 1809 mvneta_rx_lockq(sc, q); 1810 mvneta_rx_queue_refill(sc, q); 1811 mvneta_rx_unlockq(sc, q); 1812 } 1813 } 1814 1815 /* 1816 * Watchdog: 1817 * - check if queue is mark as hung. 1818 * - ignore hung status if we received some pause frame 1819 * as hardware may have paused packet transmit. 1820 */ 1821 for (q = 0; q < MVNETA_TX_QNUM_MAX; q++) { 1822 /* 1823 * We should take queue lock, but as we only read 1824 * queue status we can do it without lock, we may 1825 * only missdetect queue status for one tick. 1826 */ 1827 tx = MVNETA_TX_RING(sc, q); 1828 1829 if (tx->queue_hung && (fc_curr - fc_prev) == 0) 1830 goto timeout; 1831 } 1832 1833 callout_schedule(&sc->tick_ch, hz); 1834 return; 1835 1836 timeout: 1837 if_printf(sc->ifp, "watchdog timeout\n"); 1838 1839 mvneta_sc_lock(sc); 1840 sc->counter_watchdog++; 1841 sc->counter_watchdog_mib++; 1842 /* Trigger reinitialize sequence. */ 1843 mvneta_stop_locked(sc); 1844 mvneta_init_locked(sc); 1845 mvneta_sc_unlock(sc); 1846 } 1847 1848 STATIC void 1849 mvneta_qflush(struct ifnet *ifp) 1850 { 1851 #ifdef MVNETA_MULTIQUEUE 1852 struct mvneta_softc *sc; 1853 struct mvneta_tx_ring *tx; 1854 struct mbuf *m; 1855 size_t q; 1856 1857 sc = ifp->if_softc; 1858 1859 for (q = 0; q < MVNETA_TX_QNUM_MAX; q++) { 1860 tx = MVNETA_TX_RING(sc, q); 1861 mvneta_tx_lockq(sc, q); 1862 while ((m = buf_ring_dequeue_sc(tx->br)) != NULL) 1863 m_freem(m); 1864 mvneta_tx_unlockq(sc, q); 1865 } 1866 #endif 1867 if_qflush(ifp); 1868 } 1869 1870 STATIC void 1871 mvneta_tx_task(void *arg, int pending) 1872 { 1873 struct mvneta_softc *sc; 1874 struct mvneta_tx_ring *tx; 1875 struct ifnet *ifp; 1876 int error; 1877 1878 tx = arg; 1879 ifp = tx->ifp; 1880 sc = ifp->if_softc; 1881 1882 mvneta_tx_lockq(sc, tx->qidx); 1883 error = mvneta_xmit_locked(sc, tx->qidx); 1884 mvneta_tx_unlockq(sc, tx->qidx); 1885 1886 /* Try again */ 1887 if (__predict_false(error != 0 && error != ENETDOWN)) { 1888 pause("mvneta_tx_task_sleep", 1); 1889 taskqueue_enqueue(tx->taskq, &tx->task); 1890 } 1891 } 1892 1893 STATIC int 1894 mvneta_xmitfast_locked(struct mvneta_softc *sc, int q, struct mbuf **m) 1895 { 1896 struct mvneta_tx_ring *tx; 1897 struct ifnet *ifp; 1898 int error; 1899 1900 KASSERT_TX_MTX(sc, q); 1901 tx = MVNETA_TX_RING(sc, q); 1902 error = 0; 1903 1904 ifp = sc->ifp; 1905 1906 /* Dont enqueue packet if the queue is disabled. */ 1907 if (__predict_false(tx->queue_status == MVNETA_QUEUE_DISABLED)) { 1908 m_freem(*m); 1909 *m = NULL; 1910 return (ENETDOWN); 1911 } 1912 1913 /* Reclaim mbuf if above threshold. */ 1914 if (__predict_true(tx->used > MVNETA_TX_RECLAIM_COUNT)) 1915 mvneta_tx_queue_complete(sc, q); 1916 1917 /* Do not call transmit path if queue is already too full. */ 1918 if (__predict_false(tx->used > 1919 MVNETA_TX_RING_CNT - MVNETA_TX_SEGLIMIT)) 1920 return (ENOBUFS); 1921 1922 error = mvneta_tx_queue(sc, m, q); 1923 if (__predict_false(error != 0)) 1924 return (error); 1925 1926 /* Send a copy of the frame to the BPF listener */ 1927 ETHER_BPF_MTAP(ifp, *m); 1928 1929 /* Set watchdog on */ 1930 tx->watchdog_time = ticks; 1931 tx->queue_status = MVNETA_QUEUE_WORKING; 1932 1933 return (error); 1934 } 1935 1936 #ifdef MVNETA_MULTIQUEUE 1937 STATIC int 1938 mvneta_transmit(struct ifnet *ifp, struct mbuf *m) 1939 { 1940 struct mvneta_softc *sc; 1941 struct mvneta_tx_ring *tx; 1942 int error; 1943 int q; 1944 1945 sc = ifp->if_softc; 1946 1947 /* Use default queue if there is no flow id as thread can migrate. */ 1948 if (__predict_true(M_HASHTYPE_GET(m) != M_HASHTYPE_NONE)) 1949 q = m->m_pkthdr.flowid % MVNETA_TX_QNUM_MAX; 1950 else 1951 q = 0; 1952 1953 tx = MVNETA_TX_RING(sc, q); 1954 1955 /* If buf_ring is full start transmit immediatly. */ 1956 if (buf_ring_full(tx->br)) { 1957 mvneta_tx_lockq(sc, q); 1958 mvneta_xmit_locked(sc, q); 1959 mvneta_tx_unlockq(sc, q); 1960 } 1961 1962 /* 1963 * If the buf_ring is empty we will not reorder packets. 1964 * If the lock is available transmit without using buf_ring. 1965 */ 1966 if (buf_ring_empty(tx->br) && mvneta_tx_trylockq(sc, q) != 0) { 1967 error = mvneta_xmitfast_locked(sc, q, &m); 1968 mvneta_tx_unlockq(sc, q); 1969 if (__predict_true(error == 0)) 1970 return (0); 1971 1972 /* Transmit can fail in fastpath. */ 1973 if (__predict_false(m == NULL)) 1974 return (error); 1975 } 1976 1977 /* Enqueue then schedule taskqueue. */ 1978 error = drbr_enqueue(ifp, tx->br, m); 1979 if (__predict_false(error != 0)) 1980 return (error); 1981 1982 taskqueue_enqueue(tx->taskq, &tx->task); 1983 return (0); 1984 } 1985 1986 STATIC int 1987 mvneta_xmit_locked(struct mvneta_softc *sc, int q) 1988 { 1989 struct ifnet *ifp; 1990 struct mvneta_tx_ring *tx; 1991 struct mbuf *m; 1992 int error; 1993 1994 KASSERT_TX_MTX(sc, q); 1995 ifp = sc->ifp; 1996 tx = MVNETA_TX_RING(sc, q); 1997 error = 0; 1998 1999 while ((m = drbr_peek(ifp, tx->br)) != NULL) { 2000 error = mvneta_xmitfast_locked(sc, q, &m); 2001 if (__predict_false(error != 0)) { 2002 if (m != NULL) 2003 drbr_putback(ifp, tx->br, m); 2004 else 2005 drbr_advance(ifp, tx->br); 2006 break; 2007 } 2008 drbr_advance(ifp, tx->br); 2009 } 2010 2011 return (error); 2012 } 2013 #else /* !MVNETA_MULTIQUEUE */ 2014 STATIC void 2015 mvneta_start(struct ifnet *ifp) 2016 { 2017 struct mvneta_softc *sc; 2018 struct mvneta_tx_ring *tx; 2019 int error; 2020 2021 sc = ifp->if_softc; 2022 tx = MVNETA_TX_RING(sc, 0); 2023 2024 mvneta_tx_lockq(sc, 0); 2025 error = mvneta_xmit_locked(sc, 0); 2026 mvneta_tx_unlockq(sc, 0); 2027 /* Handle retransmit in the background taskq. */ 2028 if (__predict_false(error != 0 && error != ENETDOWN)) 2029 taskqueue_enqueue(tx->taskq, &tx->task); 2030 } 2031 2032 STATIC int 2033 mvneta_xmit_locked(struct mvneta_softc *sc, int q) 2034 { 2035 struct ifnet *ifp; 2036 struct mvneta_tx_ring *tx; 2037 struct mbuf *m; 2038 int error; 2039 2040 KASSERT_TX_MTX(sc, q); 2041 ifp = sc->ifp; 2042 tx = MVNETA_TX_RING(sc, 0); 2043 error = 0; 2044 2045 while (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 2046 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 2047 if (m == NULL) 2048 break; 2049 2050 error = mvneta_xmitfast_locked(sc, q, &m); 2051 if (__predict_false(error != 0)) { 2052 if (m != NULL) 2053 IFQ_DRV_PREPEND(&ifp->if_snd, m); 2054 break; 2055 } 2056 } 2057 2058 return (error); 2059 } 2060 #endif 2061 2062 STATIC int 2063 mvneta_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 2064 { 2065 struct mvneta_softc *sc; 2066 struct mvneta_rx_ring *rx; 2067 struct ifreq *ifr; 2068 int error, mask; 2069 uint32_t flags; 2070 int q; 2071 2072 error = 0; 2073 sc = ifp->if_softc; 2074 ifr = (struct ifreq *)data; 2075 switch (cmd) { 2076 case SIOCSIFFLAGS: 2077 mvneta_sc_lock(sc); 2078 if (ifp->if_flags & IFF_UP) { 2079 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 2080 flags = ifp->if_flags ^ sc->mvneta_if_flags; 2081 2082 if (flags != 0) 2083 sc->mvneta_if_flags = ifp->if_flags; 2084 2085 if ((flags & IFF_PROMISC) != 0) 2086 mvneta_filter_setup(sc); 2087 } else { 2088 mvneta_init_locked(sc); 2089 sc->mvneta_if_flags = ifp->if_flags; 2090 if (sc->phy_attached) 2091 mii_mediachg(sc->mii); 2092 mvneta_sc_unlock(sc); 2093 break; 2094 } 2095 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2096 mvneta_stop_locked(sc); 2097 2098 sc->mvneta_if_flags = ifp->if_flags; 2099 mvneta_sc_unlock(sc); 2100 break; 2101 case SIOCSIFCAP: 2102 if (ifp->if_mtu > sc->tx_csum_limit && 2103 ifr->ifr_reqcap & IFCAP_TXCSUM) 2104 ifr->ifr_reqcap &= ~IFCAP_TXCSUM; 2105 mask = ifp->if_capenable ^ ifr->ifr_reqcap; 2106 if (mask & IFCAP_HWCSUM) { 2107 ifp->if_capenable &= ~IFCAP_HWCSUM; 2108 ifp->if_capenable |= IFCAP_HWCSUM & ifr->ifr_reqcap; 2109 if (ifp->if_capenable & IFCAP_TXCSUM) 2110 ifp->if_hwassist = CSUM_IP | CSUM_TCP | 2111 CSUM_UDP; 2112 else 2113 ifp->if_hwassist = 0; 2114 } 2115 if (mask & IFCAP_LRO) { 2116 mvneta_sc_lock(sc); 2117 ifp->if_capenable ^= IFCAP_LRO; 2118 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2119 for (q = 0; q < MVNETA_RX_QNUM_MAX; q++) { 2120 rx = MVNETA_RX_RING(sc, q); 2121 rx->lro_enabled = !rx->lro_enabled; 2122 } 2123 } 2124 mvneta_sc_unlock(sc); 2125 } 2126 VLAN_CAPABILITIES(ifp); 2127 break; 2128 case SIOCSIFMEDIA: 2129 if ((IFM_SUBTYPE(ifr->ifr_media) == IFM_1000_T || 2130 IFM_SUBTYPE(ifr->ifr_media) == IFM_2500_T) && 2131 (ifr->ifr_media & IFM_FDX) == 0) { 2132 device_printf(sc->dev, 2133 "%s half-duplex unsupported\n", 2134 IFM_SUBTYPE(ifr->ifr_media) == IFM_1000_T ? 2135 "1000Base-T" : 2136 "2500Base-T"); 2137 error = EINVAL; 2138 break; 2139 } 2140 case SIOCGIFMEDIA: /* FALLTHROUGH */ 2141 case SIOCGIFXMEDIA: 2142 if (!sc->phy_attached) 2143 error = ifmedia_ioctl(ifp, ifr, &sc->mvneta_ifmedia, 2144 cmd); 2145 else 2146 error = ifmedia_ioctl(ifp, ifr, &sc->mii->mii_media, 2147 cmd); 2148 break; 2149 case SIOCSIFMTU: 2150 if (ifr->ifr_mtu < 68 || ifr->ifr_mtu > MVNETA_MAX_FRAME - 2151 MVNETA_ETHER_SIZE) { 2152 error = EINVAL; 2153 } else { 2154 ifp->if_mtu = ifr->ifr_mtu; 2155 mvneta_sc_lock(sc); 2156 if (ifp->if_mtu + MVNETA_ETHER_SIZE <= MCLBYTES) { 2157 sc->rx_frame_size = MCLBYTES; 2158 } else { 2159 sc->rx_frame_size = MJUM9BYTES; 2160 } 2161 if (ifp->if_mtu > sc->tx_csum_limit) { 2162 ifp->if_capenable &= ~IFCAP_TXCSUM; 2163 ifp->if_hwassist = 0; 2164 } else { 2165 ifp->if_capenable |= IFCAP_TXCSUM; 2166 ifp->if_hwassist = CSUM_IP | CSUM_TCP | 2167 CSUM_UDP; 2168 } 2169 2170 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 2171 /* Stop hardware */ 2172 mvneta_stop_locked(sc); 2173 /* 2174 * Reinitialize RX queues. 2175 * We need to update RX descriptor size. 2176 */ 2177 for (q = 0; q < MVNETA_RX_QNUM_MAX; q++) { 2178 mvneta_rx_lockq(sc, q); 2179 if (mvneta_rx_queue_init(ifp, q) != 0) { 2180 device_printf(sc->dev, 2181 "initialization failed:" 2182 " cannot initialize queue\n"); 2183 mvneta_rx_unlockq(sc, q); 2184 error = ENOBUFS; 2185 break; 2186 } 2187 mvneta_rx_unlockq(sc, q); 2188 } 2189 /* Trigger reinitialization */ 2190 mvneta_init_locked(sc); 2191 } 2192 mvneta_sc_unlock(sc); 2193 } 2194 break; 2195 2196 default: 2197 error = ether_ioctl(ifp, cmd, data); 2198 break; 2199 } 2200 2201 return (error); 2202 } 2203 2204 STATIC void 2205 mvneta_init_locked(void *arg) 2206 { 2207 struct mvneta_softc *sc; 2208 struct ifnet *ifp; 2209 uint32_t reg; 2210 int q, cpu; 2211 2212 sc = arg; 2213 ifp = sc->ifp; 2214 2215 if (!device_is_attached(sc->dev) || 2216 (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2217 return; 2218 2219 mvneta_disable_intr(sc); 2220 callout_stop(&sc->tick_ch); 2221 2222 /* Get the latest mac address */ 2223 bcopy(IF_LLADDR(ifp), sc->enaddr, ETHER_ADDR_LEN); 2224 mvneta_set_mac_address(sc, sc->enaddr); 2225 mvneta_filter_setup(sc); 2226 2227 /* Start DMA Engine */ 2228 MVNETA_WRITE(sc, MVNETA_PRXINIT, 0x00000000); 2229 MVNETA_WRITE(sc, MVNETA_PTXINIT, 0x00000000); 2230 MVNETA_WRITE(sc, MVNETA_PACC, MVNETA_PACC_ACCELERATIONMODE_EDM); 2231 2232 /* Enable port */ 2233 reg = MVNETA_READ(sc, MVNETA_PMACC0); 2234 reg |= MVNETA_PMACC0_PORTEN; 2235 reg &= ~MVNETA_PMACC0_FRAMESIZELIMIT_MASK; 2236 reg |= MVNETA_PMACC0_FRAMESIZELIMIT(ifp->if_mtu + MVNETA_ETHER_SIZE); 2237 MVNETA_WRITE(sc, MVNETA_PMACC0, reg); 2238 2239 /* Allow access to each TXQ/RXQ from both CPU's */ 2240 for (cpu = 0; cpu < mp_ncpus; ++cpu) 2241 MVNETA_WRITE(sc, MVNETA_PCP2Q(cpu), 2242 MVNETA_PCP2Q_TXQEN_MASK | MVNETA_PCP2Q_RXQEN_MASK); 2243 2244 for (q = 0; q < MVNETA_RX_QNUM_MAX; q++) { 2245 mvneta_rx_lockq(sc, q); 2246 mvneta_rx_queue_refill(sc, q); 2247 mvneta_rx_unlockq(sc, q); 2248 } 2249 2250 if (!sc->phy_attached) 2251 mvneta_linkup(sc); 2252 2253 /* Enable interrupt */ 2254 mvneta_enable_intr(sc); 2255 2256 /* Set Counter */ 2257 callout_schedule(&sc->tick_ch, hz); 2258 2259 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2260 } 2261 2262 STATIC void 2263 mvneta_init(void *arg) 2264 { 2265 struct mvneta_softc *sc; 2266 2267 sc = arg; 2268 mvneta_sc_lock(sc); 2269 mvneta_init_locked(sc); 2270 if (sc->phy_attached) 2271 mii_mediachg(sc->mii); 2272 mvneta_sc_unlock(sc); 2273 } 2274 2275 /* ARGSUSED */ 2276 STATIC void 2277 mvneta_stop_locked(struct mvneta_softc *sc) 2278 { 2279 struct ifnet *ifp; 2280 struct mvneta_rx_ring *rx; 2281 struct mvneta_tx_ring *tx; 2282 uint32_t reg; 2283 int q; 2284 2285 ifp = sc->ifp; 2286 if (ifp == NULL || (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 2287 return; 2288 2289 mvneta_disable_intr(sc); 2290 2291 callout_stop(&sc->tick_ch); 2292 2293 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2294 2295 /* Link down */ 2296 if (sc->linkup == TRUE) 2297 mvneta_linkdown(sc); 2298 2299 /* Reset the MAC Port Enable bit */ 2300 reg = MVNETA_READ(sc, MVNETA_PMACC0); 2301 reg &= ~MVNETA_PMACC0_PORTEN; 2302 MVNETA_WRITE(sc, MVNETA_PMACC0, reg); 2303 2304 /* Disable each of queue */ 2305 for (q = 0; q < MVNETA_RX_QNUM_MAX; q++) { 2306 rx = MVNETA_RX_RING(sc, q); 2307 2308 mvneta_rx_lockq(sc, q); 2309 mvneta_ring_flush_rx_queue(sc, q); 2310 mvneta_rx_unlockq(sc, q); 2311 } 2312 2313 /* 2314 * Hold Reset state of DMA Engine 2315 * (must write 0x0 to restart it) 2316 */ 2317 MVNETA_WRITE(sc, MVNETA_PRXINIT, 0x00000001); 2318 MVNETA_WRITE(sc, MVNETA_PTXINIT, 0x00000001); 2319 2320 for (q = 0; q < MVNETA_TX_QNUM_MAX; q++) { 2321 tx = MVNETA_TX_RING(sc, q); 2322 2323 mvneta_tx_lockq(sc, q); 2324 mvneta_ring_flush_tx_queue(sc, q); 2325 mvneta_tx_unlockq(sc, q); 2326 } 2327 } 2328 2329 STATIC void 2330 mvneta_stop(struct mvneta_softc *sc) 2331 { 2332 2333 mvneta_sc_lock(sc); 2334 mvneta_stop_locked(sc); 2335 mvneta_sc_unlock(sc); 2336 } 2337 2338 STATIC int 2339 mvneta_mediachange(struct ifnet *ifp) 2340 { 2341 struct mvneta_softc *sc; 2342 2343 sc = ifp->if_softc; 2344 2345 if (!sc->phy_attached && !sc->use_inband_status) { 2346 /* We shouldn't be here */ 2347 if_printf(ifp, "Cannot change media in fixed-link mode!\n"); 2348 return (0); 2349 } 2350 2351 if (sc->use_inband_status) { 2352 mvneta_update_media(sc, sc->mvneta_ifmedia.ifm_media); 2353 return (0); 2354 } 2355 2356 mvneta_sc_lock(sc); 2357 2358 /* Update PHY */ 2359 mii_mediachg(sc->mii); 2360 2361 mvneta_sc_unlock(sc); 2362 2363 return (0); 2364 } 2365 2366 STATIC void 2367 mvneta_get_media(struct mvneta_softc *sc, struct ifmediareq *ifmr) 2368 { 2369 uint32_t psr; 2370 2371 psr = MVNETA_READ(sc, MVNETA_PSR); 2372 2373 /* Speed */ 2374 if (psr & MVNETA_PSR_GMIISPEED) 2375 ifmr->ifm_active = IFM_ETHER_SUBTYPE_SET(IFM_1000_T); 2376 else if (psr & MVNETA_PSR_MIISPEED) 2377 ifmr->ifm_active = IFM_ETHER_SUBTYPE_SET(IFM_100_TX); 2378 else if (psr & MVNETA_PSR_LINKUP) 2379 ifmr->ifm_active = IFM_ETHER_SUBTYPE_SET(IFM_10_T); 2380 2381 /* Duplex */ 2382 if (psr & MVNETA_PSR_FULLDX) 2383 ifmr->ifm_active |= IFM_FDX; 2384 2385 /* Link */ 2386 ifmr->ifm_status = IFM_AVALID; 2387 if (psr & MVNETA_PSR_LINKUP) 2388 ifmr->ifm_status |= IFM_ACTIVE; 2389 } 2390 2391 STATIC void 2392 mvneta_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 2393 { 2394 struct mvneta_softc *sc; 2395 struct mii_data *mii; 2396 2397 sc = ifp->if_softc; 2398 2399 if (!sc->phy_attached && !sc->use_inband_status) { 2400 ifmr->ifm_status = IFM_AVALID | IFM_ACTIVE; 2401 return; 2402 } 2403 2404 mvneta_sc_lock(sc); 2405 2406 if (sc->use_inband_status) { 2407 mvneta_get_media(sc, ifmr); 2408 mvneta_sc_unlock(sc); 2409 return; 2410 } 2411 2412 mii = sc->mii; 2413 mii_pollstat(mii); 2414 2415 ifmr->ifm_active = mii->mii_media_active; 2416 ifmr->ifm_status = mii->mii_media_status; 2417 2418 mvneta_sc_unlock(sc); 2419 } 2420 2421 /* 2422 * Link State Notify 2423 */ 2424 STATIC void 2425 mvneta_update_autoneg(struct mvneta_softc *sc, int enable) 2426 { 2427 int reg; 2428 2429 if (enable) { 2430 reg = MVNETA_READ(sc, MVNETA_PANC); 2431 reg &= ~(MVNETA_PANC_FORCELINKFAIL | MVNETA_PANC_FORCELINKPASS | 2432 MVNETA_PANC_ANFCEN); 2433 reg |= MVNETA_PANC_ANDUPLEXEN | MVNETA_PANC_ANSPEEDEN | 2434 MVNETA_PANC_INBANDANEN; 2435 MVNETA_WRITE(sc, MVNETA_PANC, reg); 2436 2437 reg = MVNETA_READ(sc, MVNETA_PMACC2); 2438 reg |= MVNETA_PMACC2_INBANDANMODE; 2439 MVNETA_WRITE(sc, MVNETA_PMACC2, reg); 2440 2441 reg = MVNETA_READ(sc, MVNETA_PSOMSCD); 2442 reg |= MVNETA_PSOMSCD_ENABLE; 2443 MVNETA_WRITE(sc, MVNETA_PSOMSCD, reg); 2444 } else { 2445 reg = MVNETA_READ(sc, MVNETA_PANC); 2446 reg &= ~(MVNETA_PANC_FORCELINKFAIL | MVNETA_PANC_FORCELINKPASS | 2447 MVNETA_PANC_ANDUPLEXEN | MVNETA_PANC_ANSPEEDEN | 2448 MVNETA_PANC_INBANDANEN); 2449 MVNETA_WRITE(sc, MVNETA_PANC, reg); 2450 2451 reg = MVNETA_READ(sc, MVNETA_PMACC2); 2452 reg &= ~MVNETA_PMACC2_INBANDANMODE; 2453 MVNETA_WRITE(sc, MVNETA_PMACC2, reg); 2454 2455 reg = MVNETA_READ(sc, MVNETA_PSOMSCD); 2456 reg &= ~MVNETA_PSOMSCD_ENABLE; 2457 MVNETA_WRITE(sc, MVNETA_PSOMSCD, reg); 2458 } 2459 } 2460 2461 STATIC int 2462 mvneta_update_media(struct mvneta_softc *sc, int media) 2463 { 2464 int reg, err; 2465 boolean_t running; 2466 2467 err = 0; 2468 2469 mvneta_sc_lock(sc); 2470 2471 mvneta_linkreset(sc); 2472 2473 running = (sc->ifp->if_drv_flags & IFF_DRV_RUNNING) != 0; 2474 if (running) 2475 mvneta_stop_locked(sc); 2476 2477 sc->autoneg = (IFM_SUBTYPE(media) == IFM_AUTO); 2478 2479 if (sc->use_inband_status) 2480 mvneta_update_autoneg(sc, IFM_SUBTYPE(media) == IFM_AUTO); 2481 2482 mvneta_update_eee(sc); 2483 mvneta_update_fc(sc); 2484 2485 if (IFM_SUBTYPE(media) != IFM_AUTO) { 2486 reg = MVNETA_READ(sc, MVNETA_PANC); 2487 reg &= ~(MVNETA_PANC_SETGMIISPEED | 2488 MVNETA_PANC_SETMIISPEED | 2489 MVNETA_PANC_SETFULLDX); 2490 if (IFM_SUBTYPE(media) == IFM_1000_T || 2491 IFM_SUBTYPE(media) == IFM_2500_T) { 2492 if ((media & IFM_FDX) == 0) { 2493 device_printf(sc->dev, 2494 "%s half-duplex unsupported\n", 2495 IFM_SUBTYPE(media) == IFM_1000_T ? 2496 "1000Base-T" : 2497 "2500Base-T"); 2498 err = EINVAL; 2499 goto out; 2500 } 2501 reg |= MVNETA_PANC_SETGMIISPEED; 2502 } else if (IFM_SUBTYPE(media) == IFM_100_TX) 2503 reg |= MVNETA_PANC_SETMIISPEED; 2504 2505 if (media & IFM_FDX) 2506 reg |= MVNETA_PANC_SETFULLDX; 2507 2508 MVNETA_WRITE(sc, MVNETA_PANC, reg); 2509 } 2510 out: 2511 if (running) 2512 mvneta_init_locked(sc); 2513 mvneta_sc_unlock(sc); 2514 return (err); 2515 } 2516 2517 STATIC void 2518 mvneta_adjust_link(struct mvneta_softc *sc) 2519 { 2520 boolean_t phy_linkup; 2521 int reg; 2522 2523 /* Update eee/fc */ 2524 mvneta_update_eee(sc); 2525 mvneta_update_fc(sc); 2526 2527 /* Check for link change */ 2528 phy_linkup = (sc->mii->mii_media_status & 2529 (IFM_AVALID | IFM_ACTIVE)) == (IFM_AVALID | IFM_ACTIVE); 2530 2531 if (sc->linkup != phy_linkup) 2532 mvneta_linkupdate(sc, phy_linkup); 2533 2534 /* Don't update media on disabled link */ 2535 if (!phy_linkup) 2536 return; 2537 2538 /* Check for media type change */ 2539 if (sc->mvneta_media != sc->mii->mii_media_active) { 2540 sc->mvneta_media = sc->mii->mii_media_active; 2541 2542 reg = MVNETA_READ(sc, MVNETA_PANC); 2543 reg &= ~(MVNETA_PANC_SETGMIISPEED | 2544 MVNETA_PANC_SETMIISPEED | 2545 MVNETA_PANC_SETFULLDX); 2546 if (IFM_SUBTYPE(sc->mvneta_media) == IFM_1000_T || 2547 IFM_SUBTYPE(sc->mvneta_media) == IFM_2500_T) { 2548 reg |= MVNETA_PANC_SETGMIISPEED; 2549 } else if (IFM_SUBTYPE(sc->mvneta_media) == IFM_100_TX) 2550 reg |= MVNETA_PANC_SETMIISPEED; 2551 2552 if (sc->mvneta_media & IFM_FDX) 2553 reg |= MVNETA_PANC_SETFULLDX; 2554 2555 MVNETA_WRITE(sc, MVNETA_PANC, reg); 2556 } 2557 } 2558 2559 STATIC void 2560 mvneta_link_isr(struct mvneta_softc *sc) 2561 { 2562 int linkup; 2563 2564 KASSERT_SC_MTX(sc); 2565 2566 linkup = MVNETA_IS_LINKUP(sc) ? TRUE : FALSE; 2567 if (sc->linkup == linkup) 2568 return; 2569 2570 if (linkup == TRUE) 2571 mvneta_linkup(sc); 2572 else 2573 mvneta_linkdown(sc); 2574 2575 #ifdef DEBUG 2576 log(LOG_DEBUG, 2577 "%s: link %s\n", device_xname(sc->dev), linkup ? "up" : "down"); 2578 #endif 2579 } 2580 2581 STATIC void 2582 mvneta_linkupdate(struct mvneta_softc *sc, boolean_t linkup) 2583 { 2584 2585 KASSERT_SC_MTX(sc); 2586 2587 if (linkup == TRUE) 2588 mvneta_linkup(sc); 2589 else 2590 mvneta_linkdown(sc); 2591 2592 #ifdef DEBUG 2593 log(LOG_DEBUG, 2594 "%s: link %s\n", device_xname(sc->dev), linkup ? "up" : "down"); 2595 #endif 2596 } 2597 2598 STATIC void 2599 mvneta_update_eee(struct mvneta_softc *sc) 2600 { 2601 uint32_t reg; 2602 2603 KASSERT_SC_MTX(sc); 2604 2605 /* set EEE parameters */ 2606 reg = MVNETA_READ(sc, MVNETA_LPIC1); 2607 if (sc->cf_lpi) 2608 reg |= MVNETA_LPIC1_LPIRE; 2609 else 2610 reg &= ~MVNETA_LPIC1_LPIRE; 2611 MVNETA_WRITE(sc, MVNETA_LPIC1, reg); 2612 } 2613 2614 STATIC void 2615 mvneta_update_fc(struct mvneta_softc *sc) 2616 { 2617 uint32_t reg; 2618 2619 KASSERT_SC_MTX(sc); 2620 2621 reg = MVNETA_READ(sc, MVNETA_PANC); 2622 if (sc->cf_fc) { 2623 /* Flow control negotiation */ 2624 reg |= MVNETA_PANC_PAUSEADV; 2625 reg |= MVNETA_PANC_ANFCEN; 2626 } else { 2627 /* Disable flow control negotiation */ 2628 reg &= ~MVNETA_PANC_PAUSEADV; 2629 reg &= ~MVNETA_PANC_ANFCEN; 2630 } 2631 2632 MVNETA_WRITE(sc, MVNETA_PANC, reg); 2633 } 2634 2635 STATIC void 2636 mvneta_linkup(struct mvneta_softc *sc) 2637 { 2638 uint32_t reg; 2639 2640 KASSERT_SC_MTX(sc); 2641 2642 if (!sc->use_inband_status) { 2643 reg = MVNETA_READ(sc, MVNETA_PANC); 2644 reg |= MVNETA_PANC_FORCELINKPASS; 2645 reg &= ~MVNETA_PANC_FORCELINKFAIL; 2646 MVNETA_WRITE(sc, MVNETA_PANC, reg); 2647 } 2648 2649 mvneta_qflush(sc->ifp); 2650 mvneta_portup(sc); 2651 sc->linkup = TRUE; 2652 if_link_state_change(sc->ifp, LINK_STATE_UP); 2653 } 2654 2655 STATIC void 2656 mvneta_linkdown(struct mvneta_softc *sc) 2657 { 2658 uint32_t reg; 2659 2660 KASSERT_SC_MTX(sc); 2661 2662 if (!sc->use_inband_status) { 2663 reg = MVNETA_READ(sc, MVNETA_PANC); 2664 reg &= ~MVNETA_PANC_FORCELINKPASS; 2665 reg |= MVNETA_PANC_FORCELINKFAIL; 2666 MVNETA_WRITE(sc, MVNETA_PANC, reg); 2667 } 2668 2669 mvneta_portdown(sc); 2670 mvneta_qflush(sc->ifp); 2671 sc->linkup = FALSE; 2672 if_link_state_change(sc->ifp, LINK_STATE_DOWN); 2673 } 2674 2675 STATIC void 2676 mvneta_linkreset(struct mvneta_softc *sc) 2677 { 2678 struct mii_softc *mii; 2679 2680 if (sc->phy_attached) { 2681 /* Force reset PHY */ 2682 mii = LIST_FIRST(&sc->mii->mii_phys); 2683 if (mii) 2684 mii_phy_reset(mii); 2685 } 2686 } 2687 2688 /* 2689 * Tx Subroutines 2690 */ 2691 STATIC int 2692 mvneta_tx_queue(struct mvneta_softc *sc, struct mbuf **mbufp, int q) 2693 { 2694 struct ifnet *ifp; 2695 bus_dma_segment_t txsegs[MVNETA_TX_SEGLIMIT]; 2696 struct mbuf *mtmp, *mbuf; 2697 struct mvneta_tx_ring *tx; 2698 struct mvneta_buf *txbuf; 2699 struct mvneta_tx_desc *t; 2700 uint32_t ptxsu; 2701 int start, used, error, i, txnsegs; 2702 2703 mbuf = *mbufp; 2704 tx = MVNETA_TX_RING(sc, q); 2705 DASSERT(tx->used >= 0); 2706 DASSERT(tx->used <= MVNETA_TX_RING_CNT); 2707 t = NULL; 2708 ifp = sc->ifp; 2709 2710 if (__predict_false(mbuf->m_flags & M_VLANTAG)) { 2711 mbuf = ether_vlanencap(mbuf, mbuf->m_pkthdr.ether_vtag); 2712 if (mbuf == NULL) { 2713 tx->drv_error++; 2714 *mbufp = NULL; 2715 return (ENOBUFS); 2716 } 2717 mbuf->m_flags &= ~M_VLANTAG; 2718 *mbufp = mbuf; 2719 } 2720 2721 if (__predict_false(mbuf->m_next != NULL && 2722 (mbuf->m_pkthdr.csum_flags & 2723 (CSUM_IP | CSUM_TCP | CSUM_UDP)) != 0)) { 2724 if (M_WRITABLE(mbuf) == 0) { 2725 mtmp = m_dup(mbuf, M_NOWAIT); 2726 m_freem(mbuf); 2727 if (mtmp == NULL) { 2728 tx->drv_error++; 2729 *mbufp = NULL; 2730 return (ENOBUFS); 2731 } 2732 *mbufp = mbuf = mtmp; 2733 } 2734 } 2735 2736 /* load mbuf using dmamap of 1st descriptor */ 2737 txbuf = &tx->txbuf[tx->cpu]; 2738 error = bus_dmamap_load_mbuf_sg(sc->txmbuf_dtag, 2739 txbuf->dmap, mbuf, txsegs, &txnsegs, 2740 BUS_DMA_NOWAIT); 2741 if (__predict_false(error != 0)) { 2742 #ifdef MVNETA_KTR 2743 CTR3(KTR_SPARE2, "%s:%u bus_dmamap_load_mbuf_sg error=%d", ifp->if_xname, q, error); 2744 #endif 2745 /* This is the only recoverable error (except EFBIG). */ 2746 if (error != ENOMEM) { 2747 tx->drv_error++; 2748 m_freem(mbuf); 2749 *mbufp = NULL; 2750 return (ENOBUFS); 2751 } 2752 return (error); 2753 } 2754 2755 if (__predict_false(txnsegs <= 0 2756 || (txnsegs + tx->used) > MVNETA_TX_RING_CNT)) { 2757 /* we have no enough descriptors or mbuf is broken */ 2758 #ifdef MVNETA_KTR 2759 CTR3(KTR_SPARE2, "%s:%u not enough descriptors txnsegs=%d", 2760 ifp->if_xname, q, txnsegs); 2761 #endif 2762 bus_dmamap_unload(sc->txmbuf_dtag, txbuf->dmap); 2763 return (ENOBUFS); 2764 } 2765 DASSERT(txbuf->m == NULL); 2766 2767 /* remember mbuf using 1st descriptor */ 2768 txbuf->m = mbuf; 2769 bus_dmamap_sync(sc->txmbuf_dtag, txbuf->dmap, 2770 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2771 2772 /* load to tx descriptors */ 2773 start = tx->cpu; 2774 used = 0; 2775 for (i = 0; i < txnsegs; i++) { 2776 t = &tx->desc[tx->cpu]; 2777 t->command = 0; 2778 t->l4ichk = 0; 2779 t->flags = 0; 2780 if (__predict_true(i == 0)) { 2781 /* 1st descriptor */ 2782 t->command |= MVNETA_TX_CMD_W_PACKET_OFFSET(0); 2783 t->command |= MVNETA_TX_CMD_F; 2784 mvneta_tx_set_csumflag(ifp, t, mbuf); 2785 } 2786 t->bufptr_pa = txsegs[i].ds_addr; 2787 t->bytecnt = txsegs[i].ds_len; 2788 tx->cpu = tx_counter_adv(tx->cpu, 1); 2789 2790 tx->used++; 2791 used++; 2792 } 2793 /* t is last descriptor here */ 2794 DASSERT(t != NULL); 2795 t->command |= MVNETA_TX_CMD_L|MVNETA_TX_CMD_PADDING; 2796 2797 bus_dmamap_sync(sc->tx_dtag, tx->desc_map, 2798 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2799 2800 while (__predict_false(used > 255)) { 2801 ptxsu = MVNETA_PTXSU_NOWD(255); 2802 MVNETA_WRITE(sc, MVNETA_PTXSU(q), ptxsu); 2803 used -= 255; 2804 } 2805 if (__predict_true(used > 0)) { 2806 ptxsu = MVNETA_PTXSU_NOWD(used); 2807 MVNETA_WRITE(sc, MVNETA_PTXSU(q), ptxsu); 2808 } 2809 return (0); 2810 } 2811 2812 STATIC void 2813 mvneta_tx_set_csumflag(struct ifnet *ifp, 2814 struct mvneta_tx_desc *t, struct mbuf *m) 2815 { 2816 struct ether_header *eh; 2817 int csum_flags; 2818 uint32_t iphl, ipoff; 2819 struct ip *ip; 2820 2821 iphl = ipoff = 0; 2822 csum_flags = ifp->if_hwassist & m->m_pkthdr.csum_flags; 2823 eh = mtod(m, struct ether_header *); 2824 2825 switch (ntohs(eh->ether_type)) { 2826 case ETHERTYPE_IP: 2827 ipoff = ETHER_HDR_LEN; 2828 break; 2829 case ETHERTYPE_VLAN: 2830 ipoff = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 2831 break; 2832 default: 2833 csum_flags = 0; 2834 } 2835 2836 if (__predict_true(csum_flags & (CSUM_IP|CSUM_IP_TCP|CSUM_IP_UDP))) { 2837 ip = (struct ip *)(m->m_data + ipoff); 2838 iphl = ip->ip_hl<<2; 2839 t->command |= MVNETA_TX_CMD_L3_IP4; 2840 } else { 2841 t->command |= MVNETA_TX_CMD_L4_CHECKSUM_NONE; 2842 return; 2843 } 2844 2845 2846 /* L3 */ 2847 if (csum_flags & CSUM_IP) { 2848 t->command |= MVNETA_TX_CMD_IP4_CHECKSUM; 2849 } 2850 2851 /* L4 */ 2852 if (csum_flags & CSUM_IP_TCP) { 2853 t->command |= MVNETA_TX_CMD_L4_CHECKSUM_NOFRAG; 2854 t->command |= MVNETA_TX_CMD_L4_TCP; 2855 } else if (csum_flags & CSUM_IP_UDP) { 2856 t->command |= MVNETA_TX_CMD_L4_CHECKSUM_NOFRAG; 2857 t->command |= MVNETA_TX_CMD_L4_UDP; 2858 } else 2859 t->command |= MVNETA_TX_CMD_L4_CHECKSUM_NONE; 2860 2861 t->l4ichk = 0; 2862 t->command |= MVNETA_TX_CMD_IP_HEADER_LEN(iphl >> 2); 2863 t->command |= MVNETA_TX_CMD_L3_OFFSET(ipoff); 2864 } 2865 2866 STATIC void 2867 mvneta_tx_queue_complete(struct mvneta_softc *sc, int q) 2868 { 2869 struct mvneta_tx_ring *tx; 2870 struct mvneta_buf *txbuf; 2871 struct mvneta_tx_desc *t; 2872 uint32_t ptxs, ptxsu, ndesc; 2873 int i; 2874 2875 KASSERT_TX_MTX(sc, q); 2876 2877 tx = MVNETA_TX_RING(sc, q); 2878 if (__predict_false(tx->queue_status == MVNETA_QUEUE_DISABLED)) 2879 return; 2880 2881 ptxs = MVNETA_READ(sc, MVNETA_PTXS(q)); 2882 ndesc = MVNETA_PTXS_GET_TBC(ptxs); 2883 2884 if (__predict_false(ndesc == 0)) { 2885 if (tx->used == 0) 2886 tx->queue_status = MVNETA_QUEUE_IDLE; 2887 else if (tx->queue_status == MVNETA_QUEUE_WORKING && 2888 ((ticks - tx->watchdog_time) > MVNETA_WATCHDOG)) 2889 tx->queue_hung = TRUE; 2890 return; 2891 } 2892 2893 #ifdef MVNETA_KTR 2894 CTR3(KTR_SPARE2, "%s:%u tx_complete begin ndesc=%u", 2895 sc->ifp->if_xname, q, ndesc); 2896 #endif 2897 2898 bus_dmamap_sync(sc->tx_dtag, tx->desc_map, 2899 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2900 2901 for (i = 0; i < ndesc; i++) { 2902 t = &tx->desc[tx->dma]; 2903 #ifdef MVNETA_KTR 2904 if (t->flags & MVNETA_TX_F_ES) 2905 CTR3(KTR_SPARE2, "%s tx error queue %d desc %d", 2906 sc->ifp->if_xname, q, tx->dma); 2907 #endif 2908 txbuf = &tx->txbuf[tx->dma]; 2909 if (__predict_true(txbuf->m != NULL)) { 2910 DASSERT((t->command & MVNETA_TX_CMD_F) != 0); 2911 bus_dmamap_unload(sc->txmbuf_dtag, txbuf->dmap); 2912 m_freem(txbuf->m); 2913 txbuf->m = NULL; 2914 } 2915 else 2916 DASSERT((t->flags & MVNETA_TX_CMD_F) == 0); 2917 tx->dma = tx_counter_adv(tx->dma, 1); 2918 tx->used--; 2919 } 2920 DASSERT(tx->used >= 0); 2921 DASSERT(tx->used <= MVNETA_TX_RING_CNT); 2922 while (__predict_false(ndesc > 255)) { 2923 ptxsu = MVNETA_PTXSU_NORB(255); 2924 MVNETA_WRITE(sc, MVNETA_PTXSU(q), ptxsu); 2925 ndesc -= 255; 2926 } 2927 if (__predict_true(ndesc > 0)) { 2928 ptxsu = MVNETA_PTXSU_NORB(ndesc); 2929 MVNETA_WRITE(sc, MVNETA_PTXSU(q), ptxsu); 2930 } 2931 #ifdef MVNETA_KTR 2932 CTR5(KTR_SPARE2, "%s:%u tx_complete tx_cpu=%d tx_dma=%d tx_used=%d", 2933 sc->ifp->if_xname, q, tx->cpu, tx->dma, tx->used); 2934 #endif 2935 2936 tx->watchdog_time = ticks; 2937 2938 if (tx->used == 0) 2939 tx->queue_status = MVNETA_QUEUE_IDLE; 2940 } 2941 2942 /* 2943 * Do a final TX complete when TX is idle. 2944 */ 2945 STATIC void 2946 mvneta_tx_drain(struct mvneta_softc *sc) 2947 { 2948 struct mvneta_tx_ring *tx; 2949 int q; 2950 2951 /* 2952 * Handle trailing mbuf on TX queue. 2953 * Check is done lockess to avoid TX path contention. 2954 */ 2955 for (q = 0; q < MVNETA_TX_QNUM_MAX; q++) { 2956 tx = MVNETA_TX_RING(sc, q); 2957 if ((ticks - tx->watchdog_time) > MVNETA_WATCHDOG_TXCOMP && 2958 tx->used > 0) { 2959 mvneta_tx_lockq(sc, q); 2960 mvneta_tx_queue_complete(sc, q); 2961 mvneta_tx_unlockq(sc, q); 2962 } 2963 } 2964 } 2965 2966 /* 2967 * Rx Subroutines 2968 */ 2969 STATIC int 2970 mvneta_rx(struct mvneta_softc *sc, int q, int count) 2971 { 2972 uint32_t prxs, npkt; 2973 int more; 2974 2975 more = 0; 2976 mvneta_rx_lockq(sc, q); 2977 prxs = MVNETA_READ(sc, MVNETA_PRXS(q)); 2978 npkt = MVNETA_PRXS_GET_ODC(prxs); 2979 if (__predict_false(npkt == 0)) 2980 goto out; 2981 2982 if (count > 0 && npkt > count) { 2983 more = 1; 2984 npkt = count; 2985 } 2986 mvneta_rx_queue(sc, q, npkt); 2987 out: 2988 mvneta_rx_unlockq(sc, q); 2989 return more; 2990 } 2991 2992 /* 2993 * Helper routine for updating PRXSU register of a given queue. 2994 * Handles number of processed descriptors bigger than maximum acceptable value. 2995 */ 2996 STATIC __inline void 2997 mvneta_prxsu_update(struct mvneta_softc *sc, int q, int processed) 2998 { 2999 uint32_t prxsu; 3000 3001 while (__predict_false(processed > 255)) { 3002 prxsu = MVNETA_PRXSU_NOOFPROCESSEDDESCRIPTORS(255); 3003 MVNETA_WRITE(sc, MVNETA_PRXSU(q), prxsu); 3004 processed -= 255; 3005 } 3006 prxsu = MVNETA_PRXSU_NOOFPROCESSEDDESCRIPTORS(processed); 3007 MVNETA_WRITE(sc, MVNETA_PRXSU(q), prxsu); 3008 } 3009 3010 static __inline void 3011 mvneta_prefetch(void *p) 3012 { 3013 3014 __builtin_prefetch(p); 3015 } 3016 3017 STATIC void 3018 mvneta_rx_queue(struct mvneta_softc *sc, int q, int npkt) 3019 { 3020 struct ifnet *ifp; 3021 struct mvneta_rx_ring *rx; 3022 struct mvneta_rx_desc *r; 3023 struct mvneta_buf *rxbuf; 3024 struct mbuf *m; 3025 struct lro_ctrl *lro; 3026 struct lro_entry *queued; 3027 void *pktbuf; 3028 int i, pktlen, processed, ndma; 3029 3030 KASSERT_RX_MTX(sc, q); 3031 3032 ifp = sc->ifp; 3033 rx = MVNETA_RX_RING(sc, q); 3034 processed = 0; 3035 3036 if (__predict_false(rx->queue_status == MVNETA_QUEUE_DISABLED)) 3037 return; 3038 3039 bus_dmamap_sync(sc->rx_dtag, rx->desc_map, 3040 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3041 3042 for (i = 0; i < npkt; i++) { 3043 /* Prefetch next desc, rxbuf. */ 3044 ndma = rx_counter_adv(rx->dma, 1); 3045 mvneta_prefetch(&rx->desc[ndma]); 3046 mvneta_prefetch(&rx->rxbuf[ndma]); 3047 3048 /* get descriptor and packet */ 3049 r = &rx->desc[rx->dma]; 3050 rxbuf = &rx->rxbuf[rx->dma]; 3051 m = rxbuf->m; 3052 rxbuf->m = NULL; 3053 DASSERT(m != NULL); 3054 bus_dmamap_sync(sc->rxbuf_dtag, rxbuf->dmap, 3055 BUS_DMASYNC_POSTREAD); 3056 bus_dmamap_unload(sc->rxbuf_dtag, rxbuf->dmap); 3057 /* Prefetch mbuf header. */ 3058 mvneta_prefetch(m); 3059 3060 processed++; 3061 /* Drop desc with error status or not in a single buffer. */ 3062 DASSERT((r->status & (MVNETA_RX_F|MVNETA_RX_L)) == 3063 (MVNETA_RX_F|MVNETA_RX_L)); 3064 if (__predict_false((r->status & MVNETA_RX_ES) || 3065 (r->status & (MVNETA_RX_F|MVNETA_RX_L)) != 3066 (MVNETA_RX_F|MVNETA_RX_L))) 3067 goto rx_error; 3068 3069 /* 3070 * [ OFF | MH | PKT | CRC ] 3071 * bytecnt cover MH, PKT, CRC 3072 */ 3073 pktlen = r->bytecnt - ETHER_CRC_LEN - MVNETA_HWHEADER_SIZE; 3074 pktbuf = (uint8_t *)rx->rxbuf_virt_addr[rx->dma] + MVNETA_PACKET_OFFSET + 3075 MVNETA_HWHEADER_SIZE; 3076 3077 /* Prefetch mbuf data. */ 3078 mvneta_prefetch(pktbuf); 3079 3080 /* Write value to mbuf (avoid read). */ 3081 m->m_data = pktbuf; 3082 m->m_len = m->m_pkthdr.len = pktlen; 3083 m->m_pkthdr.rcvif = ifp; 3084 mvneta_rx_set_csumflag(ifp, r, m); 3085 3086 /* Increase rx_dma before releasing the lock. */ 3087 rx->dma = ndma; 3088 3089 if (__predict_false(rx->lro_enabled && 3090 ((r->status & MVNETA_RX_L3_IP) != 0) && 3091 ((r->status & MVNETA_RX_L4_MASK) == MVNETA_RX_L4_TCP) && 3092 (m->m_pkthdr.csum_flags & 3093 (CSUM_DATA_VALID | CSUM_PSEUDO_HDR)) == 3094 (CSUM_DATA_VALID | CSUM_PSEUDO_HDR))) { 3095 if (rx->lro.lro_cnt != 0) { 3096 if (tcp_lro_rx(&rx->lro, m, 0) == 0) 3097 goto rx_done; 3098 } 3099 } 3100 3101 mvneta_rx_unlockq(sc, q); 3102 (*ifp->if_input)(ifp, m); 3103 mvneta_rx_lockq(sc, q); 3104 /* 3105 * Check whether this queue has been disabled in the 3106 * meantime. If yes, then clear LRO and exit. 3107 */ 3108 if(__predict_false(rx->queue_status == MVNETA_QUEUE_DISABLED)) 3109 goto rx_lro; 3110 rx_done: 3111 /* Refresh receive ring to avoid stall and minimize jitter. */ 3112 if (processed >= MVNETA_RX_REFILL_COUNT) { 3113 mvneta_prxsu_update(sc, q, processed); 3114 mvneta_rx_queue_refill(sc, q); 3115 processed = 0; 3116 } 3117 continue; 3118 rx_error: 3119 m_freem(m); 3120 rx->dma = ndma; 3121 /* Refresh receive ring to avoid stall and minimize jitter. */ 3122 if (processed >= MVNETA_RX_REFILL_COUNT) { 3123 mvneta_prxsu_update(sc, q, processed); 3124 mvneta_rx_queue_refill(sc, q); 3125 processed = 0; 3126 } 3127 } 3128 #ifdef MVNETA_KTR 3129 CTR3(KTR_SPARE2, "%s:%u %u packets received", ifp->if_xname, q, npkt); 3130 #endif 3131 /* DMA status update */ 3132 mvneta_prxsu_update(sc, q, processed); 3133 /* Refill the rest of buffers if there are any to refill */ 3134 mvneta_rx_queue_refill(sc, q); 3135 3136 rx_lro: 3137 /* 3138 * Flush any outstanding LRO work 3139 */ 3140 lro = &rx->lro; 3141 while (__predict_false((queued = LIST_FIRST(&lro->lro_active)) != NULL)) { 3142 LIST_REMOVE(LIST_FIRST((&lro->lro_active)), next); 3143 tcp_lro_flush(lro, queued); 3144 } 3145 } 3146 3147 STATIC void 3148 mvneta_rx_buf_free(struct mvneta_softc *sc, struct mvneta_buf *rxbuf) 3149 { 3150 3151 bus_dmamap_unload(sc->rxbuf_dtag, rxbuf->dmap); 3152 /* This will remove all data at once */ 3153 m_freem(rxbuf->m); 3154 } 3155 3156 STATIC void 3157 mvneta_rx_queue_refill(struct mvneta_softc *sc, int q) 3158 { 3159 struct mvneta_rx_ring *rx; 3160 struct mvneta_rx_desc *r; 3161 struct mvneta_buf *rxbuf; 3162 bus_dma_segment_t segs; 3163 struct mbuf *m; 3164 uint32_t prxs, prxsu, ndesc; 3165 int npkt, refill, nsegs, error; 3166 3167 KASSERT_RX_MTX(sc, q); 3168 3169 rx = MVNETA_RX_RING(sc, q); 3170 prxs = MVNETA_READ(sc, MVNETA_PRXS(q)); 3171 ndesc = MVNETA_PRXS_GET_NODC(prxs) + MVNETA_PRXS_GET_ODC(prxs); 3172 refill = MVNETA_RX_RING_CNT - ndesc; 3173 #ifdef MVNETA_KTR 3174 CTR3(KTR_SPARE2, "%s:%u refill %u packets", sc->ifp->if_xname, q, 3175 refill); 3176 #endif 3177 if (__predict_false(refill <= 0)) 3178 return; 3179 3180 for (npkt = 0; npkt < refill; npkt++) { 3181 rxbuf = &rx->rxbuf[rx->cpu]; 3182 m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, sc->rx_frame_size); 3183 if (__predict_false(m == NULL)) { 3184 error = ENOBUFS; 3185 break; 3186 } 3187 m->m_len = m->m_pkthdr.len = m->m_ext.ext_size; 3188 3189 error = bus_dmamap_load_mbuf_sg(sc->rxbuf_dtag, rxbuf->dmap, 3190 m, &segs, &nsegs, BUS_DMA_NOWAIT); 3191 if (__predict_false(error != 0 || nsegs != 1)) { 3192 KASSERT(1, ("Failed to load Rx mbuf DMA map")); 3193 m_freem(m); 3194 break; 3195 } 3196 3197 /* Add the packet to the ring */ 3198 rxbuf->m = m; 3199 r = &rx->desc[rx->cpu]; 3200 r->bufptr_pa = segs.ds_addr; 3201 rx->rxbuf_virt_addr[rx->cpu] = m->m_data; 3202 3203 rx->cpu = rx_counter_adv(rx->cpu, 1); 3204 } 3205 if (npkt == 0) { 3206 if (refill == MVNETA_RX_RING_CNT) 3207 rx->needs_refill = TRUE; 3208 return; 3209 } 3210 3211 rx->needs_refill = FALSE; 3212 bus_dmamap_sync(sc->rx_dtag, rx->desc_map, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 3213 3214 while (__predict_false(npkt > 255)) { 3215 prxsu = MVNETA_PRXSU_NOOFNEWDESCRIPTORS(255); 3216 MVNETA_WRITE(sc, MVNETA_PRXSU(q), prxsu); 3217 npkt -= 255; 3218 } 3219 if (__predict_true(npkt > 0)) { 3220 prxsu = MVNETA_PRXSU_NOOFNEWDESCRIPTORS(npkt); 3221 MVNETA_WRITE(sc, MVNETA_PRXSU(q), prxsu); 3222 } 3223 } 3224 3225 STATIC __inline void 3226 mvneta_rx_set_csumflag(struct ifnet *ifp, 3227 struct mvneta_rx_desc *r, struct mbuf *m) 3228 { 3229 uint32_t csum_flags; 3230 3231 csum_flags = 0; 3232 if (__predict_false((r->status & 3233 (MVNETA_RX_IP_HEADER_OK|MVNETA_RX_L3_IP)) == 0)) 3234 return; /* not a IP packet */ 3235 3236 /* L3 */ 3237 if (__predict_true((r->status & MVNETA_RX_IP_HEADER_OK) == 3238 MVNETA_RX_IP_HEADER_OK)) 3239 csum_flags |= CSUM_L3_CALC|CSUM_L3_VALID; 3240 3241 if (__predict_true((r->status & (MVNETA_RX_IP_HEADER_OK|MVNETA_RX_L3_IP)) == 3242 (MVNETA_RX_IP_HEADER_OK|MVNETA_RX_L3_IP))) { 3243 /* L4 */ 3244 switch (r->status & MVNETA_RX_L4_MASK) { 3245 case MVNETA_RX_L4_TCP: 3246 case MVNETA_RX_L4_UDP: 3247 csum_flags |= CSUM_L4_CALC; 3248 if (__predict_true((r->status & 3249 MVNETA_RX_L4_CHECKSUM_OK) == MVNETA_RX_L4_CHECKSUM_OK)) { 3250 csum_flags |= CSUM_L4_VALID; 3251 m->m_pkthdr.csum_data = htons(0xffff); 3252 } 3253 break; 3254 case MVNETA_RX_L4_OTH: 3255 default: 3256 break; 3257 } 3258 } 3259 m->m_pkthdr.csum_flags = csum_flags; 3260 } 3261 3262 /* 3263 * MAC address filter 3264 */ 3265 STATIC void 3266 mvneta_filter_setup(struct mvneta_softc *sc) 3267 { 3268 struct ifnet *ifp; 3269 uint32_t dfut[MVNETA_NDFUT], dfsmt[MVNETA_NDFSMT], dfomt[MVNETA_NDFOMT]; 3270 uint32_t pxc; 3271 int i; 3272 3273 KASSERT_SC_MTX(sc); 3274 3275 memset(dfut, 0, sizeof(dfut)); 3276 memset(dfsmt, 0, sizeof(dfsmt)); 3277 memset(dfomt, 0, sizeof(dfomt)); 3278 3279 ifp = sc->ifp; 3280 ifp->if_flags |= IFF_ALLMULTI; 3281 if (ifp->if_flags & (IFF_ALLMULTI|IFF_PROMISC)) { 3282 for (i = 0; i < MVNETA_NDFSMT; i++) { 3283 dfsmt[i] = dfomt[i] = 3284 MVNETA_DF(0, MVNETA_DF_QUEUE(0) | MVNETA_DF_PASS) | 3285 MVNETA_DF(1, MVNETA_DF_QUEUE(0) | MVNETA_DF_PASS) | 3286 MVNETA_DF(2, MVNETA_DF_QUEUE(0) | MVNETA_DF_PASS) | 3287 MVNETA_DF(3, MVNETA_DF_QUEUE(0) | MVNETA_DF_PASS); 3288 } 3289 } 3290 3291 pxc = MVNETA_READ(sc, MVNETA_PXC); 3292 pxc &= ~(MVNETA_PXC_UPM | MVNETA_PXC_RXQ_MASK | MVNETA_PXC_RXQARP_MASK | 3293 MVNETA_PXC_TCPQ_MASK | MVNETA_PXC_UDPQ_MASK | MVNETA_PXC_BPDUQ_MASK); 3294 pxc |= MVNETA_PXC_RXQ(MVNETA_RX_QNUM_MAX-1); 3295 pxc |= MVNETA_PXC_RXQARP(MVNETA_RX_QNUM_MAX-1); 3296 pxc |= MVNETA_PXC_TCPQ(MVNETA_RX_QNUM_MAX-1); 3297 pxc |= MVNETA_PXC_UDPQ(MVNETA_RX_QNUM_MAX-1); 3298 pxc |= MVNETA_PXC_BPDUQ(MVNETA_RX_QNUM_MAX-1); 3299 pxc |= MVNETA_PXC_RB | MVNETA_PXC_RBIP | MVNETA_PXC_RBARP; 3300 if (ifp->if_flags & IFF_BROADCAST) { 3301 pxc &= ~(MVNETA_PXC_RB | MVNETA_PXC_RBIP | MVNETA_PXC_RBARP); 3302 } 3303 if (ifp->if_flags & IFF_PROMISC) { 3304 pxc |= MVNETA_PXC_UPM; 3305 } 3306 MVNETA_WRITE(sc, MVNETA_PXC, pxc); 3307 3308 /* Set Destination Address Filter Unicast Table */ 3309 if (ifp->if_flags & IFF_PROMISC) { 3310 /* pass all unicast addresses */ 3311 for (i = 0; i < MVNETA_NDFUT; i++) { 3312 dfut[i] = 3313 MVNETA_DF(0, MVNETA_DF_QUEUE(0) | MVNETA_DF_PASS) | 3314 MVNETA_DF(1, MVNETA_DF_QUEUE(0) | MVNETA_DF_PASS) | 3315 MVNETA_DF(2, MVNETA_DF_QUEUE(0) | MVNETA_DF_PASS) | 3316 MVNETA_DF(3, MVNETA_DF_QUEUE(0) | MVNETA_DF_PASS); 3317 } 3318 } else { 3319 i = sc->enaddr[5] & 0xf; /* last nibble */ 3320 dfut[i>>2] = MVNETA_DF(i&3, MVNETA_DF_QUEUE(0) | MVNETA_DF_PASS); 3321 } 3322 MVNETA_WRITE_REGION(sc, MVNETA_DFUT(0), dfut, MVNETA_NDFUT); 3323 3324 /* Set Destination Address Filter Multicast Tables */ 3325 MVNETA_WRITE_REGION(sc, MVNETA_DFSMT(0), dfsmt, MVNETA_NDFSMT); 3326 MVNETA_WRITE_REGION(sc, MVNETA_DFOMT(0), dfomt, MVNETA_NDFOMT); 3327 } 3328 3329 /* 3330 * sysctl(9) 3331 */ 3332 STATIC int 3333 sysctl_read_mib(SYSCTL_HANDLER_ARGS) 3334 { 3335 struct mvneta_sysctl_mib *arg; 3336 struct mvneta_softc *sc; 3337 uint64_t val; 3338 3339 arg = (struct mvneta_sysctl_mib *)arg1; 3340 if (arg == NULL) 3341 return (EINVAL); 3342 3343 sc = arg->sc; 3344 if (sc == NULL) 3345 return (EINVAL); 3346 if (arg->index < 0 || arg->index > MVNETA_PORTMIB_NOCOUNTER) 3347 return (EINVAL); 3348 3349 mvneta_sc_lock(sc); 3350 val = arg->counter; 3351 mvneta_sc_unlock(sc); 3352 return sysctl_handle_64(oidp, &val, 0, req); 3353 } 3354 3355 3356 STATIC int 3357 sysctl_clear_mib(SYSCTL_HANDLER_ARGS) 3358 { 3359 struct mvneta_softc *sc; 3360 int err, val; 3361 3362 val = 0; 3363 sc = (struct mvneta_softc *)arg1; 3364 if (sc == NULL) 3365 return (EINVAL); 3366 3367 err = sysctl_handle_int(oidp, &val, 0, req); 3368 if (err != 0) 3369 return (err); 3370 3371 if (val < 0 || val > 1) 3372 return (EINVAL); 3373 3374 if (val == 1) { 3375 mvneta_sc_lock(sc); 3376 mvneta_clear_mib(sc); 3377 mvneta_sc_unlock(sc); 3378 } 3379 3380 return (0); 3381 } 3382 3383 STATIC int 3384 sysctl_set_queue_rxthtime(SYSCTL_HANDLER_ARGS) 3385 { 3386 struct mvneta_sysctl_queue *arg; 3387 struct mvneta_rx_ring *rx; 3388 struct mvneta_softc *sc; 3389 uint32_t reg, time_mvtclk; 3390 int err, time_us; 3391 3392 rx = NULL; 3393 arg = (struct mvneta_sysctl_queue *)arg1; 3394 if (arg == NULL) 3395 return (EINVAL); 3396 if (arg->queue < 0 || arg->queue > MVNETA_RX_RING_CNT) 3397 return (EINVAL); 3398 if (arg->rxtx != MVNETA_SYSCTL_RX) 3399 return (EINVAL); 3400 3401 sc = arg->sc; 3402 if (sc == NULL) 3403 return (EINVAL); 3404 3405 /* read queue length */ 3406 mvneta_sc_lock(sc); 3407 mvneta_rx_lockq(sc, arg->queue); 3408 rx = MVNETA_RX_RING(sc, arg->queue); 3409 time_mvtclk = rx->queue_th_time; 3410 time_us = ((uint64_t)time_mvtclk * 1000ULL * 1000ULL) / mvneta_get_clk(); 3411 mvneta_rx_unlockq(sc, arg->queue); 3412 mvneta_sc_unlock(sc); 3413 3414 err = sysctl_handle_int(oidp, &time_us, 0, req); 3415 if (err != 0) 3416 return (err); 3417 3418 mvneta_sc_lock(sc); 3419 mvneta_rx_lockq(sc, arg->queue); 3420 3421 /* update queue length (0[sec] - 1[sec]) */ 3422 if (time_us < 0 || time_us > (1000 * 1000)) { 3423 mvneta_rx_unlockq(sc, arg->queue); 3424 mvneta_sc_unlock(sc); 3425 return (EINVAL); 3426 } 3427 time_mvtclk = 3428 (uint64_t)mvneta_get_clk() * (uint64_t)time_us / (1000ULL * 1000ULL); 3429 rx->queue_th_time = time_mvtclk; 3430 reg = MVNETA_PRXITTH_RITT(rx->queue_th_time); 3431 MVNETA_WRITE(sc, MVNETA_PRXITTH(arg->queue), reg); 3432 mvneta_rx_unlockq(sc, arg->queue); 3433 mvneta_sc_unlock(sc); 3434 3435 return (0); 3436 } 3437 3438 STATIC void 3439 sysctl_mvneta_init(struct mvneta_softc *sc) 3440 { 3441 struct sysctl_ctx_list *ctx; 3442 struct sysctl_oid_list *children; 3443 struct sysctl_oid_list *rxchildren; 3444 struct sysctl_oid_list *qchildren, *mchildren; 3445 struct sysctl_oid *tree; 3446 int i, q; 3447 struct mvneta_sysctl_queue *rxarg; 3448 #define MVNETA_SYSCTL_NAME(num) "queue" # num 3449 static const char *sysctl_queue_names[] = { 3450 MVNETA_SYSCTL_NAME(0), MVNETA_SYSCTL_NAME(1), 3451 MVNETA_SYSCTL_NAME(2), MVNETA_SYSCTL_NAME(3), 3452 MVNETA_SYSCTL_NAME(4), MVNETA_SYSCTL_NAME(5), 3453 MVNETA_SYSCTL_NAME(6), MVNETA_SYSCTL_NAME(7), 3454 }; 3455 #undef MVNETA_SYSCTL_NAME 3456 3457 #ifndef NO_SYSCTL_DESCR 3458 #define MVNETA_SYSCTL_DESCR(num) "configuration parameters for queue " # num 3459 static const char *sysctl_queue_descrs[] = { 3460 MVNETA_SYSCTL_DESCR(0), MVNETA_SYSCTL_DESCR(1), 3461 MVNETA_SYSCTL_DESCR(2), MVNETA_SYSCTL_DESCR(3), 3462 MVNETA_SYSCTL_DESCR(4), MVNETA_SYSCTL_DESCR(5), 3463 MVNETA_SYSCTL_DESCR(6), MVNETA_SYSCTL_DESCR(7), 3464 }; 3465 #undef MVNETA_SYSCTL_DESCR 3466 #endif 3467 3468 3469 ctx = device_get_sysctl_ctx(sc->dev); 3470 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)); 3471 3472 tree = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "rx", 3473 CTLFLAG_RD | CTLFLAG_MPSAFE, 0, "NETA RX"); 3474 rxchildren = SYSCTL_CHILDREN(tree); 3475 tree = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "mib", 3476 CTLFLAG_RD | CTLFLAG_MPSAFE, 0, "NETA MIB"); 3477 mchildren = SYSCTL_CHILDREN(tree); 3478 3479 3480 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "flow_control", 3481 CTLFLAG_RW, &sc->cf_fc, 0, "flow control"); 3482 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "lpi", 3483 CTLFLAG_RW, &sc->cf_lpi, 0, "Low Power Idle"); 3484 3485 /* 3486 * MIB access 3487 */ 3488 /* dev.mvneta.[unit].mib.<mibs> */ 3489 for (i = 0; i < MVNETA_PORTMIB_NOCOUNTER; i++) { 3490 struct mvneta_sysctl_mib *mib_arg = &sc->sysctl_mib[i]; 3491 3492 mib_arg->sc = sc; 3493 mib_arg->index = i; 3494 SYSCTL_ADD_PROC(ctx, mchildren, OID_AUTO, 3495 mvneta_mib_list[i].sysctl_name, 3496 CTLTYPE_U64 | CTLFLAG_RD | CTLFLAG_NEEDGIANT, 3497 (void *)mib_arg, 0, sysctl_read_mib, "I", 3498 mvneta_mib_list[i].desc); 3499 } 3500 SYSCTL_ADD_UQUAD(ctx, mchildren, OID_AUTO, "rx_discard", 3501 CTLFLAG_RD, &sc->counter_pdfc, "Port Rx Discard Frame Counter"); 3502 SYSCTL_ADD_UQUAD(ctx, mchildren, OID_AUTO, "overrun", 3503 CTLFLAG_RD, &sc->counter_pofc, "Port Overrun Frame Counter"); 3504 SYSCTL_ADD_UINT(ctx, mchildren, OID_AUTO, "watchdog", 3505 CTLFLAG_RD, &sc->counter_watchdog, 0, "TX Watchdog Counter"); 3506 3507 SYSCTL_ADD_PROC(ctx, mchildren, OID_AUTO, "reset", 3508 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 3509 (void *)sc, 0, sysctl_clear_mib, "I", "Reset MIB counters"); 3510 3511 for (q = 0; q < MVNETA_RX_QNUM_MAX; q++) { 3512 rxarg = &sc->sysctl_rx_queue[q]; 3513 3514 rxarg->sc = sc; 3515 rxarg->queue = q; 3516 rxarg->rxtx = MVNETA_SYSCTL_RX; 3517 3518 /* hw.mvneta.mvneta[unit].rx.[queue] */ 3519 tree = SYSCTL_ADD_NODE(ctx, rxchildren, OID_AUTO, 3520 sysctl_queue_names[q], CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 3521 sysctl_queue_descrs[q]); 3522 qchildren = SYSCTL_CHILDREN(tree); 3523 3524 /* hw.mvneta.mvneta[unit].rx.[queue].threshold_timer_us */ 3525 SYSCTL_ADD_PROC(ctx, qchildren, OID_AUTO, "threshold_timer_us", 3526 CTLTYPE_UINT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, rxarg, 0, 3527 sysctl_set_queue_rxthtime, "I", 3528 "interrupt coalescing threshold timer [us]"); 3529 } 3530 } 3531 3532 /* 3533 * MIB 3534 */ 3535 STATIC uint64_t 3536 mvneta_read_mib(struct mvneta_softc *sc, int index) 3537 { 3538 struct mvneta_mib_def *mib; 3539 uint64_t val; 3540 3541 mib = &mvneta_mib_list[index]; 3542 val = MVNETA_READ_MIB(sc, mib->regnum); 3543 if (mib->reg64) 3544 val |= (uint64_t)MVNETA_READ_MIB(sc, mib->regnum + 4) << 32; 3545 return (val); 3546 } 3547 3548 STATIC void 3549 mvneta_clear_mib(struct mvneta_softc *sc) 3550 { 3551 int i; 3552 3553 KASSERT_SC_MTX(sc); 3554 3555 for (i = 0; i < nitems(mvneta_mib_list); i++) { 3556 (void)mvneta_read_mib(sc, i); 3557 sc->sysctl_mib[i].counter = 0; 3558 } 3559 MVNETA_READ(sc, MVNETA_PDFC); 3560 sc->counter_pdfc = 0; 3561 MVNETA_READ(sc, MVNETA_POFC); 3562 sc->counter_pofc = 0; 3563 sc->counter_watchdog = 0; 3564 } 3565 3566 STATIC void 3567 mvneta_update_mib(struct mvneta_softc *sc) 3568 { 3569 struct mvneta_tx_ring *tx; 3570 int i; 3571 uint64_t val; 3572 uint32_t reg; 3573 3574 for (i = 0; i < nitems(mvneta_mib_list); i++) { 3575 3576 val = mvneta_read_mib(sc, i); 3577 if (val == 0) 3578 continue; 3579 3580 sc->sysctl_mib[i].counter += val; 3581 switch (mvneta_mib_list[i].regnum) { 3582 case MVNETA_MIB_RX_GOOD_OCT: 3583 if_inc_counter(sc->ifp, IFCOUNTER_IBYTES, val); 3584 break; 3585 case MVNETA_MIB_RX_BAD_FRAME: 3586 if_inc_counter(sc->ifp, IFCOUNTER_IERRORS, val); 3587 break; 3588 case MVNETA_MIB_RX_GOOD_FRAME: 3589 if_inc_counter(sc->ifp, IFCOUNTER_IPACKETS, val); 3590 break; 3591 case MVNETA_MIB_RX_MCAST_FRAME: 3592 if_inc_counter(sc->ifp, IFCOUNTER_IMCASTS, val); 3593 break; 3594 case MVNETA_MIB_TX_GOOD_OCT: 3595 if_inc_counter(sc->ifp, IFCOUNTER_OBYTES, val); 3596 break; 3597 case MVNETA_MIB_TX_GOOD_FRAME: 3598 if_inc_counter(sc->ifp, IFCOUNTER_OPACKETS, val); 3599 break; 3600 case MVNETA_MIB_TX_MCAST_FRAME: 3601 if_inc_counter(sc->ifp, IFCOUNTER_OMCASTS, val); 3602 break; 3603 case MVNETA_MIB_MAC_COL: 3604 if_inc_counter(sc->ifp, IFCOUNTER_COLLISIONS, val); 3605 break; 3606 case MVNETA_MIB_TX_MAC_TRNS_ERR: 3607 case MVNETA_MIB_TX_EXCES_COL: 3608 case MVNETA_MIB_MAC_LATE_COL: 3609 if_inc_counter(sc->ifp, IFCOUNTER_OERRORS, val); 3610 break; 3611 } 3612 } 3613 3614 reg = MVNETA_READ(sc, MVNETA_PDFC); 3615 sc->counter_pdfc += reg; 3616 if_inc_counter(sc->ifp, IFCOUNTER_IQDROPS, reg); 3617 reg = MVNETA_READ(sc, MVNETA_POFC); 3618 sc->counter_pofc += reg; 3619 if_inc_counter(sc->ifp, IFCOUNTER_IQDROPS, reg); 3620 3621 /* TX watchdog. */ 3622 if (sc->counter_watchdog_mib > 0) { 3623 if_inc_counter(sc->ifp, IFCOUNTER_OERRORS, sc->counter_watchdog_mib); 3624 sc->counter_watchdog_mib = 0; 3625 } 3626 /* 3627 * TX driver errors: 3628 * We do not take queue locks to not disrupt TX path. 3629 * We may only miss one drv error which will be fixed at 3630 * next mib update. We may also clear counter when TX path 3631 * is incrementing it but we only do it if counter was not zero 3632 * thus we may only loose one error. 3633 */ 3634 for (i = 0; i < MVNETA_TX_QNUM_MAX; i++) { 3635 tx = MVNETA_TX_RING(sc, i); 3636 3637 if (tx->drv_error > 0) { 3638 if_inc_counter(sc->ifp, IFCOUNTER_OERRORS, tx->drv_error); 3639 tx->drv_error = 0; 3640 } 3641 } 3642 } 3643