xref: /freebsd/sys/dev/my/if_my.c (revision ef544f631226436ef590825881e7a28369df82f6)
1 /*-
2  * Written by: yen_cw@myson.com.tw
3  * Copyright (c) 2002 Myson Technology Inc.
4  * All rights reserved.
5  *
6  * Redistribution and use in source and binary forms, with or without
7  * modification, are permitted provided that the following conditions
8  * are met:
9  * 1. Redistributions of source code must retain the above copyright
10  *    notice, this list of conditions, and the following disclaimer,
11  *    without modification, immediately at the beginning of the file.
12  * 2. The name of the author may not be used to endorse or promote products
13  *    derived from this software without specific prior written permission.
14  *
15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
19  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25  * SUCH DAMAGE.
26  *
27  * Myson fast ethernet PCI NIC driver, available at: http://www.myson.com.tw/
28  */
29 
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
32 
33 #include <sys/param.h>
34 #include <sys/systm.h>
35 #include <sys/sockio.h>
36 #include <sys/mbuf.h>
37 #include <sys/malloc.h>
38 #include <sys/kernel.h>
39 #include <sys/socket.h>
40 #include <sys/queue.h>
41 #include <sys/types.h>
42 #include <sys/bus.h>
43 #include <sys/module.h>
44 #include <sys/lock.h>
45 #include <sys/mutex.h>
46 
47 #define NBPFILTER	1
48 
49 #include <net/if.h>
50 #include <net/if_arp.h>
51 #include <net/ethernet.h>
52 #include <net/if_media.h>
53 #include <net/if_types.h>
54 #include <net/if_dl.h>
55 #include <net/bpf.h>
56 
57 #include <vm/vm.h>		/* for vtophys */
58 #include <vm/pmap.h>		/* for vtophys */
59 #include <machine/bus.h>
60 #include <machine/resource.h>
61 #include <sys/bus.h>
62 #include <sys/rman.h>
63 
64 #include <dev/pci/pcireg.h>
65 #include <dev/pci/pcivar.h>
66 
67 #include <dev/mii/mii.h>
68 #include <dev/mii/miivar.h>
69 
70 #include "miibus_if.h"
71 
72 /*
73  * #define MY_USEIOSPACE
74  */
75 
76 static int      MY_USEIOSPACE = 1;
77 
78 #ifdef MY_USEIOSPACE
79 #define MY_RES                  SYS_RES_IOPORT
80 #define MY_RID                  MY_PCI_LOIO
81 #else
82 #define MY_RES                  SYS_RES_MEMORY
83 #define MY_RID                  MY_PCI_LOMEM
84 #endif
85 
86 
87 #include <dev/my/if_myreg.h>
88 
89 #ifndef lint
90 static          const char rcsid[] =
91 "$Id: if_my.c,v 1.16 2003/04/15 06:37:25 mdodd Exp $";
92 #endif
93 
94 /*
95  * Various supported device vendors/types and their names.
96  */
97 struct my_type *my_info_tmp;
98 static struct my_type my_devs[] = {
99 	{MYSONVENDORID, MTD800ID, "Myson MTD80X Based Fast Ethernet Card"},
100 	{MYSONVENDORID, MTD803ID, "Myson MTD80X Based Fast Ethernet Card"},
101 	{MYSONVENDORID, MTD891ID, "Myson MTD89X Based Giga Ethernet Card"},
102 	{0, 0, NULL}
103 };
104 
105 /*
106  * Various supported PHY vendors/types and their names. Note that this driver
107  * will work with pretty much any MII-compliant PHY, so failure to positively
108  * identify the chip is not a fatal error.
109  */
110 static struct my_type my_phys[] = {
111 	{MysonPHYID0, MysonPHYID0, "<MYSON MTD981>"},
112 	{SeeqPHYID0, SeeqPHYID0, "<SEEQ 80225>"},
113 	{AhdocPHYID0, AhdocPHYID0, "<AHDOC 101>"},
114 	{MarvellPHYID0, MarvellPHYID0, "<MARVELL 88E1000>"},
115 	{LevelOnePHYID0, LevelOnePHYID0, "<LevelOne LXT1000>"},
116 	{0, 0, "<MII-compliant physical interface>"}
117 };
118 
119 static int      my_probe(device_t);
120 static int      my_attach(device_t);
121 static int      my_detach(device_t);
122 static int      my_newbuf(struct my_softc *, struct my_chain_onefrag *);
123 static int      my_encap(struct my_softc *, struct my_chain *, struct mbuf *);
124 static void     my_rxeof(struct my_softc *);
125 static void     my_txeof(struct my_softc *);
126 static void     my_txeoc(struct my_softc *);
127 static void     my_intr(void *);
128 static void     my_start(struct ifnet *);
129 static void     my_start_locked(struct ifnet *);
130 static int      my_ioctl(struct ifnet *, u_long, caddr_t);
131 static void     my_init(void *);
132 static void     my_init_locked(struct my_softc *);
133 static void     my_stop(struct my_softc *);
134 static void     my_watchdog(struct ifnet *);
135 static void     my_shutdown(device_t);
136 static int      my_ifmedia_upd(struct ifnet *);
137 static void     my_ifmedia_sts(struct ifnet *, struct ifmediareq *);
138 static u_int16_t my_phy_readreg(struct my_softc *, int);
139 static void     my_phy_writereg(struct my_softc *, int, int);
140 static void     my_autoneg_xmit(struct my_softc *);
141 static void     my_autoneg_mii(struct my_softc *, int, int);
142 static void     my_setmode_mii(struct my_softc *, int);
143 static void     my_getmode_mii(struct my_softc *);
144 static void     my_setcfg(struct my_softc *, int);
145 static void     my_setmulti(struct my_softc *);
146 static void     my_reset(struct my_softc *);
147 static int      my_list_rx_init(struct my_softc *);
148 static int      my_list_tx_init(struct my_softc *);
149 static long     my_send_cmd_to_phy(struct my_softc *, int, int);
150 
151 #define MY_SETBIT(sc, reg, x) CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))
152 #define MY_CLRBIT(sc, reg, x) CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
153 
154 static device_method_t my_methods[] = {
155 	/* Device interface */
156 	DEVMETHOD(device_probe, my_probe),
157 	DEVMETHOD(device_attach, my_attach),
158 	DEVMETHOD(device_detach, my_detach),
159 	DEVMETHOD(device_shutdown, my_shutdown),
160 
161 	{0, 0}
162 };
163 
164 static driver_t my_driver = {
165 	"my",
166 	my_methods,
167 	sizeof(struct my_softc)
168 };
169 
170 static devclass_t my_devclass;
171 
172 DRIVER_MODULE(my, pci, my_driver, my_devclass, 0, 0);
173 MODULE_DEPEND(my, pci, 1, 1, 1);
174 MODULE_DEPEND(my, ether, 1, 1, 1);
175 
176 static long
177 my_send_cmd_to_phy(struct my_softc * sc, int opcode, int regad)
178 {
179 	long            miir;
180 	int             i;
181 	int             mask, data;
182 
183 	MY_LOCK_ASSERT(sc);
184 
185 	/* enable MII output */
186 	miir = CSR_READ_4(sc, MY_MANAGEMENT);
187 	miir &= 0xfffffff0;
188 
189 	miir |= MY_MASK_MIIR_MII_WRITE + MY_MASK_MIIR_MII_MDO;
190 
191 	/* send 32 1's preamble */
192 	for (i = 0; i < 32; i++) {
193 		/* low MDC; MDO is already high (miir) */
194 		miir &= ~MY_MASK_MIIR_MII_MDC;
195 		CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
196 
197 		/* high MDC */
198 		miir |= MY_MASK_MIIR_MII_MDC;
199 		CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
200 	}
201 
202 	/* calculate ST+OP+PHYAD+REGAD+TA */
203 	data = opcode | (sc->my_phy_addr << 7) | (regad << 2);
204 
205 	/* sent out */
206 	mask = 0x8000;
207 	while (mask) {
208 		/* low MDC, prepare MDO */
209 		miir &= ~(MY_MASK_MIIR_MII_MDC + MY_MASK_MIIR_MII_MDO);
210 		if (mask & data)
211 			miir |= MY_MASK_MIIR_MII_MDO;
212 
213 		CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
214 		/* high MDC */
215 		miir |= MY_MASK_MIIR_MII_MDC;
216 		CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
217 		DELAY(30);
218 
219 		/* next */
220 		mask >>= 1;
221 		if (mask == 0x2 && opcode == MY_OP_READ)
222 			miir &= ~MY_MASK_MIIR_MII_WRITE;
223 	}
224 
225 	return miir;
226 }
227 
228 
229 static u_int16_t
230 my_phy_readreg(struct my_softc * sc, int reg)
231 {
232 	long            miir;
233 	int             mask, data;
234 
235 	MY_LOCK_ASSERT(sc);
236 
237 	if (sc->my_info->my_did == MTD803ID)
238 		data = CSR_READ_2(sc, MY_PHYBASE + reg * 2);
239 	else {
240 		miir = my_send_cmd_to_phy(sc, MY_OP_READ, reg);
241 
242 		/* read data */
243 		mask = 0x8000;
244 		data = 0;
245 		while (mask) {
246 			/* low MDC */
247 			miir &= ~MY_MASK_MIIR_MII_MDC;
248 			CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
249 
250 			/* read MDI */
251 			miir = CSR_READ_4(sc, MY_MANAGEMENT);
252 			if (miir & MY_MASK_MIIR_MII_MDI)
253 				data |= mask;
254 
255 			/* high MDC, and wait */
256 			miir |= MY_MASK_MIIR_MII_MDC;
257 			CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
258 			DELAY(30);
259 
260 			/* next */
261 			mask >>= 1;
262 		}
263 
264 		/* low MDC */
265 		miir &= ~MY_MASK_MIIR_MII_MDC;
266 		CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
267 	}
268 
269 	return (u_int16_t) data;
270 }
271 
272 
273 static void
274 my_phy_writereg(struct my_softc * sc, int reg, int data)
275 {
276 	long            miir;
277 	int             mask;
278 
279 	MY_LOCK_ASSERT(sc);
280 
281 	if (sc->my_info->my_did == MTD803ID)
282 		CSR_WRITE_2(sc, MY_PHYBASE + reg * 2, data);
283 	else {
284 		miir = my_send_cmd_to_phy(sc, MY_OP_WRITE, reg);
285 
286 		/* write data */
287 		mask = 0x8000;
288 		while (mask) {
289 			/* low MDC, prepare MDO */
290 			miir &= ~(MY_MASK_MIIR_MII_MDC + MY_MASK_MIIR_MII_MDO);
291 			if (mask & data)
292 				miir |= MY_MASK_MIIR_MII_MDO;
293 			CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
294 			DELAY(1);
295 
296 			/* high MDC */
297 			miir |= MY_MASK_MIIR_MII_MDC;
298 			CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
299 			DELAY(1);
300 
301 			/* next */
302 			mask >>= 1;
303 		}
304 
305 		/* low MDC */
306 		miir &= ~MY_MASK_MIIR_MII_MDC;
307 		CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
308 	}
309 	return;
310 }
311 
312 
313 /*
314  * Program the 64-bit multicast hash filter.
315  */
316 static void
317 my_setmulti(struct my_softc * sc)
318 {
319 	struct ifnet   *ifp;
320 	int             h = 0;
321 	u_int32_t       hashes[2] = {0, 0};
322 	struct ifmultiaddr *ifma;
323 	u_int32_t       rxfilt;
324 	int             mcnt = 0;
325 
326 	MY_LOCK_ASSERT(sc);
327 
328 	ifp = sc->my_ifp;
329 
330 	rxfilt = CSR_READ_4(sc, MY_TCRRCR);
331 
332 	if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
333 		rxfilt |= MY_AM;
334 		CSR_WRITE_4(sc, MY_TCRRCR, rxfilt);
335 		CSR_WRITE_4(sc, MY_MAR0, 0xFFFFFFFF);
336 		CSR_WRITE_4(sc, MY_MAR1, 0xFFFFFFFF);
337 
338 		return;
339 	}
340 	/* first, zot all the existing hash bits */
341 	CSR_WRITE_4(sc, MY_MAR0, 0);
342 	CSR_WRITE_4(sc, MY_MAR1, 0);
343 
344 	/* now program new ones */
345 	IF_ADDR_LOCK(ifp);
346 	TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
347 		if (ifma->ifma_addr->sa_family != AF_LINK)
348 			continue;
349 		h = ~ether_crc32_be(LLADDR((struct sockaddr_dl *)
350 		    ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
351 		if (h < 32)
352 			hashes[0] |= (1 << h);
353 		else
354 			hashes[1] |= (1 << (h - 32));
355 		mcnt++;
356 	}
357 	IF_ADDR_UNLOCK(ifp);
358 
359 	if (mcnt)
360 		rxfilt |= MY_AM;
361 	else
362 		rxfilt &= ~MY_AM;
363 	CSR_WRITE_4(sc, MY_MAR0, hashes[0]);
364 	CSR_WRITE_4(sc, MY_MAR1, hashes[1]);
365 	CSR_WRITE_4(sc, MY_TCRRCR, rxfilt);
366 	return;
367 }
368 
369 /*
370  * Initiate an autonegotiation session.
371  */
372 static void
373 my_autoneg_xmit(struct my_softc * sc)
374 {
375 	u_int16_t       phy_sts = 0;
376 
377 	MY_LOCK_ASSERT(sc);
378 
379 	my_phy_writereg(sc, PHY_BMCR, PHY_BMCR_RESET);
380 	DELAY(500);
381 	while (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_RESET);
382 
383 	phy_sts = my_phy_readreg(sc, PHY_BMCR);
384 	phy_sts |= PHY_BMCR_AUTONEGENBL | PHY_BMCR_AUTONEGRSTR;
385 	my_phy_writereg(sc, PHY_BMCR, phy_sts);
386 
387 	return;
388 }
389 
390 
391 /*
392  * Invoke autonegotiation on a PHY.
393  */
394 static void
395 my_autoneg_mii(struct my_softc * sc, int flag, int verbose)
396 {
397 	u_int16_t       phy_sts = 0, media, advert, ability;
398 	u_int16_t       ability2 = 0;
399 	struct ifnet   *ifp;
400 	struct ifmedia *ifm;
401 
402 	MY_LOCK_ASSERT(sc);
403 
404 	ifm = &sc->ifmedia;
405 	ifp = sc->my_ifp;
406 
407 	ifm->ifm_media = IFM_ETHER | IFM_AUTO;
408 
409 #ifndef FORCE_AUTONEG_TFOUR
410 	/*
411 	 * First, see if autoneg is supported. If not, there's no point in
412 	 * continuing.
413 	 */
414 	phy_sts = my_phy_readreg(sc, PHY_BMSR);
415 	if (!(phy_sts & PHY_BMSR_CANAUTONEG)) {
416 		if (verbose)
417 			device_printf(sc->my_dev,
418 			    "autonegotiation not supported\n");
419 		ifm->ifm_media = IFM_ETHER | IFM_10_T | IFM_HDX;
420 		return;
421 	}
422 #endif
423 	switch (flag) {
424 	case MY_FLAG_FORCEDELAY:
425 		/*
426 		 * XXX Never use this option anywhere but in the probe
427 		 * routine: making the kernel stop dead in its tracks for
428 		 * three whole seconds after we've gone multi-user is really
429 		 * bad manners.
430 		 */
431 		my_autoneg_xmit(sc);
432 		DELAY(5000000);
433 		break;
434 	case MY_FLAG_SCHEDDELAY:
435 		/*
436 		 * Wait for the transmitter to go idle before starting an
437 		 * autoneg session, otherwise my_start() may clobber our
438 		 * timeout, and we don't want to allow transmission during an
439 		 * autoneg session since that can screw it up.
440 		 */
441 		if (sc->my_cdata.my_tx_head != NULL) {
442 			sc->my_want_auto = 1;
443 			MY_UNLOCK(sc);
444 			return;
445 		}
446 		my_autoneg_xmit(sc);
447 		ifp->if_timer = 5;
448 		sc->my_autoneg = 1;
449 		sc->my_want_auto = 0;
450 		return;
451 	case MY_FLAG_DELAYTIMEO:
452 		ifp->if_timer = 0;
453 		sc->my_autoneg = 0;
454 		break;
455 	default:
456 		device_printf(sc->my_dev, "invalid autoneg flag: %d\n", flag);
457 		return;
458 	}
459 
460 	if (my_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_AUTONEGCOMP) {
461 		if (verbose)
462 			device_printf(sc->my_dev, "autoneg complete, ");
463 		phy_sts = my_phy_readreg(sc, PHY_BMSR);
464 	} else {
465 		if (verbose)
466 			device_printf(sc->my_dev, "autoneg not complete, ");
467 	}
468 
469 	media = my_phy_readreg(sc, PHY_BMCR);
470 
471 	/* Link is good. Report modes and set duplex mode. */
472 	if (my_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT) {
473 		if (verbose)
474 			device_printf(sc->my_dev, "link status good. ");
475 		advert = my_phy_readreg(sc, PHY_ANAR);
476 		ability = my_phy_readreg(sc, PHY_LPAR);
477 		if ((sc->my_pinfo->my_vid == MarvellPHYID0) ||
478 		    (sc->my_pinfo->my_vid == LevelOnePHYID0)) {
479 			ability2 = my_phy_readreg(sc, PHY_1000SR);
480 			if (ability2 & PHY_1000SR_1000BTXFULL) {
481 				advert = 0;
482 				ability = 0;
483 				/*
484 				 * this version did not support 1000M,
485 				 * ifm->ifm_media =
486 				 * IFM_ETHER|IFM_1000_T|IFM_FDX;
487 				 */
488 				ifm->ifm_media =
489 				    IFM_ETHER | IFM_100_TX | IFM_FDX;
490 				media &= ~PHY_BMCR_SPEEDSEL;
491 				media |= PHY_BMCR_1000;
492 				media |= PHY_BMCR_DUPLEX;
493 				printf("(full-duplex, 1000Mbps)\n");
494 			} else if (ability2 & PHY_1000SR_1000BTXHALF) {
495 				advert = 0;
496 				ability = 0;
497 				/*
498 				 * this version did not support 1000M,
499 				 * ifm->ifm_media = IFM_ETHER|IFM_1000_T;
500 				 */
501 				ifm->ifm_media = IFM_ETHER | IFM_100_TX;
502 				media &= ~PHY_BMCR_SPEEDSEL;
503 				media &= ~PHY_BMCR_DUPLEX;
504 				media |= PHY_BMCR_1000;
505 				printf("(half-duplex, 1000Mbps)\n");
506 			}
507 		}
508 		if (advert & PHY_ANAR_100BT4 && ability & PHY_ANAR_100BT4) {
509 			ifm->ifm_media = IFM_ETHER | IFM_100_T4;
510 			media |= PHY_BMCR_SPEEDSEL;
511 			media &= ~PHY_BMCR_DUPLEX;
512 			printf("(100baseT4)\n");
513 		} else if (advert & PHY_ANAR_100BTXFULL &&
514 			   ability & PHY_ANAR_100BTXFULL) {
515 			ifm->ifm_media = IFM_ETHER | IFM_100_TX | IFM_FDX;
516 			media |= PHY_BMCR_SPEEDSEL;
517 			media |= PHY_BMCR_DUPLEX;
518 			printf("(full-duplex, 100Mbps)\n");
519 		} else if (advert & PHY_ANAR_100BTXHALF &&
520 			   ability & PHY_ANAR_100BTXHALF) {
521 			ifm->ifm_media = IFM_ETHER | IFM_100_TX | IFM_HDX;
522 			media |= PHY_BMCR_SPEEDSEL;
523 			media &= ~PHY_BMCR_DUPLEX;
524 			printf("(half-duplex, 100Mbps)\n");
525 		} else if (advert & PHY_ANAR_10BTFULL &&
526 			   ability & PHY_ANAR_10BTFULL) {
527 			ifm->ifm_media = IFM_ETHER | IFM_10_T | IFM_FDX;
528 			media &= ~PHY_BMCR_SPEEDSEL;
529 			media |= PHY_BMCR_DUPLEX;
530 			printf("(full-duplex, 10Mbps)\n");
531 		} else if (advert) {
532 			ifm->ifm_media = IFM_ETHER | IFM_10_T | IFM_HDX;
533 			media &= ~PHY_BMCR_SPEEDSEL;
534 			media &= ~PHY_BMCR_DUPLEX;
535 			printf("(half-duplex, 10Mbps)\n");
536 		}
537 		media &= ~PHY_BMCR_AUTONEGENBL;
538 
539 		/* Set ASIC's duplex mode to match the PHY. */
540 		my_phy_writereg(sc, PHY_BMCR, media);
541 		my_setcfg(sc, media);
542 	} else {
543 		if (verbose)
544 			device_printf(sc->my_dev, "no carrier\n");
545 	}
546 
547 	my_init_locked(sc);
548 	if (sc->my_tx_pend) {
549 		sc->my_autoneg = 0;
550 		sc->my_tx_pend = 0;
551 		my_start_locked(ifp);
552 	}
553 	return;
554 }
555 
556 /*
557  * To get PHY ability.
558  */
559 static void
560 my_getmode_mii(struct my_softc * sc)
561 {
562 	u_int16_t       bmsr;
563 	struct ifnet   *ifp;
564 
565 	MY_LOCK_ASSERT(sc);
566 	ifp = sc->my_ifp;
567 	bmsr = my_phy_readreg(sc, PHY_BMSR);
568 	if (bootverbose)
569 		device_printf(sc->my_dev, "PHY status word: %x\n", bmsr);
570 
571 	/* fallback */
572 	sc->ifmedia.ifm_media = IFM_ETHER | IFM_10_T | IFM_HDX;
573 
574 	if (bmsr & PHY_BMSR_10BTHALF) {
575 		if (bootverbose)
576 			device_printf(sc->my_dev,
577 			    "10Mbps half-duplex mode supported\n");
578 		ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_10_T | IFM_HDX,
579 		    0, NULL);
580 		ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_10_T, 0, NULL);
581 	}
582 	if (bmsr & PHY_BMSR_10BTFULL) {
583 		if (bootverbose)
584 			device_printf(sc->my_dev,
585 			    "10Mbps full-duplex mode supported\n");
586 
587 		ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_10_T | IFM_FDX,
588 		    0, NULL);
589 		sc->ifmedia.ifm_media = IFM_ETHER | IFM_10_T | IFM_FDX;
590 	}
591 	if (bmsr & PHY_BMSR_100BTXHALF) {
592 		if (bootverbose)
593 			device_printf(sc->my_dev,
594 			    "100Mbps half-duplex mode supported\n");
595 		ifp->if_baudrate = 100000000;
596 		ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_TX, 0, NULL);
597 		ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_TX | IFM_HDX,
598 			    0, NULL);
599 		sc->ifmedia.ifm_media = IFM_ETHER | IFM_100_TX | IFM_HDX;
600 	}
601 	if (bmsr & PHY_BMSR_100BTXFULL) {
602 		if (bootverbose)
603 			device_printf(sc->my_dev,
604 			    "100Mbps full-duplex mode supported\n");
605 		ifp->if_baudrate = 100000000;
606 		ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_TX | IFM_FDX,
607 		    0, NULL);
608 		sc->ifmedia.ifm_media = IFM_ETHER | IFM_100_TX | IFM_FDX;
609 	}
610 	/* Some also support 100BaseT4. */
611 	if (bmsr & PHY_BMSR_100BT4) {
612 		if (bootverbose)
613 			device_printf(sc->my_dev, "100baseT4 mode supported\n");
614 		ifp->if_baudrate = 100000000;
615 		ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_T4, 0, NULL);
616 		sc->ifmedia.ifm_media = IFM_ETHER | IFM_100_T4;
617 #ifdef FORCE_AUTONEG_TFOUR
618 		if (bootverbose)
619 			device_printf(sc->my_dev,
620 			    "forcing on autoneg support for BT4\n");
621 		ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_AUTO, 0 NULL):
622 		sc->ifmedia.ifm_media = IFM_ETHER | IFM_AUTO;
623 #endif
624 	}
625 #if 0				/* this version did not support 1000M, */
626 	if (sc->my_pinfo->my_vid == MarvellPHYID0) {
627 		if (bootverbose)
628 			device_printf(sc->my_dev,
629 			    "1000Mbps half-duplex mode supported\n");
630 
631 		ifp->if_baudrate = 1000000000;
632 		ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_T, 0, NULL);
633 		ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_T | IFM_HDX,
634 		    0, NULL);
635 		if (bootverbose)
636 			device_printf(sc->my_dev,
637 			    "1000Mbps full-duplex mode supported\n");
638 		ifp->if_baudrate = 1000000000;
639 		ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_T | IFM_FDX,
640 		    0, NULL);
641 		sc->ifmedia.ifm_media = IFM_ETHER | IFM_1000_T | IFM_FDX;
642 	}
643 #endif
644 	if (bmsr & PHY_BMSR_CANAUTONEG) {
645 		if (bootverbose)
646 			device_printf(sc->my_dev, "autoneg supported\n");
647 		ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL);
648 		sc->ifmedia.ifm_media = IFM_ETHER | IFM_AUTO;
649 	}
650 	return;
651 }
652 
653 /*
654  * Set speed and duplex mode.
655  */
656 static void
657 my_setmode_mii(struct my_softc * sc, int media)
658 {
659 	u_int16_t       bmcr;
660 	struct ifnet   *ifp;
661 
662 	MY_LOCK_ASSERT(sc);
663 	ifp = sc->my_ifp;
664 	/*
665 	 * If an autoneg session is in progress, stop it.
666 	 */
667 	if (sc->my_autoneg) {
668 		device_printf(sc->my_dev, "canceling autoneg session\n");
669 		ifp->if_timer = sc->my_autoneg = sc->my_want_auto = 0;
670 		bmcr = my_phy_readreg(sc, PHY_BMCR);
671 		bmcr &= ~PHY_BMCR_AUTONEGENBL;
672 		my_phy_writereg(sc, PHY_BMCR, bmcr);
673 	}
674 	device_printf(sc->my_dev, "selecting MII, ");
675 	bmcr = my_phy_readreg(sc, PHY_BMCR);
676 	bmcr &= ~(PHY_BMCR_AUTONEGENBL | PHY_BMCR_SPEEDSEL | PHY_BMCR_1000 |
677 		  PHY_BMCR_DUPLEX | PHY_BMCR_LOOPBK);
678 
679 #if 0				/* this version did not support 1000M, */
680 	if (IFM_SUBTYPE(media) == IFM_1000_T) {
681 		printf("1000Mbps/T4, half-duplex\n");
682 		bmcr &= ~PHY_BMCR_SPEEDSEL;
683 		bmcr &= ~PHY_BMCR_DUPLEX;
684 		bmcr |= PHY_BMCR_1000;
685 	}
686 #endif
687 	if (IFM_SUBTYPE(media) == IFM_100_T4) {
688 		printf("100Mbps/T4, half-duplex\n");
689 		bmcr |= PHY_BMCR_SPEEDSEL;
690 		bmcr &= ~PHY_BMCR_DUPLEX;
691 	}
692 	if (IFM_SUBTYPE(media) == IFM_100_TX) {
693 		printf("100Mbps, ");
694 		bmcr |= PHY_BMCR_SPEEDSEL;
695 	}
696 	if (IFM_SUBTYPE(media) == IFM_10_T) {
697 		printf("10Mbps, ");
698 		bmcr &= ~PHY_BMCR_SPEEDSEL;
699 	}
700 	if ((media & IFM_GMASK) == IFM_FDX) {
701 		printf("full duplex\n");
702 		bmcr |= PHY_BMCR_DUPLEX;
703 	} else {
704 		printf("half duplex\n");
705 		bmcr &= ~PHY_BMCR_DUPLEX;
706 	}
707 	my_phy_writereg(sc, PHY_BMCR, bmcr);
708 	my_setcfg(sc, bmcr);
709 	return;
710 }
711 
712 /*
713  * The Myson manual states that in order to fiddle with the 'full-duplex' and
714  * '100Mbps' bits in the netconfig register, we first have to put the
715  * transmit and/or receive logic in the idle state.
716  */
717 static void
718 my_setcfg(struct my_softc * sc, int bmcr)
719 {
720 	int             i, restart = 0;
721 
722 	MY_LOCK_ASSERT(sc);
723 	if (CSR_READ_4(sc, MY_TCRRCR) & (MY_TE | MY_RE)) {
724 		restart = 1;
725 		MY_CLRBIT(sc, MY_TCRRCR, (MY_TE | MY_RE));
726 		for (i = 0; i < MY_TIMEOUT; i++) {
727 			DELAY(10);
728 			if (!(CSR_READ_4(sc, MY_TCRRCR) &
729 			    (MY_TXRUN | MY_RXRUN)))
730 				break;
731 		}
732 		if (i == MY_TIMEOUT)
733 			device_printf(sc->my_dev,
734 			    "failed to force tx and rx to idle \n");
735 	}
736 	MY_CLRBIT(sc, MY_TCRRCR, MY_PS1000);
737 	MY_CLRBIT(sc, MY_TCRRCR, MY_PS10);
738 	if (bmcr & PHY_BMCR_1000)
739 		MY_SETBIT(sc, MY_TCRRCR, MY_PS1000);
740 	else if (!(bmcr & PHY_BMCR_SPEEDSEL))
741 		MY_SETBIT(sc, MY_TCRRCR, MY_PS10);
742 	if (bmcr & PHY_BMCR_DUPLEX)
743 		MY_SETBIT(sc, MY_TCRRCR, MY_FD);
744 	else
745 		MY_CLRBIT(sc, MY_TCRRCR, MY_FD);
746 	if (restart)
747 		MY_SETBIT(sc, MY_TCRRCR, MY_TE | MY_RE);
748 	return;
749 }
750 
751 static void
752 my_reset(struct my_softc * sc)
753 {
754 	register int    i;
755 
756 	MY_LOCK_ASSERT(sc);
757 	MY_SETBIT(sc, MY_BCR, MY_SWR);
758 	for (i = 0; i < MY_TIMEOUT; i++) {
759 		DELAY(10);
760 		if (!(CSR_READ_4(sc, MY_BCR) & MY_SWR))
761 			break;
762 	}
763 	if (i == MY_TIMEOUT)
764 		device_printf(sc->my_dev, "reset never completed!\n");
765 
766 	/* Wait a little while for the chip to get its brains in order. */
767 	DELAY(1000);
768 	return;
769 }
770 
771 /*
772  * Probe for a Myson chip. Check the PCI vendor and device IDs against our
773  * list and return a device name if we find a match.
774  */
775 static int
776 my_probe(device_t dev)
777 {
778 	struct my_type *t;
779 
780 	t = my_devs;
781 	while (t->my_name != NULL) {
782 		if ((pci_get_vendor(dev) == t->my_vid) &&
783 		    (pci_get_device(dev) == t->my_did)) {
784 			device_set_desc(dev, t->my_name);
785 			my_info_tmp = t;
786 			return (BUS_PROBE_DEFAULT);
787 		}
788 		t++;
789 	}
790 	return (ENXIO);
791 }
792 
793 /*
794  * Attach the interface. Allocate softc structures, do ifmedia setup and
795  * ethernet/BPF attach.
796  */
797 static int
798 my_attach(device_t dev)
799 {
800 	int             i;
801 	u_char          eaddr[ETHER_ADDR_LEN];
802 	u_int32_t       iobase;
803 	struct my_softc *sc;
804 	struct ifnet   *ifp;
805 	int             media = IFM_ETHER | IFM_100_TX | IFM_FDX;
806 	unsigned int    round;
807 	caddr_t         roundptr;
808 	struct my_type *p;
809 	u_int16_t       phy_vid, phy_did, phy_sts = 0;
810 	int             rid, error = 0;
811 
812 	sc = device_get_softc(dev);
813 	sc->my_dev = dev;
814 	mtx_init(&sc->my_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
815 	    MTX_DEF);
816 
817 	/*
818 	 * Map control/status registers.
819 	 */
820 	pci_enable_busmaster(dev);
821 
822 	if (my_info_tmp->my_did == MTD800ID) {
823 		iobase = pci_read_config(dev, MY_PCI_LOIO, 4);
824 		if (iobase & 0x300)
825 			MY_USEIOSPACE = 0;
826 	}
827 
828 	rid = MY_RID;
829 	sc->my_res = bus_alloc_resource_any(dev, MY_RES, &rid, RF_ACTIVE);
830 
831 	if (sc->my_res == NULL) {
832 		device_printf(dev, "couldn't map ports/memory\n");
833 		error = ENXIO;
834 		goto destroy_mutex;
835 	}
836 	sc->my_btag = rman_get_bustag(sc->my_res);
837 	sc->my_bhandle = rman_get_bushandle(sc->my_res);
838 
839 	rid = 0;
840 	sc->my_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
841 					    RF_SHAREABLE | RF_ACTIVE);
842 
843 	if (sc->my_irq == NULL) {
844 		device_printf(dev, "couldn't map interrupt\n");
845 		error = ENXIO;
846 		goto release_io;
847 	}
848 
849 	sc->my_info = my_info_tmp;
850 
851 	/* Reset the adapter. */
852 	MY_LOCK(sc);
853 	my_reset(sc);
854 	MY_UNLOCK(sc);
855 
856 	/*
857 	 * Get station address
858 	 */
859 	for (i = 0; i < ETHER_ADDR_LEN; ++i)
860 		eaddr[i] = CSR_READ_1(sc, MY_PAR0 + i);
861 
862 	sc->my_ldata_ptr = malloc(sizeof(struct my_list_data) + 8,
863 				  M_DEVBUF, M_NOWAIT);
864 	if (sc->my_ldata_ptr == NULL) {
865 		device_printf(dev, "no memory for list buffers!\n");
866 		error = ENXIO;
867 		goto release_irq;
868 	}
869 	sc->my_ldata = (struct my_list_data *) sc->my_ldata_ptr;
870 	round = (uintptr_t)sc->my_ldata_ptr & 0xF;
871 	roundptr = sc->my_ldata_ptr;
872 	for (i = 0; i < 8; i++) {
873 		if (round % 8) {
874 			round++;
875 			roundptr++;
876 		} else
877 			break;
878 	}
879 	sc->my_ldata = (struct my_list_data *) roundptr;
880 	bzero(sc->my_ldata, sizeof(struct my_list_data));
881 
882 	ifp = sc->my_ifp = if_alloc(IFT_ETHER);
883 	if (ifp == NULL) {
884 		device_printf(dev, "can not if_alloc()\n");
885 		error = ENOSPC;
886 		goto free_ldata;
887 	}
888 	ifp->if_softc = sc;
889 	if_initname(ifp, device_get_name(dev), device_get_unit(dev));
890 	ifp->if_mtu = ETHERMTU;
891 	ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
892 	ifp->if_ioctl = my_ioctl;
893 	ifp->if_start = my_start;
894 	ifp->if_watchdog = my_watchdog;
895 	ifp->if_init = my_init;
896 	ifp->if_baudrate = 10000000;
897 	IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN);
898 	ifp->if_snd.ifq_drv_maxlen = IFQ_MAXLEN;
899 	IFQ_SET_READY(&ifp->if_snd);
900 
901 	if (sc->my_info->my_did == MTD803ID)
902 		sc->my_pinfo = my_phys;
903 	else {
904 		if (bootverbose)
905 			device_printf(dev, "probing for a PHY\n");
906 		MY_LOCK(sc);
907 		for (i = MY_PHYADDR_MIN; i < MY_PHYADDR_MAX + 1; i++) {
908 			if (bootverbose)
909 				device_printf(dev, "checking address: %d\n", i);
910 			sc->my_phy_addr = i;
911 			phy_sts = my_phy_readreg(sc, PHY_BMSR);
912 			if ((phy_sts != 0) && (phy_sts != 0xffff))
913 				break;
914 			else
915 				phy_sts = 0;
916 		}
917 		if (phy_sts) {
918 			phy_vid = my_phy_readreg(sc, PHY_VENID);
919 			phy_did = my_phy_readreg(sc, PHY_DEVID);
920 			if (bootverbose) {
921 				device_printf(dev, "found PHY at address %d, ",
922 				    sc->my_phy_addr);
923 				printf("vendor id: %x device id: %x\n",
924 				    phy_vid, phy_did);
925 			}
926 			p = my_phys;
927 			while (p->my_vid) {
928 				if (phy_vid == p->my_vid) {
929 					sc->my_pinfo = p;
930 					break;
931 				}
932 				p++;
933 			}
934 			if (sc->my_pinfo == NULL)
935 				sc->my_pinfo = &my_phys[PHY_UNKNOWN];
936 			if (bootverbose)
937 				device_printf(dev, "PHY type: %s\n",
938 				       sc->my_pinfo->my_name);
939 		} else {
940 			MY_UNLOCK(sc);
941 			device_printf(dev, "MII without any phy!\n");
942 			error = ENXIO;
943 			goto free_if;
944 		}
945 		MY_UNLOCK(sc);
946 	}
947 
948 	/* Do ifmedia setup. */
949 	ifmedia_init(&sc->ifmedia, 0, my_ifmedia_upd, my_ifmedia_sts);
950 	MY_LOCK(sc);
951 	my_getmode_mii(sc);
952 	my_autoneg_mii(sc, MY_FLAG_FORCEDELAY, 1);
953 	media = sc->ifmedia.ifm_media;
954 	my_stop(sc);
955 	MY_UNLOCK(sc);
956 	ifmedia_set(&sc->ifmedia, media);
957 
958 	ether_ifattach(ifp, eaddr);
959 
960 	error = bus_setup_intr(dev, sc->my_irq, INTR_TYPE_NET | INTR_MPSAFE,
961 			       NULL, my_intr, sc, &sc->my_intrhand);
962 
963 	if (error) {
964 		device_printf(dev, "couldn't set up irq\n");
965 		goto detach_if;
966 	}
967 
968 	return (0);
969 
970 detach_if:
971 	ether_ifdetach(ifp);
972 free_if:
973 	if_free(ifp);
974 free_ldata:
975 	free(sc->my_ldata_ptr, M_DEVBUF);
976 release_irq:
977 	bus_release_resource(dev, SYS_RES_IRQ, 0, sc->my_irq);
978 release_io:
979 	bus_release_resource(dev, MY_RES, MY_RID, sc->my_res);
980 destroy_mutex:
981 	mtx_destroy(&sc->my_mtx);
982 	return (error);
983 }
984 
985 static int
986 my_detach(device_t dev)
987 {
988 	struct my_softc *sc;
989 	struct ifnet   *ifp;
990 
991 	sc = device_get_softc(dev);
992 	MY_LOCK(sc);
993 	my_stop(sc);
994 	MY_UNLOCK(sc);
995 	bus_teardown_intr(dev, sc->my_irq, sc->my_intrhand);
996 
997 	ifp = sc->my_ifp;
998 	ether_ifdetach(ifp);
999 	if_free(ifp);
1000 	free(sc->my_ldata_ptr, M_DEVBUF);
1001 
1002 	bus_release_resource(dev, SYS_RES_IRQ, 0, sc->my_irq);
1003 	bus_release_resource(dev, MY_RES, MY_RID, sc->my_res);
1004 	mtx_destroy(&sc->my_mtx);
1005 	return (0);
1006 }
1007 
1008 
1009 /*
1010  * Initialize the transmit descriptors.
1011  */
1012 static int
1013 my_list_tx_init(struct my_softc * sc)
1014 {
1015 	struct my_chain_data *cd;
1016 	struct my_list_data *ld;
1017 	int             i;
1018 
1019 	MY_LOCK_ASSERT(sc);
1020 	cd = &sc->my_cdata;
1021 	ld = sc->my_ldata;
1022 	for (i = 0; i < MY_TX_LIST_CNT; i++) {
1023 		cd->my_tx_chain[i].my_ptr = &ld->my_tx_list[i];
1024 		if (i == (MY_TX_LIST_CNT - 1))
1025 			cd->my_tx_chain[i].my_nextdesc = &cd->my_tx_chain[0];
1026 		else
1027 			cd->my_tx_chain[i].my_nextdesc =
1028 			    &cd->my_tx_chain[i + 1];
1029 	}
1030 	cd->my_tx_free = &cd->my_tx_chain[0];
1031 	cd->my_tx_tail = cd->my_tx_head = NULL;
1032 	return (0);
1033 }
1034 
1035 /*
1036  * Initialize the RX descriptors and allocate mbufs for them. Note that we
1037  * arrange the descriptors in a closed ring, so that the last descriptor
1038  * points back to the first.
1039  */
1040 static int
1041 my_list_rx_init(struct my_softc * sc)
1042 {
1043 	struct my_chain_data *cd;
1044 	struct my_list_data *ld;
1045 	int             i;
1046 
1047 	MY_LOCK_ASSERT(sc);
1048 	cd = &sc->my_cdata;
1049 	ld = sc->my_ldata;
1050 	for (i = 0; i < MY_RX_LIST_CNT; i++) {
1051 		cd->my_rx_chain[i].my_ptr =
1052 		    (struct my_desc *) & ld->my_rx_list[i];
1053 		if (my_newbuf(sc, &cd->my_rx_chain[i]) == ENOBUFS) {
1054 			MY_UNLOCK(sc);
1055 			return (ENOBUFS);
1056 		}
1057 		if (i == (MY_RX_LIST_CNT - 1)) {
1058 			cd->my_rx_chain[i].my_nextdesc = &cd->my_rx_chain[0];
1059 			ld->my_rx_list[i].my_next = vtophys(&ld->my_rx_list[0]);
1060 		} else {
1061 			cd->my_rx_chain[i].my_nextdesc =
1062 			    &cd->my_rx_chain[i + 1];
1063 			ld->my_rx_list[i].my_next =
1064 			    vtophys(&ld->my_rx_list[i + 1]);
1065 		}
1066 	}
1067 	cd->my_rx_head = &cd->my_rx_chain[0];
1068 	return (0);
1069 }
1070 
1071 /*
1072  * Initialize an RX descriptor and attach an MBUF cluster.
1073  */
1074 static int
1075 my_newbuf(struct my_softc * sc, struct my_chain_onefrag * c)
1076 {
1077 	struct mbuf    *m_new = NULL;
1078 
1079 	MY_LOCK_ASSERT(sc);
1080 	MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1081 	if (m_new == NULL) {
1082 		device_printf(sc->my_dev,
1083 		    "no memory for rx list -- packet dropped!\n");
1084 		return (ENOBUFS);
1085 	}
1086 	MCLGET(m_new, M_DONTWAIT);
1087 	if (!(m_new->m_flags & M_EXT)) {
1088 		device_printf(sc->my_dev,
1089 		    "no memory for rx list -- packet dropped!\n");
1090 		m_freem(m_new);
1091 		return (ENOBUFS);
1092 	}
1093 	c->my_mbuf = m_new;
1094 	c->my_ptr->my_data = vtophys(mtod(m_new, caddr_t));
1095 	c->my_ptr->my_ctl = (MCLBYTES - 1) << MY_RBSShift;
1096 	c->my_ptr->my_status = MY_OWNByNIC;
1097 	return (0);
1098 }
1099 
1100 /*
1101  * A frame has been uploaded: pass the resulting mbuf chain up to the higher
1102  * level protocols.
1103  */
1104 static void
1105 my_rxeof(struct my_softc * sc)
1106 {
1107 	struct ether_header *eh;
1108 	struct mbuf    *m;
1109 	struct ifnet   *ifp;
1110 	struct my_chain_onefrag *cur_rx;
1111 	int             total_len = 0;
1112 	u_int32_t       rxstat;
1113 
1114 	MY_LOCK_ASSERT(sc);
1115 	ifp = sc->my_ifp;
1116 	while (!((rxstat = sc->my_cdata.my_rx_head->my_ptr->my_status)
1117 	    & MY_OWNByNIC)) {
1118 		cur_rx = sc->my_cdata.my_rx_head;
1119 		sc->my_cdata.my_rx_head = cur_rx->my_nextdesc;
1120 
1121 		if (rxstat & MY_ES) {	/* error summary: give up this rx pkt */
1122 			ifp->if_ierrors++;
1123 			cur_rx->my_ptr->my_status = MY_OWNByNIC;
1124 			continue;
1125 		}
1126 		/* No errors; receive the packet. */
1127 		total_len = (rxstat & MY_FLNGMASK) >> MY_FLNGShift;
1128 		total_len -= ETHER_CRC_LEN;
1129 
1130 		if (total_len < MINCLSIZE) {
1131 			m = m_devget(mtod(cur_rx->my_mbuf, char *),
1132 			    total_len, 0, ifp, NULL);
1133 			cur_rx->my_ptr->my_status = MY_OWNByNIC;
1134 			if (m == NULL) {
1135 				ifp->if_ierrors++;
1136 				continue;
1137 			}
1138 		} else {
1139 			m = cur_rx->my_mbuf;
1140 			/*
1141 			 * Try to conjure up a new mbuf cluster. If that
1142 			 * fails, it means we have an out of memory condition
1143 			 * and should leave the buffer in place and continue.
1144 			 * This will result in a lost packet, but there's
1145 			 * little else we can do in this situation.
1146 			 */
1147 			if (my_newbuf(sc, cur_rx) == ENOBUFS) {
1148 				ifp->if_ierrors++;
1149 				cur_rx->my_ptr->my_status = MY_OWNByNIC;
1150 				continue;
1151 			}
1152 			m->m_pkthdr.rcvif = ifp;
1153 			m->m_pkthdr.len = m->m_len = total_len;
1154 		}
1155 		ifp->if_ipackets++;
1156 		eh = mtod(m, struct ether_header *);
1157 #if NBPFILTER > 0
1158 		/*
1159 		 * Handle BPF listeners. Let the BPF user see the packet, but
1160 		 * don't pass it up to the ether_input() layer unless it's a
1161 		 * broadcast packet, multicast packet, matches our ethernet
1162 		 * address or the interface is in promiscuous mode.
1163 		 */
1164 		if (bpf_peers_present(ifp->if_bpf)) {
1165 			bpf_mtap(ifp->if_bpf, m);
1166 			if (ifp->if_flags & IFF_PROMISC &&
1167 			    (bcmp(eh->ether_dhost, IF_LLADDR(sc->my_ifp),
1168 				ETHER_ADDR_LEN) &&
1169 			     (eh->ether_dhost[0] & 1) == 0)) {
1170 				m_freem(m);
1171 				continue;
1172 			}
1173 		}
1174 #endif
1175 		MY_UNLOCK(sc);
1176 		(*ifp->if_input)(ifp, m);
1177 		MY_LOCK(sc);
1178 	}
1179 	return;
1180 }
1181 
1182 
1183 /*
1184  * A frame was downloaded to the chip. It's safe for us to clean up the list
1185  * buffers.
1186  */
1187 static void
1188 my_txeof(struct my_softc * sc)
1189 {
1190 	struct my_chain *cur_tx;
1191 	struct ifnet   *ifp;
1192 
1193 	MY_LOCK_ASSERT(sc);
1194 	ifp = sc->my_ifp;
1195 	/* Clear the timeout timer. */
1196 	ifp->if_timer = 0;
1197 	if (sc->my_cdata.my_tx_head == NULL) {
1198 		return;
1199 	}
1200 	/*
1201 	 * Go through our tx list and free mbufs for those frames that have
1202 	 * been transmitted.
1203 	 */
1204 	while (sc->my_cdata.my_tx_head->my_mbuf != NULL) {
1205 		u_int32_t       txstat;
1206 
1207 		cur_tx = sc->my_cdata.my_tx_head;
1208 		txstat = MY_TXSTATUS(cur_tx);
1209 		if ((txstat & MY_OWNByNIC) || txstat == MY_UNSENT)
1210 			break;
1211 		if (!(CSR_READ_4(sc, MY_TCRRCR) & MY_Enhanced)) {
1212 			if (txstat & MY_TXERR) {
1213 				ifp->if_oerrors++;
1214 				if (txstat & MY_EC) /* excessive collision */
1215 					ifp->if_collisions++;
1216 				if (txstat & MY_LC)	/* late collision */
1217 					ifp->if_collisions++;
1218 			}
1219 			ifp->if_collisions += (txstat & MY_NCRMASK) >>
1220 			    MY_NCRShift;
1221 		}
1222 		ifp->if_opackets++;
1223 		m_freem(cur_tx->my_mbuf);
1224 		cur_tx->my_mbuf = NULL;
1225 		if (sc->my_cdata.my_tx_head == sc->my_cdata.my_tx_tail) {
1226 			sc->my_cdata.my_tx_head = NULL;
1227 			sc->my_cdata.my_tx_tail = NULL;
1228 			break;
1229 		}
1230 		sc->my_cdata.my_tx_head = cur_tx->my_nextdesc;
1231 	}
1232 	if (CSR_READ_4(sc, MY_TCRRCR) & MY_Enhanced) {
1233 		ifp->if_collisions += (CSR_READ_4(sc, MY_TSR) & MY_NCRMask);
1234 	}
1235 	return;
1236 }
1237 
1238 /*
1239  * TX 'end of channel' interrupt handler.
1240  */
1241 static void
1242 my_txeoc(struct my_softc * sc)
1243 {
1244 	struct ifnet   *ifp;
1245 
1246 	MY_LOCK_ASSERT(sc);
1247 	ifp = sc->my_ifp;
1248 	ifp->if_timer = 0;
1249 	if (sc->my_cdata.my_tx_head == NULL) {
1250 		ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1251 		sc->my_cdata.my_tx_tail = NULL;
1252 		if (sc->my_want_auto)
1253 			my_autoneg_mii(sc, MY_FLAG_SCHEDDELAY, 1);
1254 	} else {
1255 		if (MY_TXOWN(sc->my_cdata.my_tx_head) == MY_UNSENT) {
1256 			MY_TXOWN(sc->my_cdata.my_tx_head) = MY_OWNByNIC;
1257 			ifp->if_timer = 5;
1258 			CSR_WRITE_4(sc, MY_TXPDR, 0xFFFFFFFF);
1259 		}
1260 	}
1261 	return;
1262 }
1263 
1264 static void
1265 my_intr(void *arg)
1266 {
1267 	struct my_softc *sc;
1268 	struct ifnet   *ifp;
1269 	u_int32_t       status;
1270 
1271 	sc = arg;
1272 	MY_LOCK(sc);
1273 	ifp = sc->my_ifp;
1274 	if (!(ifp->if_flags & IFF_UP)) {
1275 		MY_UNLOCK(sc);
1276 		return;
1277 	}
1278 	/* Disable interrupts. */
1279 	CSR_WRITE_4(sc, MY_IMR, 0x00000000);
1280 
1281 	for (;;) {
1282 		status = CSR_READ_4(sc, MY_ISR);
1283 		status &= MY_INTRS;
1284 		if (status)
1285 			CSR_WRITE_4(sc, MY_ISR, status);
1286 		else
1287 			break;
1288 
1289 		if (status & MY_RI)	/* receive interrupt */
1290 			my_rxeof(sc);
1291 
1292 		if ((status & MY_RBU) || (status & MY_RxErr)) {
1293 			/* rx buffer unavailable or rx error */
1294 			ifp->if_ierrors++;
1295 #ifdef foo
1296 			my_stop(sc);
1297 			my_reset(sc);
1298 			my_init_locked(sc);
1299 #endif
1300 		}
1301 		if (status & MY_TI)	/* tx interrupt */
1302 			my_txeof(sc);
1303 		if (status & MY_ETI)	/* tx early interrupt */
1304 			my_txeof(sc);
1305 		if (status & MY_TBU)	/* tx buffer unavailable */
1306 			my_txeoc(sc);
1307 
1308 #if 0				/* 90/1/18 delete */
1309 		if (status & MY_FBE) {
1310 			my_reset(sc);
1311 			my_init_locked(sc);
1312 		}
1313 #endif
1314 
1315 	}
1316 
1317 	/* Re-enable interrupts. */
1318 	CSR_WRITE_4(sc, MY_IMR, MY_INTRS);
1319 	if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1320 		my_start_locked(ifp);
1321 	MY_UNLOCK(sc);
1322 	return;
1323 }
1324 
1325 /*
1326  * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1327  * pointers to the fragment pointers.
1328  */
1329 static int
1330 my_encap(struct my_softc * sc, struct my_chain * c, struct mbuf * m_head)
1331 {
1332 	struct my_desc *f = NULL;
1333 	int             total_len;
1334 	struct mbuf    *m, *m_new = NULL;
1335 
1336 	MY_LOCK_ASSERT(sc);
1337 	/* calculate the total tx pkt length */
1338 	total_len = 0;
1339 	for (m = m_head; m != NULL; m = m->m_next)
1340 		total_len += m->m_len;
1341 	/*
1342 	 * Start packing the mbufs in this chain into the fragment pointers.
1343 	 * Stop when we run out of fragments or hit the end of the mbuf
1344 	 * chain.
1345 	 */
1346 	m = m_head;
1347 	MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1348 	if (m_new == NULL) {
1349 		device_printf(sc->my_dev, "no memory for tx list");
1350 		return (1);
1351 	}
1352 	if (m_head->m_pkthdr.len > MHLEN) {
1353 		MCLGET(m_new, M_DONTWAIT);
1354 		if (!(m_new->m_flags & M_EXT)) {
1355 			m_freem(m_new);
1356 			device_printf(sc->my_dev, "no memory for tx list");
1357 			return (1);
1358 		}
1359 	}
1360 	m_copydata(m_head, 0, m_head->m_pkthdr.len, mtod(m_new, caddr_t));
1361 	m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len;
1362 	m_freem(m_head);
1363 	m_head = m_new;
1364 	f = &c->my_ptr->my_frag[0];
1365 	f->my_status = 0;
1366 	f->my_data = vtophys(mtod(m_new, caddr_t));
1367 	total_len = m_new->m_len;
1368 	f->my_ctl = MY_TXFD | MY_TXLD | MY_CRCEnable | MY_PADEnable;
1369 	f->my_ctl |= total_len << MY_PKTShift;	/* pkt size */
1370 	f->my_ctl |= total_len;	/* buffer size */
1371 	/* 89/12/29 add, for mtd891 *//* [ 89? ] */
1372 	if (sc->my_info->my_did == MTD891ID)
1373 		f->my_ctl |= MY_ETIControl | MY_RetryTxLC;
1374 	c->my_mbuf = m_head;
1375 	c->my_lastdesc = 0;
1376 	MY_TXNEXT(c) = vtophys(&c->my_nextdesc->my_ptr->my_frag[0]);
1377 	return (0);
1378 }
1379 
1380 /*
1381  * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1382  * to the mbuf data regions directly in the transmit lists. We also save a
1383  * copy of the pointers since the transmit list fragment pointers are
1384  * physical addresses.
1385  */
1386 static void
1387 my_start(struct ifnet * ifp)
1388 {
1389 	struct my_softc *sc;
1390 
1391 	sc = ifp->if_softc;
1392 	MY_LOCK(sc);
1393 	my_start_locked(ifp);
1394 	MY_UNLOCK(sc);
1395 }
1396 
1397 static void
1398 my_start_locked(struct ifnet * ifp)
1399 {
1400 	struct my_softc *sc;
1401 	struct mbuf    *m_head = NULL;
1402 	struct my_chain *cur_tx = NULL, *start_tx;
1403 
1404 	sc = ifp->if_softc;
1405 	MY_LOCK_ASSERT(sc);
1406 	if (sc->my_autoneg) {
1407 		sc->my_tx_pend = 1;
1408 		return;
1409 	}
1410 	/*
1411 	 * Check for an available queue slot. If there are none, punt.
1412 	 */
1413 	if (sc->my_cdata.my_tx_free->my_mbuf != NULL) {
1414 		ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1415 		return;
1416 	}
1417 	start_tx = sc->my_cdata.my_tx_free;
1418 	while (sc->my_cdata.my_tx_free->my_mbuf == NULL) {
1419 		IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
1420 		if (m_head == NULL)
1421 			break;
1422 
1423 		/* Pick a descriptor off the free list. */
1424 		cur_tx = sc->my_cdata.my_tx_free;
1425 		sc->my_cdata.my_tx_free = cur_tx->my_nextdesc;
1426 
1427 		/* Pack the data into the descriptor. */
1428 		my_encap(sc, cur_tx, m_head);
1429 
1430 		if (cur_tx != start_tx)
1431 			MY_TXOWN(cur_tx) = MY_OWNByNIC;
1432 #if NBPFILTER > 0
1433 		/*
1434 		 * If there's a BPF listener, bounce a copy of this frame to
1435 		 * him.
1436 		 */
1437 		BPF_MTAP(ifp, cur_tx->my_mbuf);
1438 #endif
1439 	}
1440 	/*
1441 	 * If there are no packets queued, bail.
1442 	 */
1443 	if (cur_tx == NULL) {
1444 		return;
1445 	}
1446 	/*
1447 	 * Place the request for the upload interrupt in the last descriptor
1448 	 * in the chain. This way, if we're chaining several packets at once,
1449 	 * we'll only get an interupt once for the whole chain rather than
1450 	 * once for each packet.
1451 	 */
1452 	MY_TXCTL(cur_tx) |= MY_TXIC;
1453 	cur_tx->my_ptr->my_frag[0].my_ctl |= MY_TXIC;
1454 	sc->my_cdata.my_tx_tail = cur_tx;
1455 	if (sc->my_cdata.my_tx_head == NULL)
1456 		sc->my_cdata.my_tx_head = start_tx;
1457 	MY_TXOWN(start_tx) = MY_OWNByNIC;
1458 	CSR_WRITE_4(sc, MY_TXPDR, 0xFFFFFFFF);	/* tx polling demand */
1459 
1460 	/*
1461 	 * Set a timeout in case the chip goes out to lunch.
1462 	 */
1463 	ifp->if_timer = 5;
1464 	return;
1465 }
1466 
1467 static void
1468 my_init(void *xsc)
1469 {
1470 	struct my_softc *sc = xsc;
1471 
1472 	MY_LOCK(sc);
1473 	my_init_locked(sc);
1474 	MY_UNLOCK(sc);
1475 }
1476 
1477 static void
1478 my_init_locked(struct my_softc *sc)
1479 {
1480 	struct ifnet   *ifp = sc->my_ifp;
1481 	u_int16_t       phy_bmcr = 0;
1482 
1483 	MY_LOCK_ASSERT(sc);
1484 	if (sc->my_autoneg) {
1485 		return;
1486 	}
1487 	if (sc->my_pinfo != NULL)
1488 		phy_bmcr = my_phy_readreg(sc, PHY_BMCR);
1489 	/*
1490 	 * Cancel pending I/O and free all RX/TX buffers.
1491 	 */
1492 	my_stop(sc);
1493 	my_reset(sc);
1494 
1495 	/*
1496 	 * Set cache alignment and burst length.
1497 	 */
1498 #if 0				/* 89/9/1 modify,  */
1499 	CSR_WRITE_4(sc, MY_BCR, MY_RPBLE512);
1500 	CSR_WRITE_4(sc, MY_TCRRCR, MY_TFTSF);
1501 #endif
1502 	CSR_WRITE_4(sc, MY_BCR, MY_PBL8);
1503 	CSR_WRITE_4(sc, MY_TCRRCR, MY_TFTSF | MY_RBLEN | MY_RPBLE512);
1504 	/*
1505 	 * 89/12/29 add, for mtd891,
1506 	 */
1507 	if (sc->my_info->my_did == MTD891ID) {
1508 		MY_SETBIT(sc, MY_BCR, MY_PROG);
1509 		MY_SETBIT(sc, MY_TCRRCR, MY_Enhanced);
1510 	}
1511 	my_setcfg(sc, phy_bmcr);
1512 	/* Init circular RX list. */
1513 	if (my_list_rx_init(sc) == ENOBUFS) {
1514 		device_printf(sc->my_dev, "init failed: no memory for rx buffers\n");
1515 		my_stop(sc);
1516 		return;
1517 	}
1518 	/* Init TX descriptors. */
1519 	my_list_tx_init(sc);
1520 
1521 	/* If we want promiscuous mode, set the allframes bit. */
1522 	if (ifp->if_flags & IFF_PROMISC)
1523 		MY_SETBIT(sc, MY_TCRRCR, MY_PROM);
1524 	else
1525 		MY_CLRBIT(sc, MY_TCRRCR, MY_PROM);
1526 
1527 	/*
1528 	 * Set capture broadcast bit to capture broadcast frames.
1529 	 */
1530 	if (ifp->if_flags & IFF_BROADCAST)
1531 		MY_SETBIT(sc, MY_TCRRCR, MY_AB);
1532 	else
1533 		MY_CLRBIT(sc, MY_TCRRCR, MY_AB);
1534 
1535 	/*
1536 	 * Program the multicast filter, if necessary.
1537 	 */
1538 	my_setmulti(sc);
1539 
1540 	/*
1541 	 * Load the address of the RX list.
1542 	 */
1543 	MY_CLRBIT(sc, MY_TCRRCR, MY_RE);
1544 	CSR_WRITE_4(sc, MY_RXLBA, vtophys(&sc->my_ldata->my_rx_list[0]));
1545 
1546 	/*
1547 	 * Enable interrupts.
1548 	 */
1549 	CSR_WRITE_4(sc, MY_IMR, MY_INTRS);
1550 	CSR_WRITE_4(sc, MY_ISR, 0xFFFFFFFF);
1551 
1552 	/* Enable receiver and transmitter. */
1553 	MY_SETBIT(sc, MY_TCRRCR, MY_RE);
1554 	MY_CLRBIT(sc, MY_TCRRCR, MY_TE);
1555 	CSR_WRITE_4(sc, MY_TXLBA, vtophys(&sc->my_ldata->my_tx_list[0]));
1556 	MY_SETBIT(sc, MY_TCRRCR, MY_TE);
1557 
1558 	/* Restore state of BMCR */
1559 	if (sc->my_pinfo != NULL)
1560 		my_phy_writereg(sc, PHY_BMCR, phy_bmcr);
1561 	ifp->if_drv_flags |= IFF_DRV_RUNNING;
1562 	ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1563 	return;
1564 }
1565 
1566 /*
1567  * Set media options.
1568  */
1569 
1570 static int
1571 my_ifmedia_upd(struct ifnet * ifp)
1572 {
1573 	struct my_softc *sc;
1574 	struct ifmedia *ifm;
1575 
1576 	sc = ifp->if_softc;
1577 	MY_LOCK(sc);
1578 	ifm = &sc->ifmedia;
1579 	if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) {
1580 		MY_UNLOCK(sc);
1581 		return (EINVAL);
1582 	}
1583 	if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO)
1584 		my_autoneg_mii(sc, MY_FLAG_SCHEDDELAY, 1);
1585 	else
1586 		my_setmode_mii(sc, ifm->ifm_media);
1587 	MY_UNLOCK(sc);
1588 	return (0);
1589 }
1590 
1591 /*
1592  * Report current media status.
1593  */
1594 
1595 static void
1596 my_ifmedia_sts(struct ifnet * ifp, struct ifmediareq * ifmr)
1597 {
1598 	struct my_softc *sc;
1599 	u_int16_t advert = 0, ability = 0;
1600 
1601 	sc = ifp->if_softc;
1602 	MY_LOCK(sc);
1603 	ifmr->ifm_active = IFM_ETHER;
1604 	if (!(my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_AUTONEGENBL)) {
1605 #if 0				/* this version did not support 1000M, */
1606 		if (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_1000)
1607 			ifmr->ifm_active = IFM_ETHER | IFM_1000TX;
1608 #endif
1609 		if (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_SPEEDSEL)
1610 			ifmr->ifm_active = IFM_ETHER | IFM_100_TX;
1611 		else
1612 			ifmr->ifm_active = IFM_ETHER | IFM_10_T;
1613 		if (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_DUPLEX)
1614 			ifmr->ifm_active |= IFM_FDX;
1615 		else
1616 			ifmr->ifm_active |= IFM_HDX;
1617 
1618 		MY_UNLOCK(sc);
1619 		return;
1620 	}
1621 	ability = my_phy_readreg(sc, PHY_LPAR);
1622 	advert = my_phy_readreg(sc, PHY_ANAR);
1623 
1624 #if 0				/* this version did not support 1000M, */
1625 	if (sc->my_pinfo->my_vid = MarvellPHYID0) {
1626 		ability2 = my_phy_readreg(sc, PHY_1000SR);
1627 		if (ability2 & PHY_1000SR_1000BTXFULL) {
1628 			advert = 0;
1629 			ability = 0;
1630 	  		ifmr->ifm_active = IFM_ETHER|IFM_1000_T|IFM_FDX;
1631 	  	} else if (ability & PHY_1000SR_1000BTXHALF) {
1632 			advert = 0;
1633 			ability = 0;
1634 			ifmr->ifm_active = IFM_ETHER|IFM_1000_T|IFM_HDX;
1635 		}
1636 	}
1637 #endif
1638 	if (advert & PHY_ANAR_100BT4 && ability & PHY_ANAR_100BT4)
1639 		ifmr->ifm_active = IFM_ETHER | IFM_100_T4;
1640 	else if (advert & PHY_ANAR_100BTXFULL && ability & PHY_ANAR_100BTXFULL)
1641 		ifmr->ifm_active = IFM_ETHER | IFM_100_TX | IFM_FDX;
1642 	else if (advert & PHY_ANAR_100BTXHALF && ability & PHY_ANAR_100BTXHALF)
1643 		ifmr->ifm_active = IFM_ETHER | IFM_100_TX | IFM_HDX;
1644 	else if (advert & PHY_ANAR_10BTFULL && ability & PHY_ANAR_10BTFULL)
1645 		ifmr->ifm_active = IFM_ETHER | IFM_10_T | IFM_FDX;
1646 	else if (advert & PHY_ANAR_10BTHALF && ability & PHY_ANAR_10BTHALF)
1647 		ifmr->ifm_active = IFM_ETHER | IFM_10_T | IFM_HDX;
1648 	MY_UNLOCK(sc);
1649 	return;
1650 }
1651 
1652 static int
1653 my_ioctl(struct ifnet * ifp, u_long command, caddr_t data)
1654 {
1655 	struct my_softc *sc = ifp->if_softc;
1656 	struct ifreq   *ifr = (struct ifreq *) data;
1657 	int             error;
1658 
1659 	switch (command) {
1660 	case SIOCSIFFLAGS:
1661 		MY_LOCK(sc);
1662 		if (ifp->if_flags & IFF_UP)
1663 			my_init_locked(sc);
1664 		else if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1665 			my_stop(sc);
1666 		MY_UNLOCK(sc);
1667 		error = 0;
1668 		break;
1669 	case SIOCADDMULTI:
1670 	case SIOCDELMULTI:
1671 		MY_LOCK(sc);
1672 		my_setmulti(sc);
1673 		MY_UNLOCK(sc);
1674 		error = 0;
1675 		break;
1676 	case SIOCGIFMEDIA:
1677 	case SIOCSIFMEDIA:
1678 		error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command);
1679 		break;
1680 	default:
1681 		error = ether_ioctl(ifp, command, data);
1682 		break;
1683 	}
1684 	return (error);
1685 }
1686 
1687 static void
1688 my_watchdog(struct ifnet * ifp)
1689 {
1690 	struct my_softc *sc;
1691 
1692 	sc = ifp->if_softc;
1693 	MY_LOCK(sc);
1694 	if (sc->my_autoneg) {
1695 		my_autoneg_mii(sc, MY_FLAG_DELAYTIMEO, 1);
1696 		MY_UNLOCK(sc);
1697 		return;
1698 	}
1699 	ifp->if_oerrors++;
1700 	if_printf(ifp, "watchdog timeout\n");
1701 	if (!(my_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT))
1702 		if_printf(ifp, "no carrier - transceiver cable problem?\n");
1703 	my_stop(sc);
1704 	my_reset(sc);
1705 	my_init_locked(sc);
1706 	if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1707 		my_start_locked(ifp);
1708 	MY_LOCK(sc);
1709 	return;
1710 }
1711 
1712 
1713 /*
1714  * Stop the adapter and free any mbufs allocated to the RX and TX lists.
1715  */
1716 static void
1717 my_stop(struct my_softc * sc)
1718 {
1719 	register int    i;
1720 	struct ifnet   *ifp;
1721 
1722 	MY_LOCK_ASSERT(sc);
1723 	ifp = sc->my_ifp;
1724 	ifp->if_timer = 0;
1725 
1726 	MY_CLRBIT(sc, MY_TCRRCR, (MY_RE | MY_TE));
1727 	CSR_WRITE_4(sc, MY_IMR, 0x00000000);
1728 	CSR_WRITE_4(sc, MY_TXLBA, 0x00000000);
1729 	CSR_WRITE_4(sc, MY_RXLBA, 0x00000000);
1730 
1731 	/*
1732 	 * Free data in the RX lists.
1733 	 */
1734 	for (i = 0; i < MY_RX_LIST_CNT; i++) {
1735 		if (sc->my_cdata.my_rx_chain[i].my_mbuf != NULL) {
1736 			m_freem(sc->my_cdata.my_rx_chain[i].my_mbuf);
1737 			sc->my_cdata.my_rx_chain[i].my_mbuf = NULL;
1738 		}
1739 	}
1740 	bzero((char *)&sc->my_ldata->my_rx_list,
1741 	    sizeof(sc->my_ldata->my_rx_list));
1742 	/*
1743 	 * Free the TX list buffers.
1744 	 */
1745 	for (i = 0; i < MY_TX_LIST_CNT; i++) {
1746 		if (sc->my_cdata.my_tx_chain[i].my_mbuf != NULL) {
1747 			m_freem(sc->my_cdata.my_tx_chain[i].my_mbuf);
1748 			sc->my_cdata.my_tx_chain[i].my_mbuf = NULL;
1749 		}
1750 	}
1751 	bzero((char *)&sc->my_ldata->my_tx_list,
1752 	    sizeof(sc->my_ldata->my_tx_list));
1753 	ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1754 	return;
1755 }
1756 
1757 /*
1758  * Stop all chip I/O so that the kernel's probe routines don't get confused
1759  * by errant DMAs when rebooting.
1760  */
1761 static void
1762 my_shutdown(device_t dev)
1763 {
1764 	struct my_softc *sc;
1765 
1766 	sc = device_get_softc(dev);
1767 	MY_LOCK(sc);
1768 	my_stop(sc);
1769 	MY_UNLOCK(sc);
1770 	return;
1771 }
1772