1 /*- 2 * Written by: yen_cw@myson.com.tw 3 * Copyright (c) 2002 Myson Technology Inc. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions, and the following disclaimer, 11 * without modification, immediately at the beginning of the file. 12 * 2. The name of the author may not be used to endorse or promote products 13 * derived from this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 19 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * Myson fast ethernet PCI NIC driver, available at: http://www.myson.com.tw/ 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/sockio.h> 36 #include <sys/mbuf.h> 37 #include <sys/malloc.h> 38 #include <sys/kernel.h> 39 #include <sys/socket.h> 40 #include <sys/queue.h> 41 #include <sys/types.h> 42 #include <sys/bus.h> 43 #include <sys/module.h> 44 #include <sys/lock.h> 45 #include <sys/mutex.h> 46 47 #define NBPFILTER 1 48 49 #include <net/if.h> 50 #include <net/if_arp.h> 51 #include <net/ethernet.h> 52 #include <net/if_media.h> 53 #include <net/if_types.h> 54 #include <net/if_dl.h> 55 #include <net/bpf.h> 56 57 #include <vm/vm.h> /* for vtophys */ 58 #include <vm/pmap.h> /* for vtophys */ 59 #include <machine/clock.h> /* for DELAY */ 60 #include <machine/bus.h> 61 #include <machine/resource.h> 62 #include <sys/bus.h> 63 #include <sys/rman.h> 64 65 #include <dev/pci/pcireg.h> 66 #include <dev/pci/pcivar.h> 67 68 #include <dev/mii/mii.h> 69 #include <dev/mii/miivar.h> 70 71 #include "miibus_if.h" 72 73 /* 74 * #define MY_USEIOSPACE 75 */ 76 77 static int MY_USEIOSPACE = 1; 78 79 #if (MY_USEIOSPACE) 80 #define MY_RES SYS_RES_IOPORT 81 #define MY_RID MY_PCI_LOIO 82 #else 83 #define MY_RES SYS_RES_MEMORY 84 #define MY_RID MY_PCI_LOMEM 85 #endif 86 87 88 #include <dev/my/if_myreg.h> 89 90 #ifndef lint 91 static const char rcsid[] = 92 "$Id: if_my.c,v 1.16 2003/04/15 06:37:25 mdodd Exp $"; 93 #endif 94 95 /* 96 * Various supported device vendors/types and their names. 97 */ 98 struct my_type *my_info_tmp; 99 static struct my_type my_devs[] = { 100 {MYSONVENDORID, MTD800ID, "Myson MTD80X Based Fast Ethernet Card"}, 101 {MYSONVENDORID, MTD803ID, "Myson MTD80X Based Fast Ethernet Card"}, 102 {MYSONVENDORID, MTD891ID, "Myson MTD89X Based Giga Ethernet Card"}, 103 {0, 0, NULL} 104 }; 105 106 /* 107 * Various supported PHY vendors/types and their names. Note that this driver 108 * will work with pretty much any MII-compliant PHY, so failure to positively 109 * identify the chip is not a fatal error. 110 */ 111 static struct my_type my_phys[] = { 112 {MysonPHYID0, MysonPHYID0, "<MYSON MTD981>"}, 113 {SeeqPHYID0, SeeqPHYID0, "<SEEQ 80225>"}, 114 {AhdocPHYID0, AhdocPHYID0, "<AHDOC 101>"}, 115 {MarvellPHYID0, MarvellPHYID0, "<MARVELL 88E1000>"}, 116 {LevelOnePHYID0, LevelOnePHYID0, "<LevelOne LXT1000>"}, 117 {0, 0, "<MII-compliant physical interface>"} 118 }; 119 120 static int my_probe(device_t); 121 static int my_attach(device_t); 122 static int my_detach(device_t); 123 static int my_newbuf(struct my_softc *, struct my_chain_onefrag *); 124 static int my_encap(struct my_softc *, struct my_chain *, struct mbuf *); 125 static void my_rxeof(struct my_softc *); 126 static void my_txeof(struct my_softc *); 127 static void my_txeoc(struct my_softc *); 128 static void my_intr(void *); 129 static void my_start(struct ifnet *); 130 static int my_ioctl(struct ifnet *, u_long, caddr_t); 131 static void my_init(void *); 132 static void my_stop(struct my_softc *); 133 static void my_watchdog(struct ifnet *); 134 static void my_shutdown(device_t); 135 static int my_ifmedia_upd(struct ifnet *); 136 static void my_ifmedia_sts(struct ifnet *, struct ifmediareq *); 137 static u_int16_t my_phy_readreg(struct my_softc *, int); 138 static void my_phy_writereg(struct my_softc *, int, int); 139 static void my_autoneg_xmit(struct my_softc *); 140 static void my_autoneg_mii(struct my_softc *, int, int); 141 static void my_setmode_mii(struct my_softc *, int); 142 static void my_getmode_mii(struct my_softc *); 143 static void my_setcfg(struct my_softc *, int); 144 static void my_setmulti(struct my_softc *); 145 static void my_reset(struct my_softc *); 146 static int my_list_rx_init(struct my_softc *); 147 static int my_list_tx_init(struct my_softc *); 148 static long my_send_cmd_to_phy(struct my_softc *, int, int); 149 150 #define MY_SETBIT(sc, reg, x) CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 151 #define MY_CLRBIT(sc, reg, x) CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 152 153 static device_method_t my_methods[] = { 154 /* Device interface */ 155 DEVMETHOD(device_probe, my_probe), 156 DEVMETHOD(device_attach, my_attach), 157 DEVMETHOD(device_detach, my_detach), 158 DEVMETHOD(device_shutdown, my_shutdown), 159 160 {0, 0} 161 }; 162 163 static driver_t my_driver = { 164 "my", 165 my_methods, 166 sizeof(struct my_softc) 167 }; 168 169 static devclass_t my_devclass; 170 171 DRIVER_MODULE(my, pci, my_driver, my_devclass, 0, 0); 172 MODULE_DEPEND(my, pci, 1, 1, 1); 173 MODULE_DEPEND(my, ether, 1, 1, 1); 174 175 static long 176 my_send_cmd_to_phy(struct my_softc * sc, int opcode, int regad) 177 { 178 long miir; 179 int i; 180 int mask, data; 181 182 MY_LOCK(sc); 183 184 /* enable MII output */ 185 miir = CSR_READ_4(sc, MY_MANAGEMENT); 186 miir &= 0xfffffff0; 187 188 miir |= MY_MASK_MIIR_MII_WRITE + MY_MASK_MIIR_MII_MDO; 189 190 /* send 32 1's preamble */ 191 for (i = 0; i < 32; i++) { 192 /* low MDC; MDO is already high (miir) */ 193 miir &= ~MY_MASK_MIIR_MII_MDC; 194 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 195 196 /* high MDC */ 197 miir |= MY_MASK_MIIR_MII_MDC; 198 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 199 } 200 201 /* calculate ST+OP+PHYAD+REGAD+TA */ 202 data = opcode | (sc->my_phy_addr << 7) | (regad << 2); 203 204 /* sent out */ 205 mask = 0x8000; 206 while (mask) { 207 /* low MDC, prepare MDO */ 208 miir &= ~(MY_MASK_MIIR_MII_MDC + MY_MASK_MIIR_MII_MDO); 209 if (mask & data) 210 miir |= MY_MASK_MIIR_MII_MDO; 211 212 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 213 /* high MDC */ 214 miir |= MY_MASK_MIIR_MII_MDC; 215 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 216 DELAY(30); 217 218 /* next */ 219 mask >>= 1; 220 if (mask == 0x2 && opcode == MY_OP_READ) 221 miir &= ~MY_MASK_MIIR_MII_WRITE; 222 } 223 224 MY_UNLOCK(sc); 225 return miir; 226 } 227 228 229 static u_int16_t 230 my_phy_readreg(struct my_softc * sc, int reg) 231 { 232 long miir; 233 int mask, data; 234 235 MY_LOCK(sc); 236 237 if (sc->my_info->my_did == MTD803ID) 238 data = CSR_READ_2(sc, MY_PHYBASE + reg * 2); 239 else { 240 miir = my_send_cmd_to_phy(sc, MY_OP_READ, reg); 241 242 /* read data */ 243 mask = 0x8000; 244 data = 0; 245 while (mask) { 246 /* low MDC */ 247 miir &= ~MY_MASK_MIIR_MII_MDC; 248 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 249 250 /* read MDI */ 251 miir = CSR_READ_4(sc, MY_MANAGEMENT); 252 if (miir & MY_MASK_MIIR_MII_MDI) 253 data |= mask; 254 255 /* high MDC, and wait */ 256 miir |= MY_MASK_MIIR_MII_MDC; 257 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 258 DELAY(30); 259 260 /* next */ 261 mask >>= 1; 262 } 263 264 /* low MDC */ 265 miir &= ~MY_MASK_MIIR_MII_MDC; 266 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 267 } 268 269 MY_UNLOCK(sc); 270 return (u_int16_t) data; 271 } 272 273 274 static void 275 my_phy_writereg(struct my_softc * sc, int reg, int data) 276 { 277 long miir; 278 int mask; 279 280 MY_LOCK(sc); 281 282 if (sc->my_info->my_did == MTD803ID) 283 CSR_WRITE_2(sc, MY_PHYBASE + reg * 2, data); 284 else { 285 miir = my_send_cmd_to_phy(sc, MY_OP_WRITE, reg); 286 287 /* write data */ 288 mask = 0x8000; 289 while (mask) { 290 /* low MDC, prepare MDO */ 291 miir &= ~(MY_MASK_MIIR_MII_MDC + MY_MASK_MIIR_MII_MDO); 292 if (mask & data) 293 miir |= MY_MASK_MIIR_MII_MDO; 294 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 295 DELAY(1); 296 297 /* high MDC */ 298 miir |= MY_MASK_MIIR_MII_MDC; 299 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 300 DELAY(1); 301 302 /* next */ 303 mask >>= 1; 304 } 305 306 /* low MDC */ 307 miir &= ~MY_MASK_MIIR_MII_MDC; 308 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 309 } 310 MY_UNLOCK(sc); 311 return; 312 } 313 314 315 /* 316 * Program the 64-bit multicast hash filter. 317 */ 318 static void 319 my_setmulti(struct my_softc * sc) 320 { 321 struct ifnet *ifp; 322 int h = 0; 323 u_int32_t hashes[2] = {0, 0}; 324 struct ifmultiaddr *ifma; 325 u_int32_t rxfilt; 326 int mcnt = 0; 327 328 MY_LOCK(sc); 329 330 ifp = sc->my_ifp; 331 332 rxfilt = CSR_READ_4(sc, MY_TCRRCR); 333 334 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 335 rxfilt |= MY_AM; 336 CSR_WRITE_4(sc, MY_TCRRCR, rxfilt); 337 CSR_WRITE_4(sc, MY_MAR0, 0xFFFFFFFF); 338 CSR_WRITE_4(sc, MY_MAR1, 0xFFFFFFFF); 339 340 MY_UNLOCK(sc); 341 342 return; 343 } 344 /* first, zot all the existing hash bits */ 345 CSR_WRITE_4(sc, MY_MAR0, 0); 346 CSR_WRITE_4(sc, MY_MAR1, 0); 347 348 /* now program new ones */ 349 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 350 if (ifma->ifma_addr->sa_family != AF_LINK) 351 continue; 352 h = ~ether_crc32_be(LLADDR((struct sockaddr_dl *) 353 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 354 if (h < 32) 355 hashes[0] |= (1 << h); 356 else 357 hashes[1] |= (1 << (h - 32)); 358 mcnt++; 359 } 360 361 if (mcnt) 362 rxfilt |= MY_AM; 363 else 364 rxfilt &= ~MY_AM; 365 CSR_WRITE_4(sc, MY_MAR0, hashes[0]); 366 CSR_WRITE_4(sc, MY_MAR1, hashes[1]); 367 CSR_WRITE_4(sc, MY_TCRRCR, rxfilt); 368 MY_UNLOCK(sc); 369 return; 370 } 371 372 /* 373 * Initiate an autonegotiation session. 374 */ 375 static void 376 my_autoneg_xmit(struct my_softc * sc) 377 { 378 u_int16_t phy_sts = 0; 379 380 MY_LOCK(sc); 381 382 my_phy_writereg(sc, PHY_BMCR, PHY_BMCR_RESET); 383 DELAY(500); 384 while (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_RESET); 385 386 phy_sts = my_phy_readreg(sc, PHY_BMCR); 387 phy_sts |= PHY_BMCR_AUTONEGENBL | PHY_BMCR_AUTONEGRSTR; 388 my_phy_writereg(sc, PHY_BMCR, phy_sts); 389 390 MY_UNLOCK(sc); 391 return; 392 } 393 394 395 /* 396 * Invoke autonegotiation on a PHY. 397 */ 398 static void 399 my_autoneg_mii(struct my_softc * sc, int flag, int verbose) 400 { 401 u_int16_t phy_sts = 0, media, advert, ability; 402 u_int16_t ability2 = 0; 403 struct ifnet *ifp; 404 struct ifmedia *ifm; 405 406 MY_LOCK(sc); 407 408 ifm = &sc->ifmedia; 409 ifp = sc->my_ifp; 410 411 ifm->ifm_media = IFM_ETHER | IFM_AUTO; 412 413 #ifndef FORCE_AUTONEG_TFOUR 414 /* 415 * First, see if autoneg is supported. If not, there's no point in 416 * continuing. 417 */ 418 phy_sts = my_phy_readreg(sc, PHY_BMSR); 419 if (!(phy_sts & PHY_BMSR_CANAUTONEG)) { 420 if (verbose) 421 printf("my%d: autonegotiation not supported\n", 422 sc->my_unit); 423 ifm->ifm_media = IFM_ETHER | IFM_10_T | IFM_HDX; 424 MY_UNLOCK(sc); 425 return; 426 } 427 #endif 428 switch (flag) { 429 case MY_FLAG_FORCEDELAY: 430 /* 431 * XXX Never use this option anywhere but in the probe 432 * routine: making the kernel stop dead in its tracks for 433 * three whole seconds after we've gone multi-user is really 434 * bad manners. 435 */ 436 my_autoneg_xmit(sc); 437 DELAY(5000000); 438 break; 439 case MY_FLAG_SCHEDDELAY: 440 /* 441 * Wait for the transmitter to go idle before starting an 442 * autoneg session, otherwise my_start() may clobber our 443 * timeout, and we don't want to allow transmission during an 444 * autoneg session since that can screw it up. 445 */ 446 if (sc->my_cdata.my_tx_head != NULL) { 447 sc->my_want_auto = 1; 448 MY_UNLOCK(sc); 449 return; 450 } 451 my_autoneg_xmit(sc); 452 ifp->if_timer = 5; 453 sc->my_autoneg = 1; 454 sc->my_want_auto = 0; 455 MY_UNLOCK(sc); 456 return; 457 case MY_FLAG_DELAYTIMEO: 458 ifp->if_timer = 0; 459 sc->my_autoneg = 0; 460 break; 461 default: 462 printf("my%d: invalid autoneg flag: %d\n", sc->my_unit, flag); 463 MY_UNLOCK(sc); 464 return; 465 } 466 467 if (my_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_AUTONEGCOMP) { 468 if (verbose) 469 printf("my%d: autoneg complete, ", sc->my_unit); 470 phy_sts = my_phy_readreg(sc, PHY_BMSR); 471 } else { 472 if (verbose) 473 printf("my%d: autoneg not complete, ", sc->my_unit); 474 } 475 476 media = my_phy_readreg(sc, PHY_BMCR); 477 478 /* Link is good. Report modes and set duplex mode. */ 479 if (my_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT) { 480 if (verbose) 481 printf("my%d: link status good. ", sc->my_unit); 482 advert = my_phy_readreg(sc, PHY_ANAR); 483 ability = my_phy_readreg(sc, PHY_LPAR); 484 if ((sc->my_pinfo->my_vid == MarvellPHYID0) || 485 (sc->my_pinfo->my_vid == LevelOnePHYID0)) { 486 ability2 = my_phy_readreg(sc, PHY_1000SR); 487 if (ability2 & PHY_1000SR_1000BTXFULL) { 488 advert = 0; 489 ability = 0; 490 /* 491 * this version did not support 1000M, 492 * ifm->ifm_media = 493 * IFM_ETHER|IFM_1000_T|IFM_FDX; 494 */ 495 ifm->ifm_media = 496 IFM_ETHER | IFM_100_TX | IFM_FDX; 497 media &= ~PHY_BMCR_SPEEDSEL; 498 media |= PHY_BMCR_1000; 499 media |= PHY_BMCR_DUPLEX; 500 printf("(full-duplex, 1000Mbps)\n"); 501 } else if (ability2 & PHY_1000SR_1000BTXHALF) { 502 advert = 0; 503 ability = 0; 504 /* 505 * this version did not support 1000M, 506 * ifm->ifm_media = IFM_ETHER|IFM_1000_T; 507 */ 508 ifm->ifm_media = IFM_ETHER | IFM_100_TX; 509 media &= ~PHY_BMCR_SPEEDSEL; 510 media &= ~PHY_BMCR_DUPLEX; 511 media |= PHY_BMCR_1000; 512 printf("(half-duplex, 1000Mbps)\n"); 513 } 514 } 515 if (advert & PHY_ANAR_100BT4 && ability & PHY_ANAR_100BT4) { 516 ifm->ifm_media = IFM_ETHER | IFM_100_T4; 517 media |= PHY_BMCR_SPEEDSEL; 518 media &= ~PHY_BMCR_DUPLEX; 519 printf("(100baseT4)\n"); 520 } else if (advert & PHY_ANAR_100BTXFULL && 521 ability & PHY_ANAR_100BTXFULL) { 522 ifm->ifm_media = IFM_ETHER | IFM_100_TX | IFM_FDX; 523 media |= PHY_BMCR_SPEEDSEL; 524 media |= PHY_BMCR_DUPLEX; 525 printf("(full-duplex, 100Mbps)\n"); 526 } else if (advert & PHY_ANAR_100BTXHALF && 527 ability & PHY_ANAR_100BTXHALF) { 528 ifm->ifm_media = IFM_ETHER | IFM_100_TX | IFM_HDX; 529 media |= PHY_BMCR_SPEEDSEL; 530 media &= ~PHY_BMCR_DUPLEX; 531 printf("(half-duplex, 100Mbps)\n"); 532 } else if (advert & PHY_ANAR_10BTFULL && 533 ability & PHY_ANAR_10BTFULL) { 534 ifm->ifm_media = IFM_ETHER | IFM_10_T | IFM_FDX; 535 media &= ~PHY_BMCR_SPEEDSEL; 536 media |= PHY_BMCR_DUPLEX; 537 printf("(full-duplex, 10Mbps)\n"); 538 } else if (advert) { 539 ifm->ifm_media = IFM_ETHER | IFM_10_T | IFM_HDX; 540 media &= ~PHY_BMCR_SPEEDSEL; 541 media &= ~PHY_BMCR_DUPLEX; 542 printf("(half-duplex, 10Mbps)\n"); 543 } 544 media &= ~PHY_BMCR_AUTONEGENBL; 545 546 /* Set ASIC's duplex mode to match the PHY. */ 547 my_phy_writereg(sc, PHY_BMCR, media); 548 my_setcfg(sc, media); 549 } else { 550 if (verbose) 551 printf("my%d: no carrier\n", sc->my_unit); 552 } 553 554 my_init(sc); 555 if (sc->my_tx_pend) { 556 sc->my_autoneg = 0; 557 sc->my_tx_pend = 0; 558 my_start(ifp); 559 } 560 MY_UNLOCK(sc); 561 return; 562 } 563 564 /* 565 * To get PHY ability. 566 */ 567 static void 568 my_getmode_mii(struct my_softc * sc) 569 { 570 u_int16_t bmsr; 571 struct ifnet *ifp; 572 573 MY_LOCK(sc); 574 ifp = sc->my_ifp; 575 bmsr = my_phy_readreg(sc, PHY_BMSR); 576 if (bootverbose) 577 printf("my%d: PHY status word: %x\n", sc->my_unit, bmsr); 578 579 /* fallback */ 580 sc->ifmedia.ifm_media = IFM_ETHER | IFM_10_T | IFM_HDX; 581 582 if (bmsr & PHY_BMSR_10BTHALF) { 583 if (bootverbose) 584 printf("my%d: 10Mbps half-duplex mode supported\n", 585 sc->my_unit); 586 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_10_T | IFM_HDX, 587 0, NULL); 588 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_10_T, 0, NULL); 589 } 590 if (bmsr & PHY_BMSR_10BTFULL) { 591 if (bootverbose) 592 printf("my%d: 10Mbps full-duplex mode supported\n", 593 sc->my_unit); 594 595 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_10_T | IFM_FDX, 596 0, NULL); 597 sc->ifmedia.ifm_media = IFM_ETHER | IFM_10_T | IFM_FDX; 598 } 599 if (bmsr & PHY_BMSR_100BTXHALF) { 600 if (bootverbose) 601 printf("my%d: 100Mbps half-duplex mode supported\n", 602 sc->my_unit); 603 ifp->if_baudrate = 100000000; 604 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_TX, 0, NULL); 605 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_TX | IFM_HDX, 606 0, NULL); 607 sc->ifmedia.ifm_media = IFM_ETHER | IFM_100_TX | IFM_HDX; 608 } 609 if (bmsr & PHY_BMSR_100BTXFULL) { 610 if (bootverbose) 611 printf("my%d: 100Mbps full-duplex mode supported\n", 612 sc->my_unit); 613 ifp->if_baudrate = 100000000; 614 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_TX | IFM_FDX, 615 0, NULL); 616 sc->ifmedia.ifm_media = IFM_ETHER | IFM_100_TX | IFM_FDX; 617 } 618 /* Some also support 100BaseT4. */ 619 if (bmsr & PHY_BMSR_100BT4) { 620 if (bootverbose) 621 printf("my%d: 100baseT4 mode supported\n", sc->my_unit); 622 ifp->if_baudrate = 100000000; 623 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_T4, 0, NULL); 624 sc->ifmedia.ifm_media = IFM_ETHER | IFM_100_T4; 625 #ifdef FORCE_AUTONEG_TFOUR 626 if (bootverbose) 627 printf("my%d: forcing on autoneg support for BT4\n", 628 sc->my_unit); 629 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_AUTO, 0 NULL): 630 sc->ifmedia.ifm_media = IFM_ETHER | IFM_AUTO; 631 #endif 632 } 633 #if 0 /* this version did not support 1000M, */ 634 if (sc->my_pinfo->my_vid == MarvellPHYID0) { 635 if (bootverbose) 636 printf("my%d: 1000Mbps half-duplex mode supported\n", 637 sc->my_unit); 638 639 ifp->if_baudrate = 1000000000; 640 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_T, 0, NULL); 641 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_T | IFM_HDX, 642 0, NULL); 643 if (bootverbose) 644 printf("my%d: 1000Mbps full-duplex mode supported\n", 645 sc->my_unit); 646 ifp->if_baudrate = 1000000000; 647 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_T | IFM_FDX, 648 0, NULL); 649 sc->ifmedia.ifm_media = IFM_ETHER | IFM_1000_T | IFM_FDX; 650 } 651 #endif 652 if (bmsr & PHY_BMSR_CANAUTONEG) { 653 if (bootverbose) 654 printf("my%d: autoneg supported\n", sc->my_unit); 655 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 656 sc->ifmedia.ifm_media = IFM_ETHER | IFM_AUTO; 657 } 658 MY_UNLOCK(sc); 659 return; 660 } 661 662 /* 663 * Set speed and duplex mode. 664 */ 665 static void 666 my_setmode_mii(struct my_softc * sc, int media) 667 { 668 u_int16_t bmcr; 669 struct ifnet *ifp; 670 671 MY_LOCK(sc); 672 ifp = sc->my_ifp; 673 /* 674 * If an autoneg session is in progress, stop it. 675 */ 676 if (sc->my_autoneg) { 677 printf("my%d: canceling autoneg session\n", sc->my_unit); 678 ifp->if_timer = sc->my_autoneg = sc->my_want_auto = 0; 679 bmcr = my_phy_readreg(sc, PHY_BMCR); 680 bmcr &= ~PHY_BMCR_AUTONEGENBL; 681 my_phy_writereg(sc, PHY_BMCR, bmcr); 682 } 683 printf("my%d: selecting MII, ", sc->my_unit); 684 bmcr = my_phy_readreg(sc, PHY_BMCR); 685 bmcr &= ~(PHY_BMCR_AUTONEGENBL | PHY_BMCR_SPEEDSEL | PHY_BMCR_1000 | 686 PHY_BMCR_DUPLEX | PHY_BMCR_LOOPBK); 687 688 #if 0 /* this version did not support 1000M, */ 689 if (IFM_SUBTYPE(media) == IFM_1000_T) { 690 printf("1000Mbps/T4, half-duplex\n"); 691 bmcr &= ~PHY_BMCR_SPEEDSEL; 692 bmcr &= ~PHY_BMCR_DUPLEX; 693 bmcr |= PHY_BMCR_1000; 694 } 695 #endif 696 if (IFM_SUBTYPE(media) == IFM_100_T4) { 697 printf("100Mbps/T4, half-duplex\n"); 698 bmcr |= PHY_BMCR_SPEEDSEL; 699 bmcr &= ~PHY_BMCR_DUPLEX; 700 } 701 if (IFM_SUBTYPE(media) == IFM_100_TX) { 702 printf("100Mbps, "); 703 bmcr |= PHY_BMCR_SPEEDSEL; 704 } 705 if (IFM_SUBTYPE(media) == IFM_10_T) { 706 printf("10Mbps, "); 707 bmcr &= ~PHY_BMCR_SPEEDSEL; 708 } 709 if ((media & IFM_GMASK) == IFM_FDX) { 710 printf("full duplex\n"); 711 bmcr |= PHY_BMCR_DUPLEX; 712 } else { 713 printf("half duplex\n"); 714 bmcr &= ~PHY_BMCR_DUPLEX; 715 } 716 my_phy_writereg(sc, PHY_BMCR, bmcr); 717 my_setcfg(sc, bmcr); 718 MY_UNLOCK(sc); 719 return; 720 } 721 722 /* 723 * The Myson manual states that in order to fiddle with the 'full-duplex' and 724 * '100Mbps' bits in the netconfig register, we first have to put the 725 * transmit and/or receive logic in the idle state. 726 */ 727 static void 728 my_setcfg(struct my_softc * sc, int bmcr) 729 { 730 int i, restart = 0; 731 732 MY_LOCK(sc); 733 if (CSR_READ_4(sc, MY_TCRRCR) & (MY_TE | MY_RE)) { 734 restart = 1; 735 MY_CLRBIT(sc, MY_TCRRCR, (MY_TE | MY_RE)); 736 for (i = 0; i < MY_TIMEOUT; i++) { 737 DELAY(10); 738 if (!(CSR_READ_4(sc, MY_TCRRCR) & 739 (MY_TXRUN | MY_RXRUN))) 740 break; 741 } 742 if (i == MY_TIMEOUT) 743 printf("my%d: failed to force tx and rx to idle \n", 744 sc->my_unit); 745 } 746 MY_CLRBIT(sc, MY_TCRRCR, MY_PS1000); 747 MY_CLRBIT(sc, MY_TCRRCR, MY_PS10); 748 if (bmcr & PHY_BMCR_1000) 749 MY_SETBIT(sc, MY_TCRRCR, MY_PS1000); 750 else if (!(bmcr & PHY_BMCR_SPEEDSEL)) 751 MY_SETBIT(sc, MY_TCRRCR, MY_PS10); 752 if (bmcr & PHY_BMCR_DUPLEX) 753 MY_SETBIT(sc, MY_TCRRCR, MY_FD); 754 else 755 MY_CLRBIT(sc, MY_TCRRCR, MY_FD); 756 if (restart) 757 MY_SETBIT(sc, MY_TCRRCR, MY_TE | MY_RE); 758 MY_UNLOCK(sc); 759 return; 760 } 761 762 static void 763 my_reset(struct my_softc * sc) 764 { 765 register int i; 766 767 MY_LOCK(sc); 768 MY_SETBIT(sc, MY_BCR, MY_SWR); 769 for (i = 0; i < MY_TIMEOUT; i++) { 770 DELAY(10); 771 if (!(CSR_READ_4(sc, MY_BCR) & MY_SWR)) 772 break; 773 } 774 if (i == MY_TIMEOUT) 775 printf("m0x%d: reset never completed!\n", sc->my_unit); 776 777 /* Wait a little while for the chip to get its brains in order. */ 778 DELAY(1000); 779 MY_UNLOCK(sc); 780 return; 781 } 782 783 /* 784 * Probe for a Myson chip. Check the PCI vendor and device IDs against our 785 * list and return a device name if we find a match. 786 */ 787 static int 788 my_probe(device_t dev) 789 { 790 struct my_type *t; 791 792 t = my_devs; 793 while (t->my_name != NULL) { 794 if ((pci_get_vendor(dev) == t->my_vid) && 795 (pci_get_device(dev) == t->my_did)) { 796 device_set_desc(dev, t->my_name); 797 my_info_tmp = t; 798 return (BUS_PROBE_DEFAULT); 799 } 800 t++; 801 } 802 return (ENXIO); 803 } 804 805 /* 806 * Attach the interface. Allocate softc structures, do ifmedia setup and 807 * ethernet/BPF attach. 808 */ 809 static int 810 my_attach(device_t dev) 811 { 812 int s, i; 813 u_char eaddr[ETHER_ADDR_LEN]; 814 u_int32_t command, iobase; 815 struct my_softc *sc; 816 struct ifnet *ifp; 817 int media = IFM_ETHER | IFM_100_TX | IFM_FDX; 818 unsigned int round; 819 caddr_t roundptr; 820 struct my_type *p; 821 u_int16_t phy_vid, phy_did, phy_sts = 0; 822 int rid, unit, error = 0; 823 824 s = splimp(); 825 sc = device_get_softc(dev); 826 unit = device_get_unit(dev); 827 bzero(sc, sizeof(struct my_softc)); 828 mtx_init(&sc->my_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 829 MTX_DEF | MTX_RECURSE); 830 MY_LOCK(sc); 831 832 /* 833 * Map control/status registers. 834 */ 835 #if 0 836 command = pci_read_config(dev, PCI_COMMAND_STATUS_REG, 4); 837 command |= (PCIM_CMD_PORTEN | PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN); 838 pci_write_config(dev, PCI_COMMAND_STATUS_REG, command & 0x000000ff, 4); 839 command = pci_read_config(dev, PCI_COMMAND_STATUS_REG, 4); 840 #endif 841 command = pci_read_config(dev, PCIR_COMMAND, 4); 842 command |= (PCIM_CMD_PORTEN | PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN); 843 pci_write_config(dev, PCIR_COMMAND, command & 0x000000ff, 4); 844 command = pci_read_config(dev, PCIR_COMMAND, 4); 845 846 if (my_info_tmp->my_did == MTD800ID) { 847 iobase = pci_read_config(dev, MY_PCI_LOIO, 4); 848 if (iobase & 0x300) 849 MY_USEIOSPACE = 0; 850 } 851 if (MY_USEIOSPACE) { 852 if (!(command & PCIM_CMD_PORTEN)) { 853 printf("my%d: failed to enable I/O ports!\n", unit); 854 free(sc, M_DEVBUF); 855 error = ENXIO; 856 goto fail; 857 } 858 #if 0 859 if (!pci_map_port(config_id, MY_PCI_LOIO, (u_int16_t *) & (sc->my_bhandle))) { 860 printf("my%d: couldn't map ports\n", unit); 861 error = ENXIO; 862 goto fail; 863 } 864 865 sc->my_btag = I386_BUS_SPACE_IO; 866 #endif 867 } else { 868 if (!(command & PCIM_CMD_MEMEN)) { 869 printf("my%d: failed to enable memory mapping!\n", 870 unit); 871 error = ENXIO; 872 goto fail; 873 } 874 #if 0 875 if (!pci_map_mem(config_id, MY_PCI_LOMEM, &vbase, &pbase)) { 876 printf ("my%d: couldn't map memory\n", unit); 877 error = ENXIO; 878 goto fail; 879 } 880 sc->my_btag = I386_BUS_SPACE_MEM; 881 sc->my_bhandle = vbase; 882 #endif 883 } 884 885 rid = MY_RID; 886 sc->my_res = bus_alloc_resource_any(dev, MY_RES, &rid, RF_ACTIVE); 887 888 if (sc->my_res == NULL) { 889 printf("my%d: couldn't map ports/memory\n", unit); 890 error = ENXIO; 891 goto fail; 892 } 893 sc->my_btag = rman_get_bustag(sc->my_res); 894 sc->my_bhandle = rman_get_bushandle(sc->my_res); 895 896 rid = 0; 897 sc->my_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 898 RF_SHAREABLE | RF_ACTIVE); 899 900 if (sc->my_irq == NULL) { 901 printf("my%d: couldn't map interrupt\n", unit); 902 bus_release_resource(dev, MY_RES, MY_RID, sc->my_res); 903 error = ENXIO; 904 goto fail; 905 } 906 error = bus_setup_intr(dev, sc->my_irq, INTR_TYPE_NET, 907 my_intr, sc, &sc->my_intrhand); 908 909 if (error) { 910 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->my_irq); 911 bus_release_resource(dev, MY_RES, MY_RID, sc->my_res); 912 printf("my%d: couldn't set up irq\n", unit); 913 goto fail; 914 } 915 callout_handle_init(&sc->my_stat_ch); 916 917 sc->my_info = my_info_tmp; 918 919 /* Reset the adapter. */ 920 my_reset(sc); 921 922 /* 923 * Get station address 924 */ 925 for (i = 0; i < ETHER_ADDR_LEN; ++i) 926 eaddr[i] = CSR_READ_1(sc, MY_PAR0 + i); 927 928 sc->my_unit = unit; 929 930 sc->my_ldata_ptr = malloc(sizeof(struct my_list_data) + 8, 931 M_DEVBUF, M_NOWAIT); 932 if (sc->my_ldata_ptr == NULL) { 933 free(sc, M_DEVBUF); 934 printf("my%d: no memory for list buffers!\n", unit); 935 error = ENXIO; 936 goto fail; 937 } 938 sc->my_ldata = (struct my_list_data *) sc->my_ldata_ptr; 939 round = (uintptr_t)sc->my_ldata_ptr & 0xF; 940 roundptr = sc->my_ldata_ptr; 941 for (i = 0; i < 8; i++) { 942 if (round % 8) { 943 round++; 944 roundptr++; 945 } else 946 break; 947 } 948 sc->my_ldata = (struct my_list_data *) roundptr; 949 bzero(sc->my_ldata, sizeof(struct my_list_data)); 950 951 ifp = sc->my_ifp = if_alloc(IFT_ETHER); 952 if (ifp == NULL) { 953 device_printf(dev, "can not if_alloc()\n"); 954 error = ENOSPC; 955 goto fail; 956 } 957 ifp->if_softc = sc; 958 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 959 ifp->if_mtu = ETHERMTU; 960 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 961 ifp->if_ioctl = my_ioctl; 962 ifp->if_start = my_start; 963 ifp->if_watchdog = my_watchdog; 964 ifp->if_init = my_init; 965 ifp->if_baudrate = 10000000; 966 ifp->if_snd.ifq_maxlen = IFQ_MAXLEN; 967 968 if (sc->my_info->my_did == MTD803ID) 969 sc->my_pinfo = my_phys; 970 else { 971 if (bootverbose) 972 printf("my%d: probing for a PHY\n", sc->my_unit); 973 for (i = MY_PHYADDR_MIN; i < MY_PHYADDR_MAX + 1; i++) { 974 if (bootverbose) 975 printf("my%d: checking address: %d\n", 976 sc->my_unit, i); 977 sc->my_phy_addr = i; 978 phy_sts = my_phy_readreg(sc, PHY_BMSR); 979 if ((phy_sts != 0) && (phy_sts != 0xffff)) 980 break; 981 else 982 phy_sts = 0; 983 } 984 if (phy_sts) { 985 phy_vid = my_phy_readreg(sc, PHY_VENID); 986 phy_did = my_phy_readreg(sc, PHY_DEVID); 987 if (bootverbose) { 988 printf("my%d: found PHY at address %d, ", 989 sc->my_unit, sc->my_phy_addr); 990 printf("vendor id: %x device id: %x\n", 991 phy_vid, phy_did); 992 } 993 p = my_phys; 994 while (p->my_vid) { 995 if (phy_vid == p->my_vid) { 996 sc->my_pinfo = p; 997 break; 998 } 999 p++; 1000 } 1001 if (sc->my_pinfo == NULL) 1002 sc->my_pinfo = &my_phys[PHY_UNKNOWN]; 1003 if (bootverbose) 1004 printf("my%d: PHY type: %s\n", 1005 sc->my_unit, sc->my_pinfo->my_name); 1006 } else { 1007 printf("my%d: MII without any phy!\n", sc->my_unit); 1008 error = ENXIO; 1009 goto fail; 1010 } 1011 } 1012 1013 /* Do ifmedia setup. */ 1014 ifmedia_init(&sc->ifmedia, 0, my_ifmedia_upd, my_ifmedia_sts); 1015 my_getmode_mii(sc); 1016 my_autoneg_mii(sc, MY_FLAG_FORCEDELAY, 1); 1017 media = sc->ifmedia.ifm_media; 1018 my_stop(sc); 1019 ifmedia_set(&sc->ifmedia, media); 1020 1021 ether_ifattach(ifp, eaddr); 1022 1023 #if 0 1024 at_shutdown(my_shutdown, sc, SHUTDOWN_POST_SYNC); 1025 shutdownhook_establish(my_shutdown, sc); 1026 #endif 1027 1028 MY_UNLOCK(sc); 1029 return (0); 1030 1031 fail: 1032 MY_UNLOCK(sc); 1033 mtx_destroy(&sc->my_mtx); 1034 if (sc->my_ldata_ptr != NULL) 1035 free(sc->my_ldata_ptr, M_DEVBUF); 1036 splx(s); 1037 return (error); 1038 } 1039 1040 static int 1041 my_detach(device_t dev) 1042 { 1043 struct my_softc *sc; 1044 struct ifnet *ifp; 1045 int s; 1046 1047 s = splimp(); 1048 sc = device_get_softc(dev); 1049 MY_LOCK(sc); 1050 ifp = sc->my_ifp; 1051 ether_ifdetach(ifp); 1052 if_free(ifp); 1053 my_stop(sc); 1054 1055 #if 0 1056 bus_generic_detach(dev); 1057 device_delete_child(dev, sc->rl_miibus); 1058 #endif 1059 1060 bus_teardown_intr(dev, sc->my_irq, sc->my_intrhand); 1061 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->my_irq); 1062 bus_release_resource(dev, MY_RES, MY_RID, sc->my_res); 1063 #if 0 1064 contigfree(sc->my_cdata.my_rx_buf, MY_RXBUFLEN + 32, M_DEVBUF); 1065 #endif 1066 free(sc, M_DEVBUF); 1067 MY_UNLOCK(sc); 1068 splx(s); 1069 mtx_destroy(&sc->my_mtx); 1070 return (0); 1071 } 1072 1073 1074 /* 1075 * Initialize the transmit descriptors. 1076 */ 1077 static int 1078 my_list_tx_init(struct my_softc * sc) 1079 { 1080 struct my_chain_data *cd; 1081 struct my_list_data *ld; 1082 int i; 1083 1084 MY_LOCK(sc); 1085 cd = &sc->my_cdata; 1086 ld = sc->my_ldata; 1087 for (i = 0; i < MY_TX_LIST_CNT; i++) { 1088 cd->my_tx_chain[i].my_ptr = &ld->my_tx_list[i]; 1089 if (i == (MY_TX_LIST_CNT - 1)) 1090 cd->my_tx_chain[i].my_nextdesc = &cd->my_tx_chain[0]; 1091 else 1092 cd->my_tx_chain[i].my_nextdesc = 1093 &cd->my_tx_chain[i + 1]; 1094 } 1095 cd->my_tx_free = &cd->my_tx_chain[0]; 1096 cd->my_tx_tail = cd->my_tx_head = NULL; 1097 MY_UNLOCK(sc); 1098 return (0); 1099 } 1100 1101 /* 1102 * Initialize the RX descriptors and allocate mbufs for them. Note that we 1103 * arrange the descriptors in a closed ring, so that the last descriptor 1104 * points back to the first. 1105 */ 1106 static int 1107 my_list_rx_init(struct my_softc * sc) 1108 { 1109 struct my_chain_data *cd; 1110 struct my_list_data *ld; 1111 int i; 1112 1113 MY_LOCK(sc); 1114 cd = &sc->my_cdata; 1115 ld = sc->my_ldata; 1116 for (i = 0; i < MY_RX_LIST_CNT; i++) { 1117 cd->my_rx_chain[i].my_ptr = 1118 (struct my_desc *) & ld->my_rx_list[i]; 1119 if (my_newbuf(sc, &cd->my_rx_chain[i]) == ENOBUFS) { 1120 MY_UNLOCK(sc); 1121 return (ENOBUFS); 1122 } 1123 if (i == (MY_RX_LIST_CNT - 1)) { 1124 cd->my_rx_chain[i].my_nextdesc = &cd->my_rx_chain[0]; 1125 ld->my_rx_list[i].my_next = vtophys(&ld->my_rx_list[0]); 1126 } else { 1127 cd->my_rx_chain[i].my_nextdesc = 1128 &cd->my_rx_chain[i + 1]; 1129 ld->my_rx_list[i].my_next = 1130 vtophys(&ld->my_rx_list[i + 1]); 1131 } 1132 } 1133 cd->my_rx_head = &cd->my_rx_chain[0]; 1134 MY_UNLOCK(sc); 1135 return (0); 1136 } 1137 1138 /* 1139 * Initialize an RX descriptor and attach an MBUF cluster. 1140 */ 1141 static int 1142 my_newbuf(struct my_softc * sc, struct my_chain_onefrag * c) 1143 { 1144 struct mbuf *m_new = NULL; 1145 1146 MY_LOCK(sc); 1147 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1148 if (m_new == NULL) { 1149 printf("my%d: no memory for rx list -- packet dropped!\n", 1150 sc->my_unit); 1151 MY_UNLOCK(sc); 1152 return (ENOBUFS); 1153 } 1154 MCLGET(m_new, M_DONTWAIT); 1155 if (!(m_new->m_flags & M_EXT)) { 1156 printf("my%d: no memory for rx list -- packet dropped!\n", 1157 sc->my_unit); 1158 m_freem(m_new); 1159 MY_UNLOCK(sc); 1160 return (ENOBUFS); 1161 } 1162 c->my_mbuf = m_new; 1163 c->my_ptr->my_data = vtophys(mtod(m_new, caddr_t)); 1164 c->my_ptr->my_ctl = (MCLBYTES - 1) << MY_RBSShift; 1165 c->my_ptr->my_status = MY_OWNByNIC; 1166 MY_UNLOCK(sc); 1167 return (0); 1168 } 1169 1170 /* 1171 * A frame has been uploaded: pass the resulting mbuf chain up to the higher 1172 * level protocols. 1173 */ 1174 static void 1175 my_rxeof(struct my_softc * sc) 1176 { 1177 struct ether_header *eh; 1178 struct mbuf *m; 1179 struct ifnet *ifp; 1180 struct my_chain_onefrag *cur_rx; 1181 int total_len = 0; 1182 u_int32_t rxstat; 1183 1184 MY_LOCK(sc); 1185 ifp = sc->my_ifp; 1186 while (!((rxstat = sc->my_cdata.my_rx_head->my_ptr->my_status) 1187 & MY_OWNByNIC)) { 1188 cur_rx = sc->my_cdata.my_rx_head; 1189 sc->my_cdata.my_rx_head = cur_rx->my_nextdesc; 1190 1191 if (rxstat & MY_ES) { /* error summary: give up this rx pkt */ 1192 ifp->if_ierrors++; 1193 cur_rx->my_ptr->my_status = MY_OWNByNIC; 1194 continue; 1195 } 1196 /* No errors; receive the packet. */ 1197 total_len = (rxstat & MY_FLNGMASK) >> MY_FLNGShift; 1198 total_len -= ETHER_CRC_LEN; 1199 1200 if (total_len < MINCLSIZE) { 1201 m = m_devget(mtod(cur_rx->my_mbuf, char *), 1202 total_len, 0, ifp, NULL); 1203 cur_rx->my_ptr->my_status = MY_OWNByNIC; 1204 if (m == NULL) { 1205 ifp->if_ierrors++; 1206 continue; 1207 } 1208 } else { 1209 m = cur_rx->my_mbuf; 1210 /* 1211 * Try to conjure up a new mbuf cluster. If that 1212 * fails, it means we have an out of memory condition 1213 * and should leave the buffer in place and continue. 1214 * This will result in a lost packet, but there's 1215 * little else we can do in this situation. 1216 */ 1217 if (my_newbuf(sc, cur_rx) == ENOBUFS) { 1218 ifp->if_ierrors++; 1219 cur_rx->my_ptr->my_status = MY_OWNByNIC; 1220 continue; 1221 } 1222 m->m_pkthdr.rcvif = ifp; 1223 m->m_pkthdr.len = m->m_len = total_len; 1224 } 1225 ifp->if_ipackets++; 1226 eh = mtod(m, struct ether_header *); 1227 #if NBPFILTER > 0 1228 /* 1229 * Handle BPF listeners. Let the BPF user see the packet, but 1230 * don't pass it up to the ether_input() layer unless it's a 1231 * broadcast packet, multicast packet, matches our ethernet 1232 * address or the interface is in promiscuous mode. 1233 */ 1234 if (ifp->if_bpf) { 1235 BPF_MTAP(ifp, m); 1236 if (ifp->if_flags & IFF_PROMISC && 1237 (bcmp(eh->ether_dhost, IFP2ENADDR(sc->my_ifp), 1238 ETHER_ADDR_LEN) && 1239 (eh->ether_dhost[0] & 1) == 0)) { 1240 m_freem(m); 1241 continue; 1242 } 1243 } 1244 #endif 1245 MY_UNLOCK(sc); 1246 (*ifp->if_input)(ifp, m); 1247 MY_LOCK(sc); 1248 } 1249 MY_UNLOCK(sc); 1250 return; 1251 } 1252 1253 1254 /* 1255 * A frame was downloaded to the chip. It's safe for us to clean up the list 1256 * buffers. 1257 */ 1258 static void 1259 my_txeof(struct my_softc * sc) 1260 { 1261 struct my_chain *cur_tx; 1262 struct ifnet *ifp; 1263 1264 MY_LOCK(sc); 1265 ifp = sc->my_ifp; 1266 /* Clear the timeout timer. */ 1267 ifp->if_timer = 0; 1268 if (sc->my_cdata.my_tx_head == NULL) { 1269 MY_UNLOCK(sc); 1270 return; 1271 } 1272 /* 1273 * Go through our tx list and free mbufs for those frames that have 1274 * been transmitted. 1275 */ 1276 while (sc->my_cdata.my_tx_head->my_mbuf != NULL) { 1277 u_int32_t txstat; 1278 1279 cur_tx = sc->my_cdata.my_tx_head; 1280 txstat = MY_TXSTATUS(cur_tx); 1281 if ((txstat & MY_OWNByNIC) || txstat == MY_UNSENT) 1282 break; 1283 if (!(CSR_READ_4(sc, MY_TCRRCR) & MY_Enhanced)) { 1284 if (txstat & MY_TXERR) { 1285 ifp->if_oerrors++; 1286 if (txstat & MY_EC) /* excessive collision */ 1287 ifp->if_collisions++; 1288 if (txstat & MY_LC) /* late collision */ 1289 ifp->if_collisions++; 1290 } 1291 ifp->if_collisions += (txstat & MY_NCRMASK) >> 1292 MY_NCRShift; 1293 } 1294 ifp->if_opackets++; 1295 m_freem(cur_tx->my_mbuf); 1296 cur_tx->my_mbuf = NULL; 1297 if (sc->my_cdata.my_tx_head == sc->my_cdata.my_tx_tail) { 1298 sc->my_cdata.my_tx_head = NULL; 1299 sc->my_cdata.my_tx_tail = NULL; 1300 break; 1301 } 1302 sc->my_cdata.my_tx_head = cur_tx->my_nextdesc; 1303 } 1304 if (CSR_READ_4(sc, MY_TCRRCR) & MY_Enhanced) { 1305 ifp->if_collisions += (CSR_READ_4(sc, MY_TSR) & MY_NCRMask); 1306 } 1307 MY_UNLOCK(sc); 1308 return; 1309 } 1310 1311 /* 1312 * TX 'end of channel' interrupt handler. 1313 */ 1314 static void 1315 my_txeoc(struct my_softc * sc) 1316 { 1317 struct ifnet *ifp; 1318 1319 MY_LOCK(sc); 1320 ifp = sc->my_ifp; 1321 ifp->if_timer = 0; 1322 if (sc->my_cdata.my_tx_head == NULL) { 1323 ifp->if_flags &= ~IFF_OACTIVE; 1324 sc->my_cdata.my_tx_tail = NULL; 1325 if (sc->my_want_auto) 1326 my_autoneg_mii(sc, MY_FLAG_SCHEDDELAY, 1); 1327 } else { 1328 if (MY_TXOWN(sc->my_cdata.my_tx_head) == MY_UNSENT) { 1329 MY_TXOWN(sc->my_cdata.my_tx_head) = MY_OWNByNIC; 1330 ifp->if_timer = 5; 1331 CSR_WRITE_4(sc, MY_TXPDR, 0xFFFFFFFF); 1332 } 1333 } 1334 MY_UNLOCK(sc); 1335 return; 1336 } 1337 1338 static void 1339 my_intr(void *arg) 1340 { 1341 struct my_softc *sc; 1342 struct ifnet *ifp; 1343 u_int32_t status; 1344 1345 sc = arg; 1346 MY_LOCK(sc); 1347 ifp = sc->my_ifp; 1348 if (!(ifp->if_flags & IFF_UP)) { 1349 MY_UNLOCK(sc); 1350 return; 1351 } 1352 /* Disable interrupts. */ 1353 CSR_WRITE_4(sc, MY_IMR, 0x00000000); 1354 1355 for (;;) { 1356 status = CSR_READ_4(sc, MY_ISR); 1357 status &= MY_INTRS; 1358 if (status) 1359 CSR_WRITE_4(sc, MY_ISR, status); 1360 else 1361 break; 1362 1363 if (status & MY_RI) /* receive interrupt */ 1364 my_rxeof(sc); 1365 1366 if ((status & MY_RBU) || (status & MY_RxErr)) { 1367 /* rx buffer unavailable or rx error */ 1368 ifp->if_ierrors++; 1369 #ifdef foo 1370 my_stop(sc); 1371 my_reset(sc); 1372 my_init(sc); 1373 #endif 1374 } 1375 if (status & MY_TI) /* tx interrupt */ 1376 my_txeof(sc); 1377 if (status & MY_ETI) /* tx early interrupt */ 1378 my_txeof(sc); 1379 if (status & MY_TBU) /* tx buffer unavailable */ 1380 my_txeoc(sc); 1381 1382 #if 0 /* 90/1/18 delete */ 1383 if (status & MY_FBE) { 1384 my_reset(sc); 1385 my_init(sc); 1386 } 1387 #endif 1388 1389 } 1390 1391 /* Re-enable interrupts. */ 1392 CSR_WRITE_4(sc, MY_IMR, MY_INTRS); 1393 if (ifp->if_snd.ifq_head != NULL) 1394 my_start(ifp); 1395 MY_UNLOCK(sc); 1396 return; 1397 } 1398 1399 /* 1400 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1401 * pointers to the fragment pointers. 1402 */ 1403 static int 1404 my_encap(struct my_softc * sc, struct my_chain * c, struct mbuf * m_head) 1405 { 1406 struct my_desc *f = NULL; 1407 int total_len; 1408 struct mbuf *m, *m_new = NULL; 1409 1410 MY_LOCK(sc); 1411 /* calculate the total tx pkt length */ 1412 total_len = 0; 1413 for (m = m_head; m != NULL; m = m->m_next) 1414 total_len += m->m_len; 1415 /* 1416 * Start packing the mbufs in this chain into the fragment pointers. 1417 * Stop when we run out of fragments or hit the end of the mbuf 1418 * chain. 1419 */ 1420 m = m_head; 1421 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1422 if (m_new == NULL) { 1423 printf("my%d: no memory for tx list", sc->my_unit); 1424 MY_UNLOCK(sc); 1425 return (1); 1426 } 1427 if (m_head->m_pkthdr.len > MHLEN) { 1428 MCLGET(m_new, M_DONTWAIT); 1429 if (!(m_new->m_flags & M_EXT)) { 1430 m_freem(m_new); 1431 printf("my%d: no memory for tx list", sc->my_unit); 1432 MY_UNLOCK(sc); 1433 return (1); 1434 } 1435 } 1436 m_copydata(m_head, 0, m_head->m_pkthdr.len, mtod(m_new, caddr_t)); 1437 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1438 m_freem(m_head); 1439 m_head = m_new; 1440 f = &c->my_ptr->my_frag[0]; 1441 f->my_status = 0; 1442 f->my_data = vtophys(mtod(m_new, caddr_t)); 1443 total_len = m_new->m_len; 1444 f->my_ctl = MY_TXFD | MY_TXLD | MY_CRCEnable | MY_PADEnable; 1445 f->my_ctl |= total_len << MY_PKTShift; /* pkt size */ 1446 f->my_ctl |= total_len; /* buffer size */ 1447 /* 89/12/29 add, for mtd891 *//* [ 89? ] */ 1448 if (sc->my_info->my_did == MTD891ID) 1449 f->my_ctl |= MY_ETIControl | MY_RetryTxLC; 1450 c->my_mbuf = m_head; 1451 c->my_lastdesc = 0; 1452 MY_TXNEXT(c) = vtophys(&c->my_nextdesc->my_ptr->my_frag[0]); 1453 MY_UNLOCK(sc); 1454 return (0); 1455 } 1456 1457 /* 1458 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1459 * to the mbuf data regions directly in the transmit lists. We also save a 1460 * copy of the pointers since the transmit list fragment pointers are 1461 * physical addresses. 1462 */ 1463 static void 1464 my_start(struct ifnet * ifp) 1465 { 1466 struct my_softc *sc; 1467 struct mbuf *m_head = NULL; 1468 struct my_chain *cur_tx = NULL, *start_tx; 1469 1470 sc = ifp->if_softc; 1471 MY_LOCK(sc); 1472 if (sc->my_autoneg) { 1473 sc->my_tx_pend = 1; 1474 MY_UNLOCK(sc); 1475 return; 1476 } 1477 /* 1478 * Check for an available queue slot. If there are none, punt. 1479 */ 1480 if (sc->my_cdata.my_tx_free->my_mbuf != NULL) { 1481 ifp->if_flags |= IFF_OACTIVE; 1482 MY_UNLOCK(sc); 1483 return; 1484 } 1485 start_tx = sc->my_cdata.my_tx_free; 1486 while (sc->my_cdata.my_tx_free->my_mbuf == NULL) { 1487 IF_DEQUEUE(&ifp->if_snd, m_head); 1488 if (m_head == NULL) 1489 break; 1490 1491 /* Pick a descriptor off the free list. */ 1492 cur_tx = sc->my_cdata.my_tx_free; 1493 sc->my_cdata.my_tx_free = cur_tx->my_nextdesc; 1494 1495 /* Pack the data into the descriptor. */ 1496 my_encap(sc, cur_tx, m_head); 1497 1498 if (cur_tx != start_tx) 1499 MY_TXOWN(cur_tx) = MY_OWNByNIC; 1500 #if NBPFILTER > 0 1501 /* 1502 * If there's a BPF listener, bounce a copy of this frame to 1503 * him. 1504 */ 1505 BPF_MTAP(ifp, cur_tx->my_mbuf); 1506 #endif 1507 } 1508 /* 1509 * If there are no packets queued, bail. 1510 */ 1511 if (cur_tx == NULL) { 1512 MY_UNLOCK(sc); 1513 return; 1514 } 1515 /* 1516 * Place the request for the upload interrupt in the last descriptor 1517 * in the chain. This way, if we're chaining several packets at once, 1518 * we'll only get an interupt once for the whole chain rather than 1519 * once for each packet. 1520 */ 1521 MY_TXCTL(cur_tx) |= MY_TXIC; 1522 cur_tx->my_ptr->my_frag[0].my_ctl |= MY_TXIC; 1523 sc->my_cdata.my_tx_tail = cur_tx; 1524 if (sc->my_cdata.my_tx_head == NULL) 1525 sc->my_cdata.my_tx_head = start_tx; 1526 MY_TXOWN(start_tx) = MY_OWNByNIC; 1527 CSR_WRITE_4(sc, MY_TXPDR, 0xFFFFFFFF); /* tx polling demand */ 1528 1529 /* 1530 * Set a timeout in case the chip goes out to lunch. 1531 */ 1532 ifp->if_timer = 5; 1533 MY_UNLOCK(sc); 1534 return; 1535 } 1536 1537 static void 1538 my_init(void *xsc) 1539 { 1540 struct my_softc *sc = xsc; 1541 struct ifnet *ifp = sc->my_ifp; 1542 int s; 1543 u_int16_t phy_bmcr = 0; 1544 1545 MY_LOCK(sc); 1546 if (sc->my_autoneg) { 1547 MY_UNLOCK(sc); 1548 return; 1549 } 1550 s = splimp(); 1551 if (sc->my_pinfo != NULL) 1552 phy_bmcr = my_phy_readreg(sc, PHY_BMCR); 1553 /* 1554 * Cancel pending I/O and free all RX/TX buffers. 1555 */ 1556 my_stop(sc); 1557 my_reset(sc); 1558 1559 /* 1560 * Set cache alignment and burst length. 1561 */ 1562 #if 0 /* 89/9/1 modify, */ 1563 CSR_WRITE_4(sc, MY_BCR, MY_RPBLE512); 1564 CSR_WRITE_4(sc, MY_TCRRCR, MY_TFTSF); 1565 #endif 1566 CSR_WRITE_4(sc, MY_BCR, MY_PBL8); 1567 CSR_WRITE_4(sc, MY_TCRRCR, MY_TFTSF | MY_RBLEN | MY_RPBLE512); 1568 /* 1569 * 89/12/29 add, for mtd891, 1570 */ 1571 if (sc->my_info->my_did == MTD891ID) { 1572 MY_SETBIT(sc, MY_BCR, MY_PROG); 1573 MY_SETBIT(sc, MY_TCRRCR, MY_Enhanced); 1574 } 1575 my_setcfg(sc, phy_bmcr); 1576 /* Init circular RX list. */ 1577 if (my_list_rx_init(sc) == ENOBUFS) { 1578 printf("my%d: init failed: no memory for rx buffers\n", 1579 sc->my_unit); 1580 my_stop(sc); 1581 (void)splx(s); 1582 MY_UNLOCK(sc); 1583 return; 1584 } 1585 /* Init TX descriptors. */ 1586 my_list_tx_init(sc); 1587 1588 /* If we want promiscuous mode, set the allframes bit. */ 1589 if (ifp->if_flags & IFF_PROMISC) 1590 MY_SETBIT(sc, MY_TCRRCR, MY_PROM); 1591 else 1592 MY_CLRBIT(sc, MY_TCRRCR, MY_PROM); 1593 1594 /* 1595 * Set capture broadcast bit to capture broadcast frames. 1596 */ 1597 if (ifp->if_flags & IFF_BROADCAST) 1598 MY_SETBIT(sc, MY_TCRRCR, MY_AB); 1599 else 1600 MY_CLRBIT(sc, MY_TCRRCR, MY_AB); 1601 1602 /* 1603 * Program the multicast filter, if necessary. 1604 */ 1605 my_setmulti(sc); 1606 1607 /* 1608 * Load the address of the RX list. 1609 */ 1610 MY_CLRBIT(sc, MY_TCRRCR, MY_RE); 1611 CSR_WRITE_4(sc, MY_RXLBA, vtophys(&sc->my_ldata->my_rx_list[0])); 1612 1613 /* 1614 * Enable interrupts. 1615 */ 1616 CSR_WRITE_4(sc, MY_IMR, MY_INTRS); 1617 CSR_WRITE_4(sc, MY_ISR, 0xFFFFFFFF); 1618 1619 /* Enable receiver and transmitter. */ 1620 MY_SETBIT(sc, MY_TCRRCR, MY_RE); 1621 MY_CLRBIT(sc, MY_TCRRCR, MY_TE); 1622 CSR_WRITE_4(sc, MY_TXLBA, vtophys(&sc->my_ldata->my_tx_list[0])); 1623 MY_SETBIT(sc, MY_TCRRCR, MY_TE); 1624 1625 /* Restore state of BMCR */ 1626 if (sc->my_pinfo != NULL) 1627 my_phy_writereg(sc, PHY_BMCR, phy_bmcr); 1628 ifp->if_flags |= IFF_RUNNING; 1629 ifp->if_flags &= ~IFF_OACTIVE; 1630 (void)splx(s); 1631 MY_UNLOCK(sc); 1632 return; 1633 } 1634 1635 /* 1636 * Set media options. 1637 */ 1638 1639 static int 1640 my_ifmedia_upd(struct ifnet * ifp) 1641 { 1642 struct my_softc *sc; 1643 struct ifmedia *ifm; 1644 1645 sc = ifp->if_softc; 1646 MY_LOCK(sc); 1647 ifm = &sc->ifmedia; 1648 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) { 1649 MY_UNLOCK(sc); 1650 return (EINVAL); 1651 } 1652 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO) 1653 my_autoneg_mii(sc, MY_FLAG_SCHEDDELAY, 1); 1654 else 1655 my_setmode_mii(sc, ifm->ifm_media); 1656 MY_UNLOCK(sc); 1657 return (0); 1658 } 1659 1660 /* 1661 * Report current media status. 1662 */ 1663 1664 static void 1665 my_ifmedia_sts(struct ifnet * ifp, struct ifmediareq * ifmr) 1666 { 1667 struct my_softc *sc; 1668 u_int16_t advert = 0, ability = 0; 1669 1670 sc = ifp->if_softc; 1671 MY_LOCK(sc); 1672 ifmr->ifm_active = IFM_ETHER; 1673 if (!(my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_AUTONEGENBL)) { 1674 #if 0 /* this version did not support 1000M, */ 1675 if (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_1000) 1676 ifmr->ifm_active = IFM_ETHER | IFM_1000TX; 1677 #endif 1678 if (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_SPEEDSEL) 1679 ifmr->ifm_active = IFM_ETHER | IFM_100_TX; 1680 else 1681 ifmr->ifm_active = IFM_ETHER | IFM_10_T; 1682 if (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_DUPLEX) 1683 ifmr->ifm_active |= IFM_FDX; 1684 else 1685 ifmr->ifm_active |= IFM_HDX; 1686 1687 MY_UNLOCK(sc); 1688 return; 1689 } 1690 ability = my_phy_readreg(sc, PHY_LPAR); 1691 advert = my_phy_readreg(sc, PHY_ANAR); 1692 1693 #if 0 /* this version did not support 1000M, */ 1694 if (sc->my_pinfo->my_vid = MarvellPHYID0) { 1695 ability2 = my_phy_readreg(sc, PHY_1000SR); 1696 if (ability2 & PHY_1000SR_1000BTXFULL) { 1697 advert = 0; 1698 ability = 0; 1699 ifmr->ifm_active = IFM_ETHER|IFM_1000_T|IFM_FDX; 1700 } else if (ability & PHY_1000SR_1000BTXHALF) { 1701 advert = 0; 1702 ability = 0; 1703 ifmr->ifm_active = IFM_ETHER|IFM_1000_T|IFM_HDX; 1704 } 1705 } 1706 #endif 1707 if (advert & PHY_ANAR_100BT4 && ability & PHY_ANAR_100BT4) 1708 ifmr->ifm_active = IFM_ETHER | IFM_100_T4; 1709 else if (advert & PHY_ANAR_100BTXFULL && ability & PHY_ANAR_100BTXFULL) 1710 ifmr->ifm_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 1711 else if (advert & PHY_ANAR_100BTXHALF && ability & PHY_ANAR_100BTXHALF) 1712 ifmr->ifm_active = IFM_ETHER | IFM_100_TX | IFM_HDX; 1713 else if (advert & PHY_ANAR_10BTFULL && ability & PHY_ANAR_10BTFULL) 1714 ifmr->ifm_active = IFM_ETHER | IFM_10_T | IFM_FDX; 1715 else if (advert & PHY_ANAR_10BTHALF && ability & PHY_ANAR_10BTHALF) 1716 ifmr->ifm_active = IFM_ETHER | IFM_10_T | IFM_HDX; 1717 MY_UNLOCK(sc); 1718 return; 1719 } 1720 1721 static int 1722 my_ioctl(struct ifnet * ifp, u_long command, caddr_t data) 1723 { 1724 struct my_softc *sc = ifp->if_softc; 1725 struct ifreq *ifr = (struct ifreq *) data; 1726 int s, error = 0; 1727 1728 s = splimp(); 1729 MY_LOCK(sc); 1730 switch (command) { 1731 case SIOCSIFFLAGS: 1732 if (ifp->if_flags & IFF_UP) 1733 my_init(sc); 1734 else if (ifp->if_flags & IFF_RUNNING) 1735 my_stop(sc); 1736 error = 0; 1737 break; 1738 case SIOCADDMULTI: 1739 case SIOCDELMULTI: 1740 my_setmulti(sc); 1741 error = 0; 1742 break; 1743 case SIOCGIFMEDIA: 1744 case SIOCSIFMEDIA: 1745 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); 1746 break; 1747 default: 1748 error = ether_ioctl(ifp, command, data); 1749 break; 1750 } 1751 MY_UNLOCK(sc); 1752 (void)splx(s); 1753 return (error); 1754 } 1755 1756 static void 1757 my_watchdog(struct ifnet * ifp) 1758 { 1759 struct my_softc *sc; 1760 1761 sc = ifp->if_softc; 1762 MY_LOCK(sc); 1763 if (sc->my_autoneg) { 1764 my_autoneg_mii(sc, MY_FLAG_DELAYTIMEO, 1); 1765 MY_UNLOCK(sc); 1766 return; 1767 } 1768 ifp->if_oerrors++; 1769 printf("my%d: watchdog timeout\n", sc->my_unit); 1770 if (!(my_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT)) 1771 printf("my%d: no carrier - transceiver cable problem?\n", 1772 sc->my_unit); 1773 my_stop(sc); 1774 my_reset(sc); 1775 my_init(sc); 1776 if (ifp->if_snd.ifq_head != NULL) 1777 my_start(ifp); 1778 MY_LOCK(sc); 1779 return; 1780 } 1781 1782 1783 /* 1784 * Stop the adapter and free any mbufs allocated to the RX and TX lists. 1785 */ 1786 static void 1787 my_stop(struct my_softc * sc) 1788 { 1789 register int i; 1790 struct ifnet *ifp; 1791 1792 MY_LOCK(sc); 1793 ifp = sc->my_ifp; 1794 ifp->if_timer = 0; 1795 1796 MY_CLRBIT(sc, MY_TCRRCR, (MY_RE | MY_TE)); 1797 CSR_WRITE_4(sc, MY_IMR, 0x00000000); 1798 CSR_WRITE_4(sc, MY_TXLBA, 0x00000000); 1799 CSR_WRITE_4(sc, MY_RXLBA, 0x00000000); 1800 1801 /* 1802 * Free data in the RX lists. 1803 */ 1804 for (i = 0; i < MY_RX_LIST_CNT; i++) { 1805 if (sc->my_cdata.my_rx_chain[i].my_mbuf != NULL) { 1806 m_freem(sc->my_cdata.my_rx_chain[i].my_mbuf); 1807 sc->my_cdata.my_rx_chain[i].my_mbuf = NULL; 1808 } 1809 } 1810 bzero((char *)&sc->my_ldata->my_rx_list, 1811 sizeof(sc->my_ldata->my_rx_list)); 1812 /* 1813 * Free the TX list buffers. 1814 */ 1815 for (i = 0; i < MY_TX_LIST_CNT; i++) { 1816 if (sc->my_cdata.my_tx_chain[i].my_mbuf != NULL) { 1817 m_freem(sc->my_cdata.my_tx_chain[i].my_mbuf); 1818 sc->my_cdata.my_tx_chain[i].my_mbuf = NULL; 1819 } 1820 } 1821 bzero((char *)&sc->my_ldata->my_tx_list, 1822 sizeof(sc->my_ldata->my_tx_list)); 1823 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1824 MY_UNLOCK(sc); 1825 return; 1826 } 1827 1828 /* 1829 * Stop all chip I/O so that the kernel's probe routines don't get confused 1830 * by errant DMAs when rebooting. 1831 */ 1832 static void 1833 my_shutdown(device_t dev) 1834 { 1835 struct my_softc *sc; 1836 1837 sc = device_get_softc(dev); 1838 my_stop(sc); 1839 return; 1840 } 1841