1 /*- 2 * Written by: yen_cw@myson.com.tw 3 * Copyright (c) 2002 Myson Technology Inc. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions, and the following disclaimer, 11 * without modification, immediately at the beginning of the file. 12 * 2. The name of the author may not be used to endorse or promote products 13 * derived from this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 19 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * Myson fast ethernet PCI NIC driver, available at: http://www.myson.com.tw/ 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/sockio.h> 36 #include <sys/mbuf.h> 37 #include <sys/malloc.h> 38 #include <sys/kernel.h> 39 #include <sys/socket.h> 40 #include <sys/queue.h> 41 #include <sys/types.h> 42 #include <sys/bus.h> 43 #include <sys/module.h> 44 #include <sys/lock.h> 45 #include <sys/mutex.h> 46 47 #define NBPFILTER 1 48 49 #include <net/if.h> 50 #include <net/if_arp.h> 51 #include <net/ethernet.h> 52 #include <net/if_media.h> 53 #include <net/if_dl.h> 54 #include <net/bpf.h> 55 56 #include <vm/vm.h> /* for vtophys */ 57 #include <vm/pmap.h> /* for vtophys */ 58 #include <machine/clock.h> /* for DELAY */ 59 #include <machine/bus_memio.h> 60 #include <machine/bus_pio.h> 61 #include <machine/bus.h> 62 #include <machine/resource.h> 63 #include <sys/bus.h> 64 #include <sys/rman.h> 65 66 #include <dev/pci/pcireg.h> 67 #include <dev/pci/pcivar.h> 68 69 #include <dev/mii/mii.h> 70 #include <dev/mii/miivar.h> 71 72 #include "miibus_if.h" 73 74 /* 75 * #define MY_USEIOSPACE 76 */ 77 78 static int MY_USEIOSPACE = 1; 79 80 #if (MY_USEIOSPACE) 81 #define MY_RES SYS_RES_IOPORT 82 #define MY_RID MY_PCI_LOIO 83 #else 84 #define MY_RES SYS_RES_MEMORY 85 #define MY_RID MY_PCI_LOMEM 86 #endif 87 88 89 #include <dev/my/if_myreg.h> 90 91 #ifndef lint 92 static const char rcsid[] = 93 "$Id: if_my.c,v 1.16 2003/04/15 06:37:25 mdodd Exp $"; 94 #endif 95 96 /* 97 * Various supported device vendors/types and their names. 98 */ 99 struct my_type *my_info_tmp; 100 static struct my_type my_devs[] = { 101 {MYSONVENDORID, MTD800ID, "Myson MTD80X Based Fast Ethernet Card"}, 102 {MYSONVENDORID, MTD803ID, "Myson MTD80X Based Fast Ethernet Card"}, 103 {MYSONVENDORID, MTD891ID, "Myson MTD89X Based Giga Ethernet Card"}, 104 {0, 0, NULL} 105 }; 106 107 /* 108 * Various supported PHY vendors/types and their names. Note that this driver 109 * will work with pretty much any MII-compliant PHY, so failure to positively 110 * identify the chip is not a fatal error. 111 */ 112 static struct my_type my_phys[] = { 113 {MysonPHYID0, MysonPHYID0, "<MYSON MTD981>"}, 114 {SeeqPHYID0, SeeqPHYID0, "<SEEQ 80225>"}, 115 {AhdocPHYID0, AhdocPHYID0, "<AHDOC 101>"}, 116 {MarvellPHYID0, MarvellPHYID0, "<MARVELL 88E1000>"}, 117 {LevelOnePHYID0, LevelOnePHYID0, "<LevelOne LXT1000>"}, 118 {0, 0, "<MII-compliant physical interface>"} 119 }; 120 121 static int my_probe(device_t); 122 static int my_attach(device_t); 123 static int my_detach(device_t); 124 static int my_newbuf(struct my_softc *, struct my_chain_onefrag *); 125 static int my_encap(struct my_softc *, struct my_chain *, struct mbuf *); 126 static void my_rxeof(struct my_softc *); 127 static void my_txeof(struct my_softc *); 128 static void my_txeoc(struct my_softc *); 129 static void my_intr(void *); 130 static void my_start(struct ifnet *); 131 static int my_ioctl(struct ifnet *, u_long, caddr_t); 132 static void my_init(void *); 133 static void my_stop(struct my_softc *); 134 static void my_watchdog(struct ifnet *); 135 static void my_shutdown(device_t); 136 static int my_ifmedia_upd(struct ifnet *); 137 static void my_ifmedia_sts(struct ifnet *, struct ifmediareq *); 138 static u_int16_t my_phy_readreg(struct my_softc *, int); 139 static void my_phy_writereg(struct my_softc *, int, int); 140 static void my_autoneg_xmit(struct my_softc *); 141 static void my_autoneg_mii(struct my_softc *, int, int); 142 static void my_setmode_mii(struct my_softc *, int); 143 static void my_getmode_mii(struct my_softc *); 144 static void my_setcfg(struct my_softc *, int); 145 static u_int8_t my_calchash(caddr_t); 146 static void my_setmulti(struct my_softc *); 147 static void my_reset(struct my_softc *); 148 static int my_list_rx_init(struct my_softc *); 149 static int my_list_tx_init(struct my_softc *); 150 static long my_send_cmd_to_phy(struct my_softc *, int, int); 151 152 #define MY_SETBIT(sc, reg, x) CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 153 #define MY_CLRBIT(sc, reg, x) CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 154 155 static device_method_t my_methods[] = { 156 /* Device interface */ 157 DEVMETHOD(device_probe, my_probe), 158 DEVMETHOD(device_attach, my_attach), 159 DEVMETHOD(device_detach, my_detach), 160 DEVMETHOD(device_shutdown, my_shutdown), 161 162 {0, 0} 163 }; 164 165 static driver_t my_driver = { 166 "my", 167 my_methods, 168 sizeof(struct my_softc) 169 }; 170 171 static devclass_t my_devclass; 172 173 DRIVER_MODULE(my, pci, my_driver, my_devclass, 0, 0); 174 MODULE_DEPEND(my, pci, 1, 1, 1); 175 MODULE_DEPEND(my, ether, 1, 1, 1); 176 177 static long 178 my_send_cmd_to_phy(struct my_softc * sc, int opcode, int regad) 179 { 180 long miir; 181 int i; 182 int mask, data; 183 184 MY_LOCK(sc); 185 186 /* enable MII output */ 187 miir = CSR_READ_4(sc, MY_MANAGEMENT); 188 miir &= 0xfffffff0; 189 190 miir |= MY_MASK_MIIR_MII_WRITE + MY_MASK_MIIR_MII_MDO; 191 192 /* send 32 1's preamble */ 193 for (i = 0; i < 32; i++) { 194 /* low MDC; MDO is already high (miir) */ 195 miir &= ~MY_MASK_MIIR_MII_MDC; 196 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 197 198 /* high MDC */ 199 miir |= MY_MASK_MIIR_MII_MDC; 200 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 201 } 202 203 /* calculate ST+OP+PHYAD+REGAD+TA */ 204 data = opcode | (sc->my_phy_addr << 7) | (regad << 2); 205 206 /* sent out */ 207 mask = 0x8000; 208 while (mask) { 209 /* low MDC, prepare MDO */ 210 miir &= ~(MY_MASK_MIIR_MII_MDC + MY_MASK_MIIR_MII_MDO); 211 if (mask & data) 212 miir |= MY_MASK_MIIR_MII_MDO; 213 214 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 215 /* high MDC */ 216 miir |= MY_MASK_MIIR_MII_MDC; 217 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 218 DELAY(30); 219 220 /* next */ 221 mask >>= 1; 222 if (mask == 0x2 && opcode == MY_OP_READ) 223 miir &= ~MY_MASK_MIIR_MII_WRITE; 224 } 225 226 MY_UNLOCK(sc); 227 return miir; 228 } 229 230 231 static u_int16_t 232 my_phy_readreg(struct my_softc * sc, int reg) 233 { 234 long miir; 235 int mask, data; 236 237 MY_LOCK(sc); 238 239 if (sc->my_info->my_did == MTD803ID) 240 data = CSR_READ_2(sc, MY_PHYBASE + reg * 2); 241 else { 242 miir = my_send_cmd_to_phy(sc, MY_OP_READ, reg); 243 244 /* read data */ 245 mask = 0x8000; 246 data = 0; 247 while (mask) { 248 /* low MDC */ 249 miir &= ~MY_MASK_MIIR_MII_MDC; 250 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 251 252 /* read MDI */ 253 miir = CSR_READ_4(sc, MY_MANAGEMENT); 254 if (miir & MY_MASK_MIIR_MII_MDI) 255 data |= mask; 256 257 /* high MDC, and wait */ 258 miir |= MY_MASK_MIIR_MII_MDC; 259 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 260 DELAY(30); 261 262 /* next */ 263 mask >>= 1; 264 } 265 266 /* low MDC */ 267 miir &= ~MY_MASK_MIIR_MII_MDC; 268 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 269 } 270 271 MY_UNLOCK(sc); 272 return (u_int16_t) data; 273 } 274 275 276 static void 277 my_phy_writereg(struct my_softc * sc, int reg, int data) 278 { 279 long miir; 280 int mask; 281 282 MY_LOCK(sc); 283 284 if (sc->my_info->my_did == MTD803ID) 285 CSR_WRITE_2(sc, MY_PHYBASE + reg * 2, data); 286 else { 287 miir = my_send_cmd_to_phy(sc, MY_OP_WRITE, reg); 288 289 /* write data */ 290 mask = 0x8000; 291 while (mask) { 292 /* low MDC, prepare MDO */ 293 miir &= ~(MY_MASK_MIIR_MII_MDC + MY_MASK_MIIR_MII_MDO); 294 if (mask & data) 295 miir |= MY_MASK_MIIR_MII_MDO; 296 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 297 DELAY(1); 298 299 /* high MDC */ 300 miir |= MY_MASK_MIIR_MII_MDC; 301 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 302 DELAY(1); 303 304 /* next */ 305 mask >>= 1; 306 } 307 308 /* low MDC */ 309 miir &= ~MY_MASK_MIIR_MII_MDC; 310 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 311 } 312 MY_UNLOCK(sc); 313 return; 314 } 315 316 static u_int8_t 317 my_calchash(caddr_t addr) 318 { 319 u_int32_t crc, carry; 320 int i, j; 321 u_int8_t c; 322 323 /* Compute CRC for the address value. */ 324 crc = 0xFFFFFFFF; /* initial value */ 325 326 for (i = 0; i < 6; i++) { 327 c = *(addr + i); 328 for (j = 0; j < 8; j++) { 329 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 330 crc <<= 1; 331 c >>= 1; 332 if (carry) 333 crc = (crc ^ 0x04c11db6) | carry; 334 } 335 } 336 337 /* 338 * return the filter bit position Note: I arrived at the following 339 * nonsense through experimentation. It's not the usual way to 340 * generate the bit position but it's the only thing I could come up 341 * with that works. 342 */ 343 return (~(crc >> 26) & 0x0000003F); 344 } 345 346 347 /* 348 * Program the 64-bit multicast hash filter. 349 */ 350 static void 351 my_setmulti(struct my_softc * sc) 352 { 353 struct ifnet *ifp; 354 int h = 0; 355 u_int32_t hashes[2] = {0, 0}; 356 struct ifmultiaddr *ifma; 357 u_int32_t rxfilt; 358 int mcnt = 0; 359 360 MY_LOCK(sc); 361 362 ifp = &sc->arpcom.ac_if; 363 364 rxfilt = CSR_READ_4(sc, MY_TCRRCR); 365 366 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 367 rxfilt |= MY_AM; 368 CSR_WRITE_4(sc, MY_TCRRCR, rxfilt); 369 CSR_WRITE_4(sc, MY_MAR0, 0xFFFFFFFF); 370 CSR_WRITE_4(sc, MY_MAR1, 0xFFFFFFFF); 371 372 MY_UNLOCK(sc); 373 374 return; 375 } 376 /* first, zot all the existing hash bits */ 377 CSR_WRITE_4(sc, MY_MAR0, 0); 378 CSR_WRITE_4(sc, MY_MAR1, 0); 379 380 /* now program new ones */ 381 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 382 if (ifma->ifma_addr->sa_family != AF_LINK) 383 continue; 384 h = my_calchash(LLADDR((struct sockaddr_dl *) ifma->ifma_addr)); 385 if (h < 32) 386 hashes[0] |= (1 << h); 387 else 388 hashes[1] |= (1 << (h - 32)); 389 mcnt++; 390 } 391 392 if (mcnt) 393 rxfilt |= MY_AM; 394 else 395 rxfilt &= ~MY_AM; 396 CSR_WRITE_4(sc, MY_MAR0, hashes[0]); 397 CSR_WRITE_4(sc, MY_MAR1, hashes[1]); 398 CSR_WRITE_4(sc, MY_TCRRCR, rxfilt); 399 MY_UNLOCK(sc); 400 return; 401 } 402 403 /* 404 * Initiate an autonegotiation session. 405 */ 406 static void 407 my_autoneg_xmit(struct my_softc * sc) 408 { 409 u_int16_t phy_sts = 0; 410 411 MY_LOCK(sc); 412 413 my_phy_writereg(sc, PHY_BMCR, PHY_BMCR_RESET); 414 DELAY(500); 415 while (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_RESET); 416 417 phy_sts = my_phy_readreg(sc, PHY_BMCR); 418 phy_sts |= PHY_BMCR_AUTONEGENBL | PHY_BMCR_AUTONEGRSTR; 419 my_phy_writereg(sc, PHY_BMCR, phy_sts); 420 421 MY_UNLOCK(sc); 422 return; 423 } 424 425 426 /* 427 * Invoke autonegotiation on a PHY. 428 */ 429 static void 430 my_autoneg_mii(struct my_softc * sc, int flag, int verbose) 431 { 432 u_int16_t phy_sts = 0, media, advert, ability; 433 u_int16_t ability2 = 0; 434 struct ifnet *ifp; 435 struct ifmedia *ifm; 436 437 MY_LOCK(sc); 438 439 ifm = &sc->ifmedia; 440 ifp = &sc->arpcom.ac_if; 441 442 ifm->ifm_media = IFM_ETHER | IFM_AUTO; 443 444 #ifndef FORCE_AUTONEG_TFOUR 445 /* 446 * First, see if autoneg is supported. If not, there's no point in 447 * continuing. 448 */ 449 phy_sts = my_phy_readreg(sc, PHY_BMSR); 450 if (!(phy_sts & PHY_BMSR_CANAUTONEG)) { 451 if (verbose) 452 printf("my%d: autonegotiation not supported\n", 453 sc->my_unit); 454 ifm->ifm_media = IFM_ETHER | IFM_10_T | IFM_HDX; 455 MY_UNLOCK(sc); 456 return; 457 } 458 #endif 459 switch (flag) { 460 case MY_FLAG_FORCEDELAY: 461 /* 462 * XXX Never use this option anywhere but in the probe 463 * routine: making the kernel stop dead in its tracks for 464 * three whole seconds after we've gone multi-user is really 465 * bad manners. 466 */ 467 my_autoneg_xmit(sc); 468 DELAY(5000000); 469 break; 470 case MY_FLAG_SCHEDDELAY: 471 /* 472 * Wait for the transmitter to go idle before starting an 473 * autoneg session, otherwise my_start() may clobber our 474 * timeout, and we don't want to allow transmission during an 475 * autoneg session since that can screw it up. 476 */ 477 if (sc->my_cdata.my_tx_head != NULL) { 478 sc->my_want_auto = 1; 479 MY_UNLOCK(sc); 480 return; 481 } 482 my_autoneg_xmit(sc); 483 ifp->if_timer = 5; 484 sc->my_autoneg = 1; 485 sc->my_want_auto = 0; 486 MY_UNLOCK(sc); 487 return; 488 case MY_FLAG_DELAYTIMEO: 489 ifp->if_timer = 0; 490 sc->my_autoneg = 0; 491 break; 492 default: 493 printf("my%d: invalid autoneg flag: %d\n", sc->my_unit, flag); 494 MY_UNLOCK(sc); 495 return; 496 } 497 498 if (my_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_AUTONEGCOMP) { 499 if (verbose) 500 printf("my%d: autoneg complete, ", sc->my_unit); 501 phy_sts = my_phy_readreg(sc, PHY_BMSR); 502 } else { 503 if (verbose) 504 printf("my%d: autoneg not complete, ", sc->my_unit); 505 } 506 507 media = my_phy_readreg(sc, PHY_BMCR); 508 509 /* Link is good. Report modes and set duplex mode. */ 510 if (my_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT) { 511 if (verbose) 512 printf("my%d: link status good. ", sc->my_unit); 513 advert = my_phy_readreg(sc, PHY_ANAR); 514 ability = my_phy_readreg(sc, PHY_LPAR); 515 if ((sc->my_pinfo->my_vid == MarvellPHYID0) || 516 (sc->my_pinfo->my_vid == LevelOnePHYID0)) { 517 ability2 = my_phy_readreg(sc, PHY_1000SR); 518 if (ability2 & PHY_1000SR_1000BTXFULL) { 519 advert = 0; 520 ability = 0; 521 /* 522 * this version did not support 1000M, 523 * ifm->ifm_media = 524 * IFM_ETHER|IFM_1000_T|IFM_FDX; 525 */ 526 ifm->ifm_media = 527 IFM_ETHER | IFM_100_TX | IFM_FDX; 528 media &= ~PHY_BMCR_SPEEDSEL; 529 media |= PHY_BMCR_1000; 530 media |= PHY_BMCR_DUPLEX; 531 printf("(full-duplex, 1000Mbps)\n"); 532 } else if (ability2 & PHY_1000SR_1000BTXHALF) { 533 advert = 0; 534 ability = 0; 535 /* 536 * this version did not support 1000M, 537 * ifm->ifm_media = IFM_ETHER|IFM_1000_T; 538 */ 539 ifm->ifm_media = IFM_ETHER | IFM_100_TX; 540 media &= ~PHY_BMCR_SPEEDSEL; 541 media &= ~PHY_BMCR_DUPLEX; 542 media |= PHY_BMCR_1000; 543 printf("(half-duplex, 1000Mbps)\n"); 544 } 545 } 546 if (advert & PHY_ANAR_100BT4 && ability & PHY_ANAR_100BT4) { 547 ifm->ifm_media = IFM_ETHER | IFM_100_T4; 548 media |= PHY_BMCR_SPEEDSEL; 549 media &= ~PHY_BMCR_DUPLEX; 550 printf("(100baseT4)\n"); 551 } else if (advert & PHY_ANAR_100BTXFULL && 552 ability & PHY_ANAR_100BTXFULL) { 553 ifm->ifm_media = IFM_ETHER | IFM_100_TX | IFM_FDX; 554 media |= PHY_BMCR_SPEEDSEL; 555 media |= PHY_BMCR_DUPLEX; 556 printf("(full-duplex, 100Mbps)\n"); 557 } else if (advert & PHY_ANAR_100BTXHALF && 558 ability & PHY_ANAR_100BTXHALF) { 559 ifm->ifm_media = IFM_ETHER | IFM_100_TX | IFM_HDX; 560 media |= PHY_BMCR_SPEEDSEL; 561 media &= ~PHY_BMCR_DUPLEX; 562 printf("(half-duplex, 100Mbps)\n"); 563 } else if (advert & PHY_ANAR_10BTFULL && 564 ability & PHY_ANAR_10BTFULL) { 565 ifm->ifm_media = IFM_ETHER | IFM_10_T | IFM_FDX; 566 media &= ~PHY_BMCR_SPEEDSEL; 567 media |= PHY_BMCR_DUPLEX; 568 printf("(full-duplex, 10Mbps)\n"); 569 } else if (advert) { 570 ifm->ifm_media = IFM_ETHER | IFM_10_T | IFM_HDX; 571 media &= ~PHY_BMCR_SPEEDSEL; 572 media &= ~PHY_BMCR_DUPLEX; 573 printf("(half-duplex, 10Mbps)\n"); 574 } 575 media &= ~PHY_BMCR_AUTONEGENBL; 576 577 /* Set ASIC's duplex mode to match the PHY. */ 578 my_phy_writereg(sc, PHY_BMCR, media); 579 my_setcfg(sc, media); 580 } else { 581 if (verbose) 582 printf("my%d: no carrier\n", sc->my_unit); 583 } 584 585 my_init(sc); 586 if (sc->my_tx_pend) { 587 sc->my_autoneg = 0; 588 sc->my_tx_pend = 0; 589 my_start(ifp); 590 } 591 MY_UNLOCK(sc); 592 return; 593 } 594 595 /* 596 * To get PHY ability. 597 */ 598 static void 599 my_getmode_mii(struct my_softc * sc) 600 { 601 u_int16_t bmsr; 602 struct ifnet *ifp; 603 604 MY_LOCK(sc); 605 ifp = &sc->arpcom.ac_if; 606 bmsr = my_phy_readreg(sc, PHY_BMSR); 607 if (bootverbose) 608 printf("my%d: PHY status word: %x\n", sc->my_unit, bmsr); 609 610 /* fallback */ 611 sc->ifmedia.ifm_media = IFM_ETHER | IFM_10_T | IFM_HDX; 612 613 if (bmsr & PHY_BMSR_10BTHALF) { 614 if (bootverbose) 615 printf("my%d: 10Mbps half-duplex mode supported\n", 616 sc->my_unit); 617 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_10_T | IFM_HDX, 618 0, NULL); 619 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_10_T, 0, NULL); 620 } 621 if (bmsr & PHY_BMSR_10BTFULL) { 622 if (bootverbose) 623 printf("my%d: 10Mbps full-duplex mode supported\n", 624 sc->my_unit); 625 626 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_10_T | IFM_FDX, 627 0, NULL); 628 sc->ifmedia.ifm_media = IFM_ETHER | IFM_10_T | IFM_FDX; 629 } 630 if (bmsr & PHY_BMSR_100BTXHALF) { 631 if (bootverbose) 632 printf("my%d: 100Mbps half-duplex mode supported\n", 633 sc->my_unit); 634 ifp->if_baudrate = 100000000; 635 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_TX, 0, NULL); 636 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_TX | IFM_HDX, 637 0, NULL); 638 sc->ifmedia.ifm_media = IFM_ETHER | IFM_100_TX | IFM_HDX; 639 } 640 if (bmsr & PHY_BMSR_100BTXFULL) { 641 if (bootverbose) 642 printf("my%d: 100Mbps full-duplex mode supported\n", 643 sc->my_unit); 644 ifp->if_baudrate = 100000000; 645 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_TX | IFM_FDX, 646 0, NULL); 647 sc->ifmedia.ifm_media = IFM_ETHER | IFM_100_TX | IFM_FDX; 648 } 649 /* Some also support 100BaseT4. */ 650 if (bmsr & PHY_BMSR_100BT4) { 651 if (bootverbose) 652 printf("my%d: 100baseT4 mode supported\n", sc->my_unit); 653 ifp->if_baudrate = 100000000; 654 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_T4, 0, NULL); 655 sc->ifmedia.ifm_media = IFM_ETHER | IFM_100_T4; 656 #ifdef FORCE_AUTONEG_TFOUR 657 if (bootverbose) 658 printf("my%d: forcing on autoneg support for BT4\n", 659 sc->my_unit); 660 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_AUTO, 0 NULL): 661 sc->ifmedia.ifm_media = IFM_ETHER | IFM_AUTO; 662 #endif 663 } 664 #if 0 /* this version did not support 1000M, */ 665 if (sc->my_pinfo->my_vid == MarvellPHYID0) { 666 if (bootverbose) 667 printf("my%d: 1000Mbps half-duplex mode supported\n", 668 sc->my_unit); 669 670 ifp->if_baudrate = 1000000000; 671 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_T, 0, NULL); 672 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_T | IFM_HDX, 673 0, NULL); 674 if (bootverbose) 675 printf("my%d: 1000Mbps full-duplex mode supported\n", 676 sc->my_unit); 677 ifp->if_baudrate = 1000000000; 678 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_T | IFM_FDX, 679 0, NULL); 680 sc->ifmedia.ifm_media = IFM_ETHER | IFM_1000_T | IFM_FDX; 681 } 682 #endif 683 if (bmsr & PHY_BMSR_CANAUTONEG) { 684 if (bootverbose) 685 printf("my%d: autoneg supported\n", sc->my_unit); 686 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 687 sc->ifmedia.ifm_media = IFM_ETHER | IFM_AUTO; 688 } 689 MY_UNLOCK(sc); 690 return; 691 } 692 693 /* 694 * Set speed and duplex mode. 695 */ 696 static void 697 my_setmode_mii(struct my_softc * sc, int media) 698 { 699 u_int16_t bmcr; 700 struct ifnet *ifp; 701 702 MY_LOCK(sc); 703 ifp = &sc->arpcom.ac_if; 704 /* 705 * If an autoneg session is in progress, stop it. 706 */ 707 if (sc->my_autoneg) { 708 printf("my%d: canceling autoneg session\n", sc->my_unit); 709 ifp->if_timer = sc->my_autoneg = sc->my_want_auto = 0; 710 bmcr = my_phy_readreg(sc, PHY_BMCR); 711 bmcr &= ~PHY_BMCR_AUTONEGENBL; 712 my_phy_writereg(sc, PHY_BMCR, bmcr); 713 } 714 printf("my%d: selecting MII, ", sc->my_unit); 715 bmcr = my_phy_readreg(sc, PHY_BMCR); 716 bmcr &= ~(PHY_BMCR_AUTONEGENBL | PHY_BMCR_SPEEDSEL | PHY_BMCR_1000 | 717 PHY_BMCR_DUPLEX | PHY_BMCR_LOOPBK); 718 719 #if 0 /* this version did not support 1000M, */ 720 if (IFM_SUBTYPE(media) == IFM_1000_T) { 721 printf("1000Mbps/T4, half-duplex\n"); 722 bmcr &= ~PHY_BMCR_SPEEDSEL; 723 bmcr &= ~PHY_BMCR_DUPLEX; 724 bmcr |= PHY_BMCR_1000; 725 } 726 #endif 727 if (IFM_SUBTYPE(media) == IFM_100_T4) { 728 printf("100Mbps/T4, half-duplex\n"); 729 bmcr |= PHY_BMCR_SPEEDSEL; 730 bmcr &= ~PHY_BMCR_DUPLEX; 731 } 732 if (IFM_SUBTYPE(media) == IFM_100_TX) { 733 printf("100Mbps, "); 734 bmcr |= PHY_BMCR_SPEEDSEL; 735 } 736 if (IFM_SUBTYPE(media) == IFM_10_T) { 737 printf("10Mbps, "); 738 bmcr &= ~PHY_BMCR_SPEEDSEL; 739 } 740 if ((media & IFM_GMASK) == IFM_FDX) { 741 printf("full duplex\n"); 742 bmcr |= PHY_BMCR_DUPLEX; 743 } else { 744 printf("half duplex\n"); 745 bmcr &= ~PHY_BMCR_DUPLEX; 746 } 747 my_phy_writereg(sc, PHY_BMCR, bmcr); 748 my_setcfg(sc, bmcr); 749 MY_UNLOCK(sc); 750 return; 751 } 752 753 /* 754 * The Myson manual states that in order to fiddle with the 'full-duplex' and 755 * '100Mbps' bits in the netconfig register, we first have to put the 756 * transmit and/or receive logic in the idle state. 757 */ 758 static void 759 my_setcfg(struct my_softc * sc, int bmcr) 760 { 761 int i, restart = 0; 762 763 MY_LOCK(sc); 764 if (CSR_READ_4(sc, MY_TCRRCR) & (MY_TE | MY_RE)) { 765 restart = 1; 766 MY_CLRBIT(sc, MY_TCRRCR, (MY_TE | MY_RE)); 767 for (i = 0; i < MY_TIMEOUT; i++) { 768 DELAY(10); 769 if (!(CSR_READ_4(sc, MY_TCRRCR) & 770 (MY_TXRUN | MY_RXRUN))) 771 break; 772 } 773 if (i == MY_TIMEOUT) 774 printf("my%d: failed to force tx and rx to idle \n", 775 sc->my_unit); 776 } 777 MY_CLRBIT(sc, MY_TCRRCR, MY_PS1000); 778 MY_CLRBIT(sc, MY_TCRRCR, MY_PS10); 779 if (bmcr & PHY_BMCR_1000) 780 MY_SETBIT(sc, MY_TCRRCR, MY_PS1000); 781 else if (!(bmcr & PHY_BMCR_SPEEDSEL)) 782 MY_SETBIT(sc, MY_TCRRCR, MY_PS10); 783 if (bmcr & PHY_BMCR_DUPLEX) 784 MY_SETBIT(sc, MY_TCRRCR, MY_FD); 785 else 786 MY_CLRBIT(sc, MY_TCRRCR, MY_FD); 787 if (restart) 788 MY_SETBIT(sc, MY_TCRRCR, MY_TE | MY_RE); 789 MY_UNLOCK(sc); 790 return; 791 } 792 793 static void 794 my_reset(struct my_softc * sc) 795 { 796 register int i; 797 798 MY_LOCK(sc); 799 MY_SETBIT(sc, MY_BCR, MY_SWR); 800 for (i = 0; i < MY_TIMEOUT; i++) { 801 DELAY(10); 802 if (!(CSR_READ_4(sc, MY_BCR) & MY_SWR)) 803 break; 804 } 805 if (i == MY_TIMEOUT) 806 printf("m0x%d: reset never completed!\n", sc->my_unit); 807 808 /* Wait a little while for the chip to get its brains in order. */ 809 DELAY(1000); 810 MY_UNLOCK(sc); 811 return; 812 } 813 814 /* 815 * Probe for a Myson chip. Check the PCI vendor and device IDs against our 816 * list and return a device name if we find a match. 817 */ 818 static int 819 my_probe(device_t dev) 820 { 821 struct my_type *t; 822 823 t = my_devs; 824 while (t->my_name != NULL) { 825 if ((pci_get_vendor(dev) == t->my_vid) && 826 (pci_get_device(dev) == t->my_did)) { 827 device_set_desc(dev, t->my_name); 828 my_info_tmp = t; 829 return (0); 830 } 831 t++; 832 } 833 return (ENXIO); 834 } 835 836 /* 837 * Attach the interface. Allocate softc structures, do ifmedia setup and 838 * ethernet/BPF attach. 839 */ 840 static int 841 my_attach(device_t dev) 842 { 843 int s, i; 844 u_char eaddr[ETHER_ADDR_LEN]; 845 u_int32_t command, iobase; 846 struct my_softc *sc; 847 struct ifnet *ifp; 848 int media = IFM_ETHER | IFM_100_TX | IFM_FDX; 849 unsigned int round; 850 caddr_t roundptr; 851 struct my_type *p; 852 u_int16_t phy_vid, phy_did, phy_sts = 0; 853 int rid, unit, error = 0; 854 855 s = splimp(); 856 sc = device_get_softc(dev); 857 unit = device_get_unit(dev); 858 if (sc == NULL) { 859 printf("my%d: no memory for softc struct!\n", unit); 860 error = ENXIO; 861 goto fail; 862 863 } 864 bzero(sc, sizeof(struct my_softc)); 865 mtx_init(&sc->my_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 866 MTX_DEF | MTX_RECURSE); 867 MY_LOCK(sc); 868 869 /* 870 * Map control/status registers. 871 */ 872 #if 0 873 command = pci_read_config(dev, PCI_COMMAND_STATUS_REG, 4); 874 command |= (PCIM_CMD_PORTEN | PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN); 875 pci_write_config(dev, PCI_COMMAND_STATUS_REG, command & 0x000000ff, 4); 876 command = pci_read_config(dev, PCI_COMMAND_STATUS_REG, 4); 877 #endif 878 command = pci_read_config(dev, PCIR_COMMAND, 4); 879 command |= (PCIM_CMD_PORTEN | PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN); 880 pci_write_config(dev, PCIR_COMMAND, command & 0x000000ff, 4); 881 command = pci_read_config(dev, PCIR_COMMAND, 4); 882 883 if (my_info_tmp->my_did == MTD800ID) { 884 iobase = pci_read_config(dev, MY_PCI_LOIO, 4); 885 if (iobase & 0x300) 886 MY_USEIOSPACE = 0; 887 } 888 if (MY_USEIOSPACE) { 889 if (!(command & PCIM_CMD_PORTEN)) { 890 printf("my%d: failed to enable I/O ports!\n", unit); 891 free(sc, M_DEVBUF); 892 error = ENXIO; 893 goto fail; 894 } 895 #if 0 896 if (!pci_map_port(config_id, MY_PCI_LOIO, (u_int16_t *) & (sc->my_bhandle))) { 897 printf("my%d: couldn't map ports\n", unit); 898 error = ENXIO; 899 goto fail; 900 } 901 902 sc->my_btag = I386_BUS_SPACE_IO; 903 #endif 904 } else { 905 if (!(command & PCIM_CMD_MEMEN)) { 906 printf("my%d: failed to enable memory mapping!\n", 907 unit); 908 error = ENXIO; 909 goto fail; 910 } 911 #if 0 912 if (!pci_map_mem(config_id, MY_PCI_LOMEM, &vbase, &pbase)) { 913 printf ("my%d: couldn't map memory\n", unit); 914 error = ENXIO; 915 goto fail; 916 } 917 sc->my_btag = I386_BUS_SPACE_MEM; 918 sc->my_bhandle = vbase; 919 #endif 920 } 921 922 rid = MY_RID; 923 sc->my_res = bus_alloc_resource(dev, MY_RES, &rid, 924 0, ~0, 1, RF_ACTIVE); 925 926 if (sc->my_res == NULL) { 927 printf("my%d: couldn't map ports/memory\n", unit); 928 error = ENXIO; 929 goto fail; 930 } 931 sc->my_btag = rman_get_bustag(sc->my_res); 932 sc->my_bhandle = rman_get_bushandle(sc->my_res); 933 934 rid = 0; 935 sc->my_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 936 RF_SHAREABLE | RF_ACTIVE); 937 938 if (sc->my_irq == NULL) { 939 printf("my%d: couldn't map interrupt\n", unit); 940 bus_release_resource(dev, MY_RES, MY_RID, sc->my_res); 941 error = ENXIO; 942 goto fail; 943 } 944 error = bus_setup_intr(dev, sc->my_irq, INTR_TYPE_NET, 945 my_intr, sc, &sc->my_intrhand); 946 947 if (error) { 948 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->my_irq); 949 bus_release_resource(dev, MY_RES, MY_RID, sc->my_res); 950 printf("my%d: couldn't set up irq\n", unit); 951 goto fail; 952 } 953 callout_handle_init(&sc->my_stat_ch); 954 955 sc->my_info = my_info_tmp; 956 957 /* Reset the adapter. */ 958 my_reset(sc); 959 960 /* 961 * Get station address 962 */ 963 for (i = 0; i < ETHER_ADDR_LEN; ++i) 964 eaddr[i] = CSR_READ_1(sc, MY_PAR0 + i); 965 966 /* 967 * A Myson chip was detected. Inform the world. 968 */ 969 printf("my%d: Ethernet address: %6D\n", unit, eaddr, ":"); 970 971 sc->my_unit = unit; 972 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 973 974 sc->my_ldata_ptr = malloc(sizeof(struct my_list_data) + 8, 975 M_DEVBUF, M_NOWAIT); 976 if (sc->my_ldata_ptr == NULL) { 977 free(sc, M_DEVBUF); 978 printf("my%d: no memory for list buffers!\n", unit); 979 error = ENXIO; 980 goto fail; 981 } 982 sc->my_ldata = (struct my_list_data *) sc->my_ldata_ptr; 983 round = (uintptr_t)sc->my_ldata_ptr & 0xF; 984 roundptr = sc->my_ldata_ptr; 985 for (i = 0; i < 8; i++) { 986 if (round % 8) { 987 round++; 988 roundptr++; 989 } else 990 break; 991 } 992 sc->my_ldata = (struct my_list_data *) roundptr; 993 bzero(sc->my_ldata, sizeof(struct my_list_data)); 994 995 ifp = &sc->arpcom.ac_if; 996 ifp->if_softc = sc; 997 ifp->if_unit = unit; 998 ifp->if_name = "my"; 999 ifp->if_mtu = ETHERMTU; 1000 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1001 ifp->if_ioctl = my_ioctl; 1002 ifp->if_output = ether_output; 1003 ifp->if_start = my_start; 1004 ifp->if_watchdog = my_watchdog; 1005 ifp->if_init = my_init; 1006 ifp->if_baudrate = 10000000; 1007 ifp->if_snd.ifq_maxlen = IFQ_MAXLEN; 1008 1009 if (sc->my_info->my_did == MTD803ID) 1010 sc->my_pinfo = my_phys; 1011 else { 1012 if (bootverbose) 1013 printf("my%d: probing for a PHY\n", sc->my_unit); 1014 for (i = MY_PHYADDR_MIN; i < MY_PHYADDR_MAX + 1; i++) { 1015 if (bootverbose) 1016 printf("my%d: checking address: %d\n", 1017 sc->my_unit, i); 1018 sc->my_phy_addr = i; 1019 phy_sts = my_phy_readreg(sc, PHY_BMSR); 1020 if ((phy_sts != 0) && (phy_sts != 0xffff)) 1021 break; 1022 else 1023 phy_sts = 0; 1024 } 1025 if (phy_sts) { 1026 phy_vid = my_phy_readreg(sc, PHY_VENID); 1027 phy_did = my_phy_readreg(sc, PHY_DEVID); 1028 if (bootverbose) { 1029 printf("my%d: found PHY at address %d, ", 1030 sc->my_unit, sc->my_phy_addr); 1031 printf("vendor id: %x device id: %x\n", 1032 phy_vid, phy_did); 1033 } 1034 p = my_phys; 1035 while (p->my_vid) { 1036 if (phy_vid == p->my_vid) { 1037 sc->my_pinfo = p; 1038 break; 1039 } 1040 p++; 1041 } 1042 if (sc->my_pinfo == NULL) 1043 sc->my_pinfo = &my_phys[PHY_UNKNOWN]; 1044 if (bootverbose) 1045 printf("my%d: PHY type: %s\n", 1046 sc->my_unit, sc->my_pinfo->my_name); 1047 } else { 1048 printf("my%d: MII without any phy!\n", sc->my_unit); 1049 error = ENXIO; 1050 goto fail; 1051 } 1052 } 1053 1054 /* Do ifmedia setup. */ 1055 ifmedia_init(&sc->ifmedia, 0, my_ifmedia_upd, my_ifmedia_sts); 1056 my_getmode_mii(sc); 1057 my_autoneg_mii(sc, MY_FLAG_FORCEDELAY, 1); 1058 media = sc->ifmedia.ifm_media; 1059 my_stop(sc); 1060 ifmedia_set(&sc->ifmedia, media); 1061 1062 ether_ifattach(ifp, eaddr); 1063 1064 #if 0 1065 at_shutdown(my_shutdown, sc, SHUTDOWN_POST_SYNC); 1066 shutdownhook_establish(my_shutdown, sc); 1067 #endif 1068 1069 MY_UNLOCK(sc); 1070 return (0); 1071 1072 fail: 1073 MY_UNLOCK(sc); 1074 mtx_destroy(&sc->my_mtx); 1075 splx(s); 1076 return (error); 1077 } 1078 1079 static int 1080 my_detach(device_t dev) 1081 { 1082 struct my_softc *sc; 1083 struct ifnet *ifp; 1084 int s; 1085 1086 s = splimp(); 1087 sc = device_get_softc(dev); 1088 MY_LOCK(sc); 1089 ifp = &sc->arpcom.ac_if; 1090 ether_ifdetach(ifp); 1091 my_stop(sc); 1092 1093 #if 0 1094 bus_generic_detach(dev); 1095 device_delete_child(dev, sc->rl_miibus); 1096 #endif 1097 1098 bus_teardown_intr(dev, sc->my_irq, sc->my_intrhand); 1099 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->my_irq); 1100 bus_release_resource(dev, MY_RES, MY_RID, sc->my_res); 1101 #if 0 1102 contigfree(sc->my_cdata.my_rx_buf, MY_RXBUFLEN + 32, M_DEVBUF); 1103 #endif 1104 free(sc, M_DEVBUF); 1105 MY_UNLOCK(sc); 1106 splx(s); 1107 mtx_destroy(&sc->my_mtx); 1108 return (0); 1109 } 1110 1111 1112 /* 1113 * Initialize the transmit descriptors. 1114 */ 1115 static int 1116 my_list_tx_init(struct my_softc * sc) 1117 { 1118 struct my_chain_data *cd; 1119 struct my_list_data *ld; 1120 int i; 1121 1122 MY_LOCK(sc); 1123 cd = &sc->my_cdata; 1124 ld = sc->my_ldata; 1125 for (i = 0; i < MY_TX_LIST_CNT; i++) { 1126 cd->my_tx_chain[i].my_ptr = &ld->my_tx_list[i]; 1127 if (i == (MY_TX_LIST_CNT - 1)) 1128 cd->my_tx_chain[i].my_nextdesc = &cd->my_tx_chain[0]; 1129 else 1130 cd->my_tx_chain[i].my_nextdesc = 1131 &cd->my_tx_chain[i + 1]; 1132 } 1133 cd->my_tx_free = &cd->my_tx_chain[0]; 1134 cd->my_tx_tail = cd->my_tx_head = NULL; 1135 MY_UNLOCK(sc); 1136 return (0); 1137 } 1138 1139 /* 1140 * Initialize the RX descriptors and allocate mbufs for them. Note that we 1141 * arrange the descriptors in a closed ring, so that the last descriptor 1142 * points back to the first. 1143 */ 1144 static int 1145 my_list_rx_init(struct my_softc * sc) 1146 { 1147 struct my_chain_data *cd; 1148 struct my_list_data *ld; 1149 int i; 1150 1151 MY_LOCK(sc); 1152 cd = &sc->my_cdata; 1153 ld = sc->my_ldata; 1154 for (i = 0; i < MY_RX_LIST_CNT; i++) { 1155 cd->my_rx_chain[i].my_ptr = 1156 (struct my_desc *) & ld->my_rx_list[i]; 1157 if (my_newbuf(sc, &cd->my_rx_chain[i]) == ENOBUFS) { 1158 MY_UNLOCK(sc); 1159 return (ENOBUFS); 1160 } 1161 if (i == (MY_RX_LIST_CNT - 1)) { 1162 cd->my_rx_chain[i].my_nextdesc = &cd->my_rx_chain[0]; 1163 ld->my_rx_list[i].my_next = vtophys(&ld->my_rx_list[0]); 1164 } else { 1165 cd->my_rx_chain[i].my_nextdesc = 1166 &cd->my_rx_chain[i + 1]; 1167 ld->my_rx_list[i].my_next = 1168 vtophys(&ld->my_rx_list[i + 1]); 1169 } 1170 } 1171 cd->my_rx_head = &cd->my_rx_chain[0]; 1172 MY_UNLOCK(sc); 1173 return (0); 1174 } 1175 1176 /* 1177 * Initialize an RX descriptor and attach an MBUF cluster. 1178 */ 1179 static int 1180 my_newbuf(struct my_softc * sc, struct my_chain_onefrag * c) 1181 { 1182 struct mbuf *m_new = NULL; 1183 1184 MY_LOCK(sc); 1185 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1186 if (m_new == NULL) { 1187 printf("my%d: no memory for rx list -- packet dropped!\n", 1188 sc->my_unit); 1189 MY_UNLOCK(sc); 1190 return (ENOBUFS); 1191 } 1192 MCLGET(m_new, M_DONTWAIT); 1193 if (!(m_new->m_flags & M_EXT)) { 1194 printf("my%d: no memory for rx list -- packet dropped!\n", 1195 sc->my_unit); 1196 m_freem(m_new); 1197 MY_UNLOCK(sc); 1198 return (ENOBUFS); 1199 } 1200 c->my_mbuf = m_new; 1201 c->my_ptr->my_data = vtophys(mtod(m_new, caddr_t)); 1202 c->my_ptr->my_ctl = (MCLBYTES - 1) << MY_RBSShift; 1203 c->my_ptr->my_status = MY_OWNByNIC; 1204 MY_UNLOCK(sc); 1205 return (0); 1206 } 1207 1208 /* 1209 * A frame has been uploaded: pass the resulting mbuf chain up to the higher 1210 * level protocols. 1211 */ 1212 static void 1213 my_rxeof(struct my_softc * sc) 1214 { 1215 struct ether_header *eh; 1216 struct mbuf *m; 1217 struct ifnet *ifp; 1218 struct my_chain_onefrag *cur_rx; 1219 int total_len = 0; 1220 u_int32_t rxstat; 1221 1222 MY_LOCK(sc); 1223 ifp = &sc->arpcom.ac_if; 1224 while (!((rxstat = sc->my_cdata.my_rx_head->my_ptr->my_status) 1225 & MY_OWNByNIC)) { 1226 cur_rx = sc->my_cdata.my_rx_head; 1227 sc->my_cdata.my_rx_head = cur_rx->my_nextdesc; 1228 1229 if (rxstat & MY_ES) { /* error summary: give up this rx pkt */ 1230 ifp->if_ierrors++; 1231 cur_rx->my_ptr->my_status = MY_OWNByNIC; 1232 continue; 1233 } 1234 /* No errors; receive the packet. */ 1235 total_len = (rxstat & MY_FLNGMASK) >> MY_FLNGShift; 1236 total_len -= ETHER_CRC_LEN; 1237 1238 if (total_len < MINCLSIZE) { 1239 m = m_devget(mtod(cur_rx->my_mbuf, char *), 1240 total_len, 0, ifp, NULL); 1241 cur_rx->my_ptr->my_status = MY_OWNByNIC; 1242 if (m == NULL) { 1243 ifp->if_ierrors++; 1244 continue; 1245 } 1246 } else { 1247 m = cur_rx->my_mbuf; 1248 /* 1249 * Try to conjure up a new mbuf cluster. If that 1250 * fails, it means we have an out of memory condition 1251 * and should leave the buffer in place and continue. 1252 * This will result in a lost packet, but there's 1253 * little else we can do in this situation. 1254 */ 1255 if (my_newbuf(sc, cur_rx) == ENOBUFS) { 1256 ifp->if_ierrors++; 1257 cur_rx->my_ptr->my_status = MY_OWNByNIC; 1258 continue; 1259 } 1260 m->m_pkthdr.rcvif = ifp; 1261 m->m_pkthdr.len = m->m_len = total_len; 1262 } 1263 ifp->if_ipackets++; 1264 eh = mtod(m, struct ether_header *); 1265 #if NBPFILTER > 0 1266 /* 1267 * Handle BPF listeners. Let the BPF user see the packet, but 1268 * don't pass it up to the ether_input() layer unless it's a 1269 * broadcast packet, multicast packet, matches our ethernet 1270 * address or the interface is in promiscuous mode. 1271 */ 1272 if (ifp->if_bpf) { 1273 BPF_MTAP(ifp, m); 1274 if (ifp->if_flags & IFF_PROMISC && 1275 (bcmp(eh->ether_dhost, sc->arpcom.ac_enaddr, 1276 ETHER_ADDR_LEN) && 1277 (eh->ether_dhost[0] & 1) == 0)) { 1278 m_freem(m); 1279 continue; 1280 } 1281 } 1282 #endif 1283 (*ifp->if_input)(ifp, m); 1284 } 1285 MY_UNLOCK(sc); 1286 return; 1287 } 1288 1289 1290 /* 1291 * A frame was downloaded to the chip. It's safe for us to clean up the list 1292 * buffers. 1293 */ 1294 static void 1295 my_txeof(struct my_softc * sc) 1296 { 1297 struct my_chain *cur_tx; 1298 struct ifnet *ifp; 1299 1300 MY_LOCK(sc); 1301 ifp = &sc->arpcom.ac_if; 1302 /* Clear the timeout timer. */ 1303 ifp->if_timer = 0; 1304 if (sc->my_cdata.my_tx_head == NULL) { 1305 MY_UNLOCK(sc); 1306 return; 1307 } 1308 /* 1309 * Go through our tx list and free mbufs for those frames that have 1310 * been transmitted. 1311 */ 1312 while (sc->my_cdata.my_tx_head->my_mbuf != NULL) { 1313 u_int32_t txstat; 1314 1315 cur_tx = sc->my_cdata.my_tx_head; 1316 txstat = MY_TXSTATUS(cur_tx); 1317 if ((txstat & MY_OWNByNIC) || txstat == MY_UNSENT) 1318 break; 1319 if (!(CSR_READ_4(sc, MY_TCRRCR) & MY_Enhanced)) { 1320 if (txstat & MY_TXERR) { 1321 ifp->if_oerrors++; 1322 if (txstat & MY_EC) /* excessive collision */ 1323 ifp->if_collisions++; 1324 if (txstat & MY_LC) /* late collision */ 1325 ifp->if_collisions++; 1326 } 1327 ifp->if_collisions += (txstat & MY_NCRMASK) >> 1328 MY_NCRShift; 1329 } 1330 ifp->if_opackets++; 1331 m_freem(cur_tx->my_mbuf); 1332 cur_tx->my_mbuf = NULL; 1333 if (sc->my_cdata.my_tx_head == sc->my_cdata.my_tx_tail) { 1334 sc->my_cdata.my_tx_head = NULL; 1335 sc->my_cdata.my_tx_tail = NULL; 1336 break; 1337 } 1338 sc->my_cdata.my_tx_head = cur_tx->my_nextdesc; 1339 } 1340 if (CSR_READ_4(sc, MY_TCRRCR) & MY_Enhanced) { 1341 ifp->if_collisions += (CSR_READ_4(sc, MY_TSR) & MY_NCRMask); 1342 } 1343 MY_UNLOCK(sc); 1344 return; 1345 } 1346 1347 /* 1348 * TX 'end of channel' interrupt handler. 1349 */ 1350 static void 1351 my_txeoc(struct my_softc * sc) 1352 { 1353 struct ifnet *ifp; 1354 1355 MY_LOCK(sc); 1356 ifp = &sc->arpcom.ac_if; 1357 ifp->if_timer = 0; 1358 if (sc->my_cdata.my_tx_head == NULL) { 1359 ifp->if_flags &= ~IFF_OACTIVE; 1360 sc->my_cdata.my_tx_tail = NULL; 1361 if (sc->my_want_auto) 1362 my_autoneg_mii(sc, MY_FLAG_SCHEDDELAY, 1); 1363 } else { 1364 if (MY_TXOWN(sc->my_cdata.my_tx_head) == MY_UNSENT) { 1365 MY_TXOWN(sc->my_cdata.my_tx_head) = MY_OWNByNIC; 1366 ifp->if_timer = 5; 1367 CSR_WRITE_4(sc, MY_TXPDR, 0xFFFFFFFF); 1368 } 1369 } 1370 MY_UNLOCK(sc); 1371 return; 1372 } 1373 1374 static void 1375 my_intr(void *arg) 1376 { 1377 struct my_softc *sc; 1378 struct ifnet *ifp; 1379 u_int32_t status; 1380 1381 sc = arg; 1382 MY_LOCK(sc); 1383 ifp = &sc->arpcom.ac_if; 1384 if (!(ifp->if_flags & IFF_UP)) { 1385 MY_UNLOCK(sc); 1386 return; 1387 } 1388 /* Disable interrupts. */ 1389 CSR_WRITE_4(sc, MY_IMR, 0x00000000); 1390 1391 for (;;) { 1392 status = CSR_READ_4(sc, MY_ISR); 1393 status &= MY_INTRS; 1394 if (status) 1395 CSR_WRITE_4(sc, MY_ISR, status); 1396 else 1397 break; 1398 1399 if (status & MY_RI) /* receive interrupt */ 1400 my_rxeof(sc); 1401 1402 if ((status & MY_RBU) || (status & MY_RxErr)) { 1403 /* rx buffer unavailable or rx error */ 1404 ifp->if_ierrors++; 1405 #ifdef foo 1406 my_stop(sc); 1407 my_reset(sc); 1408 my_init(sc); 1409 #endif 1410 } 1411 if (status & MY_TI) /* tx interrupt */ 1412 my_txeof(sc); 1413 if (status & MY_ETI) /* tx early interrupt */ 1414 my_txeof(sc); 1415 if (status & MY_TBU) /* tx buffer unavailable */ 1416 my_txeoc(sc); 1417 1418 #if 0 /* 90/1/18 delete */ 1419 if (status & MY_FBE) { 1420 my_reset(sc); 1421 my_init(sc); 1422 } 1423 #endif 1424 1425 } 1426 1427 /* Re-enable interrupts. */ 1428 CSR_WRITE_4(sc, MY_IMR, MY_INTRS); 1429 if (ifp->if_snd.ifq_head != NULL) 1430 my_start(ifp); 1431 MY_UNLOCK(sc); 1432 return; 1433 } 1434 1435 /* 1436 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1437 * pointers to the fragment pointers. 1438 */ 1439 static int 1440 my_encap(struct my_softc * sc, struct my_chain * c, struct mbuf * m_head) 1441 { 1442 struct my_desc *f = NULL; 1443 int total_len; 1444 struct mbuf *m, *m_new = NULL; 1445 1446 MY_LOCK(sc); 1447 /* calculate the total tx pkt length */ 1448 total_len = 0; 1449 for (m = m_head; m != NULL; m = m->m_next) 1450 total_len += m->m_len; 1451 /* 1452 * Start packing the mbufs in this chain into the fragment pointers. 1453 * Stop when we run out of fragments or hit the end of the mbuf 1454 * chain. 1455 */ 1456 m = m_head; 1457 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1458 if (m_new == NULL) { 1459 printf("my%d: no memory for tx list", sc->my_unit); 1460 MY_UNLOCK(sc); 1461 return (1); 1462 } 1463 if (m_head->m_pkthdr.len > MHLEN) { 1464 MCLGET(m_new, M_DONTWAIT); 1465 if (!(m_new->m_flags & M_EXT)) { 1466 m_freem(m_new); 1467 printf("my%d: no memory for tx list", sc->my_unit); 1468 MY_UNLOCK(sc); 1469 return (1); 1470 } 1471 } 1472 m_copydata(m_head, 0, m_head->m_pkthdr.len, mtod(m_new, caddr_t)); 1473 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1474 m_freem(m_head); 1475 m_head = m_new; 1476 f = &c->my_ptr->my_frag[0]; 1477 f->my_status = 0; 1478 f->my_data = vtophys(mtod(m_new, caddr_t)); 1479 total_len = m_new->m_len; 1480 f->my_ctl = MY_TXFD | MY_TXLD | MY_CRCEnable | MY_PADEnable; 1481 f->my_ctl |= total_len << MY_PKTShift; /* pkt size */ 1482 f->my_ctl |= total_len; /* buffer size */ 1483 /* 89/12/29 add, for mtd891 *//* [ 89? ] */ 1484 if (sc->my_info->my_did == MTD891ID) 1485 f->my_ctl |= MY_ETIControl | MY_RetryTxLC; 1486 c->my_mbuf = m_head; 1487 c->my_lastdesc = 0; 1488 MY_TXNEXT(c) = vtophys(&c->my_nextdesc->my_ptr->my_frag[0]); 1489 MY_UNLOCK(sc); 1490 return (0); 1491 } 1492 1493 /* 1494 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1495 * to the mbuf data regions directly in the transmit lists. We also save a 1496 * copy of the pointers since the transmit list fragment pointers are 1497 * physical addresses. 1498 */ 1499 static void 1500 my_start(struct ifnet * ifp) 1501 { 1502 struct my_softc *sc; 1503 struct mbuf *m_head = NULL; 1504 struct my_chain *cur_tx = NULL, *start_tx; 1505 1506 sc = ifp->if_softc; 1507 MY_LOCK(sc); 1508 if (sc->my_autoneg) { 1509 sc->my_tx_pend = 1; 1510 MY_UNLOCK(sc); 1511 return; 1512 } 1513 /* 1514 * Check for an available queue slot. If there are none, punt. 1515 */ 1516 if (sc->my_cdata.my_tx_free->my_mbuf != NULL) { 1517 ifp->if_flags |= IFF_OACTIVE; 1518 MY_UNLOCK(sc); 1519 return; 1520 } 1521 start_tx = sc->my_cdata.my_tx_free; 1522 while (sc->my_cdata.my_tx_free->my_mbuf == NULL) { 1523 IF_DEQUEUE(&ifp->if_snd, m_head); 1524 if (m_head == NULL) 1525 break; 1526 1527 /* Pick a descriptor off the free list. */ 1528 cur_tx = sc->my_cdata.my_tx_free; 1529 sc->my_cdata.my_tx_free = cur_tx->my_nextdesc; 1530 1531 /* Pack the data into the descriptor. */ 1532 my_encap(sc, cur_tx, m_head); 1533 1534 if (cur_tx != start_tx) 1535 MY_TXOWN(cur_tx) = MY_OWNByNIC; 1536 #if NBPFILTER > 0 1537 /* 1538 * If there's a BPF listener, bounce a copy of this frame to 1539 * him. 1540 */ 1541 BPF_MTAP(ifp, cur_tx->my_mbuf); 1542 #endif 1543 } 1544 /* 1545 * If there are no packets queued, bail. 1546 */ 1547 if (cur_tx == NULL) { 1548 MY_UNLOCK(sc); 1549 return; 1550 } 1551 /* 1552 * Place the request for the upload interrupt in the last descriptor 1553 * in the chain. This way, if we're chaining several packets at once, 1554 * we'll only get an interupt once for the whole chain rather than 1555 * once for each packet. 1556 */ 1557 MY_TXCTL(cur_tx) |= MY_TXIC; 1558 cur_tx->my_ptr->my_frag[0].my_ctl |= MY_TXIC; 1559 sc->my_cdata.my_tx_tail = cur_tx; 1560 if (sc->my_cdata.my_tx_head == NULL) 1561 sc->my_cdata.my_tx_head = start_tx; 1562 MY_TXOWN(start_tx) = MY_OWNByNIC; 1563 CSR_WRITE_4(sc, MY_TXPDR, 0xFFFFFFFF); /* tx polling demand */ 1564 1565 /* 1566 * Set a timeout in case the chip goes out to lunch. 1567 */ 1568 ifp->if_timer = 5; 1569 MY_UNLOCK(sc); 1570 return; 1571 } 1572 1573 static void 1574 my_init(void *xsc) 1575 { 1576 struct my_softc *sc = xsc; 1577 struct ifnet *ifp = &sc->arpcom.ac_if; 1578 int s; 1579 u_int16_t phy_bmcr = 0; 1580 1581 MY_LOCK(sc); 1582 if (sc->my_autoneg) { 1583 MY_UNLOCK(sc); 1584 return; 1585 } 1586 s = splimp(); 1587 if (sc->my_pinfo != NULL) 1588 phy_bmcr = my_phy_readreg(sc, PHY_BMCR); 1589 /* 1590 * Cancel pending I/O and free all RX/TX buffers. 1591 */ 1592 my_stop(sc); 1593 my_reset(sc); 1594 1595 /* 1596 * Set cache alignment and burst length. 1597 */ 1598 #if 0 /* 89/9/1 modify, */ 1599 CSR_WRITE_4(sc, MY_BCR, MY_RPBLE512); 1600 CSR_WRITE_4(sc, MY_TCRRCR, MY_TFTSF); 1601 #endif 1602 CSR_WRITE_4(sc, MY_BCR, MY_PBL8); 1603 CSR_WRITE_4(sc, MY_TCRRCR, MY_TFTSF | MY_RBLEN | MY_RPBLE512); 1604 /* 1605 * 89/12/29 add, for mtd891, 1606 */ 1607 if (sc->my_info->my_did == MTD891ID) { 1608 MY_SETBIT(sc, MY_BCR, MY_PROG); 1609 MY_SETBIT(sc, MY_TCRRCR, MY_Enhanced); 1610 } 1611 my_setcfg(sc, phy_bmcr); 1612 /* Init circular RX list. */ 1613 if (my_list_rx_init(sc) == ENOBUFS) { 1614 printf("my%d: init failed: no memory for rx buffers\n", 1615 sc->my_unit); 1616 my_stop(sc); 1617 (void)splx(s); 1618 MY_UNLOCK(sc); 1619 return; 1620 } 1621 /* Init TX descriptors. */ 1622 my_list_tx_init(sc); 1623 1624 /* If we want promiscuous mode, set the allframes bit. */ 1625 if (ifp->if_flags & IFF_PROMISC) 1626 MY_SETBIT(sc, MY_TCRRCR, MY_PROM); 1627 else 1628 MY_CLRBIT(sc, MY_TCRRCR, MY_PROM); 1629 1630 /* 1631 * Set capture broadcast bit to capture broadcast frames. 1632 */ 1633 if (ifp->if_flags & IFF_BROADCAST) 1634 MY_SETBIT(sc, MY_TCRRCR, MY_AB); 1635 else 1636 MY_CLRBIT(sc, MY_TCRRCR, MY_AB); 1637 1638 /* 1639 * Program the multicast filter, if necessary. 1640 */ 1641 my_setmulti(sc); 1642 1643 /* 1644 * Load the address of the RX list. 1645 */ 1646 MY_CLRBIT(sc, MY_TCRRCR, MY_RE); 1647 CSR_WRITE_4(sc, MY_RXLBA, vtophys(&sc->my_ldata->my_rx_list[0])); 1648 1649 /* 1650 * Enable interrupts. 1651 */ 1652 CSR_WRITE_4(sc, MY_IMR, MY_INTRS); 1653 CSR_WRITE_4(sc, MY_ISR, 0xFFFFFFFF); 1654 1655 /* Enable receiver and transmitter. */ 1656 MY_SETBIT(sc, MY_TCRRCR, MY_RE); 1657 MY_CLRBIT(sc, MY_TCRRCR, MY_TE); 1658 CSR_WRITE_4(sc, MY_TXLBA, vtophys(&sc->my_ldata->my_tx_list[0])); 1659 MY_SETBIT(sc, MY_TCRRCR, MY_TE); 1660 1661 /* Restore state of BMCR */ 1662 if (sc->my_pinfo != NULL) 1663 my_phy_writereg(sc, PHY_BMCR, phy_bmcr); 1664 ifp->if_flags |= IFF_RUNNING; 1665 ifp->if_flags &= ~IFF_OACTIVE; 1666 (void)splx(s); 1667 MY_UNLOCK(sc); 1668 return; 1669 } 1670 1671 /* 1672 * Set media options. 1673 */ 1674 1675 static int 1676 my_ifmedia_upd(struct ifnet * ifp) 1677 { 1678 struct my_softc *sc; 1679 struct ifmedia *ifm; 1680 1681 sc = ifp->if_softc; 1682 MY_LOCK(sc); 1683 ifm = &sc->ifmedia; 1684 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) { 1685 MY_UNLOCK(sc); 1686 return (EINVAL); 1687 } 1688 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO) 1689 my_autoneg_mii(sc, MY_FLAG_SCHEDDELAY, 1); 1690 else 1691 my_setmode_mii(sc, ifm->ifm_media); 1692 MY_UNLOCK(sc); 1693 return (0); 1694 } 1695 1696 /* 1697 * Report current media status. 1698 */ 1699 1700 static void 1701 my_ifmedia_sts(struct ifnet * ifp, struct ifmediareq * ifmr) 1702 { 1703 struct my_softc *sc; 1704 u_int16_t advert = 0, ability = 0; 1705 1706 sc = ifp->if_softc; 1707 MY_LOCK(sc); 1708 ifmr->ifm_active = IFM_ETHER; 1709 if (!(my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_AUTONEGENBL)) { 1710 #if 0 /* this version did not support 1000M, */ 1711 if (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_1000) 1712 ifmr->ifm_active = IFM_ETHER | IFM_1000TX; 1713 #endif 1714 if (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_SPEEDSEL) 1715 ifmr->ifm_active = IFM_ETHER | IFM_100_TX; 1716 else 1717 ifmr->ifm_active = IFM_ETHER | IFM_10_T; 1718 if (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_DUPLEX) 1719 ifmr->ifm_active |= IFM_FDX; 1720 else 1721 ifmr->ifm_active |= IFM_HDX; 1722 1723 MY_UNLOCK(sc); 1724 return; 1725 } 1726 ability = my_phy_readreg(sc, PHY_LPAR); 1727 advert = my_phy_readreg(sc, PHY_ANAR); 1728 1729 #if 0 /* this version did not support 1000M, */ 1730 if (sc->my_pinfo->my_vid = MarvellPHYID0) { 1731 ability2 = my_phy_readreg(sc, PHY_1000SR); 1732 if (ability2 & PHY_1000SR_1000BTXFULL) { 1733 advert = 0; 1734 ability = 0; 1735 ifmr->ifm_active = IFM_ETHER|IFM_1000_T|IFM_FDX; 1736 } else if (ability & PHY_1000SR_1000BTXHALF) { 1737 advert = 0; 1738 ability = 0; 1739 ifmr->ifm_active = IFM_ETHER|IFM_1000_T|IFM_HDX; 1740 } 1741 } 1742 #endif 1743 if (advert & PHY_ANAR_100BT4 && ability & PHY_ANAR_100BT4) 1744 ifmr->ifm_active = IFM_ETHER | IFM_100_T4; 1745 else if (advert & PHY_ANAR_100BTXFULL && ability & PHY_ANAR_100BTXFULL) 1746 ifmr->ifm_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 1747 else if (advert & PHY_ANAR_100BTXHALF && ability & PHY_ANAR_100BTXHALF) 1748 ifmr->ifm_active = IFM_ETHER | IFM_100_TX | IFM_HDX; 1749 else if (advert & PHY_ANAR_10BTFULL && ability & PHY_ANAR_10BTFULL) 1750 ifmr->ifm_active = IFM_ETHER | IFM_10_T | IFM_FDX; 1751 else if (advert & PHY_ANAR_10BTHALF && ability & PHY_ANAR_10BTHALF) 1752 ifmr->ifm_active = IFM_ETHER | IFM_10_T | IFM_HDX; 1753 MY_UNLOCK(sc); 1754 return; 1755 } 1756 1757 static int 1758 my_ioctl(struct ifnet * ifp, u_long command, caddr_t data) 1759 { 1760 struct my_softc *sc = ifp->if_softc; 1761 struct ifreq *ifr = (struct ifreq *) data; 1762 int s, error = 0; 1763 1764 s = splimp(); 1765 MY_LOCK(sc); 1766 switch (command) { 1767 case SIOCSIFFLAGS: 1768 if (ifp->if_flags & IFF_UP) 1769 my_init(sc); 1770 else if (ifp->if_flags & IFF_RUNNING) 1771 my_stop(sc); 1772 error = 0; 1773 break; 1774 case SIOCADDMULTI: 1775 case SIOCDELMULTI: 1776 my_setmulti(sc); 1777 error = 0; 1778 break; 1779 case SIOCGIFMEDIA: 1780 case SIOCSIFMEDIA: 1781 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); 1782 break; 1783 default: 1784 error = ether_ioctl(ifp, command, data); 1785 break; 1786 } 1787 MY_UNLOCK(sc); 1788 (void)splx(s); 1789 return (error); 1790 } 1791 1792 static void 1793 my_watchdog(struct ifnet * ifp) 1794 { 1795 struct my_softc *sc; 1796 1797 sc = ifp->if_softc; 1798 MY_LOCK(sc); 1799 if (sc->my_autoneg) { 1800 my_autoneg_mii(sc, MY_FLAG_DELAYTIMEO, 1); 1801 MY_UNLOCK(sc); 1802 return; 1803 } 1804 ifp->if_oerrors++; 1805 printf("my%d: watchdog timeout\n", sc->my_unit); 1806 if (!(my_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT)) 1807 printf("my%d: no carrier - transceiver cable problem?\n", 1808 sc->my_unit); 1809 my_stop(sc); 1810 my_reset(sc); 1811 my_init(sc); 1812 if (ifp->if_snd.ifq_head != NULL) 1813 my_start(ifp); 1814 MY_LOCK(sc); 1815 return; 1816 } 1817 1818 1819 /* 1820 * Stop the adapter and free any mbufs allocated to the RX and TX lists. 1821 */ 1822 static void 1823 my_stop(struct my_softc * sc) 1824 { 1825 register int i; 1826 struct ifnet *ifp; 1827 1828 MY_LOCK(sc); 1829 ifp = &sc->arpcom.ac_if; 1830 ifp->if_timer = 0; 1831 1832 MY_CLRBIT(sc, MY_TCRRCR, (MY_RE | MY_TE)); 1833 CSR_WRITE_4(sc, MY_IMR, 0x00000000); 1834 CSR_WRITE_4(sc, MY_TXLBA, 0x00000000); 1835 CSR_WRITE_4(sc, MY_RXLBA, 0x00000000); 1836 1837 /* 1838 * Free data in the RX lists. 1839 */ 1840 for (i = 0; i < MY_RX_LIST_CNT; i++) { 1841 if (sc->my_cdata.my_rx_chain[i].my_mbuf != NULL) { 1842 m_freem(sc->my_cdata.my_rx_chain[i].my_mbuf); 1843 sc->my_cdata.my_rx_chain[i].my_mbuf = NULL; 1844 } 1845 } 1846 bzero((char *)&sc->my_ldata->my_rx_list, 1847 sizeof(sc->my_ldata->my_rx_list)); 1848 /* 1849 * Free the TX list buffers. 1850 */ 1851 for (i = 0; i < MY_TX_LIST_CNT; i++) { 1852 if (sc->my_cdata.my_tx_chain[i].my_mbuf != NULL) { 1853 m_freem(sc->my_cdata.my_tx_chain[i].my_mbuf); 1854 sc->my_cdata.my_tx_chain[i].my_mbuf = NULL; 1855 } 1856 } 1857 bzero((char *)&sc->my_ldata->my_tx_list, 1858 sizeof(sc->my_ldata->my_tx_list)); 1859 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1860 MY_UNLOCK(sc); 1861 return; 1862 } 1863 1864 /* 1865 * Stop all chip I/O so that the kernel's probe routines don't get confused 1866 * by errant DMAs when rebooting. 1867 */ 1868 static void 1869 my_shutdown(device_t dev) 1870 { 1871 struct my_softc *sc; 1872 1873 sc = device_get_softc(dev); 1874 my_stop(sc); 1875 return; 1876 } 1877