1 /*- 2 * Written by: yen_cw@myson.com.tw 3 * Copyright (c) 2002 Myson Technology Inc. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions, and the following disclaimer, 11 * without modification, immediately at the beginning of the file. 12 * 2. The name of the author may not be used to endorse or promote products 13 * derived from this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 19 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * Myson fast ethernet PCI NIC driver, available at: http://www.myson.com.tw/ 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/sockio.h> 36 #include <sys/mbuf.h> 37 #include <sys/malloc.h> 38 #include <sys/kernel.h> 39 #include <sys/socket.h> 40 #include <sys/queue.h> 41 #include <sys/types.h> 42 #include <sys/module.h> 43 #include <sys/lock.h> 44 #include <sys/mutex.h> 45 46 #define NBPFILTER 1 47 48 #include <net/if.h> 49 #include <net/if_var.h> 50 #include <net/if_arp.h> 51 #include <net/ethernet.h> 52 #include <net/if_media.h> 53 #include <net/if_types.h> 54 #include <net/if_dl.h> 55 #include <net/bpf.h> 56 57 #include <vm/vm.h> /* for vtophys */ 58 #include <vm/pmap.h> /* for vtophys */ 59 #include <machine/bus.h> 60 #include <machine/resource.h> 61 #include <sys/bus.h> 62 #include <sys/rman.h> 63 64 #include <dev/pci/pcireg.h> 65 #include <dev/pci/pcivar.h> 66 67 /* 68 * #define MY_USEIOSPACE 69 */ 70 71 static int MY_USEIOSPACE = 1; 72 73 #ifdef MY_USEIOSPACE 74 #define MY_RES SYS_RES_IOPORT 75 #define MY_RID MY_PCI_LOIO 76 #else 77 #define MY_RES SYS_RES_MEMORY 78 #define MY_RID MY_PCI_LOMEM 79 #endif 80 81 82 #include <dev/my/if_myreg.h> 83 84 /* 85 * Various supported device vendors/types and their names. 86 */ 87 struct my_type *my_info_tmp; 88 static struct my_type my_devs[] = { 89 {MYSONVENDORID, MTD800ID, "Myson MTD80X Based Fast Ethernet Card"}, 90 {MYSONVENDORID, MTD803ID, "Myson MTD80X Based Fast Ethernet Card"}, 91 {MYSONVENDORID, MTD891ID, "Myson MTD89X Based Giga Ethernet Card"}, 92 {0, 0, NULL} 93 }; 94 95 /* 96 * Various supported PHY vendors/types and their names. Note that this driver 97 * will work with pretty much any MII-compliant PHY, so failure to positively 98 * identify the chip is not a fatal error. 99 */ 100 static struct my_type my_phys[] = { 101 {MysonPHYID0, MysonPHYID0, "<MYSON MTD981>"}, 102 {SeeqPHYID0, SeeqPHYID0, "<SEEQ 80225>"}, 103 {AhdocPHYID0, AhdocPHYID0, "<AHDOC 101>"}, 104 {MarvellPHYID0, MarvellPHYID0, "<MARVELL 88E1000>"}, 105 {LevelOnePHYID0, LevelOnePHYID0, "<LevelOne LXT1000>"}, 106 {0, 0, "<MII-compliant physical interface>"} 107 }; 108 109 static int my_probe(device_t); 110 static int my_attach(device_t); 111 static int my_detach(device_t); 112 static int my_newbuf(struct my_softc *, struct my_chain_onefrag *); 113 static int my_encap(struct my_softc *, struct my_chain *, struct mbuf *); 114 static void my_rxeof(struct my_softc *); 115 static void my_txeof(struct my_softc *); 116 static void my_txeoc(struct my_softc *); 117 static void my_intr(void *); 118 static void my_start(struct ifnet *); 119 static void my_start_locked(struct ifnet *); 120 static int my_ioctl(struct ifnet *, u_long, caddr_t); 121 static void my_init(void *); 122 static void my_init_locked(struct my_softc *); 123 static void my_stop(struct my_softc *); 124 static void my_autoneg_timeout(void *); 125 static void my_watchdog(void *); 126 static int my_shutdown(device_t); 127 static int my_ifmedia_upd(struct ifnet *); 128 static void my_ifmedia_sts(struct ifnet *, struct ifmediareq *); 129 static u_int16_t my_phy_readreg(struct my_softc *, int); 130 static void my_phy_writereg(struct my_softc *, int, int); 131 static void my_autoneg_xmit(struct my_softc *); 132 static void my_autoneg_mii(struct my_softc *, int, int); 133 static void my_setmode_mii(struct my_softc *, int); 134 static void my_getmode_mii(struct my_softc *); 135 static void my_setcfg(struct my_softc *, int); 136 static void my_setmulti(struct my_softc *); 137 static void my_reset(struct my_softc *); 138 static int my_list_rx_init(struct my_softc *); 139 static int my_list_tx_init(struct my_softc *); 140 static long my_send_cmd_to_phy(struct my_softc *, int, int); 141 142 #define MY_SETBIT(sc, reg, x) CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 143 #define MY_CLRBIT(sc, reg, x) CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 144 145 static device_method_t my_methods[] = { 146 /* Device interface */ 147 DEVMETHOD(device_probe, my_probe), 148 DEVMETHOD(device_attach, my_attach), 149 DEVMETHOD(device_detach, my_detach), 150 DEVMETHOD(device_shutdown, my_shutdown), 151 152 DEVMETHOD_END 153 }; 154 155 static driver_t my_driver = { 156 "my", 157 my_methods, 158 sizeof(struct my_softc) 159 }; 160 161 static devclass_t my_devclass; 162 163 DRIVER_MODULE(my, pci, my_driver, my_devclass, 0, 0); 164 MODULE_DEPEND(my, pci, 1, 1, 1); 165 MODULE_DEPEND(my, ether, 1, 1, 1); 166 167 static long 168 my_send_cmd_to_phy(struct my_softc * sc, int opcode, int regad) 169 { 170 long miir; 171 int i; 172 int mask, data; 173 174 MY_LOCK_ASSERT(sc); 175 176 /* enable MII output */ 177 miir = CSR_READ_4(sc, MY_MANAGEMENT); 178 miir &= 0xfffffff0; 179 180 miir |= MY_MASK_MIIR_MII_WRITE + MY_MASK_MIIR_MII_MDO; 181 182 /* send 32 1's preamble */ 183 for (i = 0; i < 32; i++) { 184 /* low MDC; MDO is already high (miir) */ 185 miir &= ~MY_MASK_MIIR_MII_MDC; 186 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 187 188 /* high MDC */ 189 miir |= MY_MASK_MIIR_MII_MDC; 190 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 191 } 192 193 /* calculate ST+OP+PHYAD+REGAD+TA */ 194 data = opcode | (sc->my_phy_addr << 7) | (regad << 2); 195 196 /* sent out */ 197 mask = 0x8000; 198 while (mask) { 199 /* low MDC, prepare MDO */ 200 miir &= ~(MY_MASK_MIIR_MII_MDC + MY_MASK_MIIR_MII_MDO); 201 if (mask & data) 202 miir |= MY_MASK_MIIR_MII_MDO; 203 204 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 205 /* high MDC */ 206 miir |= MY_MASK_MIIR_MII_MDC; 207 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 208 DELAY(30); 209 210 /* next */ 211 mask >>= 1; 212 if (mask == 0x2 && opcode == MY_OP_READ) 213 miir &= ~MY_MASK_MIIR_MII_WRITE; 214 } 215 216 return miir; 217 } 218 219 220 static u_int16_t 221 my_phy_readreg(struct my_softc * sc, int reg) 222 { 223 long miir; 224 int mask, data; 225 226 MY_LOCK_ASSERT(sc); 227 228 if (sc->my_info->my_did == MTD803ID) 229 data = CSR_READ_2(sc, MY_PHYBASE + reg * 2); 230 else { 231 miir = my_send_cmd_to_phy(sc, MY_OP_READ, reg); 232 233 /* read data */ 234 mask = 0x8000; 235 data = 0; 236 while (mask) { 237 /* low MDC */ 238 miir &= ~MY_MASK_MIIR_MII_MDC; 239 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 240 241 /* read MDI */ 242 miir = CSR_READ_4(sc, MY_MANAGEMENT); 243 if (miir & MY_MASK_MIIR_MII_MDI) 244 data |= mask; 245 246 /* high MDC, and wait */ 247 miir |= MY_MASK_MIIR_MII_MDC; 248 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 249 DELAY(30); 250 251 /* next */ 252 mask >>= 1; 253 } 254 255 /* low MDC */ 256 miir &= ~MY_MASK_MIIR_MII_MDC; 257 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 258 } 259 260 return (u_int16_t) data; 261 } 262 263 264 static void 265 my_phy_writereg(struct my_softc * sc, int reg, int data) 266 { 267 long miir; 268 int mask; 269 270 MY_LOCK_ASSERT(sc); 271 272 if (sc->my_info->my_did == MTD803ID) 273 CSR_WRITE_2(sc, MY_PHYBASE + reg * 2, data); 274 else { 275 miir = my_send_cmd_to_phy(sc, MY_OP_WRITE, reg); 276 277 /* write data */ 278 mask = 0x8000; 279 while (mask) { 280 /* low MDC, prepare MDO */ 281 miir &= ~(MY_MASK_MIIR_MII_MDC + MY_MASK_MIIR_MII_MDO); 282 if (mask & data) 283 miir |= MY_MASK_MIIR_MII_MDO; 284 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 285 DELAY(1); 286 287 /* high MDC */ 288 miir |= MY_MASK_MIIR_MII_MDC; 289 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 290 DELAY(1); 291 292 /* next */ 293 mask >>= 1; 294 } 295 296 /* low MDC */ 297 miir &= ~MY_MASK_MIIR_MII_MDC; 298 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 299 } 300 return; 301 } 302 303 304 /* 305 * Program the 64-bit multicast hash filter. 306 */ 307 static void 308 my_setmulti(struct my_softc * sc) 309 { 310 struct ifnet *ifp; 311 int h = 0; 312 u_int32_t hashes[2] = {0, 0}; 313 struct ifmultiaddr *ifma; 314 u_int32_t rxfilt; 315 int mcnt = 0; 316 317 MY_LOCK_ASSERT(sc); 318 319 ifp = sc->my_ifp; 320 321 rxfilt = CSR_READ_4(sc, MY_TCRRCR); 322 323 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 324 rxfilt |= MY_AM; 325 CSR_WRITE_4(sc, MY_TCRRCR, rxfilt); 326 CSR_WRITE_4(sc, MY_MAR0, 0xFFFFFFFF); 327 CSR_WRITE_4(sc, MY_MAR1, 0xFFFFFFFF); 328 329 return; 330 } 331 /* first, zot all the existing hash bits */ 332 CSR_WRITE_4(sc, MY_MAR0, 0); 333 CSR_WRITE_4(sc, MY_MAR1, 0); 334 335 /* now program new ones */ 336 if_maddr_rlock(ifp); 337 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 338 if (ifma->ifma_addr->sa_family != AF_LINK) 339 continue; 340 h = ~ether_crc32_be(LLADDR((struct sockaddr_dl *) 341 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 342 if (h < 32) 343 hashes[0] |= (1 << h); 344 else 345 hashes[1] |= (1 << (h - 32)); 346 mcnt++; 347 } 348 if_maddr_runlock(ifp); 349 350 if (mcnt) 351 rxfilt |= MY_AM; 352 else 353 rxfilt &= ~MY_AM; 354 CSR_WRITE_4(sc, MY_MAR0, hashes[0]); 355 CSR_WRITE_4(sc, MY_MAR1, hashes[1]); 356 CSR_WRITE_4(sc, MY_TCRRCR, rxfilt); 357 return; 358 } 359 360 /* 361 * Initiate an autonegotiation session. 362 */ 363 static void 364 my_autoneg_xmit(struct my_softc * sc) 365 { 366 u_int16_t phy_sts = 0; 367 368 MY_LOCK_ASSERT(sc); 369 370 my_phy_writereg(sc, PHY_BMCR, PHY_BMCR_RESET); 371 DELAY(500); 372 while (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_RESET); 373 374 phy_sts = my_phy_readreg(sc, PHY_BMCR); 375 phy_sts |= PHY_BMCR_AUTONEGENBL | PHY_BMCR_AUTONEGRSTR; 376 my_phy_writereg(sc, PHY_BMCR, phy_sts); 377 378 return; 379 } 380 381 static void 382 my_autoneg_timeout(void *arg) 383 { 384 struct my_softc *sc; 385 386 sc = arg; 387 MY_LOCK_ASSERT(sc); 388 my_autoneg_mii(sc, MY_FLAG_DELAYTIMEO, 1); 389 } 390 391 /* 392 * Invoke autonegotiation on a PHY. 393 */ 394 static void 395 my_autoneg_mii(struct my_softc * sc, int flag, int verbose) 396 { 397 u_int16_t phy_sts = 0, media, advert, ability; 398 u_int16_t ability2 = 0; 399 struct ifnet *ifp; 400 struct ifmedia *ifm; 401 402 MY_LOCK_ASSERT(sc); 403 404 ifm = &sc->ifmedia; 405 ifp = sc->my_ifp; 406 407 ifm->ifm_media = IFM_ETHER | IFM_AUTO; 408 409 #ifndef FORCE_AUTONEG_TFOUR 410 /* 411 * First, see if autoneg is supported. If not, there's no point in 412 * continuing. 413 */ 414 phy_sts = my_phy_readreg(sc, PHY_BMSR); 415 if (!(phy_sts & PHY_BMSR_CANAUTONEG)) { 416 if (verbose) 417 device_printf(sc->my_dev, 418 "autonegotiation not supported\n"); 419 ifm->ifm_media = IFM_ETHER | IFM_10_T | IFM_HDX; 420 return; 421 } 422 #endif 423 switch (flag) { 424 case MY_FLAG_FORCEDELAY: 425 /* 426 * XXX Never use this option anywhere but in the probe 427 * routine: making the kernel stop dead in its tracks for 428 * three whole seconds after we've gone multi-user is really 429 * bad manners. 430 */ 431 my_autoneg_xmit(sc); 432 DELAY(5000000); 433 break; 434 case MY_FLAG_SCHEDDELAY: 435 /* 436 * Wait for the transmitter to go idle before starting an 437 * autoneg session, otherwise my_start() may clobber our 438 * timeout, and we don't want to allow transmission during an 439 * autoneg session since that can screw it up. 440 */ 441 if (sc->my_cdata.my_tx_head != NULL) { 442 sc->my_want_auto = 1; 443 MY_UNLOCK(sc); 444 return; 445 } 446 my_autoneg_xmit(sc); 447 callout_reset(&sc->my_autoneg_timer, hz * 5, my_autoneg_timeout, 448 sc); 449 sc->my_autoneg = 1; 450 sc->my_want_auto = 0; 451 return; 452 case MY_FLAG_DELAYTIMEO: 453 callout_stop(&sc->my_autoneg_timer); 454 sc->my_autoneg = 0; 455 break; 456 default: 457 device_printf(sc->my_dev, "invalid autoneg flag: %d\n", flag); 458 return; 459 } 460 461 if (my_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_AUTONEGCOMP) { 462 if (verbose) 463 device_printf(sc->my_dev, "autoneg complete, "); 464 phy_sts = my_phy_readreg(sc, PHY_BMSR); 465 } else { 466 if (verbose) 467 device_printf(sc->my_dev, "autoneg not complete, "); 468 } 469 470 media = my_phy_readreg(sc, PHY_BMCR); 471 472 /* Link is good. Report modes and set duplex mode. */ 473 if (my_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT) { 474 if (verbose) 475 device_printf(sc->my_dev, "link status good. "); 476 advert = my_phy_readreg(sc, PHY_ANAR); 477 ability = my_phy_readreg(sc, PHY_LPAR); 478 if ((sc->my_pinfo->my_vid == MarvellPHYID0) || 479 (sc->my_pinfo->my_vid == LevelOnePHYID0)) { 480 ability2 = my_phy_readreg(sc, PHY_1000SR); 481 if (ability2 & PHY_1000SR_1000BTXFULL) { 482 advert = 0; 483 ability = 0; 484 /* 485 * this version did not support 1000M, 486 * ifm->ifm_media = 487 * IFM_ETHER|IFM_1000_T|IFM_FDX; 488 */ 489 ifm->ifm_media = 490 IFM_ETHER | IFM_100_TX | IFM_FDX; 491 media &= ~PHY_BMCR_SPEEDSEL; 492 media |= PHY_BMCR_1000; 493 media |= PHY_BMCR_DUPLEX; 494 printf("(full-duplex, 1000Mbps)\n"); 495 } else if (ability2 & PHY_1000SR_1000BTXHALF) { 496 advert = 0; 497 ability = 0; 498 /* 499 * this version did not support 1000M, 500 * ifm->ifm_media = IFM_ETHER|IFM_1000_T; 501 */ 502 ifm->ifm_media = IFM_ETHER | IFM_100_TX; 503 media &= ~PHY_BMCR_SPEEDSEL; 504 media &= ~PHY_BMCR_DUPLEX; 505 media |= PHY_BMCR_1000; 506 printf("(half-duplex, 1000Mbps)\n"); 507 } 508 } 509 if (advert & PHY_ANAR_100BT4 && ability & PHY_ANAR_100BT4) { 510 ifm->ifm_media = IFM_ETHER | IFM_100_T4; 511 media |= PHY_BMCR_SPEEDSEL; 512 media &= ~PHY_BMCR_DUPLEX; 513 printf("(100baseT4)\n"); 514 } else if (advert & PHY_ANAR_100BTXFULL && 515 ability & PHY_ANAR_100BTXFULL) { 516 ifm->ifm_media = IFM_ETHER | IFM_100_TX | IFM_FDX; 517 media |= PHY_BMCR_SPEEDSEL; 518 media |= PHY_BMCR_DUPLEX; 519 printf("(full-duplex, 100Mbps)\n"); 520 } else if (advert & PHY_ANAR_100BTXHALF && 521 ability & PHY_ANAR_100BTXHALF) { 522 ifm->ifm_media = IFM_ETHER | IFM_100_TX | IFM_HDX; 523 media |= PHY_BMCR_SPEEDSEL; 524 media &= ~PHY_BMCR_DUPLEX; 525 printf("(half-duplex, 100Mbps)\n"); 526 } else if (advert & PHY_ANAR_10BTFULL && 527 ability & PHY_ANAR_10BTFULL) { 528 ifm->ifm_media = IFM_ETHER | IFM_10_T | IFM_FDX; 529 media &= ~PHY_BMCR_SPEEDSEL; 530 media |= PHY_BMCR_DUPLEX; 531 printf("(full-duplex, 10Mbps)\n"); 532 } else if (advert) { 533 ifm->ifm_media = IFM_ETHER | IFM_10_T | IFM_HDX; 534 media &= ~PHY_BMCR_SPEEDSEL; 535 media &= ~PHY_BMCR_DUPLEX; 536 printf("(half-duplex, 10Mbps)\n"); 537 } 538 media &= ~PHY_BMCR_AUTONEGENBL; 539 540 /* Set ASIC's duplex mode to match the PHY. */ 541 my_phy_writereg(sc, PHY_BMCR, media); 542 my_setcfg(sc, media); 543 } else { 544 if (verbose) 545 device_printf(sc->my_dev, "no carrier\n"); 546 } 547 548 my_init_locked(sc); 549 if (sc->my_tx_pend) { 550 sc->my_autoneg = 0; 551 sc->my_tx_pend = 0; 552 my_start_locked(ifp); 553 } 554 return; 555 } 556 557 /* 558 * To get PHY ability. 559 */ 560 static void 561 my_getmode_mii(struct my_softc * sc) 562 { 563 u_int16_t bmsr; 564 struct ifnet *ifp; 565 566 MY_LOCK_ASSERT(sc); 567 ifp = sc->my_ifp; 568 bmsr = my_phy_readreg(sc, PHY_BMSR); 569 if (bootverbose) 570 device_printf(sc->my_dev, "PHY status word: %x\n", bmsr); 571 572 /* fallback */ 573 sc->ifmedia.ifm_media = IFM_ETHER | IFM_10_T | IFM_HDX; 574 575 if (bmsr & PHY_BMSR_10BTHALF) { 576 if (bootverbose) 577 device_printf(sc->my_dev, 578 "10Mbps half-duplex mode supported\n"); 579 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_10_T | IFM_HDX, 580 0, NULL); 581 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_10_T, 0, NULL); 582 } 583 if (bmsr & PHY_BMSR_10BTFULL) { 584 if (bootverbose) 585 device_printf(sc->my_dev, 586 "10Mbps full-duplex mode supported\n"); 587 588 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_10_T | IFM_FDX, 589 0, NULL); 590 sc->ifmedia.ifm_media = IFM_ETHER | IFM_10_T | IFM_FDX; 591 } 592 if (bmsr & PHY_BMSR_100BTXHALF) { 593 if (bootverbose) 594 device_printf(sc->my_dev, 595 "100Mbps half-duplex mode supported\n"); 596 ifp->if_baudrate = 100000000; 597 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_TX, 0, NULL); 598 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_TX | IFM_HDX, 599 0, NULL); 600 sc->ifmedia.ifm_media = IFM_ETHER | IFM_100_TX | IFM_HDX; 601 } 602 if (bmsr & PHY_BMSR_100BTXFULL) { 603 if (bootverbose) 604 device_printf(sc->my_dev, 605 "100Mbps full-duplex mode supported\n"); 606 ifp->if_baudrate = 100000000; 607 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_TX | IFM_FDX, 608 0, NULL); 609 sc->ifmedia.ifm_media = IFM_ETHER | IFM_100_TX | IFM_FDX; 610 } 611 /* Some also support 100BaseT4. */ 612 if (bmsr & PHY_BMSR_100BT4) { 613 if (bootverbose) 614 device_printf(sc->my_dev, "100baseT4 mode supported\n"); 615 ifp->if_baudrate = 100000000; 616 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_T4, 0, NULL); 617 sc->ifmedia.ifm_media = IFM_ETHER | IFM_100_T4; 618 #ifdef FORCE_AUTONEG_TFOUR 619 if (bootverbose) 620 device_printf(sc->my_dev, 621 "forcing on autoneg support for BT4\n"); 622 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_AUTO, 0 NULL): 623 sc->ifmedia.ifm_media = IFM_ETHER | IFM_AUTO; 624 #endif 625 } 626 #if 0 /* this version did not support 1000M, */ 627 if (sc->my_pinfo->my_vid == MarvellPHYID0) { 628 if (bootverbose) 629 device_printf(sc->my_dev, 630 "1000Mbps half-duplex mode supported\n"); 631 632 ifp->if_baudrate = 1000000000; 633 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_T, 0, NULL); 634 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_T | IFM_HDX, 635 0, NULL); 636 if (bootverbose) 637 device_printf(sc->my_dev, 638 "1000Mbps full-duplex mode supported\n"); 639 ifp->if_baudrate = 1000000000; 640 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_T | IFM_FDX, 641 0, NULL); 642 sc->ifmedia.ifm_media = IFM_ETHER | IFM_1000_T | IFM_FDX; 643 } 644 #endif 645 if (bmsr & PHY_BMSR_CANAUTONEG) { 646 if (bootverbose) 647 device_printf(sc->my_dev, "autoneg supported\n"); 648 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 649 sc->ifmedia.ifm_media = IFM_ETHER | IFM_AUTO; 650 } 651 return; 652 } 653 654 /* 655 * Set speed and duplex mode. 656 */ 657 static void 658 my_setmode_mii(struct my_softc * sc, int media) 659 { 660 u_int16_t bmcr; 661 struct ifnet *ifp; 662 663 MY_LOCK_ASSERT(sc); 664 ifp = sc->my_ifp; 665 /* 666 * If an autoneg session is in progress, stop it. 667 */ 668 if (sc->my_autoneg) { 669 device_printf(sc->my_dev, "canceling autoneg session\n"); 670 callout_stop(&sc->my_autoneg_timer); 671 sc->my_autoneg = sc->my_want_auto = 0; 672 bmcr = my_phy_readreg(sc, PHY_BMCR); 673 bmcr &= ~PHY_BMCR_AUTONEGENBL; 674 my_phy_writereg(sc, PHY_BMCR, bmcr); 675 } 676 device_printf(sc->my_dev, "selecting MII, "); 677 bmcr = my_phy_readreg(sc, PHY_BMCR); 678 bmcr &= ~(PHY_BMCR_AUTONEGENBL | PHY_BMCR_SPEEDSEL | PHY_BMCR_1000 | 679 PHY_BMCR_DUPLEX | PHY_BMCR_LOOPBK); 680 681 #if 0 /* this version did not support 1000M, */ 682 if (IFM_SUBTYPE(media) == IFM_1000_T) { 683 printf("1000Mbps/T4, half-duplex\n"); 684 bmcr &= ~PHY_BMCR_SPEEDSEL; 685 bmcr &= ~PHY_BMCR_DUPLEX; 686 bmcr |= PHY_BMCR_1000; 687 } 688 #endif 689 if (IFM_SUBTYPE(media) == IFM_100_T4) { 690 printf("100Mbps/T4, half-duplex\n"); 691 bmcr |= PHY_BMCR_SPEEDSEL; 692 bmcr &= ~PHY_BMCR_DUPLEX; 693 } 694 if (IFM_SUBTYPE(media) == IFM_100_TX) { 695 printf("100Mbps, "); 696 bmcr |= PHY_BMCR_SPEEDSEL; 697 } 698 if (IFM_SUBTYPE(media) == IFM_10_T) { 699 printf("10Mbps, "); 700 bmcr &= ~PHY_BMCR_SPEEDSEL; 701 } 702 if ((media & IFM_GMASK) == IFM_FDX) { 703 printf("full duplex\n"); 704 bmcr |= PHY_BMCR_DUPLEX; 705 } else { 706 printf("half duplex\n"); 707 bmcr &= ~PHY_BMCR_DUPLEX; 708 } 709 my_phy_writereg(sc, PHY_BMCR, bmcr); 710 my_setcfg(sc, bmcr); 711 return; 712 } 713 714 /* 715 * The Myson manual states that in order to fiddle with the 'full-duplex' and 716 * '100Mbps' bits in the netconfig register, we first have to put the 717 * transmit and/or receive logic in the idle state. 718 */ 719 static void 720 my_setcfg(struct my_softc * sc, int bmcr) 721 { 722 int i, restart = 0; 723 724 MY_LOCK_ASSERT(sc); 725 if (CSR_READ_4(sc, MY_TCRRCR) & (MY_TE | MY_RE)) { 726 restart = 1; 727 MY_CLRBIT(sc, MY_TCRRCR, (MY_TE | MY_RE)); 728 for (i = 0; i < MY_TIMEOUT; i++) { 729 DELAY(10); 730 if (!(CSR_READ_4(sc, MY_TCRRCR) & 731 (MY_TXRUN | MY_RXRUN))) 732 break; 733 } 734 if (i == MY_TIMEOUT) 735 device_printf(sc->my_dev, 736 "failed to force tx and rx to idle \n"); 737 } 738 MY_CLRBIT(sc, MY_TCRRCR, MY_PS1000); 739 MY_CLRBIT(sc, MY_TCRRCR, MY_PS10); 740 if (bmcr & PHY_BMCR_1000) 741 MY_SETBIT(sc, MY_TCRRCR, MY_PS1000); 742 else if (!(bmcr & PHY_BMCR_SPEEDSEL)) 743 MY_SETBIT(sc, MY_TCRRCR, MY_PS10); 744 if (bmcr & PHY_BMCR_DUPLEX) 745 MY_SETBIT(sc, MY_TCRRCR, MY_FD); 746 else 747 MY_CLRBIT(sc, MY_TCRRCR, MY_FD); 748 if (restart) 749 MY_SETBIT(sc, MY_TCRRCR, MY_TE | MY_RE); 750 return; 751 } 752 753 static void 754 my_reset(struct my_softc * sc) 755 { 756 register int i; 757 758 MY_LOCK_ASSERT(sc); 759 MY_SETBIT(sc, MY_BCR, MY_SWR); 760 for (i = 0; i < MY_TIMEOUT; i++) { 761 DELAY(10); 762 if (!(CSR_READ_4(sc, MY_BCR) & MY_SWR)) 763 break; 764 } 765 if (i == MY_TIMEOUT) 766 device_printf(sc->my_dev, "reset never completed!\n"); 767 768 /* Wait a little while for the chip to get its brains in order. */ 769 DELAY(1000); 770 return; 771 } 772 773 /* 774 * Probe for a Myson chip. Check the PCI vendor and device IDs against our 775 * list and return a device name if we find a match. 776 */ 777 static int 778 my_probe(device_t dev) 779 { 780 struct my_type *t; 781 782 t = my_devs; 783 while (t->my_name != NULL) { 784 if ((pci_get_vendor(dev) == t->my_vid) && 785 (pci_get_device(dev) == t->my_did)) { 786 device_set_desc(dev, t->my_name); 787 my_info_tmp = t; 788 return (BUS_PROBE_DEFAULT); 789 } 790 t++; 791 } 792 return (ENXIO); 793 } 794 795 /* 796 * Attach the interface. Allocate softc structures, do ifmedia setup and 797 * ethernet/BPF attach. 798 */ 799 static int 800 my_attach(device_t dev) 801 { 802 int i; 803 u_char eaddr[ETHER_ADDR_LEN]; 804 u_int32_t iobase; 805 struct my_softc *sc; 806 struct ifnet *ifp; 807 int media = IFM_ETHER | IFM_100_TX | IFM_FDX; 808 unsigned int round; 809 caddr_t roundptr; 810 struct my_type *p; 811 u_int16_t phy_vid, phy_did, phy_sts = 0; 812 int rid, error = 0; 813 814 sc = device_get_softc(dev); 815 sc->my_dev = dev; 816 mtx_init(&sc->my_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 817 MTX_DEF); 818 callout_init_mtx(&sc->my_autoneg_timer, &sc->my_mtx, 0); 819 callout_init_mtx(&sc->my_watchdog, &sc->my_mtx, 0); 820 821 /* 822 * Map control/status registers. 823 */ 824 pci_enable_busmaster(dev); 825 826 if (my_info_tmp->my_did == MTD800ID) { 827 iobase = pci_read_config(dev, MY_PCI_LOIO, 4); 828 if (iobase & 0x300) 829 MY_USEIOSPACE = 0; 830 } 831 832 rid = MY_RID; 833 sc->my_res = bus_alloc_resource_any(dev, MY_RES, &rid, RF_ACTIVE); 834 835 if (sc->my_res == NULL) { 836 device_printf(dev, "couldn't map ports/memory\n"); 837 error = ENXIO; 838 goto destroy_mutex; 839 } 840 sc->my_btag = rman_get_bustag(sc->my_res); 841 sc->my_bhandle = rman_get_bushandle(sc->my_res); 842 843 rid = 0; 844 sc->my_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 845 RF_SHAREABLE | RF_ACTIVE); 846 847 if (sc->my_irq == NULL) { 848 device_printf(dev, "couldn't map interrupt\n"); 849 error = ENXIO; 850 goto release_io; 851 } 852 853 sc->my_info = my_info_tmp; 854 855 /* Reset the adapter. */ 856 MY_LOCK(sc); 857 my_reset(sc); 858 MY_UNLOCK(sc); 859 860 /* 861 * Get station address 862 */ 863 for (i = 0; i < ETHER_ADDR_LEN; ++i) 864 eaddr[i] = CSR_READ_1(sc, MY_PAR0 + i); 865 866 sc->my_ldata_ptr = malloc(sizeof(struct my_list_data) + 8, 867 M_DEVBUF, M_NOWAIT); 868 if (sc->my_ldata_ptr == NULL) { 869 device_printf(dev, "no memory for list buffers!\n"); 870 error = ENXIO; 871 goto release_irq; 872 } 873 sc->my_ldata = (struct my_list_data *) sc->my_ldata_ptr; 874 round = (uintptr_t)sc->my_ldata_ptr & 0xF; 875 roundptr = sc->my_ldata_ptr; 876 for (i = 0; i < 8; i++) { 877 if (round % 8) { 878 round++; 879 roundptr++; 880 } else 881 break; 882 } 883 sc->my_ldata = (struct my_list_data *) roundptr; 884 bzero(sc->my_ldata, sizeof(struct my_list_data)); 885 886 ifp = sc->my_ifp = if_alloc(IFT_ETHER); 887 if (ifp == NULL) { 888 device_printf(dev, "can not if_alloc()\n"); 889 error = ENOSPC; 890 goto free_ldata; 891 } 892 ifp->if_softc = sc; 893 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 894 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 895 ifp->if_ioctl = my_ioctl; 896 ifp->if_start = my_start; 897 ifp->if_init = my_init; 898 ifp->if_baudrate = 10000000; 899 IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen); 900 ifp->if_snd.ifq_drv_maxlen = ifqmaxlen; 901 IFQ_SET_READY(&ifp->if_snd); 902 903 if (sc->my_info->my_did == MTD803ID) 904 sc->my_pinfo = my_phys; 905 else { 906 if (bootverbose) 907 device_printf(dev, "probing for a PHY\n"); 908 MY_LOCK(sc); 909 for (i = MY_PHYADDR_MIN; i < MY_PHYADDR_MAX + 1; i++) { 910 if (bootverbose) 911 device_printf(dev, "checking address: %d\n", i); 912 sc->my_phy_addr = i; 913 phy_sts = my_phy_readreg(sc, PHY_BMSR); 914 if ((phy_sts != 0) && (phy_sts != 0xffff)) 915 break; 916 else 917 phy_sts = 0; 918 } 919 if (phy_sts) { 920 phy_vid = my_phy_readreg(sc, PHY_VENID); 921 phy_did = my_phy_readreg(sc, PHY_DEVID); 922 if (bootverbose) { 923 device_printf(dev, "found PHY at address %d, ", 924 sc->my_phy_addr); 925 printf("vendor id: %x device id: %x\n", 926 phy_vid, phy_did); 927 } 928 p = my_phys; 929 while (p->my_vid) { 930 if (phy_vid == p->my_vid) { 931 sc->my_pinfo = p; 932 break; 933 } 934 p++; 935 } 936 if (sc->my_pinfo == NULL) 937 sc->my_pinfo = &my_phys[PHY_UNKNOWN]; 938 if (bootverbose) 939 device_printf(dev, "PHY type: %s\n", 940 sc->my_pinfo->my_name); 941 } else { 942 MY_UNLOCK(sc); 943 device_printf(dev, "MII without any phy!\n"); 944 error = ENXIO; 945 goto free_if; 946 } 947 MY_UNLOCK(sc); 948 } 949 950 /* Do ifmedia setup. */ 951 ifmedia_init(&sc->ifmedia, 0, my_ifmedia_upd, my_ifmedia_sts); 952 MY_LOCK(sc); 953 my_getmode_mii(sc); 954 my_autoneg_mii(sc, MY_FLAG_FORCEDELAY, 1); 955 media = sc->ifmedia.ifm_media; 956 my_stop(sc); 957 MY_UNLOCK(sc); 958 ifmedia_set(&sc->ifmedia, media); 959 960 ether_ifattach(ifp, eaddr); 961 962 error = bus_setup_intr(dev, sc->my_irq, INTR_TYPE_NET | INTR_MPSAFE, 963 NULL, my_intr, sc, &sc->my_intrhand); 964 965 if (error) { 966 device_printf(dev, "couldn't set up irq\n"); 967 goto detach_if; 968 } 969 970 return (0); 971 972 detach_if: 973 ether_ifdetach(ifp); 974 free_if: 975 if_free(ifp); 976 free_ldata: 977 free(sc->my_ldata_ptr, M_DEVBUF); 978 release_irq: 979 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->my_irq); 980 release_io: 981 bus_release_resource(dev, MY_RES, MY_RID, sc->my_res); 982 destroy_mutex: 983 mtx_destroy(&sc->my_mtx); 984 return (error); 985 } 986 987 static int 988 my_detach(device_t dev) 989 { 990 struct my_softc *sc; 991 struct ifnet *ifp; 992 993 sc = device_get_softc(dev); 994 ifp = sc->my_ifp; 995 ether_ifdetach(ifp); 996 MY_LOCK(sc); 997 my_stop(sc); 998 MY_UNLOCK(sc); 999 bus_teardown_intr(dev, sc->my_irq, sc->my_intrhand); 1000 callout_drain(&sc->my_watchdog); 1001 callout_drain(&sc->my_autoneg_timer); 1002 1003 if_free(ifp); 1004 free(sc->my_ldata_ptr, M_DEVBUF); 1005 1006 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->my_irq); 1007 bus_release_resource(dev, MY_RES, MY_RID, sc->my_res); 1008 mtx_destroy(&sc->my_mtx); 1009 return (0); 1010 } 1011 1012 1013 /* 1014 * Initialize the transmit descriptors. 1015 */ 1016 static int 1017 my_list_tx_init(struct my_softc * sc) 1018 { 1019 struct my_chain_data *cd; 1020 struct my_list_data *ld; 1021 int i; 1022 1023 MY_LOCK_ASSERT(sc); 1024 cd = &sc->my_cdata; 1025 ld = sc->my_ldata; 1026 for (i = 0; i < MY_TX_LIST_CNT; i++) { 1027 cd->my_tx_chain[i].my_ptr = &ld->my_tx_list[i]; 1028 if (i == (MY_TX_LIST_CNT - 1)) 1029 cd->my_tx_chain[i].my_nextdesc = &cd->my_tx_chain[0]; 1030 else 1031 cd->my_tx_chain[i].my_nextdesc = 1032 &cd->my_tx_chain[i + 1]; 1033 } 1034 cd->my_tx_free = &cd->my_tx_chain[0]; 1035 cd->my_tx_tail = cd->my_tx_head = NULL; 1036 return (0); 1037 } 1038 1039 /* 1040 * Initialize the RX descriptors and allocate mbufs for them. Note that we 1041 * arrange the descriptors in a closed ring, so that the last descriptor 1042 * points back to the first. 1043 */ 1044 static int 1045 my_list_rx_init(struct my_softc * sc) 1046 { 1047 struct my_chain_data *cd; 1048 struct my_list_data *ld; 1049 int i; 1050 1051 MY_LOCK_ASSERT(sc); 1052 cd = &sc->my_cdata; 1053 ld = sc->my_ldata; 1054 for (i = 0; i < MY_RX_LIST_CNT; i++) { 1055 cd->my_rx_chain[i].my_ptr = 1056 (struct my_desc *) & ld->my_rx_list[i]; 1057 if (my_newbuf(sc, &cd->my_rx_chain[i]) == ENOBUFS) { 1058 MY_UNLOCK(sc); 1059 return (ENOBUFS); 1060 } 1061 if (i == (MY_RX_LIST_CNT - 1)) { 1062 cd->my_rx_chain[i].my_nextdesc = &cd->my_rx_chain[0]; 1063 ld->my_rx_list[i].my_next = vtophys(&ld->my_rx_list[0]); 1064 } else { 1065 cd->my_rx_chain[i].my_nextdesc = 1066 &cd->my_rx_chain[i + 1]; 1067 ld->my_rx_list[i].my_next = 1068 vtophys(&ld->my_rx_list[i + 1]); 1069 } 1070 } 1071 cd->my_rx_head = &cd->my_rx_chain[0]; 1072 return (0); 1073 } 1074 1075 /* 1076 * Initialize an RX descriptor and attach an MBUF cluster. 1077 */ 1078 static int 1079 my_newbuf(struct my_softc * sc, struct my_chain_onefrag * c) 1080 { 1081 struct mbuf *m_new = NULL; 1082 1083 MY_LOCK_ASSERT(sc); 1084 MGETHDR(m_new, M_NOWAIT, MT_DATA); 1085 if (m_new == NULL) { 1086 device_printf(sc->my_dev, 1087 "no memory for rx list -- packet dropped!\n"); 1088 return (ENOBUFS); 1089 } 1090 MCLGET(m_new, M_NOWAIT); 1091 if (!(m_new->m_flags & M_EXT)) { 1092 device_printf(sc->my_dev, 1093 "no memory for rx list -- packet dropped!\n"); 1094 m_freem(m_new); 1095 return (ENOBUFS); 1096 } 1097 c->my_mbuf = m_new; 1098 c->my_ptr->my_data = vtophys(mtod(m_new, caddr_t)); 1099 c->my_ptr->my_ctl = (MCLBYTES - 1) << MY_RBSShift; 1100 c->my_ptr->my_status = MY_OWNByNIC; 1101 return (0); 1102 } 1103 1104 /* 1105 * A frame has been uploaded: pass the resulting mbuf chain up to the higher 1106 * level protocols. 1107 */ 1108 static void 1109 my_rxeof(struct my_softc * sc) 1110 { 1111 struct ether_header *eh; 1112 struct mbuf *m; 1113 struct ifnet *ifp; 1114 struct my_chain_onefrag *cur_rx; 1115 int total_len = 0; 1116 u_int32_t rxstat; 1117 1118 MY_LOCK_ASSERT(sc); 1119 ifp = sc->my_ifp; 1120 while (!((rxstat = sc->my_cdata.my_rx_head->my_ptr->my_status) 1121 & MY_OWNByNIC)) { 1122 cur_rx = sc->my_cdata.my_rx_head; 1123 sc->my_cdata.my_rx_head = cur_rx->my_nextdesc; 1124 1125 if (rxstat & MY_ES) { /* error summary: give up this rx pkt */ 1126 ifp->if_ierrors++; 1127 cur_rx->my_ptr->my_status = MY_OWNByNIC; 1128 continue; 1129 } 1130 /* No errors; receive the packet. */ 1131 total_len = (rxstat & MY_FLNGMASK) >> MY_FLNGShift; 1132 total_len -= ETHER_CRC_LEN; 1133 1134 if (total_len < MINCLSIZE) { 1135 m = m_devget(mtod(cur_rx->my_mbuf, char *), 1136 total_len, 0, ifp, NULL); 1137 cur_rx->my_ptr->my_status = MY_OWNByNIC; 1138 if (m == NULL) { 1139 ifp->if_ierrors++; 1140 continue; 1141 } 1142 } else { 1143 m = cur_rx->my_mbuf; 1144 /* 1145 * Try to conjure up a new mbuf cluster. If that 1146 * fails, it means we have an out of memory condition 1147 * and should leave the buffer in place and continue. 1148 * This will result in a lost packet, but there's 1149 * little else we can do in this situation. 1150 */ 1151 if (my_newbuf(sc, cur_rx) == ENOBUFS) { 1152 ifp->if_ierrors++; 1153 cur_rx->my_ptr->my_status = MY_OWNByNIC; 1154 continue; 1155 } 1156 m->m_pkthdr.rcvif = ifp; 1157 m->m_pkthdr.len = m->m_len = total_len; 1158 } 1159 ifp->if_ipackets++; 1160 eh = mtod(m, struct ether_header *); 1161 #if NBPFILTER > 0 1162 /* 1163 * Handle BPF listeners. Let the BPF user see the packet, but 1164 * don't pass it up to the ether_input() layer unless it's a 1165 * broadcast packet, multicast packet, matches our ethernet 1166 * address or the interface is in promiscuous mode. 1167 */ 1168 if (bpf_peers_present(ifp->if_bpf)) { 1169 bpf_mtap(ifp->if_bpf, m); 1170 if (ifp->if_flags & IFF_PROMISC && 1171 (bcmp(eh->ether_dhost, IF_LLADDR(sc->my_ifp), 1172 ETHER_ADDR_LEN) && 1173 (eh->ether_dhost[0] & 1) == 0)) { 1174 m_freem(m); 1175 continue; 1176 } 1177 } 1178 #endif 1179 MY_UNLOCK(sc); 1180 (*ifp->if_input)(ifp, m); 1181 MY_LOCK(sc); 1182 } 1183 return; 1184 } 1185 1186 1187 /* 1188 * A frame was downloaded to the chip. It's safe for us to clean up the list 1189 * buffers. 1190 */ 1191 static void 1192 my_txeof(struct my_softc * sc) 1193 { 1194 struct my_chain *cur_tx; 1195 struct ifnet *ifp; 1196 1197 MY_LOCK_ASSERT(sc); 1198 ifp = sc->my_ifp; 1199 /* Clear the timeout timer. */ 1200 sc->my_timer = 0; 1201 if (sc->my_cdata.my_tx_head == NULL) { 1202 return; 1203 } 1204 /* 1205 * Go through our tx list and free mbufs for those frames that have 1206 * been transmitted. 1207 */ 1208 while (sc->my_cdata.my_tx_head->my_mbuf != NULL) { 1209 u_int32_t txstat; 1210 1211 cur_tx = sc->my_cdata.my_tx_head; 1212 txstat = MY_TXSTATUS(cur_tx); 1213 if ((txstat & MY_OWNByNIC) || txstat == MY_UNSENT) 1214 break; 1215 if (!(CSR_READ_4(sc, MY_TCRRCR) & MY_Enhanced)) { 1216 if (txstat & MY_TXERR) { 1217 ifp->if_oerrors++; 1218 if (txstat & MY_EC) /* excessive collision */ 1219 ifp->if_collisions++; 1220 if (txstat & MY_LC) /* late collision */ 1221 ifp->if_collisions++; 1222 } 1223 ifp->if_collisions += (txstat & MY_NCRMASK) >> 1224 MY_NCRShift; 1225 } 1226 ifp->if_opackets++; 1227 m_freem(cur_tx->my_mbuf); 1228 cur_tx->my_mbuf = NULL; 1229 if (sc->my_cdata.my_tx_head == sc->my_cdata.my_tx_tail) { 1230 sc->my_cdata.my_tx_head = NULL; 1231 sc->my_cdata.my_tx_tail = NULL; 1232 break; 1233 } 1234 sc->my_cdata.my_tx_head = cur_tx->my_nextdesc; 1235 } 1236 if (CSR_READ_4(sc, MY_TCRRCR) & MY_Enhanced) { 1237 ifp->if_collisions += (CSR_READ_4(sc, MY_TSR) & MY_NCRMask); 1238 } 1239 return; 1240 } 1241 1242 /* 1243 * TX 'end of channel' interrupt handler. 1244 */ 1245 static void 1246 my_txeoc(struct my_softc * sc) 1247 { 1248 struct ifnet *ifp; 1249 1250 MY_LOCK_ASSERT(sc); 1251 ifp = sc->my_ifp; 1252 sc->my_timer = 0; 1253 if (sc->my_cdata.my_tx_head == NULL) { 1254 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1255 sc->my_cdata.my_tx_tail = NULL; 1256 if (sc->my_want_auto) 1257 my_autoneg_mii(sc, MY_FLAG_SCHEDDELAY, 1); 1258 } else { 1259 if (MY_TXOWN(sc->my_cdata.my_tx_head) == MY_UNSENT) { 1260 MY_TXOWN(sc->my_cdata.my_tx_head) = MY_OWNByNIC; 1261 sc->my_timer = 5; 1262 CSR_WRITE_4(sc, MY_TXPDR, 0xFFFFFFFF); 1263 } 1264 } 1265 return; 1266 } 1267 1268 static void 1269 my_intr(void *arg) 1270 { 1271 struct my_softc *sc; 1272 struct ifnet *ifp; 1273 u_int32_t status; 1274 1275 sc = arg; 1276 MY_LOCK(sc); 1277 ifp = sc->my_ifp; 1278 if (!(ifp->if_flags & IFF_UP)) { 1279 MY_UNLOCK(sc); 1280 return; 1281 } 1282 /* Disable interrupts. */ 1283 CSR_WRITE_4(sc, MY_IMR, 0x00000000); 1284 1285 for (;;) { 1286 status = CSR_READ_4(sc, MY_ISR); 1287 status &= MY_INTRS; 1288 if (status) 1289 CSR_WRITE_4(sc, MY_ISR, status); 1290 else 1291 break; 1292 1293 if (status & MY_RI) /* receive interrupt */ 1294 my_rxeof(sc); 1295 1296 if ((status & MY_RBU) || (status & MY_RxErr)) { 1297 /* rx buffer unavailable or rx error */ 1298 ifp->if_ierrors++; 1299 #ifdef foo 1300 my_stop(sc); 1301 my_reset(sc); 1302 my_init_locked(sc); 1303 #endif 1304 } 1305 if (status & MY_TI) /* tx interrupt */ 1306 my_txeof(sc); 1307 if (status & MY_ETI) /* tx early interrupt */ 1308 my_txeof(sc); 1309 if (status & MY_TBU) /* tx buffer unavailable */ 1310 my_txeoc(sc); 1311 1312 #if 0 /* 90/1/18 delete */ 1313 if (status & MY_FBE) { 1314 my_reset(sc); 1315 my_init_locked(sc); 1316 } 1317 #endif 1318 1319 } 1320 1321 /* Re-enable interrupts. */ 1322 CSR_WRITE_4(sc, MY_IMR, MY_INTRS); 1323 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1324 my_start_locked(ifp); 1325 MY_UNLOCK(sc); 1326 return; 1327 } 1328 1329 /* 1330 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1331 * pointers to the fragment pointers. 1332 */ 1333 static int 1334 my_encap(struct my_softc * sc, struct my_chain * c, struct mbuf * m_head) 1335 { 1336 struct my_desc *f = NULL; 1337 int total_len; 1338 struct mbuf *m, *m_new = NULL; 1339 1340 MY_LOCK_ASSERT(sc); 1341 /* calculate the total tx pkt length */ 1342 total_len = 0; 1343 for (m = m_head; m != NULL; m = m->m_next) 1344 total_len += m->m_len; 1345 /* 1346 * Start packing the mbufs in this chain into the fragment pointers. 1347 * Stop when we run out of fragments or hit the end of the mbuf 1348 * chain. 1349 */ 1350 m = m_head; 1351 MGETHDR(m_new, M_NOWAIT, MT_DATA); 1352 if (m_new == NULL) { 1353 device_printf(sc->my_dev, "no memory for tx list"); 1354 return (1); 1355 } 1356 if (m_head->m_pkthdr.len > MHLEN) { 1357 MCLGET(m_new, M_NOWAIT); 1358 if (!(m_new->m_flags & M_EXT)) { 1359 m_freem(m_new); 1360 device_printf(sc->my_dev, "no memory for tx list"); 1361 return (1); 1362 } 1363 } 1364 m_copydata(m_head, 0, m_head->m_pkthdr.len, mtod(m_new, caddr_t)); 1365 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1366 m_freem(m_head); 1367 m_head = m_new; 1368 f = &c->my_ptr->my_frag[0]; 1369 f->my_status = 0; 1370 f->my_data = vtophys(mtod(m_new, caddr_t)); 1371 total_len = m_new->m_len; 1372 f->my_ctl = MY_TXFD | MY_TXLD | MY_CRCEnable | MY_PADEnable; 1373 f->my_ctl |= total_len << MY_PKTShift; /* pkt size */ 1374 f->my_ctl |= total_len; /* buffer size */ 1375 /* 89/12/29 add, for mtd891 *//* [ 89? ] */ 1376 if (sc->my_info->my_did == MTD891ID) 1377 f->my_ctl |= MY_ETIControl | MY_RetryTxLC; 1378 c->my_mbuf = m_head; 1379 c->my_lastdesc = 0; 1380 MY_TXNEXT(c) = vtophys(&c->my_nextdesc->my_ptr->my_frag[0]); 1381 return (0); 1382 } 1383 1384 /* 1385 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1386 * to the mbuf data regions directly in the transmit lists. We also save a 1387 * copy of the pointers since the transmit list fragment pointers are 1388 * physical addresses. 1389 */ 1390 static void 1391 my_start(struct ifnet * ifp) 1392 { 1393 struct my_softc *sc; 1394 1395 sc = ifp->if_softc; 1396 MY_LOCK(sc); 1397 my_start_locked(ifp); 1398 MY_UNLOCK(sc); 1399 } 1400 1401 static void 1402 my_start_locked(struct ifnet * ifp) 1403 { 1404 struct my_softc *sc; 1405 struct mbuf *m_head = NULL; 1406 struct my_chain *cur_tx = NULL, *start_tx; 1407 1408 sc = ifp->if_softc; 1409 MY_LOCK_ASSERT(sc); 1410 if (sc->my_autoneg) { 1411 sc->my_tx_pend = 1; 1412 return; 1413 } 1414 /* 1415 * Check for an available queue slot. If there are none, punt. 1416 */ 1417 if (sc->my_cdata.my_tx_free->my_mbuf != NULL) { 1418 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1419 return; 1420 } 1421 start_tx = sc->my_cdata.my_tx_free; 1422 while (sc->my_cdata.my_tx_free->my_mbuf == NULL) { 1423 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1424 if (m_head == NULL) 1425 break; 1426 1427 /* Pick a descriptor off the free list. */ 1428 cur_tx = sc->my_cdata.my_tx_free; 1429 sc->my_cdata.my_tx_free = cur_tx->my_nextdesc; 1430 1431 /* Pack the data into the descriptor. */ 1432 my_encap(sc, cur_tx, m_head); 1433 1434 if (cur_tx != start_tx) 1435 MY_TXOWN(cur_tx) = MY_OWNByNIC; 1436 #if NBPFILTER > 0 1437 /* 1438 * If there's a BPF listener, bounce a copy of this frame to 1439 * him. 1440 */ 1441 BPF_MTAP(ifp, cur_tx->my_mbuf); 1442 #endif 1443 } 1444 /* 1445 * If there are no packets queued, bail. 1446 */ 1447 if (cur_tx == NULL) { 1448 return; 1449 } 1450 /* 1451 * Place the request for the upload interrupt in the last descriptor 1452 * in the chain. This way, if we're chaining several packets at once, 1453 * we'll only get an interrupt once for the whole chain rather than 1454 * once for each packet. 1455 */ 1456 MY_TXCTL(cur_tx) |= MY_TXIC; 1457 cur_tx->my_ptr->my_frag[0].my_ctl |= MY_TXIC; 1458 sc->my_cdata.my_tx_tail = cur_tx; 1459 if (sc->my_cdata.my_tx_head == NULL) 1460 sc->my_cdata.my_tx_head = start_tx; 1461 MY_TXOWN(start_tx) = MY_OWNByNIC; 1462 CSR_WRITE_4(sc, MY_TXPDR, 0xFFFFFFFF); /* tx polling demand */ 1463 1464 /* 1465 * Set a timeout in case the chip goes out to lunch. 1466 */ 1467 sc->my_timer = 5; 1468 return; 1469 } 1470 1471 static void 1472 my_init(void *xsc) 1473 { 1474 struct my_softc *sc = xsc; 1475 1476 MY_LOCK(sc); 1477 my_init_locked(sc); 1478 MY_UNLOCK(sc); 1479 } 1480 1481 static void 1482 my_init_locked(struct my_softc *sc) 1483 { 1484 struct ifnet *ifp = sc->my_ifp; 1485 u_int16_t phy_bmcr = 0; 1486 1487 MY_LOCK_ASSERT(sc); 1488 if (sc->my_autoneg) { 1489 return; 1490 } 1491 if (sc->my_pinfo != NULL) 1492 phy_bmcr = my_phy_readreg(sc, PHY_BMCR); 1493 /* 1494 * Cancel pending I/O and free all RX/TX buffers. 1495 */ 1496 my_stop(sc); 1497 my_reset(sc); 1498 1499 /* 1500 * Set cache alignment and burst length. 1501 */ 1502 #if 0 /* 89/9/1 modify, */ 1503 CSR_WRITE_4(sc, MY_BCR, MY_RPBLE512); 1504 CSR_WRITE_4(sc, MY_TCRRCR, MY_TFTSF); 1505 #endif 1506 CSR_WRITE_4(sc, MY_BCR, MY_PBL8); 1507 CSR_WRITE_4(sc, MY_TCRRCR, MY_TFTSF | MY_RBLEN | MY_RPBLE512); 1508 /* 1509 * 89/12/29 add, for mtd891, 1510 */ 1511 if (sc->my_info->my_did == MTD891ID) { 1512 MY_SETBIT(sc, MY_BCR, MY_PROG); 1513 MY_SETBIT(sc, MY_TCRRCR, MY_Enhanced); 1514 } 1515 my_setcfg(sc, phy_bmcr); 1516 /* Init circular RX list. */ 1517 if (my_list_rx_init(sc) == ENOBUFS) { 1518 device_printf(sc->my_dev, "init failed: no memory for rx buffers\n"); 1519 my_stop(sc); 1520 return; 1521 } 1522 /* Init TX descriptors. */ 1523 my_list_tx_init(sc); 1524 1525 /* If we want promiscuous mode, set the allframes bit. */ 1526 if (ifp->if_flags & IFF_PROMISC) 1527 MY_SETBIT(sc, MY_TCRRCR, MY_PROM); 1528 else 1529 MY_CLRBIT(sc, MY_TCRRCR, MY_PROM); 1530 1531 /* 1532 * Set capture broadcast bit to capture broadcast frames. 1533 */ 1534 if (ifp->if_flags & IFF_BROADCAST) 1535 MY_SETBIT(sc, MY_TCRRCR, MY_AB); 1536 else 1537 MY_CLRBIT(sc, MY_TCRRCR, MY_AB); 1538 1539 /* 1540 * Program the multicast filter, if necessary. 1541 */ 1542 my_setmulti(sc); 1543 1544 /* 1545 * Load the address of the RX list. 1546 */ 1547 MY_CLRBIT(sc, MY_TCRRCR, MY_RE); 1548 CSR_WRITE_4(sc, MY_RXLBA, vtophys(&sc->my_ldata->my_rx_list[0])); 1549 1550 /* 1551 * Enable interrupts. 1552 */ 1553 CSR_WRITE_4(sc, MY_IMR, MY_INTRS); 1554 CSR_WRITE_4(sc, MY_ISR, 0xFFFFFFFF); 1555 1556 /* Enable receiver and transmitter. */ 1557 MY_SETBIT(sc, MY_TCRRCR, MY_RE); 1558 MY_CLRBIT(sc, MY_TCRRCR, MY_TE); 1559 CSR_WRITE_4(sc, MY_TXLBA, vtophys(&sc->my_ldata->my_tx_list[0])); 1560 MY_SETBIT(sc, MY_TCRRCR, MY_TE); 1561 1562 /* Restore state of BMCR */ 1563 if (sc->my_pinfo != NULL) 1564 my_phy_writereg(sc, PHY_BMCR, phy_bmcr); 1565 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1566 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1567 1568 callout_reset(&sc->my_watchdog, hz, my_watchdog, sc); 1569 return; 1570 } 1571 1572 /* 1573 * Set media options. 1574 */ 1575 1576 static int 1577 my_ifmedia_upd(struct ifnet * ifp) 1578 { 1579 struct my_softc *sc; 1580 struct ifmedia *ifm; 1581 1582 sc = ifp->if_softc; 1583 MY_LOCK(sc); 1584 ifm = &sc->ifmedia; 1585 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) { 1586 MY_UNLOCK(sc); 1587 return (EINVAL); 1588 } 1589 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO) 1590 my_autoneg_mii(sc, MY_FLAG_SCHEDDELAY, 1); 1591 else 1592 my_setmode_mii(sc, ifm->ifm_media); 1593 MY_UNLOCK(sc); 1594 return (0); 1595 } 1596 1597 /* 1598 * Report current media status. 1599 */ 1600 1601 static void 1602 my_ifmedia_sts(struct ifnet * ifp, struct ifmediareq * ifmr) 1603 { 1604 struct my_softc *sc; 1605 u_int16_t advert = 0, ability = 0; 1606 1607 sc = ifp->if_softc; 1608 MY_LOCK(sc); 1609 ifmr->ifm_active = IFM_ETHER; 1610 if (!(my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_AUTONEGENBL)) { 1611 #if 0 /* this version did not support 1000M, */ 1612 if (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_1000) 1613 ifmr->ifm_active = IFM_ETHER | IFM_1000TX; 1614 #endif 1615 if (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_SPEEDSEL) 1616 ifmr->ifm_active = IFM_ETHER | IFM_100_TX; 1617 else 1618 ifmr->ifm_active = IFM_ETHER | IFM_10_T; 1619 if (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_DUPLEX) 1620 ifmr->ifm_active |= IFM_FDX; 1621 else 1622 ifmr->ifm_active |= IFM_HDX; 1623 1624 MY_UNLOCK(sc); 1625 return; 1626 } 1627 ability = my_phy_readreg(sc, PHY_LPAR); 1628 advert = my_phy_readreg(sc, PHY_ANAR); 1629 1630 #if 0 /* this version did not support 1000M, */ 1631 if (sc->my_pinfo->my_vid = MarvellPHYID0) { 1632 ability2 = my_phy_readreg(sc, PHY_1000SR); 1633 if (ability2 & PHY_1000SR_1000BTXFULL) { 1634 advert = 0; 1635 ability = 0; 1636 ifmr->ifm_active = IFM_ETHER|IFM_1000_T|IFM_FDX; 1637 } else if (ability & PHY_1000SR_1000BTXHALF) { 1638 advert = 0; 1639 ability = 0; 1640 ifmr->ifm_active = IFM_ETHER|IFM_1000_T|IFM_HDX; 1641 } 1642 } 1643 #endif 1644 if (advert & PHY_ANAR_100BT4 && ability & PHY_ANAR_100BT4) 1645 ifmr->ifm_active = IFM_ETHER | IFM_100_T4; 1646 else if (advert & PHY_ANAR_100BTXFULL && ability & PHY_ANAR_100BTXFULL) 1647 ifmr->ifm_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 1648 else if (advert & PHY_ANAR_100BTXHALF && ability & PHY_ANAR_100BTXHALF) 1649 ifmr->ifm_active = IFM_ETHER | IFM_100_TX | IFM_HDX; 1650 else if (advert & PHY_ANAR_10BTFULL && ability & PHY_ANAR_10BTFULL) 1651 ifmr->ifm_active = IFM_ETHER | IFM_10_T | IFM_FDX; 1652 else if (advert & PHY_ANAR_10BTHALF && ability & PHY_ANAR_10BTHALF) 1653 ifmr->ifm_active = IFM_ETHER | IFM_10_T | IFM_HDX; 1654 MY_UNLOCK(sc); 1655 return; 1656 } 1657 1658 static int 1659 my_ioctl(struct ifnet * ifp, u_long command, caddr_t data) 1660 { 1661 struct my_softc *sc = ifp->if_softc; 1662 struct ifreq *ifr = (struct ifreq *) data; 1663 int error; 1664 1665 switch (command) { 1666 case SIOCSIFFLAGS: 1667 MY_LOCK(sc); 1668 if (ifp->if_flags & IFF_UP) 1669 my_init_locked(sc); 1670 else if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1671 my_stop(sc); 1672 MY_UNLOCK(sc); 1673 error = 0; 1674 break; 1675 case SIOCADDMULTI: 1676 case SIOCDELMULTI: 1677 MY_LOCK(sc); 1678 my_setmulti(sc); 1679 MY_UNLOCK(sc); 1680 error = 0; 1681 break; 1682 case SIOCGIFMEDIA: 1683 case SIOCSIFMEDIA: 1684 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); 1685 break; 1686 default: 1687 error = ether_ioctl(ifp, command, data); 1688 break; 1689 } 1690 return (error); 1691 } 1692 1693 static void 1694 my_watchdog(void *arg) 1695 { 1696 struct my_softc *sc; 1697 struct ifnet *ifp; 1698 1699 sc = arg; 1700 MY_LOCK_ASSERT(sc); 1701 callout_reset(&sc->my_watchdog, hz, my_watchdog, sc); 1702 if (sc->my_timer == 0 || --sc->my_timer > 0) 1703 return; 1704 1705 ifp = sc->my_ifp; 1706 ifp->if_oerrors++; 1707 if_printf(ifp, "watchdog timeout\n"); 1708 if (!(my_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT)) 1709 if_printf(ifp, "no carrier - transceiver cable problem?\n"); 1710 my_stop(sc); 1711 my_reset(sc); 1712 my_init_locked(sc); 1713 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1714 my_start_locked(ifp); 1715 } 1716 1717 1718 /* 1719 * Stop the adapter and free any mbufs allocated to the RX and TX lists. 1720 */ 1721 static void 1722 my_stop(struct my_softc * sc) 1723 { 1724 register int i; 1725 struct ifnet *ifp; 1726 1727 MY_LOCK_ASSERT(sc); 1728 ifp = sc->my_ifp; 1729 1730 callout_stop(&sc->my_autoneg_timer); 1731 callout_stop(&sc->my_watchdog); 1732 1733 MY_CLRBIT(sc, MY_TCRRCR, (MY_RE | MY_TE)); 1734 CSR_WRITE_4(sc, MY_IMR, 0x00000000); 1735 CSR_WRITE_4(sc, MY_TXLBA, 0x00000000); 1736 CSR_WRITE_4(sc, MY_RXLBA, 0x00000000); 1737 1738 /* 1739 * Free data in the RX lists. 1740 */ 1741 for (i = 0; i < MY_RX_LIST_CNT; i++) { 1742 if (sc->my_cdata.my_rx_chain[i].my_mbuf != NULL) { 1743 m_freem(sc->my_cdata.my_rx_chain[i].my_mbuf); 1744 sc->my_cdata.my_rx_chain[i].my_mbuf = NULL; 1745 } 1746 } 1747 bzero((char *)&sc->my_ldata->my_rx_list, 1748 sizeof(sc->my_ldata->my_rx_list)); 1749 /* 1750 * Free the TX list buffers. 1751 */ 1752 for (i = 0; i < MY_TX_LIST_CNT; i++) { 1753 if (sc->my_cdata.my_tx_chain[i].my_mbuf != NULL) { 1754 m_freem(sc->my_cdata.my_tx_chain[i].my_mbuf); 1755 sc->my_cdata.my_tx_chain[i].my_mbuf = NULL; 1756 } 1757 } 1758 bzero((char *)&sc->my_ldata->my_tx_list, 1759 sizeof(sc->my_ldata->my_tx_list)); 1760 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1761 return; 1762 } 1763 1764 /* 1765 * Stop all chip I/O so that the kernel's probe routines don't get confused 1766 * by errant DMAs when rebooting. 1767 */ 1768 static int 1769 my_shutdown(device_t dev) 1770 { 1771 struct my_softc *sc; 1772 1773 sc = device_get_softc(dev); 1774 MY_LOCK(sc); 1775 my_stop(sc); 1776 MY_UNLOCK(sc); 1777 return 0; 1778 } 1779