1 /*- 2 * Written by: yen_cw@myson.com.tw 3 * Copyright (c) 2002 Myson Technology Inc. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions, and the following disclaimer, 11 * without modification, immediately at the beginning of the file. 12 * 2. The name of the author may not be used to endorse or promote products 13 * derived from this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 19 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * Myson fast ethernet PCI NIC driver, available at: http://www.myson.com.tw/ 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/sockio.h> 36 #include <sys/mbuf.h> 37 #include <sys/malloc.h> 38 #include <sys/kernel.h> 39 #include <sys/socket.h> 40 #include <sys/queue.h> 41 #include <sys/types.h> 42 #include <sys/bus.h> 43 #include <sys/module.h> 44 #include <sys/lock.h> 45 #include <sys/mutex.h> 46 47 #define NBPFILTER 1 48 49 #include <net/if.h> 50 #include <net/if_arp.h> 51 #include <net/ethernet.h> 52 #include <net/if_media.h> 53 #include <net/if_types.h> 54 #include <net/if_dl.h> 55 #include <net/bpf.h> 56 57 #include <vm/vm.h> /* for vtophys */ 58 #include <vm/pmap.h> /* for vtophys */ 59 #include <machine/bus.h> 60 #include <machine/resource.h> 61 #include <sys/bus.h> 62 #include <sys/rman.h> 63 64 #include <dev/pci/pcireg.h> 65 #include <dev/pci/pcivar.h> 66 67 #include <dev/mii/mii.h> 68 #include <dev/mii/miivar.h> 69 70 #include "miibus_if.h" 71 72 /* 73 * #define MY_USEIOSPACE 74 */ 75 76 static int MY_USEIOSPACE = 1; 77 78 #ifdef MY_USEIOSPACE 79 #define MY_RES SYS_RES_IOPORT 80 #define MY_RID MY_PCI_LOIO 81 #else 82 #define MY_RES SYS_RES_MEMORY 83 #define MY_RID MY_PCI_LOMEM 84 #endif 85 86 87 #include <dev/my/if_myreg.h> 88 89 #ifndef lint 90 static const char rcsid[] = 91 "$Id: if_my.c,v 1.16 2003/04/15 06:37:25 mdodd Exp $"; 92 #endif 93 94 /* 95 * Various supported device vendors/types and their names. 96 */ 97 struct my_type *my_info_tmp; 98 static struct my_type my_devs[] = { 99 {MYSONVENDORID, MTD800ID, "Myson MTD80X Based Fast Ethernet Card"}, 100 {MYSONVENDORID, MTD803ID, "Myson MTD80X Based Fast Ethernet Card"}, 101 {MYSONVENDORID, MTD891ID, "Myson MTD89X Based Giga Ethernet Card"}, 102 {0, 0, NULL} 103 }; 104 105 /* 106 * Various supported PHY vendors/types and their names. Note that this driver 107 * will work with pretty much any MII-compliant PHY, so failure to positively 108 * identify the chip is not a fatal error. 109 */ 110 static struct my_type my_phys[] = { 111 {MysonPHYID0, MysonPHYID0, "<MYSON MTD981>"}, 112 {SeeqPHYID0, SeeqPHYID0, "<SEEQ 80225>"}, 113 {AhdocPHYID0, AhdocPHYID0, "<AHDOC 101>"}, 114 {MarvellPHYID0, MarvellPHYID0, "<MARVELL 88E1000>"}, 115 {LevelOnePHYID0, LevelOnePHYID0, "<LevelOne LXT1000>"}, 116 {0, 0, "<MII-compliant physical interface>"} 117 }; 118 119 static int my_probe(device_t); 120 static int my_attach(device_t); 121 static int my_detach(device_t); 122 static int my_newbuf(struct my_softc *, struct my_chain_onefrag *); 123 static int my_encap(struct my_softc *, struct my_chain *, struct mbuf *); 124 static void my_rxeof(struct my_softc *); 125 static void my_txeof(struct my_softc *); 126 static void my_txeoc(struct my_softc *); 127 static void my_intr(void *); 128 static void my_start(struct ifnet *); 129 static void my_start_locked(struct ifnet *); 130 static int my_ioctl(struct ifnet *, u_long, caddr_t); 131 static void my_init(void *); 132 static void my_init_locked(struct my_softc *); 133 static void my_stop(struct my_softc *); 134 static void my_watchdog(struct ifnet *); 135 static void my_shutdown(device_t); 136 static int my_ifmedia_upd(struct ifnet *); 137 static void my_ifmedia_sts(struct ifnet *, struct ifmediareq *); 138 static u_int16_t my_phy_readreg(struct my_softc *, int); 139 static void my_phy_writereg(struct my_softc *, int, int); 140 static void my_autoneg_xmit(struct my_softc *); 141 static void my_autoneg_mii(struct my_softc *, int, int); 142 static void my_setmode_mii(struct my_softc *, int); 143 static void my_getmode_mii(struct my_softc *); 144 static void my_setcfg(struct my_softc *, int); 145 static void my_setmulti(struct my_softc *); 146 static void my_reset(struct my_softc *); 147 static int my_list_rx_init(struct my_softc *); 148 static int my_list_tx_init(struct my_softc *); 149 static long my_send_cmd_to_phy(struct my_softc *, int, int); 150 151 #define MY_SETBIT(sc, reg, x) CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 152 #define MY_CLRBIT(sc, reg, x) CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 153 154 static device_method_t my_methods[] = { 155 /* Device interface */ 156 DEVMETHOD(device_probe, my_probe), 157 DEVMETHOD(device_attach, my_attach), 158 DEVMETHOD(device_detach, my_detach), 159 DEVMETHOD(device_shutdown, my_shutdown), 160 161 {0, 0} 162 }; 163 164 static driver_t my_driver = { 165 "my", 166 my_methods, 167 sizeof(struct my_softc) 168 }; 169 170 static devclass_t my_devclass; 171 172 DRIVER_MODULE(my, pci, my_driver, my_devclass, 0, 0); 173 MODULE_DEPEND(my, pci, 1, 1, 1); 174 MODULE_DEPEND(my, ether, 1, 1, 1); 175 176 static long 177 my_send_cmd_to_phy(struct my_softc * sc, int opcode, int regad) 178 { 179 long miir; 180 int i; 181 int mask, data; 182 183 MY_LOCK_ASSERT(sc); 184 185 /* enable MII output */ 186 miir = CSR_READ_4(sc, MY_MANAGEMENT); 187 miir &= 0xfffffff0; 188 189 miir |= MY_MASK_MIIR_MII_WRITE + MY_MASK_MIIR_MII_MDO; 190 191 /* send 32 1's preamble */ 192 for (i = 0; i < 32; i++) { 193 /* low MDC; MDO is already high (miir) */ 194 miir &= ~MY_MASK_MIIR_MII_MDC; 195 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 196 197 /* high MDC */ 198 miir |= MY_MASK_MIIR_MII_MDC; 199 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 200 } 201 202 /* calculate ST+OP+PHYAD+REGAD+TA */ 203 data = opcode | (sc->my_phy_addr << 7) | (regad << 2); 204 205 /* sent out */ 206 mask = 0x8000; 207 while (mask) { 208 /* low MDC, prepare MDO */ 209 miir &= ~(MY_MASK_MIIR_MII_MDC + MY_MASK_MIIR_MII_MDO); 210 if (mask & data) 211 miir |= MY_MASK_MIIR_MII_MDO; 212 213 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 214 /* high MDC */ 215 miir |= MY_MASK_MIIR_MII_MDC; 216 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 217 DELAY(30); 218 219 /* next */ 220 mask >>= 1; 221 if (mask == 0x2 && opcode == MY_OP_READ) 222 miir &= ~MY_MASK_MIIR_MII_WRITE; 223 } 224 225 return miir; 226 } 227 228 229 static u_int16_t 230 my_phy_readreg(struct my_softc * sc, int reg) 231 { 232 long miir; 233 int mask, data; 234 235 MY_LOCK_ASSERT(sc); 236 237 if (sc->my_info->my_did == MTD803ID) 238 data = CSR_READ_2(sc, MY_PHYBASE + reg * 2); 239 else { 240 miir = my_send_cmd_to_phy(sc, MY_OP_READ, reg); 241 242 /* read data */ 243 mask = 0x8000; 244 data = 0; 245 while (mask) { 246 /* low MDC */ 247 miir &= ~MY_MASK_MIIR_MII_MDC; 248 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 249 250 /* read MDI */ 251 miir = CSR_READ_4(sc, MY_MANAGEMENT); 252 if (miir & MY_MASK_MIIR_MII_MDI) 253 data |= mask; 254 255 /* high MDC, and wait */ 256 miir |= MY_MASK_MIIR_MII_MDC; 257 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 258 DELAY(30); 259 260 /* next */ 261 mask >>= 1; 262 } 263 264 /* low MDC */ 265 miir &= ~MY_MASK_MIIR_MII_MDC; 266 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 267 } 268 269 return (u_int16_t) data; 270 } 271 272 273 static void 274 my_phy_writereg(struct my_softc * sc, int reg, int data) 275 { 276 long miir; 277 int mask; 278 279 MY_LOCK_ASSERT(sc); 280 281 if (sc->my_info->my_did == MTD803ID) 282 CSR_WRITE_2(sc, MY_PHYBASE + reg * 2, data); 283 else { 284 miir = my_send_cmd_to_phy(sc, MY_OP_WRITE, reg); 285 286 /* write data */ 287 mask = 0x8000; 288 while (mask) { 289 /* low MDC, prepare MDO */ 290 miir &= ~(MY_MASK_MIIR_MII_MDC + MY_MASK_MIIR_MII_MDO); 291 if (mask & data) 292 miir |= MY_MASK_MIIR_MII_MDO; 293 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 294 DELAY(1); 295 296 /* high MDC */ 297 miir |= MY_MASK_MIIR_MII_MDC; 298 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 299 DELAY(1); 300 301 /* next */ 302 mask >>= 1; 303 } 304 305 /* low MDC */ 306 miir &= ~MY_MASK_MIIR_MII_MDC; 307 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 308 } 309 return; 310 } 311 312 313 /* 314 * Program the 64-bit multicast hash filter. 315 */ 316 static void 317 my_setmulti(struct my_softc * sc) 318 { 319 struct ifnet *ifp; 320 int h = 0; 321 u_int32_t hashes[2] = {0, 0}; 322 struct ifmultiaddr *ifma; 323 u_int32_t rxfilt; 324 int mcnt = 0; 325 326 MY_LOCK_ASSERT(sc); 327 328 ifp = sc->my_ifp; 329 330 rxfilt = CSR_READ_4(sc, MY_TCRRCR); 331 332 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 333 rxfilt |= MY_AM; 334 CSR_WRITE_4(sc, MY_TCRRCR, rxfilt); 335 CSR_WRITE_4(sc, MY_MAR0, 0xFFFFFFFF); 336 CSR_WRITE_4(sc, MY_MAR1, 0xFFFFFFFF); 337 338 return; 339 } 340 /* first, zot all the existing hash bits */ 341 CSR_WRITE_4(sc, MY_MAR0, 0); 342 CSR_WRITE_4(sc, MY_MAR1, 0); 343 344 /* now program new ones */ 345 IF_ADDR_LOCK(ifp); 346 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 347 if (ifma->ifma_addr->sa_family != AF_LINK) 348 continue; 349 h = ~ether_crc32_be(LLADDR((struct sockaddr_dl *) 350 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 351 if (h < 32) 352 hashes[0] |= (1 << h); 353 else 354 hashes[1] |= (1 << (h - 32)); 355 mcnt++; 356 } 357 IF_ADDR_UNLOCK(ifp); 358 359 if (mcnt) 360 rxfilt |= MY_AM; 361 else 362 rxfilt &= ~MY_AM; 363 CSR_WRITE_4(sc, MY_MAR0, hashes[0]); 364 CSR_WRITE_4(sc, MY_MAR1, hashes[1]); 365 CSR_WRITE_4(sc, MY_TCRRCR, rxfilt); 366 return; 367 } 368 369 /* 370 * Initiate an autonegotiation session. 371 */ 372 static void 373 my_autoneg_xmit(struct my_softc * sc) 374 { 375 u_int16_t phy_sts = 0; 376 377 MY_LOCK_ASSERT(sc); 378 379 my_phy_writereg(sc, PHY_BMCR, PHY_BMCR_RESET); 380 DELAY(500); 381 while (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_RESET); 382 383 phy_sts = my_phy_readreg(sc, PHY_BMCR); 384 phy_sts |= PHY_BMCR_AUTONEGENBL | PHY_BMCR_AUTONEGRSTR; 385 my_phy_writereg(sc, PHY_BMCR, phy_sts); 386 387 return; 388 } 389 390 391 /* 392 * Invoke autonegotiation on a PHY. 393 */ 394 static void 395 my_autoneg_mii(struct my_softc * sc, int flag, int verbose) 396 { 397 u_int16_t phy_sts = 0, media, advert, ability; 398 u_int16_t ability2 = 0; 399 struct ifnet *ifp; 400 struct ifmedia *ifm; 401 402 MY_LOCK_ASSERT(sc); 403 404 ifm = &sc->ifmedia; 405 ifp = sc->my_ifp; 406 407 ifm->ifm_media = IFM_ETHER | IFM_AUTO; 408 409 #ifndef FORCE_AUTONEG_TFOUR 410 /* 411 * First, see if autoneg is supported. If not, there's no point in 412 * continuing. 413 */ 414 phy_sts = my_phy_readreg(sc, PHY_BMSR); 415 if (!(phy_sts & PHY_BMSR_CANAUTONEG)) { 416 if (verbose) 417 if_printf(ifp, "autonegotiation not supported\n"); 418 ifm->ifm_media = IFM_ETHER | IFM_10_T | IFM_HDX; 419 return; 420 } 421 #endif 422 switch (flag) { 423 case MY_FLAG_FORCEDELAY: 424 /* 425 * XXX Never use this option anywhere but in the probe 426 * routine: making the kernel stop dead in its tracks for 427 * three whole seconds after we've gone multi-user is really 428 * bad manners. 429 */ 430 my_autoneg_xmit(sc); 431 DELAY(5000000); 432 break; 433 case MY_FLAG_SCHEDDELAY: 434 /* 435 * Wait for the transmitter to go idle before starting an 436 * autoneg session, otherwise my_start() may clobber our 437 * timeout, and we don't want to allow transmission during an 438 * autoneg session since that can screw it up. 439 */ 440 if (sc->my_cdata.my_tx_head != NULL) { 441 sc->my_want_auto = 1; 442 MY_UNLOCK(sc); 443 return; 444 } 445 my_autoneg_xmit(sc); 446 ifp->if_timer = 5; 447 sc->my_autoneg = 1; 448 sc->my_want_auto = 0; 449 return; 450 case MY_FLAG_DELAYTIMEO: 451 ifp->if_timer = 0; 452 sc->my_autoneg = 0; 453 break; 454 default: 455 if_printf(ifp, "invalid autoneg flag: %d\n", flag); 456 return; 457 } 458 459 if (my_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_AUTONEGCOMP) { 460 if (verbose) 461 if_printf(ifp, "autoneg complete, "); 462 phy_sts = my_phy_readreg(sc, PHY_BMSR); 463 } else { 464 if (verbose) 465 if_printf(ifp, "autoneg not complete, "); 466 } 467 468 media = my_phy_readreg(sc, PHY_BMCR); 469 470 /* Link is good. Report modes and set duplex mode. */ 471 if (my_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT) { 472 if (verbose) 473 if_printf(ifp, "link status good. "); 474 advert = my_phy_readreg(sc, PHY_ANAR); 475 ability = my_phy_readreg(sc, PHY_LPAR); 476 if ((sc->my_pinfo->my_vid == MarvellPHYID0) || 477 (sc->my_pinfo->my_vid == LevelOnePHYID0)) { 478 ability2 = my_phy_readreg(sc, PHY_1000SR); 479 if (ability2 & PHY_1000SR_1000BTXFULL) { 480 advert = 0; 481 ability = 0; 482 /* 483 * this version did not support 1000M, 484 * ifm->ifm_media = 485 * IFM_ETHER|IFM_1000_T|IFM_FDX; 486 */ 487 ifm->ifm_media = 488 IFM_ETHER | IFM_100_TX | IFM_FDX; 489 media &= ~PHY_BMCR_SPEEDSEL; 490 media |= PHY_BMCR_1000; 491 media |= PHY_BMCR_DUPLEX; 492 printf("(full-duplex, 1000Mbps)\n"); 493 } else if (ability2 & PHY_1000SR_1000BTXHALF) { 494 advert = 0; 495 ability = 0; 496 /* 497 * this version did not support 1000M, 498 * ifm->ifm_media = IFM_ETHER|IFM_1000_T; 499 */ 500 ifm->ifm_media = IFM_ETHER | IFM_100_TX; 501 media &= ~PHY_BMCR_SPEEDSEL; 502 media &= ~PHY_BMCR_DUPLEX; 503 media |= PHY_BMCR_1000; 504 printf("(half-duplex, 1000Mbps)\n"); 505 } 506 } 507 if (advert & PHY_ANAR_100BT4 && ability & PHY_ANAR_100BT4) { 508 ifm->ifm_media = IFM_ETHER | IFM_100_T4; 509 media |= PHY_BMCR_SPEEDSEL; 510 media &= ~PHY_BMCR_DUPLEX; 511 printf("(100baseT4)\n"); 512 } else if (advert & PHY_ANAR_100BTXFULL && 513 ability & PHY_ANAR_100BTXFULL) { 514 ifm->ifm_media = IFM_ETHER | IFM_100_TX | IFM_FDX; 515 media |= PHY_BMCR_SPEEDSEL; 516 media |= PHY_BMCR_DUPLEX; 517 printf("(full-duplex, 100Mbps)\n"); 518 } else if (advert & PHY_ANAR_100BTXHALF && 519 ability & PHY_ANAR_100BTXHALF) { 520 ifm->ifm_media = IFM_ETHER | IFM_100_TX | IFM_HDX; 521 media |= PHY_BMCR_SPEEDSEL; 522 media &= ~PHY_BMCR_DUPLEX; 523 printf("(half-duplex, 100Mbps)\n"); 524 } else if (advert & PHY_ANAR_10BTFULL && 525 ability & PHY_ANAR_10BTFULL) { 526 ifm->ifm_media = IFM_ETHER | IFM_10_T | IFM_FDX; 527 media &= ~PHY_BMCR_SPEEDSEL; 528 media |= PHY_BMCR_DUPLEX; 529 printf("(full-duplex, 10Mbps)\n"); 530 } else if (advert) { 531 ifm->ifm_media = IFM_ETHER | IFM_10_T | IFM_HDX; 532 media &= ~PHY_BMCR_SPEEDSEL; 533 media &= ~PHY_BMCR_DUPLEX; 534 printf("(half-duplex, 10Mbps)\n"); 535 } 536 media &= ~PHY_BMCR_AUTONEGENBL; 537 538 /* Set ASIC's duplex mode to match the PHY. */ 539 my_phy_writereg(sc, PHY_BMCR, media); 540 my_setcfg(sc, media); 541 } else { 542 if (verbose) 543 if_printf(ifp, "no carrier\n"); 544 } 545 546 my_init_locked(sc); 547 if (sc->my_tx_pend) { 548 sc->my_autoneg = 0; 549 sc->my_tx_pend = 0; 550 my_start_locked(ifp); 551 } 552 return; 553 } 554 555 /* 556 * To get PHY ability. 557 */ 558 static void 559 my_getmode_mii(struct my_softc * sc) 560 { 561 u_int16_t bmsr; 562 struct ifnet *ifp; 563 564 MY_LOCK_ASSERT(sc); 565 ifp = sc->my_ifp; 566 bmsr = my_phy_readreg(sc, PHY_BMSR); 567 if (bootverbose) 568 if_printf(ifp, "PHY status word: %x\n", bmsr); 569 570 /* fallback */ 571 sc->ifmedia.ifm_media = IFM_ETHER | IFM_10_T | IFM_HDX; 572 573 if (bmsr & PHY_BMSR_10BTHALF) { 574 if (bootverbose) 575 if_printf(ifp, "10Mbps half-duplex mode supported\n"); 576 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_10_T | IFM_HDX, 577 0, NULL); 578 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_10_T, 0, NULL); 579 } 580 if (bmsr & PHY_BMSR_10BTFULL) { 581 if (bootverbose) 582 if_printf(ifp, "10Mbps full-duplex mode supported\n"); 583 584 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_10_T | IFM_FDX, 585 0, NULL); 586 sc->ifmedia.ifm_media = IFM_ETHER | IFM_10_T | IFM_FDX; 587 } 588 if (bmsr & PHY_BMSR_100BTXHALF) { 589 if (bootverbose) 590 if_printf(ifp, "100Mbps half-duplex mode supported\n"); 591 ifp->if_baudrate = 100000000; 592 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_TX, 0, NULL); 593 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_TX | IFM_HDX, 594 0, NULL); 595 sc->ifmedia.ifm_media = IFM_ETHER | IFM_100_TX | IFM_HDX; 596 } 597 if (bmsr & PHY_BMSR_100BTXFULL) { 598 if (bootverbose) 599 if_printf(ifp, "100Mbps full-duplex mode supported\n"); 600 ifp->if_baudrate = 100000000; 601 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_TX | IFM_FDX, 602 0, NULL); 603 sc->ifmedia.ifm_media = IFM_ETHER | IFM_100_TX | IFM_FDX; 604 } 605 /* Some also support 100BaseT4. */ 606 if (bmsr & PHY_BMSR_100BT4) { 607 if (bootverbose) 608 if_printf(ifp, "100baseT4 mode supported\n"); 609 ifp->if_baudrate = 100000000; 610 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_T4, 0, NULL); 611 sc->ifmedia.ifm_media = IFM_ETHER | IFM_100_T4; 612 #ifdef FORCE_AUTONEG_TFOUR 613 if (bootverbose) 614 if_printf(ifp, "forcing on autoneg support for BT4\n"); 615 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_AUTO, 0 NULL): 616 sc->ifmedia.ifm_media = IFM_ETHER | IFM_AUTO; 617 #endif 618 } 619 #if 0 /* this version did not support 1000M, */ 620 if (sc->my_pinfo->my_vid == MarvellPHYID0) { 621 if (bootverbose) 622 if_printf(ifp, "1000Mbps half-duplex mode supported\n"); 623 624 ifp->if_baudrate = 1000000000; 625 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_T, 0, NULL); 626 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_T | IFM_HDX, 627 0, NULL); 628 if (bootverbose) 629 if_printf(ifp, "1000Mbps full-duplex mode supported\n"); 630 ifp->if_baudrate = 1000000000; 631 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_T | IFM_FDX, 632 0, NULL); 633 sc->ifmedia.ifm_media = IFM_ETHER | IFM_1000_T | IFM_FDX; 634 } 635 #endif 636 if (bmsr & PHY_BMSR_CANAUTONEG) { 637 if (bootverbose) 638 if_printf(ifp, "autoneg supported\n"); 639 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 640 sc->ifmedia.ifm_media = IFM_ETHER | IFM_AUTO; 641 } 642 return; 643 } 644 645 /* 646 * Set speed and duplex mode. 647 */ 648 static void 649 my_setmode_mii(struct my_softc * sc, int media) 650 { 651 u_int16_t bmcr; 652 struct ifnet *ifp; 653 654 MY_LOCK_ASSERT(sc); 655 ifp = sc->my_ifp; 656 /* 657 * If an autoneg session is in progress, stop it. 658 */ 659 if (sc->my_autoneg) { 660 if_printf(ifp, "canceling autoneg session\n"); 661 ifp->if_timer = sc->my_autoneg = sc->my_want_auto = 0; 662 bmcr = my_phy_readreg(sc, PHY_BMCR); 663 bmcr &= ~PHY_BMCR_AUTONEGENBL; 664 my_phy_writereg(sc, PHY_BMCR, bmcr); 665 } 666 if_printf(ifp, "selecting MII, "); 667 bmcr = my_phy_readreg(sc, PHY_BMCR); 668 bmcr &= ~(PHY_BMCR_AUTONEGENBL | PHY_BMCR_SPEEDSEL | PHY_BMCR_1000 | 669 PHY_BMCR_DUPLEX | PHY_BMCR_LOOPBK); 670 671 #if 0 /* this version did not support 1000M, */ 672 if (IFM_SUBTYPE(media) == IFM_1000_T) { 673 printf("1000Mbps/T4, half-duplex\n"); 674 bmcr &= ~PHY_BMCR_SPEEDSEL; 675 bmcr &= ~PHY_BMCR_DUPLEX; 676 bmcr |= PHY_BMCR_1000; 677 } 678 #endif 679 if (IFM_SUBTYPE(media) == IFM_100_T4) { 680 printf("100Mbps/T4, half-duplex\n"); 681 bmcr |= PHY_BMCR_SPEEDSEL; 682 bmcr &= ~PHY_BMCR_DUPLEX; 683 } 684 if (IFM_SUBTYPE(media) == IFM_100_TX) { 685 printf("100Mbps, "); 686 bmcr |= PHY_BMCR_SPEEDSEL; 687 } 688 if (IFM_SUBTYPE(media) == IFM_10_T) { 689 printf("10Mbps, "); 690 bmcr &= ~PHY_BMCR_SPEEDSEL; 691 } 692 if ((media & IFM_GMASK) == IFM_FDX) { 693 printf("full duplex\n"); 694 bmcr |= PHY_BMCR_DUPLEX; 695 } else { 696 printf("half duplex\n"); 697 bmcr &= ~PHY_BMCR_DUPLEX; 698 } 699 my_phy_writereg(sc, PHY_BMCR, bmcr); 700 my_setcfg(sc, bmcr); 701 return; 702 } 703 704 /* 705 * The Myson manual states that in order to fiddle with the 'full-duplex' and 706 * '100Mbps' bits in the netconfig register, we first have to put the 707 * transmit and/or receive logic in the idle state. 708 */ 709 static void 710 my_setcfg(struct my_softc * sc, int bmcr) 711 { 712 int i, restart = 0; 713 714 MY_LOCK_ASSERT(sc); 715 if (CSR_READ_4(sc, MY_TCRRCR) & (MY_TE | MY_RE)) { 716 restart = 1; 717 MY_CLRBIT(sc, MY_TCRRCR, (MY_TE | MY_RE)); 718 for (i = 0; i < MY_TIMEOUT; i++) { 719 DELAY(10); 720 if (!(CSR_READ_4(sc, MY_TCRRCR) & 721 (MY_TXRUN | MY_RXRUN))) 722 break; 723 } 724 if (i == MY_TIMEOUT) 725 if_printf(sc->my_ifp, 726 "failed to force tx and rx to idle \n"); 727 } 728 MY_CLRBIT(sc, MY_TCRRCR, MY_PS1000); 729 MY_CLRBIT(sc, MY_TCRRCR, MY_PS10); 730 if (bmcr & PHY_BMCR_1000) 731 MY_SETBIT(sc, MY_TCRRCR, MY_PS1000); 732 else if (!(bmcr & PHY_BMCR_SPEEDSEL)) 733 MY_SETBIT(sc, MY_TCRRCR, MY_PS10); 734 if (bmcr & PHY_BMCR_DUPLEX) 735 MY_SETBIT(sc, MY_TCRRCR, MY_FD); 736 else 737 MY_CLRBIT(sc, MY_TCRRCR, MY_FD); 738 if (restart) 739 MY_SETBIT(sc, MY_TCRRCR, MY_TE | MY_RE); 740 return; 741 } 742 743 static void 744 my_reset(struct my_softc * sc) 745 { 746 register int i; 747 748 MY_LOCK_ASSERT(sc); 749 MY_SETBIT(sc, MY_BCR, MY_SWR); 750 for (i = 0; i < MY_TIMEOUT; i++) { 751 DELAY(10); 752 if (!(CSR_READ_4(sc, MY_BCR) & MY_SWR)) 753 break; 754 } 755 if (i == MY_TIMEOUT) 756 if_printf(sc->my_ifp, "reset never completed!\n"); 757 758 /* Wait a little while for the chip to get its brains in order. */ 759 DELAY(1000); 760 return; 761 } 762 763 /* 764 * Probe for a Myson chip. Check the PCI vendor and device IDs against our 765 * list and return a device name if we find a match. 766 */ 767 static int 768 my_probe(device_t dev) 769 { 770 struct my_type *t; 771 772 t = my_devs; 773 while (t->my_name != NULL) { 774 if ((pci_get_vendor(dev) == t->my_vid) && 775 (pci_get_device(dev) == t->my_did)) { 776 device_set_desc(dev, t->my_name); 777 my_info_tmp = t; 778 return (BUS_PROBE_DEFAULT); 779 } 780 t++; 781 } 782 return (ENXIO); 783 } 784 785 /* 786 * Attach the interface. Allocate softc structures, do ifmedia setup and 787 * ethernet/BPF attach. 788 */ 789 static int 790 my_attach(device_t dev) 791 { 792 int i; 793 u_char eaddr[ETHER_ADDR_LEN]; 794 u_int32_t iobase; 795 struct my_softc *sc; 796 struct ifnet *ifp; 797 int media = IFM_ETHER | IFM_100_TX | IFM_FDX; 798 unsigned int round; 799 caddr_t roundptr; 800 struct my_type *p; 801 u_int16_t phy_vid, phy_did, phy_sts = 0; 802 int rid, error = 0; 803 804 sc = device_get_softc(dev); 805 mtx_init(&sc->my_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 806 MTX_DEF); 807 808 /* 809 * Map control/status registers. 810 */ 811 pci_enable_busmaster(dev); 812 813 if (my_info_tmp->my_did == MTD800ID) { 814 iobase = pci_read_config(dev, MY_PCI_LOIO, 4); 815 if (iobase & 0x300) 816 MY_USEIOSPACE = 0; 817 } 818 819 rid = MY_RID; 820 sc->my_res = bus_alloc_resource_any(dev, MY_RES, &rid, RF_ACTIVE); 821 822 if (sc->my_res == NULL) { 823 device_printf(dev, "couldn't map ports/memory\n"); 824 error = ENXIO; 825 goto destroy_mutex; 826 } 827 sc->my_btag = rman_get_bustag(sc->my_res); 828 sc->my_bhandle = rman_get_bushandle(sc->my_res); 829 830 rid = 0; 831 sc->my_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 832 RF_SHAREABLE | RF_ACTIVE); 833 834 if (sc->my_irq == NULL) { 835 device_printf(dev, "couldn't map interrupt\n"); 836 error = ENXIO; 837 goto release_io; 838 } 839 840 sc->my_info = my_info_tmp; 841 842 /* Reset the adapter. */ 843 MY_LOCK(sc); 844 my_reset(sc); 845 MY_UNLOCK(sc); 846 847 /* 848 * Get station address 849 */ 850 for (i = 0; i < ETHER_ADDR_LEN; ++i) 851 eaddr[i] = CSR_READ_1(sc, MY_PAR0 + i); 852 853 sc->my_ldata_ptr = malloc(sizeof(struct my_list_data) + 8, 854 M_DEVBUF, M_NOWAIT); 855 if (sc->my_ldata_ptr == NULL) { 856 device_printf(dev, "no memory for list buffers!\n"); 857 error = ENXIO; 858 goto release_irq; 859 } 860 sc->my_ldata = (struct my_list_data *) sc->my_ldata_ptr; 861 round = (uintptr_t)sc->my_ldata_ptr & 0xF; 862 roundptr = sc->my_ldata_ptr; 863 for (i = 0; i < 8; i++) { 864 if (round % 8) { 865 round++; 866 roundptr++; 867 } else 868 break; 869 } 870 sc->my_ldata = (struct my_list_data *) roundptr; 871 bzero(sc->my_ldata, sizeof(struct my_list_data)); 872 873 ifp = sc->my_ifp = if_alloc(IFT_ETHER); 874 if (ifp == NULL) { 875 device_printf(dev, "can not if_alloc()\n"); 876 error = ENOSPC; 877 goto free_ldata; 878 } 879 ifp->if_softc = sc; 880 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 881 ifp->if_mtu = ETHERMTU; 882 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 883 ifp->if_ioctl = my_ioctl; 884 ifp->if_start = my_start; 885 ifp->if_watchdog = my_watchdog; 886 ifp->if_init = my_init; 887 ifp->if_baudrate = 10000000; 888 ifp->if_snd.ifq_maxlen = IFQ_MAXLEN; 889 890 if (sc->my_info->my_did == MTD803ID) 891 sc->my_pinfo = my_phys; 892 else { 893 if (bootverbose) 894 device_printf(dev, "probing for a PHY\n"); 895 MY_LOCK(sc); 896 for (i = MY_PHYADDR_MIN; i < MY_PHYADDR_MAX + 1; i++) { 897 if (bootverbose) 898 device_printf(dev, "checking address: %d\n", i); 899 sc->my_phy_addr = i; 900 phy_sts = my_phy_readreg(sc, PHY_BMSR); 901 if ((phy_sts != 0) && (phy_sts != 0xffff)) 902 break; 903 else 904 phy_sts = 0; 905 } 906 if (phy_sts) { 907 phy_vid = my_phy_readreg(sc, PHY_VENID); 908 phy_did = my_phy_readreg(sc, PHY_DEVID); 909 if (bootverbose) { 910 device_printf(dev, "found PHY at address %d, ", 911 sc->my_phy_addr); 912 printf("vendor id: %x device id: %x\n", 913 phy_vid, phy_did); 914 } 915 p = my_phys; 916 while (p->my_vid) { 917 if (phy_vid == p->my_vid) { 918 sc->my_pinfo = p; 919 break; 920 } 921 p++; 922 } 923 if (sc->my_pinfo == NULL) 924 sc->my_pinfo = &my_phys[PHY_UNKNOWN]; 925 if (bootverbose) 926 device_printf(dev, "PHY type: %s\n", 927 sc->my_pinfo->my_name); 928 } else { 929 MY_UNLOCK(sc); 930 device_printf(dev, "MII without any phy!\n"); 931 error = ENXIO; 932 goto free_if; 933 } 934 MY_UNLOCK(sc); 935 } 936 937 /* Do ifmedia setup. */ 938 ifmedia_init(&sc->ifmedia, 0, my_ifmedia_upd, my_ifmedia_sts); 939 MY_LOCK(sc); 940 my_getmode_mii(sc); 941 my_autoneg_mii(sc, MY_FLAG_FORCEDELAY, 1); 942 media = sc->ifmedia.ifm_media; 943 my_stop(sc); 944 MY_UNLOCK(sc); 945 ifmedia_set(&sc->ifmedia, media); 946 947 ether_ifattach(ifp, eaddr); 948 949 error = bus_setup_intr(dev, sc->my_irq, INTR_TYPE_NET | INTR_MPSAFE, 950 my_intr, sc, &sc->my_intrhand); 951 952 if (error) { 953 device_printf(dev, "couldn't set up irq\n"); 954 goto detach_if; 955 } 956 957 return (0); 958 959 detach_if: 960 ether_ifdetach(ifp); 961 free_if: 962 if_free(ifp); 963 free_ldata: 964 free(sc->my_ldata_ptr, M_DEVBUF); 965 release_irq: 966 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->my_irq); 967 release_io: 968 bus_release_resource(dev, MY_RES, MY_RID, sc->my_res); 969 destroy_mutex: 970 mtx_destroy(&sc->my_mtx); 971 return (error); 972 } 973 974 static int 975 my_detach(device_t dev) 976 { 977 struct my_softc *sc; 978 struct ifnet *ifp; 979 980 sc = device_get_softc(dev); 981 MY_LOCK(sc); 982 my_stop(sc); 983 MY_UNLOCK(sc); 984 bus_teardown_intr(dev, sc->my_irq, sc->my_intrhand); 985 986 ifp = sc->my_ifp; 987 ether_ifdetach(ifp); 988 if_free(ifp); 989 free(sc->my_ldata_ptr, M_DEVBUF); 990 991 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->my_irq); 992 bus_release_resource(dev, MY_RES, MY_RID, sc->my_res); 993 mtx_destroy(&sc->my_mtx); 994 return (0); 995 } 996 997 998 /* 999 * Initialize the transmit descriptors. 1000 */ 1001 static int 1002 my_list_tx_init(struct my_softc * sc) 1003 { 1004 struct my_chain_data *cd; 1005 struct my_list_data *ld; 1006 int i; 1007 1008 MY_LOCK_ASSERT(sc); 1009 cd = &sc->my_cdata; 1010 ld = sc->my_ldata; 1011 for (i = 0; i < MY_TX_LIST_CNT; i++) { 1012 cd->my_tx_chain[i].my_ptr = &ld->my_tx_list[i]; 1013 if (i == (MY_TX_LIST_CNT - 1)) 1014 cd->my_tx_chain[i].my_nextdesc = &cd->my_tx_chain[0]; 1015 else 1016 cd->my_tx_chain[i].my_nextdesc = 1017 &cd->my_tx_chain[i + 1]; 1018 } 1019 cd->my_tx_free = &cd->my_tx_chain[0]; 1020 cd->my_tx_tail = cd->my_tx_head = NULL; 1021 return (0); 1022 } 1023 1024 /* 1025 * Initialize the RX descriptors and allocate mbufs for them. Note that we 1026 * arrange the descriptors in a closed ring, so that the last descriptor 1027 * points back to the first. 1028 */ 1029 static int 1030 my_list_rx_init(struct my_softc * sc) 1031 { 1032 struct my_chain_data *cd; 1033 struct my_list_data *ld; 1034 int i; 1035 1036 MY_LOCK_ASSERT(sc); 1037 cd = &sc->my_cdata; 1038 ld = sc->my_ldata; 1039 for (i = 0; i < MY_RX_LIST_CNT; i++) { 1040 cd->my_rx_chain[i].my_ptr = 1041 (struct my_desc *) & ld->my_rx_list[i]; 1042 if (my_newbuf(sc, &cd->my_rx_chain[i]) == ENOBUFS) { 1043 MY_UNLOCK(sc); 1044 return (ENOBUFS); 1045 } 1046 if (i == (MY_RX_LIST_CNT - 1)) { 1047 cd->my_rx_chain[i].my_nextdesc = &cd->my_rx_chain[0]; 1048 ld->my_rx_list[i].my_next = vtophys(&ld->my_rx_list[0]); 1049 } else { 1050 cd->my_rx_chain[i].my_nextdesc = 1051 &cd->my_rx_chain[i + 1]; 1052 ld->my_rx_list[i].my_next = 1053 vtophys(&ld->my_rx_list[i + 1]); 1054 } 1055 } 1056 cd->my_rx_head = &cd->my_rx_chain[0]; 1057 return (0); 1058 } 1059 1060 /* 1061 * Initialize an RX descriptor and attach an MBUF cluster. 1062 */ 1063 static int 1064 my_newbuf(struct my_softc * sc, struct my_chain_onefrag * c) 1065 { 1066 struct mbuf *m_new = NULL; 1067 1068 MY_LOCK_ASSERT(sc); 1069 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1070 if (m_new == NULL) { 1071 if_printf(sc->my_ifp, 1072 "no memory for rx list -- packet dropped!\n"); 1073 return (ENOBUFS); 1074 } 1075 MCLGET(m_new, M_DONTWAIT); 1076 if (!(m_new->m_flags & M_EXT)) { 1077 if_printf(sc->my_ifp, 1078 "no memory for rx list -- packet dropped!\n"); 1079 m_freem(m_new); 1080 return (ENOBUFS); 1081 } 1082 c->my_mbuf = m_new; 1083 c->my_ptr->my_data = vtophys(mtod(m_new, caddr_t)); 1084 c->my_ptr->my_ctl = (MCLBYTES - 1) << MY_RBSShift; 1085 c->my_ptr->my_status = MY_OWNByNIC; 1086 return (0); 1087 } 1088 1089 /* 1090 * A frame has been uploaded: pass the resulting mbuf chain up to the higher 1091 * level protocols. 1092 */ 1093 static void 1094 my_rxeof(struct my_softc * sc) 1095 { 1096 struct ether_header *eh; 1097 struct mbuf *m; 1098 struct ifnet *ifp; 1099 struct my_chain_onefrag *cur_rx; 1100 int total_len = 0; 1101 u_int32_t rxstat; 1102 1103 MY_LOCK_ASSERT(sc); 1104 ifp = sc->my_ifp; 1105 while (!((rxstat = sc->my_cdata.my_rx_head->my_ptr->my_status) 1106 & MY_OWNByNIC)) { 1107 cur_rx = sc->my_cdata.my_rx_head; 1108 sc->my_cdata.my_rx_head = cur_rx->my_nextdesc; 1109 1110 if (rxstat & MY_ES) { /* error summary: give up this rx pkt */ 1111 ifp->if_ierrors++; 1112 cur_rx->my_ptr->my_status = MY_OWNByNIC; 1113 continue; 1114 } 1115 /* No errors; receive the packet. */ 1116 total_len = (rxstat & MY_FLNGMASK) >> MY_FLNGShift; 1117 total_len -= ETHER_CRC_LEN; 1118 1119 if (total_len < MINCLSIZE) { 1120 m = m_devget(mtod(cur_rx->my_mbuf, char *), 1121 total_len, 0, ifp, NULL); 1122 cur_rx->my_ptr->my_status = MY_OWNByNIC; 1123 if (m == NULL) { 1124 ifp->if_ierrors++; 1125 continue; 1126 } 1127 } else { 1128 m = cur_rx->my_mbuf; 1129 /* 1130 * Try to conjure up a new mbuf cluster. If that 1131 * fails, it means we have an out of memory condition 1132 * and should leave the buffer in place and continue. 1133 * This will result in a lost packet, but there's 1134 * little else we can do in this situation. 1135 */ 1136 if (my_newbuf(sc, cur_rx) == ENOBUFS) { 1137 ifp->if_ierrors++; 1138 cur_rx->my_ptr->my_status = MY_OWNByNIC; 1139 continue; 1140 } 1141 m->m_pkthdr.rcvif = ifp; 1142 m->m_pkthdr.len = m->m_len = total_len; 1143 } 1144 ifp->if_ipackets++; 1145 eh = mtod(m, struct ether_header *); 1146 #if NBPFILTER > 0 1147 /* 1148 * Handle BPF listeners. Let the BPF user see the packet, but 1149 * don't pass it up to the ether_input() layer unless it's a 1150 * broadcast packet, multicast packet, matches our ethernet 1151 * address or the interface is in promiscuous mode. 1152 */ 1153 if (ifp->if_bpf) { 1154 BPF_MTAP(ifp, m); 1155 if (ifp->if_flags & IFF_PROMISC && 1156 (bcmp(eh->ether_dhost, IF_LLADDR(sc->my_ifp), 1157 ETHER_ADDR_LEN) && 1158 (eh->ether_dhost[0] & 1) == 0)) { 1159 m_freem(m); 1160 continue; 1161 } 1162 } 1163 #endif 1164 MY_UNLOCK(sc); 1165 (*ifp->if_input)(ifp, m); 1166 MY_LOCK(sc); 1167 } 1168 return; 1169 } 1170 1171 1172 /* 1173 * A frame was downloaded to the chip. It's safe for us to clean up the list 1174 * buffers. 1175 */ 1176 static void 1177 my_txeof(struct my_softc * sc) 1178 { 1179 struct my_chain *cur_tx; 1180 struct ifnet *ifp; 1181 1182 MY_LOCK_ASSERT(sc); 1183 ifp = sc->my_ifp; 1184 /* Clear the timeout timer. */ 1185 ifp->if_timer = 0; 1186 if (sc->my_cdata.my_tx_head == NULL) { 1187 return; 1188 } 1189 /* 1190 * Go through our tx list and free mbufs for those frames that have 1191 * been transmitted. 1192 */ 1193 while (sc->my_cdata.my_tx_head->my_mbuf != NULL) { 1194 u_int32_t txstat; 1195 1196 cur_tx = sc->my_cdata.my_tx_head; 1197 txstat = MY_TXSTATUS(cur_tx); 1198 if ((txstat & MY_OWNByNIC) || txstat == MY_UNSENT) 1199 break; 1200 if (!(CSR_READ_4(sc, MY_TCRRCR) & MY_Enhanced)) { 1201 if (txstat & MY_TXERR) { 1202 ifp->if_oerrors++; 1203 if (txstat & MY_EC) /* excessive collision */ 1204 ifp->if_collisions++; 1205 if (txstat & MY_LC) /* late collision */ 1206 ifp->if_collisions++; 1207 } 1208 ifp->if_collisions += (txstat & MY_NCRMASK) >> 1209 MY_NCRShift; 1210 } 1211 ifp->if_opackets++; 1212 m_freem(cur_tx->my_mbuf); 1213 cur_tx->my_mbuf = NULL; 1214 if (sc->my_cdata.my_tx_head == sc->my_cdata.my_tx_tail) { 1215 sc->my_cdata.my_tx_head = NULL; 1216 sc->my_cdata.my_tx_tail = NULL; 1217 break; 1218 } 1219 sc->my_cdata.my_tx_head = cur_tx->my_nextdesc; 1220 } 1221 if (CSR_READ_4(sc, MY_TCRRCR) & MY_Enhanced) { 1222 ifp->if_collisions += (CSR_READ_4(sc, MY_TSR) & MY_NCRMask); 1223 } 1224 return; 1225 } 1226 1227 /* 1228 * TX 'end of channel' interrupt handler. 1229 */ 1230 static void 1231 my_txeoc(struct my_softc * sc) 1232 { 1233 struct ifnet *ifp; 1234 1235 MY_LOCK_ASSERT(sc); 1236 ifp = sc->my_ifp; 1237 ifp->if_timer = 0; 1238 if (sc->my_cdata.my_tx_head == NULL) { 1239 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1240 sc->my_cdata.my_tx_tail = NULL; 1241 if (sc->my_want_auto) 1242 my_autoneg_mii(sc, MY_FLAG_SCHEDDELAY, 1); 1243 } else { 1244 if (MY_TXOWN(sc->my_cdata.my_tx_head) == MY_UNSENT) { 1245 MY_TXOWN(sc->my_cdata.my_tx_head) = MY_OWNByNIC; 1246 ifp->if_timer = 5; 1247 CSR_WRITE_4(sc, MY_TXPDR, 0xFFFFFFFF); 1248 } 1249 } 1250 return; 1251 } 1252 1253 static void 1254 my_intr(void *arg) 1255 { 1256 struct my_softc *sc; 1257 struct ifnet *ifp; 1258 u_int32_t status; 1259 1260 sc = arg; 1261 MY_LOCK(sc); 1262 ifp = sc->my_ifp; 1263 if (!(ifp->if_flags & IFF_UP)) { 1264 MY_UNLOCK(sc); 1265 return; 1266 } 1267 /* Disable interrupts. */ 1268 CSR_WRITE_4(sc, MY_IMR, 0x00000000); 1269 1270 for (;;) { 1271 status = CSR_READ_4(sc, MY_ISR); 1272 status &= MY_INTRS; 1273 if (status) 1274 CSR_WRITE_4(sc, MY_ISR, status); 1275 else 1276 break; 1277 1278 if (status & MY_RI) /* receive interrupt */ 1279 my_rxeof(sc); 1280 1281 if ((status & MY_RBU) || (status & MY_RxErr)) { 1282 /* rx buffer unavailable or rx error */ 1283 ifp->if_ierrors++; 1284 #ifdef foo 1285 my_stop(sc); 1286 my_reset(sc); 1287 my_init_locked(sc); 1288 #endif 1289 } 1290 if (status & MY_TI) /* tx interrupt */ 1291 my_txeof(sc); 1292 if (status & MY_ETI) /* tx early interrupt */ 1293 my_txeof(sc); 1294 if (status & MY_TBU) /* tx buffer unavailable */ 1295 my_txeoc(sc); 1296 1297 #if 0 /* 90/1/18 delete */ 1298 if (status & MY_FBE) { 1299 my_reset(sc); 1300 my_init_locked(sc); 1301 } 1302 #endif 1303 1304 } 1305 1306 /* Re-enable interrupts. */ 1307 CSR_WRITE_4(sc, MY_IMR, MY_INTRS); 1308 if (ifp->if_snd.ifq_head != NULL) 1309 my_start_locked(ifp); 1310 MY_UNLOCK(sc); 1311 return; 1312 } 1313 1314 /* 1315 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1316 * pointers to the fragment pointers. 1317 */ 1318 static int 1319 my_encap(struct my_softc * sc, struct my_chain * c, struct mbuf * m_head) 1320 { 1321 struct my_desc *f = NULL; 1322 int total_len; 1323 struct mbuf *m, *m_new = NULL; 1324 1325 MY_LOCK_ASSERT(sc); 1326 /* calculate the total tx pkt length */ 1327 total_len = 0; 1328 for (m = m_head; m != NULL; m = m->m_next) 1329 total_len += m->m_len; 1330 /* 1331 * Start packing the mbufs in this chain into the fragment pointers. 1332 * Stop when we run out of fragments or hit the end of the mbuf 1333 * chain. 1334 */ 1335 m = m_head; 1336 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1337 if (m_new == NULL) { 1338 if_printf(sc->my_ifp, "no memory for tx list"); 1339 return (1); 1340 } 1341 if (m_head->m_pkthdr.len > MHLEN) { 1342 MCLGET(m_new, M_DONTWAIT); 1343 if (!(m_new->m_flags & M_EXT)) { 1344 m_freem(m_new); 1345 if_printf(sc->my_ifp, "no memory for tx list"); 1346 return (1); 1347 } 1348 } 1349 m_copydata(m_head, 0, m_head->m_pkthdr.len, mtod(m_new, caddr_t)); 1350 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1351 m_freem(m_head); 1352 m_head = m_new; 1353 f = &c->my_ptr->my_frag[0]; 1354 f->my_status = 0; 1355 f->my_data = vtophys(mtod(m_new, caddr_t)); 1356 total_len = m_new->m_len; 1357 f->my_ctl = MY_TXFD | MY_TXLD | MY_CRCEnable | MY_PADEnable; 1358 f->my_ctl |= total_len << MY_PKTShift; /* pkt size */ 1359 f->my_ctl |= total_len; /* buffer size */ 1360 /* 89/12/29 add, for mtd891 *//* [ 89? ] */ 1361 if (sc->my_info->my_did == MTD891ID) 1362 f->my_ctl |= MY_ETIControl | MY_RetryTxLC; 1363 c->my_mbuf = m_head; 1364 c->my_lastdesc = 0; 1365 MY_TXNEXT(c) = vtophys(&c->my_nextdesc->my_ptr->my_frag[0]); 1366 return (0); 1367 } 1368 1369 /* 1370 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1371 * to the mbuf data regions directly in the transmit lists. We also save a 1372 * copy of the pointers since the transmit list fragment pointers are 1373 * physical addresses. 1374 */ 1375 static void 1376 my_start(struct ifnet * ifp) 1377 { 1378 struct my_softc *sc; 1379 1380 sc = ifp->if_softc; 1381 MY_LOCK(sc); 1382 my_start_locked(ifp); 1383 MY_UNLOCK(sc); 1384 } 1385 1386 static void 1387 my_start_locked(struct ifnet * ifp) 1388 { 1389 struct my_softc *sc; 1390 struct mbuf *m_head = NULL; 1391 struct my_chain *cur_tx = NULL, *start_tx; 1392 1393 sc = ifp->if_softc; 1394 MY_LOCK_ASSERT(sc); 1395 if (sc->my_autoneg) { 1396 sc->my_tx_pend = 1; 1397 return; 1398 } 1399 /* 1400 * Check for an available queue slot. If there are none, punt. 1401 */ 1402 if (sc->my_cdata.my_tx_free->my_mbuf != NULL) { 1403 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1404 return; 1405 } 1406 start_tx = sc->my_cdata.my_tx_free; 1407 while (sc->my_cdata.my_tx_free->my_mbuf == NULL) { 1408 IF_DEQUEUE(&ifp->if_snd, m_head); 1409 if (m_head == NULL) 1410 break; 1411 1412 /* Pick a descriptor off the free list. */ 1413 cur_tx = sc->my_cdata.my_tx_free; 1414 sc->my_cdata.my_tx_free = cur_tx->my_nextdesc; 1415 1416 /* Pack the data into the descriptor. */ 1417 my_encap(sc, cur_tx, m_head); 1418 1419 if (cur_tx != start_tx) 1420 MY_TXOWN(cur_tx) = MY_OWNByNIC; 1421 #if NBPFILTER > 0 1422 /* 1423 * If there's a BPF listener, bounce a copy of this frame to 1424 * him. 1425 */ 1426 BPF_MTAP(ifp, cur_tx->my_mbuf); 1427 #endif 1428 } 1429 /* 1430 * If there are no packets queued, bail. 1431 */ 1432 if (cur_tx == NULL) { 1433 return; 1434 } 1435 /* 1436 * Place the request for the upload interrupt in the last descriptor 1437 * in the chain. This way, if we're chaining several packets at once, 1438 * we'll only get an interupt once for the whole chain rather than 1439 * once for each packet. 1440 */ 1441 MY_TXCTL(cur_tx) |= MY_TXIC; 1442 cur_tx->my_ptr->my_frag[0].my_ctl |= MY_TXIC; 1443 sc->my_cdata.my_tx_tail = cur_tx; 1444 if (sc->my_cdata.my_tx_head == NULL) 1445 sc->my_cdata.my_tx_head = start_tx; 1446 MY_TXOWN(start_tx) = MY_OWNByNIC; 1447 CSR_WRITE_4(sc, MY_TXPDR, 0xFFFFFFFF); /* tx polling demand */ 1448 1449 /* 1450 * Set a timeout in case the chip goes out to lunch. 1451 */ 1452 ifp->if_timer = 5; 1453 return; 1454 } 1455 1456 static void 1457 my_init(void *xsc) 1458 { 1459 struct my_softc *sc = xsc; 1460 1461 MY_LOCK(sc); 1462 my_init_locked(sc); 1463 MY_UNLOCK(sc); 1464 } 1465 1466 static void 1467 my_init_locked(struct my_softc *sc) 1468 { 1469 struct ifnet *ifp = sc->my_ifp; 1470 u_int16_t phy_bmcr = 0; 1471 1472 MY_LOCK_ASSERT(sc); 1473 if (sc->my_autoneg) { 1474 return; 1475 } 1476 if (sc->my_pinfo != NULL) 1477 phy_bmcr = my_phy_readreg(sc, PHY_BMCR); 1478 /* 1479 * Cancel pending I/O and free all RX/TX buffers. 1480 */ 1481 my_stop(sc); 1482 my_reset(sc); 1483 1484 /* 1485 * Set cache alignment and burst length. 1486 */ 1487 #if 0 /* 89/9/1 modify, */ 1488 CSR_WRITE_4(sc, MY_BCR, MY_RPBLE512); 1489 CSR_WRITE_4(sc, MY_TCRRCR, MY_TFTSF); 1490 #endif 1491 CSR_WRITE_4(sc, MY_BCR, MY_PBL8); 1492 CSR_WRITE_4(sc, MY_TCRRCR, MY_TFTSF | MY_RBLEN | MY_RPBLE512); 1493 /* 1494 * 89/12/29 add, for mtd891, 1495 */ 1496 if (sc->my_info->my_did == MTD891ID) { 1497 MY_SETBIT(sc, MY_BCR, MY_PROG); 1498 MY_SETBIT(sc, MY_TCRRCR, MY_Enhanced); 1499 } 1500 my_setcfg(sc, phy_bmcr); 1501 /* Init circular RX list. */ 1502 if (my_list_rx_init(sc) == ENOBUFS) { 1503 if_printf(ifp, "init failed: no memory for rx buffers\n"); 1504 my_stop(sc); 1505 return; 1506 } 1507 /* Init TX descriptors. */ 1508 my_list_tx_init(sc); 1509 1510 /* If we want promiscuous mode, set the allframes bit. */ 1511 if (ifp->if_flags & IFF_PROMISC) 1512 MY_SETBIT(sc, MY_TCRRCR, MY_PROM); 1513 else 1514 MY_CLRBIT(sc, MY_TCRRCR, MY_PROM); 1515 1516 /* 1517 * Set capture broadcast bit to capture broadcast frames. 1518 */ 1519 if (ifp->if_flags & IFF_BROADCAST) 1520 MY_SETBIT(sc, MY_TCRRCR, MY_AB); 1521 else 1522 MY_CLRBIT(sc, MY_TCRRCR, MY_AB); 1523 1524 /* 1525 * Program the multicast filter, if necessary. 1526 */ 1527 my_setmulti(sc); 1528 1529 /* 1530 * Load the address of the RX list. 1531 */ 1532 MY_CLRBIT(sc, MY_TCRRCR, MY_RE); 1533 CSR_WRITE_4(sc, MY_RXLBA, vtophys(&sc->my_ldata->my_rx_list[0])); 1534 1535 /* 1536 * Enable interrupts. 1537 */ 1538 CSR_WRITE_4(sc, MY_IMR, MY_INTRS); 1539 CSR_WRITE_4(sc, MY_ISR, 0xFFFFFFFF); 1540 1541 /* Enable receiver and transmitter. */ 1542 MY_SETBIT(sc, MY_TCRRCR, MY_RE); 1543 MY_CLRBIT(sc, MY_TCRRCR, MY_TE); 1544 CSR_WRITE_4(sc, MY_TXLBA, vtophys(&sc->my_ldata->my_tx_list[0])); 1545 MY_SETBIT(sc, MY_TCRRCR, MY_TE); 1546 1547 /* Restore state of BMCR */ 1548 if (sc->my_pinfo != NULL) 1549 my_phy_writereg(sc, PHY_BMCR, phy_bmcr); 1550 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1551 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1552 return; 1553 } 1554 1555 /* 1556 * Set media options. 1557 */ 1558 1559 static int 1560 my_ifmedia_upd(struct ifnet * ifp) 1561 { 1562 struct my_softc *sc; 1563 struct ifmedia *ifm; 1564 1565 sc = ifp->if_softc; 1566 MY_LOCK(sc); 1567 ifm = &sc->ifmedia; 1568 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) { 1569 MY_UNLOCK(sc); 1570 return (EINVAL); 1571 } 1572 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO) 1573 my_autoneg_mii(sc, MY_FLAG_SCHEDDELAY, 1); 1574 else 1575 my_setmode_mii(sc, ifm->ifm_media); 1576 MY_UNLOCK(sc); 1577 return (0); 1578 } 1579 1580 /* 1581 * Report current media status. 1582 */ 1583 1584 static void 1585 my_ifmedia_sts(struct ifnet * ifp, struct ifmediareq * ifmr) 1586 { 1587 struct my_softc *sc; 1588 u_int16_t advert = 0, ability = 0; 1589 1590 sc = ifp->if_softc; 1591 MY_LOCK(sc); 1592 ifmr->ifm_active = IFM_ETHER; 1593 if (!(my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_AUTONEGENBL)) { 1594 #if 0 /* this version did not support 1000M, */ 1595 if (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_1000) 1596 ifmr->ifm_active = IFM_ETHER | IFM_1000TX; 1597 #endif 1598 if (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_SPEEDSEL) 1599 ifmr->ifm_active = IFM_ETHER | IFM_100_TX; 1600 else 1601 ifmr->ifm_active = IFM_ETHER | IFM_10_T; 1602 if (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_DUPLEX) 1603 ifmr->ifm_active |= IFM_FDX; 1604 else 1605 ifmr->ifm_active |= IFM_HDX; 1606 1607 MY_UNLOCK(sc); 1608 return; 1609 } 1610 ability = my_phy_readreg(sc, PHY_LPAR); 1611 advert = my_phy_readreg(sc, PHY_ANAR); 1612 1613 #if 0 /* this version did not support 1000M, */ 1614 if (sc->my_pinfo->my_vid = MarvellPHYID0) { 1615 ability2 = my_phy_readreg(sc, PHY_1000SR); 1616 if (ability2 & PHY_1000SR_1000BTXFULL) { 1617 advert = 0; 1618 ability = 0; 1619 ifmr->ifm_active = IFM_ETHER|IFM_1000_T|IFM_FDX; 1620 } else if (ability & PHY_1000SR_1000BTXHALF) { 1621 advert = 0; 1622 ability = 0; 1623 ifmr->ifm_active = IFM_ETHER|IFM_1000_T|IFM_HDX; 1624 } 1625 } 1626 #endif 1627 if (advert & PHY_ANAR_100BT4 && ability & PHY_ANAR_100BT4) 1628 ifmr->ifm_active = IFM_ETHER | IFM_100_T4; 1629 else if (advert & PHY_ANAR_100BTXFULL && ability & PHY_ANAR_100BTXFULL) 1630 ifmr->ifm_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 1631 else if (advert & PHY_ANAR_100BTXHALF && ability & PHY_ANAR_100BTXHALF) 1632 ifmr->ifm_active = IFM_ETHER | IFM_100_TX | IFM_HDX; 1633 else if (advert & PHY_ANAR_10BTFULL && ability & PHY_ANAR_10BTFULL) 1634 ifmr->ifm_active = IFM_ETHER | IFM_10_T | IFM_FDX; 1635 else if (advert & PHY_ANAR_10BTHALF && ability & PHY_ANAR_10BTHALF) 1636 ifmr->ifm_active = IFM_ETHER | IFM_10_T | IFM_HDX; 1637 MY_UNLOCK(sc); 1638 return; 1639 } 1640 1641 static int 1642 my_ioctl(struct ifnet * ifp, u_long command, caddr_t data) 1643 { 1644 struct my_softc *sc = ifp->if_softc; 1645 struct ifreq *ifr = (struct ifreq *) data; 1646 int error; 1647 1648 switch (command) { 1649 case SIOCSIFFLAGS: 1650 MY_LOCK(sc); 1651 if (ifp->if_flags & IFF_UP) 1652 my_init_locked(sc); 1653 else if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1654 my_stop(sc); 1655 MY_UNLOCK(sc); 1656 error = 0; 1657 break; 1658 case SIOCADDMULTI: 1659 case SIOCDELMULTI: 1660 MY_LOCK(sc); 1661 my_setmulti(sc); 1662 MY_UNLOCK(sc); 1663 error = 0; 1664 break; 1665 case SIOCGIFMEDIA: 1666 case SIOCSIFMEDIA: 1667 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); 1668 break; 1669 default: 1670 error = ether_ioctl(ifp, command, data); 1671 break; 1672 } 1673 return (error); 1674 } 1675 1676 static void 1677 my_watchdog(struct ifnet * ifp) 1678 { 1679 struct my_softc *sc; 1680 1681 sc = ifp->if_softc; 1682 MY_LOCK(sc); 1683 if (sc->my_autoneg) { 1684 my_autoneg_mii(sc, MY_FLAG_DELAYTIMEO, 1); 1685 MY_UNLOCK(sc); 1686 return; 1687 } 1688 ifp->if_oerrors++; 1689 if_printf(ifp, "watchdog timeout\n"); 1690 if (!(my_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT)) 1691 if_printf(ifp, "no carrier - transceiver cable problem?\n"); 1692 my_stop(sc); 1693 my_reset(sc); 1694 my_init_locked(sc); 1695 if (ifp->if_snd.ifq_head != NULL) 1696 my_start_locked(ifp); 1697 MY_LOCK(sc); 1698 return; 1699 } 1700 1701 1702 /* 1703 * Stop the adapter and free any mbufs allocated to the RX and TX lists. 1704 */ 1705 static void 1706 my_stop(struct my_softc * sc) 1707 { 1708 register int i; 1709 struct ifnet *ifp; 1710 1711 MY_LOCK_ASSERT(sc); 1712 ifp = sc->my_ifp; 1713 ifp->if_timer = 0; 1714 1715 MY_CLRBIT(sc, MY_TCRRCR, (MY_RE | MY_TE)); 1716 CSR_WRITE_4(sc, MY_IMR, 0x00000000); 1717 CSR_WRITE_4(sc, MY_TXLBA, 0x00000000); 1718 CSR_WRITE_4(sc, MY_RXLBA, 0x00000000); 1719 1720 /* 1721 * Free data in the RX lists. 1722 */ 1723 for (i = 0; i < MY_RX_LIST_CNT; i++) { 1724 if (sc->my_cdata.my_rx_chain[i].my_mbuf != NULL) { 1725 m_freem(sc->my_cdata.my_rx_chain[i].my_mbuf); 1726 sc->my_cdata.my_rx_chain[i].my_mbuf = NULL; 1727 } 1728 } 1729 bzero((char *)&sc->my_ldata->my_rx_list, 1730 sizeof(sc->my_ldata->my_rx_list)); 1731 /* 1732 * Free the TX list buffers. 1733 */ 1734 for (i = 0; i < MY_TX_LIST_CNT; i++) { 1735 if (sc->my_cdata.my_tx_chain[i].my_mbuf != NULL) { 1736 m_freem(sc->my_cdata.my_tx_chain[i].my_mbuf); 1737 sc->my_cdata.my_tx_chain[i].my_mbuf = NULL; 1738 } 1739 } 1740 bzero((char *)&sc->my_ldata->my_tx_list, 1741 sizeof(sc->my_ldata->my_tx_list)); 1742 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1743 return; 1744 } 1745 1746 /* 1747 * Stop all chip I/O so that the kernel's probe routines don't get confused 1748 * by errant DMAs when rebooting. 1749 */ 1750 static void 1751 my_shutdown(device_t dev) 1752 { 1753 struct my_softc *sc; 1754 1755 sc = device_get_softc(dev); 1756 MY_LOCK(sc); 1757 my_stop(sc); 1758 MY_UNLOCK(sc); 1759 return; 1760 } 1761