1 /* 2 * Copyright (c) 2002 Myson Technology Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions, and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. The name of the author may not be used to endorse or promote products 12 * derived from this software without specific prior written permission. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 18 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * Written by: yen_cw@myson.com.tw available at: http://www.myson.com.tw/ 27 * 28 * Myson fast ethernet PCI NIC driver 29 */ 30 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD$"); 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/sockio.h> 37 #include <sys/mbuf.h> 38 #include <sys/malloc.h> 39 #include <sys/kernel.h> 40 #include <sys/socket.h> 41 #include <sys/queue.h> 42 #include <sys/types.h> 43 #include <sys/bus.h> 44 #include <sys/module.h> 45 #include <sys/lock.h> 46 #include <sys/mutex.h> 47 48 #define NBPFILTER 1 49 50 #include <net/if.h> 51 #include <net/if_arp.h> 52 #include <net/ethernet.h> 53 #include <net/if_media.h> 54 #include <net/if_dl.h> 55 #include <net/bpf.h> 56 57 #include <vm/vm.h> /* for vtophys */ 58 #include <vm/pmap.h> /* for vtophys */ 59 #include <machine/clock.h> /* for DELAY */ 60 #include <machine/bus_memio.h> 61 #include <machine/bus_pio.h> 62 #include <machine/bus.h> 63 #include <machine/resource.h> 64 #include <sys/bus.h> 65 #include <sys/rman.h> 66 67 #include <pci/pcireg.h> 68 #include <pci/pcivar.h> 69 70 #include <dev/mii/mii.h> 71 #include <dev/mii/miivar.h> 72 73 #include "miibus_if.h" 74 75 /* 76 * #define MY_USEIOSPACE 77 */ 78 79 static int MY_USEIOSPACE = 1; 80 81 #if (MY_USEIOSPACE) 82 #define MY_RES SYS_RES_IOPORT 83 #define MY_RID MY_PCI_LOIO 84 #else 85 #define MY_RES SYS_RES_MEMORY 86 #define MY_RID MY_PCI_LOMEM 87 #endif 88 89 90 #include <dev/my/if_myreg.h> 91 92 #ifndef lint 93 static const char rcsid[] = 94 "$Id: if_my.c,v 1.50 2001/12/03 04:15:33 <yen_cw@myson.com.tw> wpaul Exp $"; 95 #endif 96 97 /* 98 * Various supported device vendors/types and their names. 99 */ 100 struct my_type *my_info_tmp; 101 static struct my_type my_devs[] = { 102 {MYSONVENDORID, MTD800ID, "Myson MTD80X Based Fast Ethernet Card"}, 103 {MYSONVENDORID, MTD803ID, "Myson MTD80X Based Fast Ethernet Card"}, 104 {MYSONVENDORID, MTD891ID, "Myson MTD89X Based Giga Ethernet Card"}, 105 {0, 0, NULL} 106 }; 107 108 /* 109 * Various supported PHY vendors/types and their names. Note that this driver 110 * will work with pretty much any MII-compliant PHY, so failure to positively 111 * identify the chip is not a fatal error. 112 */ 113 static struct my_type my_phys[] = { 114 {MysonPHYID0, MysonPHYID0, "<MYSON MTD981>"}, 115 {SeeqPHYID0, SeeqPHYID0, "<SEEQ 80225>"}, 116 {AhdocPHYID0, AhdocPHYID0, "<AHDOC 101>"}, 117 {MarvellPHYID0, MarvellPHYID0, "<MARVELL 88E1000>"}, 118 {LevelOnePHYID0, LevelOnePHYID0, "<LevelOne LXT1000>"}, 119 {0, 0, "<MII-compliant physical interface>"} 120 }; 121 122 static int my_probe(device_t); 123 static int my_attach(device_t); 124 static int my_detach(device_t); 125 static int my_newbuf(struct my_softc *, struct my_chain_onefrag *); 126 static int my_encap(struct my_softc *, struct my_chain *, struct mbuf *); 127 static void my_rxeof(struct my_softc *); 128 static void my_txeof(struct my_softc *); 129 static void my_txeoc(struct my_softc *); 130 static void my_intr(void *); 131 static void my_start(struct ifnet *); 132 static int my_ioctl(struct ifnet *, u_long, caddr_t); 133 static void my_init(void *); 134 static void my_stop(struct my_softc *); 135 static void my_watchdog(struct ifnet *); 136 static void my_shutdown(device_t); 137 static int my_ifmedia_upd(struct ifnet *); 138 static void my_ifmedia_sts(struct ifnet *, struct ifmediareq *); 139 static u_int16_t my_phy_readreg(struct my_softc *, int); 140 static void my_phy_writereg(struct my_softc *, int, int); 141 static void my_autoneg_xmit(struct my_softc *); 142 static void my_autoneg_mii(struct my_softc *, int, int); 143 static void my_setmode_mii(struct my_softc *, int); 144 static void my_getmode_mii(struct my_softc *); 145 static void my_setcfg(struct my_softc *, int); 146 static u_int8_t my_calchash(caddr_t); 147 static void my_setmulti(struct my_softc *); 148 static void my_reset(struct my_softc *); 149 static int my_list_rx_init(struct my_softc *); 150 static int my_list_tx_init(struct my_softc *); 151 static long my_send_cmd_to_phy(struct my_softc *, int, int); 152 153 #define MY_SETBIT(sc, reg, x) CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 154 #define MY_CLRBIT(sc, reg, x) CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 155 156 static device_method_t my_methods[] = { 157 /* Device interface */ 158 DEVMETHOD(device_probe, my_probe), 159 DEVMETHOD(device_attach, my_attach), 160 DEVMETHOD(device_detach, my_detach), 161 DEVMETHOD(device_shutdown, my_shutdown), 162 163 {0, 0} 164 }; 165 166 static driver_t my_driver = { 167 "my", 168 my_methods, 169 sizeof(struct my_softc) 170 }; 171 172 static devclass_t my_devclass; 173 174 DRIVER_MODULE(if_my, pci, my_driver, my_devclass, 0, 0); 175 176 static long 177 my_send_cmd_to_phy(struct my_softc * sc, int opcode, int regad) 178 { 179 long miir; 180 int i; 181 int mask, data; 182 183 MY_LOCK(sc); 184 185 /* enable MII output */ 186 miir = CSR_READ_4(sc, MY_MANAGEMENT); 187 miir &= 0xfffffff0; 188 189 miir |= MY_MASK_MIIR_MII_WRITE + MY_MASK_MIIR_MII_MDO; 190 191 /* send 32 1's preamble */ 192 for (i = 0; i < 32; i++) { 193 /* low MDC; MDO is already high (miir) */ 194 miir &= ~MY_MASK_MIIR_MII_MDC; 195 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 196 197 /* high MDC */ 198 miir |= MY_MASK_MIIR_MII_MDC; 199 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 200 } 201 202 /* calculate ST+OP+PHYAD+REGAD+TA */ 203 data = opcode | (sc->my_phy_addr << 7) | (regad << 2); 204 205 /* sent out */ 206 mask = 0x8000; 207 while (mask) { 208 /* low MDC, prepare MDO */ 209 miir &= ~(MY_MASK_MIIR_MII_MDC + MY_MASK_MIIR_MII_MDO); 210 if (mask & data) 211 miir |= MY_MASK_MIIR_MII_MDO; 212 213 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 214 /* high MDC */ 215 miir |= MY_MASK_MIIR_MII_MDC; 216 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 217 DELAY(30); 218 219 /* next */ 220 mask >>= 1; 221 if (mask == 0x2 && opcode == MY_OP_READ) 222 miir &= ~MY_MASK_MIIR_MII_WRITE; 223 } 224 225 MY_UNLOCK(sc); 226 return miir; 227 } 228 229 230 static u_int16_t 231 my_phy_readreg(struct my_softc * sc, int reg) 232 { 233 long miir; 234 int mask, data; 235 236 MY_LOCK(sc); 237 238 if (sc->my_info->my_did == MTD803ID) 239 data = CSR_READ_2(sc, MY_PHYBASE + reg * 2); 240 else { 241 miir = my_send_cmd_to_phy(sc, MY_OP_READ, reg); 242 243 /* read data */ 244 mask = 0x8000; 245 data = 0; 246 while (mask) { 247 /* low MDC */ 248 miir &= ~MY_MASK_MIIR_MII_MDC; 249 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 250 251 /* read MDI */ 252 miir = CSR_READ_4(sc, MY_MANAGEMENT); 253 if (miir & MY_MASK_MIIR_MII_MDI) 254 data |= mask; 255 256 /* high MDC, and wait */ 257 miir |= MY_MASK_MIIR_MII_MDC; 258 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 259 DELAY(30); 260 261 /* next */ 262 mask >>= 1; 263 } 264 265 /* low MDC */ 266 miir &= ~MY_MASK_MIIR_MII_MDC; 267 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 268 } 269 270 MY_UNLOCK(sc); 271 return (u_int16_t) data; 272 } 273 274 275 static void 276 my_phy_writereg(struct my_softc * sc, int reg, int data) 277 { 278 long miir; 279 int mask; 280 281 MY_LOCK(sc); 282 283 if (sc->my_info->my_did == MTD803ID) 284 CSR_WRITE_2(sc, MY_PHYBASE + reg * 2, data); 285 else { 286 miir = my_send_cmd_to_phy(sc, MY_OP_WRITE, reg); 287 288 /* write data */ 289 mask = 0x8000; 290 while (mask) { 291 /* low MDC, prepare MDO */ 292 miir &= ~(MY_MASK_MIIR_MII_MDC + MY_MASK_MIIR_MII_MDO); 293 if (mask & data) 294 miir |= MY_MASK_MIIR_MII_MDO; 295 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 296 DELAY(1); 297 298 /* high MDC */ 299 miir |= MY_MASK_MIIR_MII_MDC; 300 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 301 DELAY(1); 302 303 /* next */ 304 mask >>= 1; 305 } 306 307 /* low MDC */ 308 miir &= ~MY_MASK_MIIR_MII_MDC; 309 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 310 } 311 MY_UNLOCK(sc); 312 return; 313 } 314 315 static u_int8_t 316 my_calchash(caddr_t addr) 317 { 318 u_int32_t crc, carry; 319 int i, j; 320 u_int8_t c; 321 322 /* Compute CRC for the address value. */ 323 crc = 0xFFFFFFFF; /* initial value */ 324 325 for (i = 0; i < 6; i++) { 326 c = *(addr + i); 327 for (j = 0; j < 8; j++) { 328 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 329 crc <<= 1; 330 c >>= 1; 331 if (carry) 332 crc = (crc ^ 0x04c11db6) | carry; 333 } 334 } 335 336 /* 337 * return the filter bit position Note: I arrived at the following 338 * nonsense through experimentation. It's not the usual way to 339 * generate the bit position but it's the only thing I could come up 340 * with that works. 341 */ 342 return (~(crc >> 26) & 0x0000003F); 343 } 344 345 346 /* 347 * Program the 64-bit multicast hash filter. 348 */ 349 static void 350 my_setmulti(struct my_softc * sc) 351 { 352 struct ifnet *ifp; 353 int h = 0; 354 u_int32_t hashes[2] = {0, 0}; 355 struct ifmultiaddr *ifma; 356 u_int32_t rxfilt; 357 int mcnt = 0; 358 359 MY_LOCK(sc); 360 361 ifp = &sc->arpcom.ac_if; 362 363 rxfilt = CSR_READ_4(sc, MY_TCRRCR); 364 365 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 366 rxfilt |= MY_AM; 367 CSR_WRITE_4(sc, MY_TCRRCR, rxfilt); 368 CSR_WRITE_4(sc, MY_MAR0, 0xFFFFFFFF); 369 CSR_WRITE_4(sc, MY_MAR1, 0xFFFFFFFF); 370 371 MY_UNLOCK(sc); 372 373 return; 374 } 375 /* first, zot all the existing hash bits */ 376 CSR_WRITE_4(sc, MY_MAR0, 0); 377 CSR_WRITE_4(sc, MY_MAR1, 0); 378 379 /* now program new ones */ 380 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 381 if (ifma->ifma_addr->sa_family != AF_LINK) 382 continue; 383 h = my_calchash(LLADDR((struct sockaddr_dl *) ifma->ifma_addr)); 384 if (h < 32) 385 hashes[0] |= (1 << h); 386 else 387 hashes[1] |= (1 << (h - 32)); 388 mcnt++; 389 } 390 391 if (mcnt) 392 rxfilt |= MY_AM; 393 else 394 rxfilt &= ~MY_AM; 395 CSR_WRITE_4(sc, MY_MAR0, hashes[0]); 396 CSR_WRITE_4(sc, MY_MAR1, hashes[1]); 397 CSR_WRITE_4(sc, MY_TCRRCR, rxfilt); 398 MY_UNLOCK(sc); 399 return; 400 } 401 402 /* 403 * Initiate an autonegotiation session. 404 */ 405 static void 406 my_autoneg_xmit(struct my_softc * sc) 407 { 408 u_int16_t phy_sts = 0; 409 410 MY_LOCK(sc); 411 412 my_phy_writereg(sc, PHY_BMCR, PHY_BMCR_RESET); 413 DELAY(500); 414 while (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_RESET); 415 416 phy_sts = my_phy_readreg(sc, PHY_BMCR); 417 phy_sts |= PHY_BMCR_AUTONEGENBL | PHY_BMCR_AUTONEGRSTR; 418 my_phy_writereg(sc, PHY_BMCR, phy_sts); 419 420 MY_UNLOCK(sc); 421 return; 422 } 423 424 425 /* 426 * Invoke autonegotiation on a PHY. 427 */ 428 static void 429 my_autoneg_mii(struct my_softc * sc, int flag, int verbose) 430 { 431 u_int16_t phy_sts = 0, media, advert, ability; 432 u_int16_t ability2 = 0; 433 struct ifnet *ifp; 434 struct ifmedia *ifm; 435 436 MY_LOCK(sc); 437 438 ifm = &sc->ifmedia; 439 ifp = &sc->arpcom.ac_if; 440 441 ifm->ifm_media = IFM_ETHER | IFM_AUTO; 442 443 #ifndef FORCE_AUTONEG_TFOUR 444 /* 445 * First, see if autoneg is supported. If not, there's no point in 446 * continuing. 447 */ 448 phy_sts = my_phy_readreg(sc, PHY_BMSR); 449 if (!(phy_sts & PHY_BMSR_CANAUTONEG)) { 450 if (verbose) 451 printf("my%d: autonegotiation not supported\n", 452 sc->my_unit); 453 ifm->ifm_media = IFM_ETHER | IFM_10_T | IFM_HDX; 454 MY_UNLOCK(sc); 455 return; 456 } 457 #endif 458 switch (flag) { 459 case MY_FLAG_FORCEDELAY: 460 /* 461 * XXX Never use this option anywhere but in the probe 462 * routine: making the kernel stop dead in its tracks for 463 * three whole seconds after we've gone multi-user is really 464 * bad manners. 465 */ 466 my_autoneg_xmit(sc); 467 DELAY(5000000); 468 break; 469 case MY_FLAG_SCHEDDELAY: 470 /* 471 * Wait for the transmitter to go idle before starting an 472 * autoneg session, otherwise my_start() may clobber our 473 * timeout, and we don't want to allow transmission during an 474 * autoneg session since that can screw it up. 475 */ 476 if (sc->my_cdata.my_tx_head != NULL) { 477 sc->my_want_auto = 1; 478 MY_UNLOCK(sc); 479 return; 480 } 481 my_autoneg_xmit(sc); 482 ifp->if_timer = 5; 483 sc->my_autoneg = 1; 484 sc->my_want_auto = 0; 485 MY_UNLOCK(sc); 486 return; 487 case MY_FLAG_DELAYTIMEO: 488 ifp->if_timer = 0; 489 sc->my_autoneg = 0; 490 break; 491 default: 492 printf("my%d: invalid autoneg flag: %d\n", sc->my_unit, flag); 493 MY_UNLOCK(sc); 494 return; 495 } 496 497 if (my_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_AUTONEGCOMP) { 498 if (verbose) 499 printf("my%d: autoneg complete, ", sc->my_unit); 500 phy_sts = my_phy_readreg(sc, PHY_BMSR); 501 } else { 502 if (verbose) 503 printf("my%d: autoneg not complete, ", sc->my_unit); 504 } 505 506 media = my_phy_readreg(sc, PHY_BMCR); 507 508 /* Link is good. Report modes and set duplex mode. */ 509 if (my_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT) { 510 if (verbose) 511 printf("my%d: link status good. ", sc->my_unit); 512 advert = my_phy_readreg(sc, PHY_ANAR); 513 ability = my_phy_readreg(sc, PHY_LPAR); 514 if ((sc->my_pinfo->my_vid == MarvellPHYID0) || 515 (sc->my_pinfo->my_vid == LevelOnePHYID0)) { 516 ability2 = my_phy_readreg(sc, PHY_1000SR); 517 if (ability2 & PHY_1000SR_1000BTXFULL) { 518 advert = 0; 519 ability = 0; 520 /* 521 * this version did not support 1000M, 522 * ifm->ifm_media = 523 * IFM_ETHER|IFM_1000_T|IFM_FDX; 524 */ 525 ifm->ifm_media = 526 IFM_ETHER | IFM_100_TX | IFM_FDX; 527 media &= ~PHY_BMCR_SPEEDSEL; 528 media |= PHY_BMCR_1000; 529 media |= PHY_BMCR_DUPLEX; 530 printf("(full-duplex, 1000Mbps)\n"); 531 } else if (ability2 & PHY_1000SR_1000BTXHALF) { 532 advert = 0; 533 ability = 0; 534 /* 535 * this version did not support 1000M, 536 * ifm->ifm_media = IFM_ETHER|IFM_1000_T; 537 */ 538 ifm->ifm_media = IFM_ETHER | IFM_100_TX; 539 media &= ~PHY_BMCR_SPEEDSEL; 540 media &= ~PHY_BMCR_DUPLEX; 541 media |= PHY_BMCR_1000; 542 printf("(half-duplex, 1000Mbps)\n"); 543 } 544 } 545 if (advert & PHY_ANAR_100BT4 && ability & PHY_ANAR_100BT4) { 546 ifm->ifm_media = IFM_ETHER | IFM_100_T4; 547 media |= PHY_BMCR_SPEEDSEL; 548 media &= ~PHY_BMCR_DUPLEX; 549 printf("(100baseT4)\n"); 550 } else if (advert & PHY_ANAR_100BTXFULL && 551 ability & PHY_ANAR_100BTXFULL) { 552 ifm->ifm_media = IFM_ETHER | IFM_100_TX | IFM_FDX; 553 media |= PHY_BMCR_SPEEDSEL; 554 media |= PHY_BMCR_DUPLEX; 555 printf("(full-duplex, 100Mbps)\n"); 556 } else if (advert & PHY_ANAR_100BTXHALF && 557 ability & PHY_ANAR_100BTXHALF) { 558 ifm->ifm_media = IFM_ETHER | IFM_100_TX | IFM_HDX; 559 media |= PHY_BMCR_SPEEDSEL; 560 media &= ~PHY_BMCR_DUPLEX; 561 printf("(half-duplex, 100Mbps)\n"); 562 } else if (advert & PHY_ANAR_10BTFULL && 563 ability & PHY_ANAR_10BTFULL) { 564 ifm->ifm_media = IFM_ETHER | IFM_10_T | IFM_FDX; 565 media &= ~PHY_BMCR_SPEEDSEL; 566 media |= PHY_BMCR_DUPLEX; 567 printf("(full-duplex, 10Mbps)\n"); 568 } else if (advert) { 569 ifm->ifm_media = IFM_ETHER | IFM_10_T | IFM_HDX; 570 media &= ~PHY_BMCR_SPEEDSEL; 571 media &= ~PHY_BMCR_DUPLEX; 572 printf("(half-duplex, 10Mbps)\n"); 573 } 574 media &= ~PHY_BMCR_AUTONEGENBL; 575 576 /* Set ASIC's duplex mode to match the PHY. */ 577 my_phy_writereg(sc, PHY_BMCR, media); 578 my_setcfg(sc, media); 579 } else { 580 if (verbose) 581 printf("my%d: no carrier\n", sc->my_unit); 582 } 583 584 my_init(sc); 585 if (sc->my_tx_pend) { 586 sc->my_autoneg = 0; 587 sc->my_tx_pend = 0; 588 my_start(ifp); 589 } 590 MY_UNLOCK(sc); 591 return; 592 } 593 594 /* 595 * To get PHY ability. 596 */ 597 static void 598 my_getmode_mii(struct my_softc * sc) 599 { 600 u_int16_t bmsr; 601 struct ifnet *ifp; 602 603 MY_LOCK(sc); 604 ifp = &sc->arpcom.ac_if; 605 bmsr = my_phy_readreg(sc, PHY_BMSR); 606 if (bootverbose) 607 printf("my%d: PHY status word: %x\n", sc->my_unit, bmsr); 608 609 /* fallback */ 610 sc->ifmedia.ifm_media = IFM_ETHER | IFM_10_T | IFM_HDX; 611 612 if (bmsr & PHY_BMSR_10BTHALF) { 613 if (bootverbose) 614 printf("my%d: 10Mbps half-duplex mode supported\n", 615 sc->my_unit); 616 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_10_T | IFM_HDX, 617 0, NULL); 618 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_10_T, 0, NULL); 619 } 620 if (bmsr & PHY_BMSR_10BTFULL) { 621 if (bootverbose) 622 printf("my%d: 10Mbps full-duplex mode supported\n", 623 sc->my_unit); 624 625 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_10_T | IFM_FDX, 626 0, NULL); 627 sc->ifmedia.ifm_media = IFM_ETHER | IFM_10_T | IFM_FDX; 628 } 629 if (bmsr & PHY_BMSR_100BTXHALF) { 630 if (bootverbose) 631 printf("my%d: 100Mbps half-duplex mode supported\n", 632 sc->my_unit); 633 ifp->if_baudrate = 100000000; 634 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_TX, 0, NULL); 635 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_TX | IFM_HDX, 636 0, NULL); 637 sc->ifmedia.ifm_media = IFM_ETHER | IFM_100_TX | IFM_HDX; 638 } 639 if (bmsr & PHY_BMSR_100BTXFULL) { 640 if (bootverbose) 641 printf("my%d: 100Mbps full-duplex mode supported\n", 642 sc->my_unit); 643 ifp->if_baudrate = 100000000; 644 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_TX | IFM_FDX, 645 0, NULL); 646 sc->ifmedia.ifm_media = IFM_ETHER | IFM_100_TX | IFM_FDX; 647 } 648 /* Some also support 100BaseT4. */ 649 if (bmsr & PHY_BMSR_100BT4) { 650 if (bootverbose) 651 printf("my%d: 100baseT4 mode supported\n", sc->my_unit); 652 ifp->if_baudrate = 100000000; 653 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_T4, 0, NULL); 654 sc->ifmedia.ifm_media = IFM_ETHER | IFM_100_T4; 655 #ifdef FORCE_AUTONEG_TFOUR 656 if (bootverbose) 657 printf("my%d: forcing on autoneg support for BT4\n", 658 sc->my_unit); 659 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_AUTO, 0 NULL): 660 sc->ifmedia.ifm_media = IFM_ETHER | IFM_AUTO; 661 #endif 662 } 663 #if 0 /* this version did not support 1000M, */ 664 if (sc->my_pinfo->my_vid == MarvellPHYID0) { 665 if (bootverbose) 666 printf("my%d: 1000Mbps half-duplex mode supported\n", 667 sc->my_unit); 668 669 ifp->if_baudrate = 1000000000; 670 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_T, 0, NULL); 671 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_T | IFM_HDX, 672 0, NULL); 673 if (bootverbose) 674 printf("my%d: 1000Mbps full-duplex mode supported\n", 675 sc->my_unit); 676 ifp->if_baudrate = 1000000000; 677 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_T | IFM_FDX, 678 0, NULL); 679 sc->ifmedia.ifm_media = IFM_ETHER | IFM_1000_T | IFM_FDX; 680 } 681 #endif 682 if (bmsr & PHY_BMSR_CANAUTONEG) { 683 if (bootverbose) 684 printf("my%d: autoneg supported\n", sc->my_unit); 685 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 686 sc->ifmedia.ifm_media = IFM_ETHER | IFM_AUTO; 687 } 688 MY_UNLOCK(sc); 689 return; 690 } 691 692 /* 693 * Set speed and duplex mode. 694 */ 695 static void 696 my_setmode_mii(struct my_softc * sc, int media) 697 { 698 u_int16_t bmcr; 699 struct ifnet *ifp; 700 701 MY_LOCK(sc); 702 ifp = &sc->arpcom.ac_if; 703 /* 704 * If an autoneg session is in progress, stop it. 705 */ 706 if (sc->my_autoneg) { 707 printf("my%d: canceling autoneg session\n", sc->my_unit); 708 ifp->if_timer = sc->my_autoneg = sc->my_want_auto = 0; 709 bmcr = my_phy_readreg(sc, PHY_BMCR); 710 bmcr &= ~PHY_BMCR_AUTONEGENBL; 711 my_phy_writereg(sc, PHY_BMCR, bmcr); 712 } 713 printf("my%d: selecting MII, ", sc->my_unit); 714 bmcr = my_phy_readreg(sc, PHY_BMCR); 715 bmcr &= ~(PHY_BMCR_AUTONEGENBL | PHY_BMCR_SPEEDSEL | PHY_BMCR_1000 | 716 PHY_BMCR_DUPLEX | PHY_BMCR_LOOPBK); 717 718 #if 0 /* this version did not support 1000M, */ 719 if (IFM_SUBTYPE(media) == IFM_1000_T) { 720 printf("1000Mbps/T4, half-duplex\n"); 721 bmcr &= ~PHY_BMCR_SPEEDSEL; 722 bmcr &= ~PHY_BMCR_DUPLEX; 723 bmcr |= PHY_BMCR_1000; 724 } 725 #endif 726 if (IFM_SUBTYPE(media) == IFM_100_T4) { 727 printf("100Mbps/T4, half-duplex\n"); 728 bmcr |= PHY_BMCR_SPEEDSEL; 729 bmcr &= ~PHY_BMCR_DUPLEX; 730 } 731 if (IFM_SUBTYPE(media) == IFM_100_TX) { 732 printf("100Mbps, "); 733 bmcr |= PHY_BMCR_SPEEDSEL; 734 } 735 if (IFM_SUBTYPE(media) == IFM_10_T) { 736 printf("10Mbps, "); 737 bmcr &= ~PHY_BMCR_SPEEDSEL; 738 } 739 if ((media & IFM_GMASK) == IFM_FDX) { 740 printf("full duplex\n"); 741 bmcr |= PHY_BMCR_DUPLEX; 742 } else { 743 printf("half duplex\n"); 744 bmcr &= ~PHY_BMCR_DUPLEX; 745 } 746 my_phy_writereg(sc, PHY_BMCR, bmcr); 747 my_setcfg(sc, bmcr); 748 MY_UNLOCK(sc); 749 return; 750 } 751 752 /* 753 * The Myson manual states that in order to fiddle with the 'full-duplex' and 754 * '100Mbps' bits in the netconfig register, we first have to put the 755 * transmit and/or receive logic in the idle state. 756 */ 757 static void 758 my_setcfg(struct my_softc * sc, int bmcr) 759 { 760 int i, restart = 0; 761 762 MY_LOCK(sc); 763 if (CSR_READ_4(sc, MY_TCRRCR) & (MY_TE | MY_RE)) { 764 restart = 1; 765 MY_CLRBIT(sc, MY_TCRRCR, (MY_TE | MY_RE)); 766 for (i = 0; i < MY_TIMEOUT; i++) { 767 DELAY(10); 768 if (!(CSR_READ_4(sc, MY_TCRRCR) & 769 (MY_TXRUN | MY_RXRUN))) 770 break; 771 } 772 if (i == MY_TIMEOUT) 773 printf("my%d: failed to force tx and rx to idle \n", 774 sc->my_unit); 775 } 776 MY_CLRBIT(sc, MY_TCRRCR, MY_PS1000); 777 MY_CLRBIT(sc, MY_TCRRCR, MY_PS10); 778 if (bmcr & PHY_BMCR_1000) 779 MY_SETBIT(sc, MY_TCRRCR, MY_PS1000); 780 else if (!(bmcr & PHY_BMCR_SPEEDSEL)) 781 MY_SETBIT(sc, MY_TCRRCR, MY_PS10); 782 if (bmcr & PHY_BMCR_DUPLEX) 783 MY_SETBIT(sc, MY_TCRRCR, MY_FD); 784 else 785 MY_CLRBIT(sc, MY_TCRRCR, MY_FD); 786 if (restart) 787 MY_SETBIT(sc, MY_TCRRCR, MY_TE | MY_RE); 788 MY_UNLOCK(sc); 789 return; 790 } 791 792 static void 793 my_reset(struct my_softc * sc) 794 { 795 register int i; 796 797 MY_LOCK(sc); 798 MY_SETBIT(sc, MY_BCR, MY_SWR); 799 for (i = 0; i < MY_TIMEOUT; i++) { 800 DELAY(10); 801 if (!(CSR_READ_4(sc, MY_BCR) & MY_SWR)) 802 break; 803 } 804 if (i == MY_TIMEOUT) 805 printf("m0x%d: reset never completed!\n", sc->my_unit); 806 807 /* Wait a little while for the chip to get its brains in order. */ 808 DELAY(1000); 809 MY_UNLOCK(sc); 810 return; 811 } 812 813 /* 814 * Probe for a Myson chip. Check the PCI vendor and device IDs against our 815 * list and return a device name if we find a match. 816 */ 817 static int 818 my_probe(device_t dev) 819 { 820 struct my_type *t; 821 822 t = my_devs; 823 while (t->my_name != NULL) { 824 if ((pci_get_vendor(dev) == t->my_vid) && 825 (pci_get_device(dev) == t->my_did)) { 826 device_set_desc(dev, t->my_name); 827 my_info_tmp = t; 828 return (0); 829 } 830 t++; 831 } 832 return (ENXIO); 833 } 834 835 /* 836 * Attach the interface. Allocate softc structures, do ifmedia setup and 837 * ethernet/BPF attach. 838 */ 839 static int 840 my_attach(device_t dev) 841 { 842 int s, i; 843 u_char eaddr[ETHER_ADDR_LEN]; 844 u_int32_t command, iobase; 845 struct my_softc *sc; 846 struct ifnet *ifp; 847 int media = IFM_ETHER | IFM_100_TX | IFM_FDX; 848 unsigned int round; 849 caddr_t roundptr; 850 struct my_type *p; 851 u_int16_t phy_vid, phy_did, phy_sts = 0; 852 int rid, unit, error = 0; 853 854 s = splimp(); 855 sc = device_get_softc(dev); 856 unit = device_get_unit(dev); 857 if (sc == NULL) { 858 printf("my%d: no memory for softc struct!\n", unit); 859 error = ENXIO; 860 goto fail; 861 862 } 863 bzero(sc, sizeof(struct my_softc)); 864 mtx_init(&sc->my_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 865 MTX_DEF | MTX_RECURSE); 866 MY_LOCK(sc); 867 868 /* 869 * Map control/status registers. 870 */ 871 #if 0 872 command = pci_read_config(dev, PCI_COMMAND_STATUS_REG, 4); 873 command |= (PCIM_CMD_PORTEN | PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN); 874 pci_write_config(dev, PCI_COMMAND_STATUS_REG, command & 0x000000ff, 4); 875 command = pci_read_config(dev, PCI_COMMAND_STATUS_REG, 4); 876 #endif 877 command = pci_read_config(dev, PCIR_COMMAND, 4); 878 command |= (PCIM_CMD_PORTEN | PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN); 879 pci_write_config(dev, PCIR_COMMAND, command & 0x000000ff, 4); 880 command = pci_read_config(dev, PCIR_COMMAND, 4); 881 882 if (my_info_tmp->my_did == MTD800ID) { 883 iobase = pci_read_config(dev, MY_PCI_LOIO, 4); 884 if (iobase & 0x300) 885 MY_USEIOSPACE = 0; 886 } 887 if (MY_USEIOSPACE) { 888 if (!(command & PCIM_CMD_PORTEN)) { 889 printf("my%d: failed to enable I/O ports!\n", unit); 890 free(sc, M_DEVBUF); 891 error = ENXIO; 892 goto fail; 893 } 894 #if 0 895 if (!pci_map_port(config_id, MY_PCI_LOIO, (u_int16_t *) & (sc->my_bhandle))) { 896 printf("my%d: couldn't map ports\n", unit); 897 error = ENXIO; 898 goto fail; 899 } 900 901 sc->my_btag = I386_BUS_SPACE_IO; 902 #endif 903 } else { 904 if (!(command & PCIM_CMD_MEMEN)) { 905 printf("my%d: failed to enable memory mapping!\n", 906 unit); 907 error = ENXIO; 908 goto fail; 909 } 910 #if 0 911 if (!pci_map_mem(config_id, MY_PCI_LOMEM, &vbase, &pbase)) { 912 printf ("my%d: couldn't map memory\n", unit); 913 error = ENXIO; 914 goto fail; 915 } 916 sc->my_btag = I386_BUS_SPACE_MEM; 917 sc->my_bhandle = vbase; 918 #endif 919 } 920 921 rid = MY_RID; 922 sc->my_res = bus_alloc_resource(dev, MY_RES, &rid, 923 0, ~0, 1, RF_ACTIVE); 924 925 if (sc->my_res == NULL) { 926 printf("my%d: couldn't map ports/memory\n", unit); 927 error = ENXIO; 928 goto fail; 929 } 930 sc->my_btag = rman_get_bustag(sc->my_res); 931 sc->my_bhandle = rman_get_bushandle(sc->my_res); 932 933 rid = 0; 934 sc->my_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 935 RF_SHAREABLE | RF_ACTIVE); 936 937 if (sc->my_irq == NULL) { 938 printf("my%d: couldn't map interrupt\n", unit); 939 bus_release_resource(dev, MY_RES, MY_RID, sc->my_res); 940 error = ENXIO; 941 goto fail; 942 } 943 error = bus_setup_intr(dev, sc->my_irq, INTR_TYPE_NET, 944 my_intr, sc, &sc->my_intrhand); 945 946 if (error) { 947 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->my_irq); 948 bus_release_resource(dev, MY_RES, MY_RID, sc->my_res); 949 printf("my%d: couldn't set up irq\n", unit); 950 goto fail; 951 } 952 callout_handle_init(&sc->my_stat_ch); 953 954 sc->my_info = my_info_tmp; 955 956 /* Reset the adapter. */ 957 my_reset(sc); 958 959 /* 960 * Get station address 961 */ 962 for (i = 0; i < ETHER_ADDR_LEN; ++i) 963 eaddr[i] = CSR_READ_1(sc, MY_PAR0 + i); 964 965 /* 966 * A Myson chip was detected. Inform the world. 967 */ 968 printf("my%d: Ethernet address: %6D\n", unit, eaddr, ":"); 969 970 sc->my_unit = unit; 971 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 972 973 sc->my_ldata_ptr = malloc(sizeof(struct my_list_data) + 8, 974 M_DEVBUF, M_NOWAIT); 975 if (sc->my_ldata_ptr == NULL) { 976 free(sc, M_DEVBUF); 977 printf("my%d: no memory for list buffers!\n", unit); 978 error = ENXIO; 979 goto fail; 980 } 981 sc->my_ldata = (struct my_list_data *) sc->my_ldata_ptr; 982 round = (uintptr_t)sc->my_ldata_ptr & 0xF; 983 roundptr = sc->my_ldata_ptr; 984 for (i = 0; i < 8; i++) { 985 if (round % 8) { 986 round++; 987 roundptr++; 988 } else 989 break; 990 } 991 sc->my_ldata = (struct my_list_data *) roundptr; 992 bzero(sc->my_ldata, sizeof(struct my_list_data)); 993 994 ifp = &sc->arpcom.ac_if; 995 ifp->if_softc = sc; 996 ifp->if_unit = unit; 997 ifp->if_name = "my"; 998 ifp->if_mtu = ETHERMTU; 999 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1000 ifp->if_ioctl = my_ioctl; 1001 ifp->if_output = ether_output; 1002 ifp->if_start = my_start; 1003 ifp->if_watchdog = my_watchdog; 1004 ifp->if_init = my_init; 1005 ifp->if_baudrate = 10000000; 1006 ifp->if_snd.ifq_maxlen = IFQ_MAXLEN; 1007 1008 if (sc->my_info->my_did == MTD803ID) 1009 sc->my_pinfo = my_phys; 1010 else { 1011 if (bootverbose) 1012 printf("my%d: probing for a PHY\n", sc->my_unit); 1013 for (i = MY_PHYADDR_MIN; i < MY_PHYADDR_MAX + 1; i++) { 1014 if (bootverbose) 1015 printf("my%d: checking address: %d\n", 1016 sc->my_unit, i); 1017 sc->my_phy_addr = i; 1018 phy_sts = my_phy_readreg(sc, PHY_BMSR); 1019 if ((phy_sts != 0) && (phy_sts != 0xffff)) 1020 break; 1021 else 1022 phy_sts = 0; 1023 } 1024 if (phy_sts) { 1025 phy_vid = my_phy_readreg(sc, PHY_VENID); 1026 phy_did = my_phy_readreg(sc, PHY_DEVID); 1027 if (bootverbose) { 1028 printf("my%d: found PHY at address %d, ", 1029 sc->my_unit, sc->my_phy_addr); 1030 printf("vendor id: %x device id: %x\n", 1031 phy_vid, phy_did); 1032 } 1033 p = my_phys; 1034 while (p->my_vid) { 1035 if (phy_vid == p->my_vid) { 1036 sc->my_pinfo = p; 1037 break; 1038 } 1039 p++; 1040 } 1041 if (sc->my_pinfo == NULL) 1042 sc->my_pinfo = &my_phys[PHY_UNKNOWN]; 1043 if (bootverbose) 1044 printf("my%d: PHY type: %s\n", 1045 sc->my_unit, sc->my_pinfo->my_name); 1046 } else { 1047 printf("my%d: MII without any phy!\n", sc->my_unit); 1048 error = ENXIO; 1049 goto fail; 1050 } 1051 } 1052 1053 /* Do ifmedia setup. */ 1054 ifmedia_init(&sc->ifmedia, 0, my_ifmedia_upd, my_ifmedia_sts); 1055 my_getmode_mii(sc); 1056 my_autoneg_mii(sc, MY_FLAG_FORCEDELAY, 1); 1057 media = sc->ifmedia.ifm_media; 1058 my_stop(sc); 1059 ifmedia_set(&sc->ifmedia, media); 1060 1061 ether_ifattach(ifp, eaddr); 1062 1063 #if 0 1064 at_shutdown(my_shutdown, sc, SHUTDOWN_POST_SYNC); 1065 shutdownhook_establish(my_shutdown, sc); 1066 #endif 1067 1068 MY_UNLOCK(sc); 1069 return (0); 1070 1071 fail: 1072 MY_UNLOCK(sc); 1073 mtx_destroy(&sc->my_mtx); 1074 splx(s); 1075 return (error); 1076 } 1077 1078 static int 1079 my_detach(device_t dev) 1080 { 1081 struct my_softc *sc; 1082 struct ifnet *ifp; 1083 int s; 1084 1085 s = splimp(); 1086 sc = device_get_softc(dev); 1087 MY_LOCK(sc); 1088 ifp = &sc->arpcom.ac_if; 1089 ether_ifdetach(ifp); 1090 my_stop(sc); 1091 1092 #if 0 1093 bus_generic_detach(dev); 1094 device_delete_child(dev, sc->rl_miibus); 1095 #endif 1096 1097 bus_teardown_intr(dev, sc->my_irq, sc->my_intrhand); 1098 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->my_irq); 1099 bus_release_resource(dev, MY_RES, MY_RID, sc->my_res); 1100 #if 0 1101 contigfree(sc->my_cdata.my_rx_buf, MY_RXBUFLEN + 32, M_DEVBUF); 1102 #endif 1103 free(sc, M_DEVBUF); 1104 MY_UNLOCK(sc); 1105 splx(s); 1106 mtx_destroy(&sc->my_mtx); 1107 return (0); 1108 } 1109 1110 1111 /* 1112 * Initialize the transmit descriptors. 1113 */ 1114 static int 1115 my_list_tx_init(struct my_softc * sc) 1116 { 1117 struct my_chain_data *cd; 1118 struct my_list_data *ld; 1119 int i; 1120 1121 MY_LOCK(sc); 1122 cd = &sc->my_cdata; 1123 ld = sc->my_ldata; 1124 for (i = 0; i < MY_TX_LIST_CNT; i++) { 1125 cd->my_tx_chain[i].my_ptr = &ld->my_tx_list[i]; 1126 if (i == (MY_TX_LIST_CNT - 1)) 1127 cd->my_tx_chain[i].my_nextdesc = &cd->my_tx_chain[0]; 1128 else 1129 cd->my_tx_chain[i].my_nextdesc = 1130 &cd->my_tx_chain[i + 1]; 1131 } 1132 cd->my_tx_free = &cd->my_tx_chain[0]; 1133 cd->my_tx_tail = cd->my_tx_head = NULL; 1134 MY_UNLOCK(sc); 1135 return (0); 1136 } 1137 1138 /* 1139 * Initialize the RX descriptors and allocate mbufs for them. Note that we 1140 * arrange the descriptors in a closed ring, so that the last descriptor 1141 * points back to the first. 1142 */ 1143 static int 1144 my_list_rx_init(struct my_softc * sc) 1145 { 1146 struct my_chain_data *cd; 1147 struct my_list_data *ld; 1148 int i; 1149 1150 MY_LOCK(sc); 1151 cd = &sc->my_cdata; 1152 ld = sc->my_ldata; 1153 for (i = 0; i < MY_RX_LIST_CNT; i++) { 1154 cd->my_rx_chain[i].my_ptr = 1155 (struct my_desc *) & ld->my_rx_list[i]; 1156 if (my_newbuf(sc, &cd->my_rx_chain[i]) == ENOBUFS) { 1157 MY_UNLOCK(sc); 1158 return (ENOBUFS); 1159 } 1160 if (i == (MY_RX_LIST_CNT - 1)) { 1161 cd->my_rx_chain[i].my_nextdesc = &cd->my_rx_chain[0]; 1162 ld->my_rx_list[i].my_next = vtophys(&ld->my_rx_list[0]); 1163 } else { 1164 cd->my_rx_chain[i].my_nextdesc = 1165 &cd->my_rx_chain[i + 1]; 1166 ld->my_rx_list[i].my_next = 1167 vtophys(&ld->my_rx_list[i + 1]); 1168 } 1169 } 1170 cd->my_rx_head = &cd->my_rx_chain[0]; 1171 MY_UNLOCK(sc); 1172 return (0); 1173 } 1174 1175 /* 1176 * Initialize an RX descriptor and attach an MBUF cluster. 1177 */ 1178 static int 1179 my_newbuf(struct my_softc * sc, struct my_chain_onefrag * c) 1180 { 1181 struct mbuf *m_new = NULL; 1182 1183 MY_LOCK(sc); 1184 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1185 if (m_new == NULL) { 1186 printf("my%d: no memory for rx list -- packet dropped!\n", 1187 sc->my_unit); 1188 MY_UNLOCK(sc); 1189 return (ENOBUFS); 1190 } 1191 MCLGET(m_new, M_DONTWAIT); 1192 if (!(m_new->m_flags & M_EXT)) { 1193 printf("my%d: no memory for rx list -- packet dropped!\n", 1194 sc->my_unit); 1195 m_freem(m_new); 1196 MY_UNLOCK(sc); 1197 return (ENOBUFS); 1198 } 1199 c->my_mbuf = m_new; 1200 c->my_ptr->my_data = vtophys(mtod(m_new, caddr_t)); 1201 c->my_ptr->my_ctl = (MCLBYTES - 1) << MY_RBSShift; 1202 c->my_ptr->my_status = MY_OWNByNIC; 1203 MY_UNLOCK(sc); 1204 return (0); 1205 } 1206 1207 /* 1208 * A frame has been uploaded: pass the resulting mbuf chain up to the higher 1209 * level protocols. 1210 */ 1211 static void 1212 my_rxeof(struct my_softc * sc) 1213 { 1214 struct ether_header *eh; 1215 struct mbuf *m; 1216 struct ifnet *ifp; 1217 struct my_chain_onefrag *cur_rx; 1218 int total_len = 0; 1219 u_int32_t rxstat; 1220 1221 MY_LOCK(sc); 1222 ifp = &sc->arpcom.ac_if; 1223 while (!((rxstat = sc->my_cdata.my_rx_head->my_ptr->my_status) 1224 & MY_OWNByNIC)) { 1225 cur_rx = sc->my_cdata.my_rx_head; 1226 sc->my_cdata.my_rx_head = cur_rx->my_nextdesc; 1227 1228 if (rxstat & MY_ES) { /* error summary: give up this rx pkt */ 1229 ifp->if_ierrors++; 1230 cur_rx->my_ptr->my_status = MY_OWNByNIC; 1231 continue; 1232 } 1233 /* No errors; receive the packet. */ 1234 total_len = (rxstat & MY_FLNGMASK) >> MY_FLNGShift; 1235 total_len -= ETHER_CRC_LEN; 1236 1237 if (total_len < MINCLSIZE) { 1238 m = m_devget(mtod(cur_rx->my_mbuf, char *), 1239 total_len, 0, ifp, NULL); 1240 cur_rx->my_ptr->my_status = MY_OWNByNIC; 1241 if (m == NULL) { 1242 ifp->if_ierrors++; 1243 continue; 1244 } 1245 } else { 1246 m = cur_rx->my_mbuf; 1247 /* 1248 * Try to conjure up a new mbuf cluster. If that 1249 * fails, it means we have an out of memory condition 1250 * and should leave the buffer in place and continue. 1251 * This will result in a lost packet, but there's 1252 * little else we can do in this situation. 1253 */ 1254 if (my_newbuf(sc, cur_rx) == ENOBUFS) { 1255 ifp->if_ierrors++; 1256 cur_rx->my_ptr->my_status = MY_OWNByNIC; 1257 continue; 1258 } 1259 m->m_pkthdr.rcvif = ifp; 1260 m->m_pkthdr.len = m->m_len = total_len; 1261 } 1262 ifp->if_ipackets++; 1263 eh = mtod(m, struct ether_header *); 1264 #if NBPFILTER > 0 1265 /* 1266 * Handle BPF listeners. Let the BPF user see the packet, but 1267 * don't pass it up to the ether_input() layer unless it's a 1268 * broadcast packet, multicast packet, matches our ethernet 1269 * address or the interface is in promiscuous mode. 1270 */ 1271 if (ifp->if_bpf) { 1272 BPF_MTAP(ifp, m); 1273 if (ifp->if_flags & IFF_PROMISC && 1274 (bcmp(eh->ether_dhost, sc->arpcom.ac_enaddr, 1275 ETHER_ADDR_LEN) && 1276 (eh->ether_dhost[0] & 1) == 0)) { 1277 m_freem(m); 1278 continue; 1279 } 1280 } 1281 #endif 1282 (*ifp->if_input)(ifp, m); 1283 } 1284 MY_UNLOCK(sc); 1285 return; 1286 } 1287 1288 1289 /* 1290 * A frame was downloaded to the chip. It's safe for us to clean up the list 1291 * buffers. 1292 */ 1293 static void 1294 my_txeof(struct my_softc * sc) 1295 { 1296 struct my_chain *cur_tx; 1297 struct ifnet *ifp; 1298 1299 MY_LOCK(sc); 1300 ifp = &sc->arpcom.ac_if; 1301 /* Clear the timeout timer. */ 1302 ifp->if_timer = 0; 1303 if (sc->my_cdata.my_tx_head == NULL) { 1304 MY_UNLOCK(sc); 1305 return; 1306 } 1307 /* 1308 * Go through our tx list and free mbufs for those frames that have 1309 * been transmitted. 1310 */ 1311 while (sc->my_cdata.my_tx_head->my_mbuf != NULL) { 1312 u_int32_t txstat; 1313 1314 cur_tx = sc->my_cdata.my_tx_head; 1315 txstat = MY_TXSTATUS(cur_tx); 1316 if ((txstat & MY_OWNByNIC) || txstat == MY_UNSENT) 1317 break; 1318 if (!(CSR_READ_4(sc, MY_TCRRCR) & MY_Enhanced)) { 1319 if (txstat & MY_TXERR) { 1320 ifp->if_oerrors++; 1321 if (txstat & MY_EC) /* excessive collision */ 1322 ifp->if_collisions++; 1323 if (txstat & MY_LC) /* late collision */ 1324 ifp->if_collisions++; 1325 } 1326 ifp->if_collisions += (txstat & MY_NCRMASK) >> 1327 MY_NCRShift; 1328 } 1329 ifp->if_opackets++; 1330 m_freem(cur_tx->my_mbuf); 1331 cur_tx->my_mbuf = NULL; 1332 if (sc->my_cdata.my_tx_head == sc->my_cdata.my_tx_tail) { 1333 sc->my_cdata.my_tx_head = NULL; 1334 sc->my_cdata.my_tx_tail = NULL; 1335 break; 1336 } 1337 sc->my_cdata.my_tx_head = cur_tx->my_nextdesc; 1338 } 1339 if (CSR_READ_4(sc, MY_TCRRCR) & MY_Enhanced) { 1340 ifp->if_collisions += (CSR_READ_4(sc, MY_TSR) & MY_NCRMask); 1341 } 1342 MY_UNLOCK(sc); 1343 return; 1344 } 1345 1346 /* 1347 * TX 'end of channel' interrupt handler. 1348 */ 1349 static void 1350 my_txeoc(struct my_softc * sc) 1351 { 1352 struct ifnet *ifp; 1353 1354 MY_LOCK(sc); 1355 ifp = &sc->arpcom.ac_if; 1356 ifp->if_timer = 0; 1357 if (sc->my_cdata.my_tx_head == NULL) { 1358 ifp->if_flags &= ~IFF_OACTIVE; 1359 sc->my_cdata.my_tx_tail = NULL; 1360 if (sc->my_want_auto) 1361 my_autoneg_mii(sc, MY_FLAG_SCHEDDELAY, 1); 1362 } else { 1363 if (MY_TXOWN(sc->my_cdata.my_tx_head) == MY_UNSENT) { 1364 MY_TXOWN(sc->my_cdata.my_tx_head) = MY_OWNByNIC; 1365 ifp->if_timer = 5; 1366 CSR_WRITE_4(sc, MY_TXPDR, 0xFFFFFFFF); 1367 } 1368 } 1369 MY_UNLOCK(sc); 1370 return; 1371 } 1372 1373 static void 1374 my_intr(void *arg) 1375 { 1376 struct my_softc *sc; 1377 struct ifnet *ifp; 1378 u_int32_t status; 1379 1380 sc = arg; 1381 MY_LOCK(sc); 1382 ifp = &sc->arpcom.ac_if; 1383 if (!(ifp->if_flags & IFF_UP)) { 1384 MY_UNLOCK(sc); 1385 return; 1386 } 1387 /* Disable interrupts. */ 1388 CSR_WRITE_4(sc, MY_IMR, 0x00000000); 1389 1390 for (;;) { 1391 status = CSR_READ_4(sc, MY_ISR); 1392 status &= MY_INTRS; 1393 if (status) 1394 CSR_WRITE_4(sc, MY_ISR, status); 1395 else 1396 break; 1397 1398 if (status & MY_RI) /* receive interrupt */ 1399 my_rxeof(sc); 1400 1401 if ((status & MY_RBU) || (status & MY_RxErr)) { 1402 /* rx buffer unavailable or rx error */ 1403 ifp->if_ierrors++; 1404 #ifdef foo 1405 my_stop(sc); 1406 my_reset(sc); 1407 my_init(sc); 1408 #endif 1409 } 1410 if (status & MY_TI) /* tx interrupt */ 1411 my_txeof(sc); 1412 if (status & MY_ETI) /* tx early interrupt */ 1413 my_txeof(sc); 1414 if (status & MY_TBU) /* tx buffer unavailable */ 1415 my_txeoc(sc); 1416 1417 #if 0 /* 90/1/18 delete */ 1418 if (status & MY_FBE) { 1419 my_reset(sc); 1420 my_init(sc); 1421 } 1422 #endif 1423 1424 } 1425 1426 /* Re-enable interrupts. */ 1427 CSR_WRITE_4(sc, MY_IMR, MY_INTRS); 1428 if (ifp->if_snd.ifq_head != NULL) 1429 my_start(ifp); 1430 MY_UNLOCK(sc); 1431 return; 1432 } 1433 1434 /* 1435 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1436 * pointers to the fragment pointers. 1437 */ 1438 static int 1439 my_encap(struct my_softc * sc, struct my_chain * c, struct mbuf * m_head) 1440 { 1441 struct my_desc *f = NULL; 1442 int total_len; 1443 struct mbuf *m, *m_new = NULL; 1444 1445 MY_LOCK(sc); 1446 /* calculate the total tx pkt length */ 1447 total_len = 0; 1448 for (m = m_head; m != NULL; m = m->m_next) 1449 total_len += m->m_len; 1450 /* 1451 * Start packing the mbufs in this chain into the fragment pointers. 1452 * Stop when we run out of fragments or hit the end of the mbuf 1453 * chain. 1454 */ 1455 m = m_head; 1456 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1457 if (m_new == NULL) { 1458 printf("my%d: no memory for tx list", sc->my_unit); 1459 MY_UNLOCK(sc); 1460 return (1); 1461 } 1462 if (m_head->m_pkthdr.len > MHLEN) { 1463 MCLGET(m_new, M_DONTWAIT); 1464 if (!(m_new->m_flags & M_EXT)) { 1465 m_freem(m_new); 1466 printf("my%d: no memory for tx list", sc->my_unit); 1467 MY_UNLOCK(sc); 1468 return (1); 1469 } 1470 } 1471 m_copydata(m_head, 0, m_head->m_pkthdr.len, mtod(m_new, caddr_t)); 1472 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1473 m_freem(m_head); 1474 m_head = m_new; 1475 f = &c->my_ptr->my_frag[0]; 1476 f->my_status = 0; 1477 f->my_data = vtophys(mtod(m_new, caddr_t)); 1478 total_len = m_new->m_len; 1479 f->my_ctl = MY_TXFD | MY_TXLD | MY_CRCEnable | MY_PADEnable; 1480 f->my_ctl |= total_len << MY_PKTShift; /* pkt size */ 1481 f->my_ctl |= total_len; /* buffer size */ 1482 /* 89/12/29 add, for mtd891 *//* [ 89? ] */ 1483 if (sc->my_info->my_did == MTD891ID) 1484 f->my_ctl |= MY_ETIControl | MY_RetryTxLC; 1485 c->my_mbuf = m_head; 1486 c->my_lastdesc = 0; 1487 MY_TXNEXT(c) = vtophys(&c->my_nextdesc->my_ptr->my_frag[0]); 1488 MY_UNLOCK(sc); 1489 return (0); 1490 } 1491 1492 /* 1493 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1494 * to the mbuf data regions directly in the transmit lists. We also save a 1495 * copy of the pointers since the transmit list fragment pointers are 1496 * physical addresses. 1497 */ 1498 static void 1499 my_start(struct ifnet * ifp) 1500 { 1501 struct my_softc *sc; 1502 struct mbuf *m_head = NULL; 1503 struct my_chain *cur_tx = NULL, *start_tx; 1504 1505 sc = ifp->if_softc; 1506 MY_LOCK(sc); 1507 if (sc->my_autoneg) { 1508 sc->my_tx_pend = 1; 1509 MY_UNLOCK(sc); 1510 return; 1511 } 1512 /* 1513 * Check for an available queue slot. If there are none, punt. 1514 */ 1515 if (sc->my_cdata.my_tx_free->my_mbuf != NULL) { 1516 ifp->if_flags |= IFF_OACTIVE; 1517 MY_UNLOCK(sc); 1518 return; 1519 } 1520 start_tx = sc->my_cdata.my_tx_free; 1521 while (sc->my_cdata.my_tx_free->my_mbuf == NULL) { 1522 IF_DEQUEUE(&ifp->if_snd, m_head); 1523 if (m_head == NULL) 1524 break; 1525 1526 /* Pick a descriptor off the free list. */ 1527 cur_tx = sc->my_cdata.my_tx_free; 1528 sc->my_cdata.my_tx_free = cur_tx->my_nextdesc; 1529 1530 /* Pack the data into the descriptor. */ 1531 my_encap(sc, cur_tx, m_head); 1532 1533 if (cur_tx != start_tx) 1534 MY_TXOWN(cur_tx) = MY_OWNByNIC; 1535 #if NBPFILTER > 0 1536 /* 1537 * If there's a BPF listener, bounce a copy of this frame to 1538 * him. 1539 */ 1540 BPF_MTAP(ifp, cur_tx->my_mbuf); 1541 #endif 1542 } 1543 /* 1544 * If there are no packets queued, bail. 1545 */ 1546 if (cur_tx == NULL) { 1547 MY_UNLOCK(sc); 1548 return; 1549 } 1550 /* 1551 * Place the request for the upload interrupt in the last descriptor 1552 * in the chain. This way, if we're chaining several packets at once, 1553 * we'll only get an interupt once for the whole chain rather than 1554 * once for each packet. 1555 */ 1556 MY_TXCTL(cur_tx) |= MY_TXIC; 1557 cur_tx->my_ptr->my_frag[0].my_ctl |= MY_TXIC; 1558 sc->my_cdata.my_tx_tail = cur_tx; 1559 if (sc->my_cdata.my_tx_head == NULL) 1560 sc->my_cdata.my_tx_head = start_tx; 1561 MY_TXOWN(start_tx) = MY_OWNByNIC; 1562 CSR_WRITE_4(sc, MY_TXPDR, 0xFFFFFFFF); /* tx polling demand */ 1563 1564 /* 1565 * Set a timeout in case the chip goes out to lunch. 1566 */ 1567 ifp->if_timer = 5; 1568 MY_UNLOCK(sc); 1569 return; 1570 } 1571 1572 static void 1573 my_init(void *xsc) 1574 { 1575 struct my_softc *sc = xsc; 1576 struct ifnet *ifp = &sc->arpcom.ac_if; 1577 int s; 1578 u_int16_t phy_bmcr = 0; 1579 1580 MY_LOCK(sc); 1581 if (sc->my_autoneg) { 1582 MY_UNLOCK(sc); 1583 return; 1584 } 1585 s = splimp(); 1586 if (sc->my_pinfo != NULL) 1587 phy_bmcr = my_phy_readreg(sc, PHY_BMCR); 1588 /* 1589 * Cancel pending I/O and free all RX/TX buffers. 1590 */ 1591 my_stop(sc); 1592 my_reset(sc); 1593 1594 /* 1595 * Set cache alignment and burst length. 1596 */ 1597 #if 0 /* 89/9/1 modify, */ 1598 CSR_WRITE_4(sc, MY_BCR, MY_RPBLE512); 1599 CSR_WRITE_4(sc, MY_TCRRCR, MY_TFTSF); 1600 #endif 1601 CSR_WRITE_4(sc, MY_BCR, MY_PBL8); 1602 CSR_WRITE_4(sc, MY_TCRRCR, MY_TFTSF | MY_RBLEN | MY_RPBLE512); 1603 /* 1604 * 89/12/29 add, for mtd891, 1605 */ 1606 if (sc->my_info->my_did == MTD891ID) { 1607 MY_SETBIT(sc, MY_BCR, MY_PROG); 1608 MY_SETBIT(sc, MY_TCRRCR, MY_Enhanced); 1609 } 1610 my_setcfg(sc, phy_bmcr); 1611 /* Init circular RX list. */ 1612 if (my_list_rx_init(sc) == ENOBUFS) { 1613 printf("my%d: init failed: no memory for rx buffers\n", 1614 sc->my_unit); 1615 my_stop(sc); 1616 (void)splx(s); 1617 MY_UNLOCK(sc); 1618 return; 1619 } 1620 /* Init TX descriptors. */ 1621 my_list_tx_init(sc); 1622 1623 /* If we want promiscuous mode, set the allframes bit. */ 1624 if (ifp->if_flags & IFF_PROMISC) 1625 MY_SETBIT(sc, MY_TCRRCR, MY_PROM); 1626 else 1627 MY_CLRBIT(sc, MY_TCRRCR, MY_PROM); 1628 1629 /* 1630 * Set capture broadcast bit to capture broadcast frames. 1631 */ 1632 if (ifp->if_flags & IFF_BROADCAST) 1633 MY_SETBIT(sc, MY_TCRRCR, MY_AB); 1634 else 1635 MY_CLRBIT(sc, MY_TCRRCR, MY_AB); 1636 1637 /* 1638 * Program the multicast filter, if necessary. 1639 */ 1640 my_setmulti(sc); 1641 1642 /* 1643 * Load the address of the RX list. 1644 */ 1645 MY_CLRBIT(sc, MY_TCRRCR, MY_RE); 1646 CSR_WRITE_4(sc, MY_RXLBA, vtophys(&sc->my_ldata->my_rx_list[0])); 1647 1648 /* 1649 * Enable interrupts. 1650 */ 1651 CSR_WRITE_4(sc, MY_IMR, MY_INTRS); 1652 CSR_WRITE_4(sc, MY_ISR, 0xFFFFFFFF); 1653 1654 /* Enable receiver and transmitter. */ 1655 MY_SETBIT(sc, MY_TCRRCR, MY_RE); 1656 MY_CLRBIT(sc, MY_TCRRCR, MY_TE); 1657 CSR_WRITE_4(sc, MY_TXLBA, vtophys(&sc->my_ldata->my_tx_list[0])); 1658 MY_SETBIT(sc, MY_TCRRCR, MY_TE); 1659 1660 /* Restore state of BMCR */ 1661 if (sc->my_pinfo != NULL) 1662 my_phy_writereg(sc, PHY_BMCR, phy_bmcr); 1663 ifp->if_flags |= IFF_RUNNING; 1664 ifp->if_flags &= ~IFF_OACTIVE; 1665 (void)splx(s); 1666 MY_UNLOCK(sc); 1667 return; 1668 } 1669 1670 /* 1671 * Set media options. 1672 */ 1673 1674 static int 1675 my_ifmedia_upd(struct ifnet * ifp) 1676 { 1677 struct my_softc *sc; 1678 struct ifmedia *ifm; 1679 1680 sc = ifp->if_softc; 1681 MY_LOCK(sc); 1682 ifm = &sc->ifmedia; 1683 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) { 1684 MY_UNLOCK(sc); 1685 return (EINVAL); 1686 } 1687 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO) 1688 my_autoneg_mii(sc, MY_FLAG_SCHEDDELAY, 1); 1689 else 1690 my_setmode_mii(sc, ifm->ifm_media); 1691 MY_UNLOCK(sc); 1692 return (0); 1693 } 1694 1695 /* 1696 * Report current media status. 1697 */ 1698 1699 static void 1700 my_ifmedia_sts(struct ifnet * ifp, struct ifmediareq * ifmr) 1701 { 1702 struct my_softc *sc; 1703 u_int16_t advert = 0, ability = 0; 1704 1705 sc = ifp->if_softc; 1706 MY_LOCK(sc); 1707 ifmr->ifm_active = IFM_ETHER; 1708 if (!(my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_AUTONEGENBL)) { 1709 #if 0 /* this version did not support 1000M, */ 1710 if (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_1000) 1711 ifmr->ifm_active = IFM_ETHER | IFM_1000TX; 1712 #endif 1713 if (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_SPEEDSEL) 1714 ifmr->ifm_active = IFM_ETHER | IFM_100_TX; 1715 else 1716 ifmr->ifm_active = IFM_ETHER | IFM_10_T; 1717 if (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_DUPLEX) 1718 ifmr->ifm_active |= IFM_FDX; 1719 else 1720 ifmr->ifm_active |= IFM_HDX; 1721 1722 MY_UNLOCK(sc); 1723 return; 1724 } 1725 ability = my_phy_readreg(sc, PHY_LPAR); 1726 advert = my_phy_readreg(sc, PHY_ANAR); 1727 1728 #if 0 /* this version did not support 1000M, */ 1729 if (sc->my_pinfo->my_vid = MarvellPHYID0) { 1730 ability2 = my_phy_readreg(sc, PHY_1000SR); 1731 if (ability2 & PHY_1000SR_1000BTXFULL) { 1732 advert = 0; 1733 ability = 0; 1734 ifmr->ifm_active = IFM_ETHER|IFM_1000_T|IFM_FDX; 1735 } else if (ability & PHY_1000SR_1000BTXHALF) { 1736 advert = 0; 1737 ability = 0; 1738 ifmr->ifm_active = IFM_ETHER|IFM_1000_T|IFM_HDX; 1739 } 1740 } 1741 #endif 1742 if (advert & PHY_ANAR_100BT4 && ability & PHY_ANAR_100BT4) 1743 ifmr->ifm_active = IFM_ETHER | IFM_100_T4; 1744 else if (advert & PHY_ANAR_100BTXFULL && ability & PHY_ANAR_100BTXFULL) 1745 ifmr->ifm_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 1746 else if (advert & PHY_ANAR_100BTXHALF && ability & PHY_ANAR_100BTXHALF) 1747 ifmr->ifm_active = IFM_ETHER | IFM_100_TX | IFM_HDX; 1748 else if (advert & PHY_ANAR_10BTFULL && ability & PHY_ANAR_10BTFULL) 1749 ifmr->ifm_active = IFM_ETHER | IFM_10_T | IFM_FDX; 1750 else if (advert & PHY_ANAR_10BTHALF && ability & PHY_ANAR_10BTHALF) 1751 ifmr->ifm_active = IFM_ETHER | IFM_10_T | IFM_HDX; 1752 MY_UNLOCK(sc); 1753 return; 1754 } 1755 1756 static int 1757 my_ioctl(struct ifnet * ifp, u_long command, caddr_t data) 1758 { 1759 struct my_softc *sc = ifp->if_softc; 1760 struct ifreq *ifr = (struct ifreq *) data; 1761 int s, error = 0; 1762 1763 s = splimp(); 1764 MY_LOCK(sc); 1765 switch (command) { 1766 case SIOCSIFFLAGS: 1767 if (ifp->if_flags & IFF_UP) 1768 my_init(sc); 1769 else if (ifp->if_flags & IFF_RUNNING) 1770 my_stop(sc); 1771 error = 0; 1772 break; 1773 case SIOCADDMULTI: 1774 case SIOCDELMULTI: 1775 my_setmulti(sc); 1776 error = 0; 1777 break; 1778 case SIOCGIFMEDIA: 1779 case SIOCSIFMEDIA: 1780 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); 1781 break; 1782 default: 1783 error = ether_ioctl(ifp, command, data); 1784 break; 1785 } 1786 MY_UNLOCK(sc); 1787 (void)splx(s); 1788 return (error); 1789 } 1790 1791 static void 1792 my_watchdog(struct ifnet * ifp) 1793 { 1794 struct my_softc *sc; 1795 1796 sc = ifp->if_softc; 1797 MY_LOCK(sc); 1798 if (sc->my_autoneg) { 1799 my_autoneg_mii(sc, MY_FLAG_DELAYTIMEO, 1); 1800 MY_UNLOCK(sc); 1801 return; 1802 } 1803 ifp->if_oerrors++; 1804 printf("my%d: watchdog timeout\n", sc->my_unit); 1805 if (!(my_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT)) 1806 printf("my%d: no carrier - transceiver cable problem?\n", 1807 sc->my_unit); 1808 my_stop(sc); 1809 my_reset(sc); 1810 my_init(sc); 1811 if (ifp->if_snd.ifq_head != NULL) 1812 my_start(ifp); 1813 MY_LOCK(sc); 1814 return; 1815 } 1816 1817 1818 /* 1819 * Stop the adapter and free any mbufs allocated to the RX and TX lists. 1820 */ 1821 static void 1822 my_stop(struct my_softc * sc) 1823 { 1824 register int i; 1825 struct ifnet *ifp; 1826 1827 MY_LOCK(sc); 1828 ifp = &sc->arpcom.ac_if; 1829 ifp->if_timer = 0; 1830 1831 MY_CLRBIT(sc, MY_TCRRCR, (MY_RE | MY_TE)); 1832 CSR_WRITE_4(sc, MY_IMR, 0x00000000); 1833 CSR_WRITE_4(sc, MY_TXLBA, 0x00000000); 1834 CSR_WRITE_4(sc, MY_RXLBA, 0x00000000); 1835 1836 /* 1837 * Free data in the RX lists. 1838 */ 1839 for (i = 0; i < MY_RX_LIST_CNT; i++) { 1840 if (sc->my_cdata.my_rx_chain[i].my_mbuf != NULL) { 1841 m_freem(sc->my_cdata.my_rx_chain[i].my_mbuf); 1842 sc->my_cdata.my_rx_chain[i].my_mbuf = NULL; 1843 } 1844 } 1845 bzero((char *)&sc->my_ldata->my_rx_list, 1846 sizeof(sc->my_ldata->my_rx_list)); 1847 /* 1848 * Free the TX list buffers. 1849 */ 1850 for (i = 0; i < MY_TX_LIST_CNT; i++) { 1851 if (sc->my_cdata.my_tx_chain[i].my_mbuf != NULL) { 1852 m_freem(sc->my_cdata.my_tx_chain[i].my_mbuf); 1853 sc->my_cdata.my_tx_chain[i].my_mbuf = NULL; 1854 } 1855 } 1856 bzero((char *)&sc->my_ldata->my_tx_list, 1857 sizeof(sc->my_ldata->my_tx_list)); 1858 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1859 MY_UNLOCK(sc); 1860 return; 1861 } 1862 1863 /* 1864 * Stop all chip I/O so that the kernel's probe routines don't get confused 1865 * by errant DMAs when rebooting. 1866 */ 1867 static void 1868 my_shutdown(device_t dev) 1869 { 1870 struct my_softc *sc; 1871 1872 sc = device_get_softc(dev); 1873 my_stop(sc); 1874 return; 1875 } 1876 1877 1878