1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Written by: yen_cw@myson.com.tw 5 * Copyright (c) 2002 Myson Technology Inc. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions, and the following disclaimer, 13 * without modification, immediately at the beginning of the file. 14 * 2. The name of the author may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 21 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * Myson fast ethernet PCI NIC driver, available at: http://www.myson.com.tw/ 30 */ 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/sockio.h> 35 #include <sys/mbuf.h> 36 #include <sys/malloc.h> 37 #include <sys/kernel.h> 38 #include <sys/socket.h> 39 #include <sys/queue.h> 40 #include <sys/types.h> 41 #include <sys/module.h> 42 #include <sys/lock.h> 43 #include <sys/mutex.h> 44 45 #define NBPFILTER 1 46 47 #include <net/if.h> 48 #include <net/if_var.h> 49 #include <net/if_arp.h> 50 #include <net/ethernet.h> 51 #include <net/if_media.h> 52 #include <net/if_types.h> 53 #include <net/if_dl.h> 54 #include <net/bpf.h> 55 56 #include <vm/vm.h> /* for vtophys */ 57 #include <vm/pmap.h> /* for vtophys */ 58 #include <machine/bus.h> 59 #include <machine/resource.h> 60 #include <sys/bus.h> 61 #include <sys/rman.h> 62 63 #include <dev/pci/pcireg.h> 64 #include <dev/pci/pcivar.h> 65 66 /* 67 * #define MY_USEIOSPACE 68 */ 69 70 static int MY_USEIOSPACE = 1; 71 72 #ifdef MY_USEIOSPACE 73 #define MY_RES SYS_RES_IOPORT 74 #define MY_RID MY_PCI_LOIO 75 #else 76 #define MY_RES SYS_RES_MEMORY 77 #define MY_RID MY_PCI_LOMEM 78 #endif 79 80 #include <dev/my/if_myreg.h> 81 82 /* 83 * Various supported device vendors/types and their names. 84 */ 85 struct my_type *my_info_tmp; 86 static struct my_type my_devs[] = { 87 {MYSONVENDORID, MTD800ID, "Myson MTD80X Based Fast Ethernet Card"}, 88 {MYSONVENDORID, MTD803ID, "Myson MTD80X Based Fast Ethernet Card"}, 89 {MYSONVENDORID, MTD891ID, "Myson MTD89X Based Giga Ethernet Card"}, 90 {0, 0, NULL} 91 }; 92 93 /* 94 * Various supported PHY vendors/types and their names. Note that this driver 95 * will work with pretty much any MII-compliant PHY, so failure to positively 96 * identify the chip is not a fatal error. 97 */ 98 static struct my_type my_phys[] = { 99 {MysonPHYID0, MysonPHYID0, "<MYSON MTD981>"}, 100 {SeeqPHYID0, SeeqPHYID0, "<SEEQ 80225>"}, 101 {AhdocPHYID0, AhdocPHYID0, "<AHDOC 101>"}, 102 {MarvellPHYID0, MarvellPHYID0, "<MARVELL 88E1000>"}, 103 {LevelOnePHYID0, LevelOnePHYID0, "<LevelOne LXT1000>"}, 104 {0, 0, "<MII-compliant physical interface>"} 105 }; 106 107 static int my_probe(device_t); 108 static int my_attach(device_t); 109 static int my_detach(device_t); 110 static int my_newbuf(struct my_softc *, struct my_chain_onefrag *); 111 static int my_encap(struct my_softc *, struct my_chain *, struct mbuf *); 112 static void my_rxeof(struct my_softc *); 113 static void my_txeof(struct my_softc *); 114 static void my_txeoc(struct my_softc *); 115 static void my_intr(void *); 116 static void my_start(if_t); 117 static void my_start_locked(if_t); 118 static int my_ioctl(if_t, u_long, caddr_t); 119 static void my_init(void *); 120 static void my_init_locked(struct my_softc *); 121 static void my_stop(struct my_softc *); 122 static void my_autoneg_timeout(void *); 123 static void my_watchdog(void *); 124 static int my_shutdown(device_t); 125 static int my_ifmedia_upd(if_t); 126 static void my_ifmedia_sts(if_t, struct ifmediareq *); 127 static u_int16_t my_phy_readreg(struct my_softc *, int); 128 static void my_phy_writereg(struct my_softc *, int, int); 129 static void my_autoneg_xmit(struct my_softc *); 130 static void my_autoneg_mii(struct my_softc *, int, int); 131 static void my_setmode_mii(struct my_softc *, int); 132 static void my_getmode_mii(struct my_softc *); 133 static void my_setcfg(struct my_softc *, int); 134 static void my_setmulti(struct my_softc *); 135 static void my_reset(struct my_softc *); 136 static int my_list_rx_init(struct my_softc *); 137 static int my_list_tx_init(struct my_softc *); 138 static long my_send_cmd_to_phy(struct my_softc *, int, int); 139 140 #define MY_SETBIT(sc, reg, x) CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x)) 141 #define MY_CLRBIT(sc, reg, x) CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x)) 142 143 static device_method_t my_methods[] = { 144 /* Device interface */ 145 DEVMETHOD(device_probe, my_probe), 146 DEVMETHOD(device_attach, my_attach), 147 DEVMETHOD(device_detach, my_detach), 148 DEVMETHOD(device_shutdown, my_shutdown), 149 150 DEVMETHOD_END 151 }; 152 153 static driver_t my_driver = { 154 "my", 155 my_methods, 156 sizeof(struct my_softc) 157 }; 158 159 DRIVER_MODULE(my, pci, my_driver, 0, 0); 160 MODULE_PNP_INFO("U16:vendor;U16:device;D:#", pci, my, my_devs, 161 nitems(my_devs) - 1); 162 MODULE_DEPEND(my, pci, 1, 1, 1); 163 MODULE_DEPEND(my, ether, 1, 1, 1); 164 165 static long 166 my_send_cmd_to_phy(struct my_softc * sc, int opcode, int regad) 167 { 168 long miir; 169 int i; 170 int mask, data; 171 172 MY_LOCK_ASSERT(sc); 173 174 /* enable MII output */ 175 miir = CSR_READ_4(sc, MY_MANAGEMENT); 176 miir &= 0xfffffff0; 177 178 miir |= MY_MASK_MIIR_MII_WRITE + MY_MASK_MIIR_MII_MDO; 179 180 /* send 32 1's preamble */ 181 for (i = 0; i < 32; i++) { 182 /* low MDC; MDO is already high (miir) */ 183 miir &= ~MY_MASK_MIIR_MII_MDC; 184 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 185 186 /* high MDC */ 187 miir |= MY_MASK_MIIR_MII_MDC; 188 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 189 } 190 191 /* calculate ST+OP+PHYAD+REGAD+TA */ 192 data = opcode | (sc->my_phy_addr << 7) | (regad << 2); 193 194 /* sent out */ 195 mask = 0x8000; 196 while (mask) { 197 /* low MDC, prepare MDO */ 198 miir &= ~(MY_MASK_MIIR_MII_MDC + MY_MASK_MIIR_MII_MDO); 199 if (mask & data) 200 miir |= MY_MASK_MIIR_MII_MDO; 201 202 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 203 /* high MDC */ 204 miir |= MY_MASK_MIIR_MII_MDC; 205 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 206 DELAY(30); 207 208 /* next */ 209 mask >>= 1; 210 if (mask == 0x2 && opcode == MY_OP_READ) 211 miir &= ~MY_MASK_MIIR_MII_WRITE; 212 } 213 214 return miir; 215 } 216 217 static u_int16_t 218 my_phy_readreg(struct my_softc * sc, int reg) 219 { 220 long miir; 221 int mask, data; 222 223 MY_LOCK_ASSERT(sc); 224 225 if (sc->my_info->my_did == MTD803ID) 226 data = CSR_READ_2(sc, MY_PHYBASE + reg * 2); 227 else { 228 miir = my_send_cmd_to_phy(sc, MY_OP_READ, reg); 229 230 /* read data */ 231 mask = 0x8000; 232 data = 0; 233 while (mask) { 234 /* low MDC */ 235 miir &= ~MY_MASK_MIIR_MII_MDC; 236 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 237 238 /* read MDI */ 239 miir = CSR_READ_4(sc, MY_MANAGEMENT); 240 if (miir & MY_MASK_MIIR_MII_MDI) 241 data |= mask; 242 243 /* high MDC, and wait */ 244 miir |= MY_MASK_MIIR_MII_MDC; 245 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 246 DELAY(30); 247 248 /* next */ 249 mask >>= 1; 250 } 251 252 /* low MDC */ 253 miir &= ~MY_MASK_MIIR_MII_MDC; 254 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 255 } 256 257 return (u_int16_t) data; 258 } 259 260 static void 261 my_phy_writereg(struct my_softc * sc, int reg, int data) 262 { 263 long miir; 264 int mask; 265 266 MY_LOCK_ASSERT(sc); 267 268 if (sc->my_info->my_did == MTD803ID) 269 CSR_WRITE_2(sc, MY_PHYBASE + reg * 2, data); 270 else { 271 miir = my_send_cmd_to_phy(sc, MY_OP_WRITE, reg); 272 273 /* write data */ 274 mask = 0x8000; 275 while (mask) { 276 /* low MDC, prepare MDO */ 277 miir &= ~(MY_MASK_MIIR_MII_MDC + MY_MASK_MIIR_MII_MDO); 278 if (mask & data) 279 miir |= MY_MASK_MIIR_MII_MDO; 280 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 281 DELAY(1); 282 283 /* high MDC */ 284 miir |= MY_MASK_MIIR_MII_MDC; 285 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 286 DELAY(1); 287 288 /* next */ 289 mask >>= 1; 290 } 291 292 /* low MDC */ 293 miir &= ~MY_MASK_MIIR_MII_MDC; 294 CSR_WRITE_4(sc, MY_MANAGEMENT, miir); 295 } 296 return; 297 } 298 299 static u_int 300 my_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) 301 { 302 uint32_t *hashes = arg; 303 int h; 304 305 h = ~ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN) >> 26; 306 if (h < 32) 307 hashes[0] |= (1 << h); 308 else 309 hashes[1] |= (1 << (h - 32)); 310 311 return (1); 312 } 313 /* 314 * Program the 64-bit multicast hash filter. 315 */ 316 static void 317 my_setmulti(struct my_softc * sc) 318 { 319 if_t ifp; 320 u_int32_t hashes[2] = {0, 0}; 321 u_int32_t rxfilt; 322 323 MY_LOCK_ASSERT(sc); 324 325 ifp = sc->my_ifp; 326 327 rxfilt = CSR_READ_4(sc, MY_TCRRCR); 328 329 if (if_getflags(ifp) & IFF_ALLMULTI || if_getflags(ifp) & IFF_PROMISC) { 330 rxfilt |= MY_AM; 331 CSR_WRITE_4(sc, MY_TCRRCR, rxfilt); 332 CSR_WRITE_4(sc, MY_MAR0, 0xFFFFFFFF); 333 CSR_WRITE_4(sc, MY_MAR1, 0xFFFFFFFF); 334 335 return; 336 } 337 /* first, zot all the existing hash bits */ 338 CSR_WRITE_4(sc, MY_MAR0, 0); 339 CSR_WRITE_4(sc, MY_MAR1, 0); 340 341 /* now program new ones */ 342 if (if_foreach_llmaddr(ifp, my_hash_maddr, hashes) > 0) 343 rxfilt |= MY_AM; 344 else 345 rxfilt &= ~MY_AM; 346 CSR_WRITE_4(sc, MY_MAR0, hashes[0]); 347 CSR_WRITE_4(sc, MY_MAR1, hashes[1]); 348 CSR_WRITE_4(sc, MY_TCRRCR, rxfilt); 349 } 350 351 /* 352 * Initiate an autonegotiation session. 353 */ 354 static void 355 my_autoneg_xmit(struct my_softc * sc) 356 { 357 u_int16_t phy_sts = 0; 358 359 MY_LOCK_ASSERT(sc); 360 361 my_phy_writereg(sc, PHY_BMCR, PHY_BMCR_RESET); 362 DELAY(500); 363 while (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_RESET); 364 365 phy_sts = my_phy_readreg(sc, PHY_BMCR); 366 phy_sts |= PHY_BMCR_AUTONEGENBL | PHY_BMCR_AUTONEGRSTR; 367 my_phy_writereg(sc, PHY_BMCR, phy_sts); 368 369 return; 370 } 371 372 static void 373 my_autoneg_timeout(void *arg) 374 { 375 struct my_softc *sc; 376 377 sc = arg; 378 MY_LOCK_ASSERT(sc); 379 my_autoneg_mii(sc, MY_FLAG_DELAYTIMEO, 1); 380 } 381 382 /* 383 * Invoke autonegotiation on a PHY. 384 */ 385 static void 386 my_autoneg_mii(struct my_softc * sc, int flag, int verbose) 387 { 388 u_int16_t phy_sts = 0, media, advert, ability; 389 u_int16_t ability2 = 0; 390 if_t ifp; 391 struct ifmedia *ifm; 392 393 MY_LOCK_ASSERT(sc); 394 395 ifm = &sc->ifmedia; 396 ifp = sc->my_ifp; 397 398 ifm->ifm_media = IFM_ETHER | IFM_AUTO; 399 400 #ifndef FORCE_AUTONEG_TFOUR 401 /* 402 * First, see if autoneg is supported. If not, there's no point in 403 * continuing. 404 */ 405 phy_sts = my_phy_readreg(sc, PHY_BMSR); 406 if (!(phy_sts & PHY_BMSR_CANAUTONEG)) { 407 if (verbose) 408 device_printf(sc->my_dev, 409 "autonegotiation not supported\n"); 410 ifm->ifm_media = IFM_ETHER | IFM_10_T | IFM_HDX; 411 return; 412 } 413 #endif 414 switch (flag) { 415 case MY_FLAG_FORCEDELAY: 416 /* 417 * XXX Never use this option anywhere but in the probe 418 * routine: making the kernel stop dead in its tracks for 419 * three whole seconds after we've gone multi-user is really 420 * bad manners. 421 */ 422 my_autoneg_xmit(sc); 423 DELAY(5000000); 424 break; 425 case MY_FLAG_SCHEDDELAY: 426 /* 427 * Wait for the transmitter to go idle before starting an 428 * autoneg session, otherwise my_start() may clobber our 429 * timeout, and we don't want to allow transmission during an 430 * autoneg session since that can screw it up. 431 */ 432 if (sc->my_cdata.my_tx_head != NULL) { 433 sc->my_want_auto = 1; 434 MY_UNLOCK(sc); 435 return; 436 } 437 my_autoneg_xmit(sc); 438 callout_reset(&sc->my_autoneg_timer, hz * 5, my_autoneg_timeout, 439 sc); 440 sc->my_autoneg = 1; 441 sc->my_want_auto = 0; 442 return; 443 case MY_FLAG_DELAYTIMEO: 444 callout_stop(&sc->my_autoneg_timer); 445 sc->my_autoneg = 0; 446 break; 447 default: 448 device_printf(sc->my_dev, "invalid autoneg flag: %d\n", flag); 449 return; 450 } 451 452 if (my_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_AUTONEGCOMP) { 453 if (verbose) 454 device_printf(sc->my_dev, "autoneg complete, "); 455 phy_sts = my_phy_readreg(sc, PHY_BMSR); 456 } else { 457 if (verbose) 458 device_printf(sc->my_dev, "autoneg not complete, "); 459 } 460 461 media = my_phy_readreg(sc, PHY_BMCR); 462 463 /* Link is good. Report modes and set duplex mode. */ 464 if (my_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT) { 465 if (verbose) 466 device_printf(sc->my_dev, "link status good. "); 467 advert = my_phy_readreg(sc, PHY_ANAR); 468 ability = my_phy_readreg(sc, PHY_LPAR); 469 if ((sc->my_pinfo->my_vid == MarvellPHYID0) || 470 (sc->my_pinfo->my_vid == LevelOnePHYID0)) { 471 ability2 = my_phy_readreg(sc, PHY_1000SR); 472 if (ability2 & PHY_1000SR_1000BTXFULL) { 473 advert = 0; 474 ability = 0; 475 /* 476 * this version did not support 1000M, 477 * ifm->ifm_media = 478 * IFM_ETHER|IFM_1000_T|IFM_FDX; 479 */ 480 ifm->ifm_media = 481 IFM_ETHER | IFM_100_TX | IFM_FDX; 482 media &= ~PHY_BMCR_SPEEDSEL; 483 media |= PHY_BMCR_1000; 484 media |= PHY_BMCR_DUPLEX; 485 printf("(full-duplex, 1000Mbps)\n"); 486 } else if (ability2 & PHY_1000SR_1000BTXHALF) { 487 advert = 0; 488 ability = 0; 489 /* 490 * this version did not support 1000M, 491 * ifm->ifm_media = IFM_ETHER|IFM_1000_T; 492 */ 493 ifm->ifm_media = IFM_ETHER | IFM_100_TX; 494 media &= ~PHY_BMCR_SPEEDSEL; 495 media &= ~PHY_BMCR_DUPLEX; 496 media |= PHY_BMCR_1000; 497 printf("(half-duplex, 1000Mbps)\n"); 498 } 499 } 500 if (advert & PHY_ANAR_100BT4 && ability & PHY_ANAR_100BT4) { 501 ifm->ifm_media = IFM_ETHER | IFM_100_T4; 502 media |= PHY_BMCR_SPEEDSEL; 503 media &= ~PHY_BMCR_DUPLEX; 504 printf("(100baseT4)\n"); 505 } else if (advert & PHY_ANAR_100BTXFULL && 506 ability & PHY_ANAR_100BTXFULL) { 507 ifm->ifm_media = IFM_ETHER | IFM_100_TX | IFM_FDX; 508 media |= PHY_BMCR_SPEEDSEL; 509 media |= PHY_BMCR_DUPLEX; 510 printf("(full-duplex, 100Mbps)\n"); 511 } else if (advert & PHY_ANAR_100BTXHALF && 512 ability & PHY_ANAR_100BTXHALF) { 513 ifm->ifm_media = IFM_ETHER | IFM_100_TX | IFM_HDX; 514 media |= PHY_BMCR_SPEEDSEL; 515 media &= ~PHY_BMCR_DUPLEX; 516 printf("(half-duplex, 100Mbps)\n"); 517 } else if (advert & PHY_ANAR_10BTFULL && 518 ability & PHY_ANAR_10BTFULL) { 519 ifm->ifm_media = IFM_ETHER | IFM_10_T | IFM_FDX; 520 media &= ~PHY_BMCR_SPEEDSEL; 521 media |= PHY_BMCR_DUPLEX; 522 printf("(full-duplex, 10Mbps)\n"); 523 } else if (advert) { 524 ifm->ifm_media = IFM_ETHER | IFM_10_T | IFM_HDX; 525 media &= ~PHY_BMCR_SPEEDSEL; 526 media &= ~PHY_BMCR_DUPLEX; 527 printf("(half-duplex, 10Mbps)\n"); 528 } 529 media &= ~PHY_BMCR_AUTONEGENBL; 530 531 /* Set ASIC's duplex mode to match the PHY. */ 532 my_phy_writereg(sc, PHY_BMCR, media); 533 my_setcfg(sc, media); 534 } else { 535 if (verbose) 536 device_printf(sc->my_dev, "no carrier\n"); 537 } 538 539 my_init_locked(sc); 540 if (sc->my_tx_pend) { 541 sc->my_autoneg = 0; 542 sc->my_tx_pend = 0; 543 my_start_locked(ifp); 544 } 545 return; 546 } 547 548 /* 549 * To get PHY ability. 550 */ 551 static void 552 my_getmode_mii(struct my_softc * sc) 553 { 554 u_int16_t bmsr; 555 if_t ifp; 556 557 MY_LOCK_ASSERT(sc); 558 ifp = sc->my_ifp; 559 bmsr = my_phy_readreg(sc, PHY_BMSR); 560 if (bootverbose) 561 device_printf(sc->my_dev, "PHY status word: %x\n", bmsr); 562 563 /* fallback */ 564 sc->ifmedia.ifm_media = IFM_ETHER | IFM_10_T | IFM_HDX; 565 566 if (bmsr & PHY_BMSR_10BTHALF) { 567 if (bootverbose) 568 device_printf(sc->my_dev, 569 "10Mbps half-duplex mode supported\n"); 570 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_10_T | IFM_HDX, 571 0, NULL); 572 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_10_T, 0, NULL); 573 } 574 if (bmsr & PHY_BMSR_10BTFULL) { 575 if (bootverbose) 576 device_printf(sc->my_dev, 577 "10Mbps full-duplex mode supported\n"); 578 579 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_10_T | IFM_FDX, 580 0, NULL); 581 sc->ifmedia.ifm_media = IFM_ETHER | IFM_10_T | IFM_FDX; 582 } 583 if (bmsr & PHY_BMSR_100BTXHALF) { 584 if (bootverbose) 585 device_printf(sc->my_dev, 586 "100Mbps half-duplex mode supported\n"); 587 if_setbaudrate(ifp, 100000000); 588 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_TX, 0, NULL); 589 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_TX | IFM_HDX, 590 0, NULL); 591 sc->ifmedia.ifm_media = IFM_ETHER | IFM_100_TX | IFM_HDX; 592 } 593 if (bmsr & PHY_BMSR_100BTXFULL) { 594 if (bootverbose) 595 device_printf(sc->my_dev, 596 "100Mbps full-duplex mode supported\n"); 597 if_setbaudrate(ifp, 100000000); 598 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_TX | IFM_FDX, 599 0, NULL); 600 sc->ifmedia.ifm_media = IFM_ETHER | IFM_100_TX | IFM_FDX; 601 } 602 /* Some also support 100BaseT4. */ 603 if (bmsr & PHY_BMSR_100BT4) { 604 if (bootverbose) 605 device_printf(sc->my_dev, "100baseT4 mode supported\n"); 606 if_setbaudrate(ifp, 100000000); 607 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_T4, 0, NULL); 608 sc->ifmedia.ifm_media = IFM_ETHER | IFM_100_T4; 609 #ifdef FORCE_AUTONEG_TFOUR 610 if (bootverbose) 611 device_printf(sc->my_dev, 612 "forcing on autoneg support for BT4\n"); 613 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_AUTO, 0 NULL): 614 sc->ifmedia.ifm_media = IFM_ETHER | IFM_AUTO; 615 #endif 616 } 617 #if 0 /* this version did not support 1000M, */ 618 if (sc->my_pinfo->my_vid == MarvellPHYID0) { 619 if (bootverbose) 620 device_printf(sc->my_dev, 621 "1000Mbps half-duplex mode supported\n"); 622 623 if_setbaudrate(ifp, 1000000000); 624 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_T, 0, NULL); 625 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_T | IFM_HDX, 626 0, NULL); 627 if (bootverbose) 628 device_printf(sc->my_dev, 629 "1000Mbps full-duplex mode supported\n"); 630 if_setbaudrate(ifp, 1000000000); 631 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_T | IFM_FDX, 632 0, NULL); 633 sc->ifmedia.ifm_media = IFM_ETHER | IFM_1000_T | IFM_FDX; 634 } 635 #endif 636 if (bmsr & PHY_BMSR_CANAUTONEG) { 637 if (bootverbose) 638 device_printf(sc->my_dev, "autoneg supported\n"); 639 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 640 sc->ifmedia.ifm_media = IFM_ETHER | IFM_AUTO; 641 } 642 return; 643 } 644 645 /* 646 * Set speed and duplex mode. 647 */ 648 static void 649 my_setmode_mii(struct my_softc * sc, int media) 650 { 651 u_int16_t bmcr; 652 653 MY_LOCK_ASSERT(sc); 654 /* 655 * If an autoneg session is in progress, stop it. 656 */ 657 if (sc->my_autoneg) { 658 device_printf(sc->my_dev, "canceling autoneg session\n"); 659 callout_stop(&sc->my_autoneg_timer); 660 sc->my_autoneg = sc->my_want_auto = 0; 661 bmcr = my_phy_readreg(sc, PHY_BMCR); 662 bmcr &= ~PHY_BMCR_AUTONEGENBL; 663 my_phy_writereg(sc, PHY_BMCR, bmcr); 664 } 665 device_printf(sc->my_dev, "selecting MII, "); 666 bmcr = my_phy_readreg(sc, PHY_BMCR); 667 bmcr &= ~(PHY_BMCR_AUTONEGENBL | PHY_BMCR_SPEEDSEL | PHY_BMCR_1000 | 668 PHY_BMCR_DUPLEX | PHY_BMCR_LOOPBK); 669 670 #if 0 /* this version did not support 1000M, */ 671 if (IFM_SUBTYPE(media) == IFM_1000_T) { 672 printf("1000Mbps/T4, half-duplex\n"); 673 bmcr &= ~PHY_BMCR_SPEEDSEL; 674 bmcr &= ~PHY_BMCR_DUPLEX; 675 bmcr |= PHY_BMCR_1000; 676 } 677 #endif 678 if (IFM_SUBTYPE(media) == IFM_100_T4) { 679 printf("100Mbps/T4, half-duplex\n"); 680 bmcr |= PHY_BMCR_SPEEDSEL; 681 bmcr &= ~PHY_BMCR_DUPLEX; 682 } 683 if (IFM_SUBTYPE(media) == IFM_100_TX) { 684 printf("100Mbps, "); 685 bmcr |= PHY_BMCR_SPEEDSEL; 686 } 687 if (IFM_SUBTYPE(media) == IFM_10_T) { 688 printf("10Mbps, "); 689 bmcr &= ~PHY_BMCR_SPEEDSEL; 690 } 691 if ((media & IFM_GMASK) == IFM_FDX) { 692 printf("full duplex\n"); 693 bmcr |= PHY_BMCR_DUPLEX; 694 } else { 695 printf("half duplex\n"); 696 bmcr &= ~PHY_BMCR_DUPLEX; 697 } 698 my_phy_writereg(sc, PHY_BMCR, bmcr); 699 my_setcfg(sc, bmcr); 700 return; 701 } 702 703 /* 704 * The Myson manual states that in order to fiddle with the 'full-duplex' and 705 * '100Mbps' bits in the netconfig register, we first have to put the 706 * transmit and/or receive logic in the idle state. 707 */ 708 static void 709 my_setcfg(struct my_softc * sc, int bmcr) 710 { 711 int i, restart = 0; 712 713 MY_LOCK_ASSERT(sc); 714 if (CSR_READ_4(sc, MY_TCRRCR) & (MY_TE | MY_RE)) { 715 restart = 1; 716 MY_CLRBIT(sc, MY_TCRRCR, (MY_TE | MY_RE)); 717 for (i = 0; i < MY_TIMEOUT; i++) { 718 DELAY(10); 719 if (!(CSR_READ_4(sc, MY_TCRRCR) & 720 (MY_TXRUN | MY_RXRUN))) 721 break; 722 } 723 if (i == MY_TIMEOUT) 724 device_printf(sc->my_dev, 725 "failed to force tx and rx to idle \n"); 726 } 727 MY_CLRBIT(sc, MY_TCRRCR, MY_PS1000); 728 MY_CLRBIT(sc, MY_TCRRCR, MY_PS10); 729 if (bmcr & PHY_BMCR_1000) 730 MY_SETBIT(sc, MY_TCRRCR, MY_PS1000); 731 else if (!(bmcr & PHY_BMCR_SPEEDSEL)) 732 MY_SETBIT(sc, MY_TCRRCR, MY_PS10); 733 if (bmcr & PHY_BMCR_DUPLEX) 734 MY_SETBIT(sc, MY_TCRRCR, MY_FD); 735 else 736 MY_CLRBIT(sc, MY_TCRRCR, MY_FD); 737 if (restart) 738 MY_SETBIT(sc, MY_TCRRCR, MY_TE | MY_RE); 739 return; 740 } 741 742 static void 743 my_reset(struct my_softc * sc) 744 { 745 int i; 746 747 MY_LOCK_ASSERT(sc); 748 MY_SETBIT(sc, MY_BCR, MY_SWR); 749 for (i = 0; i < MY_TIMEOUT; i++) { 750 DELAY(10); 751 if (!(CSR_READ_4(sc, MY_BCR) & MY_SWR)) 752 break; 753 } 754 if (i == MY_TIMEOUT) 755 device_printf(sc->my_dev, "reset never completed!\n"); 756 757 /* Wait a little while for the chip to get its brains in order. */ 758 DELAY(1000); 759 return; 760 } 761 762 /* 763 * Probe for a Myson chip. Check the PCI vendor and device IDs against our 764 * list and return a device name if we find a match. 765 */ 766 static int 767 my_probe(device_t dev) 768 { 769 struct my_type *t; 770 771 t = my_devs; 772 while (t->my_name != NULL) { 773 if ((pci_get_vendor(dev) == t->my_vid) && 774 (pci_get_device(dev) == t->my_did)) { 775 device_set_desc(dev, t->my_name); 776 my_info_tmp = t; 777 return (BUS_PROBE_DEFAULT); 778 } 779 t++; 780 } 781 return (ENXIO); 782 } 783 784 /* 785 * Attach the interface. Allocate softc structures, do ifmedia setup and 786 * ethernet/BPF attach. 787 */ 788 static int 789 my_attach(device_t dev) 790 { 791 int i; 792 u_char eaddr[ETHER_ADDR_LEN]; 793 u_int32_t iobase; 794 struct my_softc *sc; 795 if_t ifp; 796 int media = IFM_ETHER | IFM_100_TX | IFM_FDX; 797 unsigned int round; 798 caddr_t roundptr; 799 struct my_type *p; 800 u_int16_t phy_vid, phy_did, phy_sts = 0; 801 int rid, error = 0; 802 803 sc = device_get_softc(dev); 804 sc->my_dev = dev; 805 mtx_init(&sc->my_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 806 MTX_DEF); 807 callout_init_mtx(&sc->my_autoneg_timer, &sc->my_mtx, 0); 808 callout_init_mtx(&sc->my_watchdog, &sc->my_mtx, 0); 809 810 /* 811 * Map control/status registers. 812 */ 813 pci_enable_busmaster(dev); 814 815 if (my_info_tmp->my_did == MTD800ID) { 816 iobase = pci_read_config(dev, MY_PCI_LOIO, 4); 817 if (iobase & 0x300) 818 MY_USEIOSPACE = 0; 819 } 820 821 rid = MY_RID; 822 sc->my_res = bus_alloc_resource_any(dev, MY_RES, &rid, RF_ACTIVE); 823 824 if (sc->my_res == NULL) { 825 device_printf(dev, "couldn't map ports/memory\n"); 826 error = ENXIO; 827 goto destroy_mutex; 828 } 829 sc->my_btag = rman_get_bustag(sc->my_res); 830 sc->my_bhandle = rman_get_bushandle(sc->my_res); 831 832 rid = 0; 833 sc->my_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 834 RF_SHAREABLE | RF_ACTIVE); 835 836 if (sc->my_irq == NULL) { 837 device_printf(dev, "couldn't map interrupt\n"); 838 error = ENXIO; 839 goto release_io; 840 } 841 842 sc->my_info = my_info_tmp; 843 844 /* Reset the adapter. */ 845 MY_LOCK(sc); 846 my_reset(sc); 847 MY_UNLOCK(sc); 848 849 /* 850 * Get station address 851 */ 852 for (i = 0; i < ETHER_ADDR_LEN; ++i) 853 eaddr[i] = CSR_READ_1(sc, MY_PAR0 + i); 854 855 sc->my_ldata_ptr = malloc(sizeof(struct my_list_data) + 8, 856 M_DEVBUF, M_NOWAIT); 857 if (sc->my_ldata_ptr == NULL) { 858 device_printf(dev, "no memory for list buffers!\n"); 859 error = ENXIO; 860 goto release_irq; 861 } 862 sc->my_ldata = (struct my_list_data *) sc->my_ldata_ptr; 863 round = (uintptr_t)sc->my_ldata_ptr & 0xF; 864 roundptr = sc->my_ldata_ptr; 865 for (i = 0; i < 8; i++) { 866 if (round % 8) { 867 round++; 868 roundptr++; 869 } else 870 break; 871 } 872 sc->my_ldata = (struct my_list_data *) roundptr; 873 bzero(sc->my_ldata, sizeof(struct my_list_data)); 874 875 ifp = sc->my_ifp = if_alloc(IFT_ETHER); 876 if (ifp == NULL) { 877 device_printf(dev, "can not if_alloc()\n"); 878 error = ENOSPC; 879 goto free_ldata; 880 } 881 if_setsoftc(ifp, sc); 882 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 883 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 884 if_setioctlfn(ifp, my_ioctl); 885 if_setstartfn(ifp, my_start); 886 if_setinitfn(ifp, my_init); 887 if_setbaudrate(ifp, 10000000); 888 if_setsendqlen(ifp, ifqmaxlen); 889 if_setsendqready(ifp); 890 891 if (sc->my_info->my_did == MTD803ID) 892 sc->my_pinfo = my_phys; 893 else { 894 if (bootverbose) 895 device_printf(dev, "probing for a PHY\n"); 896 MY_LOCK(sc); 897 for (i = MY_PHYADDR_MIN; i < MY_PHYADDR_MAX + 1; i++) { 898 if (bootverbose) 899 device_printf(dev, "checking address: %d\n", i); 900 sc->my_phy_addr = i; 901 phy_sts = my_phy_readreg(sc, PHY_BMSR); 902 if ((phy_sts != 0) && (phy_sts != 0xffff)) 903 break; 904 else 905 phy_sts = 0; 906 } 907 if (phy_sts) { 908 phy_vid = my_phy_readreg(sc, PHY_VENID); 909 phy_did = my_phy_readreg(sc, PHY_DEVID); 910 if (bootverbose) { 911 device_printf(dev, "found PHY at address %d, ", 912 sc->my_phy_addr); 913 printf("vendor id: %x device id: %x\n", 914 phy_vid, phy_did); 915 } 916 p = my_phys; 917 while (p->my_vid) { 918 if (phy_vid == p->my_vid) { 919 sc->my_pinfo = p; 920 break; 921 } 922 p++; 923 } 924 if (sc->my_pinfo == NULL) 925 sc->my_pinfo = &my_phys[PHY_UNKNOWN]; 926 if (bootverbose) 927 device_printf(dev, "PHY type: %s\n", 928 sc->my_pinfo->my_name); 929 } else { 930 MY_UNLOCK(sc); 931 device_printf(dev, "MII without any phy!\n"); 932 error = ENXIO; 933 goto free_if; 934 } 935 MY_UNLOCK(sc); 936 } 937 938 /* Do ifmedia setup. */ 939 ifmedia_init(&sc->ifmedia, 0, my_ifmedia_upd, my_ifmedia_sts); 940 MY_LOCK(sc); 941 my_getmode_mii(sc); 942 my_autoneg_mii(sc, MY_FLAG_FORCEDELAY, 1); 943 media = sc->ifmedia.ifm_media; 944 my_stop(sc); 945 MY_UNLOCK(sc); 946 ifmedia_set(&sc->ifmedia, media); 947 948 ether_ifattach(ifp, eaddr); 949 950 error = bus_setup_intr(dev, sc->my_irq, INTR_TYPE_NET | INTR_MPSAFE, 951 NULL, my_intr, sc, &sc->my_intrhand); 952 953 if (error) { 954 device_printf(dev, "couldn't set up irq\n"); 955 goto detach_if; 956 } 957 958 return (0); 959 960 detach_if: 961 ether_ifdetach(ifp); 962 free_if: 963 if_free(ifp); 964 free_ldata: 965 free(sc->my_ldata_ptr, M_DEVBUF); 966 release_irq: 967 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->my_irq); 968 release_io: 969 bus_release_resource(dev, MY_RES, MY_RID, sc->my_res); 970 destroy_mutex: 971 mtx_destroy(&sc->my_mtx); 972 return (error); 973 } 974 975 static int 976 my_detach(device_t dev) 977 { 978 struct my_softc *sc; 979 if_t ifp; 980 981 sc = device_get_softc(dev); 982 ifp = sc->my_ifp; 983 ether_ifdetach(ifp); 984 MY_LOCK(sc); 985 my_stop(sc); 986 MY_UNLOCK(sc); 987 bus_teardown_intr(dev, sc->my_irq, sc->my_intrhand); 988 callout_drain(&sc->my_watchdog); 989 callout_drain(&sc->my_autoneg_timer); 990 991 if_free(ifp); 992 free(sc->my_ldata_ptr, M_DEVBUF); 993 994 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->my_irq); 995 bus_release_resource(dev, MY_RES, MY_RID, sc->my_res); 996 mtx_destroy(&sc->my_mtx); 997 return (0); 998 } 999 1000 /* 1001 * Initialize the transmit descriptors. 1002 */ 1003 static int 1004 my_list_tx_init(struct my_softc * sc) 1005 { 1006 struct my_chain_data *cd; 1007 struct my_list_data *ld; 1008 int i; 1009 1010 MY_LOCK_ASSERT(sc); 1011 cd = &sc->my_cdata; 1012 ld = sc->my_ldata; 1013 for (i = 0; i < MY_TX_LIST_CNT; i++) { 1014 cd->my_tx_chain[i].my_ptr = &ld->my_tx_list[i]; 1015 if (i == (MY_TX_LIST_CNT - 1)) 1016 cd->my_tx_chain[i].my_nextdesc = &cd->my_tx_chain[0]; 1017 else 1018 cd->my_tx_chain[i].my_nextdesc = 1019 &cd->my_tx_chain[i + 1]; 1020 } 1021 cd->my_tx_free = &cd->my_tx_chain[0]; 1022 cd->my_tx_tail = cd->my_tx_head = NULL; 1023 return (0); 1024 } 1025 1026 /* 1027 * Initialize the RX descriptors and allocate mbufs for them. Note that we 1028 * arrange the descriptors in a closed ring, so that the last descriptor 1029 * points back to the first. 1030 */ 1031 static int 1032 my_list_rx_init(struct my_softc * sc) 1033 { 1034 struct my_chain_data *cd; 1035 struct my_list_data *ld; 1036 int i; 1037 1038 MY_LOCK_ASSERT(sc); 1039 cd = &sc->my_cdata; 1040 ld = sc->my_ldata; 1041 for (i = 0; i < MY_RX_LIST_CNT; i++) { 1042 cd->my_rx_chain[i].my_ptr = 1043 (struct my_desc *) & ld->my_rx_list[i]; 1044 if (my_newbuf(sc, &cd->my_rx_chain[i]) == ENOBUFS) { 1045 MY_UNLOCK(sc); 1046 return (ENOBUFS); 1047 } 1048 if (i == (MY_RX_LIST_CNT - 1)) { 1049 cd->my_rx_chain[i].my_nextdesc = &cd->my_rx_chain[0]; 1050 ld->my_rx_list[i].my_next = vtophys(&ld->my_rx_list[0]); 1051 } else { 1052 cd->my_rx_chain[i].my_nextdesc = 1053 &cd->my_rx_chain[i + 1]; 1054 ld->my_rx_list[i].my_next = 1055 vtophys(&ld->my_rx_list[i + 1]); 1056 } 1057 } 1058 cd->my_rx_head = &cd->my_rx_chain[0]; 1059 return (0); 1060 } 1061 1062 /* 1063 * Initialize an RX descriptor and attach an MBUF cluster. 1064 */ 1065 static int 1066 my_newbuf(struct my_softc * sc, struct my_chain_onefrag * c) 1067 { 1068 struct mbuf *m_new = NULL; 1069 1070 MY_LOCK_ASSERT(sc); 1071 MGETHDR(m_new, M_NOWAIT, MT_DATA); 1072 if (m_new == NULL) { 1073 device_printf(sc->my_dev, 1074 "no memory for rx list -- packet dropped!\n"); 1075 return (ENOBUFS); 1076 } 1077 if (!(MCLGET(m_new, M_NOWAIT))) { 1078 device_printf(sc->my_dev, 1079 "no memory for rx list -- packet dropped!\n"); 1080 m_freem(m_new); 1081 return (ENOBUFS); 1082 } 1083 c->my_mbuf = m_new; 1084 c->my_ptr->my_data = vtophys(mtod(m_new, caddr_t)); 1085 c->my_ptr->my_ctl = (MCLBYTES - 1) << MY_RBSShift; 1086 c->my_ptr->my_status = MY_OWNByNIC; 1087 return (0); 1088 } 1089 1090 /* 1091 * A frame has been uploaded: pass the resulting mbuf chain up to the higher 1092 * level protocols. 1093 */ 1094 static void 1095 my_rxeof(struct my_softc * sc) 1096 { 1097 struct ether_header *eh; 1098 struct mbuf *m; 1099 if_t ifp; 1100 struct my_chain_onefrag *cur_rx; 1101 int total_len = 0; 1102 u_int32_t rxstat; 1103 1104 MY_LOCK_ASSERT(sc); 1105 ifp = sc->my_ifp; 1106 while (!((rxstat = sc->my_cdata.my_rx_head->my_ptr->my_status) 1107 & MY_OWNByNIC)) { 1108 cur_rx = sc->my_cdata.my_rx_head; 1109 sc->my_cdata.my_rx_head = cur_rx->my_nextdesc; 1110 1111 if (rxstat & MY_ES) { /* error summary: give up this rx pkt */ 1112 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 1113 cur_rx->my_ptr->my_status = MY_OWNByNIC; 1114 continue; 1115 } 1116 /* No errors; receive the packet. */ 1117 total_len = (rxstat & MY_FLNGMASK) >> MY_FLNGShift; 1118 total_len -= ETHER_CRC_LEN; 1119 1120 if (total_len < MINCLSIZE) { 1121 m = m_devget(mtod(cur_rx->my_mbuf, char *), 1122 total_len, 0, ifp, NULL); 1123 cur_rx->my_ptr->my_status = MY_OWNByNIC; 1124 if (m == NULL) { 1125 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 1126 continue; 1127 } 1128 } else { 1129 m = cur_rx->my_mbuf; 1130 /* 1131 * Try to conjure up a new mbuf cluster. If that 1132 * fails, it means we have an out of memory condition 1133 * and should leave the buffer in place and continue. 1134 * This will result in a lost packet, but there's 1135 * little else we can do in this situation. 1136 */ 1137 if (my_newbuf(sc, cur_rx) == ENOBUFS) { 1138 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 1139 cur_rx->my_ptr->my_status = MY_OWNByNIC; 1140 continue; 1141 } 1142 m->m_pkthdr.rcvif = ifp; 1143 m->m_pkthdr.len = m->m_len = total_len; 1144 } 1145 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 1146 eh = mtod(m, struct ether_header *); 1147 #if NBPFILTER > 0 1148 /* 1149 * Handle BPF listeners. Let the BPF user see the packet, but 1150 * don't pass it up to the ether_input() layer unless it's a 1151 * broadcast packet, multicast packet, matches our ethernet 1152 * address or the interface is in promiscuous mode. 1153 */ 1154 if (bpf_peers_present_if(ifp)) { 1155 bpf_mtap_if(ifp, m); 1156 if (if_getflags(ifp) & IFF_PROMISC && 1157 (bcmp(eh->ether_dhost, if_getlladdr(sc->my_ifp), 1158 ETHER_ADDR_LEN) && 1159 (eh->ether_dhost[0] & 1) == 0)) { 1160 m_freem(m); 1161 continue; 1162 } 1163 } 1164 #endif 1165 MY_UNLOCK(sc); 1166 if_input(ifp, m); 1167 MY_LOCK(sc); 1168 } 1169 return; 1170 } 1171 1172 /* 1173 * A frame was downloaded to the chip. It's safe for us to clean up the list 1174 * buffers. 1175 */ 1176 static void 1177 my_txeof(struct my_softc * sc) 1178 { 1179 struct my_chain *cur_tx; 1180 if_t ifp; 1181 1182 MY_LOCK_ASSERT(sc); 1183 ifp = sc->my_ifp; 1184 /* Clear the timeout timer. */ 1185 sc->my_timer = 0; 1186 if (sc->my_cdata.my_tx_head == NULL) { 1187 return; 1188 } 1189 /* 1190 * Go through our tx list and free mbufs for those frames that have 1191 * been transmitted. 1192 */ 1193 while (sc->my_cdata.my_tx_head->my_mbuf != NULL) { 1194 u_int32_t txstat; 1195 1196 cur_tx = sc->my_cdata.my_tx_head; 1197 txstat = MY_TXSTATUS(cur_tx); 1198 if ((txstat & MY_OWNByNIC) || txstat == MY_UNSENT) 1199 break; 1200 if (!(CSR_READ_4(sc, MY_TCRRCR) & MY_Enhanced)) { 1201 if (txstat & MY_TXERR) { 1202 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 1203 if (txstat & MY_EC) /* excessive collision */ 1204 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 1); 1205 if (txstat & MY_LC) /* late collision */ 1206 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 1); 1207 } 1208 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 1209 (txstat & MY_NCRMASK) >> MY_NCRShift); 1210 } 1211 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 1212 m_freem(cur_tx->my_mbuf); 1213 cur_tx->my_mbuf = NULL; 1214 if (sc->my_cdata.my_tx_head == sc->my_cdata.my_tx_tail) { 1215 sc->my_cdata.my_tx_head = NULL; 1216 sc->my_cdata.my_tx_tail = NULL; 1217 break; 1218 } 1219 sc->my_cdata.my_tx_head = cur_tx->my_nextdesc; 1220 } 1221 if (CSR_READ_4(sc, MY_TCRRCR) & MY_Enhanced) { 1222 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, (CSR_READ_4(sc, MY_TSR) & MY_NCRMask)); 1223 } 1224 return; 1225 } 1226 1227 /* 1228 * TX 'end of channel' interrupt handler. 1229 */ 1230 static void 1231 my_txeoc(struct my_softc * sc) 1232 { 1233 if_t ifp; 1234 1235 MY_LOCK_ASSERT(sc); 1236 ifp = sc->my_ifp; 1237 sc->my_timer = 0; 1238 if (sc->my_cdata.my_tx_head == NULL) { 1239 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 1240 sc->my_cdata.my_tx_tail = NULL; 1241 if (sc->my_want_auto) 1242 my_autoneg_mii(sc, MY_FLAG_SCHEDDELAY, 1); 1243 } else { 1244 if (MY_TXOWN(sc->my_cdata.my_tx_head) == MY_UNSENT) { 1245 MY_TXOWN(sc->my_cdata.my_tx_head) = MY_OWNByNIC; 1246 sc->my_timer = 5; 1247 CSR_WRITE_4(sc, MY_TXPDR, 0xFFFFFFFF); 1248 } 1249 } 1250 return; 1251 } 1252 1253 static void 1254 my_intr(void *arg) 1255 { 1256 struct my_softc *sc; 1257 if_t ifp; 1258 u_int32_t status; 1259 1260 sc = arg; 1261 MY_LOCK(sc); 1262 ifp = sc->my_ifp; 1263 if (!(if_getflags(ifp) & IFF_UP)) { 1264 MY_UNLOCK(sc); 1265 return; 1266 } 1267 /* Disable interrupts. */ 1268 CSR_WRITE_4(sc, MY_IMR, 0x00000000); 1269 1270 for (;;) { 1271 status = CSR_READ_4(sc, MY_ISR); 1272 status &= MY_INTRS; 1273 if (status) 1274 CSR_WRITE_4(sc, MY_ISR, status); 1275 else 1276 break; 1277 1278 if (status & MY_RI) /* receive interrupt */ 1279 my_rxeof(sc); 1280 1281 if ((status & MY_RBU) || (status & MY_RxErr)) { 1282 /* rx buffer unavailable or rx error */ 1283 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 1284 #ifdef foo 1285 my_stop(sc); 1286 my_reset(sc); 1287 my_init_locked(sc); 1288 #endif 1289 } 1290 if (status & MY_TI) /* tx interrupt */ 1291 my_txeof(sc); 1292 if (status & MY_ETI) /* tx early interrupt */ 1293 my_txeof(sc); 1294 if (status & MY_TBU) /* tx buffer unavailable */ 1295 my_txeoc(sc); 1296 1297 #if 0 /* 90/1/18 delete */ 1298 if (status & MY_FBE) { 1299 my_reset(sc); 1300 my_init_locked(sc); 1301 } 1302 #endif 1303 } 1304 1305 /* Re-enable interrupts. */ 1306 CSR_WRITE_4(sc, MY_IMR, MY_INTRS); 1307 if (!if_sendq_empty(ifp)) 1308 my_start_locked(ifp); 1309 MY_UNLOCK(sc); 1310 return; 1311 } 1312 1313 /* 1314 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1315 * pointers to the fragment pointers. 1316 */ 1317 static int 1318 my_encap(struct my_softc * sc, struct my_chain * c, struct mbuf * m_head) 1319 { 1320 struct my_desc *f = NULL; 1321 int total_len; 1322 struct mbuf *m, *m_new = NULL; 1323 1324 MY_LOCK_ASSERT(sc); 1325 /* calculate the total tx pkt length */ 1326 total_len = 0; 1327 for (m = m_head; m != NULL; m = m->m_next) 1328 total_len += m->m_len; 1329 /* 1330 * Start packing the mbufs in this chain into the fragment pointers. 1331 * Stop when we run out of fragments or hit the end of the mbuf 1332 * chain. 1333 */ 1334 m = m_head; 1335 MGETHDR(m_new, M_NOWAIT, MT_DATA); 1336 if (m_new == NULL) { 1337 device_printf(sc->my_dev, "no memory for tx list"); 1338 return (1); 1339 } 1340 if (m_head->m_pkthdr.len > MHLEN) { 1341 if (!(MCLGET(m_new, M_NOWAIT))) { 1342 m_freem(m_new); 1343 device_printf(sc->my_dev, "no memory for tx list"); 1344 return (1); 1345 } 1346 } 1347 m_copydata(m_head, 0, m_head->m_pkthdr.len, mtod(m_new, caddr_t)); 1348 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1349 m_freem(m_head); 1350 m_head = m_new; 1351 f = &c->my_ptr->my_frag[0]; 1352 f->my_status = 0; 1353 f->my_data = vtophys(mtod(m_new, caddr_t)); 1354 total_len = m_new->m_len; 1355 f->my_ctl = MY_TXFD | MY_TXLD | MY_CRCEnable | MY_PADEnable; 1356 f->my_ctl |= total_len << MY_PKTShift; /* pkt size */ 1357 f->my_ctl |= total_len; /* buffer size */ 1358 /* 89/12/29 add, for mtd891 *//* [ 89? ] */ 1359 if (sc->my_info->my_did == MTD891ID) 1360 f->my_ctl |= MY_ETIControl | MY_RetryTxLC; 1361 c->my_mbuf = m_head; 1362 c->my_lastdesc = 0; 1363 MY_TXNEXT(c) = vtophys(&c->my_nextdesc->my_ptr->my_frag[0]); 1364 return (0); 1365 } 1366 1367 /* 1368 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1369 * to the mbuf data regions directly in the transmit lists. We also save a 1370 * copy of the pointers since the transmit list fragment pointers are 1371 * physical addresses. 1372 */ 1373 static void 1374 my_start(if_t ifp) 1375 { 1376 struct my_softc *sc; 1377 1378 sc = if_getsoftc(ifp); 1379 MY_LOCK(sc); 1380 my_start_locked(ifp); 1381 MY_UNLOCK(sc); 1382 } 1383 1384 static void 1385 my_start_locked(if_t ifp) 1386 { 1387 struct my_softc *sc; 1388 struct mbuf *m_head = NULL; 1389 struct my_chain *cur_tx = NULL, *start_tx; 1390 1391 sc = if_getsoftc(ifp); 1392 MY_LOCK_ASSERT(sc); 1393 if (sc->my_autoneg) { 1394 sc->my_tx_pend = 1; 1395 return; 1396 } 1397 /* 1398 * Check for an available queue slot. If there are none, punt. 1399 */ 1400 if (sc->my_cdata.my_tx_free->my_mbuf != NULL) { 1401 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); 1402 return; 1403 } 1404 start_tx = sc->my_cdata.my_tx_free; 1405 while (sc->my_cdata.my_tx_free->my_mbuf == NULL) { 1406 m_head = if_dequeue(ifp); 1407 if (m_head == NULL) 1408 break; 1409 1410 /* Pick a descriptor off the free list. */ 1411 cur_tx = sc->my_cdata.my_tx_free; 1412 sc->my_cdata.my_tx_free = cur_tx->my_nextdesc; 1413 1414 /* Pack the data into the descriptor. */ 1415 my_encap(sc, cur_tx, m_head); 1416 1417 if (cur_tx != start_tx) 1418 MY_TXOWN(cur_tx) = MY_OWNByNIC; 1419 #if NBPFILTER > 0 1420 /* 1421 * If there's a BPF listener, bounce a copy of this frame to 1422 * him. 1423 */ 1424 BPF_MTAP(ifp, cur_tx->my_mbuf); 1425 #endif 1426 } 1427 /* 1428 * If there are no packets queued, bail. 1429 */ 1430 if (cur_tx == NULL) { 1431 return; 1432 } 1433 /* 1434 * Place the request for the upload interrupt in the last descriptor 1435 * in the chain. This way, if we're chaining several packets at once, 1436 * we'll only get an interrupt once for the whole chain rather than 1437 * once for each packet. 1438 */ 1439 MY_TXCTL(cur_tx) |= MY_TXIC; 1440 cur_tx->my_ptr->my_frag[0].my_ctl |= MY_TXIC; 1441 sc->my_cdata.my_tx_tail = cur_tx; 1442 if (sc->my_cdata.my_tx_head == NULL) 1443 sc->my_cdata.my_tx_head = start_tx; 1444 MY_TXOWN(start_tx) = MY_OWNByNIC; 1445 CSR_WRITE_4(sc, MY_TXPDR, 0xFFFFFFFF); /* tx polling demand */ 1446 1447 /* 1448 * Set a timeout in case the chip goes out to lunch. 1449 */ 1450 sc->my_timer = 5; 1451 return; 1452 } 1453 1454 static void 1455 my_init(void *xsc) 1456 { 1457 struct my_softc *sc = xsc; 1458 1459 MY_LOCK(sc); 1460 my_init_locked(sc); 1461 MY_UNLOCK(sc); 1462 } 1463 1464 static void 1465 my_init_locked(struct my_softc *sc) 1466 { 1467 if_t ifp = sc->my_ifp; 1468 u_int16_t phy_bmcr = 0; 1469 1470 MY_LOCK_ASSERT(sc); 1471 if (sc->my_autoneg) { 1472 return; 1473 } 1474 if (sc->my_pinfo != NULL) 1475 phy_bmcr = my_phy_readreg(sc, PHY_BMCR); 1476 /* 1477 * Cancel pending I/O and free all RX/TX buffers. 1478 */ 1479 my_stop(sc); 1480 my_reset(sc); 1481 1482 /* 1483 * Set cache alignment and burst length. 1484 */ 1485 #if 0 /* 89/9/1 modify, */ 1486 CSR_WRITE_4(sc, MY_BCR, MY_RPBLE512); 1487 CSR_WRITE_4(sc, MY_TCRRCR, MY_TFTSF); 1488 #endif 1489 CSR_WRITE_4(sc, MY_BCR, MY_PBL8); 1490 CSR_WRITE_4(sc, MY_TCRRCR, MY_TFTSF | MY_RBLEN | MY_RPBLE512); 1491 /* 1492 * 89/12/29 add, for mtd891, 1493 */ 1494 if (sc->my_info->my_did == MTD891ID) { 1495 MY_SETBIT(sc, MY_BCR, MY_PROG); 1496 MY_SETBIT(sc, MY_TCRRCR, MY_Enhanced); 1497 } 1498 my_setcfg(sc, phy_bmcr); 1499 /* Init circular RX list. */ 1500 if (my_list_rx_init(sc) == ENOBUFS) { 1501 device_printf(sc->my_dev, "init failed: no memory for rx buffers\n"); 1502 my_stop(sc); 1503 return; 1504 } 1505 /* Init TX descriptors. */ 1506 my_list_tx_init(sc); 1507 1508 /* If we want promiscuous mode, set the allframes bit. */ 1509 if (if_getflags(ifp) & IFF_PROMISC) 1510 MY_SETBIT(sc, MY_TCRRCR, MY_PROM); 1511 else 1512 MY_CLRBIT(sc, MY_TCRRCR, MY_PROM); 1513 1514 /* 1515 * Set capture broadcast bit to capture broadcast frames. 1516 */ 1517 if (if_getflags(ifp) & IFF_BROADCAST) 1518 MY_SETBIT(sc, MY_TCRRCR, MY_AB); 1519 else 1520 MY_CLRBIT(sc, MY_TCRRCR, MY_AB); 1521 1522 /* 1523 * Program the multicast filter, if necessary. 1524 */ 1525 my_setmulti(sc); 1526 1527 /* 1528 * Load the address of the RX list. 1529 */ 1530 MY_CLRBIT(sc, MY_TCRRCR, MY_RE); 1531 CSR_WRITE_4(sc, MY_RXLBA, vtophys(&sc->my_ldata->my_rx_list[0])); 1532 1533 /* 1534 * Enable interrupts. 1535 */ 1536 CSR_WRITE_4(sc, MY_IMR, MY_INTRS); 1537 CSR_WRITE_4(sc, MY_ISR, 0xFFFFFFFF); 1538 1539 /* Enable receiver and transmitter. */ 1540 MY_SETBIT(sc, MY_TCRRCR, MY_RE); 1541 MY_CLRBIT(sc, MY_TCRRCR, MY_TE); 1542 CSR_WRITE_4(sc, MY_TXLBA, vtophys(&sc->my_ldata->my_tx_list[0])); 1543 MY_SETBIT(sc, MY_TCRRCR, MY_TE); 1544 1545 /* Restore state of BMCR */ 1546 if (sc->my_pinfo != NULL) 1547 my_phy_writereg(sc, PHY_BMCR, phy_bmcr); 1548 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0); 1549 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 1550 1551 callout_reset(&sc->my_watchdog, hz, my_watchdog, sc); 1552 return; 1553 } 1554 1555 /* 1556 * Set media options. 1557 */ 1558 1559 static int 1560 my_ifmedia_upd(if_t ifp) 1561 { 1562 struct my_softc *sc; 1563 struct ifmedia *ifm; 1564 1565 sc = if_getsoftc(ifp); 1566 MY_LOCK(sc); 1567 ifm = &sc->ifmedia; 1568 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) { 1569 MY_UNLOCK(sc); 1570 return (EINVAL); 1571 } 1572 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO) 1573 my_autoneg_mii(sc, MY_FLAG_SCHEDDELAY, 1); 1574 else 1575 my_setmode_mii(sc, ifm->ifm_media); 1576 MY_UNLOCK(sc); 1577 return (0); 1578 } 1579 1580 /* 1581 * Report current media status. 1582 */ 1583 1584 static void 1585 my_ifmedia_sts(if_t ifp, struct ifmediareq * ifmr) 1586 { 1587 struct my_softc *sc; 1588 u_int16_t advert = 0, ability = 0; 1589 1590 sc = if_getsoftc(ifp); 1591 MY_LOCK(sc); 1592 ifmr->ifm_active = IFM_ETHER; 1593 if (!(my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_AUTONEGENBL)) { 1594 #if 0 /* this version did not support 1000M, */ 1595 if (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_1000) 1596 ifmr->ifm_active = IFM_ETHER | IFM_1000TX; 1597 #endif 1598 if (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_SPEEDSEL) 1599 ifmr->ifm_active = IFM_ETHER | IFM_100_TX; 1600 else 1601 ifmr->ifm_active = IFM_ETHER | IFM_10_T; 1602 if (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_DUPLEX) 1603 ifmr->ifm_active |= IFM_FDX; 1604 else 1605 ifmr->ifm_active |= IFM_HDX; 1606 1607 MY_UNLOCK(sc); 1608 return; 1609 } 1610 ability = my_phy_readreg(sc, PHY_LPAR); 1611 advert = my_phy_readreg(sc, PHY_ANAR); 1612 1613 #if 0 /* this version did not support 1000M, */ 1614 if (sc->my_pinfo->my_vid = MarvellPHYID0) { 1615 ability2 = my_phy_readreg(sc, PHY_1000SR); 1616 if (ability2 & PHY_1000SR_1000BTXFULL) { 1617 advert = 0; 1618 ability = 0; 1619 ifmr->ifm_active = IFM_ETHER|IFM_1000_T|IFM_FDX; 1620 } else if (ability & PHY_1000SR_1000BTXHALF) { 1621 advert = 0; 1622 ability = 0; 1623 ifmr->ifm_active = IFM_ETHER|IFM_1000_T|IFM_HDX; 1624 } 1625 } 1626 #endif 1627 if (advert & PHY_ANAR_100BT4 && ability & PHY_ANAR_100BT4) 1628 ifmr->ifm_active = IFM_ETHER | IFM_100_T4; 1629 else if (advert & PHY_ANAR_100BTXFULL && ability & PHY_ANAR_100BTXFULL) 1630 ifmr->ifm_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 1631 else if (advert & PHY_ANAR_100BTXHALF && ability & PHY_ANAR_100BTXHALF) 1632 ifmr->ifm_active = IFM_ETHER | IFM_100_TX | IFM_HDX; 1633 else if (advert & PHY_ANAR_10BTFULL && ability & PHY_ANAR_10BTFULL) 1634 ifmr->ifm_active = IFM_ETHER | IFM_10_T | IFM_FDX; 1635 else if (advert & PHY_ANAR_10BTHALF && ability & PHY_ANAR_10BTHALF) 1636 ifmr->ifm_active = IFM_ETHER | IFM_10_T | IFM_HDX; 1637 MY_UNLOCK(sc); 1638 return; 1639 } 1640 1641 static int 1642 my_ioctl(if_t ifp, u_long command, caddr_t data) 1643 { 1644 struct my_softc *sc = if_getsoftc(ifp); 1645 struct ifreq *ifr = (struct ifreq *) data; 1646 int error; 1647 1648 switch (command) { 1649 case SIOCSIFFLAGS: 1650 MY_LOCK(sc); 1651 if (if_getflags(ifp) & IFF_UP) 1652 my_init_locked(sc); 1653 else if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) 1654 my_stop(sc); 1655 MY_UNLOCK(sc); 1656 error = 0; 1657 break; 1658 case SIOCADDMULTI: 1659 case SIOCDELMULTI: 1660 MY_LOCK(sc); 1661 my_setmulti(sc); 1662 MY_UNLOCK(sc); 1663 error = 0; 1664 break; 1665 case SIOCGIFMEDIA: 1666 case SIOCSIFMEDIA: 1667 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); 1668 break; 1669 default: 1670 error = ether_ioctl(ifp, command, data); 1671 break; 1672 } 1673 return (error); 1674 } 1675 1676 static void 1677 my_watchdog(void *arg) 1678 { 1679 struct my_softc *sc; 1680 if_t ifp; 1681 1682 sc = arg; 1683 MY_LOCK_ASSERT(sc); 1684 callout_reset(&sc->my_watchdog, hz, my_watchdog, sc); 1685 if (sc->my_timer == 0 || --sc->my_timer > 0) 1686 return; 1687 1688 ifp = sc->my_ifp; 1689 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 1690 if_printf(ifp, "watchdog timeout\n"); 1691 if (!(my_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT)) 1692 if_printf(ifp, "no carrier - transceiver cable problem?\n"); 1693 my_stop(sc); 1694 my_reset(sc); 1695 my_init_locked(sc); 1696 if (!if_sendq_empty(ifp)) 1697 my_start_locked(ifp); 1698 } 1699 1700 /* 1701 * Stop the adapter and free any mbufs allocated to the RX and TX lists. 1702 */ 1703 static void 1704 my_stop(struct my_softc * sc) 1705 { 1706 int i; 1707 if_t ifp; 1708 1709 MY_LOCK_ASSERT(sc); 1710 ifp = sc->my_ifp; 1711 1712 callout_stop(&sc->my_autoneg_timer); 1713 callout_stop(&sc->my_watchdog); 1714 1715 MY_CLRBIT(sc, MY_TCRRCR, (MY_RE | MY_TE)); 1716 CSR_WRITE_4(sc, MY_IMR, 0x00000000); 1717 CSR_WRITE_4(sc, MY_TXLBA, 0x00000000); 1718 CSR_WRITE_4(sc, MY_RXLBA, 0x00000000); 1719 1720 /* 1721 * Free data in the RX lists. 1722 */ 1723 for (i = 0; i < MY_RX_LIST_CNT; i++) { 1724 if (sc->my_cdata.my_rx_chain[i].my_mbuf != NULL) { 1725 m_freem(sc->my_cdata.my_rx_chain[i].my_mbuf); 1726 sc->my_cdata.my_rx_chain[i].my_mbuf = NULL; 1727 } 1728 } 1729 bzero((char *)&sc->my_ldata->my_rx_list, 1730 sizeof(sc->my_ldata->my_rx_list)); 1731 /* 1732 * Free the TX list buffers. 1733 */ 1734 for (i = 0; i < MY_TX_LIST_CNT; i++) { 1735 if (sc->my_cdata.my_tx_chain[i].my_mbuf != NULL) { 1736 m_freem(sc->my_cdata.my_tx_chain[i].my_mbuf); 1737 sc->my_cdata.my_tx_chain[i].my_mbuf = NULL; 1738 } 1739 } 1740 bzero((char *)&sc->my_ldata->my_tx_list, 1741 sizeof(sc->my_ldata->my_tx_list)); 1742 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)); 1743 return; 1744 } 1745 1746 /* 1747 * Stop all chip I/O so that the kernel's probe routines don't get confused 1748 * by errant DMAs when rebooting. 1749 */ 1750 static int 1751 my_shutdown(device_t dev) 1752 { 1753 struct my_softc *sc; 1754 1755 sc = device_get_softc(dev); 1756 MY_LOCK(sc); 1757 my_stop(sc); 1758 MY_UNLOCK(sc); 1759 return 0; 1760 } 1761