1 /******************************************************************************* 2 3 Copyright (c) 2006-2007, Myricom Inc. 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Neither the name of the Myricom Inc, nor the names of its 13 contributors may be used to endorse or promote products derived from 14 this software without specific prior written permission. 15 16 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 20 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 POSSIBILITY OF SUCH DAMAGE. 27 28 $FreeBSD$ 29 ***************************************************************************/ 30 31 #ifndef _myri10ge_mcp_h 32 #define _myri10ge_mcp_h 33 34 #define MXGEFW_VERSION_MAJOR 1 35 #define MXGEFW_VERSION_MINOR 4 36 37 #ifdef MXGEFW 38 typedef signed char int8_t; 39 typedef signed short int16_t; 40 typedef signed int int32_t; 41 typedef signed long long int64_t; 42 typedef unsigned char uint8_t; 43 typedef unsigned short uint16_t; 44 typedef unsigned int uint32_t; 45 typedef unsigned long long uint64_t; 46 #endif 47 48 /* 8 Bytes */ 49 struct mcp_dma_addr { 50 uint32_t high; 51 uint32_t low; 52 }; 53 typedef struct mcp_dma_addr mcp_dma_addr_t; 54 55 /* 4 Bytes. 8 Bytes for NDIS drivers. */ 56 struct mcp_slot { 57 #ifdef MXGEFW_NDIS 58 /* Place at the top so it gets written before length. 59 * The driver polls length. 60 */ 61 uint32_t hash; 62 #endif 63 uint16_t checksum; 64 uint16_t length; 65 }; 66 typedef struct mcp_slot mcp_slot_t; 67 68 #ifdef MXGEFW_NDIS 69 /* Two bits of length in mcp_slot are used to indicate hash type. */ 70 #define MXGEFW_RSS_HASH_NULL (0 << 14) /* bit 15:14 = 00 */ 71 #define MXGEFW_RSS_HASH_IPV4 (1 << 14) /* bit 15:14 = 01 */ 72 #define MXGEFW_RSS_HASH_TCP_IPV4 (2 << 14) /* bit 15:14 = 10 */ 73 #define MXGEFW_RSS_HASH_MASK (3 << 14) /* bit 15:14 = 11 */ 74 #endif 75 76 /* 64 Bytes */ 77 struct mcp_cmd { 78 uint32_t cmd; 79 uint32_t data0; /* will be low portion if data > 32 bits */ 80 /* 8 */ 81 uint32_t data1; /* will be high portion if data > 32 bits */ 82 uint32_t data2; /* currently unused.. */ 83 /* 16 */ 84 struct mcp_dma_addr response_addr; 85 /* 24 */ 86 uint8_t pad[40]; 87 }; 88 typedef struct mcp_cmd mcp_cmd_t; 89 90 /* 8 Bytes */ 91 struct mcp_cmd_response { 92 uint32_t data; 93 uint32_t result; 94 }; 95 typedef struct mcp_cmd_response mcp_cmd_response_t; 96 97 98 99 /* 100 flags used in mcp_kreq_ether_send_t: 101 102 The SMALL flag is only needed in the first segment. It is raised 103 for packets that are total less or equal 512 bytes. 104 105 The CKSUM flag must be set in all segments. 106 107 The PADDED flags is set if the packet needs to be padded, and it 108 must be set for all segments. 109 110 The MXGEFW_FLAGS_ALIGN_ODD must be set if the cumulative 111 length of all previous segments was odd. 112 */ 113 114 115 #define MXGEFW_FLAGS_SMALL 0x1 116 #define MXGEFW_FLAGS_TSO_HDR 0x1 117 #define MXGEFW_FLAGS_FIRST 0x2 118 #define MXGEFW_FLAGS_ALIGN_ODD 0x4 119 #define MXGEFW_FLAGS_CKSUM 0x8 120 #define MXGEFW_FLAGS_TSO_LAST 0x8 121 #define MXGEFW_FLAGS_NO_TSO 0x10 122 #define MXGEFW_FLAGS_TSO_CHOP 0x10 123 #define MXGEFW_FLAGS_TSO_PLD 0x20 124 125 #define MXGEFW_SEND_SMALL_SIZE 1520 126 #define MXGEFW_MAX_MTU 9400 127 128 union mcp_pso_or_cumlen { 129 uint16_t pseudo_hdr_offset; 130 uint16_t cum_len; 131 }; 132 typedef union mcp_pso_or_cumlen mcp_pso_or_cumlen_t; 133 134 #define MXGEFW_MAX_SEND_DESC 12 135 #define MXGEFW_PAD 2 136 137 /* 16 Bytes */ 138 struct mcp_kreq_ether_send { 139 uint32_t addr_high; 140 uint32_t addr_low; 141 uint16_t pseudo_hdr_offset; 142 uint16_t length; 143 uint8_t pad; 144 uint8_t rdma_count; 145 uint8_t cksum_offset; /* where to start computing cksum */ 146 uint8_t flags; /* as defined above */ 147 }; 148 typedef struct mcp_kreq_ether_send mcp_kreq_ether_send_t; 149 150 /* 8 Bytes */ 151 struct mcp_kreq_ether_recv { 152 uint32_t addr_high; 153 uint32_t addr_low; 154 }; 155 typedef struct mcp_kreq_ether_recv mcp_kreq_ether_recv_t; 156 157 158 /* Commands */ 159 160 #define MXGEFW_BOOT_HANDOFF 0xfc0000 161 #define MXGEFW_BOOT_DUMMY_RDMA 0xfc01c0 162 163 #define MXGEFW_ETH_CMD 0xf80000 164 #define MXGEFW_ETH_SEND_4 0x200000 165 #define MXGEFW_ETH_SEND_1 0x240000 166 #define MXGEFW_ETH_SEND_2 0x280000 167 #define MXGEFW_ETH_SEND_3 0x2c0000 168 #define MXGEFW_ETH_RECV_SMALL 0x300000 169 #define MXGEFW_ETH_RECV_BIG 0x340000 170 171 #define MXGEFW_ETH_SEND(n) (0x200000 + (((n) & 0x03) * 0x40000)) 172 #define MXGEFW_ETH_SEND_OFFSET(n) (MXGEFW_ETH_SEND(n) - MXGEFW_ETH_SEND_4) 173 174 enum myri10ge_mcp_cmd_type { 175 MXGEFW_CMD_NONE = 0, 176 /* Reset the mcp, it is left in a safe state, waiting 177 for the driver to set all its parameters */ 178 MXGEFW_CMD_RESET, 179 180 /* get the version number of the current firmware.. 181 (may be available in the eeprom strings..? */ 182 MXGEFW_GET_MCP_VERSION, 183 184 185 /* Parameters which must be set by the driver before it can 186 issue MXGEFW_CMD_ETHERNET_UP. They persist until the next 187 MXGEFW_CMD_RESET is issued */ 188 189 MXGEFW_CMD_SET_INTRQ_DMA, 190 MXGEFW_CMD_SET_BIG_BUFFER_SIZE, /* in bytes, power of 2 */ 191 MXGEFW_CMD_SET_SMALL_BUFFER_SIZE, /* in bytes */ 192 193 194 /* Parameters which refer to lanai SRAM addresses where the 195 driver must issue PIO writes for various things */ 196 197 MXGEFW_CMD_GET_SEND_OFFSET, 198 MXGEFW_CMD_GET_SMALL_RX_OFFSET, 199 MXGEFW_CMD_GET_BIG_RX_OFFSET, 200 MXGEFW_CMD_GET_IRQ_ACK_OFFSET, 201 MXGEFW_CMD_GET_IRQ_DEASSERT_OFFSET, 202 203 /* Parameters which refer to rings stored on the MCP, 204 and whose size is controlled by the mcp */ 205 206 MXGEFW_CMD_GET_SEND_RING_SIZE, /* in bytes */ 207 MXGEFW_CMD_GET_RX_RING_SIZE, /* in bytes */ 208 209 /* Parameters which refer to rings stored in the host, 210 and whose size is controlled by the host. Note that 211 all must be physically contiguous and must contain 212 a power of 2 number of entries. */ 213 214 MXGEFW_CMD_SET_INTRQ_SIZE, /* in bytes */ 215 216 /* command to bring ethernet interface up. Above parameters 217 (plus mtu & mac address) must have been exchanged prior 218 to issuing this command */ 219 MXGEFW_CMD_ETHERNET_UP, 220 221 /* command to bring ethernet interface down. No further sends 222 or receives may be processed until an MXGEFW_CMD_ETHERNET_UP 223 is issued, and all interrupt queues must be flushed prior 224 to ack'ing this command */ 225 226 MXGEFW_CMD_ETHERNET_DOWN, 227 228 /* commands the driver may issue live, without resetting 229 the nic. Note that increasing the mtu "live" should 230 only be done if the driver has already supplied buffers 231 sufficiently large to handle the new mtu. Decreasing 232 the mtu live is safe */ 233 234 MXGEFW_CMD_SET_MTU, 235 MXGEFW_CMD_GET_INTR_COAL_DELAY_OFFSET, /* in microseconds */ 236 MXGEFW_CMD_SET_STATS_INTERVAL, /* in microseconds */ 237 MXGEFW_CMD_SET_STATS_DMA_OBSOLETE, /* replaced by SET_STATS_DMA_V2 */ 238 239 MXGEFW_ENABLE_PROMISC, 240 MXGEFW_DISABLE_PROMISC, 241 MXGEFW_SET_MAC_ADDRESS, 242 243 MXGEFW_ENABLE_FLOW_CONTROL, 244 MXGEFW_DISABLE_FLOW_CONTROL, 245 246 /* do a DMA test 247 data0,data1 = DMA address 248 data2 = RDMA length (MSH), WDMA length (LSH) 249 command return data = repetitions (MSH), 0.5-ms ticks (LSH) 250 */ 251 MXGEFW_DMA_TEST, 252 253 MXGEFW_ENABLE_ALLMULTI, 254 MXGEFW_DISABLE_ALLMULTI, 255 256 /* returns MXGEFW_CMD_ERROR_MULTICAST 257 if there is no room in the cache 258 data0,MSH(data1) = multicast group address */ 259 MXGEFW_JOIN_MULTICAST_GROUP, 260 /* returns MXGEFW_CMD_ERROR_MULTICAST 261 if the address is not in the cache, 262 or is equal to FF-FF-FF-FF-FF-FF 263 data0,MSH(data1) = multicast group address */ 264 MXGEFW_LEAVE_MULTICAST_GROUP, 265 MXGEFW_LEAVE_ALL_MULTICAST_GROUPS, 266 267 MXGEFW_CMD_SET_STATS_DMA_V2, 268 /* data0, data1 = bus addr, 269 data2 = sizeof(struct mcp_irq_data) from driver point of view, allows 270 adding new stuff to mcp_irq_data without changing the ABI */ 271 272 MXGEFW_CMD_UNALIGNED_TEST, 273 /* same than DMA_TEST (same args) but abort with UNALIGNED on unaligned 274 chipset */ 275 276 MXGEFW_CMD_UNALIGNED_STATUS, 277 /* return data = boolean, true if the chipset is known to be unaligned */ 278 279 MXGEFW_CMD_ALWAYS_USE_N_BIG_BUFFERS, 280 /* data0 = number of big buffers to use. It must be 0 or a power of 2. 281 * 0 indicates that the NIC consumes as many buffers as they are required 282 * for packet. This is the default behavior. 283 * A power of 2 number indicates that the NIC always uses the specified 284 * number of buffers for each big receive packet. 285 * It is up to the driver to ensure that this value is big enough for 286 * the NIC to be able to receive maximum-sized packets. 287 */ 288 289 MXGEFW_CMD_GET_MAX_RSS_QUEUES, 290 MXGEFW_CMD_ENABLE_RSS_QUEUES, 291 /* data0 = number of slices n (0, 1, ..., n-1) to enable 292 * data1 = interrupt mode. 0=share one INTx/MSI, 1=use one MSI-X per queue. 293 * If all queues share one interrupt, the driver must have set 294 * RSS_SHARED_INTERRUPT_DMA before enabling queues. 295 */ 296 MXGEFW_CMD_GET_RSS_SHARED_INTERRUPT_MASK_OFFSET, 297 MXGEFW_CMD_SET_RSS_SHARED_INTERRUPT_DMA, 298 /* data0, data1 = bus address lsw, msw */ 299 MXGEFW_CMD_GET_RSS_TABLE_OFFSET, 300 /* get the offset of the indirection table */ 301 MXGEFW_CMD_SET_RSS_TABLE_SIZE, 302 /* set the size of the indirection table */ 303 MXGEFW_CMD_GET_RSS_KEY_OFFSET, 304 /* get the offset of the secret key */ 305 MXGEFW_CMD_RSS_KEY_UPDATED, 306 /* tell nic that the secret key's been updated */ 307 MXGEFW_CMD_SET_RSS_ENABLE, 308 /* data0 = enable/disable rss 309 * 0: disable rss. nic does not distribute receive packets. 310 * 1: enable rss. nic distributes receive packets among queues. 311 * data1 = hash type 312 * 1: IPV4 313 * 2: TCP_IPV4 314 * 3: IPV4 | TCP_IPV4 315 */ 316 317 MXGEFW_CMD_GET_MAX_TSO6_HDR_SIZE, 318 /* Return data = the max. size of the entire headers of a IPv6 TSO packet. 319 * If the header size of a IPv6 TSO packet is larger than the specified 320 * value, then the driver must not use TSO. 321 * This size restriction only applies to IPv6 TSO. 322 * For IPv4 TSO, the maximum size of the headers is fixed, and the NIC 323 * always has enough header buffer to store maximum-sized headers. 324 */ 325 326 MXGEFW_CMD_SET_TSO_MODE, 327 /* data0 = TSO mode. 328 * 0: Linux/FreeBSD style (NIC default) 329 * 1: NDIS/NetBSD style 330 */ 331 332 MXGEFW_CMD_MDIO_READ, 333 /* data0 = dev_addr (PMA/PMD or PCS ...), data1 = register/addr */ 334 MXGEFW_CMD_MDIO_WRITE, 335 /* data0 = dev_addr, data1 = register/addr, data2 = value */ 336 337 MXGEFW_CMD_XFP_I2C_READ, 338 /* Starts to get a fresh copy of one byte or of the whole xfp i2c table, the 339 * obtained data is cached inside the xaui-xfi chip : 340 * data0 : "all" flag : 0 => get one byte, 1=> get 256 bytes, 341 * data1 : if (data0 == 0): index of byte to refresh [ not used otherwise ] 342 * The operation might take ~1ms for a single byte or ~65ms when refreshing all 256 bytes 343 * During the i2c operation, MXGEFW_CMD_XFP_I2C_READ or MXGEFW_CMD_XFP_BYTE attempts 344 * will return MXGEFW_CMD_ERROR_BUSY 345 */ 346 MXGEFW_CMD_XFP_BYTE 347 /* Return the last obtained copy of a given byte in the xfp i2c table 348 * (copy cached during the last relevant MXGEFW_CMD_XFP_I2C_READ) 349 * data0 : index of the desired table entry 350 * Return data = the byte stored at the requested index in the table 351 */ 352 }; 353 typedef enum myri10ge_mcp_cmd_type myri10ge_mcp_cmd_type_t; 354 355 356 enum myri10ge_mcp_cmd_status { 357 MXGEFW_CMD_OK = 0, 358 MXGEFW_CMD_UNKNOWN, 359 MXGEFW_CMD_ERROR_RANGE, 360 MXGEFW_CMD_ERROR_BUSY, 361 MXGEFW_CMD_ERROR_EMPTY, 362 MXGEFW_CMD_ERROR_CLOSED, 363 MXGEFW_CMD_ERROR_HASH_ERROR, 364 MXGEFW_CMD_ERROR_BAD_PORT, 365 MXGEFW_CMD_ERROR_RESOURCES, 366 MXGEFW_CMD_ERROR_MULTICAST, 367 MXGEFW_CMD_ERROR_UNALIGNED, 368 MXGEFW_CMD_ERROR_NO_MDIO, 369 MXGEFW_CMD_ERROR_XFP_FAILURE, 370 MXGEFW_CMD_ERROR_XFP_ABSENT 371 }; 372 typedef enum myri10ge_mcp_cmd_status myri10ge_mcp_cmd_status_t; 373 374 375 #define MXGEFW_OLD_IRQ_DATA_LEN 40 376 377 struct mcp_irq_data { 378 /* add new counters at the beginning */ 379 uint32_t future_use[1]; 380 uint32_t dropped_pause; 381 uint32_t dropped_unicast_filtered; 382 uint32_t dropped_bad_crc32; 383 uint32_t dropped_bad_phy; 384 uint32_t dropped_multicast_filtered; 385 /* 40 Bytes */ 386 uint32_t send_done_count; 387 388 #define MXGEFW_LINK_DOWN 0 389 #define MXGEFW_LINK_UP 1 390 #define MXGEFW_LINK_MYRINET 2 391 #define MXGEFW_LINK_UNKNOWN 3 392 uint32_t link_up; 393 uint32_t dropped_link_overflow; 394 uint32_t dropped_link_error_or_filtered; 395 uint32_t dropped_runt; 396 uint32_t dropped_overrun; 397 uint32_t dropped_no_small_buffer; 398 uint32_t dropped_no_big_buffer; 399 uint32_t rdma_tags_available; 400 401 uint8_t tx_stopped; 402 uint8_t link_down; 403 uint8_t stats_updated; 404 uint8_t valid; 405 }; 406 typedef struct mcp_irq_data mcp_irq_data_t; 407 408 #ifdef MXGEFW_NDIS 409 struct mcp_rss_shared_interrupt { 410 uint8_t pad[2]; 411 uint8_t queue; 412 uint8_t valid; 413 }; 414 #endif 415 416 #endif /* _myri10ge_mcp_h */ 417