1 /******************************************************************************* 2 3 Copyright (c) 2006-2008, Myricom Inc. 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Neither the name of the Myricom Inc, nor the names of its 13 contributors may be used to endorse or promote products derived from 14 this software without specific prior written permission. 15 16 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 20 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 POSSIBILITY OF SUCH DAMAGE. 27 28 $FreeBSD$ 29 ***************************************************************************/ 30 31 #ifndef _myri10ge_mcp_h 32 #define _myri10ge_mcp_h 33 34 #define MXGEFW_VERSION_MAJOR 1 35 #define MXGEFW_VERSION_MINOR 4 36 37 #ifdef MXGEFW 38 typedef signed char int8_t; 39 typedef signed short int16_t; 40 typedef signed int int32_t; 41 typedef signed long long int64_t; 42 typedef unsigned char uint8_t; 43 typedef unsigned short uint16_t; 44 typedef unsigned int uint32_t; 45 typedef unsigned long long uint64_t; 46 #endif 47 48 /* 8 Bytes */ 49 struct mcp_dma_addr { 50 uint32_t high; 51 uint32_t low; 52 }; 53 typedef struct mcp_dma_addr mcp_dma_addr_t; 54 55 /* 4 Bytes */ 56 struct mcp_slot { 57 uint16_t checksum; 58 uint16_t length; 59 }; 60 typedef struct mcp_slot mcp_slot_t; 61 62 #ifdef MXGEFW_NDIS 63 /* 8-byte descriptor, exclusively used by NDIS drivers. */ 64 struct mcp_slot_8 { 65 /* Place hash value at the top so it gets written before length. 66 * The driver polls length. 67 */ 68 uint32_t hash; 69 uint16_t checksum; 70 uint16_t length; 71 }; 72 typedef struct mcp_slot_8 mcp_slot_8_t; 73 74 /* Two bits of length in mcp_slot are used to indicate hash type. */ 75 #define MXGEFW_RSS_HASH_NULL (0 << 14) /* bit 15:14 = 00 */ 76 #define MXGEFW_RSS_HASH_IPV4 (1 << 14) /* bit 15:14 = 01 */ 77 #define MXGEFW_RSS_HASH_TCP_IPV4 (2 << 14) /* bit 15:14 = 10 */ 78 #define MXGEFW_RSS_HASH_MASK (3 << 14) /* bit 15:14 = 11 */ 79 #endif 80 81 /* 64 Bytes */ 82 struct mcp_cmd { 83 uint32_t cmd; 84 uint32_t data0; /* will be low portion if data > 32 bits */ 85 /* 8 */ 86 uint32_t data1; /* will be high portion if data > 32 bits */ 87 uint32_t data2; /* currently unused.. */ 88 /* 16 */ 89 struct mcp_dma_addr response_addr; 90 /* 24 */ 91 uint8_t pad[40]; 92 }; 93 typedef struct mcp_cmd mcp_cmd_t; 94 95 /* 8 Bytes */ 96 struct mcp_cmd_response { 97 uint32_t data; 98 uint32_t result; 99 }; 100 typedef struct mcp_cmd_response mcp_cmd_response_t; 101 102 103 104 /* 105 flags used in mcp_kreq_ether_send_t: 106 107 The SMALL flag is only needed in the first segment. It is raised 108 for packets that are total less or equal 512 bytes. 109 110 The CKSUM flag must be set in all segments. 111 112 The PADDED flags is set if the packet needs to be padded, and it 113 must be set for all segments. 114 115 The MXGEFW_FLAGS_ALIGN_ODD must be set if the cumulative 116 length of all previous segments was odd. 117 */ 118 119 120 #define MXGEFW_FLAGS_SMALL 0x1 121 #define MXGEFW_FLAGS_TSO_HDR 0x1 122 #define MXGEFW_FLAGS_FIRST 0x2 123 #define MXGEFW_FLAGS_ALIGN_ODD 0x4 124 #define MXGEFW_FLAGS_CKSUM 0x8 125 #define MXGEFW_FLAGS_TSO_LAST 0x8 126 #define MXGEFW_FLAGS_NO_TSO 0x10 127 #define MXGEFW_FLAGS_TSO_CHOP 0x10 128 #define MXGEFW_FLAGS_TSO_PLD 0x20 129 130 #define MXGEFW_SEND_SMALL_SIZE 1520 131 #define MXGEFW_MAX_MTU 9400 132 133 union mcp_pso_or_cumlen { 134 uint16_t pseudo_hdr_offset; 135 uint16_t cum_len; 136 }; 137 typedef union mcp_pso_or_cumlen mcp_pso_or_cumlen_t; 138 139 #define MXGEFW_MAX_SEND_DESC 12 140 #define MXGEFW_PAD 2 141 142 /* 16 Bytes */ 143 struct mcp_kreq_ether_send { 144 uint32_t addr_high; 145 uint32_t addr_low; 146 uint16_t pseudo_hdr_offset; 147 uint16_t length; 148 uint8_t pad; 149 uint8_t rdma_count; 150 uint8_t cksum_offset; /* where to start computing cksum */ 151 uint8_t flags; /* as defined above */ 152 }; 153 typedef struct mcp_kreq_ether_send mcp_kreq_ether_send_t; 154 155 /* 8 Bytes */ 156 struct mcp_kreq_ether_recv { 157 uint32_t addr_high; 158 uint32_t addr_low; 159 }; 160 typedef struct mcp_kreq_ether_recv mcp_kreq_ether_recv_t; 161 162 163 /* Commands */ 164 165 #define MXGEFW_BOOT_HANDOFF 0xfc0000 166 #define MXGEFW_BOOT_DUMMY_RDMA 0xfc01c0 167 168 #define MXGEFW_ETH_CMD 0xf80000 169 #define MXGEFW_ETH_SEND_4 0x200000 170 #define MXGEFW_ETH_SEND_1 0x240000 171 #define MXGEFW_ETH_SEND_2 0x280000 172 #define MXGEFW_ETH_SEND_3 0x2c0000 173 #define MXGEFW_ETH_RECV_SMALL 0x300000 174 #define MXGEFW_ETH_RECV_BIG 0x340000 175 176 #define MXGEFW_ETH_SEND(n) (0x200000 + (((n) & 0x03) * 0x40000)) 177 #define MXGEFW_ETH_SEND_OFFSET(n) (MXGEFW_ETH_SEND(n) - MXGEFW_ETH_SEND_4) 178 179 enum myri10ge_mcp_cmd_type { 180 MXGEFW_CMD_NONE = 0, 181 /* Reset the mcp, it is left in a safe state, waiting 182 for the driver to set all its parameters */ 183 MXGEFW_CMD_RESET, 184 185 /* get the version number of the current firmware.. 186 (may be available in the eeprom strings..? */ 187 MXGEFW_GET_MCP_VERSION, 188 189 190 /* Parameters which must be set by the driver before it can 191 issue MXGEFW_CMD_ETHERNET_UP. They persist until the next 192 MXGEFW_CMD_RESET is issued */ 193 194 MXGEFW_CMD_SET_INTRQ_DMA, 195 MXGEFW_CMD_SET_BIG_BUFFER_SIZE, /* in bytes, power of 2 */ 196 MXGEFW_CMD_SET_SMALL_BUFFER_SIZE, /* in bytes */ 197 198 199 /* Parameters which refer to lanai SRAM addresses where the 200 driver must issue PIO writes for various things */ 201 202 MXGEFW_CMD_GET_SEND_OFFSET, 203 MXGEFW_CMD_GET_SMALL_RX_OFFSET, 204 MXGEFW_CMD_GET_BIG_RX_OFFSET, 205 MXGEFW_CMD_GET_IRQ_ACK_OFFSET, 206 MXGEFW_CMD_GET_IRQ_DEASSERT_OFFSET, 207 208 /* Parameters which refer to rings stored on the MCP, 209 and whose size is controlled by the mcp */ 210 211 MXGEFW_CMD_GET_SEND_RING_SIZE, /* in bytes */ 212 MXGEFW_CMD_GET_RX_RING_SIZE, /* in bytes */ 213 214 /* Parameters which refer to rings stored in the host, 215 and whose size is controlled by the host. Note that 216 all must be physically contiguous and must contain 217 a power of 2 number of entries. */ 218 219 MXGEFW_CMD_SET_INTRQ_SIZE, /* in bytes */ 220 221 /* command to bring ethernet interface up. Above parameters 222 (plus mtu & mac address) must have been exchanged prior 223 to issuing this command */ 224 MXGEFW_CMD_ETHERNET_UP, 225 226 /* command to bring ethernet interface down. No further sends 227 or receives may be processed until an MXGEFW_CMD_ETHERNET_UP 228 is issued, and all interrupt queues must be flushed prior 229 to ack'ing this command */ 230 231 MXGEFW_CMD_ETHERNET_DOWN, 232 233 /* commands the driver may issue live, without resetting 234 the nic. Note that increasing the mtu "live" should 235 only be done if the driver has already supplied buffers 236 sufficiently large to handle the new mtu. Decreasing 237 the mtu live is safe */ 238 239 MXGEFW_CMD_SET_MTU, 240 MXGEFW_CMD_GET_INTR_COAL_DELAY_OFFSET, /* in microseconds */ 241 MXGEFW_CMD_SET_STATS_INTERVAL, /* in microseconds */ 242 MXGEFW_CMD_SET_STATS_DMA_OBSOLETE, /* replaced by SET_STATS_DMA_V2 */ 243 244 MXGEFW_ENABLE_PROMISC, 245 MXGEFW_DISABLE_PROMISC, 246 MXGEFW_SET_MAC_ADDRESS, 247 248 MXGEFW_ENABLE_FLOW_CONTROL, 249 MXGEFW_DISABLE_FLOW_CONTROL, 250 251 /* do a DMA test 252 data0,data1 = DMA address 253 data2 = RDMA length (MSH), WDMA length (LSH) 254 command return data = repetitions (MSH), 0.5-ms ticks (LSH) 255 */ 256 MXGEFW_DMA_TEST, 257 258 MXGEFW_ENABLE_ALLMULTI, 259 MXGEFW_DISABLE_ALLMULTI, 260 261 /* returns MXGEFW_CMD_ERROR_MULTICAST 262 if there is no room in the cache 263 data0,MSH(data1) = multicast group address */ 264 MXGEFW_JOIN_MULTICAST_GROUP, 265 /* returns MXGEFW_CMD_ERROR_MULTICAST 266 if the address is not in the cache, 267 or is equal to FF-FF-FF-FF-FF-FF 268 data0,MSH(data1) = multicast group address */ 269 MXGEFW_LEAVE_MULTICAST_GROUP, 270 MXGEFW_LEAVE_ALL_MULTICAST_GROUPS, 271 272 MXGEFW_CMD_SET_STATS_DMA_V2, 273 /* data0, data1 = bus addr, 274 data2 = sizeof(struct mcp_irq_data) from driver point of view, allows 275 adding new stuff to mcp_irq_data without changing the ABI */ 276 277 MXGEFW_CMD_UNALIGNED_TEST, 278 /* same than DMA_TEST (same args) but abort with UNALIGNED on unaligned 279 chipset */ 280 281 MXGEFW_CMD_UNALIGNED_STATUS, 282 /* return data = boolean, true if the chipset is known to be unaligned */ 283 284 MXGEFW_CMD_ALWAYS_USE_N_BIG_BUFFERS, 285 /* data0 = number of big buffers to use. It must be 0 or a power of 2. 286 * 0 indicates that the NIC consumes as many buffers as they are required 287 * for packet. This is the default behavior. 288 * A power of 2 number indicates that the NIC always uses the specified 289 * number of buffers for each big receive packet. 290 * It is up to the driver to ensure that this value is big enough for 291 * the NIC to be able to receive maximum-sized packets. 292 */ 293 294 MXGEFW_CMD_GET_MAX_RSS_QUEUES, 295 MXGEFW_CMD_ENABLE_RSS_QUEUES, 296 /* data0 = number of slices n (0, 1, ..., n-1) to enable 297 * data1 = interrupt mode. 298 * 0=share one INTx/MSI, 1=use one MSI-X per queue. 299 * If all queues share one interrupt, the driver must have set 300 * RSS_SHARED_INTERRUPT_DMA before enabling queues. 301 */ 302 #define MXGEFW_SLICE_INTR_MODE_SHARED 0 303 #define MXGEFW_SLICE_INTR_MODE_ONE_PER_SLICE 1 304 305 MXGEFW_CMD_GET_RSS_SHARED_INTERRUPT_MASK_OFFSET, 306 MXGEFW_CMD_SET_RSS_SHARED_INTERRUPT_DMA, 307 /* data0, data1 = bus address lsw, msw */ 308 MXGEFW_CMD_GET_RSS_TABLE_OFFSET, 309 /* get the offset of the indirection table */ 310 MXGEFW_CMD_SET_RSS_TABLE_SIZE, 311 /* set the size of the indirection table */ 312 MXGEFW_CMD_GET_RSS_KEY_OFFSET, 313 /* get the offset of the secret key */ 314 MXGEFW_CMD_RSS_KEY_UPDATED, 315 /* tell nic that the secret key's been updated */ 316 MXGEFW_CMD_SET_RSS_ENABLE, 317 /* data0 = enable/disable rss 318 * 0: disable rss. nic does not distribute receive packets. 319 * 1: enable rss. nic distributes receive packets among queues. 320 * data1 = hash type 321 * 1: IPV4 (required by RSS) 322 * 2: TCP_IPV4 (required by RSS) 323 * 3: IPV4 | TCP_IPV4 (required by RSS) 324 * 4: source port 325 */ 326 #define MXGEFW_RSS_HASH_TYPE_IPV4 0x1 327 #define MXGEFW_RSS_HASH_TYPE_TCP_IPV4 0x2 328 #define MXGEFW_RSS_HASH_TYPE_SRC_PORT 0x4 329 330 MXGEFW_CMD_GET_MAX_TSO6_HDR_SIZE, 331 /* Return data = the max. size of the entire headers of a IPv6 TSO packet. 332 * If the header size of a IPv6 TSO packet is larger than the specified 333 * value, then the driver must not use TSO. 334 * This size restriction only applies to IPv6 TSO. 335 * For IPv4 TSO, the maximum size of the headers is fixed, and the NIC 336 * always has enough header buffer to store maximum-sized headers. 337 */ 338 339 MXGEFW_CMD_SET_TSO_MODE, 340 /* data0 = TSO mode. 341 * 0: Linux/FreeBSD style (NIC default) 342 * 1: NDIS/NetBSD style 343 */ 344 #define MXGEFW_TSO_MODE_LINUX 0 345 #define MXGEFW_TSO_MODE_NDIS 1 346 347 MXGEFW_CMD_MDIO_READ, 348 /* data0 = dev_addr (PMA/PMD or PCS ...), data1 = register/addr */ 349 MXGEFW_CMD_MDIO_WRITE, 350 /* data0 = dev_addr, data1 = register/addr, data2 = value */ 351 352 MXGEFW_CMD_XFP_I2C_READ, 353 /* Starts to get a fresh copy of one byte or of the whole xfp i2c table, the 354 * obtained data is cached inside the xaui-xfi chip : 355 * data0 : "all" flag : 0 => get one byte, 1=> get 256 bytes, 356 * data1 : if (data0 == 0): index of byte to refresh [ not used otherwise ] 357 * The operation might take ~1ms for a single byte or ~65ms when refreshing all 256 bytes 358 * During the i2c operation, MXGEFW_CMD_XFP_I2C_READ or MXGEFW_CMD_XFP_BYTE attempts 359 * will return MXGEFW_CMD_ERROR_BUSY 360 */ 361 MXGEFW_CMD_XFP_BYTE, 362 /* Return the last obtained copy of a given byte in the xfp i2c table 363 * (copy cached during the last relevant MXGEFW_CMD_XFP_I2C_READ) 364 * data0 : index of the desired table entry 365 * Return data = the byte stored at the requested index in the table 366 */ 367 368 MXGEFW_CMD_GET_VPUMP_OFFSET, 369 /* Return data = NIC memory offset of mcp_vpump_public_global */ 370 MXGEFW_CMD_RESET_VPUMP, 371 /* Resets the VPUMP state */ 372 373 MXGEFW_CMD_SET_RSS_MCP_SLOT_TYPE, 374 /* data0 = mcp_slot type to use. 375 * 0 = the default 4B mcp_slot 376 * 1 = 8B mcp_slot_8 377 */ 378 #define MXGEFW_RSS_MCP_SLOT_TYPE_MIN 0 379 #define MXGEFW_RSS_MCP_SLOT_TYPE_WITH_HASH 1 380 381 MXGEFW_CMD_SET_THROTTLE_FACTOR, 382 /* set the throttle factor for ethp_z8e 383 data0 = throttle_factor 384 throttle_factor = 256 * pcie-raw-speed / tx_speed 385 tx_speed = 256 * pcie-raw-speed / throttle_factor 386 387 For PCI-E x8: pcie-raw-speed == 16Gb/s 388 For PCI-E x4: pcie-raw-speed == 8Gb/s 389 390 ex1: throttle_factor == 0x1a0 (416), tx_speed == 1.23GB/s == 9.846 Gb/s 391 ex2: throttle_factor == 0x200 (512), tx_speed == 1.0GB/s == 8 Gb/s 392 393 with tx_boundary == 2048, max-throttle-factor == 8191 => min-speed == 500Mb/s 394 with tx_boundary == 4096, max-throttle-factor == 4095 => min-speed == 1Gb/s 395 */ 396 397 MXGEFW_CMD_VPUMP_UP 398 /* Allocates VPump Connection, Send Request and Zero copy buffer address tables */ 399 400 }; 401 typedef enum myri10ge_mcp_cmd_type myri10ge_mcp_cmd_type_t; 402 403 404 enum myri10ge_mcp_cmd_status { 405 MXGEFW_CMD_OK = 0, 406 MXGEFW_CMD_UNKNOWN, 407 MXGEFW_CMD_ERROR_RANGE, 408 MXGEFW_CMD_ERROR_BUSY, 409 MXGEFW_CMD_ERROR_EMPTY, 410 MXGEFW_CMD_ERROR_CLOSED, 411 MXGEFW_CMD_ERROR_HASH_ERROR, 412 MXGEFW_CMD_ERROR_BAD_PORT, 413 MXGEFW_CMD_ERROR_RESOURCES, 414 MXGEFW_CMD_ERROR_MULTICAST, 415 MXGEFW_CMD_ERROR_UNALIGNED, 416 MXGEFW_CMD_ERROR_NO_MDIO, 417 MXGEFW_CMD_ERROR_XFP_FAILURE, 418 MXGEFW_CMD_ERROR_XFP_ABSENT 419 }; 420 typedef enum myri10ge_mcp_cmd_status myri10ge_mcp_cmd_status_t; 421 422 423 #define MXGEFW_OLD_IRQ_DATA_LEN 40 424 425 struct mcp_irq_data { 426 /* add new counters at the beginning */ 427 uint32_t future_use[1]; 428 uint32_t dropped_pause; 429 uint32_t dropped_unicast_filtered; 430 uint32_t dropped_bad_crc32; 431 uint32_t dropped_bad_phy; 432 uint32_t dropped_multicast_filtered; 433 /* 40 Bytes */ 434 uint32_t send_done_count; 435 436 #define MXGEFW_LINK_DOWN 0 437 #define MXGEFW_LINK_UP 1 438 #define MXGEFW_LINK_MYRINET 2 439 #define MXGEFW_LINK_UNKNOWN 3 440 uint32_t link_up; 441 uint32_t dropped_link_overflow; 442 uint32_t dropped_link_error_or_filtered; 443 uint32_t dropped_runt; 444 uint32_t dropped_overrun; 445 uint32_t dropped_no_small_buffer; 446 uint32_t dropped_no_big_buffer; 447 uint32_t rdma_tags_available; 448 449 uint8_t tx_stopped; 450 uint8_t link_down; 451 uint8_t stats_updated; 452 uint8_t valid; 453 }; 454 typedef struct mcp_irq_data mcp_irq_data_t; 455 456 #ifdef MXGEFW_NDIS 457 /* Exclusively used by NDIS drivers */ 458 struct mcp_rss_shared_interrupt { 459 uint8_t pad[2]; 460 uint8_t queue; 461 uint8_t valid; 462 }; 463 #endif 464 465 #endif /* _myri10ge_mcp_h */ 466