1 /******************************************************************************* 2 3 Copyright (c) 2006-2007, Myricom Inc. 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Neither the name of the Myricom Inc, nor the names of its 13 contributors may be used to endorse or promote products derived from 14 this software without specific prior written permission. 15 16 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 20 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 POSSIBILITY OF SUCH DAMAGE. 27 28 $FreeBSD$ 29 ***************************************************************************/ 30 31 #ifndef _myri10ge_mcp_h 32 #define _myri10ge_mcp_h 33 34 #define MXGEFW_VERSION_MAJOR 1 35 #define MXGEFW_VERSION_MINOR 4 36 37 #ifdef MXGEFW 38 typedef signed char int8_t; 39 typedef signed short int16_t; 40 typedef signed int int32_t; 41 typedef signed long long int64_t; 42 typedef unsigned char uint8_t; 43 typedef unsigned short uint16_t; 44 typedef unsigned int uint32_t; 45 typedef unsigned long long uint64_t; 46 #endif 47 48 /* 8 Bytes */ 49 struct mcp_dma_addr { 50 uint32_t high; 51 uint32_t low; 52 }; 53 typedef struct mcp_dma_addr mcp_dma_addr_t; 54 55 /* 4 Bytes */ 56 struct mcp_slot { 57 uint16_t checksum; 58 uint16_t length; 59 }; 60 typedef struct mcp_slot mcp_slot_t; 61 62 /* 64 Bytes */ 63 struct mcp_cmd { 64 uint32_t cmd; 65 uint32_t data0; /* will be low portion if data > 32 bits */ 66 /* 8 */ 67 uint32_t data1; /* will be high portion if data > 32 bits */ 68 uint32_t data2; /* currently unused.. */ 69 /* 16 */ 70 struct mcp_dma_addr response_addr; 71 /* 24 */ 72 uint8_t pad[40]; 73 }; 74 typedef struct mcp_cmd mcp_cmd_t; 75 76 /* 8 Bytes */ 77 struct mcp_cmd_response { 78 uint32_t data; 79 uint32_t result; 80 }; 81 typedef struct mcp_cmd_response mcp_cmd_response_t; 82 83 84 85 /* 86 flags used in mcp_kreq_ether_send_t: 87 88 The SMALL flag is only needed in the first segment. It is raised 89 for packets that are total less or equal 512 bytes. 90 91 The CKSUM flag must be set in all segments. 92 93 The PADDED flags is set if the packet needs to be padded, and it 94 must be set for all segments. 95 96 The MXGEFW_FLAGS_ALIGN_ODD must be set if the cumulative 97 length of all previous segments was odd. 98 */ 99 100 101 #define MXGEFW_FLAGS_SMALL 0x1 102 #define MXGEFW_FLAGS_TSO_HDR 0x1 103 #define MXGEFW_FLAGS_FIRST 0x2 104 #define MXGEFW_FLAGS_ALIGN_ODD 0x4 105 #define MXGEFW_FLAGS_CKSUM 0x8 106 #define MXGEFW_FLAGS_TSO_LAST 0x8 107 #define MXGEFW_FLAGS_NO_TSO 0x10 108 #define MXGEFW_FLAGS_TSO_CHOP 0x10 109 #define MXGEFW_FLAGS_TSO_PLD 0x20 110 111 #define MXGEFW_SEND_SMALL_SIZE 1520 112 #define MXGEFW_MAX_MTU 9400 113 114 union mcp_pso_or_cumlen { 115 uint16_t pseudo_hdr_offset; 116 uint16_t cum_len; 117 }; 118 typedef union mcp_pso_or_cumlen mcp_pso_or_cumlen_t; 119 120 #define MXGEFW_MAX_SEND_DESC 12 121 #define MXGEFW_PAD 2 122 123 /* 16 Bytes */ 124 struct mcp_kreq_ether_send { 125 uint32_t addr_high; 126 uint32_t addr_low; 127 uint16_t pseudo_hdr_offset; 128 uint16_t length; 129 uint8_t pad; 130 uint8_t rdma_count; 131 uint8_t cksum_offset; /* where to start computing cksum */ 132 uint8_t flags; /* as defined above */ 133 }; 134 typedef struct mcp_kreq_ether_send mcp_kreq_ether_send_t; 135 136 /* 8 Bytes */ 137 struct mcp_kreq_ether_recv { 138 uint32_t addr_high; 139 uint32_t addr_low; 140 }; 141 typedef struct mcp_kreq_ether_recv mcp_kreq_ether_recv_t; 142 143 144 /* Commands */ 145 146 #define MXGEFW_BOOT_HANDOFF 0xfc0000 147 #define MXGEFW_BOOT_DUMMY_RDMA 0xfc01c0 148 149 #define MXGEFW_ETH_CMD 0xf80000 150 #define MXGEFW_ETH_SEND_4 0x200000 151 #define MXGEFW_ETH_SEND_1 0x240000 152 #define MXGEFW_ETH_SEND_2 0x280000 153 #define MXGEFW_ETH_SEND_3 0x2c0000 154 #define MXGEFW_ETH_RECV_SMALL 0x300000 155 #define MXGEFW_ETH_RECV_BIG 0x340000 156 157 #define MXGEFW_ETH_SEND(n) (0x200000 + (((n) & 0x03) * 0x40000)) 158 #define MXGEFW_ETH_SEND_OFFSET(n) (MXGEFW_ETH_SEND(n) - MXGEFW_ETH_SEND_4) 159 160 enum myri10ge_mcp_cmd_type { 161 MXGEFW_CMD_NONE = 0, 162 /* Reset the mcp, it is left in a safe state, waiting 163 for the driver to set all its parameters */ 164 MXGEFW_CMD_RESET, 165 166 /* get the version number of the current firmware.. 167 (may be available in the eeprom strings..? */ 168 MXGEFW_GET_MCP_VERSION, 169 170 171 /* Parameters which must be set by the driver before it can 172 issue MXGEFW_CMD_ETHERNET_UP. They persist until the next 173 MXGEFW_CMD_RESET is issued */ 174 175 MXGEFW_CMD_SET_INTRQ_DMA, 176 MXGEFW_CMD_SET_BIG_BUFFER_SIZE, /* in bytes, power of 2 */ 177 MXGEFW_CMD_SET_SMALL_BUFFER_SIZE, /* in bytes */ 178 179 180 /* Parameters which refer to lanai SRAM addresses where the 181 driver must issue PIO writes for various things */ 182 183 MXGEFW_CMD_GET_SEND_OFFSET, 184 MXGEFW_CMD_GET_SMALL_RX_OFFSET, 185 MXGEFW_CMD_GET_BIG_RX_OFFSET, 186 MXGEFW_CMD_GET_IRQ_ACK_OFFSET, 187 MXGEFW_CMD_GET_IRQ_DEASSERT_OFFSET, 188 189 /* Parameters which refer to rings stored on the MCP, 190 and whose size is controlled by the mcp */ 191 192 MXGEFW_CMD_GET_SEND_RING_SIZE, /* in bytes */ 193 MXGEFW_CMD_GET_RX_RING_SIZE, /* in bytes */ 194 195 /* Parameters which refer to rings stored in the host, 196 and whose size is controlled by the host. Note that 197 all must be physically contiguous and must contain 198 a power of 2 number of entries. */ 199 200 MXGEFW_CMD_SET_INTRQ_SIZE, /* in bytes */ 201 202 /* command to bring ethernet interface up. Above parameters 203 (plus mtu & mac address) must have been exchanged prior 204 to issuing this command */ 205 MXGEFW_CMD_ETHERNET_UP, 206 207 /* command to bring ethernet interface down. No further sends 208 or receives may be processed until an MXGEFW_CMD_ETHERNET_UP 209 is issued, and all interrupt queues must be flushed prior 210 to ack'ing this command */ 211 212 MXGEFW_CMD_ETHERNET_DOWN, 213 214 /* commands the driver may issue live, without resetting 215 the nic. Note that increasing the mtu "live" should 216 only be done if the driver has already supplied buffers 217 sufficiently large to handle the new mtu. Decreasing 218 the mtu live is safe */ 219 220 MXGEFW_CMD_SET_MTU, 221 MXGEFW_CMD_GET_INTR_COAL_DELAY_OFFSET, /* in microseconds */ 222 MXGEFW_CMD_SET_STATS_INTERVAL, /* in microseconds */ 223 MXGEFW_CMD_SET_STATS_DMA_OBSOLETE, /* replaced by SET_STATS_DMA_V2 */ 224 225 MXGEFW_ENABLE_PROMISC, 226 MXGEFW_DISABLE_PROMISC, 227 MXGEFW_SET_MAC_ADDRESS, 228 229 MXGEFW_ENABLE_FLOW_CONTROL, 230 MXGEFW_DISABLE_FLOW_CONTROL, 231 232 /* do a DMA test 233 data0,data1 = DMA address 234 data2 = RDMA length (MSH), WDMA length (LSH) 235 command return data = repetitions (MSH), 0.5-ms ticks (LSH) 236 */ 237 MXGEFW_DMA_TEST, 238 239 MXGEFW_ENABLE_ALLMULTI, 240 MXGEFW_DISABLE_ALLMULTI, 241 242 /* returns MXGEFW_CMD_ERROR_MULTICAST 243 if there is no room in the cache 244 data0,MSH(data1) = multicast group address */ 245 MXGEFW_JOIN_MULTICAST_GROUP, 246 /* returns MXGEFW_CMD_ERROR_MULTICAST 247 if the address is not in the cache, 248 or is equal to FF-FF-FF-FF-FF-FF 249 data0,MSH(data1) = multicast group address */ 250 MXGEFW_LEAVE_MULTICAST_GROUP, 251 MXGEFW_LEAVE_ALL_MULTICAST_GROUPS, 252 253 MXGEFW_CMD_SET_STATS_DMA_V2, 254 /* data0, data1 = bus addr, 255 data2 = sizeof(struct mcp_irq_data) from driver point of view, allows 256 adding new stuff to mcp_irq_data without changing the ABI */ 257 258 MXGEFW_CMD_UNALIGNED_TEST, 259 /* same than DMA_TEST (same args) but abort with UNALIGNED on unaligned 260 chipset */ 261 262 MXGEFW_CMD_UNALIGNED_STATUS, 263 /* return data = boolean, true if the chipset is known to be unaligned */ 264 265 MXGEFW_CMD_ALWAYS_USE_N_BIG_BUFFERS, 266 /* data0 = number of big buffers to use. It must be 0 or a power of 2. 267 * 0 indicates that the NIC consumes as many buffers as they are required 268 * for packet. This is the default behavior. 269 * A power of 2 number indicates that the NIC always uses the specified 270 * number of buffers for each big receive packet. 271 * It is up to the driver to ensure that this value is big enough for 272 * the NIC to be able to receive maximum-sized packets. 273 */ 274 }; 275 typedef enum myri10ge_mcp_cmd_type myri10ge_mcp_cmd_type_t; 276 277 278 enum myri10ge_mcp_cmd_status { 279 MXGEFW_CMD_OK = 0, 280 MXGEFW_CMD_UNKNOWN, 281 MXGEFW_CMD_ERROR_RANGE, 282 MXGEFW_CMD_ERROR_BUSY, 283 MXGEFW_CMD_ERROR_EMPTY, 284 MXGEFW_CMD_ERROR_CLOSED, 285 MXGEFW_CMD_ERROR_HASH_ERROR, 286 MXGEFW_CMD_ERROR_BAD_PORT, 287 MXGEFW_CMD_ERROR_RESOURCES, 288 MXGEFW_CMD_ERROR_MULTICAST, 289 MXGEFW_CMD_ERROR_UNALIGNED 290 }; 291 typedef enum myri10ge_mcp_cmd_status myri10ge_mcp_cmd_status_t; 292 293 294 #define MXGEFW_OLD_IRQ_DATA_LEN 40 295 296 struct mcp_irq_data { 297 /* add new counters at the beginning */ 298 uint32_t future_use[1]; 299 uint32_t dropped_pause; 300 uint32_t dropped_unicast_filtered; 301 uint32_t dropped_bad_crc32; 302 uint32_t dropped_bad_phy; 303 uint32_t dropped_multicast_filtered; 304 /* 40 Bytes */ 305 uint32_t send_done_count; 306 307 #define MXGEFW_LINK_DOWN 0 308 #define MXGEFW_LINK_UP 1 309 #define MXGEFW_LINK_MYRINET 2 310 #define MXGEFW_LINK_UNKNOWN 3 311 uint32_t link_up; 312 uint32_t dropped_link_overflow; 313 uint32_t dropped_link_error_or_filtered; 314 uint32_t dropped_runt; 315 uint32_t dropped_overrun; 316 uint32_t dropped_no_small_buffer; 317 uint32_t dropped_no_big_buffer; 318 uint32_t rdma_tags_available; 319 320 uint8_t tx_stopped; 321 uint8_t link_down; 322 uint8_t stats_updated; 323 uint8_t valid; 324 }; 325 typedef struct mcp_irq_data mcp_irq_data_t; 326 327 328 #endif /* _myri10ge_mcp_h */ 329