1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2007-2009 Sam Leffler, Errno Consulting 5 * Copyright (c) 2007-2009 Marvell Semiconductor, Inc. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer, 13 * without modification. 14 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 15 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 16 * redistribution must be conditioned upon including a substantially 17 * similar Disclaimer requirement for further binary redistribution. 18 * 19 * NO WARRANTY 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 22 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 23 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 24 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 25 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 28 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGES. 31 */ 32 33 /* 34 * Definitions for the Marvell Wireless LAN controller Hardware Access Layer. 35 */ 36 #ifndef _MWL_HALREG_H_ 37 #define _MWL_HALREG_H_ 38 39 #define MWL_ANT_INFO_SUPPORT /* per-antenna data in rx descriptor */ 40 41 #define MACREG_REG_TSF_LOW 0xa600 /* TSF lo */ 42 #define MACREG_REG_TSF_HIGH 0xa604 /* TSF hi */ 43 #define MACREG_REG_CHIP_REV 0xa814 /* chip rev */ 44 45 // Map to 0x80000000 (Bus control) on BAR0 46 #define MACREG_REG_H2A_INTERRUPT_EVENTS 0x00000C18 // (From host to ARM) 47 #define MACREG_REG_H2A_INTERRUPT_CAUSE 0x00000C1C // (From host to ARM) 48 #define MACREG_REG_H2A_INTERRUPT_MASK 0x00000C20 // (From host to ARM) 49 #define MACREG_REG_H2A_INTERRUPT_CLEAR_SEL 0x00000C24 // (From host to ARM) 50 #define MACREG_REG_H2A_INTERRUPT_STATUS_MASK 0x00000C28 // (From host to ARM) 51 52 #define MACREG_REG_A2H_INTERRUPT_EVENTS 0x00000C2C // (From ARM to host) 53 #define MACREG_REG_A2H_INTERRUPT_CAUSE 0x00000C30 // (From ARM to host) 54 #define MACREG_REG_A2H_INTERRUPT_MASK 0x00000C34 // (From ARM to host) 55 #define MACREG_REG_A2H_INTERRUPT_CLEAR_SEL 0x00000C38 // (From ARM to host) 56 #define MACREG_REG_A2H_INTERRUPT_STATUS_MASK 0x00000C3C // (From ARM to host) 57 58 // Map to 0x80000000 on BAR1 59 #define MACREG_REG_GEN_PTR 0x00000C10 60 #define MACREG_REG_INT_CODE 0x00000C14 61 #define MACREG_REG_SCRATCH 0x00000C40 62 #define MACREG_REG_FW_PRESENT 0x0000BFFC 63 64 #define MACREG_REG_PROMISCUOUS 0xA300 65 66 // Bit definitio for MACREG_REG_A2H_INTERRUPT_CAUSE (A2HRIC) 67 #define MACREG_A2HRIC_BIT_TX_DONE 0x00000001 // bit 0 68 #define MACREG_A2HRIC_BIT_RX_RDY 0x00000002 // bit 1 69 #define MACREG_A2HRIC_BIT_OPC_DONE 0x00000004 // bit 2 70 #define MACREG_A2HRIC_BIT_MAC_EVENT 0x00000008 // bit 3 71 #define MACREG_A2HRIC_BIT_RX_PROBLEM 0x00000010 // bit 4 72 73 #define MACREG_A2HRIC_BIT_RADIO_OFF 0x00000020 // bit 5 74 #define MACREG_A2HRIC_BIT_RADIO_ON 0x00000040 // bit 6 75 76 #define MACREG_A2HRIC_BIT_RADAR_DETECT 0x00000080 // bit 7 77 78 #define MACREG_A2HRIC_BIT_ICV_ERROR 0x00000100 // bit 8 79 #define MACREG_A2HRIC_BIT_MIC_ERROR 0x00000200 // bit 9 80 #define MACREG_A2HRIC_BIT_QUEUE_EMPTY 0x00004000 81 #define MACREG_A2HRIC_BIT_QUEUE_FULL 0x00000800 82 #define MACREG_A2HRIC_BIT_CHAN_SWITCH 0x00001000 83 #define MACREG_A2HRIC_BIT_TX_WATCHDOG 0x00002000 84 #define MACREG_A2HRIC_BIT_BA_WATCHDOG 0x00000400 85 #define MACREQ_A2HRIC_BIT_TX_ACK 0x00008000 86 #define ISR_SRC_BITS ((MACREG_A2HRIC_BIT_RX_RDY) | \ 87 (MACREG_A2HRIC_BIT_TX_DONE) | \ 88 (MACREG_A2HRIC_BIT_OPC_DONE) | \ 89 (MACREG_A2HRIC_BIT_MAC_EVENT)| \ 90 (MACREG_A2HRIC_BIT_MIC_ERROR)| \ 91 (MACREG_A2HRIC_BIT_ICV_ERROR)| \ 92 (MACREG_A2HRIC_BIT_RADAR_DETECT)| \ 93 (MACREG_A2HRIC_BIT_CHAN_SWITCH)| \ 94 (MACREG_A2HRIC_BIT_TX_WATCHDOG)| \ 95 (MACREG_A2HRIC_BIT_QUEUE_EMPTY)| \ 96 (MACREG_A2HRIC_BIT_BA_WATCHDOG)| \ 97 (MACREQ_A2HRIC_BIT_TX_ACK)) 98 99 #define MACREG_A2HRIC_BIT_MASK ISR_SRC_BITS 100 101 // Bit definitio for MACREG_REG_H2A_INTERRUPT_CAUSE (H2ARIC) 102 #define MACREG_H2ARIC_BIT_PPA_READY 0x00000001 // bit 0 103 #define MACREG_H2ARIC_BIT_DOOR_BELL 0x00000002 // bit 1 104 #define ISR_RESET (1<<15) 105 106 // INT code register event definition 107 #define MACREG_INT_CODE_CMD_FINISHED 0x00000005 108 109 /* 110 * Host/Firmware Interface definitions. 111 */ 112 113 /** 114 * Define total number of TX queues in the shared memory. 115 * This count includes the EDCA queues, Block Ack queues, and HCCA queues 116 * In addition to this, there could be a management packet queue some 117 * time in the future 118 */ 119 #define NUM_EDCA_QUEUES 4 120 #define NUM_HCCA_QUEUES 0 121 #define NUM_BA_QUEUES 0 122 #define NUM_MGMT_QUEUES 0 123 #define NUM_ACK_EVENT_QUEUE 1 124 #define TOTAL_TX_QUEUES \ 125 (NUM_EDCA_QUEUES + NUM_HCCA_QUEUES + NUM_BA_QUEUES + NUM_MGMT_QUEUES + NUM_ACK_EVENT_QUEUE) 126 #define MAX_TXWCB_QUEUES TOTAL_TX_QUEUES - NUM_ACK_EVENT_QUEUE 127 #define MAX_RXWCB_QUEUES 1 128 129 //============================================================================= 130 // PUBLIC DEFINITIONS 131 //============================================================================= 132 133 #define RATE_INDEX_MAX_ARRAY 14 134 #define WOW_MAX_STATION 32 135 136 /* 137 * Hardware tx/rx descriptors. 138 * 139 * NB: tx descriptor size must match f/w expected size 140 * because f/w prefetch's the next descriptor linearly 141 * and doesn't chase the next pointer. 142 */ 143 struct mwl_txdesc { 144 uint32_t Status; 145 #define EAGLE_TXD_STATUS_IDLE 0x00000000 146 #define EAGLE_TXD_STATUS_USED 0x00000001 147 #define EAGLE_TXD_STATUS_OK 0x00000001 148 #define EAGLE_TXD_STATUS_OK_RETRY 0x00000002 149 #define EAGLE_TXD_STATUS_OK_MORE_RETRY 0x00000004 150 #define EAGLE_TXD_STATUS_MULTICAST_TX 0x00000008 151 #define EAGLE_TXD_STATUS_BROADCAST_TX 0x00000010 152 #define EAGLE_TXD_STATUS_FAILED_LINK_ERROR 0x00000020 153 #define EAGLE_TXD_STATUS_FAILED_EXCEED_LIMIT 0x00000040 154 #define EAGLE_TXD_STATUS_FAILED_XRETRY EAGLE_TXD_STATUS_FAILED_EXCEED_LIMIT 155 #define EAGLE_TXD_STATUS_FAILED_AGING 0x00000080 156 #define EAGLE_TXD_STATUS_FW_OWNED 0x80000000 157 uint8_t DataRate; 158 uint8_t TxPriority; 159 uint16_t QosCtrl; 160 uint32_t PktPtr; 161 uint16_t PktLen; 162 uint8_t DestAddr[6]; 163 uint32_t pPhysNext; 164 uint32_t SapPktInfo; 165 #define EAGLE_TXD_MODE_BONLY 1 166 #define EAGLE_TXD_MODE_GONLY 2 167 #define EAGLE_TXD_MODE_BG 3 168 #define EAGLE_TXD_MODE_NONLY 4 169 #define EAGLE_TXD_MODE_BN 5 170 #define EAGLE_TXD_MODE_GN 6 171 #define EAGLE_TXD_MODE_BGN 7 172 #define EAGLE_TXD_MODE_AONLY 8 173 #define EAGLE_TXD_MODE_AG 10 174 #define EAGLE_TXD_MODE_AN 12 175 uint16_t Format; 176 #define EAGLE_TXD_FORMAT 0x0001 /* frame format/rate */ 177 #define EAGLE_TXD_FORMAT_LEGACY 0x0000 /* legacy rate frame */ 178 #define EAGLE_TXD_FORMAT_HT 0x0001 /* HT rate frame */ 179 #define EAGLE_TXD_GI 0x0002 /* guard interval */ 180 #define EAGLE_TXD_GI_SHORT 0x0002 /* short guard interval */ 181 #define EAGLE_TXD_GI_LONG 0x0000 /* long guard interval */ 182 #define EAGLE_TXD_CHW 0x0004 /* channel width */ 183 #define EAGLE_TXD_CHW_20 0x0000 /* 20MHz channel width */ 184 #define EAGLE_TXD_CHW_40 0x0004 /* 40MHz channel width */ 185 #define EAGLE_TXD_RATE 0x01f8 /* tx rate (legacy)/ MCS */ 186 #define EAGLE_TXD_RATE_S 3 187 #define EAGLE_TXD_ADV 0x0600 /* advanced coding */ 188 #define EAGLE_TXD_ADV_S 9 189 #define EAGLE_TXD_ADV_NONE 0x0000 190 #define EAGLE_TXD_ADV_LDPC 0x0200 191 #define EAGLE_TXD_ADV_RS 0x0400 192 /* NB: 3 is reserved */ 193 #define EAGLE_TXD_ANTENNA 0x1800 /* antenna select */ 194 #define EAGLE_TXD_ANTENNA_S 11 195 #define EAGLE_TXD_EXTCHAN 0x6000 /* extension channel */ 196 #define EAGLE_TXD_EXTCHAN_S 13 197 #define EAGLE_TXD_EXTCHAN_HI 0x0000 /* above */ 198 #define EAGLE_TXD_EXTCHAN_LO 0x2000 /* below */ 199 #define EAGLE_TXD_PREAMBLE 0x8000 200 #define EAGLE_TXD_PREAMBLE_SHORT 0x8000 /* short preamble */ 201 #define EAGLE_TXD_PREAMBLE_LONG 0x0000 /* long preamble */ 202 uint16_t pad; /* align to 4-byte boundary */ 203 #define EAGLE_TXD_FIXED_RATE 0x0100 /* get tx rate from Format */ 204 #define EAGLE_TXD_DONT_AGGR 0x0200 /* don't aggregate frame */ 205 uint32_t ack_wcb_addr; 206 } __packed; 207 208 struct mwl_ant_info { 209 uint8_t rssi_a; /* RSSI for antenna A */ 210 uint8_t rssi_b; /* RSSI for antenna B */ 211 uint8_t rssi_c; /* RSSI for antenna C */ 212 uint8_t rsvd1; /* Reserved */ 213 uint8_t nf_a; /* Noise floor for antenna A */ 214 uint8_t nf_b; /* Noise floor for antenna B */ 215 uint8_t nf_c; /* Noise floor for antenna C */ 216 uint8_t rsvd2; /* Reserved */ 217 uint8_t nf; /* Noise floor */ 218 uint8_t rsvd3[3]; /* Reserved - To make word aligned */ 219 } __packed; 220 221 struct mwl_rxdesc { 222 uint8_t RxControl; /* control element */ 223 #define EAGLE_RXD_CTRL_DRIVER_OWN 0x00 224 #define EAGLE_RXD_CTRL_OS_OWN 0x04 225 #define EAGLE_RXD_CTRL_DMA_OWN 0x80 226 uint8_t RSSI; /* received signal strengt indication */ 227 uint8_t Status; /* status field w/ USED bit */ 228 #define EAGLE_RXD_STATUS_IDLE 0x00 229 #define EAGLE_RXD_STATUS_OK 0x01 230 #define EAGLE_RXD_STATUS_MULTICAST_RX 0x02 231 #define EAGLE_RXD_STATUS_BROADCAST_RX 0x04 232 #define EAGLE_RXD_STATUS_FRAGMENT_RX 0x08 233 #define EAGLE_RXD_STATUS_GENERAL_DECRYPT_ERR 0xff 234 #define EAGLE_RXD_STATUS_DECRYPT_ERR_MASK 0x80 235 #define EAGLE_RXD_STATUS_TKIP_MIC_DECRYPT_ERR 0x02 236 #define EAGLE_RXD_STATUS_WEP_ICV_DECRYPT_ERR 0x04 237 #define EAGLE_RXD_STATUS_TKIP_ICV_DECRYPT_ERR 0x08 238 uint8_t Channel; /* channel # pkt received on */ 239 uint16_t PktLen; /* total length of received data */ 240 uint8_t SQ2; /* not used */ 241 uint8_t Rate; /* received data rate */ 242 uint32_t pPhysBuffData; /* physical address of payload data */ 243 uint32_t pPhysNext; /* physical address of next RX desc */ 244 uint16_t QosCtrl; /* received QosCtrl field variable */ 245 uint16_t HtSig2; /* like name states */ 246 #ifdef MWL_ANT_INFO_SUPPORT 247 struct mwl_ant_info ai; /* antenna info */ 248 #endif 249 } __packed; 250 251 /* 252 // Define OpMode for SoftAP/Station mode 253 // 254 // The following mode signature has to be written to PCI scratch register#0 255 // right after successfully downloading the last block of firmware and 256 // before waiting for firmware ready signature 257 */ 258 #define HostCmd_STA_MODE 0x5A 259 #define HostCmd_SOFTAP_MODE 0xA5 260 261 #define HostCmd_STA_FWRDY_SIGNATURE 0xF0F1F2F4 262 #define HostCmd_SOFTAP_FWRDY_SIGNATURE 0xF1F2F4A5 263 264 //*************************************************************************** 265 //*************************************************************************** 266 267 //*************************************************************************** 268 269 #define HostCmd_CMD_CODE_DNLD 0x0001 270 #define HostCmd_CMD_GET_HW_SPEC 0x0003 271 #define HostCmd_CMD_SET_HW_SPEC 0x0004 272 #define HostCmd_CMD_MAC_MULTICAST_ADR 0x0010 273 #define HostCmd_CMD_802_11_GET_STAT 0x0014 274 #define HostCmd_CMD_MAC_REG_ACCESS 0x0019 275 #define HostCmd_CMD_BBP_REG_ACCESS 0x001a 276 #define HostCmd_CMD_RF_REG_ACCESS 0x001b 277 #define HostCmd_CMD_802_11_RADIO_CONTROL 0x001c 278 #define HostCmd_CMD_802_11_RF_TX_POWER 0x001e 279 #define HostCmd_CMD_802_11_RF_ANTENNA 0x0020 280 #define HostCmd_CMD_SET_BEACON 0x0100 281 #define HostCmd_CMD_SET_AID 0x010d 282 #define HostCmd_CMD_SET_RF_CHANNEL 0x010a 283 #define HostCmd_CMD_SET_INFRA_MODE 0x010e 284 #define HostCmd_CMD_SET_G_PROTECT_FLAG 0x010f 285 #define HostCmd_CMD_802_11_RTS_THSD 0x0113 286 #define HostCmd_CMD_802_11_SET_SLOT 0x0114 287 288 #define HostCmd_CMD_802_11H_DETECT_RADAR 0x0120 289 #define HostCmd_CMD_SET_WMM_MODE 0x0123 290 #define HostCmd_CMD_HT_GUARD_INTERVAL 0x0124 291 #define HostCmd_CMD_SET_FIXED_RATE 0x0126 292 #define HostCmd_CMD_SET_LINKADAPT_CS_MODE 0x0129 293 #define HostCmd_CMD_SET_MAC_ADDR 0x0202 294 #define HostCmd_CMD_SET_RATE_ADAPT_MODE 0x0203 295 #define HostCmd_CMD_GET_WATCHDOG_BITMAP 0x0205 296 297 //SoftAP command code 298 #define HostCmd_CMD_BSS_START 0x1100 299 #define HostCmd_CMD_SET_NEW_STN 0x1111 300 #define HostCmd_CMD_SET_KEEP_ALIVE 0x1112 301 #define HostCmd_CMD_SET_APMODE 0x1114 302 #define HostCmd_CMD_SET_SWITCH_CHANNEL 0x1121 303 304 /* 305 @HWENCR@ 306 Command to update firmware encryption keys. 307 */ 308 #define HostCmd_CMD_UPDATE_ENCRYPTION 0x1122 309 /* 310 @11E-BA@ 311 Command to create/destroy block ACK 312 */ 313 #define HostCmd_CMD_BASTREAM 0x1125 314 #define HostCmd_CMD_SET_RIFS 0x1126 315 #define HostCmd_CMD_SET_N_PROTECT_FLAG 0x1131 316 #define HostCmd_CMD_SET_N_PROTECT_OPMODE 0x1132 317 #define HostCmd_CMD_SET_OPTIMIZATION_LEVEL 0x1133 318 #define HostCmd_CMD_GET_CALTABLE 0x1134 319 #define HostCmd_CMD_SET_MIMOPSHT 0x1135 320 #define HostCmd_CMD_GET_BEACON 0x1138 321 #define HostCmd_CMD_SET_REGION_CODE 0x1139 322 #define HostCmd_CMD_SET_POWERSAVESTATION 0x1140 323 #define HostCmd_CMD_SET_TIM 0x1141 324 #define HostCmd_CMD_GET_TIM 0x1142 325 #define HostCmd_CMD_GET_SEQNO 0x1143 326 #define HostCmd_CMD_DWDS_ENABLE 0x1144 327 #define HostCmd_CMD_AMPDU_RETRY_RATEDROP_MODE 0x1145 328 #define HostCmd_CMD_CFEND_ENABLE 0x1146 329 330 /* 331 // Define general result code for each command 332 */ 333 #define HostCmd_RESULT_OK 0x0000 // OK 334 #define HostCmd_RESULT_ERROR 0x0001 // Genenral error 335 #define HostCmd_RESULT_NOT_SUPPORT 0x0002 // Command is not valid 336 #define HostCmd_RESULT_PENDING 0x0003 // Command is pending (will be processed) 337 #define HostCmd_RESULT_BUSY 0x0004 // System is busy (command ignored) 338 #define HostCmd_RESULT_PARTIAL_DATA 0x0005 // Data buffer is not big enough 339 340 /* 341 // Definition of action or option for each command 342 // 343 // Define general purpose action 344 */ 345 #define HostCmd_ACT_GEN_READ 0x0000 346 #define HostCmd_ACT_GEN_WRITE 0x0001 347 #define HostCmd_ACT_GEN_GET 0x0000 348 #define HostCmd_ACT_GEN_SET 0x0001 349 #define HostCmd_ACT_GEN_OFF 0x0000 350 #define HostCmd_ACT_GEN_ON 0x0001 351 352 #define HostCmd_ACT_DIFF_CHANNEL 0x0002 353 #define HostCmd_ACT_GEN_SET_LIST 0x0002 354 355 // Define action or option for HostCmd_FW_USE_FIXED_RATE 356 #define HostCmd_ACT_USE_FIXED_RATE 0x0001 357 #define HostCmd_ACT_NOT_USE_FIXED_RATE 0x0002 358 359 // Define action or option for HostCmd_CMD_802_11_SET_WEP 360 //#define HostCmd_ACT_ENABLE 0x0001 // Use MAC control for WEP on/off 361 //#define HostCmd_ACT_DISABLE 0x0000 362 #define HostCmd_ACT_ADD 0x0002 363 #define HostCmd_ACT_REMOVE 0x0004 364 #define HostCmd_ACT_USE_DEFAULT 0x0008 365 366 #define HostCmd_TYPE_WEP_40_BIT 0x0001 // 40 bit 367 #define HostCmd_TYPE_WEP_104_BIT 0x0002 // 104 bit 368 #define HostCmd_TYPE_WEP_128_BIT 0x0003 // 128 bit 369 #define HostCmd_TYPE_WEP_TX_KEY 0x0004 // TX WEP 370 371 #define HostCmd_NUM_OF_WEP_KEYS 4 372 373 #define HostCmd_WEP_KEY_INDEX_MASK 0x3fffffff 374 375 // Define action or option for HostCmd_CMD_802_11_RESET 376 #define HostCmd_ACT_HALT 0x0001 377 #define HostCmd_ACT_RESTART 0x0002 378 379 // Define action or option for HostCmd_CMD_802_11_RADIO_CONTROL 380 #define HostCmd_TYPE_AUTO_PREAMBLE 0x0001 381 #define HostCmd_TYPE_SHORT_PREAMBLE 0x0002 382 #define HostCmd_TYPE_LONG_PREAMBLE 0x0003 383 384 // Define action or option for CMD_802_11_RF_CHANNEL 385 #define HostCmd_TYPE_802_11A 0x0001 386 #define HostCmd_TYPE_802_11B 0x0002 387 388 // Define action or option for HostCmd_CMD_802_11_RF_TX_POWER 389 #define HostCmd_ACT_TX_POWER_OPT_SET_HIGH 0x0003 390 #define HostCmd_ACT_TX_POWER_OPT_SET_MID 0x0002 391 #define HostCmd_ACT_TX_POWER_OPT_SET_LOW 0x0001 392 #define HostCmd_ACT_TX_POWER_OPT_SET_AUTO 0x0000 393 394 #define HostCmd_ACT_TX_POWER_LEVEL_MIN 0x000e // in dbm 395 #define HostCmd_ACT_TX_POWER_LEVEL_GAP 0x0001 // in dbm 396 // Define action or option for HostCmd_CMD_802_11_DATA_RATE 397 #define HostCmd_ACT_SET_TX_AUTO 0x0000 398 #define HostCmd_ACT_SET_TX_FIX_RATE 0x0001 399 #define HostCmd_ACT_GET_TX_RATE 0x0002 400 401 #define HostCmd_ACT_SET_RX 0x0001 402 #define HostCmd_ACT_SET_TX 0x0002 403 #define HostCmd_ACT_SET_BOTH 0x0003 404 #define HostCmd_ACT_GET_RX 0x0004 405 #define HostCmd_ACT_GET_TX 0x0008 406 #define HostCmd_ACT_GET_BOTH 0x000c 407 408 #define TYPE_ANTENNA_DIVERSITY 0xffff 409 410 // Define action or option for HostCmd_CMD_802_11_PS_MODE 411 #define HostCmd_TYPE_CAM 0x0000 412 #define HostCmd_TYPE_MAX_PSP 0x0001 413 #define HostCmd_TYPE_FAST_PSP 0x0002 414 415 #define HostCmd_CMD_SET_EDCA_PARAMS 0x0115 416 417 //============================================================================= 418 // HOST COMMAND DEFINITIONS 419 //============================================================================= 420 421 // 422 // Definition of data structure for each command 423 // 424 // Define general data structure 425 typedef struct { 426 uint16_t Cmd; 427 uint16_t Length; 428 #ifdef MWL_MBSS_SUPPORT 429 uint8_t SeqNum; 430 uint8_t MacId; 431 #else 432 uint16_t SeqNum; 433 #endif 434 uint16_t Result; 435 } __packed FWCmdHdr; 436 437 typedef struct { 438 FWCmdHdr CmdHdr; 439 uint8_t Version; // HW revision 440 uint8_t HostIf; // Host interface 441 uint16_t NumOfMCastAdr; // Max. number of Multicast address FW can handle 442 uint8_t PermanentAddr[6]; // MAC address 443 uint16_t RegionCode; // Region Code 444 uint32_t FWReleaseNumber; // 4 byte of FW release number 445 uint32_t ulFwAwakeCookie; // Firmware awake cookie 446 uint32_t DeviceCaps; // Device capabilities (see above) 447 uint32_t RxPdWrPtr; // Rx shared memory queue 448 uint32_t NumTxQueues; // # TX queues in WcbBase array 449 uint32_t WcbBase[MAX_TXWCB_QUEUES]; // TX WCB Rings 450 uint32_t Flags; 451 #define SET_HW_SPEC_DISABLEMBSS 0x08 452 #define SET_HW_SPEC_HOSTFORM_BEACON 0x10 453 #define SET_HW_SPEC_HOSTFORM_PROBERESP 0x20 454 #define SET_HW_SPEC_HOST_POWERSAVE 0x40 455 #define SET_HW_SPEC_HOSTENCRDECR_MGMT 0x80 456 uint32_t TxWcbNumPerQueue; 457 uint32_t TotalRxWcb; 458 } __packed HostCmd_DS_SET_HW_SPEC; 459 460 typedef struct { 461 FWCmdHdr CmdHdr; 462 u_int8_t Version; /* version of the HW */ 463 u_int8_t HostIf; /* host interface */ 464 u_int16_t NumOfWCB; /* Max. number of WCB FW can handle */ 465 u_int16_t NumOfMCastAddr; /* MaxNbr of MC addresses FW can handle */ 466 u_int8_t PermanentAddr[6]; /* MAC address programmed in HW */ 467 u_int16_t RegionCode; 468 u_int16_t NumberOfAntenna; /* Number of antenna used */ 469 u_int32_t FWReleaseNumber; /* 4 byte of FW release number */ 470 u_int32_t WcbBase0; 471 u_int32_t RxPdWrPtr; 472 u_int32_t RxPdRdPtr; 473 u_int32_t ulFwAwakeCookie; 474 u_int32_t WcbBase1[TOTAL_TX_QUEUES-1]; 475 } __packed HostCmd_DS_GET_HW_SPEC; 476 477 typedef struct { 478 FWCmdHdr CmdHdr; 479 u_int32_t Enable; /* FALSE: Disable or TRUE: Enable */ 480 } __packed HostCmd_DS_BSS_START; 481 482 typedef struct { 483 u_int8_t ElemId; 484 u_int8_t Len; 485 u_int8_t OuiType[4]; /* 00:50:f2:01 */ 486 u_int8_t Ver[2]; 487 u_int8_t GrpKeyCipher[4]; 488 u_int8_t PwsKeyCnt[2]; 489 u_int8_t PwsKeyCipherList[4]; 490 u_int8_t AuthKeyCnt[2]; 491 u_int8_t AuthKeyList[4]; 492 } __packed RsnIE_t; 493 494 typedef struct { 495 u_int8_t ElemId; 496 u_int8_t Len; 497 u_int8_t Ver[2]; 498 u_int8_t GrpKeyCipher[4]; 499 u_int8_t PwsKeyCnt[2]; 500 u_int8_t PwsKeyCipherList[4]; 501 u_int8_t AuthKeyCnt[2]; 502 u_int8_t AuthKeyList[4]; 503 u_int8_t RsnCap[2]; 504 } __packed Rsn48IE_t; 505 506 typedef struct { 507 u_int8_t ElementId; 508 u_int8_t Len; 509 u_int8_t CfpCnt; 510 u_int8_t CfpPeriod; 511 u_int16_t CfpMaxDuration; 512 u_int16_t CfpDurationRemaining; 513 } __packed CfParams_t; 514 515 typedef struct { 516 u_int8_t ElementId; 517 u_int8_t Len; 518 u_int16_t AtimWindow; 519 } __packed IbssParams_t; 520 521 typedef union { 522 CfParams_t CfParamSet; 523 IbssParams_t IbssParamSet; 524 } __packed SsParams_t; 525 526 typedef struct { 527 u_int8_t ElementId; 528 u_int8_t Len; 529 u_int16_t DwellTime; 530 u_int8_t HopSet; 531 u_int8_t HopPattern; 532 u_int8_t HopIndex; 533 } __packed FhParams_t; 534 535 typedef struct { 536 u_int8_t ElementId; 537 u_int8_t Len; 538 u_int8_t CurrentChan; 539 } __packed DsParams_t; 540 541 typedef union { 542 FhParams_t FhParamSet; 543 DsParams_t DsParamSet; 544 } __packed PhyParams_t; 545 546 typedef struct { 547 u_int8_t FirstChannelNum; 548 u_int8_t NumOfChannels; 549 u_int8_t MaxTxPwrLevel; 550 } __packed ChannelInfo_t; 551 552 typedef struct { 553 u_int8_t ElementId; 554 u_int8_t Len; 555 u_int8_t CountryStr[3]; 556 ChannelInfo_t ChannelInfo[40]; 557 } __packed Country_t; 558 559 typedef struct { 560 u_int8_t AIFSN : 4; 561 u_int8_t ACM : 1; 562 u_int8_t ACI : 2; 563 u_int8_t rsvd : 1; 564 565 }__packed ACIAIFSN_field_t; 566 567 typedef struct { 568 u_int8_t ECW_min : 4; 569 u_int8_t ECW_max : 4; 570 }__packed ECWmin_max_field_t; 571 572 typedef struct { 573 ACIAIFSN_field_t ACI_AIFSN; 574 ECWmin_max_field_t ECW_min_max; 575 u_int16_t TXOP_lim; 576 }__packed ACparam_rcd_t; 577 578 typedef struct { 579 u_int8_t ElementId; 580 u_int8_t Len; 581 u_int8_t OUI[3]; 582 u_int8_t Type; 583 u_int8_t Subtype; 584 u_int8_t version; 585 u_int8_t rsvd; 586 ACparam_rcd_t AC_BE; 587 ACparam_rcd_t AC_BK; 588 ACparam_rcd_t AC_VI; 589 ACparam_rcd_t AC_VO; 590 } __packed WMM_param_elem_t ; 591 592 typedef struct { 593 #ifdef MWL_MBSS_SUPPORT 594 u_int8_t StaMacAddr[6]; 595 #endif 596 u_int8_t SsId[32]; 597 u_int8_t BssType; 598 u_int16_t BcnPeriod; 599 u_int8_t DtimPeriod; 600 SsParams_t SsParamSet; 601 PhyParams_t PhyParamSet; 602 u_int16_t ProbeDelay; 603 u_int16_t CapInfo; /* see below */ 604 u_int8_t BssBasicRateSet[14]; 605 u_int8_t OpRateSet[14]; 606 RsnIE_t RsnIE; 607 Rsn48IE_t Rsn48IE; 608 WMM_param_elem_t WMMParam; 609 Country_t Country; 610 u_int32_t ApRFType; /* 0->B, 1->G, 2->Mixed, 3->A, 4->11J */ 611 } __packed StartCmd_t; 612 613 #define HostCmd_CAPINFO_DEFAULT 0x0000 614 #define HostCmd_CAPINFO_ESS 0x0001 615 #define HostCmd_CAPINFO_IBSS 0x0002 616 #define HostCmd_CAPINFO_CF_POLLABLE 0x0004 617 #define HostCmd_CAPINFO_CF_REQUEST 0x0008 618 #define HostCmd_CAPINFO_PRIVACY 0x0010 619 #define HostCmd_CAPINFO_SHORT_PREAMBLE 0x0020 620 #define HostCmd_CAPINFO_PBCC 0x0040 621 #define HostCmd_CAPINFO_CHANNEL_AGILITY 0x0080 622 #define HostCmd_CAPINFO_SHORT_SLOT 0x0400 623 #define HostCmd_CAPINFO_DSSS_OFDM 0x2000 624 625 typedef struct { 626 FWCmdHdr CmdHdr; 627 StartCmd_t StartCmd; 628 } __packed HostCmd_DS_AP_BEACON; 629 630 typedef struct { 631 FWCmdHdr CmdHdr; 632 uint16_t FrmBodyLen; 633 uint8_t FrmBody[1]; /* NB: variable length */ 634 } __packed HostCmd_DS_SET_BEACON; 635 636 // Define data structure for HostCmd_CMD_MAC_MULTICAST_ADR 637 typedef struct { 638 FWCmdHdr CmdHdr; 639 uint16_t Action; 640 uint16_t NumOfAdrs; 641 #define MWL_HAL_MCAST_MAX 32 642 uint8_t MACList[6*32]; 643 } __packed HostCmd_DS_MAC_MULTICAST_ADR; 644 645 // Indicate to FW the current state of AP ERP info 646 typedef struct { 647 FWCmdHdr CmdHdr; 648 uint32_t GProtectFlag; 649 } __packed HostCmd_FW_SET_G_PROTECT_FLAG; 650 651 typedef struct { 652 FWCmdHdr CmdHdr; 653 } __packed HostCmd_FW_SET_INFRA_MODE; 654 655 // Define data structure for HostCmd_CMD_802_11_RF_CHANNEL 656 typedef struct { 657 FWCmdHdr CmdHdr; 658 uint16_t Action; 659 uint8_t CurrentChannel; /* channel # */ 660 uint32_t ChannelFlags; /* see below */ 661 } __packed HostCmd_FW_SET_RF_CHANNEL; 662 663 /* bits 0-5 specify frequency band */ 664 #define FREQ_BAND_2DOT4GHZ 0x0001 665 #define FREQ_BAND_4DOT9GHZ 0x0002 /* XXX not implemented */ 666 #define FREQ_BAND_5GHZ 0x0004 667 #define FREQ_BAND_5DOT2GHZ 0x0008 /* XXX not implemented */ 668 /* bits 6-10 specify channel width */ 669 #define CH_AUTO_WIDTH 0x0000 /* XXX not used? */ 670 #define CH_10_MHz_WIDTH 0x0040 671 #define CH_20_MHz_WIDTH 0x0080 672 #define CH_40_MHz_WIDTH 0x0100 673 /* bits 11-12 specify extension channel */ 674 #define EXT_CH_NONE 0x0000 /* no extension channel */ 675 #define EXT_CH_ABOVE_CTRL_CH 0x0800 /* extension channel above */ 676 #define EXT_CH_AUTO 0x1000 /* XXX not used? */ 677 #define EXT_CH_BELOW_CTRL_CH 0x1800 /* extension channel below */ 678 /* bits 13-31 are reserved */ 679 680 #define FIXED_RATE_WITH_AUTO_RATE_DROP 0 681 #define FIXED_RATE_WITHOUT_AUTORATE_DROP 1 682 683 #define LEGACY_RATE_TYPE 0 684 #define HT_RATE_TYPE 1 685 686 #define RETRY_COUNT_VALID 0 687 #define RETRY_COUNT_INVALID 1 688 689 typedef struct { 690 // lower rate after the retry count 691 uint32_t FixRateType; //0: legacy, 1: HT 692 uint32_t RetryCountValid; //0: retry count is not valid, 1: use retry count specified 693 } __packed FIX_RATE_FLAG; 694 695 typedef struct { 696 FIX_RATE_FLAG FixRateTypeFlags; 697 uint32_t FixedRate; // legacy rate(not index) or an MCS code. 698 uint32_t RetryCount; 699 } __packed FIXED_RATE_ENTRY; 700 701 typedef struct { 702 FWCmdHdr CmdHdr; 703 uint32_t Action; //HostCmd_ACT_GEN_GET 0x0000 704 //HostCmd_ACT_GEN_SET 0x0001 705 //HostCmd_ACT_NOT_USE_FIXED_RATE 0x0002 706 uint32_t AllowRateDrop; // use fixed rate specified but firmware can drop to 707 uint32_t EntryCount; 708 FIXED_RATE_ENTRY FixedRateTable[4]; 709 uint8_t MulticastRate; 710 uint8_t MultiRateTxType; 711 uint8_t ManagementRate; 712 } __packed HostCmd_FW_USE_FIXED_RATE; 713 714 typedef struct { 715 uint32_t AllowRateDrop; 716 uint32_t EntryCount; 717 FIXED_RATE_ENTRY FixedRateTable[4]; 718 } __packed USE_FIXED_RATE_INFO; 719 720 typedef struct { 721 FWCmdHdr CmdHdr; 722 uint32_t Action; 723 uint32_t GIType; 724 #define GI_TYPE_LONG 0x0001 725 #define GI_TYPE_SHORT 0x0002 726 } __packed HostCmd_FW_HT_GUARD_INTERVAL; 727 728 typedef struct { 729 FWCmdHdr CmdHdr; 730 uint32_t Action; 731 uint8_t RxAntennaMap; 732 uint8_t TxAntennaMap; 733 } __packed HostCmd_FW_HT_MIMO_CONFIG; 734 735 typedef struct { 736 FWCmdHdr CmdHdr; 737 uint16_t Action; 738 uint8_t Slot; // Slot=0 if regular, Slot=1 if short. 739 } __packed HostCmd_FW_SET_SLOT; 740 741 // Define data structure for HostCmd_CMD_802_11_GET_STAT 742 typedef struct { 743 FWCmdHdr CmdHdr; 744 uint32_t TxRetrySuccesses; 745 uint32_t TxMultipleRetrySuccesses; 746 uint32_t TxFailures; 747 uint32_t RTSSuccesses; 748 uint32_t RTSFailures; 749 uint32_t AckFailures; 750 uint32_t RxDuplicateFrames; 751 uint32_t FCSErrorCount; 752 uint32_t TxWatchDogTimeouts; 753 uint32_t RxOverflows; //used 754 uint32_t RxFragErrors; //used 755 uint32_t RxMemErrors; //used 756 uint32_t PointerErrors; //used 757 uint32_t TxUnderflows; //used 758 uint32_t TxDone; 759 uint32_t TxDoneBufTryPut; 760 uint32_t TxDoneBufPut; 761 uint32_t Wait4TxBuf; // Put size of requested buffer in here 762 uint32_t TxAttempts; 763 uint32_t TxSuccesses; 764 uint32_t TxFragments; 765 uint32_t TxMulticasts; 766 uint32_t RxNonCtlPkts; 767 uint32_t RxMulticasts; 768 uint32_t RxUndecryptableFrames; 769 uint32_t RxICVErrors; 770 uint32_t RxExcludedFrames; 771 } __packed HostCmd_DS_802_11_GET_STAT; 772 773 // Define data structure for HostCmd_CMD_MAC_REG_ACCESS 774 typedef struct { 775 FWCmdHdr CmdHdr; 776 uint16_t Action; 777 uint16_t Offset; 778 uint32_t Value; 779 uint16_t Reserved; 780 } __packed HostCmd_DS_MAC_REG_ACCESS; 781 782 // Define data structure for HostCmd_CMD_BBP_REG_ACCESS 783 typedef struct { 784 FWCmdHdr CmdHdr; 785 uint16_t Action; 786 uint16_t Offset; 787 uint8_t Value; 788 uint8_t Reserverd[3]; 789 } __packed HostCmd_DS_BBP_REG_ACCESS; 790 791 // Define data structure for HostCmd_CMD_RF_REG_ACCESS 792 typedef struct { 793 FWCmdHdr CmdHdr; 794 uint16_t Action; 795 uint16_t Offset; 796 uint8_t Value; 797 uint8_t Reserverd[3]; 798 } __packed HostCmd_DS_RF_REG_ACCESS; 799 800 // Define data structure for HostCmd_CMD_802_11_RADIO_CONTROL 801 typedef struct { 802 FWCmdHdr CmdHdr; 803 uint16_t Action; 804 uint16_t Control; // @bit0: 1/0,on/off, @bit1: 1/0, long/short @bit2: 1/0,auto/fix 805 uint16_t RadioOn; 806 } __packed HostCmd_DS_802_11_RADIO_CONTROL; 807 808 #define TX_POWER_LEVEL_TOTAL 8 809 // Define data structure for HostCmd_CMD_802_11_RF_TX_POWER 810 typedef struct { 811 FWCmdHdr CmdHdr; 812 uint16_t Action; 813 uint16_t SupportTxPowerLevel; 814 uint16_t CurrentTxPowerLevel; 815 uint16_t Reserved; 816 uint16_t PowerLevelList[TX_POWER_LEVEL_TOTAL]; 817 } __packed HostCmd_DS_802_11_RF_TX_POWER; 818 819 // Define data structure for HostCmd_CMD_802_11_RF_ANTENNA 820 typedef struct _HostCmd_DS_802_11_RF_ANTENNA { 821 FWCmdHdr CmdHdr; 822 uint16_t Action; 823 uint16_t AntennaMode; // Number of antennas or 0xffff(diversity) 824 } __packed HostCmd_DS_802_11_RF_ANTENNA; 825 826 // Define data structure for HostCmd_CMD_802_11_PS_MODE 827 typedef struct { 828 FWCmdHdr CmdHdr; 829 uint16_t Action; 830 uint16_t PowerMode; // CAM, Max.PSP or Fast PSP 831 } __packed HostCmd_DS_802_11_PS_MODE; 832 833 typedef struct { 834 FWCmdHdr CmdHdr; 835 uint16_t Action; 836 uint16_t Threshold; 837 } __packed HostCmd_DS_802_11_RTS_THSD; 838 839 // used for stand alone bssid sets/clears 840 typedef struct { 841 FWCmdHdr CmdHdr; 842 #ifdef MWL_MBSS_SUPPORT 843 uint16_t MacType; 844 #define WL_MAC_TYPE_PRIMARY_CLIENT 0 845 #define WL_MAC_TYPE_SECONDARY_CLIENT 1 846 #define WL_MAC_TYPE_PRIMARY_AP 2 847 #define WL_MAC_TYPE_SECONDARY_AP 3 848 #endif 849 uint8_t MacAddr[6]; 850 } __packed HostCmd_DS_SET_MAC, 851 HostCmd_FW_SET_BSSID, 852 HostCmd_FW_SET_MAC; 853 854 // Indicate to FW to send out PS Poll 855 typedef struct { 856 FWCmdHdr CmdHdr; 857 uint32_t PSPoll; 858 } __packed HostCmd_FW_TX_POLL; 859 860 // used for AID sets/clears 861 typedef struct { 862 FWCmdHdr CmdHdr; 863 uint16_t AssocID; 864 uint8_t MacAddr[6]; //AP's Mac Address(BSSID) 865 uint32_t GProtection; 866 uint8_t ApRates[ RATE_INDEX_MAX_ARRAY]; 867 } __packed HostCmd_FW_SET_AID; 868 869 typedef struct { 870 uint32_t LegacyRateBitMap; 871 uint32_t HTRateBitMap; 872 uint16_t CapInfo; 873 uint16_t HTCapabilitiesInfo; 874 uint8_t MacHTParamInfo; 875 uint8_t Rev; 876 struct { 877 uint8_t ControlChan; 878 uint8_t AddChan; 879 uint16_t OpMode; 880 uint16_t stbc; 881 } __packed AddHtInfo; 882 } __packed PeerInfo_t; 883 884 typedef struct { 885 FWCmdHdr CmdHdr; 886 uint16_t AID; 887 uint8_t MacAddr[6]; 888 uint16_t StnId; 889 uint16_t Action; 890 uint16_t Reserved; 891 PeerInfo_t PeerInfo; 892 uint8_t Qosinfo; 893 uint8_t isQosSta; 894 uint32_t FwStaPtr; 895 } __packed HostCmd_FW_SET_NEW_STN; 896 897 typedef struct { 898 FWCmdHdr CmdHdr; 899 uint8_t tick; 900 } __packed HostCmd_FW_SET_KEEP_ALIVE_TICK; 901 902 typedef struct { 903 FWCmdHdr CmdHdr; 904 uint8_t QNum; 905 } __packed HostCmd_FW_SET_RIFS; 906 907 typedef struct { 908 FWCmdHdr CmdHdr; 909 uint8_t ApMode; 910 } __packed HostCmd_FW_SET_APMODE; 911 912 typedef struct { 913 FWCmdHdr CmdHdr; 914 uint16_t Action; // see following 915 uint16_t RadarTypeCode; 916 } __packed HostCmd_802_11h_Detect_Radar; 917 918 #define DR_DFS_DISABLE 0 919 #define DR_CHK_CHANNEL_AVAILABLE_START 1 920 #define DR_CHK_CHANNEL_AVAILABLE_STOP 2 921 #define DR_IN_SERVICE_MONITOR_START 3 922 923 //New Structure for Update Tim 30/9/2003 924 typedef struct { 925 FWCmdHdr CmdHdr; 926 uint16_t Aid; 927 uint32_t Set; 928 } __packed HostCmd_UpdateTIM; 929 930 typedef struct { 931 FWCmdHdr CmdHdr; 932 uint32_t SsidBroadcastEnable; 933 } __packed HostCmd_SSID_BROADCAST; 934 935 typedef struct { 936 FWCmdHdr CmdHdr; 937 uint32_t WdsEnable; 938 } __packed HostCmd_WDS; 939 940 typedef struct { 941 FWCmdHdr CmdHdr; 942 uint32_t Next11hChannel; 943 uint32_t Mode; 944 uint32_t InitialCount; 945 uint32_t ChannelFlags ; 946 } __packed HostCmd_SET_SWITCH_CHANNEL; 947 948 typedef struct { 949 FWCmdHdr CmdHdr; 950 uint32_t SpectrumMgmt; 951 } __packed HostCmd_SET_SPECTRUM_MGMT; 952 953 typedef struct { 954 FWCmdHdr CmdHdr; 955 int32_t PowerConstraint; 956 } __packed HostCmd_SET_POWER_CONSTRAINT; 957 958 typedef struct { 959 uint8_t FirstChannelNo; 960 uint8_t NoofChannel; 961 uint8_t MaxTransmitPw; 962 } __packed DomainChannelEntry; 963 964 typedef struct { 965 uint8_t CountryString[3]; 966 uint8_t GChannelLen; 967 DomainChannelEntry DomainEntryG[1]; /** Assume only 1 G zone **/ 968 uint8_t AChannelLen; 969 DomainChannelEntry DomainEntryA[20]; /** Assume max of 5 A zone **/ 970 } __packed DomainCountryInfo; 971 972 typedef struct { 973 FWCmdHdr CmdHdr; 974 uint32_t Action ; // 0 -> unset, 1 ->set 975 DomainCountryInfo DomainInfo ; 976 } __packed HostCmd_SET_COUNTRY_INFO; 977 978 typedef struct { 979 FWCmdHdr CmdHdr; 980 uint16_t regionCode ; 981 } __packed HostCmd_SET_REGIONCODE_INFO; 982 983 // for HostCmd_CMD_SET_WMM_MODE 984 typedef struct { 985 FWCmdHdr CmdHdr; 986 uint16_t Action; // 0->unset, 1->set 987 } __packed HostCmd_FW_SetWMMMode; 988 989 typedef struct { 990 FWCmdHdr CmdHdr; 991 uint16_t Action; // 0->unset, 1->set 992 uint16_t IeListLen; 993 uint8_t IeList[200]; 994 } __packed HostCmd_FW_SetIEs; 995 996 #define EDCA_PARAM_SIZE 18 997 #define BA_PARAM_SIZE 2 998 999 typedef struct { 1000 FWCmdHdr CmdHdr; 1001 uint16_t Action; //0 = get all, 0x1 =set CWMin/Max, 0x2 = set TXOP , 0x4 =set AIFSN 1002 uint16_t TxOP; // in unit of 32 us 1003 uint32_t CWMax; // 0~15 1004 uint32_t CWMin; // 0~15 1005 uint8_t AIFSN; 1006 uint8_t TxQNum; // Tx Queue number. 1007 } __packed HostCmd_FW_SET_EDCA_PARAMS; 1008 1009 /****************************************************************************** 1010 @HWENCR@ 1011 Hardware Encryption related data structures and constant definitions. 1012 Note that all related changes are marked with the @HWENCR@ tag. 1013 *******************************************************************************/ 1014 1015 #define MAX_ENCR_KEY_LENGTH 16 /* max 128 bits - depends on type */ 1016 #define MIC_KEY_LENGTH 8 /* size of Tx/Rx MIC key - 8 bytes*/ 1017 1018 #define ENCR_KEY_TYPE_ID_WEP 0x00 /* Key type is WEP */ 1019 #define ENCR_KEY_TYPE_ID_TKIP 0x01 /* Key type is TKIP */ 1020 #define ENCR_KEY_TYPE_ID_AES 0x02 /* Key type is AES-CCMP */ 1021 1022 /* flags used in structure - same as driver EKF_XXX flags */ 1023 #define ENCR_KEY_FLAG_INUSE 0x00000001 /* indicate key is in use */ 1024 #define ENCR_KEY_FLAG_RXGROUPKEY 0x00000002 /* Group key for RX only */ 1025 #define ENCR_KEY_FLAG_TXGROUPKEY 0x00000004 /* Group key for TX */ 1026 #define ENCR_KEY_FLAG_PAIRWISE 0x00000008 /* pairwise */ 1027 #define ENCR_KEY_FLAG_RXONLY 0x00000010 /* only used for RX */ 1028 // These flags are new additions - for hardware encryption commands only. 1029 #define ENCR_KEY_FLAG_AUTHENTICATOR 0x00000020 /* Key is for Authenticator */ 1030 #define ENCR_KEY_FLAG_TSC_VALID 0x00000040 /* Sequence counters valid */ 1031 #define ENCR_KEY_FLAG_WEP_TXKEY 0x01000000 /* Tx key for WEP */ 1032 #define ENCR_KEY_FLAG_MICKEY_VALID 0x02000000 /* Tx/Rx MIC keys are valid */ 1033 1034 /* 1035 UPDATE_ENCRYPTION command action type. 1036 */ 1037 typedef enum { 1038 // request to enable/disable HW encryption 1039 EncrActionEnableHWEncryption, 1040 // request to set encryption key 1041 EncrActionTypeSetKey, 1042 // request to remove one or more keys 1043 EncrActionTypeRemoveKey, 1044 EncrActionTypeSetGroupKey 1045 } ENCR_ACTION_TYPE; 1046 1047 /* 1048 Key material definitions (for WEP, TKIP, & AES-CCMP) 1049 */ 1050 1051 /* 1052 WEP Key material definition 1053 ---------------------------- 1054 WEPKey --> An array of 'MAX_ENCR_KEY_LENGTH' bytes. 1055 Note that we do not support 152bit WEP keys 1056 */ 1057 typedef struct { 1058 // WEP key material (max 128bit) 1059 uint8_t KeyMaterial[ MAX_ENCR_KEY_LENGTH ]; 1060 } __packed WEP_TYPE_KEY; 1061 1062 /* 1063 TKIP Key material definition 1064 ---------------------------- 1065 This structure defines TKIP key material. Note that 1066 the TxMicKey and RxMicKey may or may not be valid. 1067 */ 1068 /* TKIP Sequence counter - 24 bits */ 1069 /* Incremented on each fragment MPDU */ 1070 typedef struct { 1071 uint16_t low; 1072 uint32_t high; 1073 } __packed ENCR_TKIPSEQCNT; 1074 1075 typedef struct { 1076 // TKIP Key material. Key type (group or pairwise key) is 1077 // determined by flags in KEY_PARAM_SET structure. 1078 uint8_t KeyMaterial[ MAX_ENCR_KEY_LENGTH ]; 1079 uint8_t TkipTxMicKey[ MIC_KEY_LENGTH ]; 1080 uint8_t TkipRxMicKey[ MIC_KEY_LENGTH ]; 1081 ENCR_TKIPSEQCNT TkipRsc; 1082 ENCR_TKIPSEQCNT TkipTsc; 1083 } __packed TKIP_TYPE_KEY; 1084 1085 /* 1086 AES-CCMP Key material definition 1087 -------------------------------- 1088 This structure defines AES-CCMP key material. 1089 */ 1090 typedef struct { 1091 // AES Key material 1092 uint8_t KeyMaterial[ MAX_ENCR_KEY_LENGTH ]; 1093 } __packed AES_TYPE_KEY; 1094 1095 /* 1096 Encryption key definition. 1097 -------------------------- 1098 This structure provides all required/essential 1099 information about the key being set/removed. 1100 */ 1101 typedef struct { 1102 uint16_t Length; // Total length of this structure 1103 uint16_t KeyTypeId; // Key type - WEP, TKIP or AES-CCMP. 1104 uint32_t KeyInfo; // key flags (ENCR_KEY_FLAG_XXX_ 1105 uint32_t KeyIndex; // For WEP only - actual key index 1106 uint16_t KeyLen; // Size of the key 1107 union { // Key material (variable size array) 1108 WEP_TYPE_KEY WepKey; 1109 TKIP_TYPE_KEY TkipKey; 1110 AES_TYPE_KEY AesKey; 1111 }__packed Key; 1112 #ifdef MWL_MBSS_SUPPORT 1113 uint8_t Macaddr[6]; 1114 #endif 1115 } __packed KEY_PARAM_SET; 1116 1117 /* 1118 HostCmd_FW_UPDATE_ENCRYPTION 1119 ---------------------------- 1120 Define data structure for updating firmware encryption keys. 1121 1122 */ 1123 typedef struct { 1124 FWCmdHdr CmdHdr; 1125 uint32_t ActionType; // ENCR_ACTION_TYPE 1126 uint32_t DataLength; // size of the data buffer attached. 1127 #ifdef MWL_MBSS_SUPPORT 1128 uint8_t macaddr[6]; 1129 #endif 1130 uint8_t ActionData[1]; 1131 } __packed HostCmd_FW_UPDATE_ENCRYPTION; 1132 1133 typedef struct { 1134 FWCmdHdr CmdHdr; 1135 uint32_t ActionType; // ENCR_ACTION_TYPE 1136 uint32_t DataLength; // size of the data buffer attached. 1137 KEY_PARAM_SET KeyParam; 1138 #ifndef MWL_MBSS_SUPPORT 1139 uint8_t Macaddr[8]; /* XXX? */ 1140 #endif 1141 } __packed HostCmd_FW_UPDATE_ENCRYPTION_SET_KEY; 1142 1143 typedef struct { 1144 // Rate flags - see above. 1145 uint32_t Flags; 1146 // Rate in 500Kbps units. 1147 uint8_t RateKbps; 1148 // 802.11 rate to conversion table index value. 1149 // This is the value required by the firmware/hardware. 1150 uint16_t RateCodeToIndex; 1151 }__packed RATE_INFO; 1152 1153 /* 1154 UPDATE_STADB command action type. 1155 */ 1156 typedef enum { 1157 // request to add entry to stainfo db 1158 StaInfoDbActionAddEntry, 1159 // request to modify peer entry 1160 StaInfoDbActionModifyEntry, 1161 // request to remove peer from stainfo db 1162 StaInfoDbActionRemoveEntry 1163 }__packed STADB_ACTION_TYPE; 1164 1165 /* 1166 @11E-BA@ 1167 802.11e/WMM Related command(s)/data structures 1168 */ 1169 1170 // Flag to indicate if the stream is an immediate block ack stream. 1171 // if this bit is not set, the stream is delayed block ack stream. 1172 #define BASTREAM_FLAG_DELAYED_TYPE 0x00 1173 #define BASTREAM_FLAG_IMMEDIATE_TYPE 0x01 1174 1175 // Flag to indicate the direction of the stream (upstream/downstream). 1176 // If this bit is not set, the direction is downstream. 1177 #define BASTREAM_FLAG_DIRECTION_UPSTREAM 0x00 1178 #define BASTREAM_FLAG_DIRECTION_DOWNSTREAM 0x02 1179 #define BASTREAM_FLAG_DIRECTION_DLP 0x04 1180 #define BASTREAM_FLAG_DIRECTION_BOTH 0x06 1181 1182 typedef enum { 1183 BaCreateStream, 1184 BaUpdateStream, 1185 BaDestroyStream, 1186 BaFlushStream, 1187 BaCheckCreateStream 1188 } BASTREAM_ACTION_TYPE; 1189 1190 typedef struct { 1191 uint32_t Context; 1192 } __packed BASTREAM_CONTEXT; 1193 1194 // parameters for block ack creation 1195 typedef struct { 1196 // BA Creation flags - see above 1197 uint32_t Flags; 1198 // idle threshold 1199 uint32_t IdleThrs; 1200 // block ack transmit threshold (after how many pkts should we send BAR?) 1201 uint32_t BarThrs; 1202 // receiver window size 1203 uint32_t WindowSize; 1204 // MAC Address of the BA partner 1205 uint8_t PeerMacAddr[6]; 1206 // Dialog Token 1207 uint8_t DialogToken; 1208 //TID for the traffic stream in this BA 1209 uint8_t Tid; 1210 // shared memory queue ID (not sure if this is required) 1211 uint8_t QueueId; 1212 uint8_t ParamInfo; 1213 // returned by firmware - firmware context pointer. 1214 // this context pointer will be passed to firmware for all future commands. 1215 BASTREAM_CONTEXT FwBaContext; 1216 uint8_t ResetSeqNo; /** 0 or 1**/ 1217 uint16_t StartSeqNo; 1218 1219 // proxy sta MAC Address 1220 uint8_t StaSrcMacAddr[6]; 1221 }__packed BASTREAM_CREATE_STREAM; 1222 1223 // new transmit sequence number information 1224 typedef struct { 1225 // BA flags - see above 1226 uint32_t Flags; 1227 // returned by firmware in the create ba stream response 1228 BASTREAM_CONTEXT FwBaContext; 1229 // new sequence number for this block ack stream 1230 uint16_t BaSeqNum; 1231 }__packed BASTREAM_UPDATE_STREAM; 1232 1233 typedef struct { 1234 // BA Stream flags 1235 uint32_t Flags; 1236 // returned by firmware in the create ba stream response 1237 BASTREAM_CONTEXT FwBaContext; 1238 }__packed BASTREAM_STREAM_INFO; 1239 1240 //Command to create/destroy block ACK 1241 typedef struct { 1242 FWCmdHdr CmdHdr; 1243 uint32_t ActionType; 1244 union 1245 { 1246 // information required to create BA Stream... 1247 BASTREAM_CREATE_STREAM CreateParams; 1248 // update starting/new sequence number etc. 1249 BASTREAM_UPDATE_STREAM UpdtSeqNum; 1250 // destroy an existing stream... 1251 BASTREAM_STREAM_INFO DestroyParams; 1252 // destroy an existing stream... 1253 BASTREAM_STREAM_INFO FlushParams; 1254 }__packed BaInfo; 1255 }__packed HostCmd_FW_BASTREAM; 1256 1257 // Define data structure for HostCmd_CMD_GET_WATCHDOG_BITMAP 1258 typedef struct { 1259 FWCmdHdr CmdHdr; 1260 uint8_t Watchdogbitmap; // for SW/BA 1261 } __packed HostCmd_FW_GET_WATCHDOG_BITMAP; 1262 1263 // Define data structure for HostCmd_CMD_SET_REGION_POWER 1264 typedef struct { 1265 FWCmdHdr CmdHdr; 1266 uint16_t MaxPowerLevel; 1267 uint16_t Reserved; 1268 } __packed HostCmd_DS_SET_REGION_POWER; 1269 1270 // Define data structure for HostCmd_CMD_SET_RATE_ADAPT_MODE 1271 typedef struct { 1272 FWCmdHdr CmdHdr; 1273 uint16_t Action; 1274 uint16_t RateAdaptMode; 1275 } __packed HostCmd_DS_SET_RATE_ADAPT_MODE; 1276 1277 // Define data structure for HostCmd_CMD_SET_LINKADAPT_CS_MODE 1278 typedef struct { 1279 FWCmdHdr CmdHdr; 1280 uint16_t Action; 1281 uint16_t CSMode; 1282 } __packed HostCmd_DS_SET_LINKADAPT_CS_MODE; 1283 1284 typedef struct { 1285 FWCmdHdr CmdHdr; 1286 uint32_t NProtectFlag; 1287 } __packed HostCmd_FW_SET_N_PROTECT_FLAG; 1288 1289 typedef struct { 1290 FWCmdHdr CmdHdr; 1291 uint8_t NProtectOpMode; 1292 } __packed HostCmd_FW_SET_N_PROTECT_OPMODE; 1293 1294 typedef struct { 1295 FWCmdHdr CmdHdr; 1296 uint8_t OptLevel; 1297 } __packed HostCmd_FW_SET_OPTIMIZATION_LEVEL; 1298 1299 typedef struct { 1300 FWCmdHdr CmdHdr; 1301 uint8_t annex; 1302 uint8_t index; 1303 uint8_t len; 1304 uint8_t Reserverd; 1305 #define CAL_TBL_SIZE 160 1306 uint8_t calTbl[CAL_TBL_SIZE]; 1307 } __packed HostCmd_FW_GET_CALTABLE; 1308 1309 typedef struct { 1310 FWCmdHdr CmdHdr; 1311 uint8_t Addr[6]; 1312 uint8_t Enable; 1313 uint8_t Mode; 1314 } __packed HostCmd_FW_SET_MIMOPSHT; 1315 1316 #define MAX_BEACON_SIZE 1024 1317 typedef struct { 1318 FWCmdHdr CmdHdr; 1319 uint16_t Bcnlen; 1320 uint8_t Reserverd[2]; 1321 uint8_t Bcn[MAX_BEACON_SIZE]; 1322 } __packed HostCmd_FW_GET_BEACON; 1323 1324 typedef struct { 1325 FWCmdHdr CmdHdr; 1326 uint8_t NumberOfPowersave; 1327 uint8_t reserved; 1328 } __packed HostCmd_SET_POWERSAVESTATION; 1329 1330 typedef struct { 1331 FWCmdHdr CmdHdr; 1332 uint16_t Aid; 1333 uint32_t Set; 1334 uint8_t reserved; 1335 } __packed HostCmd_SET_TIM; 1336 1337 typedef struct { 1338 FWCmdHdr CmdHdr; 1339 uint8_t TrafficMap[251]; 1340 uint8_t reserved; 1341 } __packed HostCmd_GET_TIM; 1342 1343 typedef struct { 1344 FWCmdHdr CmdHdr; 1345 uint8_t MacAddr[6]; 1346 uint8_t TID; 1347 uint16_t SeqNo; 1348 uint8_t reserved; 1349 } __packed HostCmd_GET_SEQNO; 1350 1351 typedef struct { 1352 FWCmdHdr CmdHdr; 1353 uint32_t Enable; //0 -- Disbale. or 1 -- Enable. 1354 } __packed HostCmd_DWDS_ENABLE; 1355 1356 typedef struct { 1357 FWCmdHdr CmdHdr; 1358 uint16_t Action; /* 0: Get. 1:Set */ 1359 uint32_t Option; /* 0: default. 1:Aggressive */ 1360 uint32_t Threshold; /* Range 0-200, default 8 */ 1361 }__packed HostCmd_FW_AMPDU_RETRY_RATEDROP_MODE; 1362 1363 typedef struct { 1364 FWCmdHdr CmdHdr; 1365 uint32_t Enable; /* 0 -- Disable. or 1 -- Enable */ 1366 }__packed HostCmd_CFEND_ENABLE; 1367 #endif /* _MWL_HALREG_H_ */ 1368