1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2007-2009 Sam Leffler, Errno Consulting 5 * Copyright (c) 2007-2009 Marvell Semiconductor, Inc. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer, 13 * without modification. 14 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 15 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 16 * redistribution must be conditioned upon including a substantially 17 * similar Disclaimer requirement for further binary redistribution. 18 * 19 * NO WARRANTY 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 22 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 23 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 24 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 25 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 28 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGES. 31 * 32 * $FreeBSD$ 33 */ 34 35 #ifndef _MWL_HAL_H_ 36 #define _MWL_HAL_H_ 37 /* 38 * Hardware Access Layer for Marvell Wireless Devices. 39 */ 40 41 #define MWL_MBSS_SUPPORT /* enable multi-bss support */ 42 43 /* 44 * Define total number of TX queues in the shared memory. 45 * This count includes the EDCA queues, Block Ack queues, and HCCA queues 46 * In addition to this, there could be a management packet queue some 47 * time in the future 48 */ 49 #define MWL_NUM_EDCA_QUEUES 4 50 #define MWL_NUM_HCCA_QUEUES 0 51 #define MWL_NUM_BA_QUEUES 0 52 #define MWL_NUM_MGMT_QUEUES 0 53 #define MWL_NUM_ACK_QUEUES 0 54 #define MWL_NUM_TX_QUEUES \ 55 (MWL_NUM_EDCA_QUEUES + MWL_NUM_HCCA_QUEUES + MWL_NUM_BA_QUEUES + \ 56 MWL_NUM_MGMT_QUEUES + MWL_NUM_ACK_QUEUES) 57 #define MWL_MAX_RXWCB_QUEUES 1 58 59 #define MWL_MAX_SUPPORTED_RATES 12 60 #define MWL_MAX_SUPPORTED_MCS 32 61 62 typedef enum { 63 MWL_HAL_OK 64 } MWL_HAL_STATUS; 65 66 /* 67 * Transmit queue assignment. 68 */ 69 enum { 70 MWL_WME_AC_BK = 0, /* background access category */ 71 MWL_WME_AC_BE = 1, /* best effort access category*/ 72 MWL_WME_AC_VI = 2, /* video access category */ 73 MWL_WME_AC_VO = 3, /* voice access category */ 74 }; 75 76 struct mwl_hal { 77 bus_space_handle_t mh_ioh; /* BAR 1 copied from softc */ 78 bus_space_tag_t mh_iot; 79 uint32_t mh_imask; /* interrupt mask */ 80 /* remainder is opaque to driver */ 81 }; 82 struct mwl_hal *mwl_hal_attach(device_t dev, uint16_t devid, 83 bus_space_handle_t ioh, bus_space_tag_t iot, bus_dma_tag_t tag); 84 void mwl_hal_detach(struct mwl_hal *); 85 86 /* 87 * Query whether multi-bss support is available/enabled. 88 */ 89 int mwl_hal_ismbsscapable(struct mwl_hal *); 90 91 typedef enum { 92 MWL_HAL_AP, 93 MWL_HAL_STA, /* infrastructure mode */ 94 MWL_HAL_IBSS /* ibss/adhoc mode */ 95 } MWL_HAL_BSSTYPE; 96 struct mwl_hal_vap; 97 98 struct mwl_hal_vap *mwl_hal_newvap(struct mwl_hal *, MWL_HAL_BSSTYPE, 99 const uint8_t mac[6]); 100 void mwl_hal_delvap(struct mwl_hal_vap *); 101 102 enum { 103 MWL_HAL_DEBUG_SENDCMD = 0x00000001, 104 MWL_HAL_DEBUG_CMDDONE = 0x00000002, 105 MWL_HAL_DEBUG_IGNHANG = 0x00000004, 106 }; 107 void mwl_hal_setdebug(struct mwl_hal *, int); 108 int mwl_hal_getdebug(struct mwl_hal *); 109 110 typedef struct { 111 uint16_t freqLow, freqHigh; 112 int nchannels; 113 struct mwl_hal_channel { 114 uint16_t freq; /* channel center */ 115 uint8_t ieee; /* channel number */ 116 int8_t maxTxPow; /* max tx power (dBm) */ 117 uint8_t targetPowers[4];/* target powers (dBm) */ 118 #define MWL_HAL_MAXCHAN 40 119 } channels[MWL_HAL_MAXCHAN]; 120 } MWL_HAL_CHANNELINFO; 121 int mwl_hal_getchannelinfo(struct mwl_hal *, int band, int chw, 122 const MWL_HAL_CHANNELINFO **); 123 124 /* 125 * Return the current ISR setting and clear the cause. 126 */ 127 static __inline void 128 mwl_hal_getisr(struct mwl_hal *mh, uint32_t *status) 129 { 130 #define MACREG_REG_A2H_INTERRUPT_CAUSE 0x00000C30 // (From ARM to host) 131 #define MACREG_REG_INT_CODE 0x00000C14 132 uint32_t cause; 133 134 cause = bus_space_read_4(mh->mh_iot, mh->mh_ioh, 135 MACREG_REG_A2H_INTERRUPT_CAUSE); 136 if (cause == 0xffffffff) { /* card removed */ 137 cause = 0; 138 } else if (cause != 0) { 139 /* clear cause bits */ 140 bus_space_write_4(mh->mh_iot, mh->mh_ioh, 141 MACREG_REG_A2H_INTERRUPT_CAUSE, cause &~ mh->mh_imask); 142 (void) bus_space_read_4(mh->mh_iot, mh->mh_ioh, 143 MACREG_REG_INT_CODE); 144 cause &= mh->mh_imask; 145 } 146 *status = cause; 147 #undef MACREG_REG_INT_CODE 148 #undef MACREG_REG_A2H_INTERRUPT_CAUSE 149 } 150 151 void mwl_hal_intrset(struct mwl_hal *mh, uint32_t mask); 152 153 /* 154 * Kick the firmware to tell it there are new tx descriptors 155 * for processing. The driver says what h/w q has work in 156 * case the f/w ever gets smarter. 157 */ 158 static __inline void 159 mwl_hal_txstart(struct mwl_hal *mh, int qnum) 160 { 161 #define MACREG_REG_H2A_INTERRUPT_EVENTS 0x00000C18 // (From host to ARM) 162 #define MACREG_H2ARIC_BIT_PPA_READY 0x00000001 // bit 0 163 #define MACREG_REG_INT_CODE 0x00000C14 164 165 bus_space_write_4(mh->mh_iot, mh->mh_ioh, 166 MACREG_REG_H2A_INTERRUPT_EVENTS, MACREG_H2ARIC_BIT_PPA_READY); 167 (void) bus_space_read_4(mh->mh_iot, mh->mh_ioh, MACREG_REG_INT_CODE); 168 #undef MACREG_REG_INT_CODE 169 #undef MACREG_H2ARIC_BIT_PPA_READY 170 #undef MACREG_REG_H2A_INTERRUPT_EVENTS 171 } 172 173 void mwl_hal_cmddone(struct mwl_hal *mh); 174 175 typedef struct { 176 uint32_t FreqBand : 6, 177 #define MWL_FREQ_BAND_2DOT4GHZ 0x1 178 #define MWL_FREQ_BAND_5GHZ 0x4 179 ChnlWidth: 5, 180 #define MWL_CH_10_MHz_WIDTH 0x1 181 #define MWL_CH_20_MHz_WIDTH 0x2 182 #define MWL_CH_40_MHz_WIDTH 0x4 183 ExtChnlOffset: 2, 184 #define MWL_EXT_CH_NONE 0x0 185 #define MWL_EXT_CH_ABOVE_CTRL_CH 0x1 186 #define MWL_EXT_CH_BELOW_CTRL_CH 0x3 187 : 19; /* reserved */ 188 } MWL_HAL_CHANNEL_FLAGS; 189 190 typedef struct { 191 uint32_t channel; 192 MWL_HAL_CHANNEL_FLAGS channelFlags; 193 } MWL_HAL_CHANNEL; 194 195 /* 196 * Get Hardware/Firmware capabilities. 197 */ 198 struct mwl_hal_hwspec { 199 uint8_t hwVersion; /* version of the HW */ 200 uint8_t hostInterface; /* host interface */ 201 uint16_t maxNumWCB; /* max # of WCB FW handles */ 202 uint16_t maxNumMCAddr; /* max # of mcast addresses FW handles*/ 203 uint16_t maxNumTxWcb; /* max # of tx descs per WCB */ 204 uint8_t macAddr[6]; /* MAC address programmed in HW */ 205 uint16_t regionCode; /* EEPROM region code */ 206 uint16_t numAntennas; /* Number of antenna used */ 207 uint32_t fwReleaseNumber; /* firmware release number */ 208 uint32_t wcbBase0; 209 uint32_t rxDescRead; 210 uint32_t rxDescWrite; 211 uint32_t ulFwAwakeCookie; 212 uint32_t wcbBase[MWL_NUM_TX_QUEUES - MWL_NUM_ACK_QUEUES]; 213 }; 214 int mwl_hal_gethwspecs(struct mwl_hal *mh, struct mwl_hal_hwspec *); 215 216 /* 217 * Supply tx/rx dma-related settings to the firmware. 218 */ 219 struct mwl_hal_txrxdma { 220 uint32_t maxNumWCB; /* max # of WCB FW handles */ 221 uint32_t maxNumTxWcb; /* max # of tx descs per WCB */ 222 uint32_t rxDescRead; 223 uint32_t rxDescWrite; 224 uint32_t wcbBase[MWL_NUM_TX_QUEUES - MWL_NUM_ACK_QUEUES]; 225 }; 226 int mwl_hal_sethwdma(struct mwl_hal *mh, const struct mwl_hal_txrxdma *); 227 228 /* 229 * Get Hardware Statistics. 230 * 231 * Items marked with ! are deprecated and not ever updated. In 232 * some cases this is because work has been moved to the host (e.g. 233 * rx defragmentation). 234 */ 235 struct mwl_hal_hwstats { 236 uint32_t TxRetrySuccesses; /* tx success w/ 1 retry */ 237 uint32_t TxMultipleRetrySuccesses;/* tx success w/ >1 retry */ 238 uint32_t TxFailures; /* tx fail due to no ACK */ 239 uint32_t RTSSuccesses; /* CTS rx'd for RTS */ 240 uint32_t RTSFailures; /* CTS not rx'd for RTS */ 241 uint32_t AckFailures; /* same as TxFailures */ 242 uint32_t RxDuplicateFrames; /* rx discard for dup seqno */ 243 uint32_t FCSErrorCount; /* rx discard for bad FCS */ 244 uint32_t TxWatchDogTimeouts; /* MAC tx hang (f/w recovery) */ 245 uint32_t RxOverflows; /* no f/w buffer for rx data */ 246 uint32_t RxFragErrors; /* !rx fail due to defrag */ 247 uint32_t RxMemErrors; /* out of mem or desc corrupted 248 in some way */ 249 uint32_t RxPointerErrors; /* MAC internal ptr problem */ 250 uint32_t TxUnderflows; /* !tx underflow on dma */ 251 uint32_t TxDone; /* MAC tx ops completed 252 (possibly w/ error) */ 253 uint32_t TxDoneBufTryPut; /* ! */ 254 uint32_t TxDoneBufPut; /* same as TxDone */ 255 uint32_t Wait4TxBuf; /* !no f/w buf avail when 256 supplied a tx descriptor */ 257 uint32_t TxAttempts; /* tx descriptors processed */ 258 uint32_t TxSuccesses; /* tx attempts successful */ 259 uint32_t TxFragments; /* tx with fragmentation */ 260 uint32_t TxMulticasts; /* tx multicast frames */ 261 uint32_t RxNonCtlPkts; /* rx non-control frames */ 262 uint32_t RxMulticasts; /* rx multicast frames */ 263 uint32_t RxUndecryptableFrames; /* rx failed due to crypto */ 264 uint32_t RxICVErrors; /* rx failed due to ICV check */ 265 uint32_t RxExcludedFrames; /* rx discarded, e.g. bssid */ 266 }; 267 int mwl_hal_gethwstats(struct mwl_hal *mh, struct mwl_hal_hwstats *); 268 269 /* 270 * Set HT Guard Interval. 271 * 272 * GIType = 0: enable long and short GI 273 * GIType = 1: enable short GI 274 * GIType = 2: enable long GI 275 */ 276 int mwl_hal_sethtgi(struct mwl_hal_vap *, int GIType); 277 278 /* 279 * Set Radio Configuration. 280 * 281 * onoff != 0 turns radio on; otherwise off. 282 * if radio is enabled, the preamble is set too. 283 */ 284 typedef enum { 285 WL_LONG_PREAMBLE = 1, 286 WL_SHORT_PREAMBLE = 3, 287 WL_AUTO_PREAMBLE = 5, 288 } MWL_HAL_PREAMBLE; 289 int mwl_hal_setradio(struct mwl_hal *mh, int onoff, MWL_HAL_PREAMBLE preamble); 290 291 /* 292 * Set Antenna Configuration (legacy operation). 293 * 294 * The RX antenna can be selected using the bitmask 295 * ant (bit 0 = antenna 1, bit 1 = antenna 2, etc.) 296 * (diversity?XXX) 297 */ 298 typedef enum { 299 WL_ANTENNATYPE_RX = 1, 300 WL_ANTENNATYPE_TX = 2, 301 } MWL_HAL_ANTENNA; 302 int mwl_hal_setantenna(struct mwl_hal *mh, MWL_HAL_ANTENNA dirSet, int ant); 303 304 /* 305 * Set the threshold for using RTS on TX. 306 */ 307 int mwl_hal_setrtsthreshold(struct mwl_hal_vap *, int threshold); 308 309 /* 310 * Set the adapter to operate in infrastructure mode. 311 */ 312 int mwl_hal_setinframode(struct mwl_hal_vap *); 313 314 /* 315 * Set Radar Detection Configuration. 316 */ 317 typedef enum { 318 DR_DFS_DISABLE = 0, 319 DR_CHK_CHANNEL_AVAILABLE_START = 1, 320 DR_CHK_CHANNEL_AVAILABLE_STOP = 2, 321 DR_IN_SERVICE_MONITOR_START = 3 322 } MWL_HAL_RADAR; 323 int mwl_hal_setradardetection(struct mwl_hal *mh, MWL_HAL_RADAR action); 324 /* 325 * Set the region code that selects the radar bin'ing agorithm. 326 */ 327 int mwl_hal_setregioncode(struct mwl_hal *mh, int regionCode); 328 329 /* 330 * Initiate an 802.11h-based channel switch. The CSA ie 331 * is included in the next beacon(s) using the specified 332 * information and the firmware counts down until switch 333 * time after which it notifies the driver by delivering 334 * an interrupt with MACREG_A2HRIC_BIT_CHAN_SWITCH set in 335 * the cause register. 336 */ 337 int mwl_hal_setchannelswitchie(struct mwl_hal *, 338 const MWL_HAL_CHANNEL *nextchan, uint32_t mode, uint32_t count); 339 340 /* 341 * Set regdomain code (IEEE SKU). 342 */ 343 enum { 344 DOMAIN_CODE_FCC = 0x10, /* USA */ 345 DOMAIN_CODE_IC = 0x20, /* Canda */ 346 DOMAIN_CODE_ETSI = 0x30, /* Europe */ 347 DOMAIN_CODE_SPAIN = 0x31, /* Spain */ 348 DOMAIN_CODE_FRANCE = 0x32, /* France */ 349 DOMAIN_CODE_ETSI_131 = 0x130,/* ETSI w/ 1.3.1 radar type */ 350 DOMAIN_CODE_MKK = 0x40, /* Japan */ 351 DOMAIN_CODE_MKK2 = 0x41, /* Japan w/ 10MHz chan spacing */ 352 DOMAIN_CODE_DGT = 0x80, /* Taiwan */ 353 DOMAIN_CODE_AUS = 0x81, /* Australia */ 354 }; 355 356 /* 357 * Transmit rate control. Rate codes with bit 0x80 set are 358 * interpreted as MCS codes (this limits us to 0-127). The 359 * transmit rate can be set to a single fixed rate or can 360 * be configured to start at an initial rate and drop based 361 * on retry counts. 362 */ 363 typedef enum { 364 RATE_AUTO = 0, /* rate selected by firmware */ 365 RATE_FIXED = 2, /* rate fixed */ 366 RATE_FIXED_DROP = 1, /* rate starts fixed but may drop */ 367 } MWL_HAL_TXRATE_HANDLING; 368 369 typedef struct { 370 uint8_t McastRate; /* rate for multicast frames */ 371 #define RATE_MCS 0x80 /* rate is an MCS index */ 372 uint8_t MgtRate; /* rate for management frames */ 373 struct { 374 uint8_t TryCount; /* try this many times */ 375 uint8_t Rate; /* use this tx rate */ 376 } RateSeries[4]; /* rate series */ 377 } MWL_HAL_TXRATE; 378 379 int mwl_hal_settxrate(struct mwl_hal_vap *, 380 MWL_HAL_TXRATE_HANDLING handling, const MWL_HAL_TXRATE *rate); 381 /* NB: hack for setting rates while scanning */ 382 int mwl_hal_settxrate_auto(struct mwl_hal *, const MWL_HAL_TXRATE *rate); 383 384 /* 385 * Set the Slot Time Configuration. 386 * NB: usecs must either be 9 or 20 for now. 387 */ 388 int mwl_hal_setslottime(struct mwl_hal *mh, int usecs); 389 390 /* 391 * Adjust current transmit power settings according to powerLevel. 392 * This translates to low/medium/high use of the current tx power rate tables. 393 */ 394 int mwl_hal_adjusttxpower(struct mwl_hal *, uint32_t powerLevel); 395 /* 396 * Set the transmit power for the specified channel; the power 397 * is taken from the calibration data and capped according to 398 * the specified max tx power (in dBm). 399 */ 400 int mwl_hal_settxpower(struct mwl_hal *, const MWL_HAL_CHANNEL *, 401 uint8_t maxtxpow); 402 403 /* 404 * Set the Multicast Address Filter. 405 * A packed array addresses is specified. 406 */ 407 #define MWL_HAL_MCAST_MAX 32 408 int mwl_hal_setmcast(struct mwl_hal *mh, int nmc, const uint8_t macs[]); 409 410 /* 411 * Crypto Configuration. 412 */ 413 typedef struct { 414 uint16_t pad; 415 uint16_t keyTypeId; 416 #define KEY_TYPE_ID_WEP 0 417 #define KEY_TYPE_ID_TKIP 1 418 #define KEY_TYPE_ID_AES 2 /* AES-CCMP */ 419 uint32_t keyFlags; 420 #define KEY_FLAG_INUSE 0x00000001 /* indicate key is in use */ 421 #define KEY_FLAG_RXGROUPKEY 0x00000002 /* Group key for RX only */ 422 #define KEY_FLAG_TXGROUPKEY 0x00000004 /* Group key for TX */ 423 #define KEY_FLAG_PAIRWISE 0x00000008 /* pairwise */ 424 #define KEY_FLAG_RXONLY 0x00000010 /* only used for RX */ 425 #define KEY_FLAG_AUTHENTICATOR 0x00000020 /* Key is for Authenticator */ 426 #define KEY_FLAG_TSC_VALID 0x00000040 /* Sequence counters valid */ 427 #define KEY_FLAG_WEP_TXKEY 0x01000000 /* Tx key for WEP */ 428 #define KEY_FLAG_MICKEY_VALID 0x02000000 /* Tx/Rx MIC keys are valid */ 429 uint32_t keyIndex; /* for WEP only; actual key index */ 430 uint16_t keyLen; /* key size in bytes */ 431 union { /* key material, keyLen gives size */ 432 uint8_t wep[16]; /* enough for 128 bits */ 433 uint8_t aes[16]; 434 struct { 435 /* NB: group or pairwise key is determined by keyFlags */ 436 uint8_t keyMaterial[16]; 437 uint8_t txMic[8]; 438 uint8_t rxMic[8]; 439 struct { 440 uint16_t low; 441 uint32_t high; 442 } rsc; 443 struct { 444 uint16_t low; 445 uint32_t high; 446 } tsc; 447 } __packed tkip; 448 }__packed key; 449 } __packed MWL_HAL_KEYVAL; 450 451 /* 452 * Plumb a unicast/group key. The mac address identifies 453 * the station, use the broadcast address for group keys. 454 */ 455 int mwl_hal_keyset(struct mwl_hal_vap *, const MWL_HAL_KEYVAL *kv, 456 const uint8_t mac[6]); 457 458 /* 459 * Plumb a unicast/group key. The mac address identifies 460 * the station, use the broadcast address for group keys. 461 */ 462 int mwl_hal_keyreset(struct mwl_hal_vap *, const MWL_HAL_KEYVAL *kv, 463 const uint8_t mac[6]); 464 465 /* 466 * Set the MAC address. 467 */ 468 int mwl_hal_setmac(struct mwl_hal_vap *, const uint8_t addr[6]); 469 470 /* 471 * Set the beacon frame contents. The firmware will modify the 472 * frame only to add CSA and WME ie's and to fill in dynamic fields 473 * such as the sequence #.. 474 */ 475 int mwl_hal_setbeacon(struct mwl_hal_vap *, const void *, size_t); 476 477 /* 478 * Handle power save operation for AP operation when offloaded to 479 * the host (SET_HW_SPEC_HOST_POWERSAVE). mwl_hal_setbss_powersave 480 * informs the firmware whether 1+ associated stations are in power 481 * save mode (it will then buffer mcast traffic). mwl_hal_setsta_powersave 482 * specifies a change in power save state for an associated station. 483 */ 484 int mwl_hal_setpowersave_bss(struct mwl_hal_vap *, uint8_t nsta); 485 int mwl_hal_setpowersave_sta(struct mwl_hal_vap *, uint16_t aid, int ena); 486 487 /* 488 * Set Association Configuration for station operation. 489 */ 490 int mwl_hal_setassocid(struct mwl_hal_vap *, const uint8_t bssId[6], 491 uint16_t assocId); 492 493 /* 494 * Set the current channel. 495 */ 496 int mwl_hal_setchannel(struct mwl_hal *mh, const MWL_HAL_CHANNEL *c); 497 498 /* 499 * A-MPDU Block Ack (BA) stream support. There are several 500 * streams that the driver must multiplex. Once assigned 501 * to a station the driver queues frames to a corresponding 502 * transmit queue and the firmware handles all the work. 503 * 504 * XXX no way to find out how many streams are supported 505 */ 506 typedef struct { 507 void *data[2]; /* opaque data */ 508 int txq; 509 } MWL_HAL_BASTREAM; 510 511 const MWL_HAL_BASTREAM *mwl_hal_bastream_alloc(struct mwl_hal_vap *, 512 int ba_type, const uint8_t Macaddr[6], uint8_t Tid, 513 uint8_t ParamInfo, void *, void *); 514 const MWL_HAL_BASTREAM *mwl_hal_bastream_lookup(struct mwl_hal *mh, int s); 515 int mwl_hal_bastream_create(struct mwl_hal_vap *, const MWL_HAL_BASTREAM *, 516 int BarThrs, int WindowSize, uint16_t seqno); 517 int mwl_hal_bastream_destroy(struct mwl_hal *mh, const MWL_HAL_BASTREAM *); 518 int mwl_hal_getwatchdogbitmap(struct mwl_hal *mh, uint8_t bitmap[1]); 519 int mwl_hal_bastream_get_seqno(struct mwl_hal *mh, const MWL_HAL_BASTREAM *, 520 const uint8_t Macaddr[6], uint16_t *pseqno); 521 /* for sysctl hookup for debugging */ 522 void mwl_hal_setbastreams(struct mwl_hal *mh, int mask); 523 int mwl_hal_getbastreams(struct mwl_hal *mh); 524 525 /* 526 * Set/get A-MPDU aggregation parameters. 527 */ 528 int mwl_hal_setaggampduratemode(struct mwl_hal *, int mode, int thresh); 529 int mwl_hal_getaggampduratemode(struct mwl_hal *, int *mode, int *thresh); 530 531 /* 532 * Inform the firmware of a new association station. 533 * The address is the MAC address of the peer station. 534 * The AID is supplied sans the 0xc000 bits. The station 535 * ID is defined by the caller. The peer information must 536 * be supplied. 537 * 538 * NB: All values are in host byte order; any byte swapping 539 * is handled by the hal. 540 */ 541 typedef struct { 542 uint32_t LegacyRateBitMap; 543 uint32_t HTRateBitMap; 544 uint16_t CapInfo; 545 uint16_t HTCapabilitiesInfo; 546 uint8_t MacHTParamInfo; 547 uint8_t Rev; 548 struct { 549 uint8_t ControlChan; 550 uint8_t AddChan; 551 uint8_t OpMode; 552 uint8_t stbc; 553 } __packed AddHtInfo; 554 } __packed MWL_HAL_PEERINFO; 555 int mwl_hal_newstation(struct mwl_hal_vap *, const uint8_t addr[6], 556 uint16_t aid, uint16_t sid, const MWL_HAL_PEERINFO *, 557 int isQosSta, int wmeInfo); 558 int mwl_hal_delstation(struct mwl_hal_vap *, const uint8_t addr[6]); 559 560 /* 561 * Prod the firmware to age packets on station power 562 * save queues and reap frames on the tx aggregation q's. 563 */ 564 int mwl_hal_setkeepalive(struct mwl_hal *mh); 565 566 typedef enum { 567 AP_MODE_B_ONLY = 1, 568 AP_MODE_G_ONLY = 2, 569 AP_MODE_MIXED = 3, 570 AP_MODE_N_ONLY = 4, 571 AP_MODE_BandN = 5, 572 AP_MODE_GandN = 6, 573 AP_MODE_BandGandN = 7, 574 AP_MODE_A_ONLY = 8, 575 AP_MODE_AandG = 10, 576 AP_MODE_AandN = 12, 577 } MWL_HAL_APMODE; 578 int mwl_hal_setapmode(struct mwl_hal_vap *, MWL_HAL_APMODE); 579 580 /* 581 * Enable/disable firmware operation. mwl_hal_start is 582 * also used to sync state updates, e.g. beacon frame 583 * reconstruction after content changes. 584 */ 585 int mwl_hal_stop(struct mwl_hal_vap *); 586 int mwl_hal_start(struct mwl_hal_vap *); 587 588 /* 589 * Add/Remove station from Power Save TIM handling. 590 * 591 * If set is non-zero the AID is enabled, if zero it is removed. 592 */ 593 int mwl_hal_updatetim(struct mwl_hal_vap *, uint16_t aid, int set); 594 595 /* 596 * Enable/disable 11g protection use. This call specifies 597 * the ERP information element flags to use. 598 */ 599 int mwl_hal_setgprot(struct mwl_hal *, int); 600 601 /* 602 * Enable/disable WMM support. 603 */ 604 int mwl_hal_setwmm(struct mwl_hal *mh, int onoff); 605 606 /* 607 * Configure WMM EDCA parameters for the specified h/w ring. 608 */ 609 int mwl_hal_setedcaparams(struct mwl_hal *mh, uint8_t qnum, 610 uint32_t CWmin, uint32_t CWmax, uint8_t AIFSN, uint16_t TXOPLimit); 611 612 /* 613 * Configure rate adaptation for indooor/outdoor operation. 614 * XXX wtf? 615 */ 616 int mwl_hal_setrateadaptmode(struct mwl_hal *mh, uint16_t mode); 617 618 typedef enum { 619 CSMODE_CONSERVATIVE = 0, 620 CSMODE_AGGRESSIVE = 1, 621 CSMODE_AUTO_ENA = 2, 622 CSMODE_AUTO_DIS = 3, 623 } MWL_HAL_CSMODE; 624 int mwl_hal_setcsmode(struct mwl_hal *mh, MWL_HAL_CSMODE csmode); 625 626 /* 627 * Configure 11n protection on/off. 628 */ 629 typedef enum { 630 HTPROTECT_NONE = 0, /* disable */ 631 HTPROTECT_OPT = 1, /* optional */ 632 HTPROTECT_HT20 = 2, /* protect only HT20 */ 633 HTPROTECT_HT2040 = 3, /* protect HT20/40 */ 634 HTPROTECT_AUTO = 4, /* automatic */ 635 } MWL_HAL_HTPROTECT; 636 int mwl_hal_setnprot(struct mwl_hal_vap *, MWL_HAL_HTPROTECT mode); 637 /* 638 * Configure 11n protection mechanism for when protection is enabled. 639 */ 640 int mwl_hal_setnprotmode(struct mwl_hal_vap *, uint8_t mode); 641 642 /* 643 * Enable/disable Marvell "turbo mode"". 644 */ 645 int mwl_hal_setoptimizationlevel(struct mwl_hal *mh, int onoff); 646 647 /* 648 * Set MIMO Power Save handling for a station; the enable and mode 649 * values come directly from the Action frame. 650 */ 651 int mwl_hal_setmimops(struct mwl_hal *mh, const uint8_t addr[6], 652 uint8_t enable, uint8_t mode); 653 654 /* 655 * Retrieve the region/country code from the EEPROM. 656 */ 657 int mwl_hal_getregioncode(struct mwl_hal *mh, uint8_t *countryCode); 658 int mwl_hal_GetBeacon(struct mwl_hal *mh, uint8_t *pBcn, uint16_t *pLen); 659 int mwl_hal_SetRifs(struct mwl_hal *mh, uint8_t QNum); 660 661 /* 662 * Set/get promiscuous mode. 663 */ 664 int mwl_hal_setpromisc(struct mwl_hal *, int ena); 665 int mwl_hal_getpromisc(struct mwl_hal *); 666 667 /* 668 * Enable/disable CF-End use. 669 */ 670 int mwl_hal_setcfend(struct mwl_hal *, int ena); 671 672 /* 673 * Enable/disable sta-mode DWDS use/operation. 674 */ 675 int mwl_hal_setdwds(struct mwl_hal *, int ena); 676 677 /* 678 * Diagnostic interface. This is an open-ended interface that 679 * is opaque to applications. Diagnostic programs use this to 680 * retrieve internal data structures, etc. There is no guarantee 681 * that calling conventions for calls other than MWL_DIAG_REVS 682 * are stable between HAL releases; a diagnostic application must 683 * use the HAL revision information to deal with ABI/API differences. 684 */ 685 int mwl_hal_getdiagstate(struct mwl_hal *mh, int request, 686 const void *args, uint32_t argsize, 687 void **result, uint32_t *resultsize); 688 689 int mwl_hal_fwload(struct mwl_hal *mh, void *fwargs); 690 #endif /* _MWL_HAL_H_ */ 691