1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2007-2009 Sam Leffler, Errno Consulting 5 * Copyright (c) 2007-2009 Marvell Semiconductor, Inc. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer, 13 * without modification. 14 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 15 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 16 * redistribution must be conditioned upon including a substantially 17 * similar Disclaimer requirement for further binary redistribution. 18 * 19 * NO WARRANTY 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 22 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 23 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 24 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 25 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 28 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGES. 31 */ 32 33 /* 34 * Definitions for the Marvell 88W8363 Wireless LAN controller. 35 */ 36 #ifndef _DEV_MWL_MVVAR_H 37 #define _DEV_MWL_MVVAR_H 38 39 #include <sys/endian.h> 40 #include <sys/bus.h> 41 #include <net80211/ieee80211_radiotap.h> 42 #include <dev/mwl/mwlhal.h> 43 #include <dev/mwl/mwlreg.h> 44 #include <dev/mwl/if_mwlioctl.h> 45 46 #ifndef MWL_TXBUF 47 #define MWL_TXBUF 256 /* number of TX descriptors/buffers */ 48 #endif 49 #ifndef MWL_TXACKBUF 50 #define MWL_TXACKBUF (MWL_TXBUF/2) /* number of TX ACK desc's/buffers */ 51 #endif 52 #ifndef MWL_RXDESC 53 #define MWL_RXDESC 256 /* number of RX descriptors */ 54 #endif 55 #ifndef MWL_RXBUF 56 #define MWL_RXBUF ((5*MWL_RXDESC)/2)/* number of RX dma buffers */ 57 #endif 58 #ifndef MWL_MAXBA 59 #define MWL_MAXBA 2 /* max BA streams/sta */ 60 #endif 61 62 #ifdef MWL_SGDMA_SUPPORT 63 #define MWL_TXDESC 6 /* max tx descriptors/segments */ 64 #else 65 #define MWL_TXDESC 1 /* max tx descriptors/segments */ 66 #endif 67 #ifndef MWL_AGGR_SIZE 68 #define MWL_AGGR_SIZE 3839 /* max tx aggregation size */ 69 #endif 70 #define MWL_AGEINTERVAL 1 /* poke f/w every sec to age q's */ 71 #define MWL_MAXSTAID 64 /* max of 64 stations */ 72 73 /* 74 * DMA state for tx/rx descriptors. 75 */ 76 77 /* 78 * Software backed version of tx/rx descriptors. We keep 79 * the software state out of the h/w descriptor structure 80 * so that may be allocated in uncached memory w/o paying 81 * performance hit. 82 */ 83 struct mwl_txbuf { 84 STAILQ_ENTRY(mwl_txbuf) bf_list; 85 void *bf_desc; /* h/w descriptor */ 86 bus_addr_t bf_daddr; /* physical addr of desc */ 87 bus_dmamap_t bf_dmamap; /* DMA map for descriptors */ 88 int bf_nseg; 89 bus_dma_segment_t bf_segs[MWL_TXDESC]; 90 struct mbuf *bf_m; 91 struct ieee80211_node *bf_node; 92 struct mwl_txq *bf_txq; /* backpointer to tx q/ring */ 93 }; 94 typedef STAILQ_HEAD(, mwl_txbuf) mwl_txbufhead; 95 96 /* 97 * Common "base class" for tx/rx descriptor resources 98 * allocated using the bus dma api. 99 */ 100 struct mwl_descdma { 101 const char* dd_name; 102 void *dd_desc; /* descriptors */ 103 bus_addr_t dd_desc_paddr; /* physical addr of dd_desc */ 104 bus_size_t dd_desc_len; /* size of dd_desc */ 105 bus_dma_segment_t dd_dseg; 106 int dd_dnseg; /* number of segments */ 107 bus_dma_tag_t dd_dmat; /* bus DMA tag */ 108 bus_dmamap_t dd_dmamap; /* DMA map for descriptors */ 109 void *dd_bufptr; /* associated buffers */ 110 }; 111 112 /* 113 * TX/RX ring definitions. There are 4 tx rings, one 114 * per AC, and 1 rx ring. Note carefully that transmit 115 * descriptors are treated as a contiguous chunk and the 116 * firmware pre-fetches descriptors. This means that we 117 * must preserve order when moving descriptors between 118 * the active+free lists; otherwise we may stall transmit. 119 */ 120 struct mwl_txq { 121 struct mwl_descdma dma; /* bus dma resources */ 122 struct mtx lock; /* tx q lock */ 123 char name[12]; /* e.g. "mwl0_txq4" */ 124 int qnum; /* f/w q number */ 125 int txpri; /* f/w tx priority */ 126 int nfree; /* # buffers on free list */ 127 mwl_txbufhead free; /* queue of free buffers */ 128 mwl_txbufhead active; /* queue of active buffers */ 129 }; 130 131 #define MWL_TXQ_LOCK_INIT(_sc, _tq) do { \ 132 snprintf((_tq)->name, sizeof((_tq)->name), "%s_txq%u", \ 133 device_get_nameunit((_sc)->sc_dev), (_tq)->qnum); \ 134 mtx_init(&(_tq)->lock, (_tq)->name, NULL, MTX_DEF); \ 135 } while (0) 136 #define MWL_TXQ_LOCK_DESTROY(_tq) mtx_destroy(&(_tq)->lock) 137 #define MWL_TXQ_LOCK(_tq) mtx_lock(&(_tq)->lock) 138 #define MWL_TXQ_UNLOCK(_tq) mtx_unlock(&(_tq)->lock) 139 #define MWL_TXQ_LOCK_ASSERT(_tq) mtx_assert(&(_tq)->lock, MA_OWNED) 140 141 #define MWL_TXDESC_SYNC(txq, ds, how) do { \ 142 bus_dmamap_sync((txq)->dma.dd_dmat, (txq)->dma.dd_dmamap, how); \ 143 } while(0) 144 145 /* 146 * RX dma buffers that are not in use are kept on a list. 147 */ 148 struct mwl_jumbo { 149 SLIST_ENTRY(mwl_jumbo) next; 150 }; 151 typedef SLIST_HEAD(, mwl_jumbo) mwl_jumbohead; 152 153 #define MWL_JUMBO_DATA2BUF(_data) ((struct mwl_jumbo *)(_data)) 154 #define MWL_JUMBO_BUF2DATA(_buf) ((uint8_t *)(_buf)) 155 #define MWL_JUMBO_OFFSET(_sc, _data) \ 156 (((const uint8_t *)(_data)) - (const uint8_t *)((_sc)->sc_rxmem)) 157 #define MWL_JUMBO_DMA_ADDR(_sc, _data) \ 158 ((_sc)->sc_rxmem_paddr + MWL_JUMBO_OFFSET(_sc, _data)) 159 160 struct mwl_rxbuf { 161 STAILQ_ENTRY(mwl_rxbuf) bf_list; 162 void *bf_desc; /* h/w descriptor */ 163 bus_addr_t bf_daddr; /* physical addr of desc */ 164 uint8_t *bf_data; /* rx data area */ 165 }; 166 typedef STAILQ_HEAD(, mwl_rxbuf) mwl_rxbufhead; 167 168 #define MWL_RXDESC_SYNC(sc, ds, how) do { \ 169 bus_dmamap_sync((sc)->sc_rxdma.dd_dmat, (sc)->sc_rxdma.dd_dmamap, how);\ 170 } while (0) 171 172 /* 173 * BA stream state. One of these is setup for each stream 174 * allocated/created for use. We pre-allocate the h/w stream 175 * before sending ADDBA request then complete the setup when 176 * get ADDBA response (success). The completed state is setup 177 * to optimize the fast path in mwl_txstart--we precalculate 178 * the QoS control bits in the outbound frame and use those 179 * to identify which BA stream to use (assigning the h/w q to 180 * the TxPriority field of the descriptor). 181 * 182 * NB: Each station may have at most MWL_MAXBA streams at one time. 183 */ 184 struct mwl_bastate { 185 uint16_t qos; /* QoS ctl for BA stream */ 186 uint8_t txq; /* h/w q for BA stream */ 187 const MWL_HAL_BASTREAM *bastream; /* A-MPDU BA stream */ 188 }; 189 190 static __inline__ void 191 mwl_bastream_setup(struct mwl_bastate *bas, int tid, int txq) 192 { 193 bas->txq = txq; 194 bas->qos = htole16(tid | IEEE80211_QOS_ACKPOLICY_BA); 195 } 196 197 static __inline__ void 198 mwl_bastream_free(struct mwl_bastate *bas) 199 { 200 bas->qos = 0; 201 bas->bastream = NULL; 202 /* NB: don't need to clear txq */ 203 } 204 205 /* 206 * Check the QoS control bits from an outbound frame against the 207 * value calculated when a BA stream is setup (above). We need 208 * to match the TID and also the ACK policy so we only match AMPDU 209 * frames. The bits from the frame are assumed in network byte 210 * order, hence the potential byte swap. 211 */ 212 static __inline__ int 213 mwl_bastream_match(const struct mwl_bastate *bas, uint16_t qos) 214 { 215 return (qos & htole16(IEEE80211_QOS_TID|IEEE80211_QOS_ACKPOLICY)) == 216 bas->qos; 217 } 218 219 /* driver-specific node state */ 220 struct mwl_node { 221 struct ieee80211_node mn_node; /* base class */ 222 struct mwl_ant_info mn_ai; /* antenna info */ 223 uint32_t mn_avgrssi; /* average rssi over all rx frames */ 224 uint16_t mn_staid; /* firmware station id */ 225 struct mwl_bastate mn_ba[MWL_MAXBA]; 226 struct mwl_hal_vap *mn_hvap; /* hal vap handle */ 227 }; 228 #define MWL_NODE(ni) ((struct mwl_node *)(ni)) 229 #define MWL_NODE_CONST(ni) ((const struct mwl_node *)(ni)) 230 231 /* 232 * Driver-specific vap state. 233 */ 234 struct mwl_vap { 235 struct ieee80211vap mv_vap; /* base class */ 236 struct mwl_hal_vap *mv_hvap; /* hal vap handle */ 237 struct mwl_hal_vap *mv_ap_hvap; /* ap hal vap handle for wds */ 238 uint16_t mv_last_ps_sta; /* last count of ps sta's */ 239 uint16_t mv_eapolformat; /* fixed tx rate for EAPOL */ 240 int (*mv_newstate)(struct ieee80211vap *, 241 enum ieee80211_state, int); 242 int (*mv_set_tim)(struct ieee80211_node *, int); 243 }; 244 #define MWL_VAP(vap) ((struct mwl_vap *)(vap)) 245 #define MWL_VAP_CONST(vap) ((const struct mwl_vap *)(vap)) 246 247 struct mwl_softc { 248 struct ieee80211com sc_ic; 249 struct mbufq sc_snd; 250 struct mwl_stats sc_stats; /* interface statistics */ 251 int sc_debug; 252 device_t sc_dev; 253 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 254 bus_space_handle_t sc_io0h; /* BAR 0 */ 255 bus_space_tag_t sc_io0t; 256 bus_space_handle_t sc_io1h; /* BAR 1 */ 257 bus_space_tag_t sc_io1t; 258 struct mtx sc_mtx; /* master lock (recursive) */ 259 struct taskqueue *sc_tq; /* private task queue */ 260 struct callout sc_watchdog; 261 int sc_tx_timer; 262 unsigned int sc_running : 1, 263 sc_invalid : 1, /* disable hardware accesses */ 264 sc_recvsetup:1, /* recv setup */ 265 sc_csapending:1,/* 11h channel switch pending */ 266 sc_radarena : 1,/* radar detection enabled */ 267 sc_rxblocked: 1;/* rx waiting for dma buffers */ 268 269 struct mwl_hal *sc_mh; /* h/w access layer */ 270 struct mwl_hal_vap *sc_hvap; /* hal vap handle */ 271 struct mwl_hal_hwspec sc_hwspecs; /* h/w capabilities */ 272 uint32_t sc_fwrelease; /* release # of loaded f/w */ 273 struct mwl_hal_txrxdma sc_hwdma; /* h/w dma setup */ 274 uint32_t sc_imask; /* interrupt mask copy */ 275 enum ieee80211_phymode sc_curmode; 276 u_int16_t sc_curaid; /* current association id */ 277 u_int8_t sc_curbssid[IEEE80211_ADDR_LEN]; 278 MWL_HAL_CHANNEL sc_curchan; 279 MWL_HAL_TXRATE_HANDLING sc_txratehandling; 280 u_int16_t sc_rxantenna; /* rx antenna */ 281 u_int16_t sc_txantenna; /* tx antenna */ 282 uint8_t sc_napvaps; /* # ap mode vaps */ 283 uint8_t sc_nwdsvaps; /* # wds mode vaps */ 284 uint8_t sc_nstavaps; /* # sta mode vaps */ 285 uint8_t sc_ndwdsvaps; /* # sta mode dwds vaps */ 286 uint8_t sc_nbssid0; /* # vap's using base mac */ 287 uint32_t sc_bssidmask; /* bssid mask */ 288 289 void (*sc_recv_mgmt)(struct ieee80211com *, 290 struct mbuf *, 291 struct ieee80211_node *, 292 int, int, int, u_int32_t); 293 int (*sc_newstate)(struct ieee80211com *, 294 enum ieee80211_state, int); 295 void (*sc_node_cleanup)(struct ieee80211_node *); 296 void (*sc_node_drain)(struct ieee80211_node *); 297 int (*sc_recv_action)(struct ieee80211_node *, 298 const struct ieee80211_frame *, 299 const uint8_t *, const uint8_t *); 300 int (*sc_addba_request)(struct ieee80211_node *, 301 struct ieee80211_tx_ampdu *, 302 int dialogtoken, int baparamset, 303 int batimeout); 304 int (*sc_addba_response)(struct ieee80211_node *, 305 struct ieee80211_tx_ampdu *, 306 int status, int baparamset, 307 int batimeout); 308 void (*sc_addba_stop)(struct ieee80211_node *, 309 struct ieee80211_tx_ampdu *); 310 311 struct mwl_descdma sc_rxdma; /* rx bus dma resources */ 312 mwl_rxbufhead sc_rxbuf; /* rx buffers */ 313 struct mwl_rxbuf *sc_rxnext; /* next rx buffer to process */ 314 struct task sc_rxtask; /* rx int processing */ 315 void *sc_rxmem; /* rx dma buffer pool */ 316 bus_dma_tag_t sc_rxdmat; /* rx bus DMA tag */ 317 bus_size_t sc_rxmemsize; /* rx dma buffer pool size */ 318 bus_dmamap_t sc_rxmap; /* map for rx dma buffers */ 319 bus_addr_t sc_rxmem_paddr; /* physical addr of sc_rxmem */ 320 mwl_jumbohead sc_rxfree; /* list of free dma buffers */ 321 int sc_nrxfree; /* # buffers on rx free list */ 322 struct mtx sc_rxlock; /* lock on sc_rxfree */ 323 324 struct mwl_txq sc_txq[MWL_NUM_TX_QUEUES]; 325 struct mwl_txq *sc_ac2q[5]; /* WME AC -> h/w q map */ 326 struct mbuf *sc_aggrq; /* aggregation q */ 327 struct task sc_txtask; /* tx int processing */ 328 struct task sc_bawatchdogtask;/* BA watchdog processing */ 329 330 struct task sc_radartask; /* radar detect processing */ 331 struct task sc_chanswitchtask;/* chan switch processing */ 332 333 uint8_t sc_staid[MWL_MAXSTAID/NBBY]; 334 int sc_ageinterval; 335 struct callout sc_timer; /* periodic work */ 336 337 struct mwl_tx_radiotap_header sc_tx_th; 338 struct mwl_rx_radiotap_header sc_rx_th; 339 }; 340 341 #define MWL_LOCK_INIT(_sc) \ 342 mtx_init(&(_sc)->sc_mtx, device_get_nameunit((_sc)->sc_dev), \ 343 NULL, MTX_DEF | MTX_RECURSE) 344 #define MWL_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx) 345 #define MWL_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 346 #define MWL_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 347 #define MWL_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED) 348 349 #define MWL_RXFREE_INIT(_sc) \ 350 mtx_init(&(_sc)->sc_rxlock, device_get_nameunit((_sc)->sc_dev), \ 351 NULL, MTX_DEF) 352 #define MWL_RXFREE_DESTROY(_sc) mtx_destroy(&(_sc)->sc_rxlock) 353 #define MWL_RXFREE_LOCK(_sc) mtx_lock(&(_sc)->sc_rxlock) 354 #define MWL_RXFREE_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_rxlock) 355 #define MWL_RXFREE_ASSERT(_sc) mtx_assert(&(_sc)->sc_rxlock, MA_OWNED) 356 357 int mwl_attach(u_int16_t, struct mwl_softc *); 358 int mwl_detach(struct mwl_softc *); 359 void mwl_resume(struct mwl_softc *); 360 void mwl_suspend(struct mwl_softc *); 361 void mwl_shutdown(void *); 362 void mwl_intr(void *); 363 364 #endif /* _DEV_MWL_MVVAR_H */ 365