1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2010 Alexander Motin <mav@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer, 12 * without modification, immediately at the beginning of the file. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 #include <sys/param.h> 31 #include <sys/module.h> 32 #include <sys/systm.h> 33 #include <sys/kernel.h> 34 #include <sys/bus.h> 35 #include <sys/endian.h> 36 #include <sys/malloc.h> 37 #include <sys/lock.h> 38 #include <sys/mutex.h> 39 #include <sys/sbuf.h> 40 #include <vm/uma.h> 41 #include <machine/stdarg.h> 42 #include <machine/resource.h> 43 #include <machine/bus.h> 44 #include <sys/rman.h> 45 #include <dev/pci/pcivar.h> 46 #include <dev/pci/pcireg.h> 47 #include "mvs.h" 48 49 /* local prototypes */ 50 static int mvs_setup_interrupt(device_t dev); 51 static void mvs_intr(void *data); 52 static int mvs_suspend(device_t dev); 53 static int mvs_resume(device_t dev); 54 static int mvs_ctlr_setup(device_t dev); 55 56 static struct { 57 uint32_t id; 58 uint8_t rev; 59 const char *name; 60 int ports; 61 int quirks; 62 } mvs_ids[] = { 63 {0x504011ab, 0x00, "Marvell 88SX5040", 4, MVS_Q_GENI}, 64 {0x504111ab, 0x00, "Marvell 88SX5041", 4, MVS_Q_GENI}, 65 {0x508011ab, 0x00, "Marvell 88SX5080", 8, MVS_Q_GENI}, 66 {0x508111ab, 0x00, "Marvell 88SX5081", 8, MVS_Q_GENI}, 67 {0x604011ab, 0x00, "Marvell 88SX6040", 4, MVS_Q_GENII}, 68 {0x604111ab, 0x00, "Marvell 88SX6041", 4, MVS_Q_GENII}, 69 {0x604211ab, 0x00, "Marvell 88SX6042", 4, MVS_Q_GENIIE}, 70 {0x608011ab, 0x00, "Marvell 88SX6080", 8, MVS_Q_GENII}, 71 {0x608111ab, 0x00, "Marvell 88SX6081", 8, MVS_Q_GENII}, 72 {0x704211ab, 0x00, "Marvell 88SX7042", 4, MVS_Q_GENIIE|MVS_Q_CT}, 73 {0x02419005, 0x00, "Adaptec 1420SA", 4, MVS_Q_GENII}, 74 {0x02439005, 0x00, "Adaptec 1430SA", 4, MVS_Q_GENIIE|MVS_Q_CT}, 75 {0x00000000, 0x00, NULL, 0, 0} 76 }; 77 78 static int 79 mvs_probe(device_t dev) 80 { 81 char buf[64]; 82 int i; 83 uint32_t devid = pci_get_devid(dev); 84 uint8_t revid = pci_get_revid(dev); 85 86 for (i = 0; mvs_ids[i].id != 0; i++) { 87 if (mvs_ids[i].id == devid && 88 mvs_ids[i].rev <= revid) { 89 snprintf(buf, sizeof(buf), "%s SATA controller", 90 mvs_ids[i].name); 91 device_set_desc_copy(dev, buf); 92 return (BUS_PROBE_DEFAULT); 93 } 94 } 95 return (ENXIO); 96 } 97 98 static int 99 mvs_attach(device_t dev) 100 { 101 struct mvs_controller *ctlr = device_get_softc(dev); 102 device_t child; 103 int error, unit, i; 104 uint32_t devid = pci_get_devid(dev); 105 uint8_t revid = pci_get_revid(dev); 106 107 ctlr->dev = dev; 108 i = 0; 109 while (mvs_ids[i].id != 0 && 110 (mvs_ids[i].id != devid || 111 mvs_ids[i].rev > revid)) 112 i++; 113 ctlr->channels = mvs_ids[i].ports; 114 ctlr->quirks = mvs_ids[i].quirks; 115 ctlr->ccc = 0; 116 resource_int_value(device_get_name(dev), 117 device_get_unit(dev), "ccc", &ctlr->ccc); 118 ctlr->cccc = 8; 119 resource_int_value(device_get_name(dev), 120 device_get_unit(dev), "cccc", &ctlr->cccc); 121 if (ctlr->ccc == 0 || ctlr->cccc == 0) { 122 ctlr->ccc = 0; 123 ctlr->cccc = 0; 124 } 125 if (ctlr->ccc > 100000) 126 ctlr->ccc = 100000; 127 device_printf(dev, 128 "Gen-%s, %d %sGbps ports, Port Multiplier %s%s\n", 129 ((ctlr->quirks & MVS_Q_GENI) ? "I" : 130 ((ctlr->quirks & MVS_Q_GENII) ? "II" : "IIe")), 131 ctlr->channels, 132 ((ctlr->quirks & MVS_Q_GENI) ? "1.5" : "3"), 133 ((ctlr->quirks & MVS_Q_GENI) ? 134 "not supported" : "supported"), 135 ((ctlr->quirks & MVS_Q_GENIIE) ? 136 " with FBS" : "")); 137 mtx_init(&ctlr->mtx, "MVS controller lock", NULL, MTX_DEF); 138 /* We should have a memory BAR(0). */ 139 ctlr->r_rid = PCIR_BAR(0); 140 if (!(ctlr->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 141 &ctlr->r_rid, RF_ACTIVE))) 142 return ENXIO; 143 /* Setup our own memory management for channels. */ 144 ctlr->sc_iomem.rm_start = rman_get_start(ctlr->r_mem); 145 ctlr->sc_iomem.rm_end = rman_get_end(ctlr->r_mem); 146 ctlr->sc_iomem.rm_type = RMAN_ARRAY; 147 ctlr->sc_iomem.rm_descr = "I/O memory addresses"; 148 if ((error = rman_init(&ctlr->sc_iomem)) != 0) { 149 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 150 return (error); 151 } 152 if ((error = rman_manage_region(&ctlr->sc_iomem, 153 rman_get_start(ctlr->r_mem), rman_get_end(ctlr->r_mem))) != 0) { 154 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 155 rman_fini(&ctlr->sc_iomem); 156 return (error); 157 } 158 pci_enable_busmaster(dev); 159 mvs_ctlr_setup(dev); 160 /* Setup interrupts. */ 161 if (mvs_setup_interrupt(dev)) { 162 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 163 rman_fini(&ctlr->sc_iomem); 164 return ENXIO; 165 } 166 /* Attach all channels on this controller */ 167 for (unit = 0; unit < ctlr->channels; unit++) { 168 child = device_add_child(dev, "mvsch", -1); 169 if (child == NULL) 170 device_printf(dev, "failed to add channel device\n"); 171 else 172 device_set_ivars(child, (void *)(intptr_t)unit); 173 } 174 bus_generic_attach(dev); 175 return 0; 176 } 177 178 static int 179 mvs_detach(device_t dev) 180 { 181 struct mvs_controller *ctlr = device_get_softc(dev); 182 183 /* Detach & delete all children */ 184 device_delete_children(dev); 185 186 /* Free interrupt. */ 187 if (ctlr->irq.r_irq) { 188 bus_teardown_intr(dev, ctlr->irq.r_irq, 189 ctlr->irq.handle); 190 bus_release_resource(dev, SYS_RES_IRQ, 191 ctlr->irq.r_irq_rid, ctlr->irq.r_irq); 192 } 193 pci_release_msi(dev); 194 /* Free memory. */ 195 rman_fini(&ctlr->sc_iomem); 196 if (ctlr->r_mem) 197 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem); 198 mtx_destroy(&ctlr->mtx); 199 return (0); 200 } 201 202 static int 203 mvs_ctlr_setup(device_t dev) 204 { 205 struct mvs_controller *ctlr = device_get_softc(dev); 206 int i, ccc = ctlr->ccc, cccc = ctlr->cccc, ccim = 0; 207 208 /* Mask chip interrupts */ 209 ATA_OUTL(ctlr->r_mem, CHIP_MIM, 0x00000000); 210 /* Mask PCI interrupts */ 211 ATA_OUTL(ctlr->r_mem, CHIP_PCIIM, 0x00000000); 212 /* Clear PCI interrupts */ 213 ATA_OUTL(ctlr->r_mem, CHIP_PCIIC, 0x00000000); 214 if (ccc && bootverbose) { 215 device_printf(dev, 216 "CCC with %dus/%dcmd enabled\n", 217 ctlr->ccc, ctlr->cccc); 218 } 219 ccc *= 150; 220 /* Configure chip-global CCC */ 221 if (ctlr->channels > 4 && (ctlr->quirks & MVS_Q_GENI) == 0) { 222 ATA_OUTL(ctlr->r_mem, CHIP_ICT, cccc); 223 ATA_OUTL(ctlr->r_mem, CHIP_ITT, ccc); 224 ATA_OUTL(ctlr->r_mem, CHIP_ICC, ~CHIP_ICC_ALL_PORTS); 225 if (ccc) 226 ccim |= IC_ALL_PORTS_COAL_DONE; 227 ccc = 0; 228 cccc = 0; 229 } 230 for (i = 0; i < ctlr->channels / 4; i++) { 231 /* Configure per-HC CCC */ 232 ATA_OUTL(ctlr->r_mem, HC_BASE(i) + HC_ICT, cccc); 233 ATA_OUTL(ctlr->r_mem, HC_BASE(i) + HC_ITT, ccc); 234 if (ccc) 235 ccim |= (IC_HC0_COAL_DONE << (i * IC_HC_SHIFT)); 236 /* Clear HC interrupts */ 237 ATA_OUTL(ctlr->r_mem, HC_BASE(i) + HC_IC, 0x00000000); 238 } 239 /* Enable chip interrupts */ 240 ctlr->gmim = (ccim ? ccim : (IC_DONE_HC0 | IC_DONE_HC1)) | 241 IC_ERR_HC0 | IC_ERR_HC1; 242 ctlr->mim = ctlr->gmim | ctlr->pmim; 243 ATA_OUTL(ctlr->r_mem, CHIP_MIM, ctlr->mim); 244 /* Enable PCI interrupts */ 245 ATA_OUTL(ctlr->r_mem, CHIP_PCIIM, 0x007fffff); 246 return (0); 247 } 248 249 static void 250 mvs_edma(device_t dev, device_t child, int mode) 251 { 252 struct mvs_controller *ctlr = device_get_softc(dev); 253 int unit = ((struct mvs_channel *)device_get_softc(child))->unit; 254 int bit = IC_DONE_IRQ << (unit * 2 + unit / 4) ; 255 256 if (ctlr->ccc == 0) 257 return; 258 /* CCC is not working for non-EDMA mode. Unmask device interrupts. */ 259 mtx_lock(&ctlr->mtx); 260 if (mode == MVS_EDMA_OFF) 261 ctlr->pmim |= bit; 262 else 263 ctlr->pmim &= ~bit; 264 ctlr->mim = ctlr->gmim | ctlr->pmim; 265 if (!ctlr->msia) 266 ATA_OUTL(ctlr->r_mem, CHIP_MIM, ctlr->mim); 267 mtx_unlock(&ctlr->mtx); 268 } 269 270 static int 271 mvs_suspend(device_t dev) 272 { 273 struct mvs_controller *ctlr = device_get_softc(dev); 274 275 bus_generic_suspend(dev); 276 /* Mask chip interrupts */ 277 ATA_OUTL(ctlr->r_mem, CHIP_MIM, 0x00000000); 278 /* Mask PCI interrupts */ 279 ATA_OUTL(ctlr->r_mem, CHIP_PCIIM, 0x00000000); 280 return 0; 281 } 282 283 static int 284 mvs_resume(device_t dev) 285 { 286 287 mvs_ctlr_setup(dev); 288 return (bus_generic_resume(dev)); 289 } 290 291 static int 292 mvs_setup_interrupt(device_t dev) 293 { 294 struct mvs_controller *ctlr = device_get_softc(dev); 295 int msi = 0; 296 297 /* Process hints. */ 298 resource_int_value(device_get_name(dev), 299 device_get_unit(dev), "msi", &msi); 300 if (msi < 0) 301 msi = 0; 302 else if (msi > 0) 303 msi = min(1, pci_msi_count(dev)); 304 /* Allocate MSI if needed/present. */ 305 if (msi && pci_alloc_msi(dev, &msi) != 0) 306 msi = 0; 307 ctlr->msi = msi; 308 /* Allocate all IRQs. */ 309 ctlr->irq.r_irq_rid = msi ? 1 : 0; 310 if (!(ctlr->irq.r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 311 &ctlr->irq.r_irq_rid, RF_SHAREABLE | RF_ACTIVE))) { 312 device_printf(dev, "unable to map interrupt\n"); 313 return (ENXIO); 314 } 315 if ((bus_setup_intr(dev, ctlr->irq.r_irq, ATA_INTR_FLAGS, NULL, 316 mvs_intr, ctlr, &ctlr->irq.handle))) { 317 device_printf(dev, "unable to setup interrupt\n"); 318 bus_release_resource(dev, SYS_RES_IRQ, 319 ctlr->irq.r_irq_rid, ctlr->irq.r_irq); 320 ctlr->irq.r_irq = NULL; 321 return (ENXIO); 322 } 323 return (0); 324 } 325 326 /* 327 * Common case interrupt handler. 328 */ 329 static void 330 mvs_intr(void *data) 331 { 332 struct mvs_controller *ctlr = data; 333 struct mvs_intr_arg arg; 334 void (*function)(void *); 335 int p; 336 u_int32_t ic, aic; 337 338 ic = ATA_INL(ctlr->r_mem, CHIP_MIC); 339 if (ctlr->msi) { 340 /* We have to mask MSI during processing. */ 341 mtx_lock(&ctlr->mtx); 342 ATA_OUTL(ctlr->r_mem, CHIP_MIM, 0); 343 ctlr->msia = 1; /* Deny MIM update during processing. */ 344 mtx_unlock(&ctlr->mtx); 345 } else if (ic == 0) 346 return; 347 /* Acknowledge all-ports CCC interrupt. */ 348 if (ic & IC_ALL_PORTS_COAL_DONE) 349 ATA_OUTL(ctlr->r_mem, CHIP_ICC, ~CHIP_ICC_ALL_PORTS); 350 for (p = 0; p < ctlr->channels; p++) { 351 if ((p & 3) == 0) { 352 if (p != 0) 353 ic >>= 1; 354 if ((ic & IC_HC0) == 0) { 355 p += 3; 356 ic >>= 8; 357 continue; 358 } 359 /* Acknowledge interrupts of this HC. */ 360 aic = 0; 361 if (ic & (IC_DONE_IRQ << 0)) 362 aic |= HC_IC_DONE(0) | HC_IC_DEV(0); 363 if (ic & (IC_DONE_IRQ << 2)) 364 aic |= HC_IC_DONE(1) | HC_IC_DEV(1); 365 if (ic & (IC_DONE_IRQ << 4)) 366 aic |= HC_IC_DONE(2) | HC_IC_DEV(2); 367 if (ic & (IC_DONE_IRQ << 6)) 368 aic |= HC_IC_DONE(3) | HC_IC_DEV(3); 369 if (ic & IC_HC0_COAL_DONE) 370 aic |= HC_IC_COAL; 371 ATA_OUTL(ctlr->r_mem, HC_BASE(p == 4) + HC_IC, ~aic); 372 } 373 /* Call per-port interrupt handler. */ 374 arg.cause = ic & (IC_ERR_IRQ|IC_DONE_IRQ); 375 if ((arg.cause != 0) && 376 (function = ctlr->interrupt[p].function)) { 377 arg.arg = ctlr->interrupt[p].argument; 378 function(&arg); 379 } 380 ic >>= 2; 381 } 382 if (ctlr->msi) { 383 /* Unmasking MSI triggers next interrupt, if needed. */ 384 mtx_lock(&ctlr->mtx); 385 ctlr->msia = 0; /* Allow MIM update. */ 386 ATA_OUTL(ctlr->r_mem, CHIP_MIM, ctlr->mim); 387 mtx_unlock(&ctlr->mtx); 388 } 389 } 390 391 static struct resource * 392 mvs_alloc_resource(device_t dev, device_t child, int type, int *rid, 393 rman_res_t start, rman_res_t end, rman_res_t count, 394 u_int flags) 395 { 396 struct mvs_controller *ctlr = device_get_softc(dev); 397 int unit = ((struct mvs_channel *)device_get_softc(child))->unit; 398 struct resource *res = NULL; 399 int offset = HC_BASE(unit >> 2) + PORT_BASE(unit & 0x03); 400 rman_res_t st; 401 402 switch (type) { 403 case SYS_RES_MEMORY: 404 st = rman_get_start(ctlr->r_mem); 405 res = rman_reserve_resource(&ctlr->sc_iomem, st + offset, 406 st + offset + PORT_SIZE - 1, PORT_SIZE, RF_ACTIVE, child); 407 if (res) { 408 bus_space_handle_t bsh; 409 bus_space_tag_t bst; 410 bsh = rman_get_bushandle(ctlr->r_mem); 411 bst = rman_get_bustag(ctlr->r_mem); 412 bus_space_subregion(bst, bsh, offset, PORT_SIZE, &bsh); 413 rman_set_bushandle(res, bsh); 414 rman_set_bustag(res, bst); 415 } 416 break; 417 case SYS_RES_IRQ: 418 if (*rid == ATA_IRQ_RID) 419 res = ctlr->irq.r_irq; 420 break; 421 } 422 return (res); 423 } 424 425 static int 426 mvs_release_resource(device_t dev, device_t child, int type, int rid, 427 struct resource *r) 428 { 429 430 switch (type) { 431 case SYS_RES_MEMORY: 432 rman_release_resource(r); 433 return (0); 434 case SYS_RES_IRQ: 435 if (rid != ATA_IRQ_RID) 436 return ENOENT; 437 return (0); 438 } 439 return (EINVAL); 440 } 441 442 static int 443 mvs_setup_intr(device_t dev, device_t child, struct resource *irq, 444 int flags, driver_filter_t *filter, driver_intr_t *function, 445 void *argument, void **cookiep) 446 { 447 struct mvs_controller *ctlr = device_get_softc(dev); 448 int unit = (intptr_t)device_get_ivars(child); 449 450 if (filter != NULL) { 451 printf("mvs.c: we cannot use a filter here\n"); 452 return (EINVAL); 453 } 454 ctlr->interrupt[unit].function = function; 455 ctlr->interrupt[unit].argument = argument; 456 return (0); 457 } 458 459 static int 460 mvs_teardown_intr(device_t dev, device_t child, struct resource *irq, 461 void *cookie) 462 { 463 struct mvs_controller *ctlr = device_get_softc(dev); 464 int unit = (intptr_t)device_get_ivars(child); 465 466 ctlr->interrupt[unit].function = NULL; 467 ctlr->interrupt[unit].argument = NULL; 468 return (0); 469 } 470 471 static int 472 mvs_print_child(device_t dev, device_t child) 473 { 474 int retval; 475 476 retval = bus_print_child_header(dev, child); 477 retval += printf(" at channel %d", 478 (int)(intptr_t)device_get_ivars(child)); 479 retval += bus_print_child_footer(dev, child); 480 481 return (retval); 482 } 483 484 static int 485 mvs_child_location(device_t dev, device_t child, struct sbuf *sb) 486 { 487 488 sbuf_printf(sb, "channel=%d", 489 (int)(intptr_t)device_get_ivars(child)); 490 return (0); 491 } 492 493 static bus_dma_tag_t 494 mvs_get_dma_tag(device_t bus, device_t child) 495 { 496 497 return (bus_get_dma_tag(bus)); 498 } 499 500 static device_method_t mvs_methods[] = { 501 DEVMETHOD(device_probe, mvs_probe), 502 DEVMETHOD(device_attach, mvs_attach), 503 DEVMETHOD(device_detach, mvs_detach), 504 DEVMETHOD(device_suspend, mvs_suspend), 505 DEVMETHOD(device_resume, mvs_resume), 506 DEVMETHOD(bus_print_child, mvs_print_child), 507 DEVMETHOD(bus_alloc_resource, mvs_alloc_resource), 508 DEVMETHOD(bus_release_resource, mvs_release_resource), 509 DEVMETHOD(bus_setup_intr, mvs_setup_intr), 510 DEVMETHOD(bus_teardown_intr,mvs_teardown_intr), 511 DEVMETHOD(bus_child_location, mvs_child_location), 512 DEVMETHOD(bus_get_dma_tag, mvs_get_dma_tag), 513 DEVMETHOD(mvs_edma, mvs_edma), 514 { 0, 0 } 515 }; 516 static driver_t mvs_driver = { 517 "mvs", 518 mvs_methods, 519 sizeof(struct mvs_controller) 520 }; 521 DRIVER_MODULE(mvs, pci, mvs_driver, 0, 0); 522 MODULE_PNP_INFO("W32:vendor/device", pci, mvs, mvs_ids, 523 nitems(mvs_ids) - 1); 524 MODULE_VERSION(mvs, 1); 525 MODULE_DEPEND(mvs, cam, 1, 1, 1); 526