xref: /freebsd/sys/dev/mvs/mvs_pci.c (revision 6580f5c38dd5b01aeeaed16b370f1a12423437f0)
1 /*-
2  * SPDX-License-Identifier: BSD-2-Clause
3  *
4  * Copyright (c) 2010 Alexander Motin <mav@FreeBSD.org>
5  * All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  * 1. Redistributions of source code must retain the above copyright
11  *    notice, this list of conditions and the following disclaimer,
12  *    without modification, immediately at the beginning of the file.
13  * 2. Redistributions in binary form must reproduce the above copyright
14  *    notice, this list of conditions and the following disclaimer in the
15  *    documentation and/or other materials provided with the distribution.
16  *
17  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27  */
28 
29 #include <sys/param.h>
30 #include <sys/module.h>
31 #include <sys/systm.h>
32 #include <sys/kernel.h>
33 #include <sys/bus.h>
34 #include <sys/endian.h>
35 #include <sys/malloc.h>
36 #include <sys/lock.h>
37 #include <sys/mutex.h>
38 #include <sys/sbuf.h>
39 #include <vm/uma.h>
40 #include <machine/stdarg.h>
41 #include <machine/resource.h>
42 #include <machine/bus.h>
43 #include <sys/rman.h>
44 #include <dev/pci/pcivar.h>
45 #include <dev/pci/pcireg.h>
46 #include "mvs.h"
47 
48 /* local prototypes */
49 static int mvs_setup_interrupt(device_t dev);
50 static void mvs_intr(void *data);
51 static int mvs_suspend(device_t dev);
52 static int mvs_resume(device_t dev);
53 static int mvs_ctlr_setup(device_t dev);
54 
55 static struct {
56 	uint32_t	id;
57 	uint8_t		rev;
58 	const char	*name;
59 	int		ports;
60 	int		quirks;
61 } mvs_ids[] = {
62 	{0x504011ab, 0x00, "Marvell 88SX5040",	4,	MVS_Q_GENI},
63 	{0x504111ab, 0x00, "Marvell 88SX5041",	4,	MVS_Q_GENI},
64 	{0x508011ab, 0x00, "Marvell 88SX5080",	8,	MVS_Q_GENI},
65 	{0x508111ab, 0x00, "Marvell 88SX5081",	8,	MVS_Q_GENI},
66 	{0x604011ab, 0x00, "Marvell 88SX6040",	4,	MVS_Q_GENII},
67 	{0x604111ab, 0x00, "Marvell 88SX6041",	4,	MVS_Q_GENII},
68 	{0x604211ab, 0x00, "Marvell 88SX6042",	4,	MVS_Q_GENIIE},
69 	{0x608011ab, 0x00, "Marvell 88SX6080",	8,	MVS_Q_GENII},
70 	{0x608111ab, 0x00, "Marvell 88SX6081",	8,	MVS_Q_GENII},
71 	{0x704211ab, 0x00, "Marvell 88SX7042",	4,	MVS_Q_GENIIE|MVS_Q_CT},
72 	{0x02419005, 0x00, "Adaptec 1420SA",	4,	MVS_Q_GENII},
73 	{0x02439005, 0x00, "Adaptec 1430SA",	4,	MVS_Q_GENIIE|MVS_Q_CT},
74 	{0x00000000, 0x00, NULL,	0,	0}
75 };
76 
77 static int
78 mvs_probe(device_t dev)
79 {
80 	char buf[64];
81 	int i;
82 	uint32_t devid = pci_get_devid(dev);
83 	uint8_t revid = pci_get_revid(dev);
84 
85 	for (i = 0; mvs_ids[i].id != 0; i++) {
86 		if (mvs_ids[i].id == devid &&
87 		    mvs_ids[i].rev <= revid) {
88 			snprintf(buf, sizeof(buf), "%s SATA controller",
89 			    mvs_ids[i].name);
90 			device_set_desc_copy(dev, buf);
91 			return (BUS_PROBE_DEFAULT);
92 		}
93 	}
94 	return (ENXIO);
95 }
96 
97 static int
98 mvs_attach(device_t dev)
99 {
100 	struct mvs_controller *ctlr = device_get_softc(dev);
101 	device_t child;
102 	int	error, unit, i;
103 	uint32_t devid = pci_get_devid(dev);
104 	uint8_t revid = pci_get_revid(dev);
105 
106 	ctlr->dev = dev;
107 	i = 0;
108 	while (mvs_ids[i].id != 0 &&
109 	    (mvs_ids[i].id != devid ||
110 	     mvs_ids[i].rev > revid))
111 		i++;
112 	ctlr->channels = mvs_ids[i].ports;
113 	ctlr->quirks = mvs_ids[i].quirks;
114 	ctlr->ccc = 0;
115 	resource_int_value(device_get_name(dev),
116 	    device_get_unit(dev), "ccc", &ctlr->ccc);
117 	ctlr->cccc = 8;
118 	resource_int_value(device_get_name(dev),
119 	    device_get_unit(dev), "cccc", &ctlr->cccc);
120 	if (ctlr->ccc == 0 || ctlr->cccc == 0) {
121 		ctlr->ccc = 0;
122 		ctlr->cccc = 0;
123 	}
124 	if (ctlr->ccc > 100000)
125 		ctlr->ccc = 100000;
126 	device_printf(dev,
127 	    "Gen-%s, %d %sGbps ports, Port Multiplier %s%s\n",
128 	    ((ctlr->quirks & MVS_Q_GENI) ? "I" :
129 	     ((ctlr->quirks & MVS_Q_GENII) ? "II" : "IIe")),
130 	    ctlr->channels,
131 	    ((ctlr->quirks & MVS_Q_GENI) ? "1.5" : "3"),
132 	    ((ctlr->quirks & MVS_Q_GENI) ?
133 	    "not supported" : "supported"),
134 	    ((ctlr->quirks & MVS_Q_GENIIE) ?
135 	    " with FBS" : ""));
136 	mtx_init(&ctlr->mtx, "MVS controller lock", NULL, MTX_DEF);
137 	/* We should have a memory BAR(0). */
138 	ctlr->r_rid = PCIR_BAR(0);
139 	if (!(ctlr->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
140 	    &ctlr->r_rid, RF_ACTIVE)))
141 		return ENXIO;
142 	/* Setup our own memory management for channels. */
143 	ctlr->sc_iomem.rm_start = rman_get_start(ctlr->r_mem);
144 	ctlr->sc_iomem.rm_end = rman_get_end(ctlr->r_mem);
145 	ctlr->sc_iomem.rm_type = RMAN_ARRAY;
146 	ctlr->sc_iomem.rm_descr = "I/O memory addresses";
147 	if ((error = rman_init(&ctlr->sc_iomem)) != 0) {
148 		bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem);
149 		return (error);
150 	}
151 	if ((error = rman_manage_region(&ctlr->sc_iomem,
152 	    rman_get_start(ctlr->r_mem), rman_get_end(ctlr->r_mem))) != 0) {
153 		bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem);
154 		rman_fini(&ctlr->sc_iomem);
155 		return (error);
156 	}
157 	pci_enable_busmaster(dev);
158 	mvs_ctlr_setup(dev);
159 	/* Setup interrupts. */
160 	if (mvs_setup_interrupt(dev)) {
161 		bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem);
162 		rman_fini(&ctlr->sc_iomem);
163 		return ENXIO;
164 	}
165 	/* Attach all channels on this controller */
166 	for (unit = 0; unit < ctlr->channels; unit++) {
167 		child = device_add_child(dev, "mvsch", -1);
168 		if (child == NULL)
169 			device_printf(dev, "failed to add channel device\n");
170 		else
171 			device_set_ivars(child, (void *)(intptr_t)unit);
172 	}
173 	bus_generic_attach(dev);
174 	return 0;
175 }
176 
177 static int
178 mvs_detach(device_t dev)
179 {
180 	struct mvs_controller *ctlr = device_get_softc(dev);
181 
182 	/* Detach & delete all children */
183 	device_delete_children(dev);
184 
185 	/* Free interrupt. */
186 	if (ctlr->irq.r_irq) {
187 		bus_teardown_intr(dev, ctlr->irq.r_irq,
188 		    ctlr->irq.handle);
189 		bus_release_resource(dev, SYS_RES_IRQ,
190 		    ctlr->irq.r_irq_rid, ctlr->irq.r_irq);
191 	}
192 	pci_release_msi(dev);
193 	/* Free memory. */
194 	rman_fini(&ctlr->sc_iomem);
195 	if (ctlr->r_mem)
196 		bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem);
197 	mtx_destroy(&ctlr->mtx);
198 	return (0);
199 }
200 
201 static int
202 mvs_ctlr_setup(device_t dev)
203 {
204 	struct mvs_controller *ctlr = device_get_softc(dev);
205 	int i, ccc = ctlr->ccc, cccc = ctlr->cccc, ccim = 0;
206 
207 	/* Mask chip interrupts */
208 	ATA_OUTL(ctlr->r_mem, CHIP_MIM, 0x00000000);
209 	/* Mask PCI interrupts */
210 	ATA_OUTL(ctlr->r_mem, CHIP_PCIIM, 0x00000000);
211 	/* Clear PCI interrupts */
212 	ATA_OUTL(ctlr->r_mem, CHIP_PCIIC, 0x00000000);
213 	if (ccc && bootverbose) {
214 		device_printf(dev,
215 		    "CCC with %dus/%dcmd enabled\n",
216 		    ctlr->ccc, ctlr->cccc);
217 	}
218 	ccc *= 150;
219 	/* Configure chip-global CCC */
220 	if (ctlr->channels > 4 && (ctlr->quirks & MVS_Q_GENI) == 0) {
221 		ATA_OUTL(ctlr->r_mem, CHIP_ICT, cccc);
222 		ATA_OUTL(ctlr->r_mem, CHIP_ITT, ccc);
223 		ATA_OUTL(ctlr->r_mem, CHIP_ICC, ~CHIP_ICC_ALL_PORTS);
224 		if (ccc)
225 			ccim |= IC_ALL_PORTS_COAL_DONE;
226 		ccc = 0;
227 		cccc = 0;
228 	}
229 	for (i = 0; i < ctlr->channels / 4; i++) {
230 		/* Configure per-HC CCC */
231 		ATA_OUTL(ctlr->r_mem, HC_BASE(i) + HC_ICT, cccc);
232 		ATA_OUTL(ctlr->r_mem, HC_BASE(i) + HC_ITT, ccc);
233 		if (ccc)
234 			ccim |= (IC_HC0_COAL_DONE << (i * IC_HC_SHIFT));
235 		/* Clear HC interrupts */
236 		ATA_OUTL(ctlr->r_mem, HC_BASE(i) + HC_IC, 0x00000000);
237 	}
238 	/* Enable chip interrupts */
239 	ctlr->gmim = (ccim ? ccim : (IC_DONE_HC0 | IC_DONE_HC1)) |
240 	     IC_ERR_HC0 | IC_ERR_HC1;
241 	ctlr->mim = ctlr->gmim | ctlr->pmim;
242 	ATA_OUTL(ctlr->r_mem, CHIP_MIM, ctlr->mim);
243 	/* Enable PCI interrupts */
244 	ATA_OUTL(ctlr->r_mem, CHIP_PCIIM, 0x007fffff);
245 	return (0);
246 }
247 
248 static void
249 mvs_edma(device_t dev, device_t child, int mode)
250 {
251 	struct mvs_controller *ctlr = device_get_softc(dev);
252 	int unit = ((struct mvs_channel *)device_get_softc(child))->unit;
253 	int bit = IC_DONE_IRQ << (unit * 2 + unit / 4) ;
254 
255 	if (ctlr->ccc == 0)
256 		return;
257 	/* CCC is not working for non-EDMA mode. Unmask device interrupts. */
258 	mtx_lock(&ctlr->mtx);
259 	if (mode == MVS_EDMA_OFF)
260 		ctlr->pmim |= bit;
261 	else
262 		ctlr->pmim &= ~bit;
263 	ctlr->mim = ctlr->gmim | ctlr->pmim;
264 	if (!ctlr->msia)
265 		ATA_OUTL(ctlr->r_mem, CHIP_MIM, ctlr->mim);
266 	mtx_unlock(&ctlr->mtx);
267 }
268 
269 static int
270 mvs_suspend(device_t dev)
271 {
272 	struct mvs_controller *ctlr = device_get_softc(dev);
273 
274 	bus_generic_suspend(dev);
275 	/* Mask chip interrupts */
276 	ATA_OUTL(ctlr->r_mem, CHIP_MIM, 0x00000000);
277 	/* Mask PCI interrupts */
278 	ATA_OUTL(ctlr->r_mem, CHIP_PCIIM, 0x00000000);
279 	return 0;
280 }
281 
282 static int
283 mvs_resume(device_t dev)
284 {
285 
286 	mvs_ctlr_setup(dev);
287 	return (bus_generic_resume(dev));
288 }
289 
290 static int
291 mvs_setup_interrupt(device_t dev)
292 {
293 	struct mvs_controller *ctlr = device_get_softc(dev);
294 	int msi = 0;
295 
296 	/* Process hints. */
297 	resource_int_value(device_get_name(dev),
298 	    device_get_unit(dev), "msi", &msi);
299 	if (msi < 0)
300 		msi = 0;
301 	else if (msi > 0)
302 		msi = min(1, pci_msi_count(dev));
303 	/* Allocate MSI if needed/present. */
304 	if (msi && pci_alloc_msi(dev, &msi) != 0)
305 		msi = 0;
306 	ctlr->msi = msi;
307 	/* Allocate all IRQs. */
308 	ctlr->irq.r_irq_rid = msi ? 1 : 0;
309 	if (!(ctlr->irq.r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
310 	    &ctlr->irq.r_irq_rid, RF_SHAREABLE | RF_ACTIVE))) {
311 		device_printf(dev, "unable to map interrupt\n");
312 		return (ENXIO);
313 	}
314 	if ((bus_setup_intr(dev, ctlr->irq.r_irq, ATA_INTR_FLAGS, NULL,
315 	    mvs_intr, ctlr, &ctlr->irq.handle))) {
316 		device_printf(dev, "unable to setup interrupt\n");
317 		bus_release_resource(dev, SYS_RES_IRQ,
318 		    ctlr->irq.r_irq_rid, ctlr->irq.r_irq);
319 		ctlr->irq.r_irq = NULL;
320 		return (ENXIO);
321 	}
322 	return (0);
323 }
324 
325 /*
326  * Common case interrupt handler.
327  */
328 static void
329 mvs_intr(void *data)
330 {
331 	struct mvs_controller *ctlr = data;
332 	struct mvs_intr_arg arg;
333 	void (*function)(void *);
334 	int p;
335 	u_int32_t ic, aic;
336 
337 	ic = ATA_INL(ctlr->r_mem, CHIP_MIC);
338 	if (ctlr->msi) {
339 		/* We have to mask MSI during processing. */
340 		mtx_lock(&ctlr->mtx);
341 		ATA_OUTL(ctlr->r_mem, CHIP_MIM, 0);
342 		ctlr->msia = 1; /* Deny MIM update during processing. */
343 		mtx_unlock(&ctlr->mtx);
344 	} else if (ic == 0)
345 		return;
346 	/* Acknowledge all-ports CCC interrupt. */
347 	if (ic & IC_ALL_PORTS_COAL_DONE)
348 		ATA_OUTL(ctlr->r_mem, CHIP_ICC, ~CHIP_ICC_ALL_PORTS);
349 	for (p = 0; p < ctlr->channels; p++) {
350 		if ((p & 3) == 0) {
351 			if (p != 0)
352 				ic >>= 1;
353 			if ((ic & IC_HC0) == 0) {
354 				p += 3;
355 				ic >>= 8;
356 				continue;
357 			}
358 			/* Acknowledge interrupts of this HC. */
359 			aic = 0;
360 			if (ic & (IC_DONE_IRQ << 0))
361 				aic |= HC_IC_DONE(0) | HC_IC_DEV(0);
362 			if (ic & (IC_DONE_IRQ << 2))
363 				aic |= HC_IC_DONE(1) | HC_IC_DEV(1);
364 			if (ic & (IC_DONE_IRQ << 4))
365 				aic |= HC_IC_DONE(2) | HC_IC_DEV(2);
366 			if (ic & (IC_DONE_IRQ << 6))
367 				aic |= HC_IC_DONE(3) | HC_IC_DEV(3);
368 			if (ic & IC_HC0_COAL_DONE)
369 				aic |= HC_IC_COAL;
370 			ATA_OUTL(ctlr->r_mem, HC_BASE(p == 4) + HC_IC, ~aic);
371 		}
372 		/* Call per-port interrupt handler. */
373 		arg.cause = ic & (IC_ERR_IRQ|IC_DONE_IRQ);
374 		if ((arg.cause != 0) &&
375 		    (function = ctlr->interrupt[p].function)) {
376 			arg.arg = ctlr->interrupt[p].argument;
377 			function(&arg);
378 		}
379 		ic >>= 2;
380 	}
381 	if (ctlr->msi) {
382 		/* Unmasking MSI triggers next interrupt, if needed. */
383 		mtx_lock(&ctlr->mtx);
384 		ctlr->msia = 0;	/* Allow MIM update. */
385 		ATA_OUTL(ctlr->r_mem, CHIP_MIM, ctlr->mim);
386 		mtx_unlock(&ctlr->mtx);
387 	}
388 }
389 
390 static struct resource *
391 mvs_alloc_resource(device_t dev, device_t child, int type, int *rid,
392 		       rman_res_t start, rman_res_t end, rman_res_t count,
393 		       u_int flags)
394 {
395 	struct mvs_controller *ctlr = device_get_softc(dev);
396 	int unit = ((struct mvs_channel *)device_get_softc(child))->unit;
397 	struct resource *res = NULL;
398 	int offset = HC_BASE(unit >> 2) + PORT_BASE(unit & 0x03);
399 	rman_res_t st;
400 
401 	switch (type) {
402 	case SYS_RES_MEMORY:
403 		st = rman_get_start(ctlr->r_mem);
404 		res = rman_reserve_resource(&ctlr->sc_iomem, st + offset,
405 		    st + offset + PORT_SIZE - 1, PORT_SIZE, RF_ACTIVE, child);
406 		if (res) {
407 			bus_space_handle_t bsh;
408 			bus_space_tag_t bst;
409 			bsh = rman_get_bushandle(ctlr->r_mem);
410 			bst = rman_get_bustag(ctlr->r_mem);
411 			bus_space_subregion(bst, bsh, offset, PORT_SIZE, &bsh);
412 			rman_set_bushandle(res, bsh);
413 			rman_set_bustag(res, bst);
414 		}
415 		break;
416 	case SYS_RES_IRQ:
417 		if (*rid == ATA_IRQ_RID)
418 			res = ctlr->irq.r_irq;
419 		break;
420 	}
421 	return (res);
422 }
423 
424 static int
425 mvs_release_resource(device_t dev, device_t child, struct resource *r)
426 {
427 
428 	switch (rman_get_type(r)) {
429 	case SYS_RES_MEMORY:
430 		rman_release_resource(r);
431 		return (0);
432 	case SYS_RES_IRQ:
433 		if (rman_get_rid(r) != ATA_IRQ_RID)
434 			return ENOENT;
435 		return (0);
436 	}
437 	return (EINVAL);
438 }
439 
440 static int
441 mvs_setup_intr(device_t dev, device_t child, struct resource *irq,
442 		   int flags, driver_filter_t *filter, driver_intr_t *function,
443 		   void *argument, void **cookiep)
444 {
445 	struct mvs_controller *ctlr = device_get_softc(dev);
446 	int unit = (intptr_t)device_get_ivars(child);
447 
448 	if (filter != NULL) {
449 		printf("mvs.c: we cannot use a filter here\n");
450 		return (EINVAL);
451 	}
452 	ctlr->interrupt[unit].function = function;
453 	ctlr->interrupt[unit].argument = argument;
454 	return (0);
455 }
456 
457 static int
458 mvs_teardown_intr(device_t dev, device_t child, struct resource *irq,
459 		      void *cookie)
460 {
461 	struct mvs_controller *ctlr = device_get_softc(dev);
462 	int unit = (intptr_t)device_get_ivars(child);
463 
464 	ctlr->interrupt[unit].function = NULL;
465 	ctlr->interrupt[unit].argument = NULL;
466 	return (0);
467 }
468 
469 static int
470 mvs_print_child(device_t dev, device_t child)
471 {
472 	int retval;
473 
474 	retval = bus_print_child_header(dev, child);
475 	retval += printf(" at channel %d",
476 	    (int)(intptr_t)device_get_ivars(child));
477 	retval += bus_print_child_footer(dev, child);
478 
479 	return (retval);
480 }
481 
482 static int
483 mvs_child_location(device_t dev, device_t child, struct sbuf *sb)
484 {
485 
486 	sbuf_printf(sb, "channel=%d",
487 	    (int)(intptr_t)device_get_ivars(child));
488 	return (0);
489 }
490 
491 static bus_dma_tag_t
492 mvs_get_dma_tag(device_t bus, device_t child)
493 {
494 
495 	return (bus_get_dma_tag(bus));
496 }
497 
498 static device_method_t mvs_methods[] = {
499 	DEVMETHOD(device_probe,     mvs_probe),
500 	DEVMETHOD(device_attach,    mvs_attach),
501 	DEVMETHOD(device_detach,    mvs_detach),
502 	DEVMETHOD(device_suspend,   mvs_suspend),
503 	DEVMETHOD(device_resume,    mvs_resume),
504 	DEVMETHOD(bus_print_child,  mvs_print_child),
505 	DEVMETHOD(bus_alloc_resource,       mvs_alloc_resource),
506 	DEVMETHOD(bus_release_resource,     mvs_release_resource),
507 	DEVMETHOD(bus_setup_intr,   mvs_setup_intr),
508 	DEVMETHOD(bus_teardown_intr,mvs_teardown_intr),
509 	DEVMETHOD(bus_child_location, mvs_child_location),
510 	DEVMETHOD(bus_get_dma_tag,  mvs_get_dma_tag),
511 	DEVMETHOD(mvs_edma,         mvs_edma),
512 	{ 0, 0 }
513 };
514 static driver_t mvs_driver = {
515         "mvs",
516         mvs_methods,
517         sizeof(struct mvs_controller)
518 };
519 DRIVER_MODULE(mvs, pci, mvs_driver, 0, 0);
520 MODULE_PNP_INFO("W32:vendor/device", pci, mvs, mvs_ids,
521     nitems(mvs_ids) - 1);
522 MODULE_VERSION(mvs, 1);
523 MODULE_DEPEND(mvs, cam, 1, 1, 1);
524