1 /*- 2 * Copyright (c) 2010 Alexander Motin <mav@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include <sys/param.h> 31 #include <sys/module.h> 32 #include <sys/systm.h> 33 #include <sys/kernel.h> 34 #include <sys/ata.h> 35 #include <sys/bus.h> 36 #include <sys/endian.h> 37 #include <sys/malloc.h> 38 #include <sys/lock.h> 39 #include <sys/mutex.h> 40 #include <vm/uma.h> 41 #include <machine/stdarg.h> 42 #include <machine/resource.h> 43 #include <machine/bus.h> 44 #include <sys/rman.h> 45 #include "mvs.h" 46 47 #include <cam/cam.h> 48 #include <cam/cam_ccb.h> 49 #include <cam/cam_sim.h> 50 #include <cam/cam_xpt_sim.h> 51 #include <cam/cam_debug.h> 52 53 /* local prototypes */ 54 static int mvs_ch_suspend(device_t dev); 55 static int mvs_ch_resume(device_t dev); 56 static void mvs_dmainit(device_t dev); 57 static void mvs_dmasetupc_cb(void *xsc, bus_dma_segment_t *segs, int nsegs, int error); 58 static void mvs_dmafini(device_t dev); 59 static void mvs_slotsalloc(device_t dev); 60 static void mvs_slotsfree(device_t dev); 61 static void mvs_setup_edma_queues(device_t dev); 62 static void mvs_set_edma_mode(device_t dev, enum mvs_edma_mode mode); 63 static void mvs_ch_pm(void *arg); 64 static void mvs_ch_intr_locked(void *data); 65 static void mvs_ch_intr(void *data); 66 static void mvs_reset(device_t dev); 67 static void mvs_softreset(device_t dev, union ccb *ccb); 68 69 static int mvs_sata_connect(struct mvs_channel *ch); 70 static int mvs_sata_phy_reset(device_t dev); 71 static int mvs_wait(device_t dev, u_int s, u_int c, int t); 72 static void mvs_tfd_read(device_t dev, union ccb *ccb); 73 static void mvs_tfd_write(device_t dev, union ccb *ccb); 74 static void mvs_legacy_intr(device_t dev); 75 static void mvs_crbq_intr(device_t dev); 76 static void mvs_begin_transaction(device_t dev, union ccb *ccb); 77 static void mvs_legacy_execute_transaction(struct mvs_slot *slot); 78 static void mvs_timeout(struct mvs_slot *slot); 79 static void mvs_dmasetprd(void *arg, bus_dma_segment_t *segs, int nsegs, int error); 80 static void mvs_requeue_frozen(device_t dev); 81 static void mvs_execute_transaction(struct mvs_slot *slot); 82 static void mvs_end_transaction(struct mvs_slot *slot, enum mvs_err_type et); 83 84 static void mvs_issue_read_log(device_t dev); 85 static void mvs_process_read_log(device_t dev, union ccb *ccb); 86 87 static void mvsaction(struct cam_sim *sim, union ccb *ccb); 88 static void mvspoll(struct cam_sim *sim); 89 90 MALLOC_DEFINE(M_MVS, "MVS driver", "MVS driver data buffers"); 91 92 static int 93 mvs_ch_probe(device_t dev) 94 { 95 96 device_set_desc_copy(dev, "Marvell SATA channel"); 97 return (0); 98 } 99 100 static int 101 mvs_ch_attach(device_t dev) 102 { 103 struct mvs_controller *ctlr = device_get_softc(device_get_parent(dev)); 104 struct mvs_channel *ch = device_get_softc(dev); 105 struct cam_devq *devq; 106 int rid, error, i, sata_rev = 0; 107 108 ch->dev = dev; 109 ch->unit = (intptr_t)device_get_ivars(dev); 110 ch->quirks = ctlr->quirks; 111 mtx_init(&ch->mtx, "MVS channel lock", NULL, MTX_DEF); 112 resource_int_value(device_get_name(dev), 113 device_get_unit(dev), "pm_level", &ch->pm_level); 114 if (ch->pm_level > 3) 115 callout_init_mtx(&ch->pm_timer, &ch->mtx, 0); 116 resource_int_value(device_get_name(dev), 117 device_get_unit(dev), "sata_rev", &sata_rev); 118 for (i = 0; i < 16; i++) { 119 ch->user[i].revision = sata_rev; 120 ch->user[i].mode = 0; 121 ch->user[i].bytecount = (ch->quirks & MVS_Q_GENIIE) ? 8192 : 2048; 122 ch->user[i].tags = MVS_MAX_SLOTS; 123 ch->curr[i] = ch->user[i]; 124 if (ch->pm_level) { 125 ch->user[i].caps = CTS_SATA_CAPS_H_PMREQ | 126 CTS_SATA_CAPS_H_APST | 127 CTS_SATA_CAPS_D_PMREQ | CTS_SATA_CAPS_D_APST; 128 } 129 } 130 rid = ch->unit; 131 if (!(ch->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 132 &rid, RF_ACTIVE))) 133 return (ENXIO); 134 mvs_dmainit(dev); 135 mvs_slotsalloc(dev); 136 mvs_ch_resume(dev); 137 mtx_lock(&ch->mtx); 138 rid = ATA_IRQ_RID; 139 if (!(ch->r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 140 &rid, RF_SHAREABLE | RF_ACTIVE))) { 141 device_printf(dev, "Unable to map interrupt\n"); 142 error = ENXIO; 143 goto err0; 144 } 145 if ((bus_setup_intr(dev, ch->r_irq, ATA_INTR_FLAGS, NULL, 146 mvs_ch_intr_locked, dev, &ch->ih))) { 147 device_printf(dev, "Unable to setup interrupt\n"); 148 error = ENXIO; 149 goto err1; 150 } 151 /* Create the device queue for our SIM. */ 152 devq = cam_simq_alloc(MVS_MAX_SLOTS - 1); 153 if (devq == NULL) { 154 device_printf(dev, "Unable to allocate simq\n"); 155 error = ENOMEM; 156 goto err1; 157 } 158 /* Construct SIM entry */ 159 ch->sim = cam_sim_alloc(mvsaction, mvspoll, "mvsch", ch, 160 device_get_unit(dev), &ch->mtx, 161 2, (ch->quirks & MVS_Q_GENI) ? 0 : MVS_MAX_SLOTS - 1, 162 devq); 163 if (ch->sim == NULL) { 164 cam_simq_free(devq); 165 device_printf(dev, "unable to allocate sim\n"); 166 error = ENOMEM; 167 goto err1; 168 } 169 if (xpt_bus_register(ch->sim, dev, 0) != CAM_SUCCESS) { 170 device_printf(dev, "unable to register xpt bus\n"); 171 error = ENXIO; 172 goto err2; 173 } 174 if (xpt_create_path(&ch->path, /*periph*/NULL, cam_sim_path(ch->sim), 175 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 176 device_printf(dev, "unable to create path\n"); 177 error = ENXIO; 178 goto err3; 179 } 180 if (ch->pm_level > 3) { 181 callout_reset(&ch->pm_timer, 182 (ch->pm_level == 4) ? hz / 1000 : hz / 8, 183 mvs_ch_pm, dev); 184 } 185 mtx_unlock(&ch->mtx); 186 return (0); 187 188 err3: 189 xpt_bus_deregister(cam_sim_path(ch->sim)); 190 err2: 191 cam_sim_free(ch->sim, /*free_devq*/TRUE); 192 err1: 193 bus_release_resource(dev, SYS_RES_IRQ, ATA_IRQ_RID, ch->r_irq); 194 err0: 195 bus_release_resource(dev, SYS_RES_MEMORY, ch->unit, ch->r_mem); 196 mtx_unlock(&ch->mtx); 197 mtx_destroy(&ch->mtx); 198 return (error); 199 } 200 201 static int 202 mvs_ch_detach(device_t dev) 203 { 204 struct mvs_channel *ch = device_get_softc(dev); 205 206 mtx_lock(&ch->mtx); 207 xpt_async(AC_LOST_DEVICE, ch->path, NULL); 208 xpt_free_path(ch->path); 209 xpt_bus_deregister(cam_sim_path(ch->sim)); 210 cam_sim_free(ch->sim, /*free_devq*/TRUE); 211 mtx_unlock(&ch->mtx); 212 213 if (ch->pm_level > 3) 214 callout_drain(&ch->pm_timer); 215 bus_teardown_intr(dev, ch->r_irq, ch->ih); 216 bus_release_resource(dev, SYS_RES_IRQ, ATA_IRQ_RID, ch->r_irq); 217 218 mvs_ch_suspend(dev); 219 mvs_slotsfree(dev); 220 mvs_dmafini(dev); 221 222 bus_release_resource(dev, SYS_RES_MEMORY, ch->unit, ch->r_mem); 223 mtx_destroy(&ch->mtx); 224 return (0); 225 } 226 227 static int 228 mvs_ch_suspend(device_t dev) 229 { 230 struct mvs_channel *ch = device_get_softc(dev); 231 232 /* Stop EDMA */ 233 mvs_set_edma_mode(dev, MVS_EDMA_OFF); 234 /* Disable port interrupts. */ 235 ATA_OUTL(ch->r_mem, EDMA_IEM, 0); 236 return (0); 237 } 238 239 static int 240 mvs_ch_resume(device_t dev) 241 { 242 struct mvs_channel *ch = device_get_softc(dev); 243 uint32_t reg; 244 245 /* Disable port interrupts */ 246 ATA_OUTL(ch->r_mem, EDMA_IEM, 0); 247 /* Stop EDMA */ 248 ch->curr_mode = MVS_EDMA_UNKNOWN; 249 mvs_set_edma_mode(dev, MVS_EDMA_OFF); 250 /* Clear and configure FIS interrupts. */ 251 ATA_OUTL(ch->r_mem, SATA_FISIC, 0); 252 reg = ATA_INL(ch->r_mem, SATA_FISC); 253 reg |= SATA_FISC_FISWAIT4HOSTRDYEN_B1; 254 ATA_OUTL(ch->r_mem, SATA_FISC, reg); 255 reg = ATA_INL(ch->r_mem, SATA_FISIM); 256 reg |= SATA_FISC_FISWAIT4HOSTRDYEN_B1; 257 ATA_OUTL(ch->r_mem, SATA_FISC, reg); 258 /* Clear SATA error register. */ 259 ATA_OUTL(ch->r_mem, SATA_SE, 0xffffffff); 260 /* Clear any outstanding error interrupts. */ 261 ATA_OUTL(ch->r_mem, EDMA_IEC, 0); 262 /* Unmask all error interrupts */ 263 ATA_OUTL(ch->r_mem, EDMA_IEM, ~EDMA_IE_TRANSIENT); 264 return (0); 265 } 266 267 struct mvs_dc_cb_args { 268 bus_addr_t maddr; 269 int error; 270 }; 271 272 static void 273 mvs_dmainit(device_t dev) 274 { 275 struct mvs_channel *ch = device_get_softc(dev); 276 struct mvs_dc_cb_args dcba; 277 278 /* EDMA command request area. */ 279 if (bus_dma_tag_create(bus_get_dma_tag(dev), 1024, 0, 280 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 281 NULL, NULL, MVS_WORKRQ_SIZE, 1, MVS_WORKRQ_SIZE, 282 0, NULL, NULL, &ch->dma.workrq_tag)) 283 goto error; 284 if (bus_dmamem_alloc(ch->dma.workrq_tag, (void **)&ch->dma.workrq, 0, 285 &ch->dma.workrq_map)) 286 goto error; 287 if (bus_dmamap_load(ch->dma.workrq_tag, ch->dma.workrq_map, ch->dma.workrq, 288 MVS_WORKRQ_SIZE, mvs_dmasetupc_cb, &dcba, 0) || dcba.error) { 289 bus_dmamem_free(ch->dma.workrq_tag, ch->dma.workrq, ch->dma.workrq_map); 290 goto error; 291 } 292 ch->dma.workrq_bus = dcba.maddr; 293 /* EDMA command response area. */ 294 if (bus_dma_tag_create(bus_get_dma_tag(dev), 256, 0, 295 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 296 NULL, NULL, MVS_WORKRP_SIZE, 1, MVS_WORKRP_SIZE, 297 0, NULL, NULL, &ch->dma.workrp_tag)) 298 goto error; 299 if (bus_dmamem_alloc(ch->dma.workrp_tag, (void **)&ch->dma.workrp, 0, 300 &ch->dma.workrp_map)) 301 goto error; 302 if (bus_dmamap_load(ch->dma.workrp_tag, ch->dma.workrp_map, ch->dma.workrp, 303 MVS_WORKRP_SIZE, mvs_dmasetupc_cb, &dcba, 0) || dcba.error) { 304 bus_dmamem_free(ch->dma.workrp_tag, ch->dma.workrp, ch->dma.workrp_map); 305 goto error; 306 } 307 ch->dma.workrp_bus = dcba.maddr; 308 /* Data area. */ 309 if (bus_dma_tag_create(bus_get_dma_tag(dev), 2, MVS_EPRD_MAX, 310 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 311 NULL, NULL, 312 MVS_SG_ENTRIES * PAGE_SIZE * MVS_MAX_SLOTS, 313 MVS_SG_ENTRIES, MVS_EPRD_MAX, 314 0, busdma_lock_mutex, &ch->mtx, &ch->dma.data_tag)) { 315 goto error; 316 } 317 return; 318 319 error: 320 device_printf(dev, "WARNING - DMA initialization failed\n"); 321 mvs_dmafini(dev); 322 } 323 324 static void 325 mvs_dmasetupc_cb(void *xsc, bus_dma_segment_t *segs, int nsegs, int error) 326 { 327 struct mvs_dc_cb_args *dcba = (struct mvs_dc_cb_args *)xsc; 328 329 if (!(dcba->error = error)) 330 dcba->maddr = segs[0].ds_addr; 331 } 332 333 static void 334 mvs_dmafini(device_t dev) 335 { 336 struct mvs_channel *ch = device_get_softc(dev); 337 338 if (ch->dma.data_tag) { 339 bus_dma_tag_destroy(ch->dma.data_tag); 340 ch->dma.data_tag = NULL; 341 } 342 if (ch->dma.workrp_bus) { 343 bus_dmamap_unload(ch->dma.workrp_tag, ch->dma.workrp_map); 344 bus_dmamem_free(ch->dma.workrp_tag, ch->dma.workrp, ch->dma.workrp_map); 345 ch->dma.workrp_bus = 0; 346 ch->dma.workrp_map = NULL; 347 ch->dma.workrp = NULL; 348 } 349 if (ch->dma.workrp_tag) { 350 bus_dma_tag_destroy(ch->dma.workrp_tag); 351 ch->dma.workrp_tag = NULL; 352 } 353 if (ch->dma.workrq_bus) { 354 bus_dmamap_unload(ch->dma.workrq_tag, ch->dma.workrq_map); 355 bus_dmamem_free(ch->dma.workrq_tag, ch->dma.workrq, ch->dma.workrq_map); 356 ch->dma.workrq_bus = 0; 357 ch->dma.workrq_map = NULL; 358 ch->dma.workrq = NULL; 359 } 360 if (ch->dma.workrq_tag) { 361 bus_dma_tag_destroy(ch->dma.workrq_tag); 362 ch->dma.workrq_tag = NULL; 363 } 364 } 365 366 static void 367 mvs_slotsalloc(device_t dev) 368 { 369 struct mvs_channel *ch = device_get_softc(dev); 370 int i; 371 372 /* Alloc and setup command/dma slots */ 373 bzero(ch->slot, sizeof(ch->slot)); 374 for (i = 0; i < MVS_MAX_SLOTS; i++) { 375 struct mvs_slot *slot = &ch->slot[i]; 376 377 slot->dev = dev; 378 slot->slot = i; 379 slot->state = MVS_SLOT_EMPTY; 380 slot->ccb = NULL; 381 callout_init_mtx(&slot->timeout, &ch->mtx, 0); 382 383 if (bus_dmamap_create(ch->dma.data_tag, 0, &slot->dma.data_map)) 384 device_printf(ch->dev, "FAILURE - create data_map\n"); 385 } 386 } 387 388 static void 389 mvs_slotsfree(device_t dev) 390 { 391 struct mvs_channel *ch = device_get_softc(dev); 392 int i; 393 394 /* Free all dma slots */ 395 for (i = 0; i < MVS_MAX_SLOTS; i++) { 396 struct mvs_slot *slot = &ch->slot[i]; 397 398 callout_drain(&slot->timeout); 399 if (slot->dma.data_map) { 400 bus_dmamap_destroy(ch->dma.data_tag, slot->dma.data_map); 401 slot->dma.data_map = NULL; 402 } 403 } 404 } 405 406 static void 407 mvs_setup_edma_queues(device_t dev) 408 { 409 struct mvs_channel *ch = device_get_softc(dev); 410 uint64_t work; 411 412 /* Requests queue. */ 413 work = ch->dma.workrq_bus; 414 ATA_OUTL(ch->r_mem, EDMA_REQQBAH, work >> 32); 415 ATA_OUTL(ch->r_mem, EDMA_REQQIP, work & 0xffffffff); 416 ATA_OUTL(ch->r_mem, EDMA_REQQOP, work & 0xffffffff); 417 bus_dmamap_sync(ch->dma.workrq_tag, ch->dma.workrq_map, BUS_DMASYNC_PREWRITE); 418 /* Reponses queue. */ 419 bzero(ch->dma.workrp, 256); 420 work = ch->dma.workrp_bus; 421 ATA_OUTL(ch->r_mem, EDMA_RESQBAH, work >> 32); 422 ATA_OUTL(ch->r_mem, EDMA_RESQIP, work & 0xffffffff); 423 ATA_OUTL(ch->r_mem, EDMA_RESQOP, work & 0xffffffff); 424 bus_dmamap_sync(ch->dma.workrp_tag, ch->dma.workrp_map, BUS_DMASYNC_PREREAD); 425 ch->out_idx = 0; 426 ch->in_idx = 0; 427 } 428 429 static void 430 mvs_set_edma_mode(device_t dev, enum mvs_edma_mode mode) 431 { 432 struct mvs_channel *ch = device_get_softc(dev); 433 int timeout; 434 uint32_t ecfg, fcfg, hc, ltm, unkn; 435 436 if (mode == ch->curr_mode) 437 return; 438 /* If we are running, we should stop first. */ 439 if (ch->curr_mode != MVS_EDMA_OFF) { 440 ATA_OUTL(ch->r_mem, EDMA_CMD, EDMA_CMD_EDSEDMA); 441 timeout = 0; 442 while (ATA_INL(ch->r_mem, EDMA_CMD) & EDMA_CMD_EENEDMA) { 443 DELAY(1000); 444 if (timeout++ > 1000) { 445 device_printf(dev, "stopping EDMA engine failed\n"); 446 break; 447 } 448 }; 449 } 450 ch->curr_mode = mode; 451 ch->fbs_enabled = 0; 452 ch->fake_busy = 0; 453 /* Report mode to controller. Needed for correct CCC operation. */ 454 MVS_EDMA(device_get_parent(dev), dev, mode); 455 /* Configure new mode. */ 456 ecfg = EDMA_CFG_RESERVED | EDMA_CFG_RESERVED2 | EDMA_CFG_EHOSTQUEUECACHEEN; 457 if (ch->pm_present) { 458 ecfg |= EDMA_CFG_EMASKRXPM; 459 if (ch->quirks & MVS_Q_GENIIE) { 460 ecfg |= EDMA_CFG_EEDMAFBS; 461 ch->fbs_enabled = 1; 462 } 463 } 464 if (ch->quirks & MVS_Q_GENI) 465 ecfg |= EDMA_CFG_ERDBSZ; 466 else if (ch->quirks & MVS_Q_GENII) 467 ecfg |= EDMA_CFG_ERDBSZEXT | EDMA_CFG_EWRBUFFERLEN; 468 if (ch->quirks & MVS_Q_CT) 469 ecfg |= EDMA_CFG_ECUTTHROUGHEN; 470 if (mode != MVS_EDMA_OFF) 471 ecfg |= EDMA_CFG_EEARLYCOMPLETIONEN; 472 if (mode == MVS_EDMA_QUEUED) 473 ecfg |= EDMA_CFG_EQUE; 474 else if (mode == MVS_EDMA_NCQ) 475 ecfg |= EDMA_CFG_ESATANATVCMDQUE; 476 ATA_OUTL(ch->r_mem, EDMA_CFG, ecfg); 477 mvs_setup_edma_queues(dev); 478 if (ch->quirks & MVS_Q_GENIIE) { 479 /* Configure FBS-related registers */ 480 fcfg = ATA_INL(ch->r_mem, SATA_FISC); 481 ltm = ATA_INL(ch->r_mem, SATA_LTM); 482 hc = ATA_INL(ch->r_mem, EDMA_HC); 483 if (ch->fbs_enabled) { 484 fcfg |= SATA_FISC_FISDMAACTIVATESYNCRESP; 485 if (mode == MVS_EDMA_NCQ) { 486 fcfg &= ~SATA_FISC_FISWAIT4HOSTRDYEN_B0; 487 hc &= ~EDMA_IE_EDEVERR; 488 } else { 489 fcfg |= SATA_FISC_FISWAIT4HOSTRDYEN_B0; 490 hc |= EDMA_IE_EDEVERR; 491 } 492 ltm |= (1 << 8); 493 } else { 494 fcfg &= ~SATA_FISC_FISDMAACTIVATESYNCRESP; 495 fcfg &= ~SATA_FISC_FISWAIT4HOSTRDYEN_B0; 496 hc |= EDMA_IE_EDEVERR; 497 ltm &= ~(1 << 8); 498 } 499 ATA_OUTL(ch->r_mem, SATA_FISC, fcfg); 500 ATA_OUTL(ch->r_mem, SATA_LTM, ltm); 501 ATA_OUTL(ch->r_mem, EDMA_HC, hc); 502 /* This is some magic, required to handle several DRQs 503 * with basic DMA. */ 504 unkn = ATA_INL(ch->r_mem, EDMA_UNKN_RESD); 505 if (mode == MVS_EDMA_OFF) 506 unkn |= 1; 507 else 508 unkn &= ~1; 509 ATA_OUTL(ch->r_mem, EDMA_UNKN_RESD, unkn); 510 } 511 /* Run EDMA. */ 512 if (mode != MVS_EDMA_OFF) 513 ATA_OUTL(ch->r_mem, EDMA_CMD, EDMA_CMD_EENEDMA); 514 } 515 516 devclass_t mvs_devclass; 517 devclass_t mvsch_devclass; 518 static device_method_t mvsch_methods[] = { 519 DEVMETHOD(device_probe, mvs_ch_probe), 520 DEVMETHOD(device_attach, mvs_ch_attach), 521 DEVMETHOD(device_detach, mvs_ch_detach), 522 DEVMETHOD(device_suspend, mvs_ch_suspend), 523 DEVMETHOD(device_resume, mvs_ch_resume), 524 { 0, 0 } 525 }; 526 static driver_t mvsch_driver = { 527 "mvsch", 528 mvsch_methods, 529 sizeof(struct mvs_channel) 530 }; 531 DRIVER_MODULE(mvsch, mvs, mvsch_driver, mvsch_devclass, 0, 0); 532 DRIVER_MODULE(mvsch, sata, mvsch_driver, mvsch_devclass, 0, 0); 533 534 static void 535 mvs_phy_check_events(device_t dev, u_int32_t serr) 536 { 537 struct mvs_channel *ch = device_get_softc(dev); 538 539 if (ch->pm_level == 0) { 540 u_int32_t status = ATA_INL(ch->r_mem, SATA_SS); 541 union ccb *ccb; 542 543 if (bootverbose) { 544 if (((status & SATA_SS_DET_MASK) == SATA_SS_DET_PHY_ONLINE) && 545 ((status & SATA_SS_SPD_MASK) != SATA_SS_SPD_NO_SPEED) && 546 ((status & SATA_SS_IPM_MASK) == SATA_SS_IPM_ACTIVE)) { 547 device_printf(dev, "CONNECT requested\n"); 548 } else 549 device_printf(dev, "DISCONNECT requested\n"); 550 } 551 mvs_reset(dev); 552 if ((ccb = xpt_alloc_ccb_nowait()) == NULL) 553 return; 554 if (xpt_create_path(&ccb->ccb_h.path, NULL, 555 cam_sim_path(ch->sim), 556 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 557 xpt_free_ccb(ccb); 558 return; 559 } 560 xpt_rescan(ccb); 561 } 562 } 563 564 static void 565 mvs_notify_events(device_t dev) 566 { 567 struct mvs_channel *ch = device_get_softc(dev); 568 struct cam_path *dpath; 569 uint32_t fis; 570 int d; 571 572 /* Try to read PMP field from SDB FIS. Present only for Gen-IIe. */ 573 fis = ATA_INL(ch->r_mem, SATA_FISDW0); 574 if ((fis & 0x80ff) == 0x80a1) 575 d = (fis & 0x0f00) >> 8; 576 else 577 d = ch->pm_present ? 15 : 0; 578 if (bootverbose) 579 device_printf(dev, "SNTF %d\n", d); 580 if (xpt_create_path(&dpath, NULL, 581 xpt_path_path_id(ch->path), d, 0) == CAM_REQ_CMP) { 582 xpt_async(AC_SCSI_AEN, dpath, NULL); 583 xpt_free_path(dpath); 584 } 585 } 586 587 static void 588 mvs_ch_intr_locked(void *data) 589 { 590 struct mvs_intr_arg *arg = (struct mvs_intr_arg *)data; 591 device_t dev = (device_t)arg->arg; 592 struct mvs_channel *ch = device_get_softc(dev); 593 594 mtx_lock(&ch->mtx); 595 mvs_ch_intr(data); 596 mtx_unlock(&ch->mtx); 597 } 598 599 static void 600 mvs_ch_pm(void *arg) 601 { 602 device_t dev = (device_t)arg; 603 struct mvs_channel *ch = device_get_softc(dev); 604 uint32_t work; 605 606 if (ch->numrslots != 0) 607 return; 608 /* If we are idle - request power state transition. */ 609 work = ATA_INL(ch->r_mem, SATA_SC); 610 work &= ~SATA_SC_SPM_MASK; 611 if (ch->pm_level == 4) 612 work |= SATA_SC_SPM_PARTIAL; 613 else 614 work |= SATA_SC_SPM_SLUMBER; 615 ATA_OUTL(ch->r_mem, SATA_SC, work); 616 } 617 618 static void 619 mvs_ch_pm_wake(device_t dev) 620 { 621 struct mvs_channel *ch = device_get_softc(dev); 622 uint32_t work; 623 int timeout = 0; 624 625 work = ATA_INL(ch->r_mem, SATA_SS); 626 if (work & SATA_SS_IPM_ACTIVE) 627 return; 628 /* If we are not in active state - request power state transition. */ 629 work = ATA_INL(ch->r_mem, SATA_SC); 630 work &= ~SATA_SC_SPM_MASK; 631 work |= SATA_SC_SPM_ACTIVE; 632 ATA_OUTL(ch->r_mem, SATA_SC, work); 633 /* Wait for transition to happen. */ 634 while ((ATA_INL(ch->r_mem, SATA_SS) & SATA_SS_IPM_ACTIVE) == 0 && 635 timeout++ < 100) { 636 DELAY(100); 637 } 638 } 639 640 static void 641 mvs_ch_intr(void *data) 642 { 643 struct mvs_intr_arg *arg = (struct mvs_intr_arg *)data; 644 device_t dev = (device_t)arg->arg; 645 struct mvs_channel *ch = device_get_softc(dev); 646 uint32_t iec, serr = 0, fisic = 0; 647 enum mvs_err_type et; 648 int i, ccs, port = -1, selfdis = 0; 649 int edma = (ch->numtslots != 0 || ch->numdslots != 0); 650 651 //device_printf(dev, "irq cause %02x EDMA %d IEC %08x\n", 652 // arg->cause, edma, ATA_INL(ch->r_mem, EDMA_IEC)); 653 /* New item in response queue. */ 654 if ((arg->cause & 2) && edma) 655 mvs_crbq_intr(dev); 656 /* Some error or special event. */ 657 if (arg->cause & 1) { 658 iec = ATA_INL(ch->r_mem, EDMA_IEC); 659 //device_printf(dev, "irq cause %02x EDMA %d IEC %08x\n", 660 // arg->cause, edma, iec); 661 if (iec & EDMA_IE_SERRINT) { 662 serr = ATA_INL(ch->r_mem, SATA_SE); 663 ATA_OUTL(ch->r_mem, SATA_SE, serr); 664 //device_printf(dev, "SERR %08x\n", serr); 665 } 666 /* EDMA self-disabled due to error. */ 667 if (iec & EDMA_IE_ESELFDIS) 668 selfdis = 1; 669 /* Transport interrupt. */ 670 if (iec & EDMA_IE_ETRANSINT) { 671 /* For Gen-I this bit means self-disable. */ 672 if (ch->quirks & MVS_Q_GENI) 673 selfdis = 1; 674 /* For Gen-II this bit means SDB-N. */ 675 else if (ch->quirks & MVS_Q_GENII) 676 fisic = SATA_FISC_FISWAIT4HOSTRDYEN_B1; 677 else /* For Gen-IIe - read FIS interrupt cause. */ 678 fisic = ATA_INL(ch->r_mem, SATA_FISIC); 679 //device_printf(dev, "FISIC %08x\n", fisic); 680 } 681 if (selfdis) 682 ch->curr_mode = MVS_EDMA_UNKNOWN; 683 ATA_OUTL(ch->r_mem, EDMA_IEC, ~iec); 684 /* Interface errors or Device error. */ 685 if (iec & (0xfc1e9000 | EDMA_IE_EDEVERR)) { 686 port = -1; 687 if (ch->numpslots != 0) { 688 ccs = 0; 689 } else { 690 if (ch->quirks & MVS_Q_GENIIE) 691 ccs = EDMA_S_EIOID(ATA_INL(ch->r_mem, EDMA_S)); 692 else 693 ccs = EDMA_S_EDEVQUETAG(ATA_INL(ch->r_mem, EDMA_S)); 694 /* Check if error is one-PMP-port-specific, */ 695 if (ch->fbs_enabled) { 696 /* Which ports were active. */ 697 for (i = 0; i < 16; i++) { 698 if (ch->numrslotspd[i] == 0) 699 continue; 700 if (port == -1) 701 port = i; 702 else if (port != i) { 703 port = -2; 704 break; 705 } 706 } 707 /* If several ports were active and EDMA still enabled - 708 * other ports are probably unaffected and may continue. 709 */ 710 if (port == -2 && !selfdis) { 711 uint16_t p = ATA_INL(ch->r_mem, SATA_SATAITC) >> 16; 712 port = ffs(p) - 1; 713 if (port != (fls(p) - 1)) 714 port = -2; 715 } 716 } 717 } 718 //device_printf(dev, "err slot %d port %d\n", ccs, port); 719 mvs_requeue_frozen(dev); 720 for (i = 0; i < MVS_MAX_SLOTS; i++) { 721 /* XXX: reqests in loading state. */ 722 if (((ch->rslots >> i) & 1) == 0) 723 continue; 724 if (port >= 0 && 725 ch->slot[i].ccb->ccb_h.target_id != port) 726 continue; 727 if (iec & EDMA_IE_EDEVERR) { /* Device error. */ 728 if (port != -2) { 729 if (ch->numtslots == 0) { 730 /* Untagged operation. */ 731 if (i == ccs) 732 et = MVS_ERR_TFE; 733 else 734 et = MVS_ERR_INNOCENT; 735 } else { 736 /* Tagged operation. */ 737 et = MVS_ERR_NCQ; 738 } 739 } else { 740 et = MVS_ERR_TFE; 741 ch->fatalerr = 1; 742 } 743 } else if (iec & 0xfc1e9000) { 744 if (ch->numtslots == 0 && i != ccs && port != -2) 745 et = MVS_ERR_INNOCENT; 746 else 747 et = MVS_ERR_SATA; 748 } else 749 et = MVS_ERR_INVALID; 750 mvs_end_transaction(&ch->slot[i], et); 751 } 752 } 753 /* Process SDB-N. */ 754 if (fisic & SATA_FISC_FISWAIT4HOSTRDYEN_B1) 755 mvs_notify_events(dev); 756 if (fisic) 757 ATA_OUTL(ch->r_mem, SATA_FISIC, ~fisic); 758 /* Process hot-plug. */ 759 if ((iec & (EDMA_IE_EDEVDIS | EDMA_IE_EDEVCON)) || 760 (serr & SATA_SE_PHY_CHANGED)) 761 mvs_phy_check_events(dev, serr); 762 } 763 /* Legacy mode device interrupt. */ 764 if ((arg->cause & 2) && !edma) 765 mvs_legacy_intr(dev); 766 } 767 768 static uint8_t 769 mvs_getstatus(device_t dev, int clear) 770 { 771 struct mvs_channel *ch = device_get_softc(dev); 772 uint8_t status = ATA_INB(ch->r_mem, clear ? ATA_STATUS : ATA_ALTSTAT); 773 774 if (ch->fake_busy) { 775 if (status & (ATA_S_BUSY | ATA_S_DRQ | ATA_S_ERROR)) 776 ch->fake_busy = 0; 777 else 778 status |= ATA_S_BUSY; 779 } 780 return (status); 781 } 782 783 static void 784 mvs_legacy_intr(device_t dev) 785 { 786 struct mvs_channel *ch = device_get_softc(dev); 787 struct mvs_slot *slot = &ch->slot[0]; /* PIO is always in slot 0. */ 788 union ccb *ccb = slot->ccb; 789 enum mvs_err_type et = MVS_ERR_NONE; 790 int port; 791 u_int length; 792 uint8_t status, ireason; 793 794 /* Clear interrupt and get status. */ 795 status = mvs_getstatus(dev, 1); 796 // device_printf(dev, "Legacy intr status %02x\n", 797 // status); 798 if (slot->state < MVS_SLOT_RUNNING) 799 return; 800 port = ccb->ccb_h.target_id & 0x0f; 801 /* Wait a bit for late !BUSY status update. */ 802 if (status & ATA_S_BUSY) { 803 DELAY(100); 804 if ((status = mvs_getstatus(dev, 1)) & ATA_S_BUSY) { 805 DELAY(1000); 806 if ((status = mvs_getstatus(dev, 1)) & ATA_S_BUSY) 807 return; 808 } 809 } 810 /* If we got an error, we are done. */ 811 if (status & ATA_S_ERROR) { 812 et = MVS_ERR_TFE; 813 goto end_finished; 814 } 815 if (ccb->ccb_h.func_code == XPT_ATA_IO) { /* ATA PIO */ 816 ccb->ataio.res.status = status; 817 /* Are we moving data? */ 818 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 819 /* If data read command - get them. */ 820 if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 821 if (mvs_wait(dev, ATA_S_DRQ, ATA_S_BUSY, 1000) < 0) { 822 device_printf(dev, "timeout waiting for read DRQ\n"); 823 et = MVS_ERR_TIMEOUT; 824 goto end_finished; 825 } 826 ATA_INSW_STRM(ch->r_mem, ATA_DATA, 827 (uint16_t *)(ccb->ataio.data_ptr + ch->donecount), 828 ch->transfersize / 2); 829 } 830 /* Update how far we've gotten. */ 831 ch->donecount += ch->transfersize; 832 /* Do we need more? */ 833 if (ccb->ataio.dxfer_len > ch->donecount) { 834 /* Set this transfer size according to HW capabilities */ 835 ch->transfersize = min(ccb->ataio.dxfer_len - ch->donecount, 836 ch->curr[ccb->ccb_h.target_id].bytecount); 837 /* If data write command - put them */ 838 if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_OUT) { 839 if (mvs_wait(dev, ATA_S_DRQ, ATA_S_BUSY, 1000) < 0) { 840 device_printf(dev, "timeout waiting for write DRQ\n"); 841 et = MVS_ERR_TIMEOUT; 842 goto end_finished; 843 } 844 ATA_OUTSW_STRM(ch->r_mem, ATA_DATA, 845 (uint16_t *)(ccb->ataio.data_ptr + ch->donecount), 846 ch->transfersize / 2); 847 return; 848 } 849 /* If data read command, return & wait for interrupt */ 850 if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) 851 return; 852 } 853 } 854 } else if (ch->basic_dma) { /* ATAPI DMA */ 855 if (status & ATA_S_DWF) 856 et = MVS_ERR_TFE; 857 else if (ATA_INL(ch->r_mem, DMA_S) & DMA_S_ERR) 858 et = MVS_ERR_TFE; 859 /* Stop basic DMA. */ 860 ATA_OUTL(ch->r_mem, DMA_C, 0); 861 goto end_finished; 862 } else { /* ATAPI PIO */ 863 length = ATA_INB(ch->r_mem,ATA_CYL_LSB) | (ATA_INB(ch->r_mem,ATA_CYL_MSB) << 8); 864 ireason = ATA_INB(ch->r_mem,ATA_IREASON); 865 //device_printf(dev, "status %02x, ireason %02x, length %d\n", status, ireason, length); 866 switch ((ireason & (ATA_I_CMD | ATA_I_IN)) | 867 (status & ATA_S_DRQ)) { 868 869 case ATAPI_P_CMDOUT: 870 device_printf(dev, "ATAPI CMDOUT\n"); 871 /* Return wait for interrupt */ 872 return; 873 874 case ATAPI_P_WRITE: 875 //device_printf(dev, "ATAPI WRITE\n"); 876 if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 877 device_printf(dev, "trying to write on read buffer\n"); 878 et = MVS_ERR_TFE; 879 goto end_finished; 880 break; 881 } 882 ATA_OUTSW_STRM(ch->r_mem, ATA_DATA, 883 (uint16_t *)(ccb->csio.data_ptr + ch->donecount), 884 length / 2); 885 ch->donecount += length; 886 /* Set next transfer size according to HW capabilities */ 887 ch->transfersize = min(ccb->csio.dxfer_len - ch->donecount, 888 ch->curr[ccb->ccb_h.target_id].bytecount); 889 /* Return wait for interrupt */ 890 return; 891 892 case ATAPI_P_READ: 893 //device_printf(dev, "ATAPI READ\n"); 894 if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_OUT) { 895 device_printf(dev, "trying to read on write buffer\n"); 896 et = MVS_ERR_TFE; 897 goto end_finished; 898 } 899 ATA_INSW_STRM(ch->r_mem, ATA_DATA, 900 (uint16_t *)(ccb->csio.data_ptr + ch->donecount), 901 length / 2); 902 ch->donecount += length; 903 /* Set next transfer size according to HW capabilities */ 904 ch->transfersize = min(ccb->csio.dxfer_len - ch->donecount, 905 ch->curr[ccb->ccb_h.target_id].bytecount); 906 /* Return wait for interrupt */ 907 return; 908 909 case ATAPI_P_DONEDRQ: 910 device_printf(dev, "ATAPI DONEDRQ\n"); 911 device_printf(dev, 912 "WARNING - DONEDRQ non conformant device\n"); 913 if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 914 ATA_INSW_STRM(ch->r_mem, ATA_DATA, 915 (uint16_t *)(ccb->csio.data_ptr + ch->donecount), 916 length / 2); 917 ch->donecount += length; 918 } 919 else if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_OUT) { 920 ATA_OUTSW_STRM(ch->r_mem, ATA_DATA, 921 (uint16_t *)(ccb->csio.data_ptr + ch->donecount), 922 length / 2); 923 ch->donecount += length; 924 } 925 else 926 et = MVS_ERR_TFE; 927 /* FALLTHROUGH */ 928 929 case ATAPI_P_ABORT: 930 case ATAPI_P_DONE: 931 //device_printf(dev, "ATAPI ABORT/DONE\n"); 932 if (status & (ATA_S_ERROR | ATA_S_DWF)) 933 et = MVS_ERR_TFE; 934 goto end_finished; 935 936 default: 937 device_printf(dev, "unknown transfer phase (status %02x, ireason %02x)\n", 938 status, ireason); 939 et = MVS_ERR_TFE; 940 } 941 } 942 943 end_finished: 944 mvs_end_transaction(slot, et); 945 } 946 947 static void 948 mvs_crbq_intr(device_t dev) 949 { 950 struct mvs_channel *ch = device_get_softc(dev); 951 struct mvs_crpb *crpb; 952 union ccb *ccb; 953 int in_idx, cin_idx, slot; 954 uint16_t flags; 955 956 in_idx = (ATA_INL(ch->r_mem, EDMA_RESQIP) & EDMA_RESQP_ERPQP_MASK) >> 957 EDMA_RESQP_ERPQP_SHIFT; 958 bus_dmamap_sync(ch->dma.workrp_tag, ch->dma.workrp_map, 959 BUS_DMASYNC_POSTREAD); 960 cin_idx = ch->in_idx; 961 ch->in_idx = in_idx; 962 while (in_idx != cin_idx) { 963 crpb = (struct mvs_crpb *) 964 (ch->dma.workrp + MVS_CRPB_OFFSET + (MVS_CRPB_SIZE * cin_idx)); 965 slot = le16toh(crpb->id) & MVS_CRPB_TAG_MASK; 966 flags = le16toh(crpb->rspflg); 967 //device_printf(dev, "CRPB %d %d %04x\n", cin_idx, slot, flags); 968 /* 969 * Handle only successfull completions here. 970 * Errors will be handled by main intr handler. 971 */ 972 if (ch->numtslots != 0 || (flags & EDMA_IE_EDEVERR) == 0) { 973 if ((flags >> 8) & ATA_S_ERROR) 974 device_printf(dev, "ERROR STATUS CRPB %d %d %04x\n", cin_idx, slot, flags); 975 if (ch->slot[slot].state >= MVS_SLOT_RUNNING) { 976 ccb = ch->slot[slot].ccb; 977 ccb->ataio.res.status = (flags & MVS_CRPB_ATASTS_MASK) >> 978 MVS_CRPB_ATASTS_SHIFT; 979 mvs_end_transaction(&ch->slot[slot], MVS_ERR_NONE); 980 } else 981 device_printf(dev, "EMPTY CRPB %d (->%d) %d %04x\n", cin_idx, in_idx, slot, flags); 982 } else 983 device_printf(dev, "ERROR FLAGS CRPB %d %d %04x\n", cin_idx, slot, flags); 984 985 cin_idx = (cin_idx + 1) & (MVS_MAX_SLOTS - 1); 986 } 987 bus_dmamap_sync(ch->dma.workrp_tag, ch->dma.workrp_map, 988 BUS_DMASYNC_PREREAD); 989 if (cin_idx == ch->in_idx) { 990 ATA_OUTL(ch->r_mem, EDMA_RESQOP, 991 ch->dma.workrp_bus | (cin_idx << EDMA_RESQP_ERPQP_SHIFT)); 992 } 993 } 994 995 /* Must be called with channel locked. */ 996 static int 997 mvs_check_collision(device_t dev, union ccb *ccb) 998 { 999 struct mvs_channel *ch = device_get_softc(dev); 1000 1001 if (ccb->ccb_h.func_code == XPT_ATA_IO) { 1002 /* NCQ DMA */ 1003 if (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) { 1004 /* Can't mix NCQ and non-NCQ DMA commands. */ 1005 if (ch->numdslots != 0) 1006 return (1); 1007 /* Can't mix NCQ and PIO commands. */ 1008 if (ch->numpslots != 0) 1009 return (1); 1010 /* If we have no FBS */ 1011 if (!ch->fbs_enabled) { 1012 /* Tagged command while tagged to other target is active. */ 1013 if (ch->numtslots != 0 && 1014 ch->taggedtarget != ccb->ccb_h.target_id) 1015 return (1); 1016 } 1017 /* Non-NCQ DMA */ 1018 } else if (ccb->ataio.cmd.flags & CAM_ATAIO_DMA) { 1019 /* Can't mix non-NCQ DMA and NCQ commands. */ 1020 if (ch->numtslots != 0) 1021 return (1); 1022 /* Can't mix non-NCQ DMA and PIO commands. */ 1023 if (ch->numpslots != 0) 1024 return (1); 1025 /* PIO */ 1026 } else { 1027 /* Can't mix PIO with anything. */ 1028 if (ch->numrslots != 0) 1029 return (1); 1030 } 1031 if (ccb->ataio.cmd.flags & (CAM_ATAIO_CONTROL | CAM_ATAIO_NEEDRESULT)) { 1032 /* Atomic command while anything active. */ 1033 if (ch->numrslots != 0) 1034 return (1); 1035 } 1036 } else { /* ATAPI */ 1037 /* ATAPI goes without EDMA, so can't mix it with anything. */ 1038 if (ch->numrslots != 0) 1039 return (1); 1040 } 1041 /* We have some atomic command running. */ 1042 if (ch->aslots != 0) 1043 return (1); 1044 return (0); 1045 } 1046 1047 static void 1048 mvs_tfd_read(device_t dev, union ccb *ccb) 1049 { 1050 struct mvs_channel *ch = device_get_softc(dev); 1051 struct ata_res *res = &ccb->ataio.res; 1052 1053 res->status = ATA_INB(ch->r_mem, ATA_ALTSTAT); 1054 res->error = ATA_INB(ch->r_mem, ATA_ERROR); 1055 res->device = ATA_INB(ch->r_mem, ATA_DRIVE); 1056 ATA_OUTB(ch->r_mem, ATA_CONTROL, ATA_A_HOB); 1057 res->sector_count_exp = ATA_INB(ch->r_mem, ATA_COUNT); 1058 res->lba_low_exp = ATA_INB(ch->r_mem, ATA_SECTOR); 1059 res->lba_mid_exp = ATA_INB(ch->r_mem, ATA_CYL_LSB); 1060 res->lba_high_exp = ATA_INB(ch->r_mem, ATA_CYL_MSB); 1061 ATA_OUTB(ch->r_mem, ATA_CONTROL, 0); 1062 res->sector_count = ATA_INB(ch->r_mem, ATA_COUNT); 1063 res->lba_low = ATA_INB(ch->r_mem, ATA_SECTOR); 1064 res->lba_mid = ATA_INB(ch->r_mem, ATA_CYL_LSB); 1065 res->lba_high = ATA_INB(ch->r_mem, ATA_CYL_MSB); 1066 } 1067 1068 static void 1069 mvs_tfd_write(device_t dev, union ccb *ccb) 1070 { 1071 struct mvs_channel *ch = device_get_softc(dev); 1072 struct ata_cmd *cmd = &ccb->ataio.cmd; 1073 1074 ATA_OUTB(ch->r_mem, ATA_DRIVE, cmd->device); 1075 ATA_OUTB(ch->r_mem, ATA_CONTROL, cmd->control); 1076 ATA_OUTB(ch->r_mem, ATA_FEATURE, cmd->features_exp); 1077 ATA_OUTB(ch->r_mem, ATA_FEATURE, cmd->features); 1078 ATA_OUTB(ch->r_mem, ATA_COUNT, cmd->sector_count_exp); 1079 ATA_OUTB(ch->r_mem, ATA_COUNT, cmd->sector_count); 1080 ATA_OUTB(ch->r_mem, ATA_SECTOR, cmd->lba_low_exp); 1081 ATA_OUTB(ch->r_mem, ATA_SECTOR, cmd->lba_low); 1082 ATA_OUTB(ch->r_mem, ATA_CYL_LSB, cmd->lba_mid_exp); 1083 ATA_OUTB(ch->r_mem, ATA_CYL_LSB, cmd->lba_mid); 1084 ATA_OUTB(ch->r_mem, ATA_CYL_MSB, cmd->lba_high_exp); 1085 ATA_OUTB(ch->r_mem, ATA_CYL_MSB, cmd->lba_high); 1086 ATA_OUTB(ch->r_mem, ATA_COMMAND, cmd->command); 1087 } 1088 1089 1090 /* Must be called with channel locked. */ 1091 static void 1092 mvs_begin_transaction(device_t dev, union ccb *ccb) 1093 { 1094 struct mvs_channel *ch = device_get_softc(dev); 1095 struct mvs_slot *slot; 1096 int slotn, tag; 1097 1098 if (ch->pm_level > 0) 1099 mvs_ch_pm_wake(dev); 1100 /* Softreset is a special case. */ 1101 if (ccb->ccb_h.func_code == XPT_ATA_IO && 1102 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL)) { 1103 mvs_softreset(dev, ccb); 1104 return; 1105 } 1106 /* Choose empty slot. */ 1107 slotn = ffs(~ch->oslots) - 1; 1108 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1109 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 1110 if (ch->quirks & MVS_Q_GENIIE) 1111 tag = ffs(~ch->otagspd[ccb->ccb_h.target_id]) - 1; 1112 else 1113 tag = slotn; 1114 } else 1115 tag = 0; 1116 /* Occupy chosen slot. */ 1117 slot = &ch->slot[slotn]; 1118 slot->ccb = ccb; 1119 slot->tag = tag; 1120 /* Stop PM timer. */ 1121 if (ch->numrslots == 0 && ch->pm_level > 3) 1122 callout_stop(&ch->pm_timer); 1123 /* Update channel stats. */ 1124 ch->oslots |= (1 << slot->slot); 1125 ch->numrslots++; 1126 ch->numrslotspd[ccb->ccb_h.target_id]++; 1127 if (ccb->ccb_h.func_code == XPT_ATA_IO) { 1128 if (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) { 1129 ch->otagspd[ccb->ccb_h.target_id] |= (1 << slot->tag); 1130 ch->numtslots++; 1131 ch->numtslotspd[ccb->ccb_h.target_id]++; 1132 ch->taggedtarget = ccb->ccb_h.target_id; 1133 mvs_set_edma_mode(dev, MVS_EDMA_NCQ); 1134 } else if (ccb->ataio.cmd.flags & CAM_ATAIO_DMA) { 1135 ch->numdslots++; 1136 mvs_set_edma_mode(dev, MVS_EDMA_ON); 1137 } else { 1138 ch->numpslots++; 1139 mvs_set_edma_mode(dev, MVS_EDMA_OFF); 1140 } 1141 if (ccb->ataio.cmd.flags & 1142 (CAM_ATAIO_CONTROL | CAM_ATAIO_NEEDRESULT)) { 1143 ch->aslots |= (1 << slot->slot); 1144 } 1145 } else { 1146 uint8_t *cdb = (ccb->ccb_h.flags & CAM_CDB_POINTER) ? 1147 ccb->csio.cdb_io.cdb_ptr : ccb->csio.cdb_io.cdb_bytes; 1148 ch->numpslots++; 1149 /* Use ATAPI DMA only for commands without under-/overruns. */ 1150 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE && 1151 ch->curr[ccb->ccb_h.target_id].mode >= ATA_DMA && 1152 (ch->quirks & MVS_Q_SOC) == 0 && 1153 (cdb[0] == 0x08 || 1154 cdb[0] == 0x0a || 1155 cdb[0] == 0x28 || 1156 cdb[0] == 0x2a || 1157 cdb[0] == 0x88 || 1158 cdb[0] == 0x8a || 1159 cdb[0] == 0xa8 || 1160 cdb[0] == 0xaa || 1161 cdb[0] == 0xbe)) { 1162 ch->basic_dma = 1; 1163 } 1164 mvs_set_edma_mode(dev, MVS_EDMA_OFF); 1165 } 1166 if (ch->numpslots == 0 || ch->basic_dma) { 1167 void *buf; 1168 bus_size_t size; 1169 1170 slot->state = MVS_SLOT_LOADING; 1171 if (ccb->ccb_h.func_code == XPT_ATA_IO) { 1172 buf = ccb->ataio.data_ptr; 1173 size = ccb->ataio.dxfer_len; 1174 } else { 1175 buf = ccb->csio.data_ptr; 1176 size = ccb->csio.dxfer_len; 1177 } 1178 bus_dmamap_load(ch->dma.data_tag, slot->dma.data_map, 1179 buf, size, mvs_dmasetprd, slot, 0); 1180 } else 1181 mvs_legacy_execute_transaction(slot); 1182 } 1183 1184 /* Locked by busdma engine. */ 1185 static void 1186 mvs_dmasetprd(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1187 { 1188 struct mvs_slot *slot = arg; 1189 struct mvs_channel *ch = device_get_softc(slot->dev); 1190 struct mvs_eprd *eprd; 1191 int i; 1192 1193 if (error) { 1194 device_printf(slot->dev, "DMA load error\n"); 1195 mvs_end_transaction(slot, MVS_ERR_INVALID); 1196 return; 1197 } 1198 KASSERT(nsegs <= MVS_SG_ENTRIES, ("too many DMA segment entries\n")); 1199 /* If there is only one segment - no need to use S/G table on Gen-IIe. */ 1200 if (nsegs == 1 && ch->basic_dma == 0 && (ch->quirks & MVS_Q_GENIIE)) { 1201 slot->dma.addr = segs[0].ds_addr; 1202 slot->dma.len = segs[0].ds_len; 1203 } else { 1204 slot->dma.addr = 0; 1205 /* Get a piece of the workspace for this EPRD */ 1206 eprd = (struct mvs_eprd *) 1207 (ch->dma.workrq + MVS_EPRD_OFFSET + (MVS_EPRD_SIZE * slot->slot)); 1208 /* Fill S/G table */ 1209 for (i = 0; i < nsegs; i++) { 1210 eprd[i].prdbal = htole32(segs[i].ds_addr); 1211 eprd[i].bytecount = htole32(segs[i].ds_len & MVS_EPRD_MASK); 1212 eprd[i].prdbah = htole32((segs[i].ds_addr >> 16) >> 16); 1213 } 1214 eprd[i - 1].bytecount |= htole32(MVS_EPRD_EOF); 1215 } 1216 bus_dmamap_sync(ch->dma.data_tag, slot->dma.data_map, 1217 ((slot->ccb->ccb_h.flags & CAM_DIR_IN) ? 1218 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE)); 1219 if (ch->basic_dma) 1220 mvs_legacy_execute_transaction(slot); 1221 else 1222 mvs_execute_transaction(slot); 1223 } 1224 1225 static void 1226 mvs_legacy_execute_transaction(struct mvs_slot *slot) 1227 { 1228 device_t dev = slot->dev; 1229 struct mvs_channel *ch = device_get_softc(dev); 1230 bus_addr_t eprd; 1231 union ccb *ccb = slot->ccb; 1232 int port = ccb->ccb_h.target_id & 0x0f; 1233 int timeout; 1234 1235 slot->state = MVS_SLOT_RUNNING; 1236 ch->rslots |= (1 << slot->slot); 1237 ATA_OUTB(ch->r_mem, SATA_SATAICTL, port << SATA_SATAICTL_PMPTX_SHIFT); 1238 if (ccb->ccb_h.func_code == XPT_ATA_IO) { 1239 // device_printf(dev, "%d Legacy command %02x size %d\n", 1240 // port, ccb->ataio.cmd.command, ccb->ataio.dxfer_len); 1241 mvs_tfd_write(dev, ccb); 1242 /* Device reset doesn't interrupt. */ 1243 if (ccb->ataio.cmd.command == ATA_DEVICE_RESET) { 1244 int timeout = 1000000; 1245 do { 1246 DELAY(10); 1247 ccb->ataio.res.status = ATA_INB(ch->r_mem, ATA_STATUS); 1248 } while (ccb->ataio.res.status & ATA_S_BUSY && timeout--); 1249 mvs_legacy_intr(dev); 1250 return; 1251 } 1252 ch->donecount = 0; 1253 ch->transfersize = min(ccb->ataio.dxfer_len, 1254 ch->curr[port].bytecount); 1255 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) 1256 ch->fake_busy = 1; 1257 /* If data write command - output the data */ 1258 if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_OUT) { 1259 if (mvs_wait(dev, ATA_S_DRQ, ATA_S_BUSY, 1000) < 0) { 1260 device_printf(dev, "timeout waiting for write DRQ\n"); 1261 mvs_end_transaction(slot, MVS_ERR_TIMEOUT); 1262 return; 1263 } 1264 ATA_OUTSW_STRM(ch->r_mem, ATA_DATA, 1265 (uint16_t *)(ccb->ataio.data_ptr + ch->donecount), 1266 ch->transfersize / 2); 1267 } 1268 } else { 1269 // device_printf(dev, "%d ATAPI command %02x size %d dma %d\n", 1270 // port, ccb->csio.cdb_io.cdb_bytes[0], ccb->csio.dxfer_len, 1271 // ch->basic_dma); 1272 ch->donecount = 0; 1273 ch->transfersize = min(ccb->csio.dxfer_len, 1274 ch->curr[port].bytecount); 1275 /* Write ATA PACKET command. */ 1276 if (ch->basic_dma) { 1277 ATA_OUTB(ch->r_mem, ATA_FEATURE, ATA_F_DMA); 1278 ATA_OUTB(ch->r_mem, ATA_CYL_LSB, 0); 1279 ATA_OUTB(ch->r_mem, ATA_CYL_MSB, 0); 1280 } else { 1281 ATA_OUTB(ch->r_mem, ATA_FEATURE, 0); 1282 ATA_OUTB(ch->r_mem, ATA_CYL_LSB, ch->transfersize); 1283 ATA_OUTB(ch->r_mem, ATA_CYL_MSB, ch->transfersize >> 8); 1284 } 1285 ATA_OUTB(ch->r_mem, ATA_COMMAND, ATA_PACKET_CMD); 1286 ch->fake_busy = 1; 1287 /* Wait for ready to write ATAPI command block */ 1288 if (mvs_wait(dev, 0, ATA_S_BUSY, 1000) < 0) { 1289 device_printf(dev, "timeout waiting for ATAPI !BUSY\n"); 1290 mvs_end_transaction(slot, MVS_ERR_TIMEOUT); 1291 return; 1292 } 1293 timeout = 5000; 1294 while (timeout--) { 1295 int reason = ATA_INB(ch->r_mem, ATA_IREASON); 1296 int status = ATA_INB(ch->r_mem, ATA_STATUS); 1297 1298 if (((reason & (ATA_I_CMD | ATA_I_IN)) | 1299 (status & (ATA_S_DRQ | ATA_S_BUSY))) == ATAPI_P_CMDOUT) 1300 break; 1301 DELAY(20); 1302 } 1303 if (timeout <= 0) { 1304 device_printf(dev, "timeout waiting for ATAPI command ready\n"); 1305 mvs_end_transaction(slot, MVS_ERR_TIMEOUT); 1306 return; 1307 } 1308 /* Write ATAPI command. */ 1309 ATA_OUTSW_STRM(ch->r_mem, ATA_DATA, 1310 (uint16_t *)((ccb->ccb_h.flags & CAM_CDB_POINTER) ? 1311 ccb->csio.cdb_io.cdb_ptr : ccb->csio.cdb_io.cdb_bytes), 1312 ch->curr[port].atapi / 2); 1313 DELAY(10); 1314 if (ch->basic_dma) { 1315 /* Start basic DMA. */ 1316 eprd = ch->dma.workrq_bus + MVS_EPRD_OFFSET + 1317 (MVS_EPRD_SIZE * slot->slot); 1318 ATA_OUTL(ch->r_mem, DMA_DTLBA, eprd); 1319 ATA_OUTL(ch->r_mem, DMA_DTHBA, (eprd >> 16) >> 16); 1320 ATA_OUTL(ch->r_mem, DMA_C, DMA_C_START | 1321 (((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) ? 1322 DMA_C_READ : 0)); 1323 } else if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) 1324 ch->fake_busy = 1; 1325 } 1326 /* Start command execution timeout */ 1327 callout_reset(&slot->timeout, (int)ccb->ccb_h.timeout * hz / 1000, 1328 (timeout_t*)mvs_timeout, slot); 1329 } 1330 1331 /* Must be called with channel locked. */ 1332 static void 1333 mvs_execute_transaction(struct mvs_slot *slot) 1334 { 1335 device_t dev = slot->dev; 1336 struct mvs_channel *ch = device_get_softc(dev); 1337 bus_addr_t eprd; 1338 struct mvs_crqb *crqb; 1339 struct mvs_crqb_gen2e *crqb2e; 1340 union ccb *ccb = slot->ccb; 1341 int port = ccb->ccb_h.target_id & 0x0f; 1342 int i; 1343 1344 // device_printf(dev, "%d EDMA command %02x size %d slot %d tag %d\n", 1345 // port, ccb->ataio.cmd.command, ccb->ataio.dxfer_len, slot->slot, slot->tag); 1346 /* Get address of the prepared EPRD */ 1347 eprd = ch->dma.workrq_bus + MVS_EPRD_OFFSET + (MVS_EPRD_SIZE * slot->slot); 1348 /* Prepare CRQB. Gen IIe uses different CRQB format. */ 1349 if (ch->quirks & MVS_Q_GENIIE) { 1350 crqb2e = (struct mvs_crqb_gen2e *) 1351 (ch->dma.workrq + MVS_CRQB_OFFSET + (MVS_CRQB_SIZE * ch->out_idx)); 1352 crqb2e->ctrlflg = htole32( 1353 ((ccb->ccb_h.flags & CAM_DIR_IN) ? MVS_CRQB2E_READ : 0) | 1354 (slot->tag << MVS_CRQB2E_DTAG_SHIFT) | 1355 (port << MVS_CRQB2E_PMP_SHIFT) | 1356 (slot->slot << MVS_CRQB2E_HTAG_SHIFT)); 1357 /* If there is only one segment - no need to use S/G table. */ 1358 if (slot->dma.addr != 0) { 1359 eprd = slot->dma.addr; 1360 crqb2e->ctrlflg |= htole32(MVS_CRQB2E_CPRD); 1361 crqb2e->drbc = slot->dma.len; 1362 } 1363 crqb2e->cprdbl = htole32(eprd); 1364 crqb2e->cprdbh = htole32((eprd >> 16) >> 16); 1365 crqb2e->cmd[0] = 0; 1366 crqb2e->cmd[1] = 0; 1367 crqb2e->cmd[2] = ccb->ataio.cmd.command; 1368 crqb2e->cmd[3] = ccb->ataio.cmd.features; 1369 crqb2e->cmd[4] = ccb->ataio.cmd.lba_low; 1370 crqb2e->cmd[5] = ccb->ataio.cmd.lba_mid; 1371 crqb2e->cmd[6] = ccb->ataio.cmd.lba_high; 1372 crqb2e->cmd[7] = ccb->ataio.cmd.device; 1373 crqb2e->cmd[8] = ccb->ataio.cmd.lba_low_exp; 1374 crqb2e->cmd[9] = ccb->ataio.cmd.lba_mid_exp; 1375 crqb2e->cmd[10] = ccb->ataio.cmd.lba_high_exp; 1376 crqb2e->cmd[11] = ccb->ataio.cmd.features_exp; 1377 if (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) { 1378 crqb2e->cmd[12] = slot->tag << 3; 1379 crqb2e->cmd[13] = 0; 1380 } else { 1381 crqb2e->cmd[12] = ccb->ataio.cmd.sector_count; 1382 crqb2e->cmd[13] = ccb->ataio.cmd.sector_count_exp; 1383 } 1384 crqb2e->cmd[14] = 0; 1385 crqb2e->cmd[15] = 0; 1386 } else { 1387 crqb = (struct mvs_crqb *) 1388 (ch->dma.workrq + MVS_CRQB_OFFSET + (MVS_CRQB_SIZE * ch->out_idx)); 1389 crqb->cprdbl = htole32(eprd); 1390 crqb->cprdbh = htole32((eprd >> 16) >> 16); 1391 crqb->ctrlflg = htole16( 1392 ((ccb->ccb_h.flags & CAM_DIR_IN) ? MVS_CRQB_READ : 0) | 1393 (slot->slot << MVS_CRQB_TAG_SHIFT) | 1394 (port << MVS_CRQB_PMP_SHIFT)); 1395 i = 0; 1396 /* 1397 * Controller can handle only 11 of 12 ATA registers, 1398 * so we have to choose which one to skip. 1399 */ 1400 if (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) { 1401 crqb->cmd[i++] = ccb->ataio.cmd.features_exp; 1402 crqb->cmd[i++] = 0x11; 1403 } 1404 crqb->cmd[i++] = ccb->ataio.cmd.features; 1405 crqb->cmd[i++] = 0x11; 1406 if (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) { 1407 crqb->cmd[i++] = slot->tag << 3; 1408 crqb->cmd[i++] = 0x12; 1409 } else { 1410 crqb->cmd[i++] = ccb->ataio.cmd.sector_count_exp; 1411 crqb->cmd[i++] = 0x12; 1412 crqb->cmd[i++] = ccb->ataio.cmd.sector_count; 1413 crqb->cmd[i++] = 0x12; 1414 } 1415 crqb->cmd[i++] = ccb->ataio.cmd.lba_low_exp; 1416 crqb->cmd[i++] = 0x13; 1417 crqb->cmd[i++] = ccb->ataio.cmd.lba_low; 1418 crqb->cmd[i++] = 0x13; 1419 crqb->cmd[i++] = ccb->ataio.cmd.lba_mid_exp; 1420 crqb->cmd[i++] = 0x14; 1421 crqb->cmd[i++] = ccb->ataio.cmd.lba_mid; 1422 crqb->cmd[i++] = 0x14; 1423 crqb->cmd[i++] = ccb->ataio.cmd.lba_high_exp; 1424 crqb->cmd[i++] = 0x15; 1425 crqb->cmd[i++] = ccb->ataio.cmd.lba_high; 1426 crqb->cmd[i++] = 0x15; 1427 crqb->cmd[i++] = ccb->ataio.cmd.device; 1428 crqb->cmd[i++] = 0x16; 1429 crqb->cmd[i++] = ccb->ataio.cmd.command; 1430 crqb->cmd[i++] = 0x97; 1431 } 1432 bus_dmamap_sync(ch->dma.workrq_tag, ch->dma.workrq_map, 1433 BUS_DMASYNC_PREWRITE); 1434 bus_dmamap_sync(ch->dma.workrp_tag, ch->dma.workrp_map, 1435 BUS_DMASYNC_PREREAD); 1436 slot->state = MVS_SLOT_RUNNING; 1437 ch->rslots |= (1 << slot->slot); 1438 /* Issue command to the controller. */ 1439 ch->out_idx = (ch->out_idx + 1) & (MVS_MAX_SLOTS - 1); 1440 ATA_OUTL(ch->r_mem, EDMA_REQQIP, 1441 ch->dma.workrq_bus + MVS_CRQB_OFFSET + (MVS_CRQB_SIZE * ch->out_idx)); 1442 /* Start command execution timeout */ 1443 callout_reset(&slot->timeout, (int)ccb->ccb_h.timeout * hz / 1000, 1444 (timeout_t*)mvs_timeout, slot); 1445 return; 1446 } 1447 1448 /* Must be called with channel locked. */ 1449 static void 1450 mvs_process_timeout(device_t dev) 1451 { 1452 struct mvs_channel *ch = device_get_softc(dev); 1453 int i; 1454 1455 mtx_assert(&ch->mtx, MA_OWNED); 1456 /* Handle the rest of commands. */ 1457 for (i = 0; i < MVS_MAX_SLOTS; i++) { 1458 /* Do we have a running request on slot? */ 1459 if (ch->slot[i].state < MVS_SLOT_RUNNING) 1460 continue; 1461 mvs_end_transaction(&ch->slot[i], MVS_ERR_TIMEOUT); 1462 } 1463 } 1464 1465 /* Must be called with channel locked. */ 1466 static void 1467 mvs_rearm_timeout(device_t dev) 1468 { 1469 struct mvs_channel *ch = device_get_softc(dev); 1470 int i; 1471 1472 mtx_assert(&ch->mtx, MA_OWNED); 1473 for (i = 0; i < MVS_MAX_SLOTS; i++) { 1474 struct mvs_slot *slot = &ch->slot[i]; 1475 1476 /* Do we have a running request on slot? */ 1477 if (slot->state < MVS_SLOT_RUNNING) 1478 continue; 1479 if ((ch->toslots & (1 << i)) == 0) 1480 continue; 1481 callout_reset(&slot->timeout, 1482 (int)slot->ccb->ccb_h.timeout * hz / 2000, 1483 (timeout_t*)mvs_timeout, slot); 1484 } 1485 } 1486 1487 /* Locked by callout mechanism. */ 1488 static void 1489 mvs_timeout(struct mvs_slot *slot) 1490 { 1491 device_t dev = slot->dev; 1492 struct mvs_channel *ch = device_get_softc(dev); 1493 1494 /* Check for stale timeout. */ 1495 if (slot->state < MVS_SLOT_RUNNING) 1496 return; 1497 device_printf(dev, "Timeout on slot %d\n", slot->slot); 1498 device_printf(dev, "iec %08x sstat %08x serr %08x edma_s %08x " 1499 "dma_c %08x dma_s %08x rs %08x status %02x\n", 1500 ATA_INL(ch->r_mem, EDMA_IEC), 1501 ATA_INL(ch->r_mem, SATA_SS), ATA_INL(ch->r_mem, SATA_SE), 1502 ATA_INL(ch->r_mem, EDMA_S), ATA_INL(ch->r_mem, DMA_C), 1503 ATA_INL(ch->r_mem, DMA_S), ch->rslots, 1504 ATA_INB(ch->r_mem, ATA_ALTSTAT)); 1505 /* Handle frozen command. */ 1506 mvs_requeue_frozen(dev); 1507 /* We wait for other commands timeout and pray. */ 1508 if (ch->toslots == 0) 1509 xpt_freeze_simq(ch->sim, 1); 1510 ch->toslots |= (1 << slot->slot); 1511 if ((ch->rslots & ~ch->toslots) == 0) 1512 mvs_process_timeout(dev); 1513 else 1514 device_printf(dev, " ... waiting for slots %08x\n", 1515 ch->rslots & ~ch->toslots); 1516 } 1517 1518 /* Must be called with channel locked. */ 1519 static void 1520 mvs_end_transaction(struct mvs_slot *slot, enum mvs_err_type et) 1521 { 1522 device_t dev = slot->dev; 1523 struct mvs_channel *ch = device_get_softc(dev); 1524 union ccb *ccb = slot->ccb; 1525 1526 //device_printf(dev, "cmd done status %d\n", et); 1527 bus_dmamap_sync(ch->dma.workrq_tag, ch->dma.workrq_map, 1528 BUS_DMASYNC_POSTWRITE); 1529 /* Read result registers to the result struct 1530 * May be incorrect if several commands finished same time, 1531 * so read only when sure or have to. 1532 */ 1533 if (ccb->ccb_h.func_code == XPT_ATA_IO) { 1534 struct ata_res *res = &ccb->ataio.res; 1535 1536 if ((et == MVS_ERR_TFE) || 1537 (ccb->ataio.cmd.flags & CAM_ATAIO_NEEDRESULT)) { 1538 mvs_tfd_read(dev, ccb); 1539 } else 1540 bzero(res, sizeof(*res)); 1541 } 1542 if (ch->numpslots == 0 || ch->basic_dma) { 1543 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 1544 bus_dmamap_sync(ch->dma.data_tag, slot->dma.data_map, 1545 (ccb->ccb_h.flags & CAM_DIR_IN) ? 1546 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1547 bus_dmamap_unload(ch->dma.data_tag, slot->dma.data_map); 1548 } 1549 } 1550 if (et != MVS_ERR_NONE) 1551 ch->eslots |= (1 << slot->slot); 1552 /* In case of error, freeze device for proper recovery. */ 1553 if ((et != MVS_ERR_NONE) && (!ch->readlog) && 1554 !(ccb->ccb_h.status & CAM_DEV_QFRZN)) { 1555 xpt_freeze_devq(ccb->ccb_h.path, 1); 1556 ccb->ccb_h.status |= CAM_DEV_QFRZN; 1557 } 1558 /* Set proper result status. */ 1559 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 1560 switch (et) { 1561 case MVS_ERR_NONE: 1562 ccb->ccb_h.status |= CAM_REQ_CMP; 1563 if (ccb->ccb_h.func_code == XPT_SCSI_IO) 1564 ccb->csio.scsi_status = SCSI_STATUS_OK; 1565 break; 1566 case MVS_ERR_INVALID: 1567 ch->fatalerr = 1; 1568 ccb->ccb_h.status |= CAM_REQ_INVALID; 1569 break; 1570 case MVS_ERR_INNOCENT: 1571 ccb->ccb_h.status |= CAM_REQUEUE_REQ; 1572 break; 1573 case MVS_ERR_TFE: 1574 case MVS_ERR_NCQ: 1575 if (ccb->ccb_h.func_code == XPT_SCSI_IO) { 1576 ccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR; 1577 ccb->csio.scsi_status = SCSI_STATUS_CHECK_COND; 1578 } else { 1579 ccb->ccb_h.status |= CAM_ATA_STATUS_ERROR; 1580 } 1581 break; 1582 case MVS_ERR_SATA: 1583 ch->fatalerr = 1; 1584 if (!ch->readlog) { 1585 xpt_freeze_simq(ch->sim, 1); 1586 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 1587 ccb->ccb_h.status |= CAM_RELEASE_SIMQ; 1588 } 1589 ccb->ccb_h.status |= CAM_UNCOR_PARITY; 1590 break; 1591 case MVS_ERR_TIMEOUT: 1592 if (!ch->readlog) { 1593 xpt_freeze_simq(ch->sim, 1); 1594 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 1595 ccb->ccb_h.status |= CAM_RELEASE_SIMQ; 1596 } 1597 ccb->ccb_h.status |= CAM_CMD_TIMEOUT; 1598 break; 1599 default: 1600 ch->fatalerr = 1; 1601 ccb->ccb_h.status |= CAM_REQ_CMP_ERR; 1602 } 1603 /* Free slot. */ 1604 ch->oslots &= ~(1 << slot->slot); 1605 ch->rslots &= ~(1 << slot->slot); 1606 ch->aslots &= ~(1 << slot->slot); 1607 if (et != MVS_ERR_TIMEOUT) { 1608 if (ch->toslots == (1 << slot->slot)) 1609 xpt_release_simq(ch->sim, TRUE); 1610 ch->toslots &= ~(1 << slot->slot); 1611 } 1612 slot->state = MVS_SLOT_EMPTY; 1613 slot->ccb = NULL; 1614 /* Update channel stats. */ 1615 ch->numrslots--; 1616 ch->numrslotspd[ccb->ccb_h.target_id]--; 1617 if (ccb->ccb_h.func_code == XPT_ATA_IO) { 1618 if (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) { 1619 ch->otagspd[ccb->ccb_h.target_id] &= ~(1 << slot->tag); 1620 ch->numtslots--; 1621 ch->numtslotspd[ccb->ccb_h.target_id]--; 1622 } else if (ccb->ataio.cmd.flags & CAM_ATAIO_DMA) { 1623 ch->numdslots--; 1624 } else { 1625 ch->numpslots--; 1626 } 1627 } else { 1628 ch->numpslots--; 1629 ch->basic_dma = 0; 1630 } 1631 /* If it was our READ LOG command - process it. */ 1632 if (ch->readlog) { 1633 mvs_process_read_log(dev, ccb); 1634 /* If it was NCQ command error, put result on hold. */ 1635 } else if (et == MVS_ERR_NCQ) { 1636 ch->hold[slot->slot] = ccb; 1637 ch->holdtag[slot->slot] = slot->tag; 1638 ch->numhslots++; 1639 } else 1640 xpt_done(ccb); 1641 /* Unfreeze frozen command. */ 1642 if (ch->frozen && !mvs_check_collision(dev, ch->frozen)) { 1643 union ccb *fccb = ch->frozen; 1644 ch->frozen = NULL; 1645 mvs_begin_transaction(dev, fccb); 1646 xpt_release_simq(ch->sim, TRUE); 1647 } 1648 /* If we have no other active commands, ... */ 1649 if (ch->rslots == 0) { 1650 /* if there was fatal error - reset port. */ 1651 if (ch->toslots != 0 || ch->fatalerr) { 1652 mvs_reset(dev); 1653 } else { 1654 /* if we have slots in error, we can reinit port. */ 1655 if (ch->eslots != 0) { 1656 mvs_set_edma_mode(dev, MVS_EDMA_OFF); 1657 ch->eslots = 0; 1658 } 1659 /* if there commands on hold, we can do READ LOG. */ 1660 if (!ch->readlog && ch->numhslots) 1661 mvs_issue_read_log(dev); 1662 } 1663 /* If all the rest of commands are in timeout - give them chance. */ 1664 } else if ((ch->rslots & ~ch->toslots) == 0 && 1665 et != MVS_ERR_TIMEOUT) 1666 mvs_rearm_timeout(dev); 1667 /* Start PM timer. */ 1668 if (ch->numrslots == 0 && ch->pm_level > 3 && 1669 (ch->curr[ch->pm_present ? 15 : 0].caps & CTS_SATA_CAPS_D_PMREQ)) { 1670 callout_schedule(&ch->pm_timer, 1671 (ch->pm_level == 4) ? hz / 1000 : hz / 8); 1672 } 1673 } 1674 1675 static void 1676 mvs_issue_read_log(device_t dev) 1677 { 1678 struct mvs_channel *ch = device_get_softc(dev); 1679 union ccb *ccb; 1680 struct ccb_ataio *ataio; 1681 int i; 1682 1683 ch->readlog = 1; 1684 /* Find some holden command. */ 1685 for (i = 0; i < MVS_MAX_SLOTS; i++) { 1686 if (ch->hold[i]) 1687 break; 1688 } 1689 ccb = xpt_alloc_ccb_nowait(); 1690 if (ccb == NULL) { 1691 device_printf(dev, "Unable allocate READ LOG command"); 1692 return; /* XXX */ 1693 } 1694 ccb->ccb_h = ch->hold[i]->ccb_h; /* Reuse old header. */ 1695 ccb->ccb_h.func_code = XPT_ATA_IO; 1696 ccb->ccb_h.flags = CAM_DIR_IN; 1697 ccb->ccb_h.timeout = 1000; /* 1s should be enough. */ 1698 ataio = &ccb->ataio; 1699 ataio->data_ptr = malloc(512, M_MVS, M_NOWAIT); 1700 if (ataio->data_ptr == NULL) { 1701 device_printf(dev, "Unable allocate memory for READ LOG command"); 1702 return; /* XXX */ 1703 } 1704 ataio->dxfer_len = 512; 1705 bzero(&ataio->cmd, sizeof(ataio->cmd)); 1706 ataio->cmd.flags = CAM_ATAIO_48BIT; 1707 ataio->cmd.command = 0x2F; /* READ LOG EXT */ 1708 ataio->cmd.sector_count = 1; 1709 ataio->cmd.sector_count_exp = 0; 1710 ataio->cmd.lba_low = 0x10; 1711 ataio->cmd.lba_mid = 0; 1712 ataio->cmd.lba_mid_exp = 0; 1713 /* Freeze SIM while doing READ LOG EXT. */ 1714 xpt_freeze_simq(ch->sim, 1); 1715 mvs_begin_transaction(dev, ccb); 1716 } 1717 1718 static void 1719 mvs_process_read_log(device_t dev, union ccb *ccb) 1720 { 1721 struct mvs_channel *ch = device_get_softc(dev); 1722 uint8_t *data; 1723 struct ata_res *res; 1724 int i; 1725 1726 ch->readlog = 0; 1727 1728 data = ccb->ataio.data_ptr; 1729 if ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_CMP && 1730 (data[0] & 0x80) == 0) { 1731 for (i = 0; i < MVS_MAX_SLOTS; i++) { 1732 if (!ch->hold[i]) 1733 continue; 1734 if (ch->hold[i]->ccb_h.target_id != ccb->ccb_h.target_id) 1735 continue; 1736 if ((data[0] & 0x1F) == ch->holdtag[i]) { 1737 res = &ch->hold[i]->ataio.res; 1738 res->status = data[2]; 1739 res->error = data[3]; 1740 res->lba_low = data[4]; 1741 res->lba_mid = data[5]; 1742 res->lba_high = data[6]; 1743 res->device = data[7]; 1744 res->lba_low_exp = data[8]; 1745 res->lba_mid_exp = data[9]; 1746 res->lba_high_exp = data[10]; 1747 res->sector_count = data[12]; 1748 res->sector_count_exp = data[13]; 1749 } else { 1750 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK; 1751 ch->hold[i]->ccb_h.status |= CAM_REQUEUE_REQ; 1752 } 1753 xpt_done(ch->hold[i]); 1754 ch->hold[i] = NULL; 1755 ch->numhslots--; 1756 } 1757 } else { 1758 if ((ccb->ccb_h.status & CAM_STATUS_MASK) != CAM_REQ_CMP) 1759 device_printf(dev, "Error while READ LOG EXT\n"); 1760 else if ((data[0] & 0x80) == 0) { 1761 device_printf(dev, "Non-queued command error in READ LOG EXT\n"); 1762 } 1763 for (i = 0; i < MVS_MAX_SLOTS; i++) { 1764 if (!ch->hold[i]) 1765 continue; 1766 if (ch->hold[i]->ccb_h.target_id != ccb->ccb_h.target_id) 1767 continue; 1768 xpt_done(ch->hold[i]); 1769 ch->hold[i] = NULL; 1770 ch->numhslots--; 1771 } 1772 } 1773 free(ccb->ataio.data_ptr, M_MVS); 1774 xpt_free_ccb(ccb); 1775 xpt_release_simq(ch->sim, TRUE); 1776 } 1777 1778 static int 1779 mvs_wait(device_t dev, u_int s, u_int c, int t) 1780 { 1781 int timeout = 0; 1782 uint8_t st; 1783 1784 while (((st = mvs_getstatus(dev, 0)) & (s | c)) != s) { 1785 DELAY(1000); 1786 if (timeout++ > t) { 1787 device_printf(dev, "Wait status %02x\n", st); 1788 return (-1); 1789 } 1790 } 1791 return (timeout); 1792 } 1793 1794 static void 1795 mvs_requeue_frozen(device_t dev) 1796 { 1797 struct mvs_channel *ch = device_get_softc(dev); 1798 union ccb *fccb = ch->frozen; 1799 1800 if (fccb) { 1801 ch->frozen = NULL; 1802 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ; 1803 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) { 1804 xpt_freeze_devq(fccb->ccb_h.path, 1); 1805 fccb->ccb_h.status |= CAM_DEV_QFRZN; 1806 } 1807 xpt_done(fccb); 1808 } 1809 } 1810 1811 static void 1812 mvs_reset(device_t dev) 1813 { 1814 struct mvs_channel *ch = device_get_softc(dev); 1815 int i; 1816 1817 xpt_freeze_simq(ch->sim, 1); 1818 if (bootverbose) 1819 device_printf(dev, "MVS reset...\n"); 1820 /* Requeue freezed command. */ 1821 mvs_requeue_frozen(dev); 1822 /* Kill the engine and requeue all running commands. */ 1823 mvs_set_edma_mode(dev, MVS_EDMA_OFF); 1824 ATA_OUTL(ch->r_mem, DMA_C, 0); 1825 for (i = 0; i < MVS_MAX_SLOTS; i++) { 1826 /* Do we have a running request on slot? */ 1827 if (ch->slot[i].state < MVS_SLOT_RUNNING) 1828 continue; 1829 /* XXX; Commands in loading state. */ 1830 mvs_end_transaction(&ch->slot[i], MVS_ERR_INNOCENT); 1831 } 1832 for (i = 0; i < MVS_MAX_SLOTS; i++) { 1833 if (!ch->hold[i]) 1834 continue; 1835 xpt_done(ch->hold[i]); 1836 ch->hold[i] = NULL; 1837 ch->numhslots--; 1838 } 1839 if (ch->toslots != 0) 1840 xpt_release_simq(ch->sim, TRUE); 1841 ch->eslots = 0; 1842 ch->toslots = 0; 1843 ch->fatalerr = 0; 1844 /* Tell the XPT about the event */ 1845 xpt_async(AC_BUS_RESET, ch->path, NULL); 1846 ATA_OUTL(ch->r_mem, EDMA_IEM, 0); 1847 ATA_OUTL(ch->r_mem, EDMA_CMD, EDMA_CMD_EATARST); 1848 DELAY(25); 1849 ATA_OUTL(ch->r_mem, EDMA_CMD, 0); 1850 /* Reset and reconnect PHY, */ 1851 if (!mvs_sata_phy_reset(dev)) { 1852 if (bootverbose) 1853 device_printf(dev, 1854 "MVS reset done: phy reset found no device\n"); 1855 ch->devices = 0; 1856 ATA_OUTL(ch->r_mem, SATA_SE, 0xffffffff); 1857 ATA_OUTL(ch->r_mem, EDMA_IEC, 0); 1858 ATA_OUTL(ch->r_mem, EDMA_IEM, ~EDMA_IE_TRANSIENT); 1859 xpt_release_simq(ch->sim, TRUE); 1860 return; 1861 } 1862 /* Wait for clearing busy status. */ 1863 if ((i = mvs_wait(dev, 0, ATA_S_BUSY | ATA_S_DRQ, 15000)) < 0) 1864 device_printf(dev, "device is not ready\n"); 1865 else if (bootverbose) 1866 device_printf(dev, "ready wait time=%dms\n", i); 1867 ch->devices = 1; 1868 ATA_OUTL(ch->r_mem, SATA_SE, 0xffffffff); 1869 ATA_OUTL(ch->r_mem, EDMA_IEC, 0); 1870 ATA_OUTL(ch->r_mem, EDMA_IEM, ~EDMA_IE_TRANSIENT); 1871 if (bootverbose) 1872 device_printf(dev, "MVS reset done: device found\n"); 1873 xpt_release_simq(ch->sim, TRUE); 1874 } 1875 1876 static void 1877 mvs_softreset(device_t dev, union ccb *ccb) 1878 { 1879 struct mvs_channel *ch = device_get_softc(dev); 1880 int port = ccb->ccb_h.target_id & 0x0f; 1881 int i; 1882 1883 mvs_set_edma_mode(dev, MVS_EDMA_OFF); 1884 ATA_OUTB(ch->r_mem, SATA_SATAICTL, port << SATA_SATAICTL_PMPTX_SHIFT); 1885 ATA_OUTB(ch->r_mem, ATA_CONTROL, ATA_A_RESET); 1886 DELAY(10000); 1887 ATA_OUTB(ch->r_mem, ATA_CONTROL, 0); 1888 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 1889 /* Wait for clearing busy status. */ 1890 if ((i = mvs_wait(dev, 0, ATA_S_BUSY | ATA_S_DRQ, ccb->ccb_h.timeout)) < 0) { 1891 ccb->ccb_h.status |= CAM_CMD_TIMEOUT; 1892 } else { 1893 ccb->ccb_h.status |= CAM_REQ_CMP; 1894 } 1895 mvs_tfd_read(dev, ccb); 1896 xpt_done(ccb); 1897 } 1898 1899 static int 1900 mvs_sata_connect(struct mvs_channel *ch) 1901 { 1902 u_int32_t status; 1903 int timeout; 1904 1905 /* Wait up to 100ms for "connect well" */ 1906 for (timeout = 0; timeout < 100 ; timeout++) { 1907 status = ATA_INL(ch->r_mem, SATA_SS); 1908 if (((status & SATA_SS_DET_MASK) == SATA_SS_DET_PHY_ONLINE) && 1909 ((status & SATA_SS_SPD_MASK) != SATA_SS_SPD_NO_SPEED) && 1910 ((status & SATA_SS_IPM_MASK) == SATA_SS_IPM_ACTIVE)) 1911 break; 1912 if ((status & SATA_SS_DET_MASK) == SATA_SS_DET_PHY_OFFLINE) { 1913 if (bootverbose) { 1914 device_printf(ch->dev, "SATA offline status=%08x\n", 1915 status); 1916 } 1917 return (0); 1918 } 1919 DELAY(1000); 1920 } 1921 if (timeout >= 100) { 1922 if (bootverbose) { 1923 device_printf(ch->dev, "SATA connect timeout status=%08x\n", 1924 status); 1925 } 1926 return (0); 1927 } 1928 if (bootverbose) { 1929 device_printf(ch->dev, "SATA connect time=%dms status=%08x\n", 1930 timeout, status); 1931 } 1932 /* Clear SATA error register */ 1933 ATA_OUTL(ch->r_mem, SATA_SE, 0xffffffff); 1934 return (1); 1935 } 1936 1937 static int 1938 mvs_sata_phy_reset(device_t dev) 1939 { 1940 struct mvs_channel *ch = device_get_softc(dev); 1941 int sata_rev; 1942 uint32_t val; 1943 1944 sata_rev = ch->user[ch->pm_present ? 15 : 0].revision; 1945 if (sata_rev == 1) 1946 val = SATA_SC_SPD_SPEED_GEN1; 1947 else if (sata_rev == 2) 1948 val = SATA_SC_SPD_SPEED_GEN2; 1949 else if (sata_rev == 3) 1950 val = SATA_SC_SPD_SPEED_GEN3; 1951 else 1952 val = 0; 1953 ATA_OUTL(ch->r_mem, SATA_SC, 1954 SATA_SC_DET_RESET | val | 1955 SATA_SC_IPM_DIS_PARTIAL | SATA_SC_IPM_DIS_SLUMBER); 1956 DELAY(5000); 1957 ATA_OUTL(ch->r_mem, SATA_SC, 1958 SATA_SC_DET_IDLE | val | ((ch->pm_level > 0) ? 0 : 1959 (SATA_SC_IPM_DIS_PARTIAL | SATA_SC_IPM_DIS_SLUMBER))); 1960 DELAY(5000); 1961 if (!mvs_sata_connect(ch)) { 1962 if (ch->pm_level > 0) 1963 ATA_OUTL(ch->r_mem, SATA_SC, SATA_SC_DET_DISABLE); 1964 return (0); 1965 } 1966 return (1); 1967 } 1968 1969 static int 1970 mvs_check_ids(device_t dev, union ccb *ccb) 1971 { 1972 struct mvs_channel *ch = device_get_softc(dev); 1973 1974 if (ccb->ccb_h.target_id > ((ch->quirks & MVS_Q_GENI) ? 0 : 15)) { 1975 ccb->ccb_h.status = CAM_TID_INVALID; 1976 xpt_done(ccb); 1977 return (-1); 1978 } 1979 if (ccb->ccb_h.target_lun != 0) { 1980 ccb->ccb_h.status = CAM_LUN_INVALID; 1981 xpt_done(ccb); 1982 return (-1); 1983 } 1984 return (0); 1985 } 1986 1987 static void 1988 mvsaction(struct cam_sim *sim, union ccb *ccb) 1989 { 1990 device_t dev; 1991 struct mvs_channel *ch; 1992 1993 CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_TRACE, ("mvsaction func_code=%x\n", 1994 ccb->ccb_h.func_code)); 1995 1996 ch = (struct mvs_channel *)cam_sim_softc(sim); 1997 dev = ch->dev; 1998 switch (ccb->ccb_h.func_code) { 1999 /* Common cases first */ 2000 case XPT_ATA_IO: /* Execute the requested I/O operation */ 2001 case XPT_SCSI_IO: 2002 if (mvs_check_ids(dev, ccb)) 2003 return; 2004 if (ch->devices == 0 || 2005 (ch->pm_present == 0 && 2006 ccb->ccb_h.target_id > 0 && ccb->ccb_h.target_id < 15)) { 2007 ccb->ccb_h.status = CAM_SEL_TIMEOUT; 2008 break; 2009 } 2010 /* Check for command collision. */ 2011 if (mvs_check_collision(dev, ccb)) { 2012 /* Freeze command. */ 2013 ch->frozen = ccb; 2014 /* We have only one frozen slot, so freeze simq also. */ 2015 xpt_freeze_simq(ch->sim, 1); 2016 return; 2017 } 2018 mvs_begin_transaction(dev, ccb); 2019 return; 2020 case XPT_EN_LUN: /* Enable LUN as a target */ 2021 case XPT_TARGET_IO: /* Execute target I/O request */ 2022 case XPT_ACCEPT_TARGET_IO: /* Accept Host Target Mode CDB */ 2023 case XPT_CONT_TARGET_IO: /* Continue Host Target I/O Connection*/ 2024 case XPT_ABORT: /* Abort the specified CCB */ 2025 /* XXX Implement */ 2026 ccb->ccb_h.status = CAM_REQ_INVALID; 2027 break; 2028 case XPT_SET_TRAN_SETTINGS: 2029 { 2030 struct ccb_trans_settings *cts = &ccb->cts; 2031 struct mvs_device *d; 2032 2033 if (mvs_check_ids(dev, ccb)) 2034 return; 2035 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) 2036 d = &ch->curr[ccb->ccb_h.target_id]; 2037 else 2038 d = &ch->user[ccb->ccb_h.target_id]; 2039 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_REVISION) 2040 d->revision = cts->xport_specific.sata.revision; 2041 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_MODE) 2042 d->mode = cts->xport_specific.sata.mode; 2043 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_BYTECOUNT) { 2044 d->bytecount = min((ch->quirks & MVS_Q_GENIIE) ? 8192 : 2048, 2045 cts->xport_specific.sata.bytecount); 2046 } 2047 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_TAGS) 2048 d->tags = min(MVS_MAX_SLOTS, cts->xport_specific.sata.tags); 2049 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_PM) 2050 ch->pm_present = cts->xport_specific.sata.pm_present; 2051 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_ATAPI) 2052 d->atapi = cts->xport_specific.sata.atapi; 2053 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_CAPS) 2054 d->caps = cts->xport_specific.sata.caps; 2055 ccb->ccb_h.status = CAM_REQ_CMP; 2056 break; 2057 } 2058 case XPT_GET_TRAN_SETTINGS: 2059 /* Get default/user set transfer settings for the target */ 2060 { 2061 struct ccb_trans_settings *cts = &ccb->cts; 2062 struct mvs_device *d; 2063 uint32_t status; 2064 2065 if (mvs_check_ids(dev, ccb)) 2066 return; 2067 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) 2068 d = &ch->curr[ccb->ccb_h.target_id]; 2069 else 2070 d = &ch->user[ccb->ccb_h.target_id]; 2071 cts->protocol = PROTO_ATA; 2072 cts->protocol_version = PROTO_VERSION_UNSPECIFIED; 2073 cts->transport = XPORT_SATA; 2074 cts->transport_version = XPORT_VERSION_UNSPECIFIED; 2075 cts->proto_specific.valid = 0; 2076 cts->xport_specific.sata.valid = 0; 2077 if (cts->type == CTS_TYPE_CURRENT_SETTINGS && 2078 (ccb->ccb_h.target_id == 15 || 2079 (ccb->ccb_h.target_id == 0 && !ch->pm_present))) { 2080 status = ATA_INL(ch->r_mem, SATA_SS) & SATA_SS_SPD_MASK; 2081 if (status & 0x0f0) { 2082 cts->xport_specific.sata.revision = 2083 (status & 0x0f0) >> 4; 2084 cts->xport_specific.sata.valid |= 2085 CTS_SATA_VALID_REVISION; 2086 } 2087 cts->xport_specific.sata.caps = d->caps & CTS_SATA_CAPS_D; 2088 // if (ch->pm_level) 2089 // cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_PMREQ; 2090 cts->xport_specific.sata.caps &= 2091 ch->user[ccb->ccb_h.target_id].caps; 2092 cts->xport_specific.sata.valid |= CTS_SATA_VALID_CAPS; 2093 } else { 2094 cts->xport_specific.sata.revision = d->revision; 2095 cts->xport_specific.sata.valid |= CTS_SATA_VALID_REVISION; 2096 cts->xport_specific.sata.caps = d->caps; 2097 cts->xport_specific.sata.valid |= CTS_SATA_VALID_CAPS; 2098 } 2099 cts->xport_specific.sata.mode = d->mode; 2100 cts->xport_specific.sata.valid |= CTS_SATA_VALID_MODE; 2101 cts->xport_specific.sata.bytecount = d->bytecount; 2102 cts->xport_specific.sata.valid |= CTS_SATA_VALID_BYTECOUNT; 2103 cts->xport_specific.sata.pm_present = ch->pm_present; 2104 cts->xport_specific.sata.valid |= CTS_SATA_VALID_PM; 2105 cts->xport_specific.sata.tags = d->tags; 2106 cts->xport_specific.sata.valid |= CTS_SATA_VALID_TAGS; 2107 cts->xport_specific.sata.atapi = d->atapi; 2108 cts->xport_specific.sata.valid |= CTS_SATA_VALID_ATAPI; 2109 ccb->ccb_h.status = CAM_REQ_CMP; 2110 break; 2111 } 2112 case XPT_RESET_BUS: /* Reset the specified SCSI bus */ 2113 case XPT_RESET_DEV: /* Bus Device Reset the specified SCSI device */ 2114 mvs_reset(dev); 2115 ccb->ccb_h.status = CAM_REQ_CMP; 2116 break; 2117 case XPT_TERM_IO: /* Terminate the I/O process */ 2118 /* XXX Implement */ 2119 ccb->ccb_h.status = CAM_REQ_INVALID; 2120 break; 2121 case XPT_PATH_INQ: /* Path routing inquiry */ 2122 { 2123 struct ccb_pathinq *cpi = &ccb->cpi; 2124 2125 cpi->version_num = 1; /* XXX??? */ 2126 cpi->hba_inquiry = PI_SDTR_ABLE; 2127 if (!(ch->quirks & MVS_Q_GENI)) { 2128 cpi->hba_inquiry |= PI_SATAPM; 2129 /* Gen-II is extremely slow with NCQ on PMP. */ 2130 if ((ch->quirks & MVS_Q_GENIIE) || ch->pm_present == 0) 2131 cpi->hba_inquiry |= PI_TAG_ABLE; 2132 } 2133 cpi->target_sprt = 0; 2134 cpi->hba_misc = PIM_SEQSCAN; 2135 cpi->hba_eng_cnt = 0; 2136 if (!(ch->quirks & MVS_Q_GENI)) 2137 cpi->max_target = 15; 2138 else 2139 cpi->max_target = 0; 2140 cpi->max_lun = 0; 2141 cpi->initiator_id = 0; 2142 cpi->bus_id = cam_sim_bus(sim); 2143 cpi->base_transfer_speed = 150000; 2144 strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN); 2145 strncpy(cpi->hba_vid, "Marvell", HBA_IDLEN); 2146 strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN); 2147 cpi->unit_number = cam_sim_unit(sim); 2148 cpi->transport = XPORT_SATA; 2149 cpi->transport_version = XPORT_VERSION_UNSPECIFIED; 2150 cpi->protocol = PROTO_ATA; 2151 cpi->protocol_version = PROTO_VERSION_UNSPECIFIED; 2152 cpi->maxio = MAXPHYS; 2153 cpi->ccb_h.status = CAM_REQ_CMP; 2154 break; 2155 } 2156 default: 2157 ccb->ccb_h.status = CAM_REQ_INVALID; 2158 break; 2159 } 2160 xpt_done(ccb); 2161 } 2162 2163 static void 2164 mvspoll(struct cam_sim *sim) 2165 { 2166 struct mvs_channel *ch = (struct mvs_channel *)cam_sim_softc(sim); 2167 struct mvs_intr_arg arg; 2168 2169 arg.arg = ch->dev; 2170 arg.cause = 2; /* XXX */ 2171 mvs_ch_intr(arg.arg); 2172 } 2173 2174