1 /*- 2 * Copyright (c) 2010 Alexander Motin <mav@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include <sys/param.h> 31 #include <sys/module.h> 32 #include <sys/systm.h> 33 #include <sys/kernel.h> 34 #include <sys/ata.h> 35 #include <sys/bus.h> 36 #include <sys/endian.h> 37 #include <sys/malloc.h> 38 #include <sys/lock.h> 39 #include <sys/mutex.h> 40 #include <vm/uma.h> 41 #include <machine/stdarg.h> 42 #include <machine/resource.h> 43 #include <machine/bus.h> 44 #include <sys/rman.h> 45 #include <dev/pci/pcivar.h> 46 #include "mvs.h" 47 48 #include <cam/cam.h> 49 #include <cam/cam_ccb.h> 50 #include <cam/cam_sim.h> 51 #include <cam/cam_xpt_sim.h> 52 #include <cam/cam_debug.h> 53 54 /* local prototypes */ 55 static int mvs_ch_init(device_t dev); 56 static int mvs_ch_deinit(device_t dev); 57 static int mvs_ch_suspend(device_t dev); 58 static int mvs_ch_resume(device_t dev); 59 static void mvs_dmainit(device_t dev); 60 static void mvs_dmasetupc_cb(void *xsc, bus_dma_segment_t *segs, int nsegs, int error); 61 static void mvs_dmafini(device_t dev); 62 static void mvs_slotsalloc(device_t dev); 63 static void mvs_slotsfree(device_t dev); 64 static void mvs_setup_edma_queues(device_t dev); 65 static void mvs_set_edma_mode(device_t dev, enum mvs_edma_mode mode); 66 static void mvs_ch_pm(void *arg); 67 static void mvs_ch_intr_locked(void *data); 68 static void mvs_ch_intr(void *data); 69 static void mvs_reset(device_t dev); 70 static void mvs_softreset(device_t dev, union ccb *ccb); 71 72 static int mvs_sata_connect(struct mvs_channel *ch); 73 static int mvs_sata_phy_reset(device_t dev); 74 static int mvs_wait(device_t dev, u_int s, u_int c, int t); 75 static void mvs_tfd_read(device_t dev, union ccb *ccb); 76 static void mvs_tfd_write(device_t dev, union ccb *ccb); 77 static void mvs_legacy_intr(device_t dev); 78 static void mvs_crbq_intr(device_t dev); 79 static void mvs_begin_transaction(device_t dev, union ccb *ccb); 80 static void mvs_legacy_execute_transaction(struct mvs_slot *slot); 81 static void mvs_timeout(struct mvs_slot *slot); 82 static void mvs_dmasetprd(void *arg, bus_dma_segment_t *segs, int nsegs, int error); 83 static void mvs_requeue_frozen(device_t dev); 84 static void mvs_execute_transaction(struct mvs_slot *slot); 85 static void mvs_end_transaction(struct mvs_slot *slot, enum mvs_err_type et); 86 87 static void mvs_issue_read_log(device_t dev); 88 static void mvs_process_read_log(device_t dev, union ccb *ccb); 89 90 static void mvsaction(struct cam_sim *sim, union ccb *ccb); 91 static void mvspoll(struct cam_sim *sim); 92 93 MALLOC_DEFINE(M_MVS, "MVS driver", "MVS driver data buffers"); 94 95 static int 96 mvs_ch_probe(device_t dev) 97 { 98 99 device_set_desc_copy(dev, "Marvell SATA channel"); 100 return (0); 101 } 102 103 static int 104 mvs_ch_attach(device_t dev) 105 { 106 struct mvs_controller *ctlr = device_get_softc(device_get_parent(dev)); 107 struct mvs_channel *ch = device_get_softc(dev); 108 struct cam_devq *devq; 109 int rid, error, i, sata_rev = 0; 110 111 ch->dev = dev; 112 ch->unit = (intptr_t)device_get_ivars(dev); 113 ch->quirks = ctlr->quirks; 114 mtx_init(&ch->mtx, "MVS channel lock", NULL, MTX_DEF); 115 resource_int_value(device_get_name(dev), 116 device_get_unit(dev), "pm_level", &ch->pm_level); 117 if (ch->pm_level > 3) 118 callout_init_mtx(&ch->pm_timer, &ch->mtx, 0); 119 resource_int_value(device_get_name(dev), 120 device_get_unit(dev), "sata_rev", &sata_rev); 121 for (i = 0; i < 16; i++) { 122 ch->user[i].revision = sata_rev; 123 ch->user[i].mode = 0; 124 ch->user[i].bytecount = (ch->quirks & MVS_Q_GENIIE) ? 8192 : 2048; 125 ch->user[i].tags = MVS_MAX_SLOTS; 126 ch->curr[i] = ch->user[i]; 127 if (ch->pm_level) { 128 ch->user[i].caps = CTS_SATA_CAPS_H_PMREQ | 129 CTS_SATA_CAPS_H_APST | 130 CTS_SATA_CAPS_D_PMREQ | CTS_SATA_CAPS_D_APST; 131 } 132 } 133 rid = ch->unit; 134 if (!(ch->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 135 &rid, RF_ACTIVE))) 136 return (ENXIO); 137 mvs_dmainit(dev); 138 mvs_slotsalloc(dev); 139 mvs_ch_init(dev); 140 mtx_lock(&ch->mtx); 141 rid = ATA_IRQ_RID; 142 if (!(ch->r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 143 &rid, RF_SHAREABLE | RF_ACTIVE))) { 144 device_printf(dev, "Unable to map interrupt\n"); 145 error = ENXIO; 146 goto err0; 147 } 148 if ((bus_setup_intr(dev, ch->r_irq, ATA_INTR_FLAGS, NULL, 149 mvs_ch_intr_locked, dev, &ch->ih))) { 150 device_printf(dev, "Unable to setup interrupt\n"); 151 error = ENXIO; 152 goto err1; 153 } 154 /* Create the device queue for our SIM. */ 155 devq = cam_simq_alloc(MVS_MAX_SLOTS - 1); 156 if (devq == NULL) { 157 device_printf(dev, "Unable to allocate simq\n"); 158 error = ENOMEM; 159 goto err1; 160 } 161 /* Construct SIM entry */ 162 ch->sim = cam_sim_alloc(mvsaction, mvspoll, "mvsch", ch, 163 device_get_unit(dev), &ch->mtx, 164 2, (ch->quirks & MVS_Q_GENI) ? 0 : MVS_MAX_SLOTS - 1, 165 devq); 166 if (ch->sim == NULL) { 167 cam_simq_free(devq); 168 device_printf(dev, "unable to allocate sim\n"); 169 error = ENOMEM; 170 goto err1; 171 } 172 if (xpt_bus_register(ch->sim, dev, 0) != CAM_SUCCESS) { 173 device_printf(dev, "unable to register xpt bus\n"); 174 error = ENXIO; 175 goto err2; 176 } 177 if (xpt_create_path(&ch->path, /*periph*/NULL, cam_sim_path(ch->sim), 178 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 179 device_printf(dev, "unable to create path\n"); 180 error = ENXIO; 181 goto err3; 182 } 183 if (ch->pm_level > 3) { 184 callout_reset(&ch->pm_timer, 185 (ch->pm_level == 4) ? hz / 1000 : hz / 8, 186 mvs_ch_pm, dev); 187 } 188 mtx_unlock(&ch->mtx); 189 return (0); 190 191 err3: 192 xpt_bus_deregister(cam_sim_path(ch->sim)); 193 err2: 194 cam_sim_free(ch->sim, /*free_devq*/TRUE); 195 err1: 196 bus_release_resource(dev, SYS_RES_IRQ, ATA_IRQ_RID, ch->r_irq); 197 err0: 198 bus_release_resource(dev, SYS_RES_MEMORY, ch->unit, ch->r_mem); 199 mtx_unlock(&ch->mtx); 200 mtx_destroy(&ch->mtx); 201 return (error); 202 } 203 204 static int 205 mvs_ch_detach(device_t dev) 206 { 207 struct mvs_channel *ch = device_get_softc(dev); 208 209 mtx_lock(&ch->mtx); 210 xpt_async(AC_LOST_DEVICE, ch->path, NULL); 211 xpt_free_path(ch->path); 212 xpt_bus_deregister(cam_sim_path(ch->sim)); 213 cam_sim_free(ch->sim, /*free_devq*/TRUE); 214 mtx_unlock(&ch->mtx); 215 216 if (ch->pm_level > 3) 217 callout_drain(&ch->pm_timer); 218 bus_teardown_intr(dev, ch->r_irq, ch->ih); 219 bus_release_resource(dev, SYS_RES_IRQ, ATA_IRQ_RID, ch->r_irq); 220 221 mvs_ch_deinit(dev); 222 mvs_slotsfree(dev); 223 mvs_dmafini(dev); 224 225 bus_release_resource(dev, SYS_RES_MEMORY, ch->unit, ch->r_mem); 226 mtx_destroy(&ch->mtx); 227 return (0); 228 } 229 230 static int 231 mvs_ch_init(device_t dev) 232 { 233 struct mvs_channel *ch = device_get_softc(dev); 234 uint32_t reg; 235 236 /* Disable port interrupts */ 237 ATA_OUTL(ch->r_mem, EDMA_IEM, 0); 238 /* Stop EDMA */ 239 ch->curr_mode = MVS_EDMA_UNKNOWN; 240 mvs_set_edma_mode(dev, MVS_EDMA_OFF); 241 /* Clear and configure FIS interrupts. */ 242 ATA_OUTL(ch->r_mem, SATA_FISIC, 0); 243 reg = ATA_INL(ch->r_mem, SATA_FISC); 244 reg |= SATA_FISC_FISWAIT4HOSTRDYEN_B1; 245 ATA_OUTL(ch->r_mem, SATA_FISC, reg); 246 reg = ATA_INL(ch->r_mem, SATA_FISIM); 247 reg |= SATA_FISC_FISWAIT4HOSTRDYEN_B1; 248 ATA_OUTL(ch->r_mem, SATA_FISC, reg); 249 /* Clear SATA error register. */ 250 ATA_OUTL(ch->r_mem, SATA_SE, 0xffffffff); 251 /* Clear any outstanding error interrupts. */ 252 ATA_OUTL(ch->r_mem, EDMA_IEC, 0); 253 /* Unmask all error interrupts */ 254 ATA_OUTL(ch->r_mem, EDMA_IEM, ~EDMA_IE_TRANSIENT); 255 return (0); 256 } 257 258 static int 259 mvs_ch_deinit(device_t dev) 260 { 261 struct mvs_channel *ch = device_get_softc(dev); 262 263 /* Stop EDMA */ 264 mvs_set_edma_mode(dev, MVS_EDMA_OFF); 265 /* Disable port interrupts. */ 266 ATA_OUTL(ch->r_mem, EDMA_IEM, 0); 267 return (0); 268 } 269 270 static int 271 mvs_ch_suspend(device_t dev) 272 { 273 struct mvs_channel *ch = device_get_softc(dev); 274 275 mtx_lock(&ch->mtx); 276 xpt_freeze_simq(ch->sim, 1); 277 while (ch->oslots) 278 msleep(ch, &ch->mtx, PRIBIO, "mvssusp", hz/100); 279 mvs_ch_deinit(dev); 280 mtx_unlock(&ch->mtx); 281 return (0); 282 } 283 284 static int 285 mvs_ch_resume(device_t dev) 286 { 287 struct mvs_channel *ch = device_get_softc(dev); 288 289 mtx_lock(&ch->mtx); 290 mvs_ch_init(dev); 291 mvs_reset(dev); 292 xpt_release_simq(ch->sim, TRUE); 293 mtx_unlock(&ch->mtx); 294 return (0); 295 } 296 297 struct mvs_dc_cb_args { 298 bus_addr_t maddr; 299 int error; 300 }; 301 302 static void 303 mvs_dmainit(device_t dev) 304 { 305 struct mvs_channel *ch = device_get_softc(dev); 306 struct mvs_dc_cb_args dcba; 307 308 /* EDMA command request area. */ 309 if (bus_dma_tag_create(bus_get_dma_tag(dev), 1024, 0, 310 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 311 NULL, NULL, MVS_WORKRQ_SIZE, 1, MVS_WORKRQ_SIZE, 312 0, NULL, NULL, &ch->dma.workrq_tag)) 313 goto error; 314 if (bus_dmamem_alloc(ch->dma.workrq_tag, (void **)&ch->dma.workrq, 0, 315 &ch->dma.workrq_map)) 316 goto error; 317 if (bus_dmamap_load(ch->dma.workrq_tag, ch->dma.workrq_map, ch->dma.workrq, 318 MVS_WORKRQ_SIZE, mvs_dmasetupc_cb, &dcba, 0) || dcba.error) { 319 bus_dmamem_free(ch->dma.workrq_tag, ch->dma.workrq, ch->dma.workrq_map); 320 goto error; 321 } 322 ch->dma.workrq_bus = dcba.maddr; 323 /* EDMA command response area. */ 324 if (bus_dma_tag_create(bus_get_dma_tag(dev), 256, 0, 325 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 326 NULL, NULL, MVS_WORKRP_SIZE, 1, MVS_WORKRP_SIZE, 327 0, NULL, NULL, &ch->dma.workrp_tag)) 328 goto error; 329 if (bus_dmamem_alloc(ch->dma.workrp_tag, (void **)&ch->dma.workrp, 0, 330 &ch->dma.workrp_map)) 331 goto error; 332 if (bus_dmamap_load(ch->dma.workrp_tag, ch->dma.workrp_map, ch->dma.workrp, 333 MVS_WORKRP_SIZE, mvs_dmasetupc_cb, &dcba, 0) || dcba.error) { 334 bus_dmamem_free(ch->dma.workrp_tag, ch->dma.workrp, ch->dma.workrp_map); 335 goto error; 336 } 337 ch->dma.workrp_bus = dcba.maddr; 338 /* Data area. */ 339 if (bus_dma_tag_create(bus_get_dma_tag(dev), 2, MVS_EPRD_MAX, 340 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 341 NULL, NULL, 342 MVS_SG_ENTRIES * PAGE_SIZE * MVS_MAX_SLOTS, 343 MVS_SG_ENTRIES, MVS_EPRD_MAX, 344 0, busdma_lock_mutex, &ch->mtx, &ch->dma.data_tag)) { 345 goto error; 346 } 347 return; 348 349 error: 350 device_printf(dev, "WARNING - DMA initialization failed\n"); 351 mvs_dmafini(dev); 352 } 353 354 static void 355 mvs_dmasetupc_cb(void *xsc, bus_dma_segment_t *segs, int nsegs, int error) 356 { 357 struct mvs_dc_cb_args *dcba = (struct mvs_dc_cb_args *)xsc; 358 359 if (!(dcba->error = error)) 360 dcba->maddr = segs[0].ds_addr; 361 } 362 363 static void 364 mvs_dmafini(device_t dev) 365 { 366 struct mvs_channel *ch = device_get_softc(dev); 367 368 if (ch->dma.data_tag) { 369 bus_dma_tag_destroy(ch->dma.data_tag); 370 ch->dma.data_tag = NULL; 371 } 372 if (ch->dma.workrp_bus) { 373 bus_dmamap_unload(ch->dma.workrp_tag, ch->dma.workrp_map); 374 bus_dmamem_free(ch->dma.workrp_tag, ch->dma.workrp, ch->dma.workrp_map); 375 ch->dma.workrp_bus = 0; 376 ch->dma.workrp_map = NULL; 377 ch->dma.workrp = NULL; 378 } 379 if (ch->dma.workrp_tag) { 380 bus_dma_tag_destroy(ch->dma.workrp_tag); 381 ch->dma.workrp_tag = NULL; 382 } 383 if (ch->dma.workrq_bus) { 384 bus_dmamap_unload(ch->dma.workrq_tag, ch->dma.workrq_map); 385 bus_dmamem_free(ch->dma.workrq_tag, ch->dma.workrq, ch->dma.workrq_map); 386 ch->dma.workrq_bus = 0; 387 ch->dma.workrq_map = NULL; 388 ch->dma.workrq = NULL; 389 } 390 if (ch->dma.workrq_tag) { 391 bus_dma_tag_destroy(ch->dma.workrq_tag); 392 ch->dma.workrq_tag = NULL; 393 } 394 } 395 396 static void 397 mvs_slotsalloc(device_t dev) 398 { 399 struct mvs_channel *ch = device_get_softc(dev); 400 int i; 401 402 /* Alloc and setup command/dma slots */ 403 bzero(ch->slot, sizeof(ch->slot)); 404 for (i = 0; i < MVS_MAX_SLOTS; i++) { 405 struct mvs_slot *slot = &ch->slot[i]; 406 407 slot->dev = dev; 408 slot->slot = i; 409 slot->state = MVS_SLOT_EMPTY; 410 slot->ccb = NULL; 411 callout_init_mtx(&slot->timeout, &ch->mtx, 0); 412 413 if (bus_dmamap_create(ch->dma.data_tag, 0, &slot->dma.data_map)) 414 device_printf(ch->dev, "FAILURE - create data_map\n"); 415 } 416 } 417 418 static void 419 mvs_slotsfree(device_t dev) 420 { 421 struct mvs_channel *ch = device_get_softc(dev); 422 int i; 423 424 /* Free all dma slots */ 425 for (i = 0; i < MVS_MAX_SLOTS; i++) { 426 struct mvs_slot *slot = &ch->slot[i]; 427 428 callout_drain(&slot->timeout); 429 if (slot->dma.data_map) { 430 bus_dmamap_destroy(ch->dma.data_tag, slot->dma.data_map); 431 slot->dma.data_map = NULL; 432 } 433 } 434 } 435 436 static void 437 mvs_setup_edma_queues(device_t dev) 438 { 439 struct mvs_channel *ch = device_get_softc(dev); 440 uint64_t work; 441 442 /* Requests queue. */ 443 work = ch->dma.workrq_bus; 444 ATA_OUTL(ch->r_mem, EDMA_REQQBAH, work >> 32); 445 ATA_OUTL(ch->r_mem, EDMA_REQQIP, work & 0xffffffff); 446 ATA_OUTL(ch->r_mem, EDMA_REQQOP, work & 0xffffffff); 447 bus_dmamap_sync(ch->dma.workrq_tag, ch->dma.workrq_map, BUS_DMASYNC_PREWRITE); 448 /* Reponses queue. */ 449 bzero(ch->dma.workrp, 256); 450 work = ch->dma.workrp_bus; 451 ATA_OUTL(ch->r_mem, EDMA_RESQBAH, work >> 32); 452 ATA_OUTL(ch->r_mem, EDMA_RESQIP, work & 0xffffffff); 453 ATA_OUTL(ch->r_mem, EDMA_RESQOP, work & 0xffffffff); 454 bus_dmamap_sync(ch->dma.workrp_tag, ch->dma.workrp_map, BUS_DMASYNC_PREREAD); 455 ch->out_idx = 0; 456 ch->in_idx = 0; 457 } 458 459 static void 460 mvs_set_edma_mode(device_t dev, enum mvs_edma_mode mode) 461 { 462 struct mvs_channel *ch = device_get_softc(dev); 463 int timeout; 464 uint32_t ecfg, fcfg, hc, ltm, unkn; 465 466 if (mode == ch->curr_mode) 467 return; 468 /* If we are running, we should stop first. */ 469 if (ch->curr_mode != MVS_EDMA_OFF) { 470 ATA_OUTL(ch->r_mem, EDMA_CMD, EDMA_CMD_EDSEDMA); 471 timeout = 0; 472 while (ATA_INL(ch->r_mem, EDMA_CMD) & EDMA_CMD_EENEDMA) { 473 DELAY(1000); 474 if (timeout++ > 1000) { 475 device_printf(dev, "stopping EDMA engine failed\n"); 476 break; 477 } 478 }; 479 } 480 ch->curr_mode = mode; 481 ch->fbs_enabled = 0; 482 ch->fake_busy = 0; 483 /* Report mode to controller. Needed for correct CCC operation. */ 484 MVS_EDMA(device_get_parent(dev), dev, mode); 485 /* Configure new mode. */ 486 ecfg = EDMA_CFG_RESERVED | EDMA_CFG_RESERVED2 | EDMA_CFG_EHOSTQUEUECACHEEN; 487 if (ch->pm_present) { 488 ecfg |= EDMA_CFG_EMASKRXPM; 489 if (ch->quirks & MVS_Q_GENIIE) { 490 ecfg |= EDMA_CFG_EEDMAFBS; 491 ch->fbs_enabled = 1; 492 } 493 } 494 if (ch->quirks & MVS_Q_GENI) 495 ecfg |= EDMA_CFG_ERDBSZ; 496 else if (ch->quirks & MVS_Q_GENII) 497 ecfg |= EDMA_CFG_ERDBSZEXT | EDMA_CFG_EWRBUFFERLEN; 498 if (ch->quirks & MVS_Q_CT) 499 ecfg |= EDMA_CFG_ECUTTHROUGHEN; 500 if (mode != MVS_EDMA_OFF) 501 ecfg |= EDMA_CFG_EEARLYCOMPLETIONEN; 502 if (mode == MVS_EDMA_QUEUED) 503 ecfg |= EDMA_CFG_EQUE; 504 else if (mode == MVS_EDMA_NCQ) 505 ecfg |= EDMA_CFG_ESATANATVCMDQUE; 506 ATA_OUTL(ch->r_mem, EDMA_CFG, ecfg); 507 mvs_setup_edma_queues(dev); 508 if (ch->quirks & MVS_Q_GENIIE) { 509 /* Configure FBS-related registers */ 510 fcfg = ATA_INL(ch->r_mem, SATA_FISC); 511 ltm = ATA_INL(ch->r_mem, SATA_LTM); 512 hc = ATA_INL(ch->r_mem, EDMA_HC); 513 if (ch->fbs_enabled) { 514 fcfg |= SATA_FISC_FISDMAACTIVATESYNCRESP; 515 if (mode == MVS_EDMA_NCQ) { 516 fcfg &= ~SATA_FISC_FISWAIT4HOSTRDYEN_B0; 517 hc &= ~EDMA_IE_EDEVERR; 518 } else { 519 fcfg |= SATA_FISC_FISWAIT4HOSTRDYEN_B0; 520 hc |= EDMA_IE_EDEVERR; 521 } 522 ltm |= (1 << 8); 523 } else { 524 fcfg &= ~SATA_FISC_FISDMAACTIVATESYNCRESP; 525 fcfg &= ~SATA_FISC_FISWAIT4HOSTRDYEN_B0; 526 hc |= EDMA_IE_EDEVERR; 527 ltm &= ~(1 << 8); 528 } 529 ATA_OUTL(ch->r_mem, SATA_FISC, fcfg); 530 ATA_OUTL(ch->r_mem, SATA_LTM, ltm); 531 ATA_OUTL(ch->r_mem, EDMA_HC, hc); 532 /* This is some magic, required to handle several DRQs 533 * with basic DMA. */ 534 unkn = ATA_INL(ch->r_mem, EDMA_UNKN_RESD); 535 if (mode == MVS_EDMA_OFF) 536 unkn |= 1; 537 else 538 unkn &= ~1; 539 ATA_OUTL(ch->r_mem, EDMA_UNKN_RESD, unkn); 540 } 541 /* Run EDMA. */ 542 if (mode != MVS_EDMA_OFF) 543 ATA_OUTL(ch->r_mem, EDMA_CMD, EDMA_CMD_EENEDMA); 544 } 545 546 devclass_t mvs_devclass; 547 devclass_t mvsch_devclass; 548 static device_method_t mvsch_methods[] = { 549 DEVMETHOD(device_probe, mvs_ch_probe), 550 DEVMETHOD(device_attach, mvs_ch_attach), 551 DEVMETHOD(device_detach, mvs_ch_detach), 552 DEVMETHOD(device_suspend, mvs_ch_suspend), 553 DEVMETHOD(device_resume, mvs_ch_resume), 554 { 0, 0 } 555 }; 556 static driver_t mvsch_driver = { 557 "mvsch", 558 mvsch_methods, 559 sizeof(struct mvs_channel) 560 }; 561 DRIVER_MODULE(mvsch, mvs, mvsch_driver, mvsch_devclass, 0, 0); 562 DRIVER_MODULE(mvsch, sata, mvsch_driver, mvsch_devclass, 0, 0); 563 564 static void 565 mvs_phy_check_events(device_t dev, u_int32_t serr) 566 { 567 struct mvs_channel *ch = device_get_softc(dev); 568 569 if (ch->pm_level == 0) { 570 u_int32_t status = ATA_INL(ch->r_mem, SATA_SS); 571 union ccb *ccb; 572 573 if (bootverbose) { 574 if (((status & SATA_SS_DET_MASK) == SATA_SS_DET_PHY_ONLINE) && 575 ((status & SATA_SS_SPD_MASK) != SATA_SS_SPD_NO_SPEED) && 576 ((status & SATA_SS_IPM_MASK) == SATA_SS_IPM_ACTIVE)) { 577 device_printf(dev, "CONNECT requested\n"); 578 } else 579 device_printf(dev, "DISCONNECT requested\n"); 580 } 581 mvs_reset(dev); 582 if ((ccb = xpt_alloc_ccb_nowait()) == NULL) 583 return; 584 if (xpt_create_path(&ccb->ccb_h.path, NULL, 585 cam_sim_path(ch->sim), 586 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 587 xpt_free_ccb(ccb); 588 return; 589 } 590 xpt_rescan(ccb); 591 } 592 } 593 594 static void 595 mvs_notify_events(device_t dev) 596 { 597 struct mvs_channel *ch = device_get_softc(dev); 598 struct cam_path *dpath; 599 uint32_t fis; 600 int d; 601 602 /* Try to read PMP field from SDB FIS. Present only for Gen-IIe. */ 603 fis = ATA_INL(ch->r_mem, SATA_FISDW0); 604 if ((fis & 0x80ff) == 0x80a1) 605 d = (fis & 0x0f00) >> 8; 606 else 607 d = ch->pm_present ? 15 : 0; 608 if (bootverbose) 609 device_printf(dev, "SNTF %d\n", d); 610 if (xpt_create_path(&dpath, NULL, 611 xpt_path_path_id(ch->path), d, 0) == CAM_REQ_CMP) { 612 xpt_async(AC_SCSI_AEN, dpath, NULL); 613 xpt_free_path(dpath); 614 } 615 } 616 617 static void 618 mvs_ch_intr_locked(void *data) 619 { 620 struct mvs_intr_arg *arg = (struct mvs_intr_arg *)data; 621 device_t dev = (device_t)arg->arg; 622 struct mvs_channel *ch = device_get_softc(dev); 623 624 mtx_lock(&ch->mtx); 625 mvs_ch_intr(data); 626 mtx_unlock(&ch->mtx); 627 } 628 629 static void 630 mvs_ch_pm(void *arg) 631 { 632 device_t dev = (device_t)arg; 633 struct mvs_channel *ch = device_get_softc(dev); 634 uint32_t work; 635 636 if (ch->numrslots != 0) 637 return; 638 /* If we are idle - request power state transition. */ 639 work = ATA_INL(ch->r_mem, SATA_SC); 640 work &= ~SATA_SC_SPM_MASK; 641 if (ch->pm_level == 4) 642 work |= SATA_SC_SPM_PARTIAL; 643 else 644 work |= SATA_SC_SPM_SLUMBER; 645 ATA_OUTL(ch->r_mem, SATA_SC, work); 646 } 647 648 static void 649 mvs_ch_pm_wake(device_t dev) 650 { 651 struct mvs_channel *ch = device_get_softc(dev); 652 uint32_t work; 653 int timeout = 0; 654 655 work = ATA_INL(ch->r_mem, SATA_SS); 656 if (work & SATA_SS_IPM_ACTIVE) 657 return; 658 /* If we are not in active state - request power state transition. */ 659 work = ATA_INL(ch->r_mem, SATA_SC); 660 work &= ~SATA_SC_SPM_MASK; 661 work |= SATA_SC_SPM_ACTIVE; 662 ATA_OUTL(ch->r_mem, SATA_SC, work); 663 /* Wait for transition to happen. */ 664 while ((ATA_INL(ch->r_mem, SATA_SS) & SATA_SS_IPM_ACTIVE) == 0 && 665 timeout++ < 100) { 666 DELAY(100); 667 } 668 } 669 670 static void 671 mvs_ch_intr(void *data) 672 { 673 struct mvs_intr_arg *arg = (struct mvs_intr_arg *)data; 674 device_t dev = (device_t)arg->arg; 675 struct mvs_channel *ch = device_get_softc(dev); 676 uint32_t iec, serr = 0, fisic = 0; 677 enum mvs_err_type et; 678 int i, ccs, port = -1, selfdis = 0; 679 int edma = (ch->numtslots != 0 || ch->numdslots != 0); 680 681 //device_printf(dev, "irq cause %02x EDMA %d IEC %08x\n", 682 // arg->cause, edma, ATA_INL(ch->r_mem, EDMA_IEC)); 683 /* New item in response queue. */ 684 if ((arg->cause & 2) && edma) 685 mvs_crbq_intr(dev); 686 /* Some error or special event. */ 687 if (arg->cause & 1) { 688 iec = ATA_INL(ch->r_mem, EDMA_IEC); 689 //device_printf(dev, "irq cause %02x EDMA %d IEC %08x\n", 690 // arg->cause, edma, iec); 691 if (iec & EDMA_IE_SERRINT) { 692 serr = ATA_INL(ch->r_mem, SATA_SE); 693 ATA_OUTL(ch->r_mem, SATA_SE, serr); 694 //device_printf(dev, "SERR %08x\n", serr); 695 } 696 /* EDMA self-disabled due to error. */ 697 if (iec & EDMA_IE_ESELFDIS) 698 selfdis = 1; 699 /* Transport interrupt. */ 700 if (iec & EDMA_IE_ETRANSINT) { 701 /* For Gen-I this bit means self-disable. */ 702 if (ch->quirks & MVS_Q_GENI) 703 selfdis = 1; 704 /* For Gen-II this bit means SDB-N. */ 705 else if (ch->quirks & MVS_Q_GENII) 706 fisic = SATA_FISC_FISWAIT4HOSTRDYEN_B1; 707 else /* For Gen-IIe - read FIS interrupt cause. */ 708 fisic = ATA_INL(ch->r_mem, SATA_FISIC); 709 //device_printf(dev, "FISIC %08x\n", fisic); 710 } 711 if (selfdis) 712 ch->curr_mode = MVS_EDMA_UNKNOWN; 713 ATA_OUTL(ch->r_mem, EDMA_IEC, ~iec); 714 /* Interface errors or Device error. */ 715 if (iec & (0xfc1e9000 | EDMA_IE_EDEVERR)) { 716 port = -1; 717 if (ch->numpslots != 0) { 718 ccs = 0; 719 } else { 720 if (ch->quirks & MVS_Q_GENIIE) 721 ccs = EDMA_S_EIOID(ATA_INL(ch->r_mem, EDMA_S)); 722 else 723 ccs = EDMA_S_EDEVQUETAG(ATA_INL(ch->r_mem, EDMA_S)); 724 /* Check if error is one-PMP-port-specific, */ 725 if (ch->fbs_enabled) { 726 /* Which ports were active. */ 727 for (i = 0; i < 16; i++) { 728 if (ch->numrslotspd[i] == 0) 729 continue; 730 if (port == -1) 731 port = i; 732 else if (port != i) { 733 port = -2; 734 break; 735 } 736 } 737 /* If several ports were active and EDMA still enabled - 738 * other ports are probably unaffected and may continue. 739 */ 740 if (port == -2 && !selfdis) { 741 uint16_t p = ATA_INL(ch->r_mem, SATA_SATAITC) >> 16; 742 port = ffs(p) - 1; 743 if (port != (fls(p) - 1)) 744 port = -2; 745 } 746 } 747 } 748 //device_printf(dev, "err slot %d port %d\n", ccs, port); 749 mvs_requeue_frozen(dev); 750 for (i = 0; i < MVS_MAX_SLOTS; i++) { 751 /* XXX: reqests in loading state. */ 752 if (((ch->rslots >> i) & 1) == 0) 753 continue; 754 if (port >= 0 && 755 ch->slot[i].ccb->ccb_h.target_id != port) 756 continue; 757 if (iec & EDMA_IE_EDEVERR) { /* Device error. */ 758 if (port != -2) { 759 if (ch->numtslots == 0) { 760 /* Untagged operation. */ 761 if (i == ccs) 762 et = MVS_ERR_TFE; 763 else 764 et = MVS_ERR_INNOCENT; 765 } else { 766 /* Tagged operation. */ 767 et = MVS_ERR_NCQ; 768 } 769 } else { 770 et = MVS_ERR_TFE; 771 ch->fatalerr = 1; 772 } 773 } else if (iec & 0xfc1e9000) { 774 if (ch->numtslots == 0 && i != ccs && port != -2) 775 et = MVS_ERR_INNOCENT; 776 else 777 et = MVS_ERR_SATA; 778 } else 779 et = MVS_ERR_INVALID; 780 mvs_end_transaction(&ch->slot[i], et); 781 } 782 } 783 /* Process SDB-N. */ 784 if (fisic & SATA_FISC_FISWAIT4HOSTRDYEN_B1) 785 mvs_notify_events(dev); 786 if (fisic) 787 ATA_OUTL(ch->r_mem, SATA_FISIC, ~fisic); 788 /* Process hot-plug. */ 789 if ((iec & (EDMA_IE_EDEVDIS | EDMA_IE_EDEVCON)) || 790 (serr & SATA_SE_PHY_CHANGED)) 791 mvs_phy_check_events(dev, serr); 792 } 793 /* Legacy mode device interrupt. */ 794 if ((arg->cause & 2) && !edma) 795 mvs_legacy_intr(dev); 796 } 797 798 static uint8_t 799 mvs_getstatus(device_t dev, int clear) 800 { 801 struct mvs_channel *ch = device_get_softc(dev); 802 uint8_t status = ATA_INB(ch->r_mem, clear ? ATA_STATUS : ATA_ALTSTAT); 803 804 if (ch->fake_busy) { 805 if (status & (ATA_S_BUSY | ATA_S_DRQ | ATA_S_ERROR)) 806 ch->fake_busy = 0; 807 else 808 status |= ATA_S_BUSY; 809 } 810 return (status); 811 } 812 813 static void 814 mvs_legacy_intr(device_t dev) 815 { 816 struct mvs_channel *ch = device_get_softc(dev); 817 struct mvs_slot *slot = &ch->slot[0]; /* PIO is always in slot 0. */ 818 union ccb *ccb = slot->ccb; 819 enum mvs_err_type et = MVS_ERR_NONE; 820 int port; 821 u_int length; 822 uint8_t status, ireason; 823 824 /* Clear interrupt and get status. */ 825 status = mvs_getstatus(dev, 1); 826 // device_printf(dev, "Legacy intr status %02x\n", 827 // status); 828 if (slot->state < MVS_SLOT_RUNNING) 829 return; 830 port = ccb->ccb_h.target_id & 0x0f; 831 /* Wait a bit for late !BUSY status update. */ 832 if (status & ATA_S_BUSY) { 833 DELAY(100); 834 if ((status = mvs_getstatus(dev, 1)) & ATA_S_BUSY) { 835 DELAY(1000); 836 if ((status = mvs_getstatus(dev, 1)) & ATA_S_BUSY) 837 return; 838 } 839 } 840 /* If we got an error, we are done. */ 841 if (status & ATA_S_ERROR) { 842 et = MVS_ERR_TFE; 843 goto end_finished; 844 } 845 if (ccb->ccb_h.func_code == XPT_ATA_IO) { /* ATA PIO */ 846 ccb->ataio.res.status = status; 847 /* Are we moving data? */ 848 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 849 /* If data read command - get them. */ 850 if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 851 if (mvs_wait(dev, ATA_S_DRQ, ATA_S_BUSY, 1000) < 0) { 852 device_printf(dev, "timeout waiting for read DRQ\n"); 853 et = MVS_ERR_TIMEOUT; 854 goto end_finished; 855 } 856 ATA_INSW_STRM(ch->r_mem, ATA_DATA, 857 (uint16_t *)(ccb->ataio.data_ptr + ch->donecount), 858 ch->transfersize / 2); 859 } 860 /* Update how far we've gotten. */ 861 ch->donecount += ch->transfersize; 862 /* Do we need more? */ 863 if (ccb->ataio.dxfer_len > ch->donecount) { 864 /* Set this transfer size according to HW capabilities */ 865 ch->transfersize = min(ccb->ataio.dxfer_len - ch->donecount, 866 ch->curr[ccb->ccb_h.target_id].bytecount); 867 /* If data write command - put them */ 868 if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_OUT) { 869 if (mvs_wait(dev, ATA_S_DRQ, ATA_S_BUSY, 1000) < 0) { 870 device_printf(dev, "timeout waiting for write DRQ\n"); 871 et = MVS_ERR_TIMEOUT; 872 goto end_finished; 873 } 874 ATA_OUTSW_STRM(ch->r_mem, ATA_DATA, 875 (uint16_t *)(ccb->ataio.data_ptr + ch->donecount), 876 ch->transfersize / 2); 877 return; 878 } 879 /* If data read command, return & wait for interrupt */ 880 if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) 881 return; 882 } 883 } 884 } else if (ch->basic_dma) { /* ATAPI DMA */ 885 if (status & ATA_S_DWF) 886 et = MVS_ERR_TFE; 887 else if (ATA_INL(ch->r_mem, DMA_S) & DMA_S_ERR) 888 et = MVS_ERR_TFE; 889 /* Stop basic DMA. */ 890 ATA_OUTL(ch->r_mem, DMA_C, 0); 891 goto end_finished; 892 } else { /* ATAPI PIO */ 893 length = ATA_INB(ch->r_mem,ATA_CYL_LSB) | (ATA_INB(ch->r_mem,ATA_CYL_MSB) << 8); 894 ireason = ATA_INB(ch->r_mem,ATA_IREASON); 895 //device_printf(dev, "status %02x, ireason %02x, length %d\n", status, ireason, length); 896 switch ((ireason & (ATA_I_CMD | ATA_I_IN)) | 897 (status & ATA_S_DRQ)) { 898 899 case ATAPI_P_CMDOUT: 900 device_printf(dev, "ATAPI CMDOUT\n"); 901 /* Return wait for interrupt */ 902 return; 903 904 case ATAPI_P_WRITE: 905 //device_printf(dev, "ATAPI WRITE\n"); 906 if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 907 device_printf(dev, "trying to write on read buffer\n"); 908 et = MVS_ERR_TFE; 909 goto end_finished; 910 break; 911 } 912 ATA_OUTSW_STRM(ch->r_mem, ATA_DATA, 913 (uint16_t *)(ccb->csio.data_ptr + ch->donecount), 914 length / 2); 915 ch->donecount += length; 916 /* Set next transfer size according to HW capabilities */ 917 ch->transfersize = min(ccb->csio.dxfer_len - ch->donecount, 918 ch->curr[ccb->ccb_h.target_id].bytecount); 919 /* Return wait for interrupt */ 920 return; 921 922 case ATAPI_P_READ: 923 //device_printf(dev, "ATAPI READ\n"); 924 if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_OUT) { 925 device_printf(dev, "trying to read on write buffer\n"); 926 et = MVS_ERR_TFE; 927 goto end_finished; 928 } 929 ATA_INSW_STRM(ch->r_mem, ATA_DATA, 930 (uint16_t *)(ccb->csio.data_ptr + ch->donecount), 931 length / 2); 932 ch->donecount += length; 933 /* Set next transfer size according to HW capabilities */ 934 ch->transfersize = min(ccb->csio.dxfer_len - ch->donecount, 935 ch->curr[ccb->ccb_h.target_id].bytecount); 936 /* Return wait for interrupt */ 937 return; 938 939 case ATAPI_P_DONEDRQ: 940 device_printf(dev, "ATAPI DONEDRQ\n"); 941 device_printf(dev, 942 "WARNING - DONEDRQ non conformant device\n"); 943 if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 944 ATA_INSW_STRM(ch->r_mem, ATA_DATA, 945 (uint16_t *)(ccb->csio.data_ptr + ch->donecount), 946 length / 2); 947 ch->donecount += length; 948 } 949 else if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_OUT) { 950 ATA_OUTSW_STRM(ch->r_mem, ATA_DATA, 951 (uint16_t *)(ccb->csio.data_ptr + ch->donecount), 952 length / 2); 953 ch->donecount += length; 954 } 955 else 956 et = MVS_ERR_TFE; 957 /* FALLTHROUGH */ 958 959 case ATAPI_P_ABORT: 960 case ATAPI_P_DONE: 961 //device_printf(dev, "ATAPI ABORT/DONE\n"); 962 if (status & (ATA_S_ERROR | ATA_S_DWF)) 963 et = MVS_ERR_TFE; 964 goto end_finished; 965 966 default: 967 device_printf(dev, "unknown transfer phase (status %02x, ireason %02x)\n", 968 status, ireason); 969 et = MVS_ERR_TFE; 970 } 971 } 972 973 end_finished: 974 mvs_end_transaction(slot, et); 975 } 976 977 static void 978 mvs_crbq_intr(device_t dev) 979 { 980 struct mvs_channel *ch = device_get_softc(dev); 981 struct mvs_crpb *crpb; 982 union ccb *ccb; 983 int in_idx, cin_idx, slot; 984 uint16_t flags; 985 986 in_idx = (ATA_INL(ch->r_mem, EDMA_RESQIP) & EDMA_RESQP_ERPQP_MASK) >> 987 EDMA_RESQP_ERPQP_SHIFT; 988 bus_dmamap_sync(ch->dma.workrp_tag, ch->dma.workrp_map, 989 BUS_DMASYNC_POSTREAD); 990 cin_idx = ch->in_idx; 991 ch->in_idx = in_idx; 992 while (in_idx != cin_idx) { 993 crpb = (struct mvs_crpb *) 994 (ch->dma.workrp + MVS_CRPB_OFFSET + (MVS_CRPB_SIZE * cin_idx)); 995 slot = le16toh(crpb->id) & MVS_CRPB_TAG_MASK; 996 flags = le16toh(crpb->rspflg); 997 //device_printf(dev, "CRPB %d %d %04x\n", cin_idx, slot, flags); 998 /* 999 * Handle only successfull completions here. 1000 * Errors will be handled by main intr handler. 1001 */ 1002 if (ch->numtslots != 0 || (flags & EDMA_IE_EDEVERR) == 0) { 1003 if ((flags >> 8) & ATA_S_ERROR) 1004 device_printf(dev, "ERROR STATUS CRPB %d %d %04x\n", cin_idx, slot, flags); 1005 if (ch->slot[slot].state >= MVS_SLOT_RUNNING) { 1006 ccb = ch->slot[slot].ccb; 1007 ccb->ataio.res.status = (flags & MVS_CRPB_ATASTS_MASK) >> 1008 MVS_CRPB_ATASTS_SHIFT; 1009 mvs_end_transaction(&ch->slot[slot], MVS_ERR_NONE); 1010 } else 1011 device_printf(dev, "EMPTY CRPB %d (->%d) %d %04x\n", cin_idx, in_idx, slot, flags); 1012 } else 1013 device_printf(dev, "ERROR FLAGS CRPB %d %d %04x\n", cin_idx, slot, flags); 1014 1015 cin_idx = (cin_idx + 1) & (MVS_MAX_SLOTS - 1); 1016 } 1017 bus_dmamap_sync(ch->dma.workrp_tag, ch->dma.workrp_map, 1018 BUS_DMASYNC_PREREAD); 1019 if (cin_idx == ch->in_idx) { 1020 ATA_OUTL(ch->r_mem, EDMA_RESQOP, 1021 ch->dma.workrp_bus | (cin_idx << EDMA_RESQP_ERPQP_SHIFT)); 1022 } 1023 } 1024 1025 /* Must be called with channel locked. */ 1026 static int 1027 mvs_check_collision(device_t dev, union ccb *ccb) 1028 { 1029 struct mvs_channel *ch = device_get_softc(dev); 1030 1031 if (ccb->ccb_h.func_code == XPT_ATA_IO) { 1032 /* NCQ DMA */ 1033 if (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) { 1034 /* Can't mix NCQ and non-NCQ DMA commands. */ 1035 if (ch->numdslots != 0) 1036 return (1); 1037 /* Can't mix NCQ and PIO commands. */ 1038 if (ch->numpslots != 0) 1039 return (1); 1040 /* If we have no FBS */ 1041 if (!ch->fbs_enabled) { 1042 /* Tagged command while tagged to other target is active. */ 1043 if (ch->numtslots != 0 && 1044 ch->taggedtarget != ccb->ccb_h.target_id) 1045 return (1); 1046 } 1047 /* Non-NCQ DMA */ 1048 } else if (ccb->ataio.cmd.flags & CAM_ATAIO_DMA) { 1049 /* Can't mix non-NCQ DMA and NCQ commands. */ 1050 if (ch->numtslots != 0) 1051 return (1); 1052 /* Can't mix non-NCQ DMA and PIO commands. */ 1053 if (ch->numpslots != 0) 1054 return (1); 1055 /* PIO */ 1056 } else { 1057 /* Can't mix PIO with anything. */ 1058 if (ch->numrslots != 0) 1059 return (1); 1060 } 1061 if (ccb->ataio.cmd.flags & (CAM_ATAIO_CONTROL | CAM_ATAIO_NEEDRESULT)) { 1062 /* Atomic command while anything active. */ 1063 if (ch->numrslots != 0) 1064 return (1); 1065 } 1066 } else { /* ATAPI */ 1067 /* ATAPI goes without EDMA, so can't mix it with anything. */ 1068 if (ch->numrslots != 0) 1069 return (1); 1070 } 1071 /* We have some atomic command running. */ 1072 if (ch->aslots != 0) 1073 return (1); 1074 return (0); 1075 } 1076 1077 static void 1078 mvs_tfd_read(device_t dev, union ccb *ccb) 1079 { 1080 struct mvs_channel *ch = device_get_softc(dev); 1081 struct ata_res *res = &ccb->ataio.res; 1082 1083 res->status = ATA_INB(ch->r_mem, ATA_ALTSTAT); 1084 res->error = ATA_INB(ch->r_mem, ATA_ERROR); 1085 res->device = ATA_INB(ch->r_mem, ATA_DRIVE); 1086 ATA_OUTB(ch->r_mem, ATA_CONTROL, ATA_A_HOB); 1087 res->sector_count_exp = ATA_INB(ch->r_mem, ATA_COUNT); 1088 res->lba_low_exp = ATA_INB(ch->r_mem, ATA_SECTOR); 1089 res->lba_mid_exp = ATA_INB(ch->r_mem, ATA_CYL_LSB); 1090 res->lba_high_exp = ATA_INB(ch->r_mem, ATA_CYL_MSB); 1091 ATA_OUTB(ch->r_mem, ATA_CONTROL, 0); 1092 res->sector_count = ATA_INB(ch->r_mem, ATA_COUNT); 1093 res->lba_low = ATA_INB(ch->r_mem, ATA_SECTOR); 1094 res->lba_mid = ATA_INB(ch->r_mem, ATA_CYL_LSB); 1095 res->lba_high = ATA_INB(ch->r_mem, ATA_CYL_MSB); 1096 } 1097 1098 static void 1099 mvs_tfd_write(device_t dev, union ccb *ccb) 1100 { 1101 struct mvs_channel *ch = device_get_softc(dev); 1102 struct ata_cmd *cmd = &ccb->ataio.cmd; 1103 1104 ATA_OUTB(ch->r_mem, ATA_DRIVE, cmd->device); 1105 ATA_OUTB(ch->r_mem, ATA_CONTROL, cmd->control); 1106 ATA_OUTB(ch->r_mem, ATA_FEATURE, cmd->features_exp); 1107 ATA_OUTB(ch->r_mem, ATA_FEATURE, cmd->features); 1108 ATA_OUTB(ch->r_mem, ATA_COUNT, cmd->sector_count_exp); 1109 ATA_OUTB(ch->r_mem, ATA_COUNT, cmd->sector_count); 1110 ATA_OUTB(ch->r_mem, ATA_SECTOR, cmd->lba_low_exp); 1111 ATA_OUTB(ch->r_mem, ATA_SECTOR, cmd->lba_low); 1112 ATA_OUTB(ch->r_mem, ATA_CYL_LSB, cmd->lba_mid_exp); 1113 ATA_OUTB(ch->r_mem, ATA_CYL_LSB, cmd->lba_mid); 1114 ATA_OUTB(ch->r_mem, ATA_CYL_MSB, cmd->lba_high_exp); 1115 ATA_OUTB(ch->r_mem, ATA_CYL_MSB, cmd->lba_high); 1116 ATA_OUTB(ch->r_mem, ATA_COMMAND, cmd->command); 1117 } 1118 1119 1120 /* Must be called with channel locked. */ 1121 static void 1122 mvs_begin_transaction(device_t dev, union ccb *ccb) 1123 { 1124 struct mvs_channel *ch = device_get_softc(dev); 1125 struct mvs_slot *slot; 1126 int slotn, tag; 1127 1128 if (ch->pm_level > 0) 1129 mvs_ch_pm_wake(dev); 1130 /* Softreset is a special case. */ 1131 if (ccb->ccb_h.func_code == XPT_ATA_IO && 1132 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL)) { 1133 mvs_softreset(dev, ccb); 1134 return; 1135 } 1136 /* Choose empty slot. */ 1137 slotn = ffs(~ch->oslots) - 1; 1138 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1139 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 1140 if (ch->quirks & MVS_Q_GENIIE) 1141 tag = ffs(~ch->otagspd[ccb->ccb_h.target_id]) - 1; 1142 else 1143 tag = slotn; 1144 } else 1145 tag = 0; 1146 /* Occupy chosen slot. */ 1147 slot = &ch->slot[slotn]; 1148 slot->ccb = ccb; 1149 slot->tag = tag; 1150 /* Stop PM timer. */ 1151 if (ch->numrslots == 0 && ch->pm_level > 3) 1152 callout_stop(&ch->pm_timer); 1153 /* Update channel stats. */ 1154 ch->oslots |= (1 << slot->slot); 1155 ch->numrslots++; 1156 ch->numrslotspd[ccb->ccb_h.target_id]++; 1157 if (ccb->ccb_h.func_code == XPT_ATA_IO) { 1158 if (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) { 1159 ch->otagspd[ccb->ccb_h.target_id] |= (1 << slot->tag); 1160 ch->numtslots++; 1161 ch->numtslotspd[ccb->ccb_h.target_id]++; 1162 ch->taggedtarget = ccb->ccb_h.target_id; 1163 mvs_set_edma_mode(dev, MVS_EDMA_NCQ); 1164 } else if (ccb->ataio.cmd.flags & CAM_ATAIO_DMA) { 1165 ch->numdslots++; 1166 mvs_set_edma_mode(dev, MVS_EDMA_ON); 1167 } else { 1168 ch->numpslots++; 1169 mvs_set_edma_mode(dev, MVS_EDMA_OFF); 1170 } 1171 if (ccb->ataio.cmd.flags & 1172 (CAM_ATAIO_CONTROL | CAM_ATAIO_NEEDRESULT)) { 1173 ch->aslots |= (1 << slot->slot); 1174 } 1175 } else { 1176 uint8_t *cdb = (ccb->ccb_h.flags & CAM_CDB_POINTER) ? 1177 ccb->csio.cdb_io.cdb_ptr : ccb->csio.cdb_io.cdb_bytes; 1178 ch->numpslots++; 1179 /* Use ATAPI DMA only for commands without under-/overruns. */ 1180 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE && 1181 ch->curr[ccb->ccb_h.target_id].mode >= ATA_DMA && 1182 (ch->quirks & MVS_Q_SOC) == 0 && 1183 (cdb[0] == 0x08 || 1184 cdb[0] == 0x0a || 1185 cdb[0] == 0x28 || 1186 cdb[0] == 0x2a || 1187 cdb[0] == 0x88 || 1188 cdb[0] == 0x8a || 1189 cdb[0] == 0xa8 || 1190 cdb[0] == 0xaa || 1191 cdb[0] == 0xbe)) { 1192 ch->basic_dma = 1; 1193 } 1194 mvs_set_edma_mode(dev, MVS_EDMA_OFF); 1195 } 1196 if (ch->numpslots == 0 || ch->basic_dma) { 1197 void *buf; 1198 bus_size_t size; 1199 1200 slot->state = MVS_SLOT_LOADING; 1201 if (ccb->ccb_h.func_code == XPT_ATA_IO) { 1202 buf = ccb->ataio.data_ptr; 1203 size = ccb->ataio.dxfer_len; 1204 } else { 1205 buf = ccb->csio.data_ptr; 1206 size = ccb->csio.dxfer_len; 1207 } 1208 bus_dmamap_load(ch->dma.data_tag, slot->dma.data_map, 1209 buf, size, mvs_dmasetprd, slot, 0); 1210 } else 1211 mvs_legacy_execute_transaction(slot); 1212 } 1213 1214 /* Locked by busdma engine. */ 1215 static void 1216 mvs_dmasetprd(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1217 { 1218 struct mvs_slot *slot = arg; 1219 struct mvs_channel *ch = device_get_softc(slot->dev); 1220 struct mvs_eprd *eprd; 1221 int i; 1222 1223 if (error) { 1224 device_printf(slot->dev, "DMA load error\n"); 1225 mvs_end_transaction(slot, MVS_ERR_INVALID); 1226 return; 1227 } 1228 KASSERT(nsegs <= MVS_SG_ENTRIES, ("too many DMA segment entries\n")); 1229 /* If there is only one segment - no need to use S/G table on Gen-IIe. */ 1230 if (nsegs == 1 && ch->basic_dma == 0 && (ch->quirks & MVS_Q_GENIIE)) { 1231 slot->dma.addr = segs[0].ds_addr; 1232 slot->dma.len = segs[0].ds_len; 1233 } else { 1234 slot->dma.addr = 0; 1235 /* Get a piece of the workspace for this EPRD */ 1236 eprd = (struct mvs_eprd *) 1237 (ch->dma.workrq + MVS_EPRD_OFFSET + (MVS_EPRD_SIZE * slot->slot)); 1238 /* Fill S/G table */ 1239 for (i = 0; i < nsegs; i++) { 1240 eprd[i].prdbal = htole32(segs[i].ds_addr); 1241 eprd[i].bytecount = htole32(segs[i].ds_len & MVS_EPRD_MASK); 1242 eprd[i].prdbah = htole32((segs[i].ds_addr >> 16) >> 16); 1243 } 1244 eprd[i - 1].bytecount |= htole32(MVS_EPRD_EOF); 1245 } 1246 bus_dmamap_sync(ch->dma.data_tag, slot->dma.data_map, 1247 ((slot->ccb->ccb_h.flags & CAM_DIR_IN) ? 1248 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE)); 1249 if (ch->basic_dma) 1250 mvs_legacy_execute_transaction(slot); 1251 else 1252 mvs_execute_transaction(slot); 1253 } 1254 1255 static void 1256 mvs_legacy_execute_transaction(struct mvs_slot *slot) 1257 { 1258 device_t dev = slot->dev; 1259 struct mvs_channel *ch = device_get_softc(dev); 1260 bus_addr_t eprd; 1261 union ccb *ccb = slot->ccb; 1262 int port = ccb->ccb_h.target_id & 0x0f; 1263 int timeout; 1264 1265 slot->state = MVS_SLOT_RUNNING; 1266 ch->rslots |= (1 << slot->slot); 1267 ATA_OUTB(ch->r_mem, SATA_SATAICTL, port << SATA_SATAICTL_PMPTX_SHIFT); 1268 if (ccb->ccb_h.func_code == XPT_ATA_IO) { 1269 // device_printf(dev, "%d Legacy command %02x size %d\n", 1270 // port, ccb->ataio.cmd.command, ccb->ataio.dxfer_len); 1271 mvs_tfd_write(dev, ccb); 1272 /* Device reset doesn't interrupt. */ 1273 if (ccb->ataio.cmd.command == ATA_DEVICE_RESET) { 1274 int timeout = 1000000; 1275 do { 1276 DELAY(10); 1277 ccb->ataio.res.status = ATA_INB(ch->r_mem, ATA_STATUS); 1278 } while (ccb->ataio.res.status & ATA_S_BUSY && timeout--); 1279 mvs_legacy_intr(dev); 1280 return; 1281 } 1282 ch->donecount = 0; 1283 ch->transfersize = min(ccb->ataio.dxfer_len, 1284 ch->curr[port].bytecount); 1285 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) 1286 ch->fake_busy = 1; 1287 /* If data write command - output the data */ 1288 if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_OUT) { 1289 if (mvs_wait(dev, ATA_S_DRQ, ATA_S_BUSY, 1000) < 0) { 1290 device_printf(dev, "timeout waiting for write DRQ\n"); 1291 mvs_end_transaction(slot, MVS_ERR_TIMEOUT); 1292 return; 1293 } 1294 ATA_OUTSW_STRM(ch->r_mem, ATA_DATA, 1295 (uint16_t *)(ccb->ataio.data_ptr + ch->donecount), 1296 ch->transfersize / 2); 1297 } 1298 } else { 1299 // device_printf(dev, "%d ATAPI command %02x size %d dma %d\n", 1300 // port, ccb->csio.cdb_io.cdb_bytes[0], ccb->csio.dxfer_len, 1301 // ch->basic_dma); 1302 ch->donecount = 0; 1303 ch->transfersize = min(ccb->csio.dxfer_len, 1304 ch->curr[port].bytecount); 1305 /* Write ATA PACKET command. */ 1306 if (ch->basic_dma) { 1307 ATA_OUTB(ch->r_mem, ATA_FEATURE, ATA_F_DMA); 1308 ATA_OUTB(ch->r_mem, ATA_CYL_LSB, 0); 1309 ATA_OUTB(ch->r_mem, ATA_CYL_MSB, 0); 1310 } else { 1311 ATA_OUTB(ch->r_mem, ATA_FEATURE, 0); 1312 ATA_OUTB(ch->r_mem, ATA_CYL_LSB, ch->transfersize); 1313 ATA_OUTB(ch->r_mem, ATA_CYL_MSB, ch->transfersize >> 8); 1314 } 1315 ATA_OUTB(ch->r_mem, ATA_COMMAND, ATA_PACKET_CMD); 1316 ch->fake_busy = 1; 1317 /* Wait for ready to write ATAPI command block */ 1318 if (mvs_wait(dev, 0, ATA_S_BUSY, 1000) < 0) { 1319 device_printf(dev, "timeout waiting for ATAPI !BUSY\n"); 1320 mvs_end_transaction(slot, MVS_ERR_TIMEOUT); 1321 return; 1322 } 1323 timeout = 5000; 1324 while (timeout--) { 1325 int reason = ATA_INB(ch->r_mem, ATA_IREASON); 1326 int status = ATA_INB(ch->r_mem, ATA_STATUS); 1327 1328 if (((reason & (ATA_I_CMD | ATA_I_IN)) | 1329 (status & (ATA_S_DRQ | ATA_S_BUSY))) == ATAPI_P_CMDOUT) 1330 break; 1331 DELAY(20); 1332 } 1333 if (timeout <= 0) { 1334 device_printf(dev, "timeout waiting for ATAPI command ready\n"); 1335 mvs_end_transaction(slot, MVS_ERR_TIMEOUT); 1336 return; 1337 } 1338 /* Write ATAPI command. */ 1339 ATA_OUTSW_STRM(ch->r_mem, ATA_DATA, 1340 (uint16_t *)((ccb->ccb_h.flags & CAM_CDB_POINTER) ? 1341 ccb->csio.cdb_io.cdb_ptr : ccb->csio.cdb_io.cdb_bytes), 1342 ch->curr[port].atapi / 2); 1343 DELAY(10); 1344 if (ch->basic_dma) { 1345 /* Start basic DMA. */ 1346 eprd = ch->dma.workrq_bus + MVS_EPRD_OFFSET + 1347 (MVS_EPRD_SIZE * slot->slot); 1348 ATA_OUTL(ch->r_mem, DMA_DTLBA, eprd); 1349 ATA_OUTL(ch->r_mem, DMA_DTHBA, (eprd >> 16) >> 16); 1350 ATA_OUTL(ch->r_mem, DMA_C, DMA_C_START | 1351 (((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) ? 1352 DMA_C_READ : 0)); 1353 } else if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) 1354 ch->fake_busy = 1; 1355 } 1356 /* Start command execution timeout */ 1357 callout_reset(&slot->timeout, (int)ccb->ccb_h.timeout * hz / 1000, 1358 (timeout_t*)mvs_timeout, slot); 1359 } 1360 1361 /* Must be called with channel locked. */ 1362 static void 1363 mvs_execute_transaction(struct mvs_slot *slot) 1364 { 1365 device_t dev = slot->dev; 1366 struct mvs_channel *ch = device_get_softc(dev); 1367 bus_addr_t eprd; 1368 struct mvs_crqb *crqb; 1369 struct mvs_crqb_gen2e *crqb2e; 1370 union ccb *ccb = slot->ccb; 1371 int port = ccb->ccb_h.target_id & 0x0f; 1372 int i; 1373 1374 // device_printf(dev, "%d EDMA command %02x size %d slot %d tag %d\n", 1375 // port, ccb->ataio.cmd.command, ccb->ataio.dxfer_len, slot->slot, slot->tag); 1376 /* Get address of the prepared EPRD */ 1377 eprd = ch->dma.workrq_bus + MVS_EPRD_OFFSET + (MVS_EPRD_SIZE * slot->slot); 1378 /* Prepare CRQB. Gen IIe uses different CRQB format. */ 1379 if (ch->quirks & MVS_Q_GENIIE) { 1380 crqb2e = (struct mvs_crqb_gen2e *) 1381 (ch->dma.workrq + MVS_CRQB_OFFSET + (MVS_CRQB_SIZE * ch->out_idx)); 1382 crqb2e->ctrlflg = htole32( 1383 ((ccb->ccb_h.flags & CAM_DIR_IN) ? MVS_CRQB2E_READ : 0) | 1384 (slot->tag << MVS_CRQB2E_DTAG_SHIFT) | 1385 (port << MVS_CRQB2E_PMP_SHIFT) | 1386 (slot->slot << MVS_CRQB2E_HTAG_SHIFT)); 1387 /* If there is only one segment - no need to use S/G table. */ 1388 if (slot->dma.addr != 0) { 1389 eprd = slot->dma.addr; 1390 crqb2e->ctrlflg |= htole32(MVS_CRQB2E_CPRD); 1391 crqb2e->drbc = slot->dma.len; 1392 } 1393 crqb2e->cprdbl = htole32(eprd); 1394 crqb2e->cprdbh = htole32((eprd >> 16) >> 16); 1395 crqb2e->cmd[0] = 0; 1396 crqb2e->cmd[1] = 0; 1397 crqb2e->cmd[2] = ccb->ataio.cmd.command; 1398 crqb2e->cmd[3] = ccb->ataio.cmd.features; 1399 crqb2e->cmd[4] = ccb->ataio.cmd.lba_low; 1400 crqb2e->cmd[5] = ccb->ataio.cmd.lba_mid; 1401 crqb2e->cmd[6] = ccb->ataio.cmd.lba_high; 1402 crqb2e->cmd[7] = ccb->ataio.cmd.device; 1403 crqb2e->cmd[8] = ccb->ataio.cmd.lba_low_exp; 1404 crqb2e->cmd[9] = ccb->ataio.cmd.lba_mid_exp; 1405 crqb2e->cmd[10] = ccb->ataio.cmd.lba_high_exp; 1406 crqb2e->cmd[11] = ccb->ataio.cmd.features_exp; 1407 if (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) { 1408 crqb2e->cmd[12] = slot->tag << 3; 1409 crqb2e->cmd[13] = 0; 1410 } else { 1411 crqb2e->cmd[12] = ccb->ataio.cmd.sector_count; 1412 crqb2e->cmd[13] = ccb->ataio.cmd.sector_count_exp; 1413 } 1414 crqb2e->cmd[14] = 0; 1415 crqb2e->cmd[15] = 0; 1416 } else { 1417 crqb = (struct mvs_crqb *) 1418 (ch->dma.workrq + MVS_CRQB_OFFSET + (MVS_CRQB_SIZE * ch->out_idx)); 1419 crqb->cprdbl = htole32(eprd); 1420 crqb->cprdbh = htole32((eprd >> 16) >> 16); 1421 crqb->ctrlflg = htole16( 1422 ((ccb->ccb_h.flags & CAM_DIR_IN) ? MVS_CRQB_READ : 0) | 1423 (slot->slot << MVS_CRQB_TAG_SHIFT) | 1424 (port << MVS_CRQB_PMP_SHIFT)); 1425 i = 0; 1426 /* 1427 * Controller can handle only 11 of 12 ATA registers, 1428 * so we have to choose which one to skip. 1429 */ 1430 if (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) { 1431 crqb->cmd[i++] = ccb->ataio.cmd.features_exp; 1432 crqb->cmd[i++] = 0x11; 1433 } 1434 crqb->cmd[i++] = ccb->ataio.cmd.features; 1435 crqb->cmd[i++] = 0x11; 1436 if (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) { 1437 crqb->cmd[i++] = slot->tag << 3; 1438 crqb->cmd[i++] = 0x12; 1439 } else { 1440 crqb->cmd[i++] = ccb->ataio.cmd.sector_count_exp; 1441 crqb->cmd[i++] = 0x12; 1442 crqb->cmd[i++] = ccb->ataio.cmd.sector_count; 1443 crqb->cmd[i++] = 0x12; 1444 } 1445 crqb->cmd[i++] = ccb->ataio.cmd.lba_low_exp; 1446 crqb->cmd[i++] = 0x13; 1447 crqb->cmd[i++] = ccb->ataio.cmd.lba_low; 1448 crqb->cmd[i++] = 0x13; 1449 crqb->cmd[i++] = ccb->ataio.cmd.lba_mid_exp; 1450 crqb->cmd[i++] = 0x14; 1451 crqb->cmd[i++] = ccb->ataio.cmd.lba_mid; 1452 crqb->cmd[i++] = 0x14; 1453 crqb->cmd[i++] = ccb->ataio.cmd.lba_high_exp; 1454 crqb->cmd[i++] = 0x15; 1455 crqb->cmd[i++] = ccb->ataio.cmd.lba_high; 1456 crqb->cmd[i++] = 0x15; 1457 crqb->cmd[i++] = ccb->ataio.cmd.device; 1458 crqb->cmd[i++] = 0x16; 1459 crqb->cmd[i++] = ccb->ataio.cmd.command; 1460 crqb->cmd[i++] = 0x97; 1461 } 1462 bus_dmamap_sync(ch->dma.workrq_tag, ch->dma.workrq_map, 1463 BUS_DMASYNC_PREWRITE); 1464 bus_dmamap_sync(ch->dma.workrp_tag, ch->dma.workrp_map, 1465 BUS_DMASYNC_PREREAD); 1466 slot->state = MVS_SLOT_RUNNING; 1467 ch->rslots |= (1 << slot->slot); 1468 /* Issue command to the controller. */ 1469 ch->out_idx = (ch->out_idx + 1) & (MVS_MAX_SLOTS - 1); 1470 ATA_OUTL(ch->r_mem, EDMA_REQQIP, 1471 ch->dma.workrq_bus + MVS_CRQB_OFFSET + (MVS_CRQB_SIZE * ch->out_idx)); 1472 /* Start command execution timeout */ 1473 callout_reset(&slot->timeout, (int)ccb->ccb_h.timeout * hz / 1000, 1474 (timeout_t*)mvs_timeout, slot); 1475 return; 1476 } 1477 1478 /* Must be called with channel locked. */ 1479 static void 1480 mvs_process_timeout(device_t dev) 1481 { 1482 struct mvs_channel *ch = device_get_softc(dev); 1483 int i; 1484 1485 mtx_assert(&ch->mtx, MA_OWNED); 1486 /* Handle the rest of commands. */ 1487 for (i = 0; i < MVS_MAX_SLOTS; i++) { 1488 /* Do we have a running request on slot? */ 1489 if (ch->slot[i].state < MVS_SLOT_RUNNING) 1490 continue; 1491 mvs_end_transaction(&ch->slot[i], MVS_ERR_TIMEOUT); 1492 } 1493 } 1494 1495 /* Must be called with channel locked. */ 1496 static void 1497 mvs_rearm_timeout(device_t dev) 1498 { 1499 struct mvs_channel *ch = device_get_softc(dev); 1500 int i; 1501 1502 mtx_assert(&ch->mtx, MA_OWNED); 1503 for (i = 0; i < MVS_MAX_SLOTS; i++) { 1504 struct mvs_slot *slot = &ch->slot[i]; 1505 1506 /* Do we have a running request on slot? */ 1507 if (slot->state < MVS_SLOT_RUNNING) 1508 continue; 1509 if ((ch->toslots & (1 << i)) == 0) 1510 continue; 1511 callout_reset(&slot->timeout, 1512 (int)slot->ccb->ccb_h.timeout * hz / 2000, 1513 (timeout_t*)mvs_timeout, slot); 1514 } 1515 } 1516 1517 /* Locked by callout mechanism. */ 1518 static void 1519 mvs_timeout(struct mvs_slot *slot) 1520 { 1521 device_t dev = slot->dev; 1522 struct mvs_channel *ch = device_get_softc(dev); 1523 1524 /* Check for stale timeout. */ 1525 if (slot->state < MVS_SLOT_RUNNING) 1526 return; 1527 device_printf(dev, "Timeout on slot %d\n", slot->slot); 1528 device_printf(dev, "iec %08x sstat %08x serr %08x edma_s %08x " 1529 "dma_c %08x dma_s %08x rs %08x status %02x\n", 1530 ATA_INL(ch->r_mem, EDMA_IEC), 1531 ATA_INL(ch->r_mem, SATA_SS), ATA_INL(ch->r_mem, SATA_SE), 1532 ATA_INL(ch->r_mem, EDMA_S), ATA_INL(ch->r_mem, DMA_C), 1533 ATA_INL(ch->r_mem, DMA_S), ch->rslots, 1534 ATA_INB(ch->r_mem, ATA_ALTSTAT)); 1535 /* Handle frozen command. */ 1536 mvs_requeue_frozen(dev); 1537 /* We wait for other commands timeout and pray. */ 1538 if (ch->toslots == 0) 1539 xpt_freeze_simq(ch->sim, 1); 1540 ch->toslots |= (1 << slot->slot); 1541 if ((ch->rslots & ~ch->toslots) == 0) 1542 mvs_process_timeout(dev); 1543 else 1544 device_printf(dev, " ... waiting for slots %08x\n", 1545 ch->rslots & ~ch->toslots); 1546 } 1547 1548 /* Must be called with channel locked. */ 1549 static void 1550 mvs_end_transaction(struct mvs_slot *slot, enum mvs_err_type et) 1551 { 1552 device_t dev = slot->dev; 1553 struct mvs_channel *ch = device_get_softc(dev); 1554 union ccb *ccb = slot->ccb; 1555 1556 //device_printf(dev, "cmd done status %d\n", et); 1557 bus_dmamap_sync(ch->dma.workrq_tag, ch->dma.workrq_map, 1558 BUS_DMASYNC_POSTWRITE); 1559 /* Read result registers to the result struct 1560 * May be incorrect if several commands finished same time, 1561 * so read only when sure or have to. 1562 */ 1563 if (ccb->ccb_h.func_code == XPT_ATA_IO) { 1564 struct ata_res *res = &ccb->ataio.res; 1565 1566 if ((et == MVS_ERR_TFE) || 1567 (ccb->ataio.cmd.flags & CAM_ATAIO_NEEDRESULT)) { 1568 mvs_tfd_read(dev, ccb); 1569 } else 1570 bzero(res, sizeof(*res)); 1571 } 1572 if (ch->numpslots == 0 || ch->basic_dma) { 1573 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 1574 bus_dmamap_sync(ch->dma.data_tag, slot->dma.data_map, 1575 (ccb->ccb_h.flags & CAM_DIR_IN) ? 1576 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1577 bus_dmamap_unload(ch->dma.data_tag, slot->dma.data_map); 1578 } 1579 } 1580 if (et != MVS_ERR_NONE) 1581 ch->eslots |= (1 << slot->slot); 1582 /* In case of error, freeze device for proper recovery. */ 1583 if ((et != MVS_ERR_NONE) && (!ch->readlog) && 1584 !(ccb->ccb_h.status & CAM_DEV_QFRZN)) { 1585 xpt_freeze_devq(ccb->ccb_h.path, 1); 1586 ccb->ccb_h.status |= CAM_DEV_QFRZN; 1587 } 1588 /* Set proper result status. */ 1589 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 1590 switch (et) { 1591 case MVS_ERR_NONE: 1592 ccb->ccb_h.status |= CAM_REQ_CMP; 1593 if (ccb->ccb_h.func_code == XPT_SCSI_IO) 1594 ccb->csio.scsi_status = SCSI_STATUS_OK; 1595 break; 1596 case MVS_ERR_INVALID: 1597 ch->fatalerr = 1; 1598 ccb->ccb_h.status |= CAM_REQ_INVALID; 1599 break; 1600 case MVS_ERR_INNOCENT: 1601 ccb->ccb_h.status |= CAM_REQUEUE_REQ; 1602 break; 1603 case MVS_ERR_TFE: 1604 case MVS_ERR_NCQ: 1605 if (ccb->ccb_h.func_code == XPT_SCSI_IO) { 1606 ccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR; 1607 ccb->csio.scsi_status = SCSI_STATUS_CHECK_COND; 1608 } else { 1609 ccb->ccb_h.status |= CAM_ATA_STATUS_ERROR; 1610 } 1611 break; 1612 case MVS_ERR_SATA: 1613 ch->fatalerr = 1; 1614 if (!ch->readlog) { 1615 xpt_freeze_simq(ch->sim, 1); 1616 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 1617 ccb->ccb_h.status |= CAM_RELEASE_SIMQ; 1618 } 1619 ccb->ccb_h.status |= CAM_UNCOR_PARITY; 1620 break; 1621 case MVS_ERR_TIMEOUT: 1622 if (!ch->readlog) { 1623 xpt_freeze_simq(ch->sim, 1); 1624 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 1625 ccb->ccb_h.status |= CAM_RELEASE_SIMQ; 1626 } 1627 ccb->ccb_h.status |= CAM_CMD_TIMEOUT; 1628 break; 1629 default: 1630 ch->fatalerr = 1; 1631 ccb->ccb_h.status |= CAM_REQ_CMP_ERR; 1632 } 1633 /* Free slot. */ 1634 ch->oslots &= ~(1 << slot->slot); 1635 ch->rslots &= ~(1 << slot->slot); 1636 ch->aslots &= ~(1 << slot->slot); 1637 if (et != MVS_ERR_TIMEOUT) { 1638 if (ch->toslots == (1 << slot->slot)) 1639 xpt_release_simq(ch->sim, TRUE); 1640 ch->toslots &= ~(1 << slot->slot); 1641 } 1642 slot->state = MVS_SLOT_EMPTY; 1643 slot->ccb = NULL; 1644 /* Update channel stats. */ 1645 ch->numrslots--; 1646 ch->numrslotspd[ccb->ccb_h.target_id]--; 1647 if (ccb->ccb_h.func_code == XPT_ATA_IO) { 1648 if (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) { 1649 ch->otagspd[ccb->ccb_h.target_id] &= ~(1 << slot->tag); 1650 ch->numtslots--; 1651 ch->numtslotspd[ccb->ccb_h.target_id]--; 1652 } else if (ccb->ataio.cmd.flags & CAM_ATAIO_DMA) { 1653 ch->numdslots--; 1654 } else { 1655 ch->numpslots--; 1656 } 1657 } else { 1658 ch->numpslots--; 1659 ch->basic_dma = 0; 1660 } 1661 /* If it was our READ LOG command - process it. */ 1662 if (ch->readlog) { 1663 mvs_process_read_log(dev, ccb); 1664 /* If it was NCQ command error, put result on hold. */ 1665 } else if (et == MVS_ERR_NCQ) { 1666 ch->hold[slot->slot] = ccb; 1667 ch->holdtag[slot->slot] = slot->tag; 1668 ch->numhslots++; 1669 } else 1670 xpt_done(ccb); 1671 /* Unfreeze frozen command. */ 1672 if (ch->frozen && !mvs_check_collision(dev, ch->frozen)) { 1673 union ccb *fccb = ch->frozen; 1674 ch->frozen = NULL; 1675 mvs_begin_transaction(dev, fccb); 1676 xpt_release_simq(ch->sim, TRUE); 1677 } 1678 /* If we have no other active commands, ... */ 1679 if (ch->rslots == 0) { 1680 /* if there was fatal error - reset port. */ 1681 if (ch->toslots != 0 || ch->fatalerr) { 1682 mvs_reset(dev); 1683 } else { 1684 /* if we have slots in error, we can reinit port. */ 1685 if (ch->eslots != 0) { 1686 mvs_set_edma_mode(dev, MVS_EDMA_OFF); 1687 ch->eslots = 0; 1688 } 1689 /* if there commands on hold, we can do READ LOG. */ 1690 if (!ch->readlog && ch->numhslots) 1691 mvs_issue_read_log(dev); 1692 } 1693 /* If all the rest of commands are in timeout - give them chance. */ 1694 } else if ((ch->rslots & ~ch->toslots) == 0 && 1695 et != MVS_ERR_TIMEOUT) 1696 mvs_rearm_timeout(dev); 1697 /* Start PM timer. */ 1698 if (ch->numrslots == 0 && ch->pm_level > 3 && 1699 (ch->curr[ch->pm_present ? 15 : 0].caps & CTS_SATA_CAPS_D_PMREQ)) { 1700 callout_schedule(&ch->pm_timer, 1701 (ch->pm_level == 4) ? hz / 1000 : hz / 8); 1702 } 1703 } 1704 1705 static void 1706 mvs_issue_read_log(device_t dev) 1707 { 1708 struct mvs_channel *ch = device_get_softc(dev); 1709 union ccb *ccb; 1710 struct ccb_ataio *ataio; 1711 int i; 1712 1713 ch->readlog = 1; 1714 /* Find some holden command. */ 1715 for (i = 0; i < MVS_MAX_SLOTS; i++) { 1716 if (ch->hold[i]) 1717 break; 1718 } 1719 ccb = xpt_alloc_ccb_nowait(); 1720 if (ccb == NULL) { 1721 device_printf(dev, "Unable allocate READ LOG command"); 1722 return; /* XXX */ 1723 } 1724 ccb->ccb_h = ch->hold[i]->ccb_h; /* Reuse old header. */ 1725 ccb->ccb_h.func_code = XPT_ATA_IO; 1726 ccb->ccb_h.flags = CAM_DIR_IN; 1727 ccb->ccb_h.timeout = 1000; /* 1s should be enough. */ 1728 ataio = &ccb->ataio; 1729 ataio->data_ptr = malloc(512, M_MVS, M_NOWAIT); 1730 if (ataio->data_ptr == NULL) { 1731 xpt_free_ccb(ccb); 1732 device_printf(dev, "Unable allocate memory for READ LOG command"); 1733 return; /* XXX */ 1734 } 1735 ataio->dxfer_len = 512; 1736 bzero(&ataio->cmd, sizeof(ataio->cmd)); 1737 ataio->cmd.flags = CAM_ATAIO_48BIT; 1738 ataio->cmd.command = 0x2F; /* READ LOG EXT */ 1739 ataio->cmd.sector_count = 1; 1740 ataio->cmd.sector_count_exp = 0; 1741 ataio->cmd.lba_low = 0x10; 1742 ataio->cmd.lba_mid = 0; 1743 ataio->cmd.lba_mid_exp = 0; 1744 /* Freeze SIM while doing READ LOG EXT. */ 1745 xpt_freeze_simq(ch->sim, 1); 1746 mvs_begin_transaction(dev, ccb); 1747 } 1748 1749 static void 1750 mvs_process_read_log(device_t dev, union ccb *ccb) 1751 { 1752 struct mvs_channel *ch = device_get_softc(dev); 1753 uint8_t *data; 1754 struct ata_res *res; 1755 int i; 1756 1757 ch->readlog = 0; 1758 1759 data = ccb->ataio.data_ptr; 1760 if ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_CMP && 1761 (data[0] & 0x80) == 0) { 1762 for (i = 0; i < MVS_MAX_SLOTS; i++) { 1763 if (!ch->hold[i]) 1764 continue; 1765 if (ch->hold[i]->ccb_h.target_id != ccb->ccb_h.target_id) 1766 continue; 1767 if ((data[0] & 0x1F) == ch->holdtag[i]) { 1768 res = &ch->hold[i]->ataio.res; 1769 res->status = data[2]; 1770 res->error = data[3]; 1771 res->lba_low = data[4]; 1772 res->lba_mid = data[5]; 1773 res->lba_high = data[6]; 1774 res->device = data[7]; 1775 res->lba_low_exp = data[8]; 1776 res->lba_mid_exp = data[9]; 1777 res->lba_high_exp = data[10]; 1778 res->sector_count = data[12]; 1779 res->sector_count_exp = data[13]; 1780 } else { 1781 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK; 1782 ch->hold[i]->ccb_h.status |= CAM_REQUEUE_REQ; 1783 } 1784 xpt_done(ch->hold[i]); 1785 ch->hold[i] = NULL; 1786 ch->numhslots--; 1787 } 1788 } else { 1789 if ((ccb->ccb_h.status & CAM_STATUS_MASK) != CAM_REQ_CMP) 1790 device_printf(dev, "Error while READ LOG EXT\n"); 1791 else if ((data[0] & 0x80) == 0) { 1792 device_printf(dev, "Non-queued command error in READ LOG EXT\n"); 1793 } 1794 for (i = 0; i < MVS_MAX_SLOTS; i++) { 1795 if (!ch->hold[i]) 1796 continue; 1797 if (ch->hold[i]->ccb_h.target_id != ccb->ccb_h.target_id) 1798 continue; 1799 xpt_done(ch->hold[i]); 1800 ch->hold[i] = NULL; 1801 ch->numhslots--; 1802 } 1803 } 1804 free(ccb->ataio.data_ptr, M_MVS); 1805 xpt_free_ccb(ccb); 1806 xpt_release_simq(ch->sim, TRUE); 1807 } 1808 1809 static int 1810 mvs_wait(device_t dev, u_int s, u_int c, int t) 1811 { 1812 int timeout = 0; 1813 uint8_t st; 1814 1815 while (((st = mvs_getstatus(dev, 0)) & (s | c)) != s) { 1816 DELAY(1000); 1817 if (timeout++ > t) { 1818 device_printf(dev, "Wait status %02x\n", st); 1819 return (-1); 1820 } 1821 } 1822 return (timeout); 1823 } 1824 1825 static void 1826 mvs_requeue_frozen(device_t dev) 1827 { 1828 struct mvs_channel *ch = device_get_softc(dev); 1829 union ccb *fccb = ch->frozen; 1830 1831 if (fccb) { 1832 ch->frozen = NULL; 1833 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ; 1834 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) { 1835 xpt_freeze_devq(fccb->ccb_h.path, 1); 1836 fccb->ccb_h.status |= CAM_DEV_QFRZN; 1837 } 1838 xpt_done(fccb); 1839 } 1840 } 1841 1842 static void 1843 mvs_reset(device_t dev) 1844 { 1845 struct mvs_channel *ch = device_get_softc(dev); 1846 int i; 1847 1848 xpt_freeze_simq(ch->sim, 1); 1849 if (bootverbose) 1850 device_printf(dev, "MVS reset...\n"); 1851 /* Requeue freezed command. */ 1852 mvs_requeue_frozen(dev); 1853 /* Kill the engine and requeue all running commands. */ 1854 mvs_set_edma_mode(dev, MVS_EDMA_OFF); 1855 ATA_OUTL(ch->r_mem, DMA_C, 0); 1856 for (i = 0; i < MVS_MAX_SLOTS; i++) { 1857 /* Do we have a running request on slot? */ 1858 if (ch->slot[i].state < MVS_SLOT_RUNNING) 1859 continue; 1860 /* XXX; Commands in loading state. */ 1861 mvs_end_transaction(&ch->slot[i], MVS_ERR_INNOCENT); 1862 } 1863 for (i = 0; i < MVS_MAX_SLOTS; i++) { 1864 if (!ch->hold[i]) 1865 continue; 1866 xpt_done(ch->hold[i]); 1867 ch->hold[i] = NULL; 1868 ch->numhslots--; 1869 } 1870 if (ch->toslots != 0) 1871 xpt_release_simq(ch->sim, TRUE); 1872 ch->eslots = 0; 1873 ch->toslots = 0; 1874 ch->fatalerr = 0; 1875 /* Tell the XPT about the event */ 1876 xpt_async(AC_BUS_RESET, ch->path, NULL); 1877 ATA_OUTL(ch->r_mem, EDMA_IEM, 0); 1878 ATA_OUTL(ch->r_mem, EDMA_CMD, EDMA_CMD_EATARST); 1879 DELAY(25); 1880 ATA_OUTL(ch->r_mem, EDMA_CMD, 0); 1881 /* Reset and reconnect PHY, */ 1882 if (!mvs_sata_phy_reset(dev)) { 1883 if (bootverbose) 1884 device_printf(dev, 1885 "MVS reset done: phy reset found no device\n"); 1886 ch->devices = 0; 1887 ATA_OUTL(ch->r_mem, SATA_SE, 0xffffffff); 1888 ATA_OUTL(ch->r_mem, EDMA_IEC, 0); 1889 ATA_OUTL(ch->r_mem, EDMA_IEM, ~EDMA_IE_TRANSIENT); 1890 xpt_release_simq(ch->sim, TRUE); 1891 return; 1892 } 1893 /* Wait for clearing busy status. */ 1894 if ((i = mvs_wait(dev, 0, ATA_S_BUSY | ATA_S_DRQ, 15000)) < 0) 1895 device_printf(dev, "device is not ready\n"); 1896 else if (bootverbose) 1897 device_printf(dev, "ready wait time=%dms\n", i); 1898 ch->devices = 1; 1899 ATA_OUTL(ch->r_mem, SATA_SE, 0xffffffff); 1900 ATA_OUTL(ch->r_mem, EDMA_IEC, 0); 1901 ATA_OUTL(ch->r_mem, EDMA_IEM, ~EDMA_IE_TRANSIENT); 1902 if (bootverbose) 1903 device_printf(dev, "MVS reset done: device found\n"); 1904 xpt_release_simq(ch->sim, TRUE); 1905 } 1906 1907 static void 1908 mvs_softreset(device_t dev, union ccb *ccb) 1909 { 1910 struct mvs_channel *ch = device_get_softc(dev); 1911 int port = ccb->ccb_h.target_id & 0x0f; 1912 int i; 1913 1914 mvs_set_edma_mode(dev, MVS_EDMA_OFF); 1915 ATA_OUTB(ch->r_mem, SATA_SATAICTL, port << SATA_SATAICTL_PMPTX_SHIFT); 1916 ATA_OUTB(ch->r_mem, ATA_CONTROL, ATA_A_RESET); 1917 DELAY(10000); 1918 ATA_OUTB(ch->r_mem, ATA_CONTROL, 0); 1919 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 1920 /* Wait for clearing busy status. */ 1921 if ((i = mvs_wait(dev, 0, ATA_S_BUSY | ATA_S_DRQ, ccb->ccb_h.timeout)) < 0) { 1922 ccb->ccb_h.status |= CAM_CMD_TIMEOUT; 1923 } else { 1924 ccb->ccb_h.status |= CAM_REQ_CMP; 1925 } 1926 mvs_tfd_read(dev, ccb); 1927 xpt_done(ccb); 1928 } 1929 1930 static int 1931 mvs_sata_connect(struct mvs_channel *ch) 1932 { 1933 u_int32_t status; 1934 int timeout; 1935 1936 /* Wait up to 100ms for "connect well" */ 1937 for (timeout = 0; timeout < 100 ; timeout++) { 1938 status = ATA_INL(ch->r_mem, SATA_SS); 1939 if (((status & SATA_SS_DET_MASK) == SATA_SS_DET_PHY_ONLINE) && 1940 ((status & SATA_SS_SPD_MASK) != SATA_SS_SPD_NO_SPEED) && 1941 ((status & SATA_SS_IPM_MASK) == SATA_SS_IPM_ACTIVE)) 1942 break; 1943 if ((status & SATA_SS_DET_MASK) == SATA_SS_DET_PHY_OFFLINE) { 1944 if (bootverbose) { 1945 device_printf(ch->dev, "SATA offline status=%08x\n", 1946 status); 1947 } 1948 return (0); 1949 } 1950 DELAY(1000); 1951 } 1952 if (timeout >= 100) { 1953 if (bootverbose) { 1954 device_printf(ch->dev, "SATA connect timeout status=%08x\n", 1955 status); 1956 } 1957 return (0); 1958 } 1959 if (bootverbose) { 1960 device_printf(ch->dev, "SATA connect time=%dms status=%08x\n", 1961 timeout, status); 1962 } 1963 /* Clear SATA error register */ 1964 ATA_OUTL(ch->r_mem, SATA_SE, 0xffffffff); 1965 return (1); 1966 } 1967 1968 static int 1969 mvs_sata_phy_reset(device_t dev) 1970 { 1971 struct mvs_channel *ch = device_get_softc(dev); 1972 int sata_rev; 1973 uint32_t val; 1974 1975 sata_rev = ch->user[ch->pm_present ? 15 : 0].revision; 1976 if (sata_rev == 1) 1977 val = SATA_SC_SPD_SPEED_GEN1; 1978 else if (sata_rev == 2) 1979 val = SATA_SC_SPD_SPEED_GEN2; 1980 else if (sata_rev == 3) 1981 val = SATA_SC_SPD_SPEED_GEN3; 1982 else 1983 val = 0; 1984 ATA_OUTL(ch->r_mem, SATA_SC, 1985 SATA_SC_DET_RESET | val | 1986 SATA_SC_IPM_DIS_PARTIAL | SATA_SC_IPM_DIS_SLUMBER); 1987 DELAY(5000); 1988 ATA_OUTL(ch->r_mem, SATA_SC, 1989 SATA_SC_DET_IDLE | val | ((ch->pm_level > 0) ? 0 : 1990 (SATA_SC_IPM_DIS_PARTIAL | SATA_SC_IPM_DIS_SLUMBER))); 1991 DELAY(5000); 1992 if (!mvs_sata_connect(ch)) { 1993 if (ch->pm_level > 0) 1994 ATA_OUTL(ch->r_mem, SATA_SC, SATA_SC_DET_DISABLE); 1995 return (0); 1996 } 1997 return (1); 1998 } 1999 2000 static int 2001 mvs_check_ids(device_t dev, union ccb *ccb) 2002 { 2003 struct mvs_channel *ch = device_get_softc(dev); 2004 2005 if (ccb->ccb_h.target_id > ((ch->quirks & MVS_Q_GENI) ? 0 : 15)) { 2006 ccb->ccb_h.status = CAM_TID_INVALID; 2007 xpt_done(ccb); 2008 return (-1); 2009 } 2010 if (ccb->ccb_h.target_lun != 0) { 2011 ccb->ccb_h.status = CAM_LUN_INVALID; 2012 xpt_done(ccb); 2013 return (-1); 2014 } 2015 return (0); 2016 } 2017 2018 static void 2019 mvsaction(struct cam_sim *sim, union ccb *ccb) 2020 { 2021 device_t dev, parent; 2022 struct mvs_channel *ch; 2023 2024 CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_TRACE, ("mvsaction func_code=%x\n", 2025 ccb->ccb_h.func_code)); 2026 2027 ch = (struct mvs_channel *)cam_sim_softc(sim); 2028 dev = ch->dev; 2029 switch (ccb->ccb_h.func_code) { 2030 /* Common cases first */ 2031 case XPT_ATA_IO: /* Execute the requested I/O operation */ 2032 case XPT_SCSI_IO: 2033 if (mvs_check_ids(dev, ccb)) 2034 return; 2035 if (ch->devices == 0 || 2036 (ch->pm_present == 0 && 2037 ccb->ccb_h.target_id > 0 && ccb->ccb_h.target_id < 15)) { 2038 ccb->ccb_h.status = CAM_SEL_TIMEOUT; 2039 break; 2040 } 2041 /* Check for command collision. */ 2042 if (mvs_check_collision(dev, ccb)) { 2043 /* Freeze command. */ 2044 ch->frozen = ccb; 2045 /* We have only one frozen slot, so freeze simq also. */ 2046 xpt_freeze_simq(ch->sim, 1); 2047 return; 2048 } 2049 mvs_begin_transaction(dev, ccb); 2050 return; 2051 case XPT_EN_LUN: /* Enable LUN as a target */ 2052 case XPT_TARGET_IO: /* Execute target I/O request */ 2053 case XPT_ACCEPT_TARGET_IO: /* Accept Host Target Mode CDB */ 2054 case XPT_CONT_TARGET_IO: /* Continue Host Target I/O Connection*/ 2055 case XPT_ABORT: /* Abort the specified CCB */ 2056 /* XXX Implement */ 2057 ccb->ccb_h.status = CAM_REQ_INVALID; 2058 break; 2059 case XPT_SET_TRAN_SETTINGS: 2060 { 2061 struct ccb_trans_settings *cts = &ccb->cts; 2062 struct mvs_device *d; 2063 2064 if (mvs_check_ids(dev, ccb)) 2065 return; 2066 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) 2067 d = &ch->curr[ccb->ccb_h.target_id]; 2068 else 2069 d = &ch->user[ccb->ccb_h.target_id]; 2070 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_REVISION) 2071 d->revision = cts->xport_specific.sata.revision; 2072 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_MODE) 2073 d->mode = cts->xport_specific.sata.mode; 2074 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_BYTECOUNT) { 2075 d->bytecount = min((ch->quirks & MVS_Q_GENIIE) ? 8192 : 2048, 2076 cts->xport_specific.sata.bytecount); 2077 } 2078 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_TAGS) 2079 d->tags = min(MVS_MAX_SLOTS, cts->xport_specific.sata.tags); 2080 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_PM) 2081 ch->pm_present = cts->xport_specific.sata.pm_present; 2082 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_ATAPI) 2083 d->atapi = cts->xport_specific.sata.atapi; 2084 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_CAPS) 2085 d->caps = cts->xport_specific.sata.caps; 2086 ccb->ccb_h.status = CAM_REQ_CMP; 2087 break; 2088 } 2089 case XPT_GET_TRAN_SETTINGS: 2090 /* Get default/user set transfer settings for the target */ 2091 { 2092 struct ccb_trans_settings *cts = &ccb->cts; 2093 struct mvs_device *d; 2094 uint32_t status; 2095 2096 if (mvs_check_ids(dev, ccb)) 2097 return; 2098 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) 2099 d = &ch->curr[ccb->ccb_h.target_id]; 2100 else 2101 d = &ch->user[ccb->ccb_h.target_id]; 2102 cts->protocol = PROTO_ATA; 2103 cts->protocol_version = PROTO_VERSION_UNSPECIFIED; 2104 cts->transport = XPORT_SATA; 2105 cts->transport_version = XPORT_VERSION_UNSPECIFIED; 2106 cts->proto_specific.valid = 0; 2107 cts->xport_specific.sata.valid = 0; 2108 if (cts->type == CTS_TYPE_CURRENT_SETTINGS && 2109 (ccb->ccb_h.target_id == 15 || 2110 (ccb->ccb_h.target_id == 0 && !ch->pm_present))) { 2111 status = ATA_INL(ch->r_mem, SATA_SS) & SATA_SS_SPD_MASK; 2112 if (status & 0x0f0) { 2113 cts->xport_specific.sata.revision = 2114 (status & 0x0f0) >> 4; 2115 cts->xport_specific.sata.valid |= 2116 CTS_SATA_VALID_REVISION; 2117 } 2118 cts->xport_specific.sata.caps = d->caps & CTS_SATA_CAPS_D; 2119 // if (ch->pm_level) 2120 // cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_PMREQ; 2121 cts->xport_specific.sata.caps &= 2122 ch->user[ccb->ccb_h.target_id].caps; 2123 cts->xport_specific.sata.valid |= CTS_SATA_VALID_CAPS; 2124 } else { 2125 cts->xport_specific.sata.revision = d->revision; 2126 cts->xport_specific.sata.valid |= CTS_SATA_VALID_REVISION; 2127 cts->xport_specific.sata.caps = d->caps; 2128 cts->xport_specific.sata.valid |= CTS_SATA_VALID_CAPS; 2129 } 2130 cts->xport_specific.sata.mode = d->mode; 2131 cts->xport_specific.sata.valid |= CTS_SATA_VALID_MODE; 2132 cts->xport_specific.sata.bytecount = d->bytecount; 2133 cts->xport_specific.sata.valid |= CTS_SATA_VALID_BYTECOUNT; 2134 cts->xport_specific.sata.pm_present = ch->pm_present; 2135 cts->xport_specific.sata.valid |= CTS_SATA_VALID_PM; 2136 cts->xport_specific.sata.tags = d->tags; 2137 cts->xport_specific.sata.valid |= CTS_SATA_VALID_TAGS; 2138 cts->xport_specific.sata.atapi = d->atapi; 2139 cts->xport_specific.sata.valid |= CTS_SATA_VALID_ATAPI; 2140 ccb->ccb_h.status = CAM_REQ_CMP; 2141 break; 2142 } 2143 case XPT_RESET_BUS: /* Reset the specified SCSI bus */ 2144 case XPT_RESET_DEV: /* Bus Device Reset the specified SCSI device */ 2145 mvs_reset(dev); 2146 ccb->ccb_h.status = CAM_REQ_CMP; 2147 break; 2148 case XPT_TERM_IO: /* Terminate the I/O process */ 2149 /* XXX Implement */ 2150 ccb->ccb_h.status = CAM_REQ_INVALID; 2151 break; 2152 case XPT_PATH_INQ: /* Path routing inquiry */ 2153 { 2154 struct ccb_pathinq *cpi = &ccb->cpi; 2155 2156 parent = device_get_parent(dev); 2157 cpi->version_num = 1; /* XXX??? */ 2158 cpi->hba_inquiry = PI_SDTR_ABLE; 2159 if (!(ch->quirks & MVS_Q_GENI)) { 2160 cpi->hba_inquiry |= PI_SATAPM; 2161 /* Gen-II is extremely slow with NCQ on PMP. */ 2162 if ((ch->quirks & MVS_Q_GENIIE) || ch->pm_present == 0) 2163 cpi->hba_inquiry |= PI_TAG_ABLE; 2164 } 2165 cpi->target_sprt = 0; 2166 cpi->hba_misc = PIM_SEQSCAN; 2167 cpi->hba_eng_cnt = 0; 2168 if (!(ch->quirks & MVS_Q_GENI)) 2169 cpi->max_target = 15; 2170 else 2171 cpi->max_target = 0; 2172 cpi->max_lun = 0; 2173 cpi->initiator_id = 0; 2174 cpi->bus_id = cam_sim_bus(sim); 2175 cpi->base_transfer_speed = 150000; 2176 strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN); 2177 strncpy(cpi->hba_vid, "Marvell", HBA_IDLEN); 2178 strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN); 2179 cpi->unit_number = cam_sim_unit(sim); 2180 cpi->transport = XPORT_SATA; 2181 cpi->transport_version = XPORT_VERSION_UNSPECIFIED; 2182 cpi->protocol = PROTO_ATA; 2183 cpi->protocol_version = PROTO_VERSION_UNSPECIFIED; 2184 cpi->maxio = MAXPHYS; 2185 if ((ch->quirks & MVS_Q_SOC) == 0) { 2186 cpi->hba_vendor = pci_get_vendor(parent); 2187 cpi->hba_device = pci_get_device(parent); 2188 cpi->hba_subvendor = pci_get_subvendor(parent); 2189 cpi->hba_subdevice = pci_get_subdevice(parent); 2190 } 2191 cpi->ccb_h.status = CAM_REQ_CMP; 2192 break; 2193 } 2194 default: 2195 ccb->ccb_h.status = CAM_REQ_INVALID; 2196 break; 2197 } 2198 xpt_done(ccb); 2199 } 2200 2201 static void 2202 mvspoll(struct cam_sim *sim) 2203 { 2204 struct mvs_channel *ch = (struct mvs_channel *)cam_sim_softc(sim); 2205 struct mvs_intr_arg arg; 2206 2207 arg.arg = ch->dev; 2208 arg.cause = 2; /* XXX */ 2209 mvs_ch_intr(&arg); 2210 } 2211 2212