xref: /freebsd/sys/dev/mvs/mvs.c (revision aa77200569e397d6ff1fdb4d255d0fa254d0a128)
1 /*-
2  * Copyright (c) 2010 Alexander Motin <mav@FreeBSD.org>
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
7  * are met:
8  * 1. Redistributions of source code must retain the above copyright
9  *    notice, this list of conditions and the following disclaimer,
10  *    without modification, immediately at the beginning of the file.
11  * 2. Redistributions in binary form must reproduce the above copyright
12  *    notice, this list of conditions and the following disclaimer in the
13  *    documentation and/or other materials provided with the distribution.
14  *
15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25  */
26 
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
29 
30 #include <sys/param.h>
31 #include <sys/module.h>
32 #include <sys/systm.h>
33 #include <sys/kernel.h>
34 #include <sys/ata.h>
35 #include <sys/bus.h>
36 #include <sys/conf.h>
37 #include <sys/endian.h>
38 #include <sys/malloc.h>
39 #include <sys/lock.h>
40 #include <sys/mutex.h>
41 #include <vm/uma.h>
42 #include <machine/stdarg.h>
43 #include <machine/resource.h>
44 #include <machine/bus.h>
45 #include <sys/rman.h>
46 #include <dev/pci/pcivar.h>
47 #include "mvs.h"
48 
49 #include <cam/cam.h>
50 #include <cam/cam_ccb.h>
51 #include <cam/cam_sim.h>
52 #include <cam/cam_xpt_sim.h>
53 #include <cam/cam_debug.h>
54 
55 /* local prototypes */
56 static int mvs_ch_init(device_t dev);
57 static int mvs_ch_deinit(device_t dev);
58 static int mvs_ch_suspend(device_t dev);
59 static int mvs_ch_resume(device_t dev);
60 static void mvs_dmainit(device_t dev);
61 static void mvs_dmasetupc_cb(void *xsc,
62 	bus_dma_segment_t *segs, int nsegs, int error);
63 static void mvs_dmafini(device_t dev);
64 static void mvs_slotsalloc(device_t dev);
65 static void mvs_slotsfree(device_t dev);
66 static void mvs_setup_edma_queues(device_t dev);
67 static void mvs_set_edma_mode(device_t dev, enum mvs_edma_mode mode);
68 static void mvs_ch_pm(void *arg);
69 static void mvs_ch_intr_locked(void *data);
70 static void mvs_ch_intr(void *data);
71 static void mvs_reset(device_t dev);
72 static void mvs_softreset(device_t dev, union ccb *ccb);
73 
74 static int mvs_sata_connect(struct mvs_channel *ch);
75 static int mvs_sata_phy_reset(device_t dev);
76 static int mvs_wait(device_t dev, u_int s, u_int c, int t);
77 static void mvs_tfd_read(device_t dev, union ccb *ccb);
78 static void mvs_tfd_write(device_t dev, union ccb *ccb);
79 static void mvs_legacy_intr(device_t dev, int poll);
80 static void mvs_crbq_intr(device_t dev);
81 static void mvs_begin_transaction(device_t dev, union ccb *ccb);
82 static void mvs_legacy_execute_transaction(struct mvs_slot *slot);
83 static void mvs_timeout(struct mvs_slot *slot);
84 static void mvs_dmasetprd(void *arg,
85 	bus_dma_segment_t *segs, int nsegs, int error);
86 static void mvs_requeue_frozen(device_t dev);
87 static void mvs_execute_transaction(struct mvs_slot *slot);
88 static void mvs_end_transaction(struct mvs_slot *slot, enum mvs_err_type et);
89 
90 static void mvs_issue_recovery(device_t dev);
91 static void mvs_process_read_log(device_t dev, union ccb *ccb);
92 static void mvs_process_request_sense(device_t dev, union ccb *ccb);
93 
94 static void mvsaction(struct cam_sim *sim, union ccb *ccb);
95 static void mvspoll(struct cam_sim *sim);
96 
97 static MALLOC_DEFINE(M_MVS, "MVS driver", "MVS driver data buffers");
98 
99 #define recovery_type		spriv_field0
100 #define RECOVERY_NONE		0
101 #define RECOVERY_READ_LOG	1
102 #define RECOVERY_REQUEST_SENSE	2
103 #define recovery_slot		spriv_field1
104 
105 static int
106 mvs_ch_probe(device_t dev)
107 {
108 
109 	device_set_desc_copy(dev, "Marvell SATA channel");
110 	return (0);
111 }
112 
113 static int
114 mvs_ch_attach(device_t dev)
115 {
116 	struct mvs_controller *ctlr = device_get_softc(device_get_parent(dev));
117 	struct mvs_channel *ch = device_get_softc(dev);
118 	struct cam_devq *devq;
119 	int rid, error, i, sata_rev = 0;
120 
121 	ch->dev = dev;
122 	ch->unit = (intptr_t)device_get_ivars(dev);
123 	ch->quirks = ctlr->quirks;
124 	mtx_init(&ch->mtx, "MVS channel lock", NULL, MTX_DEF);
125 	resource_int_value(device_get_name(dev),
126 	    device_get_unit(dev), "pm_level", &ch->pm_level);
127 	if (ch->pm_level > 3)
128 		callout_init_mtx(&ch->pm_timer, &ch->mtx, 0);
129 	callout_init_mtx(&ch->reset_timer, &ch->mtx, 0);
130 	resource_int_value(device_get_name(dev),
131 	    device_get_unit(dev), "sata_rev", &sata_rev);
132 	for (i = 0; i < 16; i++) {
133 		ch->user[i].revision = sata_rev;
134 		ch->user[i].mode = 0;
135 		ch->user[i].bytecount = (ch->quirks & MVS_Q_GENIIE) ? 8192 : 2048;
136 		ch->user[i].tags = MVS_MAX_SLOTS;
137 		ch->curr[i] = ch->user[i];
138 		if (ch->pm_level) {
139 			ch->user[i].caps = CTS_SATA_CAPS_H_PMREQ |
140 			    CTS_SATA_CAPS_H_APST |
141 			    CTS_SATA_CAPS_D_PMREQ | CTS_SATA_CAPS_D_APST;
142 		}
143 		ch->user[i].caps |= CTS_SATA_CAPS_H_AN;
144 	}
145 	rid = ch->unit;
146 	if (!(ch->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
147 	    &rid, RF_ACTIVE)))
148 		return (ENXIO);
149 	mvs_dmainit(dev);
150 	mvs_slotsalloc(dev);
151 	mvs_ch_init(dev);
152 	mtx_lock(&ch->mtx);
153 	rid = ATA_IRQ_RID;
154 	if (!(ch->r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
155 	    &rid, RF_SHAREABLE | RF_ACTIVE))) {
156 		device_printf(dev, "Unable to map interrupt\n");
157 		error = ENXIO;
158 		goto err0;
159 	}
160 	if ((bus_setup_intr(dev, ch->r_irq, ATA_INTR_FLAGS, NULL,
161 	    mvs_ch_intr_locked, dev, &ch->ih))) {
162 		device_printf(dev, "Unable to setup interrupt\n");
163 		error = ENXIO;
164 		goto err1;
165 	}
166 	/* Create the device queue for our SIM. */
167 	devq = cam_simq_alloc(MVS_MAX_SLOTS - 1);
168 	if (devq == NULL) {
169 		device_printf(dev, "Unable to allocate simq\n");
170 		error = ENOMEM;
171 		goto err1;
172 	}
173 	/* Construct SIM entry */
174 	ch->sim = cam_sim_alloc(mvsaction, mvspoll, "mvsch", ch,
175 	    device_get_unit(dev), &ch->mtx,
176 	    2, (ch->quirks & MVS_Q_GENI) ? 0 : MVS_MAX_SLOTS - 1,
177 	    devq);
178 	if (ch->sim == NULL) {
179 		cam_simq_free(devq);
180 		device_printf(dev, "unable to allocate sim\n");
181 		error = ENOMEM;
182 		goto err1;
183 	}
184 	if (xpt_bus_register(ch->sim, dev, 0) != CAM_SUCCESS) {
185 		device_printf(dev, "unable to register xpt bus\n");
186 		error = ENXIO;
187 		goto err2;
188 	}
189 	if (xpt_create_path(&ch->path, /*periph*/NULL, cam_sim_path(ch->sim),
190 	    CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) {
191 		device_printf(dev, "unable to create path\n");
192 		error = ENXIO;
193 		goto err3;
194 	}
195 	if (ch->pm_level > 3) {
196 		callout_reset(&ch->pm_timer,
197 		    (ch->pm_level == 4) ? hz / 1000 : hz / 8,
198 		    mvs_ch_pm, dev);
199 	}
200 	mtx_unlock(&ch->mtx);
201 	return (0);
202 
203 err3:
204 	xpt_bus_deregister(cam_sim_path(ch->sim));
205 err2:
206 	cam_sim_free(ch->sim, /*free_devq*/TRUE);
207 err1:
208 	bus_release_resource(dev, SYS_RES_IRQ, ATA_IRQ_RID, ch->r_irq);
209 err0:
210 	bus_release_resource(dev, SYS_RES_MEMORY, ch->unit, ch->r_mem);
211 	mtx_unlock(&ch->mtx);
212 	mtx_destroy(&ch->mtx);
213 	return (error);
214 }
215 
216 static int
217 mvs_ch_detach(device_t dev)
218 {
219 	struct mvs_channel *ch = device_get_softc(dev);
220 
221 	mtx_lock(&ch->mtx);
222 	xpt_async(AC_LOST_DEVICE, ch->path, NULL);
223 	/* Forget about reset. */
224 	if (ch->resetting) {
225 		ch->resetting = 0;
226 		xpt_release_simq(ch->sim, TRUE);
227 	}
228 	xpt_free_path(ch->path);
229 	xpt_bus_deregister(cam_sim_path(ch->sim));
230 	cam_sim_free(ch->sim, /*free_devq*/TRUE);
231 	mtx_unlock(&ch->mtx);
232 
233 	if (ch->pm_level > 3)
234 		callout_drain(&ch->pm_timer);
235 	callout_drain(&ch->reset_timer);
236 	bus_teardown_intr(dev, ch->r_irq, ch->ih);
237 	bus_release_resource(dev, SYS_RES_IRQ, ATA_IRQ_RID, ch->r_irq);
238 
239 	mvs_ch_deinit(dev);
240 	mvs_slotsfree(dev);
241 	mvs_dmafini(dev);
242 
243 	bus_release_resource(dev, SYS_RES_MEMORY, ch->unit, ch->r_mem);
244 	mtx_destroy(&ch->mtx);
245 	return (0);
246 }
247 
248 static int
249 mvs_ch_init(device_t dev)
250 {
251 	struct mvs_channel *ch = device_get_softc(dev);
252 	uint32_t reg;
253 
254 	/* Disable port interrupts */
255 	ATA_OUTL(ch->r_mem, EDMA_IEM, 0);
256 	/* Stop EDMA */
257 	ch->curr_mode = MVS_EDMA_UNKNOWN;
258 	mvs_set_edma_mode(dev, MVS_EDMA_OFF);
259 	/* Clear and configure FIS interrupts. */
260 	ATA_OUTL(ch->r_mem, SATA_FISIC, 0);
261 	reg = ATA_INL(ch->r_mem, SATA_FISC);
262 	reg |= SATA_FISC_FISWAIT4HOSTRDYEN_B1;
263 	ATA_OUTL(ch->r_mem, SATA_FISC, reg);
264 	reg = ATA_INL(ch->r_mem, SATA_FISIM);
265 	reg |= SATA_FISC_FISWAIT4HOSTRDYEN_B1;
266 	ATA_OUTL(ch->r_mem, SATA_FISC, reg);
267 	/* Clear SATA error register. */
268 	ATA_OUTL(ch->r_mem, SATA_SE, 0xffffffff);
269 	/* Clear any outstanding error interrupts. */
270 	ATA_OUTL(ch->r_mem, EDMA_IEC, 0);
271 	/* Unmask all error interrupts */
272 	ATA_OUTL(ch->r_mem, EDMA_IEM, ~EDMA_IE_TRANSIENT);
273 	return (0);
274 }
275 
276 static int
277 mvs_ch_deinit(device_t dev)
278 {
279 	struct mvs_channel *ch = device_get_softc(dev);
280 
281 	/* Stop EDMA */
282 	mvs_set_edma_mode(dev, MVS_EDMA_OFF);
283 	/* Disable port interrupts. */
284 	ATA_OUTL(ch->r_mem, EDMA_IEM, 0);
285 	return (0);
286 }
287 
288 static int
289 mvs_ch_suspend(device_t dev)
290 {
291 	struct mvs_channel *ch = device_get_softc(dev);
292 
293 	mtx_lock(&ch->mtx);
294 	xpt_freeze_simq(ch->sim, 1);
295 	while (ch->oslots)
296 		msleep(ch, &ch->mtx, PRIBIO, "mvssusp", hz/100);
297 	/* Forget about reset. */
298 	if (ch->resetting) {
299 		ch->resetting = 0;
300 		callout_stop(&ch->reset_timer);
301 		xpt_release_simq(ch->sim, TRUE);
302 	}
303 	mvs_ch_deinit(dev);
304 	mtx_unlock(&ch->mtx);
305 	return (0);
306 }
307 
308 static int
309 mvs_ch_resume(device_t dev)
310 {
311 	struct mvs_channel *ch = device_get_softc(dev);
312 
313 	mtx_lock(&ch->mtx);
314 	mvs_ch_init(dev);
315 	mvs_reset(dev);
316 	xpt_release_simq(ch->sim, TRUE);
317 	mtx_unlock(&ch->mtx);
318 	return (0);
319 }
320 
321 struct mvs_dc_cb_args {
322 	bus_addr_t maddr;
323 	int error;
324 };
325 
326 static void
327 mvs_dmainit(device_t dev)
328 {
329 	struct mvs_channel *ch = device_get_softc(dev);
330 	struct mvs_dc_cb_args dcba;
331 
332 	/* EDMA command request area. */
333 	if (bus_dma_tag_create(bus_get_dma_tag(dev), 1024, 0,
334 	    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
335 	    NULL, NULL, MVS_WORKRQ_SIZE, 1, MVS_WORKRQ_SIZE,
336 	    0, NULL, NULL, &ch->dma.workrq_tag))
337 		goto error;
338 	if (bus_dmamem_alloc(ch->dma.workrq_tag, (void **)&ch->dma.workrq, 0,
339 	    &ch->dma.workrq_map))
340 		goto error;
341 	if (bus_dmamap_load(ch->dma.workrq_tag, ch->dma.workrq_map,
342 	    ch->dma.workrq, MVS_WORKRQ_SIZE, mvs_dmasetupc_cb, &dcba, 0) ||
343 	    dcba.error) {
344 		bus_dmamem_free(ch->dma.workrq_tag,
345 		    ch->dma.workrq, ch->dma.workrq_map);
346 		goto error;
347 	}
348 	ch->dma.workrq_bus = dcba.maddr;
349 	/* EDMA command response area. */
350 	if (bus_dma_tag_create(bus_get_dma_tag(dev), 256, 0,
351 	    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
352 	    NULL, NULL, MVS_WORKRP_SIZE, 1, MVS_WORKRP_SIZE,
353 	    0, NULL, NULL, &ch->dma.workrp_tag))
354 		goto error;
355 	if (bus_dmamem_alloc(ch->dma.workrp_tag, (void **)&ch->dma.workrp, 0,
356 	    &ch->dma.workrp_map))
357 		goto error;
358 	if (bus_dmamap_load(ch->dma.workrp_tag, ch->dma.workrp_map,
359 	    ch->dma.workrp, MVS_WORKRP_SIZE, mvs_dmasetupc_cb, &dcba, 0) ||
360 	    dcba.error) {
361 		bus_dmamem_free(ch->dma.workrp_tag,
362 		    ch->dma.workrp, ch->dma.workrp_map);
363 		goto error;
364 	}
365 	ch->dma.workrp_bus = dcba.maddr;
366 	/* Data area. */
367 	if (bus_dma_tag_create(bus_get_dma_tag(dev), 2, MVS_EPRD_MAX,
368 	    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
369 	    NULL, NULL,
370 	    MVS_SG_ENTRIES * PAGE_SIZE * MVS_MAX_SLOTS,
371 	    MVS_SG_ENTRIES, MVS_EPRD_MAX,
372 	    0, busdma_lock_mutex, &ch->mtx, &ch->dma.data_tag)) {
373 		goto error;
374 	}
375 	return;
376 
377 error:
378 	device_printf(dev, "WARNING - DMA initialization failed\n");
379 	mvs_dmafini(dev);
380 }
381 
382 static void
383 mvs_dmasetupc_cb(void *xsc, bus_dma_segment_t *segs, int nsegs, int error)
384 {
385 	struct mvs_dc_cb_args *dcba = (struct mvs_dc_cb_args *)xsc;
386 
387 	if (!(dcba->error = error))
388 		dcba->maddr = segs[0].ds_addr;
389 }
390 
391 static void
392 mvs_dmafini(device_t dev)
393 {
394 	struct mvs_channel *ch = device_get_softc(dev);
395 
396 	if (ch->dma.data_tag) {
397 		bus_dma_tag_destroy(ch->dma.data_tag);
398 		ch->dma.data_tag = NULL;
399 	}
400 	if (ch->dma.workrp_bus) {
401 		bus_dmamap_unload(ch->dma.workrp_tag, ch->dma.workrp_map);
402 		bus_dmamem_free(ch->dma.workrp_tag,
403 		    ch->dma.workrp, ch->dma.workrp_map);
404 		ch->dma.workrp_bus = 0;
405 		ch->dma.workrp_map = NULL;
406 		ch->dma.workrp = NULL;
407 	}
408 	if (ch->dma.workrp_tag) {
409 		bus_dma_tag_destroy(ch->dma.workrp_tag);
410 		ch->dma.workrp_tag = NULL;
411 	}
412 	if (ch->dma.workrq_bus) {
413 		bus_dmamap_unload(ch->dma.workrq_tag, ch->dma.workrq_map);
414 		bus_dmamem_free(ch->dma.workrq_tag,
415 		    ch->dma.workrq, ch->dma.workrq_map);
416 		ch->dma.workrq_bus = 0;
417 		ch->dma.workrq_map = NULL;
418 		ch->dma.workrq = NULL;
419 	}
420 	if (ch->dma.workrq_tag) {
421 		bus_dma_tag_destroy(ch->dma.workrq_tag);
422 		ch->dma.workrq_tag = NULL;
423 	}
424 }
425 
426 static void
427 mvs_slotsalloc(device_t dev)
428 {
429 	struct mvs_channel *ch = device_get_softc(dev);
430 	int i;
431 
432 	/* Alloc and setup command/dma slots */
433 	bzero(ch->slot, sizeof(ch->slot));
434 	for (i = 0; i < MVS_MAX_SLOTS; i++) {
435 		struct mvs_slot *slot = &ch->slot[i];
436 
437 		slot->dev = dev;
438 		slot->slot = i;
439 		slot->state = MVS_SLOT_EMPTY;
440 		slot->ccb = NULL;
441 		callout_init_mtx(&slot->timeout, &ch->mtx, 0);
442 
443 		if (bus_dmamap_create(ch->dma.data_tag, 0, &slot->dma.data_map))
444 			device_printf(ch->dev, "FAILURE - create data_map\n");
445 	}
446 }
447 
448 static void
449 mvs_slotsfree(device_t dev)
450 {
451 	struct mvs_channel *ch = device_get_softc(dev);
452 	int i;
453 
454 	/* Free all dma slots */
455 	for (i = 0; i < MVS_MAX_SLOTS; i++) {
456 		struct mvs_slot *slot = &ch->slot[i];
457 
458 		callout_drain(&slot->timeout);
459 		if (slot->dma.data_map) {
460 			bus_dmamap_destroy(ch->dma.data_tag, slot->dma.data_map);
461 			slot->dma.data_map = NULL;
462 		}
463 	}
464 }
465 
466 static void
467 mvs_setup_edma_queues(device_t dev)
468 {
469 	struct mvs_channel *ch = device_get_softc(dev);
470 	uint64_t work;
471 
472 	/* Requests queue. */
473 	work = ch->dma.workrq_bus;
474 	ATA_OUTL(ch->r_mem, EDMA_REQQBAH, work >> 32);
475 	ATA_OUTL(ch->r_mem, EDMA_REQQIP, work & 0xffffffff);
476 	ATA_OUTL(ch->r_mem, EDMA_REQQOP, work & 0xffffffff);
477 	bus_dmamap_sync(ch->dma.workrq_tag, ch->dma.workrq_map,
478 	    BUS_DMASYNC_PREWRITE);
479 	/* Reponses queue. */
480 	memset(ch->dma.workrp, 0xff, MVS_WORKRP_SIZE);
481 	work = ch->dma.workrp_bus;
482 	ATA_OUTL(ch->r_mem, EDMA_RESQBAH, work >> 32);
483 	ATA_OUTL(ch->r_mem, EDMA_RESQIP, work & 0xffffffff);
484 	ATA_OUTL(ch->r_mem, EDMA_RESQOP, work & 0xffffffff);
485 	bus_dmamap_sync(ch->dma.workrp_tag, ch->dma.workrp_map,
486 	    BUS_DMASYNC_PREREAD);
487 	ch->out_idx = 0;
488 	ch->in_idx = 0;
489 }
490 
491 static void
492 mvs_set_edma_mode(device_t dev, enum mvs_edma_mode mode)
493 {
494 	struct mvs_channel *ch = device_get_softc(dev);
495 	int timeout;
496 	uint32_t ecfg, fcfg, hc, ltm, unkn;
497 
498 	if (mode == ch->curr_mode)
499 		return;
500 	/* If we are running, we should stop first. */
501 	if (ch->curr_mode != MVS_EDMA_OFF) {
502 		ATA_OUTL(ch->r_mem, EDMA_CMD, EDMA_CMD_EDSEDMA);
503 		timeout = 0;
504 		while (ATA_INL(ch->r_mem, EDMA_CMD) & EDMA_CMD_EENEDMA) {
505 			DELAY(1000);
506 			if (timeout++ > 1000) {
507 				device_printf(dev, "stopping EDMA engine failed\n");
508 				break;
509 			}
510 		};
511 	}
512 	ch->curr_mode = mode;
513 	ch->fbs_enabled = 0;
514 	ch->fake_busy = 0;
515 	/* Report mode to controller. Needed for correct CCC operation. */
516 	MVS_EDMA(device_get_parent(dev), dev, mode);
517 	/* Configure new mode. */
518 	ecfg = EDMA_CFG_RESERVED | EDMA_CFG_RESERVED2 | EDMA_CFG_EHOSTQUEUECACHEEN;
519 	if (ch->pm_present) {
520 		ecfg |= EDMA_CFG_EMASKRXPM;
521 		if (ch->quirks & MVS_Q_GENIIE) {
522 			ecfg |= EDMA_CFG_EEDMAFBS;
523 			ch->fbs_enabled = 1;
524 		}
525 	}
526 	if (ch->quirks & MVS_Q_GENI)
527 		ecfg |= EDMA_CFG_ERDBSZ;
528 	else if (ch->quirks & MVS_Q_GENII)
529 		ecfg |= EDMA_CFG_ERDBSZEXT | EDMA_CFG_EWRBUFFERLEN;
530 	if (ch->quirks & MVS_Q_CT)
531 		ecfg |= EDMA_CFG_ECUTTHROUGHEN;
532 	if (mode != MVS_EDMA_OFF)
533 		ecfg |= EDMA_CFG_EEARLYCOMPLETIONEN;
534 	if (mode == MVS_EDMA_QUEUED)
535 		ecfg |= EDMA_CFG_EQUE;
536 	else if (mode == MVS_EDMA_NCQ)
537 		ecfg |= EDMA_CFG_ESATANATVCMDQUE;
538 	ATA_OUTL(ch->r_mem, EDMA_CFG, ecfg);
539 	mvs_setup_edma_queues(dev);
540 	if (ch->quirks & MVS_Q_GENIIE) {
541 		/* Configure FBS-related registers */
542 		fcfg = ATA_INL(ch->r_mem, SATA_FISC);
543 		ltm = ATA_INL(ch->r_mem, SATA_LTM);
544 		hc = ATA_INL(ch->r_mem, EDMA_HC);
545 		if (ch->fbs_enabled) {
546 			fcfg |= SATA_FISC_FISDMAACTIVATESYNCRESP;
547 			if (mode == MVS_EDMA_NCQ) {
548 				fcfg &= ~SATA_FISC_FISWAIT4HOSTRDYEN_B0;
549 				hc &= ~EDMA_IE_EDEVERR;
550 			} else {
551 				fcfg |= SATA_FISC_FISWAIT4HOSTRDYEN_B0;
552 				hc |= EDMA_IE_EDEVERR;
553 			}
554 			ltm |= (1 << 8);
555 		} else {
556 			fcfg &= ~SATA_FISC_FISDMAACTIVATESYNCRESP;
557 			fcfg &= ~SATA_FISC_FISWAIT4HOSTRDYEN_B0;
558 			hc |= EDMA_IE_EDEVERR;
559 			ltm &= ~(1 << 8);
560 		}
561 		ATA_OUTL(ch->r_mem, SATA_FISC, fcfg);
562 		ATA_OUTL(ch->r_mem, SATA_LTM, ltm);
563 		ATA_OUTL(ch->r_mem, EDMA_HC, hc);
564 		/* This is some magic, required to handle several DRQs
565 		 * with basic DMA. */
566 		unkn = ATA_INL(ch->r_mem, EDMA_UNKN_RESD);
567 		if (mode == MVS_EDMA_OFF)
568 			unkn |= 1;
569 		else
570 			unkn &= ~1;
571 		ATA_OUTL(ch->r_mem, EDMA_UNKN_RESD, unkn);
572 	}
573 	/* Run EDMA. */
574 	if (mode != MVS_EDMA_OFF)
575 		ATA_OUTL(ch->r_mem, EDMA_CMD, EDMA_CMD_EENEDMA);
576 }
577 
578 devclass_t mvs_devclass;
579 devclass_t mvsch_devclass;
580 static device_method_t mvsch_methods[] = {
581 	DEVMETHOD(device_probe,     mvs_ch_probe),
582 	DEVMETHOD(device_attach,    mvs_ch_attach),
583 	DEVMETHOD(device_detach,    mvs_ch_detach),
584 	DEVMETHOD(device_suspend,   mvs_ch_suspend),
585 	DEVMETHOD(device_resume,    mvs_ch_resume),
586 	{ 0, 0 }
587 };
588 static driver_t mvsch_driver = {
589         "mvsch",
590         mvsch_methods,
591         sizeof(struct mvs_channel)
592 };
593 DRIVER_MODULE(mvsch, mvs, mvsch_driver, mvsch_devclass, 0, 0);
594 DRIVER_MODULE(mvsch, sata, mvsch_driver, mvsch_devclass, 0, 0);
595 
596 static void
597 mvs_phy_check_events(device_t dev, u_int32_t serr)
598 {
599 	struct mvs_channel *ch = device_get_softc(dev);
600 
601 	if (ch->pm_level == 0) {
602 		u_int32_t status = ATA_INL(ch->r_mem, SATA_SS);
603 		union ccb *ccb;
604 
605 		if (bootverbose) {
606 			if (((status & SATA_SS_DET_MASK) == SATA_SS_DET_PHY_ONLINE) &&
607 			    ((status & SATA_SS_SPD_MASK) != SATA_SS_SPD_NO_SPEED) &&
608 			    ((status & SATA_SS_IPM_MASK) == SATA_SS_IPM_ACTIVE)) {
609 				device_printf(dev, "CONNECT requested\n");
610 			} else
611 				device_printf(dev, "DISCONNECT requested\n");
612 		}
613 		mvs_reset(dev);
614 		if ((ccb = xpt_alloc_ccb_nowait()) == NULL)
615 			return;
616 		if (xpt_create_path(&ccb->ccb_h.path, NULL,
617 		    cam_sim_path(ch->sim),
618 		    CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) {
619 			xpt_free_ccb(ccb);
620 			return;
621 		}
622 		xpt_rescan(ccb);
623 	}
624 }
625 
626 static void
627 mvs_notify_events(device_t dev)
628 {
629 	struct mvs_channel *ch = device_get_softc(dev);
630 	struct cam_path *dpath;
631 	uint32_t fis;
632 	int d;
633 
634 	/* Try to read PMP field from SDB FIS. Present only for Gen-IIe. */
635 	fis = ATA_INL(ch->r_mem, SATA_FISDW0);
636 	if ((fis & 0x80ff) == 0x80a1)
637 		d = (fis & 0x0f00) >> 8;
638 	else
639 		d = ch->pm_present ? 15 : 0;
640 	if (bootverbose)
641 		device_printf(dev, "SNTF %d\n", d);
642 	if (xpt_create_path(&dpath, NULL,
643 	    xpt_path_path_id(ch->path), d, 0) == CAM_REQ_CMP) {
644 		xpt_async(AC_SCSI_AEN, dpath, NULL);
645 		xpt_free_path(dpath);
646 	}
647 }
648 
649 static void
650 mvs_ch_intr_locked(void *data)
651 {
652 	struct mvs_intr_arg *arg = (struct mvs_intr_arg *)data;
653 	device_t dev = (device_t)arg->arg;
654 	struct mvs_channel *ch = device_get_softc(dev);
655 
656 	mtx_lock(&ch->mtx);
657 	xpt_batch_start(ch->sim);
658 	mvs_ch_intr(data);
659 	xpt_batch_done(ch->sim);
660 	mtx_unlock(&ch->mtx);
661 }
662 
663 static void
664 mvs_ch_pm(void *arg)
665 {
666 	device_t dev = (device_t)arg;
667 	struct mvs_channel *ch = device_get_softc(dev);
668 	uint32_t work;
669 
670 	if (ch->numrslots != 0)
671 		return;
672 	/* If we are idle - request power state transition. */
673 	work = ATA_INL(ch->r_mem, SATA_SC);
674 	work &= ~SATA_SC_SPM_MASK;
675 	if (ch->pm_level == 4)
676 		work |= SATA_SC_SPM_PARTIAL;
677 	else
678 		work |= SATA_SC_SPM_SLUMBER;
679 	ATA_OUTL(ch->r_mem, SATA_SC, work);
680 }
681 
682 static void
683 mvs_ch_pm_wake(device_t dev)
684 {
685 	struct mvs_channel *ch = device_get_softc(dev);
686 	uint32_t work;
687 	int timeout = 0;
688 
689 	work = ATA_INL(ch->r_mem, SATA_SS);
690 	if (work & SATA_SS_IPM_ACTIVE)
691 		return;
692 	/* If we are not in active state - request power state transition. */
693 	work = ATA_INL(ch->r_mem, SATA_SC);
694 	work &= ~SATA_SC_SPM_MASK;
695 	work |= SATA_SC_SPM_ACTIVE;
696 	ATA_OUTL(ch->r_mem, SATA_SC, work);
697 	/* Wait for transition to happen. */
698 	while ((ATA_INL(ch->r_mem, SATA_SS) & SATA_SS_IPM_ACTIVE) == 0 &&
699 	    timeout++ < 100) {
700 		DELAY(100);
701 	}
702 }
703 
704 static void
705 mvs_ch_intr(void *data)
706 {
707 	struct mvs_intr_arg *arg = (struct mvs_intr_arg *)data;
708 	device_t dev = (device_t)arg->arg;
709 	struct mvs_channel *ch = device_get_softc(dev);
710 	uint32_t iec, serr = 0, fisic = 0;
711 	enum mvs_err_type et;
712 	int i, ccs, port = -1, selfdis = 0;
713 	int edma = (ch->numtslots != 0 || ch->numdslots != 0);
714 
715 	/* New item in response queue. */
716 	if ((arg->cause & 2) && edma)
717 		mvs_crbq_intr(dev);
718 	/* Some error or special event. */
719 	if (arg->cause & 1) {
720 		iec = ATA_INL(ch->r_mem, EDMA_IEC);
721 		if (iec & EDMA_IE_SERRINT) {
722 			serr = ATA_INL(ch->r_mem, SATA_SE);
723 			ATA_OUTL(ch->r_mem, SATA_SE, serr);
724 		}
725 		/* EDMA self-disabled due to error. */
726 		if (iec & EDMA_IE_ESELFDIS)
727 			selfdis = 1;
728 		/* Transport interrupt. */
729 		if (iec & EDMA_IE_ETRANSINT) {
730 			/* For Gen-I this bit means self-disable. */
731 			if (ch->quirks & MVS_Q_GENI)
732 				selfdis = 1;
733 			/* For Gen-II this bit means SDB-N. */
734 			else if (ch->quirks & MVS_Q_GENII)
735 				fisic = SATA_FISC_FISWAIT4HOSTRDYEN_B1;
736 			else	/* For Gen-IIe - read FIS interrupt cause. */
737 				fisic = ATA_INL(ch->r_mem, SATA_FISIC);
738 		}
739 		if (selfdis)
740 			ch->curr_mode = MVS_EDMA_UNKNOWN;
741 		ATA_OUTL(ch->r_mem, EDMA_IEC, ~iec);
742 		/* Interface errors or Device error. */
743 		if (iec & (0xfc1e9000 | EDMA_IE_EDEVERR)) {
744 			port = -1;
745 			if (ch->numpslots != 0) {
746 				ccs = 0;
747 			} else {
748 				if (ch->quirks & MVS_Q_GENIIE)
749 					ccs = EDMA_S_EIOID(ATA_INL(ch->r_mem, EDMA_S));
750 				else
751 					ccs = EDMA_S_EDEVQUETAG(ATA_INL(ch->r_mem, EDMA_S));
752 				/* Check if error is one-PMP-port-specific, */
753 				if (ch->fbs_enabled) {
754 					/* Which ports were active. */
755 					for (i = 0; i < 16; i++) {
756 						if (ch->numrslotspd[i] == 0)
757 							continue;
758 						if (port == -1)
759 							port = i;
760 						else if (port != i) {
761 							port = -2;
762 							break;
763 						}
764 					}
765 					/* If several ports were active and EDMA still enabled -
766 					 * other ports are probably unaffected and may continue.
767 					 */
768 					if (port == -2 && !selfdis) {
769 						uint16_t p = ATA_INL(ch->r_mem, SATA_SATAITC) >> 16;
770 						port = ffs(p) - 1;
771 						if (port != (fls(p) - 1))
772 							port = -2;
773 					}
774 				}
775 			}
776 			mvs_requeue_frozen(dev);
777 			for (i = 0; i < MVS_MAX_SLOTS; i++) {
778 				/* XXX: reqests in loading state. */
779 				if (((ch->rslots >> i) & 1) == 0)
780 					continue;
781 				if (port >= 0 &&
782 				    ch->slot[i].ccb->ccb_h.target_id != port)
783 					continue;
784 				if (iec & EDMA_IE_EDEVERR) { /* Device error. */
785 				    if (port != -2) {
786 					if (ch->numtslots == 0) {
787 						/* Untagged operation. */
788 						if (i == ccs)
789 							et = MVS_ERR_TFE;
790 						else
791 							et = MVS_ERR_INNOCENT;
792 					} else {
793 						/* Tagged operation. */
794 						et = MVS_ERR_NCQ;
795 					}
796 				    } else {
797 					et = MVS_ERR_TFE;
798 					ch->fatalerr = 1;
799 				    }
800 				} else if (iec & 0xfc1e9000) {
801 					if (ch->numtslots == 0 &&
802 					    i != ccs && port != -2)
803 						et = MVS_ERR_INNOCENT;
804 					else
805 						et = MVS_ERR_SATA;
806 				} else
807 					et = MVS_ERR_INVALID;
808 				mvs_end_transaction(&ch->slot[i], et);
809 			}
810 		}
811 		/* Process SDB-N. */
812 		if (fisic & SATA_FISC_FISWAIT4HOSTRDYEN_B1)
813 			mvs_notify_events(dev);
814 		if (fisic)
815 			ATA_OUTL(ch->r_mem, SATA_FISIC, ~fisic);
816 		/* Process hot-plug. */
817 		if ((iec & (EDMA_IE_EDEVDIS | EDMA_IE_EDEVCON)) ||
818 		    (serr & SATA_SE_PHY_CHANGED))
819 			mvs_phy_check_events(dev, serr);
820 	}
821 	/* Legacy mode device interrupt. */
822 	if ((arg->cause & 2) && !edma)
823 		mvs_legacy_intr(dev, arg->cause & 4);
824 }
825 
826 static uint8_t
827 mvs_getstatus(device_t dev, int clear)
828 {
829 	struct mvs_channel *ch = device_get_softc(dev);
830 	uint8_t status = ATA_INB(ch->r_mem, clear ? ATA_STATUS : ATA_ALTSTAT);
831 
832 	if (ch->fake_busy) {
833 		if (status & (ATA_S_BUSY | ATA_S_DRQ | ATA_S_ERROR))
834 			ch->fake_busy = 0;
835 		else
836 			status |= ATA_S_BUSY;
837 	}
838 	return (status);
839 }
840 
841 static void
842 mvs_legacy_intr(device_t dev, int poll)
843 {
844 	struct mvs_channel *ch = device_get_softc(dev);
845 	struct mvs_slot *slot = &ch->slot[0]; /* PIO is always in slot 0. */
846 	union ccb *ccb = slot->ccb;
847 	enum mvs_err_type et = MVS_ERR_NONE;
848 	int port;
849 	u_int length, resid, size;
850 	uint8_t buf[2];
851 	uint8_t status, ireason;
852 
853 	/* Clear interrupt and get status. */
854 	status = mvs_getstatus(dev, 1);
855 	if (slot->state < MVS_SLOT_RUNNING)
856 	    return;
857 	port = ccb->ccb_h.target_id & 0x0f;
858 	/* Wait a bit for late !BUSY status update. */
859 	if (status & ATA_S_BUSY) {
860 		if (poll)
861 			return;
862 		DELAY(100);
863 		if ((status = mvs_getstatus(dev, 1)) & ATA_S_BUSY) {
864 			DELAY(1000);
865 			if ((status = mvs_getstatus(dev, 1)) & ATA_S_BUSY)
866 				return;
867 		}
868 	}
869 	/* If we got an error, we are done. */
870 	if (status & ATA_S_ERROR) {
871 		et = MVS_ERR_TFE;
872 		goto end_finished;
873 	}
874 	if (ccb->ccb_h.func_code == XPT_ATA_IO) { /* ATA PIO */
875 		ccb->ataio.res.status = status;
876 		/* Are we moving data? */
877 		if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) {
878 		    /* If data read command - get them. */
879 		    if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) {
880 			if (mvs_wait(dev, ATA_S_DRQ, ATA_S_BUSY, 1000) < 0) {
881 			    device_printf(dev, "timeout waiting for read DRQ\n");
882 			    et = MVS_ERR_TIMEOUT;
883 			    xpt_freeze_simq(ch->sim, 1);
884 			    ch->toslots |= (1 << slot->slot);
885 			    goto end_finished;
886 			}
887 			ATA_INSW_STRM(ch->r_mem, ATA_DATA,
888 			   (uint16_t *)(ccb->ataio.data_ptr + ch->donecount),
889 			   ch->transfersize / 2);
890 		    }
891 		    /* Update how far we've gotten. */
892 		    ch->donecount += ch->transfersize;
893 		    /* Do we need more? */
894 		    if (ccb->ataio.dxfer_len > ch->donecount) {
895 			/* Set this transfer size according to HW capabilities */
896 			ch->transfersize = min(ccb->ataio.dxfer_len - ch->donecount,
897 			    ch->curr[ccb->ccb_h.target_id].bytecount);
898 			/* If data write command - put them */
899 			if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_OUT) {
900 				if (mvs_wait(dev, ATA_S_DRQ, ATA_S_BUSY, 1000) < 0) {
901 				    device_printf(dev,
902 					"timeout waiting for write DRQ\n");
903 				    et = MVS_ERR_TIMEOUT;
904 				    xpt_freeze_simq(ch->sim, 1);
905 				    ch->toslots |= (1 << slot->slot);
906 				    goto end_finished;
907 				}
908 				ATA_OUTSW_STRM(ch->r_mem, ATA_DATA,
909 				   (uint16_t *)(ccb->ataio.data_ptr + ch->donecount),
910 				   ch->transfersize / 2);
911 				return;
912 			}
913 			/* If data read command, return & wait for interrupt */
914 			if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN)
915 				return;
916 		    }
917 		}
918 	} else if (ch->basic_dma) {	/* ATAPI DMA */
919 		if (status & ATA_S_DWF)
920 			et = MVS_ERR_TFE;
921 		else if (ATA_INL(ch->r_mem, DMA_S) & DMA_S_ERR)
922 			et = MVS_ERR_TFE;
923 		/* Stop basic DMA. */
924 		ATA_OUTL(ch->r_mem, DMA_C, 0);
925 		goto end_finished;
926 	} else {			/* ATAPI PIO */
927 		length = ATA_INB(ch->r_mem,ATA_CYL_LSB) |
928 		    (ATA_INB(ch->r_mem,ATA_CYL_MSB) << 8);
929 		size = min(ch->transfersize, length);
930 		ireason = ATA_INB(ch->r_mem,ATA_IREASON);
931 		switch ((ireason & (ATA_I_CMD | ATA_I_IN)) |
932 			(status & ATA_S_DRQ)) {
933 
934 		case ATAPI_P_CMDOUT:
935 		    device_printf(dev, "ATAPI CMDOUT\n");
936 		    /* Return wait for interrupt */
937 		    return;
938 
939 		case ATAPI_P_WRITE:
940 		    if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) {
941 			device_printf(dev, "trying to write on read buffer\n");
942 			et = MVS_ERR_TFE;
943 			goto end_finished;
944 			break;
945 		    }
946 		    ATA_OUTSW_STRM(ch->r_mem, ATA_DATA,
947 			(uint16_t *)(ccb->csio.data_ptr + ch->donecount),
948 			(size + 1) / 2);
949 		    for (resid = ch->transfersize + (size & 1);
950 			resid < length; resid += sizeof(int16_t))
951 			    ATA_OUTW(ch->r_mem, ATA_DATA, 0);
952 		    ch->donecount += length;
953 		    /* Set next transfer size according to HW capabilities */
954 		    ch->transfersize = min(ccb->csio.dxfer_len - ch->donecount,
955 			    ch->curr[ccb->ccb_h.target_id].bytecount);
956 		    /* Return wait for interrupt */
957 		    return;
958 
959 		case ATAPI_P_READ:
960 		    if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_OUT) {
961 			device_printf(dev, "trying to read on write buffer\n");
962 			et = MVS_ERR_TFE;
963 			goto end_finished;
964 		    }
965 		    if (size >= 2) {
966 			ATA_INSW_STRM(ch->r_mem, ATA_DATA,
967 			    (uint16_t *)(ccb->csio.data_ptr + ch->donecount),
968 			    size / 2);
969 		    }
970 		    if (size & 1) {
971 			ATA_INSW_STRM(ch->r_mem, ATA_DATA, (void*)buf, 1);
972 			((uint8_t *)ccb->csio.data_ptr + ch->donecount +
973 			    (size & ~1))[0] = buf[0];
974 		    }
975 		    for (resid = ch->transfersize + (size & 1);
976 			resid < length; resid += sizeof(int16_t))
977 			    ATA_INW(ch->r_mem, ATA_DATA);
978 		    ch->donecount += length;
979 		    /* Set next transfer size according to HW capabilities */
980 		    ch->transfersize = min(ccb->csio.dxfer_len - ch->donecount,
981 			    ch->curr[ccb->ccb_h.target_id].bytecount);
982 		    /* Return wait for interrupt */
983 		    return;
984 
985 		case ATAPI_P_DONEDRQ:
986 		    device_printf(dev,
987 			  "WARNING - DONEDRQ non conformant device\n");
988 		    if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) {
989 			ATA_INSW_STRM(ch->r_mem, ATA_DATA,
990 			    (uint16_t *)(ccb->csio.data_ptr + ch->donecount),
991 			    length / 2);
992 			ch->donecount += length;
993 		    }
994 		    else if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_OUT) {
995 			ATA_OUTSW_STRM(ch->r_mem, ATA_DATA,
996 			    (uint16_t *)(ccb->csio.data_ptr + ch->donecount),
997 			    length / 2);
998 			ch->donecount += length;
999 		    }
1000 		    else
1001 			et = MVS_ERR_TFE;
1002 		    /* FALLTHROUGH */
1003 
1004 		case ATAPI_P_ABORT:
1005 		case ATAPI_P_DONE:
1006 		    if (status & (ATA_S_ERROR | ATA_S_DWF))
1007 			et = MVS_ERR_TFE;
1008 		    goto end_finished;
1009 
1010 		default:
1011 		    device_printf(dev, "unknown transfer phase"
1012 			" (status %02x, ireason %02x)\n",
1013 			status, ireason);
1014 		    et = MVS_ERR_TFE;
1015 		}
1016 	}
1017 
1018 end_finished:
1019 	mvs_end_transaction(slot, et);
1020 }
1021 
1022 static void
1023 mvs_crbq_intr(device_t dev)
1024 {
1025 	struct mvs_channel *ch = device_get_softc(dev);
1026 	struct mvs_crpb *crpb;
1027 	union ccb *ccb;
1028 	int in_idx, fin_idx, cin_idx, slot;
1029 	uint32_t val;
1030 	uint16_t flags;
1031 
1032 	val = ATA_INL(ch->r_mem, EDMA_RESQIP);
1033 	if (val == 0)
1034 		val = ATA_INL(ch->r_mem, EDMA_RESQIP);
1035 	in_idx = (val & EDMA_RESQP_ERPQP_MASK) >>
1036 	    EDMA_RESQP_ERPQP_SHIFT;
1037 	bus_dmamap_sync(ch->dma.workrp_tag, ch->dma.workrp_map,
1038 	    BUS_DMASYNC_POSTREAD);
1039 	fin_idx = cin_idx = ch->in_idx;
1040 	ch->in_idx = in_idx;
1041 	while (in_idx != cin_idx) {
1042 		crpb = (struct mvs_crpb *)
1043 		    (ch->dma.workrp + MVS_CRPB_OFFSET +
1044 		    (MVS_CRPB_SIZE * cin_idx));
1045 		slot = le16toh(crpb->id) & MVS_CRPB_TAG_MASK;
1046 		flags = le16toh(crpb->rspflg);
1047 		/*
1048 		 * Handle only successfull completions here.
1049 		 * Errors will be handled by main intr handler.
1050 		 */
1051 #if defined(__i386__) || defined(__amd64__)
1052 		if (crpb->id == 0xffff && crpb->rspflg == 0xffff) {
1053 			device_printf(dev, "Unfilled CRPB "
1054 			    "%d (%d->%d) tag %d flags %04x rs %08x\n",
1055 			    cin_idx, fin_idx, in_idx, slot, flags, ch->rslots);
1056 		} else
1057 #endif
1058 		if (ch->numtslots != 0 ||
1059 		    (flags & EDMA_IE_EDEVERR) == 0) {
1060 #if defined(__i386__) || defined(__amd64__)
1061 			crpb->id = 0xffff;
1062 			crpb->rspflg = 0xffff;
1063 #endif
1064 			if (ch->slot[slot].state >= MVS_SLOT_RUNNING) {
1065 				ccb = ch->slot[slot].ccb;
1066 				ccb->ataio.res.status =
1067 				    (flags & MVS_CRPB_ATASTS_MASK) >>
1068 				    MVS_CRPB_ATASTS_SHIFT;
1069 				mvs_end_transaction(&ch->slot[slot], MVS_ERR_NONE);
1070 			} else {
1071 				device_printf(dev, "Unused tag in CRPB "
1072 				    "%d (%d->%d) tag %d flags %04x rs %08x\n",
1073 				    cin_idx, fin_idx, in_idx, slot, flags,
1074 				    ch->rslots);
1075 			}
1076 		} else {
1077 			device_printf(dev,
1078 			    "CRPB with error %d tag %d flags %04x\n",
1079 			    cin_idx, slot, flags);
1080 		}
1081 		cin_idx = (cin_idx + 1) & (MVS_MAX_SLOTS - 1);
1082 	}
1083 	bus_dmamap_sync(ch->dma.workrp_tag, ch->dma.workrp_map,
1084 	    BUS_DMASYNC_PREREAD);
1085 	if (cin_idx == ch->in_idx) {
1086 		ATA_OUTL(ch->r_mem, EDMA_RESQOP,
1087 		    ch->dma.workrp_bus | (cin_idx << EDMA_RESQP_ERPQP_SHIFT));
1088 	}
1089 }
1090 
1091 /* Must be called with channel locked. */
1092 static int
1093 mvs_check_collision(device_t dev, union ccb *ccb)
1094 {
1095 	struct mvs_channel *ch = device_get_softc(dev);
1096 
1097 	if (ccb->ccb_h.func_code == XPT_ATA_IO) {
1098 		/* NCQ DMA */
1099 		if (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) {
1100 			/* Can't mix NCQ and non-NCQ DMA commands. */
1101 			if (ch->numdslots != 0)
1102 				return (1);
1103 			/* Can't mix NCQ and PIO commands. */
1104 			if (ch->numpslots != 0)
1105 				return (1);
1106 			/* If we have no FBS */
1107 			if (!ch->fbs_enabled) {
1108 				/* Tagged command while tagged to other target is active. */
1109 				if (ch->numtslots != 0 &&
1110 				    ch->taggedtarget != ccb->ccb_h.target_id)
1111 					return (1);
1112 			}
1113 		/* Non-NCQ DMA */
1114 		} else if (ccb->ataio.cmd.flags & CAM_ATAIO_DMA) {
1115 			/* Can't mix non-NCQ DMA and NCQ commands. */
1116 			if (ch->numtslots != 0)
1117 				return (1);
1118 			/* Can't mix non-NCQ DMA and PIO commands. */
1119 			if (ch->numpslots != 0)
1120 				return (1);
1121 		/* PIO */
1122 		} else {
1123 			/* Can't mix PIO with anything. */
1124 			if (ch->numrslots != 0)
1125 				return (1);
1126 		}
1127 		if (ccb->ataio.cmd.flags & (CAM_ATAIO_CONTROL | CAM_ATAIO_NEEDRESULT)) {
1128 			/* Atomic command while anything active. */
1129 			if (ch->numrslots != 0)
1130 				return (1);
1131 		}
1132 	} else { /* ATAPI */
1133 		/* ATAPI goes without EDMA, so can't mix it with anything. */
1134 		if (ch->numrslots != 0)
1135 			return (1);
1136 	}
1137 	/* We have some atomic command running. */
1138 	if (ch->aslots != 0)
1139 		return (1);
1140 	return (0);
1141 }
1142 
1143 static void
1144 mvs_tfd_read(device_t dev, union ccb *ccb)
1145 {
1146 	struct mvs_channel *ch = device_get_softc(dev);
1147 	struct ata_res *res = &ccb->ataio.res;
1148 
1149 	res->status = ATA_INB(ch->r_mem, ATA_ALTSTAT);
1150 	res->error =  ATA_INB(ch->r_mem, ATA_ERROR);
1151 	res->device = ATA_INB(ch->r_mem, ATA_DRIVE);
1152 	ATA_OUTB(ch->r_mem, ATA_CONTROL, ATA_A_HOB);
1153 	res->sector_count_exp = ATA_INB(ch->r_mem, ATA_COUNT);
1154 	res->lba_low_exp = ATA_INB(ch->r_mem, ATA_SECTOR);
1155 	res->lba_mid_exp = ATA_INB(ch->r_mem, ATA_CYL_LSB);
1156 	res->lba_high_exp = ATA_INB(ch->r_mem, ATA_CYL_MSB);
1157 	ATA_OUTB(ch->r_mem, ATA_CONTROL, 0);
1158 	res->sector_count = ATA_INB(ch->r_mem, ATA_COUNT);
1159 	res->lba_low = ATA_INB(ch->r_mem, ATA_SECTOR);
1160 	res->lba_mid = ATA_INB(ch->r_mem, ATA_CYL_LSB);
1161 	res->lba_high = ATA_INB(ch->r_mem, ATA_CYL_MSB);
1162 }
1163 
1164 static void
1165 mvs_tfd_write(device_t dev, union ccb *ccb)
1166 {
1167 	struct mvs_channel *ch = device_get_softc(dev);
1168 	struct ata_cmd *cmd = &ccb->ataio.cmd;
1169 
1170 	ATA_OUTB(ch->r_mem, ATA_DRIVE, cmd->device);
1171 	ATA_OUTB(ch->r_mem, ATA_CONTROL, cmd->control);
1172 	ATA_OUTB(ch->r_mem, ATA_FEATURE, cmd->features_exp);
1173 	ATA_OUTB(ch->r_mem, ATA_FEATURE, cmd->features);
1174 	ATA_OUTB(ch->r_mem, ATA_COUNT, cmd->sector_count_exp);
1175 	ATA_OUTB(ch->r_mem, ATA_COUNT, cmd->sector_count);
1176 	ATA_OUTB(ch->r_mem, ATA_SECTOR, cmd->lba_low_exp);
1177 	ATA_OUTB(ch->r_mem, ATA_SECTOR, cmd->lba_low);
1178 	ATA_OUTB(ch->r_mem, ATA_CYL_LSB, cmd->lba_mid_exp);
1179 	ATA_OUTB(ch->r_mem, ATA_CYL_LSB, cmd->lba_mid);
1180 	ATA_OUTB(ch->r_mem, ATA_CYL_MSB, cmd->lba_high_exp);
1181 	ATA_OUTB(ch->r_mem, ATA_CYL_MSB, cmd->lba_high);
1182 	ATA_OUTB(ch->r_mem, ATA_COMMAND, cmd->command);
1183 }
1184 
1185 
1186 /* Must be called with channel locked. */
1187 static void
1188 mvs_begin_transaction(device_t dev, union ccb *ccb)
1189 {
1190 	struct mvs_channel *ch = device_get_softc(dev);
1191 	struct mvs_slot *slot;
1192 	int slotn, tag;
1193 
1194 	if (ch->pm_level > 0)
1195 		mvs_ch_pm_wake(dev);
1196 	/* Softreset is a special case. */
1197 	if (ccb->ccb_h.func_code == XPT_ATA_IO &&
1198 	    (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL)) {
1199 		mvs_softreset(dev, ccb);
1200 		return;
1201 	}
1202 	/* Choose empty slot. */
1203 	slotn = ffs(~ch->oslots) - 1;
1204 	if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1205 	    (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) {
1206 		if (ch->quirks & MVS_Q_GENIIE)
1207 			tag = ffs(~ch->otagspd[ccb->ccb_h.target_id]) - 1;
1208 		else
1209 			tag = slotn;
1210 	} else
1211 		tag = 0;
1212 	/* Occupy chosen slot. */
1213 	slot = &ch->slot[slotn];
1214 	slot->ccb = ccb;
1215 	slot->tag = tag;
1216 	/* Stop PM timer. */
1217 	if (ch->numrslots == 0 && ch->pm_level > 3)
1218 		callout_stop(&ch->pm_timer);
1219 	/* Update channel stats. */
1220 	ch->oslots |= (1 << slot->slot);
1221 	ch->numrslots++;
1222 	ch->numrslotspd[ccb->ccb_h.target_id]++;
1223 	if (ccb->ccb_h.func_code == XPT_ATA_IO) {
1224 		if (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) {
1225 			ch->otagspd[ccb->ccb_h.target_id] |= (1 << slot->tag);
1226 			ch->numtslots++;
1227 			ch->numtslotspd[ccb->ccb_h.target_id]++;
1228 			ch->taggedtarget = ccb->ccb_h.target_id;
1229 			mvs_set_edma_mode(dev, MVS_EDMA_NCQ);
1230 		} else if (ccb->ataio.cmd.flags & CAM_ATAIO_DMA) {
1231 			ch->numdslots++;
1232 			mvs_set_edma_mode(dev, MVS_EDMA_ON);
1233 		} else {
1234 			ch->numpslots++;
1235 			mvs_set_edma_mode(dev, MVS_EDMA_OFF);
1236 		}
1237 		if (ccb->ataio.cmd.flags &
1238 		    (CAM_ATAIO_CONTROL | CAM_ATAIO_NEEDRESULT)) {
1239 			ch->aslots |= (1 << slot->slot);
1240 		}
1241 	} else {
1242 		uint8_t *cdb = (ccb->ccb_h.flags & CAM_CDB_POINTER) ?
1243 		    ccb->csio.cdb_io.cdb_ptr : ccb->csio.cdb_io.cdb_bytes;
1244 		ch->numpslots++;
1245 		/* Use ATAPI DMA only for commands without under-/overruns. */
1246 		if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE &&
1247 		    ch->curr[ccb->ccb_h.target_id].mode >= ATA_DMA &&
1248 		    (ch->quirks & MVS_Q_SOC) == 0 &&
1249 		    (cdb[0] == 0x08 ||
1250 		     cdb[0] == 0x0a ||
1251 		     cdb[0] == 0x28 ||
1252 		     cdb[0] == 0x2a ||
1253 		     cdb[0] == 0x88 ||
1254 		     cdb[0] == 0x8a ||
1255 		     cdb[0] == 0xa8 ||
1256 		     cdb[0] == 0xaa ||
1257 		     cdb[0] == 0xbe)) {
1258 			ch->basic_dma = 1;
1259 		}
1260 		mvs_set_edma_mode(dev, MVS_EDMA_OFF);
1261 	}
1262 	if (ch->numpslots == 0 || ch->basic_dma) {
1263 		void *buf;
1264 		bus_size_t size;
1265 
1266 		slot->state = MVS_SLOT_LOADING;
1267 		if (ccb->ccb_h.func_code == XPT_ATA_IO) {
1268 			buf = ccb->ataio.data_ptr;
1269 			size = ccb->ataio.dxfer_len;
1270 		} else {
1271 			buf = ccb->csio.data_ptr;
1272 			size = ccb->csio.dxfer_len;
1273 		}
1274 		bus_dmamap_load(ch->dma.data_tag, slot->dma.data_map,
1275 		    buf, size, mvs_dmasetprd, slot, 0);
1276 	} else
1277 		mvs_legacy_execute_transaction(slot);
1278 }
1279 
1280 /* Locked by busdma engine. */
1281 static void
1282 mvs_dmasetprd(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
1283 {
1284 	struct mvs_slot *slot = arg;
1285 	struct mvs_channel *ch = device_get_softc(slot->dev);
1286 	struct mvs_eprd *eprd;
1287 	int i;
1288 
1289 	if (error) {
1290 		device_printf(slot->dev, "DMA load error\n");
1291 		mvs_end_transaction(slot, MVS_ERR_INVALID);
1292 		return;
1293 	}
1294 	KASSERT(nsegs <= MVS_SG_ENTRIES, ("too many DMA segment entries\n"));
1295 	/* If there is only one segment - no need to use S/G table on Gen-IIe. */
1296 	if (nsegs == 1 && ch->basic_dma == 0 && (ch->quirks & MVS_Q_GENIIE)) {
1297 		slot->dma.addr = segs[0].ds_addr;
1298 		slot->dma.len = segs[0].ds_len;
1299 	} else {
1300 		slot->dma.addr = 0;
1301 		/* Get a piece of the workspace for this EPRD */
1302 		eprd = (struct mvs_eprd *)
1303 		    (ch->dma.workrq + MVS_EPRD_OFFSET + (MVS_EPRD_SIZE * slot->slot));
1304 		/* Fill S/G table */
1305 		for (i = 0; i < nsegs; i++) {
1306 			eprd[i].prdbal = htole32(segs[i].ds_addr);
1307 			eprd[i].bytecount = htole32(segs[i].ds_len & MVS_EPRD_MASK);
1308 			eprd[i].prdbah = htole32((segs[i].ds_addr >> 16) >> 16);
1309 		}
1310 		eprd[i - 1].bytecount |= htole32(MVS_EPRD_EOF);
1311 	}
1312 	bus_dmamap_sync(ch->dma.data_tag, slot->dma.data_map,
1313 	    ((slot->ccb->ccb_h.flags & CAM_DIR_IN) ?
1314 	    BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE));
1315 	if (ch->basic_dma)
1316 		mvs_legacy_execute_transaction(slot);
1317 	else
1318 		mvs_execute_transaction(slot);
1319 }
1320 
1321 static void
1322 mvs_legacy_execute_transaction(struct mvs_slot *slot)
1323 {
1324 	device_t dev = slot->dev;
1325 	struct mvs_channel *ch = device_get_softc(dev);
1326 	bus_addr_t eprd;
1327 	union ccb *ccb = slot->ccb;
1328 	int port = ccb->ccb_h.target_id & 0x0f;
1329 	int timeout;
1330 
1331 	slot->state = MVS_SLOT_RUNNING;
1332 	ch->rslots |= (1 << slot->slot);
1333 	ATA_OUTB(ch->r_mem, SATA_SATAICTL, port << SATA_SATAICTL_PMPTX_SHIFT);
1334 	if (ccb->ccb_h.func_code == XPT_ATA_IO) {
1335 		mvs_tfd_write(dev, ccb);
1336 		/* Device reset doesn't interrupt. */
1337 		if (ccb->ataio.cmd.command == ATA_DEVICE_RESET) {
1338 			int timeout = 1000000;
1339 			do {
1340 			    DELAY(10);
1341 			    ccb->ataio.res.status = ATA_INB(ch->r_mem, ATA_STATUS);
1342 			} while (ccb->ataio.res.status & ATA_S_BUSY && timeout--);
1343 			mvs_legacy_intr(dev, 1);
1344 			return;
1345 		}
1346 		ch->donecount = 0;
1347 		ch->transfersize = min(ccb->ataio.dxfer_len,
1348 		    ch->curr[port].bytecount);
1349 		if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE)
1350 			ch->fake_busy = 1;
1351 		/* If data write command - output the data */
1352 		if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_OUT) {
1353 			if (mvs_wait(dev, ATA_S_DRQ, ATA_S_BUSY, 1000) < 0) {
1354 				device_printf(dev,
1355 				    "timeout waiting for write DRQ\n");
1356 				xpt_freeze_simq(ch->sim, 1);
1357 				ch->toslots |= (1 << slot->slot);
1358 				mvs_end_transaction(slot, MVS_ERR_TIMEOUT);
1359 				return;
1360 			}
1361 			ATA_OUTSW_STRM(ch->r_mem, ATA_DATA,
1362 			   (uint16_t *)(ccb->ataio.data_ptr + ch->donecount),
1363 			   ch->transfersize / 2);
1364 		}
1365 	} else {
1366 		ch->donecount = 0;
1367 		ch->transfersize = min(ccb->csio.dxfer_len,
1368 		    ch->curr[port].bytecount);
1369 		/* Write ATA PACKET command. */
1370 		if (ch->basic_dma) {
1371 			ATA_OUTB(ch->r_mem, ATA_FEATURE, ATA_F_DMA);
1372 			ATA_OUTB(ch->r_mem, ATA_CYL_LSB, 0);
1373 		    	ATA_OUTB(ch->r_mem, ATA_CYL_MSB, 0);
1374 		} else {
1375 			ATA_OUTB(ch->r_mem, ATA_FEATURE, 0);
1376 			ATA_OUTB(ch->r_mem, ATA_CYL_LSB, ch->transfersize);
1377 		    	ATA_OUTB(ch->r_mem, ATA_CYL_MSB, ch->transfersize >> 8);
1378 		}
1379 		ATA_OUTB(ch->r_mem, ATA_COMMAND, ATA_PACKET_CMD);
1380 		ch->fake_busy = 1;
1381 		/* Wait for ready to write ATAPI command block */
1382 		if (mvs_wait(dev, 0, ATA_S_BUSY, 1000) < 0) {
1383 			device_printf(dev, "timeout waiting for ATAPI !BUSY\n");
1384 			xpt_freeze_simq(ch->sim, 1);
1385 			ch->toslots |= (1 << slot->slot);
1386 			mvs_end_transaction(slot, MVS_ERR_TIMEOUT);
1387 			return;
1388 		}
1389 		timeout = 5000;
1390 		while (timeout--) {
1391 		    int reason = ATA_INB(ch->r_mem, ATA_IREASON);
1392 		    int status = ATA_INB(ch->r_mem, ATA_STATUS);
1393 
1394 		    if (((reason & (ATA_I_CMD | ATA_I_IN)) |
1395 			 (status & (ATA_S_DRQ | ATA_S_BUSY))) == ATAPI_P_CMDOUT)
1396 			break;
1397 		    DELAY(20);
1398 		}
1399 		if (timeout <= 0) {
1400 			device_printf(dev,
1401 			    "timeout waiting for ATAPI command ready\n");
1402 			xpt_freeze_simq(ch->sim, 1);
1403 			ch->toslots |= (1 << slot->slot);
1404 			mvs_end_transaction(slot, MVS_ERR_TIMEOUT);
1405 			return;
1406 		}
1407 		/* Write ATAPI command. */
1408 		ATA_OUTSW_STRM(ch->r_mem, ATA_DATA,
1409 		   (uint16_t *)((ccb->ccb_h.flags & CAM_CDB_POINTER) ?
1410 		    ccb->csio.cdb_io.cdb_ptr : ccb->csio.cdb_io.cdb_bytes),
1411 		   ch->curr[port].atapi / 2);
1412 		DELAY(10);
1413 		if (ch->basic_dma) {
1414 			/* Start basic DMA. */
1415 			eprd = ch->dma.workrq_bus + MVS_EPRD_OFFSET +
1416 			    (MVS_EPRD_SIZE * slot->slot);
1417 			ATA_OUTL(ch->r_mem, DMA_DTLBA, eprd);
1418 			ATA_OUTL(ch->r_mem, DMA_DTHBA, (eprd >> 16) >> 16);
1419 			ATA_OUTL(ch->r_mem, DMA_C, DMA_C_START |
1420 			    (((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) ?
1421 			    DMA_C_READ : 0));
1422 		}
1423 	}
1424 	/* Start command execution timeout */
1425 	callout_reset(&slot->timeout, (int)ccb->ccb_h.timeout * hz / 1000,
1426 	    (timeout_t*)mvs_timeout, slot);
1427 }
1428 
1429 /* Must be called with channel locked. */
1430 static void
1431 mvs_execute_transaction(struct mvs_slot *slot)
1432 {
1433 	device_t dev = slot->dev;
1434 	struct mvs_channel *ch = device_get_softc(dev);
1435 	bus_addr_t eprd;
1436 	struct mvs_crqb *crqb;
1437 	struct mvs_crqb_gen2e *crqb2e;
1438 	union ccb *ccb = slot->ccb;
1439 	int port = ccb->ccb_h.target_id & 0x0f;
1440 	int i;
1441 
1442 	/* Get address of the prepared EPRD */
1443 	eprd = ch->dma.workrq_bus + MVS_EPRD_OFFSET + (MVS_EPRD_SIZE * slot->slot);
1444 	/* Prepare CRQB. Gen IIe uses different CRQB format. */
1445 	if (ch->quirks & MVS_Q_GENIIE) {
1446 		crqb2e = (struct mvs_crqb_gen2e *)
1447 		    (ch->dma.workrq + MVS_CRQB_OFFSET + (MVS_CRQB_SIZE * ch->out_idx));
1448 		crqb2e->ctrlflg = htole32(
1449 		    ((ccb->ccb_h.flags & CAM_DIR_IN) ? MVS_CRQB2E_READ : 0) |
1450 		    (slot->tag << MVS_CRQB2E_DTAG_SHIFT) |
1451 		    (port << MVS_CRQB2E_PMP_SHIFT) |
1452 		    (slot->slot << MVS_CRQB2E_HTAG_SHIFT));
1453 		/* If there is only one segment - no need to use S/G table. */
1454 		if (slot->dma.addr != 0) {
1455 			eprd = slot->dma.addr;
1456 			crqb2e->ctrlflg |= htole32(MVS_CRQB2E_CPRD);
1457 			crqb2e->drbc = slot->dma.len;
1458 		}
1459 		crqb2e->cprdbl = htole32(eprd);
1460 		crqb2e->cprdbh = htole32((eprd >> 16) >> 16);
1461 		crqb2e->cmd[0] = 0;
1462 		crqb2e->cmd[1] = 0;
1463 		crqb2e->cmd[2] = ccb->ataio.cmd.command;
1464 		crqb2e->cmd[3] = ccb->ataio.cmd.features;
1465 		crqb2e->cmd[4] = ccb->ataio.cmd.lba_low;
1466 		crqb2e->cmd[5] = ccb->ataio.cmd.lba_mid;
1467 		crqb2e->cmd[6] = ccb->ataio.cmd.lba_high;
1468 		crqb2e->cmd[7] = ccb->ataio.cmd.device;
1469 		crqb2e->cmd[8] = ccb->ataio.cmd.lba_low_exp;
1470 		crqb2e->cmd[9] = ccb->ataio.cmd.lba_mid_exp;
1471 		crqb2e->cmd[10] = ccb->ataio.cmd.lba_high_exp;
1472 		crqb2e->cmd[11] = ccb->ataio.cmd.features_exp;
1473 		if (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) {
1474 			crqb2e->cmd[12] = slot->tag << 3;
1475 			crqb2e->cmd[13] = 0;
1476 		} else {
1477 			crqb2e->cmd[12] = ccb->ataio.cmd.sector_count;
1478 			crqb2e->cmd[13] = ccb->ataio.cmd.sector_count_exp;
1479 		}
1480 		crqb2e->cmd[14] = 0;
1481 		crqb2e->cmd[15] = 0;
1482 	} else {
1483 		crqb = (struct mvs_crqb *)
1484 		    (ch->dma.workrq + MVS_CRQB_OFFSET + (MVS_CRQB_SIZE * ch->out_idx));
1485 		crqb->cprdbl = htole32(eprd);
1486 		crqb->cprdbh = htole32((eprd >> 16) >> 16);
1487 		crqb->ctrlflg = htole16(
1488 		    ((ccb->ccb_h.flags & CAM_DIR_IN) ? MVS_CRQB_READ : 0) |
1489 		    (slot->slot << MVS_CRQB_TAG_SHIFT) |
1490 		    (port << MVS_CRQB_PMP_SHIFT));
1491 		i = 0;
1492 		/*
1493 		 * Controller can handle only 11 of 12 ATA registers,
1494 		 * so we have to choose which one to skip.
1495 		 */
1496 		if (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) {
1497 			crqb->cmd[i++] = ccb->ataio.cmd.features_exp;
1498 			crqb->cmd[i++] = 0x11;
1499 		}
1500 		crqb->cmd[i++] = ccb->ataio.cmd.features;
1501 		crqb->cmd[i++] = 0x11;
1502 		if (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) {
1503 			crqb->cmd[i++] = slot->tag << 3;
1504 			crqb->cmd[i++] = 0x12;
1505 		} else {
1506 			crqb->cmd[i++] = ccb->ataio.cmd.sector_count_exp;
1507 			crqb->cmd[i++] = 0x12;
1508 			crqb->cmd[i++] = ccb->ataio.cmd.sector_count;
1509 			crqb->cmd[i++] = 0x12;
1510 		}
1511 		crqb->cmd[i++] = ccb->ataio.cmd.lba_low_exp;
1512 		crqb->cmd[i++] = 0x13;
1513 		crqb->cmd[i++] = ccb->ataio.cmd.lba_low;
1514 		crqb->cmd[i++] = 0x13;
1515 		crqb->cmd[i++] = ccb->ataio.cmd.lba_mid_exp;
1516 		crqb->cmd[i++] = 0x14;
1517 		crqb->cmd[i++] = ccb->ataio.cmd.lba_mid;
1518 		crqb->cmd[i++] = 0x14;
1519 		crqb->cmd[i++] = ccb->ataio.cmd.lba_high_exp;
1520 		crqb->cmd[i++] = 0x15;
1521 		crqb->cmd[i++] = ccb->ataio.cmd.lba_high;
1522 		crqb->cmd[i++] = 0x15;
1523 		crqb->cmd[i++] = ccb->ataio.cmd.device;
1524 		crqb->cmd[i++] = 0x16;
1525 		crqb->cmd[i++] = ccb->ataio.cmd.command;
1526 		crqb->cmd[i++] = 0x97;
1527 	}
1528 	bus_dmamap_sync(ch->dma.workrq_tag, ch->dma.workrq_map,
1529 	    BUS_DMASYNC_PREWRITE);
1530 	bus_dmamap_sync(ch->dma.workrp_tag, ch->dma.workrp_map,
1531 	    BUS_DMASYNC_PREREAD);
1532 	slot->state = MVS_SLOT_RUNNING;
1533 	ch->rslots |= (1 << slot->slot);
1534 	/* Issue command to the controller. */
1535 	ch->out_idx = (ch->out_idx + 1) & (MVS_MAX_SLOTS - 1);
1536 	ATA_OUTL(ch->r_mem, EDMA_REQQIP,
1537 	    ch->dma.workrq_bus + MVS_CRQB_OFFSET + (MVS_CRQB_SIZE * ch->out_idx));
1538 	/* Start command execution timeout */
1539 	callout_reset(&slot->timeout, (int)ccb->ccb_h.timeout * hz / 1000,
1540 	    (timeout_t*)mvs_timeout, slot);
1541 	return;
1542 }
1543 
1544 /* Must be called with channel locked. */
1545 static void
1546 mvs_process_timeout(device_t dev)
1547 {
1548 	struct mvs_channel *ch = device_get_softc(dev);
1549 	int i;
1550 
1551 	mtx_assert(&ch->mtx, MA_OWNED);
1552 	/* Handle the rest of commands. */
1553 	for (i = 0; i < MVS_MAX_SLOTS; i++) {
1554 		/* Do we have a running request on slot? */
1555 		if (ch->slot[i].state < MVS_SLOT_RUNNING)
1556 			continue;
1557 		mvs_end_transaction(&ch->slot[i], MVS_ERR_TIMEOUT);
1558 	}
1559 }
1560 
1561 /* Must be called with channel locked. */
1562 static void
1563 mvs_rearm_timeout(device_t dev)
1564 {
1565 	struct mvs_channel *ch = device_get_softc(dev);
1566 	int i;
1567 
1568 	mtx_assert(&ch->mtx, MA_OWNED);
1569 	for (i = 0; i < MVS_MAX_SLOTS; i++) {
1570 		struct mvs_slot *slot = &ch->slot[i];
1571 
1572 		/* Do we have a running request on slot? */
1573 		if (slot->state < MVS_SLOT_RUNNING)
1574 			continue;
1575 		if ((ch->toslots & (1 << i)) == 0)
1576 			continue;
1577 		callout_reset(&slot->timeout,
1578 		    (int)slot->ccb->ccb_h.timeout * hz / 2000,
1579 		    (timeout_t*)mvs_timeout, slot);
1580 	}
1581 }
1582 
1583 /* Locked by callout mechanism. */
1584 static void
1585 mvs_timeout(struct mvs_slot *slot)
1586 {
1587 	device_t dev = slot->dev;
1588 	struct mvs_channel *ch = device_get_softc(dev);
1589 
1590 	/* Check for stale timeout. */
1591 	if (slot->state < MVS_SLOT_RUNNING)
1592 		return;
1593 	device_printf(dev, "Timeout on slot %d\n", slot->slot);
1594 	device_printf(dev, "iec %08x sstat %08x serr %08x edma_s %08x "
1595 	    "dma_c %08x dma_s %08x rs %08x status %02x\n",
1596 	    ATA_INL(ch->r_mem, EDMA_IEC),
1597 	    ATA_INL(ch->r_mem, SATA_SS), ATA_INL(ch->r_mem, SATA_SE),
1598 	    ATA_INL(ch->r_mem, EDMA_S), ATA_INL(ch->r_mem, DMA_C),
1599 	    ATA_INL(ch->r_mem, DMA_S), ch->rslots,
1600 	    ATA_INB(ch->r_mem, ATA_ALTSTAT));
1601 	/* Handle frozen command. */
1602 	mvs_requeue_frozen(dev);
1603 	/* We wait for other commands timeout and pray. */
1604 	if (ch->toslots == 0)
1605 		xpt_freeze_simq(ch->sim, 1);
1606 	ch->toslots |= (1 << slot->slot);
1607 	if ((ch->rslots & ~ch->toslots) == 0)
1608 		mvs_process_timeout(dev);
1609 	else
1610 		device_printf(dev, " ... waiting for slots %08x\n",
1611 		    ch->rslots & ~ch->toslots);
1612 }
1613 
1614 /* Must be called with channel locked. */
1615 static void
1616 mvs_end_transaction(struct mvs_slot *slot, enum mvs_err_type et)
1617 {
1618 	device_t dev = slot->dev;
1619 	struct mvs_channel *ch = device_get_softc(dev);
1620 	union ccb *ccb = slot->ccb;
1621 	int lastto;
1622 
1623 	bus_dmamap_sync(ch->dma.workrq_tag, ch->dma.workrq_map,
1624 	    BUS_DMASYNC_POSTWRITE);
1625 	/* Read result registers to the result struct
1626 	 * May be incorrect if several commands finished same time,
1627 	 * so read only when sure or have to.
1628 	 */
1629 	if (ccb->ccb_h.func_code == XPT_ATA_IO) {
1630 		struct ata_res *res = &ccb->ataio.res;
1631 
1632 		if ((et == MVS_ERR_TFE) ||
1633 		    (ccb->ataio.cmd.flags & CAM_ATAIO_NEEDRESULT)) {
1634 			mvs_tfd_read(dev, ccb);
1635 		} else
1636 			bzero(res, sizeof(*res));
1637 	} else {
1638 		if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE &&
1639 		    ch->basic_dma == 0)
1640 			ccb->csio.resid = ccb->csio.dxfer_len - ch->donecount;
1641 	}
1642 	if (ch->numpslots == 0 || ch->basic_dma) {
1643 		if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) {
1644 			bus_dmamap_sync(ch->dma.data_tag, slot->dma.data_map,
1645 			    (ccb->ccb_h.flags & CAM_DIR_IN) ?
1646 			    BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
1647 			bus_dmamap_unload(ch->dma.data_tag, slot->dma.data_map);
1648 		}
1649 	}
1650 	if (et != MVS_ERR_NONE)
1651 		ch->eslots |= (1 << slot->slot);
1652 	/* In case of error, freeze device for proper recovery. */
1653 	if ((et != MVS_ERR_NONE) && (!ch->recoverycmd) &&
1654 	    !(ccb->ccb_h.status & CAM_DEV_QFRZN)) {
1655 		xpt_freeze_devq(ccb->ccb_h.path, 1);
1656 		ccb->ccb_h.status |= CAM_DEV_QFRZN;
1657 	}
1658 	/* Set proper result status. */
1659 	ccb->ccb_h.status &= ~CAM_STATUS_MASK;
1660 	switch (et) {
1661 	case MVS_ERR_NONE:
1662 		ccb->ccb_h.status |= CAM_REQ_CMP;
1663 		if (ccb->ccb_h.func_code == XPT_SCSI_IO)
1664 			ccb->csio.scsi_status = SCSI_STATUS_OK;
1665 		break;
1666 	case MVS_ERR_INVALID:
1667 		ch->fatalerr = 1;
1668 		ccb->ccb_h.status |= CAM_REQ_INVALID;
1669 		break;
1670 	case MVS_ERR_INNOCENT:
1671 		ccb->ccb_h.status |= CAM_REQUEUE_REQ;
1672 		break;
1673 	case MVS_ERR_TFE:
1674 	case MVS_ERR_NCQ:
1675 		if (ccb->ccb_h.func_code == XPT_SCSI_IO) {
1676 			ccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR;
1677 			ccb->csio.scsi_status = SCSI_STATUS_CHECK_COND;
1678 		} else {
1679 			ccb->ccb_h.status |= CAM_ATA_STATUS_ERROR;
1680 		}
1681 		break;
1682 	case MVS_ERR_SATA:
1683 		ch->fatalerr = 1;
1684 		if (!ch->recoverycmd) {
1685 			xpt_freeze_simq(ch->sim, 1);
1686 			ccb->ccb_h.status &= ~CAM_STATUS_MASK;
1687 			ccb->ccb_h.status |= CAM_RELEASE_SIMQ;
1688 		}
1689 		ccb->ccb_h.status |= CAM_UNCOR_PARITY;
1690 		break;
1691 	case MVS_ERR_TIMEOUT:
1692 		if (!ch->recoverycmd) {
1693 			xpt_freeze_simq(ch->sim, 1);
1694 			ccb->ccb_h.status &= ~CAM_STATUS_MASK;
1695 			ccb->ccb_h.status |= CAM_RELEASE_SIMQ;
1696 		}
1697 		ccb->ccb_h.status |= CAM_CMD_TIMEOUT;
1698 		break;
1699 	default:
1700 		ch->fatalerr = 1;
1701 		ccb->ccb_h.status |= CAM_REQ_CMP_ERR;
1702 	}
1703 	/* Free slot. */
1704 	ch->oslots &= ~(1 << slot->slot);
1705 	ch->rslots &= ~(1 << slot->slot);
1706 	ch->aslots &= ~(1 << slot->slot);
1707 	slot->state = MVS_SLOT_EMPTY;
1708 	slot->ccb = NULL;
1709 	/* Update channel stats. */
1710 	ch->numrslots--;
1711 	ch->numrslotspd[ccb->ccb_h.target_id]--;
1712 	if (ccb->ccb_h.func_code == XPT_ATA_IO) {
1713 		if (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) {
1714 			ch->otagspd[ccb->ccb_h.target_id] &= ~(1 << slot->tag);
1715 			ch->numtslots--;
1716 			ch->numtslotspd[ccb->ccb_h.target_id]--;
1717 		} else if (ccb->ataio.cmd.flags & CAM_ATAIO_DMA) {
1718 			ch->numdslots--;
1719 		} else {
1720 			ch->numpslots--;
1721 		}
1722 	} else {
1723 		ch->numpslots--;
1724 		ch->basic_dma = 0;
1725 	}
1726 	/* Cancel timeout state if request completed normally. */
1727 	if (et != MVS_ERR_TIMEOUT) {
1728 		lastto = (ch->toslots == (1 << slot->slot));
1729 		ch->toslots &= ~(1 << slot->slot);
1730 		if (lastto)
1731 			xpt_release_simq(ch->sim, TRUE);
1732 	}
1733 	/* If it was our READ LOG command - process it. */
1734 	if (ccb->ccb_h.recovery_type == RECOVERY_READ_LOG) {
1735 		mvs_process_read_log(dev, ccb);
1736 	/* If it was our REQUEST SENSE command - process it. */
1737 	} else if (ccb->ccb_h.recovery_type == RECOVERY_REQUEST_SENSE) {
1738 		mvs_process_request_sense(dev, ccb);
1739 	/* If it was NCQ or ATAPI command error, put result on hold. */
1740 	} else if (et == MVS_ERR_NCQ ||
1741 	    ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_SCSI_STATUS_ERROR &&
1742 	     (ccb->ccb_h.flags & CAM_DIS_AUTOSENSE) == 0)) {
1743 		ch->hold[slot->slot] = ccb;
1744 		ch->holdtag[slot->slot] = slot->tag;
1745 		ch->numhslots++;
1746 	} else
1747 		xpt_done(ccb);
1748 	/* If we have no other active commands, ... */
1749 	if (ch->rslots == 0) {
1750 		/* if there was fatal error - reset port. */
1751 		if (ch->toslots != 0 || ch->fatalerr) {
1752 			mvs_reset(dev);
1753 		} else {
1754 			/* if we have slots in error, we can reinit port. */
1755 			if (ch->eslots != 0) {
1756 				mvs_set_edma_mode(dev, MVS_EDMA_OFF);
1757 				ch->eslots = 0;
1758 			}
1759 			/* if there commands on hold, we can do READ LOG. */
1760 			if (!ch->recoverycmd && ch->numhslots)
1761 				mvs_issue_recovery(dev);
1762 		}
1763 	/* If all the rest of commands are in timeout - give them chance. */
1764 	} else if ((ch->rslots & ~ch->toslots) == 0 &&
1765 	    et != MVS_ERR_TIMEOUT)
1766 		mvs_rearm_timeout(dev);
1767 	/* Unfreeze frozen command. */
1768 	if (ch->frozen && !mvs_check_collision(dev, ch->frozen)) {
1769 		union ccb *fccb = ch->frozen;
1770 		ch->frozen = NULL;
1771 		mvs_begin_transaction(dev, fccb);
1772 		xpt_release_simq(ch->sim, TRUE);
1773 	}
1774 	/* Start PM timer. */
1775 	if (ch->numrslots == 0 && ch->pm_level > 3 &&
1776 	    (ch->curr[ch->pm_present ? 15 : 0].caps & CTS_SATA_CAPS_D_PMREQ)) {
1777 		callout_schedule(&ch->pm_timer,
1778 		    (ch->pm_level == 4) ? hz / 1000 : hz / 8);
1779 	}
1780 }
1781 
1782 static void
1783 mvs_issue_recovery(device_t dev)
1784 {
1785 	struct mvs_channel *ch = device_get_softc(dev);
1786 	union ccb *ccb;
1787 	struct ccb_ataio *ataio;
1788 	struct ccb_scsiio *csio;
1789 	int i;
1790 
1791 	/* Find some held command. */
1792 	for (i = 0; i < MVS_MAX_SLOTS; i++) {
1793 		if (ch->hold[i])
1794 			break;
1795 	}
1796 	ccb = xpt_alloc_ccb_nowait();
1797 	if (ccb == NULL) {
1798 		device_printf(dev, "Unable to allocate recovery command\n");
1799 completeall:
1800 		/* We can't do anything -- complete held commands. */
1801 		for (i = 0; i < MVS_MAX_SLOTS; i++) {
1802 			if (ch->hold[i] == NULL)
1803 				continue;
1804 			ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK;
1805 			ch->hold[i]->ccb_h.status |= CAM_RESRC_UNAVAIL;
1806 			xpt_done(ch->hold[i]);
1807 			ch->hold[i] = NULL;
1808 			ch->numhslots--;
1809 		}
1810 		mvs_reset(dev);
1811 		return;
1812 	}
1813 	ccb->ccb_h = ch->hold[i]->ccb_h;	/* Reuse old header. */
1814 	if (ccb->ccb_h.func_code == XPT_ATA_IO) {
1815 		/* READ LOG */
1816 		ccb->ccb_h.recovery_type = RECOVERY_READ_LOG;
1817 		ccb->ccb_h.func_code = XPT_ATA_IO;
1818 		ccb->ccb_h.flags = CAM_DIR_IN;
1819 		ccb->ccb_h.timeout = 1000;	/* 1s should be enough. */
1820 		ataio = &ccb->ataio;
1821 		ataio->data_ptr = malloc(512, M_MVS, M_NOWAIT);
1822 		if (ataio->data_ptr == NULL) {
1823 			xpt_free_ccb(ccb);
1824 			device_printf(dev,
1825 			    "Unable to allocate memory for READ LOG command\n");
1826 			goto completeall;
1827 		}
1828 		ataio->dxfer_len = 512;
1829 		bzero(&ataio->cmd, sizeof(ataio->cmd));
1830 		ataio->cmd.flags = CAM_ATAIO_48BIT;
1831 		ataio->cmd.command = 0x2F;	/* READ LOG EXT */
1832 		ataio->cmd.sector_count = 1;
1833 		ataio->cmd.sector_count_exp = 0;
1834 		ataio->cmd.lba_low = 0x10;
1835 		ataio->cmd.lba_mid = 0;
1836 		ataio->cmd.lba_mid_exp = 0;
1837 	} else {
1838 		/* REQUEST SENSE */
1839 		ccb->ccb_h.recovery_type = RECOVERY_REQUEST_SENSE;
1840 		ccb->ccb_h.recovery_slot = i;
1841 		ccb->ccb_h.func_code = XPT_SCSI_IO;
1842 		ccb->ccb_h.flags = CAM_DIR_IN;
1843 		ccb->ccb_h.status = 0;
1844 		ccb->ccb_h.timeout = 1000;	/* 1s should be enough. */
1845 		csio = &ccb->csio;
1846 		csio->data_ptr = (void *)&ch->hold[i]->csio.sense_data;
1847 		csio->dxfer_len = ch->hold[i]->csio.sense_len;
1848 		csio->cdb_len = 6;
1849 		bzero(&csio->cdb_io, sizeof(csio->cdb_io));
1850 		csio->cdb_io.cdb_bytes[0] = 0x03;
1851 		csio->cdb_io.cdb_bytes[4] = csio->dxfer_len;
1852 	}
1853 	/* Freeze SIM while doing recovery. */
1854 	ch->recoverycmd = 1;
1855 	xpt_freeze_simq(ch->sim, 1);
1856 	mvs_begin_transaction(dev, ccb);
1857 }
1858 
1859 static void
1860 mvs_process_read_log(device_t dev, union ccb *ccb)
1861 {
1862 	struct mvs_channel *ch = device_get_softc(dev);
1863 	uint8_t *data;
1864 	struct ata_res *res;
1865 	int i;
1866 
1867 	ch->recoverycmd = 0;
1868 
1869 	data = ccb->ataio.data_ptr;
1870 	if ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_CMP &&
1871 	    (data[0] & 0x80) == 0) {
1872 		for (i = 0; i < MVS_MAX_SLOTS; i++) {
1873 			if (!ch->hold[i])
1874 				continue;
1875 			if (ch->hold[i]->ccb_h.target_id != ccb->ccb_h.target_id)
1876 				continue;
1877 			if ((data[0] & 0x1F) == ch->holdtag[i]) {
1878 				res = &ch->hold[i]->ataio.res;
1879 				res->status = data[2];
1880 				res->error = data[3];
1881 				res->lba_low = data[4];
1882 				res->lba_mid = data[5];
1883 				res->lba_high = data[6];
1884 				res->device = data[7];
1885 				res->lba_low_exp = data[8];
1886 				res->lba_mid_exp = data[9];
1887 				res->lba_high_exp = data[10];
1888 				res->sector_count = data[12];
1889 				res->sector_count_exp = data[13];
1890 			} else {
1891 				ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK;
1892 				ch->hold[i]->ccb_h.status |= CAM_REQUEUE_REQ;
1893 			}
1894 			xpt_done(ch->hold[i]);
1895 			ch->hold[i] = NULL;
1896 			ch->numhslots--;
1897 		}
1898 	} else {
1899 		if ((ccb->ccb_h.status & CAM_STATUS_MASK) != CAM_REQ_CMP)
1900 			device_printf(dev, "Error while READ LOG EXT\n");
1901 		else if ((data[0] & 0x80) == 0) {
1902 			device_printf(dev,
1903 			    "Non-queued command error in READ LOG EXT\n");
1904 		}
1905 		for (i = 0; i < MVS_MAX_SLOTS; i++) {
1906 			if (!ch->hold[i])
1907 				continue;
1908 			if (ch->hold[i]->ccb_h.target_id != ccb->ccb_h.target_id)
1909 				continue;
1910 			xpt_done(ch->hold[i]);
1911 			ch->hold[i] = NULL;
1912 			ch->numhslots--;
1913 		}
1914 	}
1915 	free(ccb->ataio.data_ptr, M_MVS);
1916 	xpt_free_ccb(ccb);
1917 	xpt_release_simq(ch->sim, TRUE);
1918 }
1919 
1920 static void
1921 mvs_process_request_sense(device_t dev, union ccb *ccb)
1922 {
1923 	struct mvs_channel *ch = device_get_softc(dev);
1924 	int i;
1925 
1926 	ch->recoverycmd = 0;
1927 
1928 	i = ccb->ccb_h.recovery_slot;
1929 	if ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_CMP) {
1930 		ch->hold[i]->ccb_h.status |= CAM_AUTOSNS_VALID;
1931 	} else {
1932 		ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK;
1933 		ch->hold[i]->ccb_h.status |= CAM_AUTOSENSE_FAIL;
1934 	}
1935 	xpt_done(ch->hold[i]);
1936 	ch->hold[i] = NULL;
1937 	ch->numhslots--;
1938 	xpt_free_ccb(ccb);
1939 	xpt_release_simq(ch->sim, TRUE);
1940 }
1941 
1942 static int
1943 mvs_wait(device_t dev, u_int s, u_int c, int t)
1944 {
1945 	int timeout = 0;
1946 	uint8_t st;
1947 
1948 	while (((st =  mvs_getstatus(dev, 0)) & (s | c)) != s) {
1949 		if (timeout >= t) {
1950 			if (t != 0)
1951 				device_printf(dev, "Wait status %02x\n", st);
1952 			return (-1);
1953 		}
1954 		DELAY(1000);
1955 		timeout++;
1956 	}
1957 	return (timeout);
1958 }
1959 
1960 static void
1961 mvs_requeue_frozen(device_t dev)
1962 {
1963 	struct mvs_channel *ch = device_get_softc(dev);
1964 	union ccb *fccb = ch->frozen;
1965 
1966 	if (fccb) {
1967 		ch->frozen = NULL;
1968 		fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ;
1969 		if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) {
1970 			xpt_freeze_devq(fccb->ccb_h.path, 1);
1971 			fccb->ccb_h.status |= CAM_DEV_QFRZN;
1972 		}
1973 		xpt_done(fccb);
1974 	}
1975 }
1976 
1977 static void
1978 mvs_reset_to(void *arg)
1979 {
1980 	device_t dev = arg;
1981 	struct mvs_channel *ch = device_get_softc(dev);
1982 	int t;
1983 
1984 	if (ch->resetting == 0)
1985 		return;
1986 	ch->resetting--;
1987 	if ((t = mvs_wait(dev, 0, ATA_S_BUSY | ATA_S_DRQ, 0)) >= 0) {
1988 		if (bootverbose) {
1989 			device_printf(dev,
1990 			    "MVS reset: device ready after %dms\n",
1991 			    (310 - ch->resetting) * 100);
1992 		}
1993 		ch->resetting = 0;
1994 		xpt_release_simq(ch->sim, TRUE);
1995 		return;
1996 	}
1997 	if (ch->resetting == 0) {
1998 		device_printf(dev,
1999 		    "MVS reset: device not ready after 31000ms\n");
2000 		xpt_release_simq(ch->sim, TRUE);
2001 		return;
2002 	}
2003 	callout_schedule(&ch->reset_timer, hz / 10);
2004 }
2005 
2006 static void
2007 mvs_errata(device_t dev)
2008 {
2009 	struct mvs_channel *ch = device_get_softc(dev);
2010 	uint32_t val;
2011 
2012 	if (ch->quirks & MVS_Q_SOC65) {
2013 		val = ATA_INL(ch->r_mem, SATA_PHYM3);
2014 		val &= ~(0x3 << 27);	/* SELMUPF = 1 */
2015 		val |= (0x1 << 27);
2016 		val &= ~(0x3 << 29);	/* SELMUPI = 1 */
2017 		val |= (0x1 << 29);
2018 		ATA_OUTL(ch->r_mem, SATA_PHYM3, val);
2019 
2020 		val = ATA_INL(ch->r_mem, SATA_PHYM4);
2021 		val &= ~0x1;		/* SATU_OD8 = 0 */
2022 		val |= (0x1 << 16);	/* reserved bit 16 = 1 */
2023 		ATA_OUTL(ch->r_mem, SATA_PHYM4, val);
2024 
2025 		val = ATA_INL(ch->r_mem, SATA_PHYM9_GEN2);
2026 		val &= ~0xf;		/* TXAMP[3:0] = 8 */
2027 		val |= 0x8;
2028 		val &= ~(0x1 << 14);	/* TXAMP[4] = 0 */
2029 		ATA_OUTL(ch->r_mem, SATA_PHYM9_GEN2, val);
2030 
2031 		val = ATA_INL(ch->r_mem, SATA_PHYM9_GEN1);
2032 		val &= ~0xf;		/* TXAMP[3:0] = 8 */
2033 		val |= 0x8;
2034 		val &= ~(0x1 << 14);	/* TXAMP[4] = 0 */
2035 		ATA_OUTL(ch->r_mem, SATA_PHYM9_GEN1, val);
2036 	}
2037 }
2038 
2039 static void
2040 mvs_reset(device_t dev)
2041 {
2042 	struct mvs_channel *ch = device_get_softc(dev);
2043 	int i;
2044 
2045 	xpt_freeze_simq(ch->sim, 1);
2046 	if (bootverbose)
2047 		device_printf(dev, "MVS reset...\n");
2048 	/* Forget about previous reset. */
2049 	if (ch->resetting) {
2050 		ch->resetting = 0;
2051 		callout_stop(&ch->reset_timer);
2052 		xpt_release_simq(ch->sim, TRUE);
2053 	}
2054 	/* Requeue freezed command. */
2055 	mvs_requeue_frozen(dev);
2056 	/* Kill the engine and requeue all running commands. */
2057 	mvs_set_edma_mode(dev, MVS_EDMA_OFF);
2058 	ATA_OUTL(ch->r_mem, DMA_C, 0);
2059 	for (i = 0; i < MVS_MAX_SLOTS; i++) {
2060 		/* Do we have a running request on slot? */
2061 		if (ch->slot[i].state < MVS_SLOT_RUNNING)
2062 			continue;
2063 		/* XXX; Commands in loading state. */
2064 		mvs_end_transaction(&ch->slot[i], MVS_ERR_INNOCENT);
2065 	}
2066 	for (i = 0; i < MVS_MAX_SLOTS; i++) {
2067 		if (!ch->hold[i])
2068 			continue;
2069 		xpt_done(ch->hold[i]);
2070 		ch->hold[i] = NULL;
2071 		ch->numhslots--;
2072 	}
2073 	if (ch->toslots != 0)
2074 		xpt_release_simq(ch->sim, TRUE);
2075 	ch->eslots = 0;
2076 	ch->toslots = 0;
2077 	ch->fatalerr = 0;
2078 	ch->fake_busy = 0;
2079 	/* Tell the XPT about the event */
2080 	xpt_async(AC_BUS_RESET, ch->path, NULL);
2081 	ATA_OUTL(ch->r_mem, EDMA_IEM, 0);
2082 	ATA_OUTL(ch->r_mem, EDMA_CMD, EDMA_CMD_EATARST);
2083 	DELAY(25);
2084 	ATA_OUTL(ch->r_mem, EDMA_CMD, 0);
2085 	mvs_errata(dev);
2086 	/* Reset and reconnect PHY, */
2087 	if (!mvs_sata_phy_reset(dev)) {
2088 		if (bootverbose)
2089 			device_printf(dev, "MVS reset: device not found\n");
2090 		ch->devices = 0;
2091 		ATA_OUTL(ch->r_mem, SATA_SE, 0xffffffff);
2092 		ATA_OUTL(ch->r_mem, EDMA_IEC, 0);
2093 		ATA_OUTL(ch->r_mem, EDMA_IEM, ~EDMA_IE_TRANSIENT);
2094 		xpt_release_simq(ch->sim, TRUE);
2095 		return;
2096 	}
2097 	if (bootverbose)
2098 		device_printf(dev, "MVS reset: device found\n");
2099 	/* Wait for clearing busy status. */
2100 	if ((i = mvs_wait(dev, 0, ATA_S_BUSY | ATA_S_DRQ,
2101 	    dumping ? 31000 : 0)) < 0) {
2102 		if (dumping) {
2103 			device_printf(dev,
2104 			    "MVS reset: device not ready after 31000ms\n");
2105 		} else
2106 			ch->resetting = 310;
2107 	} else if (bootverbose)
2108 		device_printf(dev, "MVS reset: device ready after %dms\n", i);
2109 	ch->devices = 1;
2110 	ATA_OUTL(ch->r_mem, SATA_SE, 0xffffffff);
2111 	ATA_OUTL(ch->r_mem, EDMA_IEC, 0);
2112 	ATA_OUTL(ch->r_mem, EDMA_IEM, ~EDMA_IE_TRANSIENT);
2113 	if (ch->resetting)
2114 		callout_reset(&ch->reset_timer, hz / 10, mvs_reset_to, dev);
2115 	else
2116 		xpt_release_simq(ch->sim, TRUE);
2117 }
2118 
2119 static void
2120 mvs_softreset(device_t dev, union ccb *ccb)
2121 {
2122 	struct mvs_channel *ch = device_get_softc(dev);
2123 	int port = ccb->ccb_h.target_id & 0x0f;
2124 	int i, stuck;
2125 	uint8_t status;
2126 
2127 	mvs_set_edma_mode(dev, MVS_EDMA_OFF);
2128 	ATA_OUTB(ch->r_mem, SATA_SATAICTL, port << SATA_SATAICTL_PMPTX_SHIFT);
2129 	ATA_OUTB(ch->r_mem, ATA_CONTROL, ATA_A_RESET);
2130 	DELAY(10000);
2131 	ATA_OUTB(ch->r_mem, ATA_CONTROL, 0);
2132 	ccb->ccb_h.status &= ~CAM_STATUS_MASK;
2133 	/* Wait for clearing busy status. */
2134 	if ((i = mvs_wait(dev, 0, ATA_S_BUSY, ccb->ccb_h.timeout)) < 0) {
2135 		ccb->ccb_h.status |= CAM_CMD_TIMEOUT;
2136 		stuck = 1;
2137 	} else {
2138 		status = mvs_getstatus(dev, 0);
2139 		if (status & ATA_S_ERROR)
2140 			ccb->ccb_h.status |= CAM_ATA_STATUS_ERROR;
2141 		else
2142 			ccb->ccb_h.status |= CAM_REQ_CMP;
2143 		if (status & ATA_S_DRQ)
2144 			stuck = 1;
2145 		else
2146 			stuck = 0;
2147 	}
2148 	mvs_tfd_read(dev, ccb);
2149 
2150 	/*
2151 	 * XXX: If some device on PMP failed to soft-reset,
2152 	 * try to recover by sending dummy soft-reset to PMP.
2153 	 */
2154 	if (stuck && ch->pm_present && port != 15) {
2155 		ATA_OUTB(ch->r_mem, SATA_SATAICTL,
2156 		    15 << SATA_SATAICTL_PMPTX_SHIFT);
2157 		ATA_OUTB(ch->r_mem, ATA_CONTROL, ATA_A_RESET);
2158 		DELAY(10000);
2159 		ATA_OUTB(ch->r_mem, ATA_CONTROL, 0);
2160 		mvs_wait(dev, 0, ATA_S_BUSY | ATA_S_DRQ, ccb->ccb_h.timeout);
2161 	}
2162 
2163 	xpt_done(ccb);
2164 }
2165 
2166 static int
2167 mvs_sata_connect(struct mvs_channel *ch)
2168 {
2169 	u_int32_t status;
2170 	int timeout, found = 0;
2171 
2172 	/* Wait up to 100ms for "connect well" */
2173 	for (timeout = 0; timeout < 1000 ; timeout++) {
2174 		status = ATA_INL(ch->r_mem, SATA_SS);
2175 		if ((status & SATA_SS_DET_MASK) != SATA_SS_DET_NO_DEVICE)
2176 			found = 1;
2177 		if (((status & SATA_SS_DET_MASK) == SATA_SS_DET_PHY_ONLINE) &&
2178 		    ((status & SATA_SS_SPD_MASK) != SATA_SS_SPD_NO_SPEED) &&
2179 		    ((status & SATA_SS_IPM_MASK) == SATA_SS_IPM_ACTIVE))
2180 			break;
2181 		if ((status & SATA_SS_DET_MASK) == SATA_SS_DET_PHY_OFFLINE) {
2182 			if (bootverbose) {
2183 				device_printf(ch->dev, "SATA offline status=%08x\n",
2184 				    status);
2185 			}
2186 			return (0);
2187 		}
2188 		if (found == 0 && timeout >= 100)
2189 			break;
2190 		DELAY(100);
2191 	}
2192 	if (timeout >= 1000 || !found) {
2193 		if (bootverbose) {
2194 			device_printf(ch->dev,
2195 			    "SATA connect timeout time=%dus status=%08x\n",
2196 			    timeout * 100, status);
2197 		}
2198 		return (0);
2199 	}
2200 	if (bootverbose) {
2201 		device_printf(ch->dev, "SATA connect time=%dus status=%08x\n",
2202 		    timeout * 100, status);
2203 	}
2204 	/* Clear SATA error register */
2205 	ATA_OUTL(ch->r_mem, SATA_SE, 0xffffffff);
2206 	return (1);
2207 }
2208 
2209 static int
2210 mvs_sata_phy_reset(device_t dev)
2211 {
2212 	struct mvs_channel *ch = device_get_softc(dev);
2213 	int sata_rev;
2214 	uint32_t val;
2215 
2216 	sata_rev = ch->user[ch->pm_present ? 15 : 0].revision;
2217 	if (sata_rev == 1)
2218 		val = SATA_SC_SPD_SPEED_GEN1;
2219 	else if (sata_rev == 2)
2220 		val = SATA_SC_SPD_SPEED_GEN2;
2221 	else if (sata_rev == 3)
2222 		val = SATA_SC_SPD_SPEED_GEN3;
2223 	else
2224 		val = 0;
2225 	ATA_OUTL(ch->r_mem, SATA_SC,
2226 	    SATA_SC_DET_RESET | val |
2227 	    SATA_SC_IPM_DIS_PARTIAL | SATA_SC_IPM_DIS_SLUMBER);
2228 	DELAY(1000);
2229 	ATA_OUTL(ch->r_mem, SATA_SC,
2230 	    SATA_SC_DET_IDLE | val | ((ch->pm_level > 0) ? 0 :
2231 	    (SATA_SC_IPM_DIS_PARTIAL | SATA_SC_IPM_DIS_SLUMBER)));
2232 	if (!mvs_sata_connect(ch)) {
2233 		if (ch->pm_level > 0)
2234 			ATA_OUTL(ch->r_mem, SATA_SC, SATA_SC_DET_DISABLE);
2235 		return (0);
2236 	}
2237 	return (1);
2238 }
2239 
2240 static int
2241 mvs_check_ids(device_t dev, union ccb *ccb)
2242 {
2243 	struct mvs_channel *ch = device_get_softc(dev);
2244 
2245 	if (ccb->ccb_h.target_id > ((ch->quirks & MVS_Q_GENI) ? 0 : 15)) {
2246 		ccb->ccb_h.status = CAM_TID_INVALID;
2247 		xpt_done(ccb);
2248 		return (-1);
2249 	}
2250 	if (ccb->ccb_h.target_lun != 0) {
2251 		ccb->ccb_h.status = CAM_LUN_INVALID;
2252 		xpt_done(ccb);
2253 		return (-1);
2254 	}
2255 	return (0);
2256 }
2257 
2258 static void
2259 mvsaction(struct cam_sim *sim, union ccb *ccb)
2260 {
2261 	device_t dev, parent;
2262 	struct mvs_channel *ch;
2263 
2264 	CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_TRACE, ("mvsaction func_code=%x\n",
2265 	    ccb->ccb_h.func_code));
2266 
2267 	ch = (struct mvs_channel *)cam_sim_softc(sim);
2268 	dev = ch->dev;
2269 	switch (ccb->ccb_h.func_code) {
2270 	/* Common cases first */
2271 	case XPT_ATA_IO:	/* Execute the requested I/O operation */
2272 	case XPT_SCSI_IO:
2273 		if (mvs_check_ids(dev, ccb))
2274 			return;
2275 		if (ch->devices == 0 ||
2276 		    (ch->pm_present == 0 &&
2277 		     ccb->ccb_h.target_id > 0 && ccb->ccb_h.target_id < 15)) {
2278 			ccb->ccb_h.status = CAM_SEL_TIMEOUT;
2279 			break;
2280 		}
2281 		ccb->ccb_h.recovery_type = RECOVERY_NONE;
2282 		/* Check for command collision. */
2283 		if (mvs_check_collision(dev, ccb)) {
2284 			/* Freeze command. */
2285 			ch->frozen = ccb;
2286 			/* We have only one frozen slot, so freeze simq also. */
2287 			xpt_freeze_simq(ch->sim, 1);
2288 			return;
2289 		}
2290 		mvs_begin_transaction(dev, ccb);
2291 		return;
2292 	case XPT_EN_LUN:		/* Enable LUN as a target */
2293 	case XPT_TARGET_IO:		/* Execute target I/O request */
2294 	case XPT_ACCEPT_TARGET_IO:	/* Accept Host Target Mode CDB */
2295 	case XPT_CONT_TARGET_IO:	/* Continue Host Target I/O Connection*/
2296 	case XPT_ABORT:			/* Abort the specified CCB */
2297 		/* XXX Implement */
2298 		ccb->ccb_h.status = CAM_REQ_INVALID;
2299 		break;
2300 	case XPT_SET_TRAN_SETTINGS:
2301 	{
2302 		struct	ccb_trans_settings *cts = &ccb->cts;
2303 		struct	mvs_device *d;
2304 
2305 		if (mvs_check_ids(dev, ccb))
2306 			return;
2307 		if (cts->type == CTS_TYPE_CURRENT_SETTINGS)
2308 			d = &ch->curr[ccb->ccb_h.target_id];
2309 		else
2310 			d = &ch->user[ccb->ccb_h.target_id];
2311 		if (cts->xport_specific.sata.valid & CTS_SATA_VALID_REVISION)
2312 			d->revision = cts->xport_specific.sata.revision;
2313 		if (cts->xport_specific.sata.valid & CTS_SATA_VALID_MODE)
2314 			d->mode = cts->xport_specific.sata.mode;
2315 		if (cts->xport_specific.sata.valid & CTS_SATA_VALID_BYTECOUNT) {
2316 			d->bytecount = min((ch->quirks & MVS_Q_GENIIE) ? 8192 : 2048,
2317 			    cts->xport_specific.sata.bytecount);
2318 		}
2319 		if (cts->xport_specific.sata.valid & CTS_SATA_VALID_TAGS)
2320 			d->tags = min(MVS_MAX_SLOTS, cts->xport_specific.sata.tags);
2321 		if (cts->xport_specific.sata.valid & CTS_SATA_VALID_PM)
2322 			ch->pm_present = cts->xport_specific.sata.pm_present;
2323 		if (cts->xport_specific.sata.valid & CTS_SATA_VALID_ATAPI)
2324 			d->atapi = cts->xport_specific.sata.atapi;
2325 		if (cts->xport_specific.sata.valid & CTS_SATA_VALID_CAPS)
2326 			d->caps = cts->xport_specific.sata.caps;
2327 		ccb->ccb_h.status = CAM_REQ_CMP;
2328 		break;
2329 	}
2330 	case XPT_GET_TRAN_SETTINGS:
2331 	/* Get default/user set transfer settings for the target */
2332 	{
2333 		struct	ccb_trans_settings *cts = &ccb->cts;
2334 		struct  mvs_device *d;
2335 		uint32_t status;
2336 
2337 		if (mvs_check_ids(dev, ccb))
2338 			return;
2339 		if (cts->type == CTS_TYPE_CURRENT_SETTINGS)
2340 			d = &ch->curr[ccb->ccb_h.target_id];
2341 		else
2342 			d = &ch->user[ccb->ccb_h.target_id];
2343 		cts->protocol = PROTO_UNSPECIFIED;
2344 		cts->protocol_version = PROTO_VERSION_UNSPECIFIED;
2345 		cts->transport = XPORT_SATA;
2346 		cts->transport_version = XPORT_VERSION_UNSPECIFIED;
2347 		cts->proto_specific.valid = 0;
2348 		cts->xport_specific.sata.valid = 0;
2349 		if (cts->type == CTS_TYPE_CURRENT_SETTINGS &&
2350 		    (ccb->ccb_h.target_id == 15 ||
2351 		    (ccb->ccb_h.target_id == 0 && !ch->pm_present))) {
2352 			status = ATA_INL(ch->r_mem, SATA_SS) & SATA_SS_SPD_MASK;
2353 			if (status & 0x0f0) {
2354 				cts->xport_specific.sata.revision =
2355 				    (status & 0x0f0) >> 4;
2356 				cts->xport_specific.sata.valid |=
2357 				    CTS_SATA_VALID_REVISION;
2358 			}
2359 			cts->xport_specific.sata.caps = d->caps & CTS_SATA_CAPS_D;
2360 //			if (ch->pm_level)
2361 //				cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_PMREQ;
2362 			cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_AN;
2363 			cts->xport_specific.sata.caps &=
2364 			    ch->user[ccb->ccb_h.target_id].caps;
2365 			cts->xport_specific.sata.valid |= CTS_SATA_VALID_CAPS;
2366 		} else {
2367 			cts->xport_specific.sata.revision = d->revision;
2368 			cts->xport_specific.sata.valid |= CTS_SATA_VALID_REVISION;
2369 			cts->xport_specific.sata.caps = d->caps;
2370 			if (cts->type == CTS_TYPE_CURRENT_SETTINGS/* &&
2371 			    (ch->quirks & MVS_Q_GENIIE) == 0*/)
2372 				cts->xport_specific.sata.caps &= ~CTS_SATA_CAPS_H_AN;
2373 			cts->xport_specific.sata.valid |= CTS_SATA_VALID_CAPS;
2374 		}
2375 		cts->xport_specific.sata.mode = d->mode;
2376 		cts->xport_specific.sata.valid |= CTS_SATA_VALID_MODE;
2377 		cts->xport_specific.sata.bytecount = d->bytecount;
2378 		cts->xport_specific.sata.valid |= CTS_SATA_VALID_BYTECOUNT;
2379 		cts->xport_specific.sata.pm_present = ch->pm_present;
2380 		cts->xport_specific.sata.valid |= CTS_SATA_VALID_PM;
2381 		cts->xport_specific.sata.tags = d->tags;
2382 		cts->xport_specific.sata.valid |= CTS_SATA_VALID_TAGS;
2383 		cts->xport_specific.sata.atapi = d->atapi;
2384 		cts->xport_specific.sata.valid |= CTS_SATA_VALID_ATAPI;
2385 		ccb->ccb_h.status = CAM_REQ_CMP;
2386 		break;
2387 	}
2388 	case XPT_RESET_BUS:		/* Reset the specified SCSI bus */
2389 	case XPT_RESET_DEV:	/* Bus Device Reset the specified SCSI device */
2390 		mvs_reset(dev);
2391 		ccb->ccb_h.status = CAM_REQ_CMP;
2392 		break;
2393 	case XPT_TERM_IO:		/* Terminate the I/O process */
2394 		/* XXX Implement */
2395 		ccb->ccb_h.status = CAM_REQ_INVALID;
2396 		break;
2397 	case XPT_PATH_INQ:		/* Path routing inquiry */
2398 	{
2399 		struct ccb_pathinq *cpi = &ccb->cpi;
2400 
2401 		parent = device_get_parent(dev);
2402 		cpi->version_num = 1; /* XXX??? */
2403 		cpi->hba_inquiry = PI_SDTR_ABLE;
2404 		if (!(ch->quirks & MVS_Q_GENI)) {
2405 			cpi->hba_inquiry |= PI_SATAPM;
2406 			/* Gen-II is extremely slow with NCQ on PMP. */
2407 			if ((ch->quirks & MVS_Q_GENIIE) || ch->pm_present == 0)
2408 				cpi->hba_inquiry |= PI_TAG_ABLE;
2409 		}
2410 		cpi->target_sprt = 0;
2411 		cpi->hba_misc = PIM_SEQSCAN;
2412 		cpi->hba_eng_cnt = 0;
2413 		if (!(ch->quirks & MVS_Q_GENI))
2414 			cpi->max_target = 15;
2415 		else
2416 			cpi->max_target = 0;
2417 		cpi->max_lun = 0;
2418 		cpi->initiator_id = 0;
2419 		cpi->bus_id = cam_sim_bus(sim);
2420 		cpi->base_transfer_speed = 150000;
2421 		strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN);
2422 		strncpy(cpi->hba_vid, "Marvell", HBA_IDLEN);
2423 		strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN);
2424 		cpi->unit_number = cam_sim_unit(sim);
2425 		cpi->transport = XPORT_SATA;
2426 		cpi->transport_version = XPORT_VERSION_UNSPECIFIED;
2427 		cpi->protocol = PROTO_ATA;
2428 		cpi->protocol_version = PROTO_VERSION_UNSPECIFIED;
2429 		cpi->maxio = MAXPHYS;
2430 		if ((ch->quirks & MVS_Q_SOC) == 0) {
2431 			cpi->hba_vendor = pci_get_vendor(parent);
2432 			cpi->hba_device = pci_get_device(parent);
2433 			cpi->hba_subvendor = pci_get_subvendor(parent);
2434 			cpi->hba_subdevice = pci_get_subdevice(parent);
2435 		}
2436 		cpi->ccb_h.status = CAM_REQ_CMP;
2437 		break;
2438 	}
2439 	default:
2440 		ccb->ccb_h.status = CAM_REQ_INVALID;
2441 		break;
2442 	}
2443 	xpt_done(ccb);
2444 }
2445 
2446 static void
2447 mvspoll(struct cam_sim *sim)
2448 {
2449 	struct mvs_channel *ch = (struct mvs_channel *)cam_sim_softc(sim);
2450 	struct mvs_intr_arg arg;
2451 
2452 	arg.arg = ch->dev;
2453 	arg.cause = 2 | 4; /* XXX */
2454 	mvs_ch_intr(&arg);
2455 	if (ch->resetting != 0 &&
2456 	    (--ch->resetpolldiv <= 0 || !callout_pending(&ch->reset_timer))) {
2457 		ch->resetpolldiv = 1000;
2458 		mvs_reset_to(ch->dev);
2459 	}
2460 }
2461 
2462