1 /*- 2 * Copyright (c) 2010 Alexander Motin <mav@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include <sys/param.h> 31 #include <sys/module.h> 32 #include <sys/systm.h> 33 #include <sys/kernel.h> 34 #include <sys/ata.h> 35 #include <sys/bus.h> 36 #include <sys/conf.h> 37 #include <sys/endian.h> 38 #include <sys/malloc.h> 39 #include <sys/lock.h> 40 #include <sys/mutex.h> 41 #include <vm/uma.h> 42 #include <machine/stdarg.h> 43 #include <machine/resource.h> 44 #include <machine/bus.h> 45 #include <sys/rman.h> 46 #include <dev/pci/pcivar.h> 47 #include "mvs.h" 48 49 #include <cam/cam.h> 50 #include <cam/cam_ccb.h> 51 #include <cam/cam_sim.h> 52 #include <cam/cam_xpt_sim.h> 53 #include <cam/cam_debug.h> 54 55 /* local prototypes */ 56 static int mvs_ch_init(device_t dev); 57 static int mvs_ch_deinit(device_t dev); 58 static int mvs_ch_suspend(device_t dev); 59 static int mvs_ch_resume(device_t dev); 60 static void mvs_dmainit(device_t dev); 61 static void mvs_dmasetupc_cb(void *xsc, 62 bus_dma_segment_t *segs, int nsegs, int error); 63 static void mvs_dmafini(device_t dev); 64 static void mvs_slotsalloc(device_t dev); 65 static void mvs_slotsfree(device_t dev); 66 static void mvs_setup_edma_queues(device_t dev); 67 static void mvs_set_edma_mode(device_t dev, enum mvs_edma_mode mode); 68 static void mvs_ch_pm(void *arg); 69 static void mvs_ch_intr_locked(void *data); 70 static void mvs_ch_intr(void *data); 71 static void mvs_reset(device_t dev); 72 static void mvs_softreset(device_t dev, union ccb *ccb); 73 74 static int mvs_sata_connect(struct mvs_channel *ch); 75 static int mvs_sata_phy_reset(device_t dev); 76 static int mvs_wait(device_t dev, u_int s, u_int c, int t); 77 static void mvs_tfd_read(device_t dev, union ccb *ccb); 78 static void mvs_tfd_write(device_t dev, union ccb *ccb); 79 static void mvs_legacy_intr(device_t dev, int poll); 80 static void mvs_crbq_intr(device_t dev); 81 static void mvs_begin_transaction(device_t dev, union ccb *ccb); 82 static void mvs_legacy_execute_transaction(struct mvs_slot *slot); 83 static void mvs_timeout(struct mvs_slot *slot); 84 static void mvs_dmasetprd(void *arg, 85 bus_dma_segment_t *segs, int nsegs, int error); 86 static void mvs_requeue_frozen(device_t dev); 87 static void mvs_execute_transaction(struct mvs_slot *slot); 88 static void mvs_end_transaction(struct mvs_slot *slot, enum mvs_err_type et); 89 90 static void mvs_issue_recovery(device_t dev); 91 static void mvs_process_read_log(device_t dev, union ccb *ccb); 92 static void mvs_process_request_sense(device_t dev, union ccb *ccb); 93 94 static void mvsaction(struct cam_sim *sim, union ccb *ccb); 95 static void mvspoll(struct cam_sim *sim); 96 97 static MALLOC_DEFINE(M_MVS, "MVS driver", "MVS driver data buffers"); 98 99 #define recovery_type spriv_field0 100 #define RECOVERY_NONE 0 101 #define RECOVERY_READ_LOG 1 102 #define RECOVERY_REQUEST_SENSE 2 103 #define recovery_slot spriv_field1 104 105 static int 106 mvs_ch_probe(device_t dev) 107 { 108 109 device_set_desc_copy(dev, "Marvell SATA channel"); 110 return (0); 111 } 112 113 static int 114 mvs_ch_attach(device_t dev) 115 { 116 struct mvs_controller *ctlr = device_get_softc(device_get_parent(dev)); 117 struct mvs_channel *ch = device_get_softc(dev); 118 struct cam_devq *devq; 119 int rid, error, i, sata_rev = 0; 120 121 ch->dev = dev; 122 ch->unit = (intptr_t)device_get_ivars(dev); 123 ch->quirks = ctlr->quirks; 124 mtx_init(&ch->mtx, "MVS channel lock", NULL, MTX_DEF); 125 resource_int_value(device_get_name(dev), 126 device_get_unit(dev), "pm_level", &ch->pm_level); 127 if (ch->pm_level > 3) 128 callout_init_mtx(&ch->pm_timer, &ch->mtx, 0); 129 callout_init_mtx(&ch->reset_timer, &ch->mtx, 0); 130 resource_int_value(device_get_name(dev), 131 device_get_unit(dev), "sata_rev", &sata_rev); 132 for (i = 0; i < 16; i++) { 133 ch->user[i].revision = sata_rev; 134 ch->user[i].mode = 0; 135 ch->user[i].bytecount = (ch->quirks & MVS_Q_GENIIE) ? 8192 : 2048; 136 ch->user[i].tags = MVS_MAX_SLOTS; 137 ch->curr[i] = ch->user[i]; 138 if (ch->pm_level) { 139 ch->user[i].caps = CTS_SATA_CAPS_H_PMREQ | 140 CTS_SATA_CAPS_H_APST | 141 CTS_SATA_CAPS_D_PMREQ | CTS_SATA_CAPS_D_APST; 142 } 143 ch->user[i].caps |= CTS_SATA_CAPS_H_AN; 144 } 145 rid = ch->unit; 146 if (!(ch->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 147 &rid, RF_ACTIVE))) 148 return (ENXIO); 149 mvs_dmainit(dev); 150 mvs_slotsalloc(dev); 151 mvs_ch_init(dev); 152 mtx_lock(&ch->mtx); 153 rid = ATA_IRQ_RID; 154 if (!(ch->r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 155 &rid, RF_SHAREABLE | RF_ACTIVE))) { 156 device_printf(dev, "Unable to map interrupt\n"); 157 error = ENXIO; 158 goto err0; 159 } 160 if ((bus_setup_intr(dev, ch->r_irq, ATA_INTR_FLAGS, NULL, 161 mvs_ch_intr_locked, dev, &ch->ih))) { 162 device_printf(dev, "Unable to setup interrupt\n"); 163 error = ENXIO; 164 goto err1; 165 } 166 /* Create the device queue for our SIM. */ 167 devq = cam_simq_alloc(MVS_MAX_SLOTS - 1); 168 if (devq == NULL) { 169 device_printf(dev, "Unable to allocate simq\n"); 170 error = ENOMEM; 171 goto err1; 172 } 173 /* Construct SIM entry */ 174 ch->sim = cam_sim_alloc(mvsaction, mvspoll, "mvsch", ch, 175 device_get_unit(dev), &ch->mtx, 176 2, (ch->quirks & MVS_Q_GENI) ? 0 : MVS_MAX_SLOTS - 1, 177 devq); 178 if (ch->sim == NULL) { 179 cam_simq_free(devq); 180 device_printf(dev, "unable to allocate sim\n"); 181 error = ENOMEM; 182 goto err1; 183 } 184 if (xpt_bus_register(ch->sim, dev, 0) != CAM_SUCCESS) { 185 device_printf(dev, "unable to register xpt bus\n"); 186 error = ENXIO; 187 goto err2; 188 } 189 if (xpt_create_path(&ch->path, /*periph*/NULL, cam_sim_path(ch->sim), 190 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 191 device_printf(dev, "unable to create path\n"); 192 error = ENXIO; 193 goto err3; 194 } 195 if (ch->pm_level > 3) { 196 callout_reset(&ch->pm_timer, 197 (ch->pm_level == 4) ? hz / 1000 : hz / 8, 198 mvs_ch_pm, dev); 199 } 200 mtx_unlock(&ch->mtx); 201 return (0); 202 203 err3: 204 xpt_bus_deregister(cam_sim_path(ch->sim)); 205 err2: 206 cam_sim_free(ch->sim, /*free_devq*/TRUE); 207 err1: 208 bus_release_resource(dev, SYS_RES_IRQ, ATA_IRQ_RID, ch->r_irq); 209 err0: 210 bus_release_resource(dev, SYS_RES_MEMORY, ch->unit, ch->r_mem); 211 mtx_unlock(&ch->mtx); 212 mtx_destroy(&ch->mtx); 213 return (error); 214 } 215 216 static int 217 mvs_ch_detach(device_t dev) 218 { 219 struct mvs_channel *ch = device_get_softc(dev); 220 221 mtx_lock(&ch->mtx); 222 xpt_async(AC_LOST_DEVICE, ch->path, NULL); 223 /* Forget about reset. */ 224 if (ch->resetting) { 225 ch->resetting = 0; 226 xpt_release_simq(ch->sim, TRUE); 227 } 228 xpt_free_path(ch->path); 229 xpt_bus_deregister(cam_sim_path(ch->sim)); 230 cam_sim_free(ch->sim, /*free_devq*/TRUE); 231 mtx_unlock(&ch->mtx); 232 233 if (ch->pm_level > 3) 234 callout_drain(&ch->pm_timer); 235 callout_drain(&ch->reset_timer); 236 bus_teardown_intr(dev, ch->r_irq, ch->ih); 237 bus_release_resource(dev, SYS_RES_IRQ, ATA_IRQ_RID, ch->r_irq); 238 239 mvs_ch_deinit(dev); 240 mvs_slotsfree(dev); 241 mvs_dmafini(dev); 242 243 bus_release_resource(dev, SYS_RES_MEMORY, ch->unit, ch->r_mem); 244 mtx_destroy(&ch->mtx); 245 return (0); 246 } 247 248 static int 249 mvs_ch_init(device_t dev) 250 { 251 struct mvs_channel *ch = device_get_softc(dev); 252 uint32_t reg; 253 254 /* Disable port interrupts */ 255 ATA_OUTL(ch->r_mem, EDMA_IEM, 0); 256 /* Stop EDMA */ 257 ch->curr_mode = MVS_EDMA_UNKNOWN; 258 mvs_set_edma_mode(dev, MVS_EDMA_OFF); 259 /* Clear and configure FIS interrupts. */ 260 ATA_OUTL(ch->r_mem, SATA_FISIC, 0); 261 reg = ATA_INL(ch->r_mem, SATA_FISC); 262 reg |= SATA_FISC_FISWAIT4HOSTRDYEN_B1; 263 ATA_OUTL(ch->r_mem, SATA_FISC, reg); 264 reg = ATA_INL(ch->r_mem, SATA_FISIM); 265 reg |= SATA_FISC_FISWAIT4HOSTRDYEN_B1; 266 ATA_OUTL(ch->r_mem, SATA_FISC, reg); 267 /* Clear SATA error register. */ 268 ATA_OUTL(ch->r_mem, SATA_SE, 0xffffffff); 269 /* Clear any outstanding error interrupts. */ 270 ATA_OUTL(ch->r_mem, EDMA_IEC, 0); 271 /* Unmask all error interrupts */ 272 ATA_OUTL(ch->r_mem, EDMA_IEM, ~EDMA_IE_TRANSIENT); 273 return (0); 274 } 275 276 static int 277 mvs_ch_deinit(device_t dev) 278 { 279 struct mvs_channel *ch = device_get_softc(dev); 280 281 /* Stop EDMA */ 282 mvs_set_edma_mode(dev, MVS_EDMA_OFF); 283 /* Disable port interrupts. */ 284 ATA_OUTL(ch->r_mem, EDMA_IEM, 0); 285 return (0); 286 } 287 288 static int 289 mvs_ch_suspend(device_t dev) 290 { 291 struct mvs_channel *ch = device_get_softc(dev); 292 293 mtx_lock(&ch->mtx); 294 xpt_freeze_simq(ch->sim, 1); 295 while (ch->oslots) 296 msleep(ch, &ch->mtx, PRIBIO, "mvssusp", hz/100); 297 /* Forget about reset. */ 298 if (ch->resetting) { 299 ch->resetting = 0; 300 callout_stop(&ch->reset_timer); 301 xpt_release_simq(ch->sim, TRUE); 302 } 303 mvs_ch_deinit(dev); 304 mtx_unlock(&ch->mtx); 305 return (0); 306 } 307 308 static int 309 mvs_ch_resume(device_t dev) 310 { 311 struct mvs_channel *ch = device_get_softc(dev); 312 313 mtx_lock(&ch->mtx); 314 mvs_ch_init(dev); 315 mvs_reset(dev); 316 xpt_release_simq(ch->sim, TRUE); 317 mtx_unlock(&ch->mtx); 318 return (0); 319 } 320 321 struct mvs_dc_cb_args { 322 bus_addr_t maddr; 323 int error; 324 }; 325 326 static void 327 mvs_dmainit(device_t dev) 328 { 329 struct mvs_channel *ch = device_get_softc(dev); 330 struct mvs_dc_cb_args dcba; 331 332 /* EDMA command request area. */ 333 if (bus_dma_tag_create(bus_get_dma_tag(dev), 1024, 0, 334 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 335 NULL, NULL, MVS_WORKRQ_SIZE, 1, MVS_WORKRQ_SIZE, 336 0, NULL, NULL, &ch->dma.workrq_tag)) 337 goto error; 338 if (bus_dmamem_alloc(ch->dma.workrq_tag, (void **)&ch->dma.workrq, 0, 339 &ch->dma.workrq_map)) 340 goto error; 341 if (bus_dmamap_load(ch->dma.workrq_tag, ch->dma.workrq_map, 342 ch->dma.workrq, MVS_WORKRQ_SIZE, mvs_dmasetupc_cb, &dcba, 0) || 343 dcba.error) { 344 bus_dmamem_free(ch->dma.workrq_tag, 345 ch->dma.workrq, ch->dma.workrq_map); 346 goto error; 347 } 348 ch->dma.workrq_bus = dcba.maddr; 349 /* EDMA command response area. */ 350 if (bus_dma_tag_create(bus_get_dma_tag(dev), 256, 0, 351 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 352 NULL, NULL, MVS_WORKRP_SIZE, 1, MVS_WORKRP_SIZE, 353 0, NULL, NULL, &ch->dma.workrp_tag)) 354 goto error; 355 if (bus_dmamem_alloc(ch->dma.workrp_tag, (void **)&ch->dma.workrp, 0, 356 &ch->dma.workrp_map)) 357 goto error; 358 if (bus_dmamap_load(ch->dma.workrp_tag, ch->dma.workrp_map, 359 ch->dma.workrp, MVS_WORKRP_SIZE, mvs_dmasetupc_cb, &dcba, 0) || 360 dcba.error) { 361 bus_dmamem_free(ch->dma.workrp_tag, 362 ch->dma.workrp, ch->dma.workrp_map); 363 goto error; 364 } 365 ch->dma.workrp_bus = dcba.maddr; 366 /* Data area. */ 367 if (bus_dma_tag_create(bus_get_dma_tag(dev), 2, MVS_EPRD_MAX, 368 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, 369 NULL, NULL, 370 MVS_SG_ENTRIES * PAGE_SIZE * MVS_MAX_SLOTS, 371 MVS_SG_ENTRIES, MVS_EPRD_MAX, 372 0, busdma_lock_mutex, &ch->mtx, &ch->dma.data_tag)) { 373 goto error; 374 } 375 return; 376 377 error: 378 device_printf(dev, "WARNING - DMA initialization failed\n"); 379 mvs_dmafini(dev); 380 } 381 382 static void 383 mvs_dmasetupc_cb(void *xsc, bus_dma_segment_t *segs, int nsegs, int error) 384 { 385 struct mvs_dc_cb_args *dcba = (struct mvs_dc_cb_args *)xsc; 386 387 if (!(dcba->error = error)) 388 dcba->maddr = segs[0].ds_addr; 389 } 390 391 static void 392 mvs_dmafini(device_t dev) 393 { 394 struct mvs_channel *ch = device_get_softc(dev); 395 396 if (ch->dma.data_tag) { 397 bus_dma_tag_destroy(ch->dma.data_tag); 398 ch->dma.data_tag = NULL; 399 } 400 if (ch->dma.workrp_bus) { 401 bus_dmamap_unload(ch->dma.workrp_tag, ch->dma.workrp_map); 402 bus_dmamem_free(ch->dma.workrp_tag, 403 ch->dma.workrp, ch->dma.workrp_map); 404 ch->dma.workrp_bus = 0; 405 ch->dma.workrp_map = NULL; 406 ch->dma.workrp = NULL; 407 } 408 if (ch->dma.workrp_tag) { 409 bus_dma_tag_destroy(ch->dma.workrp_tag); 410 ch->dma.workrp_tag = NULL; 411 } 412 if (ch->dma.workrq_bus) { 413 bus_dmamap_unload(ch->dma.workrq_tag, ch->dma.workrq_map); 414 bus_dmamem_free(ch->dma.workrq_tag, 415 ch->dma.workrq, ch->dma.workrq_map); 416 ch->dma.workrq_bus = 0; 417 ch->dma.workrq_map = NULL; 418 ch->dma.workrq = NULL; 419 } 420 if (ch->dma.workrq_tag) { 421 bus_dma_tag_destroy(ch->dma.workrq_tag); 422 ch->dma.workrq_tag = NULL; 423 } 424 } 425 426 static void 427 mvs_slotsalloc(device_t dev) 428 { 429 struct mvs_channel *ch = device_get_softc(dev); 430 int i; 431 432 /* Alloc and setup command/dma slots */ 433 bzero(ch->slot, sizeof(ch->slot)); 434 for (i = 0; i < MVS_MAX_SLOTS; i++) { 435 struct mvs_slot *slot = &ch->slot[i]; 436 437 slot->dev = dev; 438 slot->slot = i; 439 slot->state = MVS_SLOT_EMPTY; 440 slot->ccb = NULL; 441 callout_init_mtx(&slot->timeout, &ch->mtx, 0); 442 443 if (bus_dmamap_create(ch->dma.data_tag, 0, &slot->dma.data_map)) 444 device_printf(ch->dev, "FAILURE - create data_map\n"); 445 } 446 } 447 448 static void 449 mvs_slotsfree(device_t dev) 450 { 451 struct mvs_channel *ch = device_get_softc(dev); 452 int i; 453 454 /* Free all dma slots */ 455 for (i = 0; i < MVS_MAX_SLOTS; i++) { 456 struct mvs_slot *slot = &ch->slot[i]; 457 458 callout_drain(&slot->timeout); 459 if (slot->dma.data_map) { 460 bus_dmamap_destroy(ch->dma.data_tag, slot->dma.data_map); 461 slot->dma.data_map = NULL; 462 } 463 } 464 } 465 466 static void 467 mvs_setup_edma_queues(device_t dev) 468 { 469 struct mvs_channel *ch = device_get_softc(dev); 470 uint64_t work; 471 472 /* Requests queue. */ 473 work = ch->dma.workrq_bus; 474 ATA_OUTL(ch->r_mem, EDMA_REQQBAH, work >> 32); 475 ATA_OUTL(ch->r_mem, EDMA_REQQIP, work & 0xffffffff); 476 ATA_OUTL(ch->r_mem, EDMA_REQQOP, work & 0xffffffff); 477 bus_dmamap_sync(ch->dma.workrq_tag, ch->dma.workrq_map, 478 BUS_DMASYNC_PREWRITE); 479 /* Reponses queue. */ 480 memset(ch->dma.workrp, 0xff, MVS_WORKRP_SIZE); 481 work = ch->dma.workrp_bus; 482 ATA_OUTL(ch->r_mem, EDMA_RESQBAH, work >> 32); 483 ATA_OUTL(ch->r_mem, EDMA_RESQIP, work & 0xffffffff); 484 ATA_OUTL(ch->r_mem, EDMA_RESQOP, work & 0xffffffff); 485 bus_dmamap_sync(ch->dma.workrp_tag, ch->dma.workrp_map, 486 BUS_DMASYNC_PREREAD); 487 ch->out_idx = 0; 488 ch->in_idx = 0; 489 } 490 491 static void 492 mvs_set_edma_mode(device_t dev, enum mvs_edma_mode mode) 493 { 494 struct mvs_channel *ch = device_get_softc(dev); 495 int timeout; 496 uint32_t ecfg, fcfg, hc, ltm, unkn; 497 498 if (mode == ch->curr_mode) 499 return; 500 /* If we are running, we should stop first. */ 501 if (ch->curr_mode != MVS_EDMA_OFF) { 502 ATA_OUTL(ch->r_mem, EDMA_CMD, EDMA_CMD_EDSEDMA); 503 timeout = 0; 504 while (ATA_INL(ch->r_mem, EDMA_CMD) & EDMA_CMD_EENEDMA) { 505 DELAY(1000); 506 if (timeout++ > 1000) { 507 device_printf(dev, "stopping EDMA engine failed\n"); 508 break; 509 } 510 }; 511 } 512 ch->curr_mode = mode; 513 ch->fbs_enabled = 0; 514 ch->fake_busy = 0; 515 /* Report mode to controller. Needed for correct CCC operation. */ 516 MVS_EDMA(device_get_parent(dev), dev, mode); 517 /* Configure new mode. */ 518 ecfg = EDMA_CFG_RESERVED | EDMA_CFG_RESERVED2 | EDMA_CFG_EHOSTQUEUECACHEEN; 519 if (ch->pm_present) { 520 ecfg |= EDMA_CFG_EMASKRXPM; 521 if (ch->quirks & MVS_Q_GENIIE) { 522 ecfg |= EDMA_CFG_EEDMAFBS; 523 ch->fbs_enabled = 1; 524 } 525 } 526 if (ch->quirks & MVS_Q_GENI) 527 ecfg |= EDMA_CFG_ERDBSZ; 528 else if (ch->quirks & MVS_Q_GENII) 529 ecfg |= EDMA_CFG_ERDBSZEXT | EDMA_CFG_EWRBUFFERLEN; 530 if (ch->quirks & MVS_Q_CT) 531 ecfg |= EDMA_CFG_ECUTTHROUGHEN; 532 if (mode != MVS_EDMA_OFF) 533 ecfg |= EDMA_CFG_EEARLYCOMPLETIONEN; 534 if (mode == MVS_EDMA_QUEUED) 535 ecfg |= EDMA_CFG_EQUE; 536 else if (mode == MVS_EDMA_NCQ) 537 ecfg |= EDMA_CFG_ESATANATVCMDQUE; 538 ATA_OUTL(ch->r_mem, EDMA_CFG, ecfg); 539 mvs_setup_edma_queues(dev); 540 if (ch->quirks & MVS_Q_GENIIE) { 541 /* Configure FBS-related registers */ 542 fcfg = ATA_INL(ch->r_mem, SATA_FISC); 543 ltm = ATA_INL(ch->r_mem, SATA_LTM); 544 hc = ATA_INL(ch->r_mem, EDMA_HC); 545 if (ch->fbs_enabled) { 546 fcfg |= SATA_FISC_FISDMAACTIVATESYNCRESP; 547 if (mode == MVS_EDMA_NCQ) { 548 fcfg &= ~SATA_FISC_FISWAIT4HOSTRDYEN_B0; 549 hc &= ~EDMA_IE_EDEVERR; 550 } else { 551 fcfg |= SATA_FISC_FISWAIT4HOSTRDYEN_B0; 552 hc |= EDMA_IE_EDEVERR; 553 } 554 ltm |= (1 << 8); 555 } else { 556 fcfg &= ~SATA_FISC_FISDMAACTIVATESYNCRESP; 557 fcfg &= ~SATA_FISC_FISWAIT4HOSTRDYEN_B0; 558 hc |= EDMA_IE_EDEVERR; 559 ltm &= ~(1 << 8); 560 } 561 ATA_OUTL(ch->r_mem, SATA_FISC, fcfg); 562 ATA_OUTL(ch->r_mem, SATA_LTM, ltm); 563 ATA_OUTL(ch->r_mem, EDMA_HC, hc); 564 /* This is some magic, required to handle several DRQs 565 * with basic DMA. */ 566 unkn = ATA_INL(ch->r_mem, EDMA_UNKN_RESD); 567 if (mode == MVS_EDMA_OFF) 568 unkn |= 1; 569 else 570 unkn &= ~1; 571 ATA_OUTL(ch->r_mem, EDMA_UNKN_RESD, unkn); 572 } 573 /* Run EDMA. */ 574 if (mode != MVS_EDMA_OFF) 575 ATA_OUTL(ch->r_mem, EDMA_CMD, EDMA_CMD_EENEDMA); 576 } 577 578 devclass_t mvs_devclass; 579 devclass_t mvsch_devclass; 580 static device_method_t mvsch_methods[] = { 581 DEVMETHOD(device_probe, mvs_ch_probe), 582 DEVMETHOD(device_attach, mvs_ch_attach), 583 DEVMETHOD(device_detach, mvs_ch_detach), 584 DEVMETHOD(device_suspend, mvs_ch_suspend), 585 DEVMETHOD(device_resume, mvs_ch_resume), 586 { 0, 0 } 587 }; 588 static driver_t mvsch_driver = { 589 "mvsch", 590 mvsch_methods, 591 sizeof(struct mvs_channel) 592 }; 593 DRIVER_MODULE(mvsch, mvs, mvsch_driver, mvsch_devclass, 0, 0); 594 DRIVER_MODULE(mvsch, sata, mvsch_driver, mvsch_devclass, 0, 0); 595 596 static void 597 mvs_phy_check_events(device_t dev, u_int32_t serr) 598 { 599 struct mvs_channel *ch = device_get_softc(dev); 600 601 if (ch->pm_level == 0) { 602 u_int32_t status = ATA_INL(ch->r_mem, SATA_SS); 603 union ccb *ccb; 604 605 if (bootverbose) { 606 if (((status & SATA_SS_DET_MASK) == SATA_SS_DET_PHY_ONLINE) && 607 ((status & SATA_SS_SPD_MASK) != SATA_SS_SPD_NO_SPEED) && 608 ((status & SATA_SS_IPM_MASK) == SATA_SS_IPM_ACTIVE)) { 609 device_printf(dev, "CONNECT requested\n"); 610 } else 611 device_printf(dev, "DISCONNECT requested\n"); 612 } 613 mvs_reset(dev); 614 if ((ccb = xpt_alloc_ccb_nowait()) == NULL) 615 return; 616 if (xpt_create_path(&ccb->ccb_h.path, NULL, 617 cam_sim_path(ch->sim), 618 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 619 xpt_free_ccb(ccb); 620 return; 621 } 622 xpt_rescan(ccb); 623 } 624 } 625 626 static void 627 mvs_notify_events(device_t dev) 628 { 629 struct mvs_channel *ch = device_get_softc(dev); 630 struct cam_path *dpath; 631 uint32_t fis; 632 int d; 633 634 /* Try to read PMP field from SDB FIS. Present only for Gen-IIe. */ 635 fis = ATA_INL(ch->r_mem, SATA_FISDW0); 636 if ((fis & 0x80ff) == 0x80a1) 637 d = (fis & 0x0f00) >> 8; 638 else 639 d = ch->pm_present ? 15 : 0; 640 if (bootverbose) 641 device_printf(dev, "SNTF %d\n", d); 642 if (xpt_create_path(&dpath, NULL, 643 xpt_path_path_id(ch->path), d, 0) == CAM_REQ_CMP) { 644 xpt_async(AC_SCSI_AEN, dpath, NULL); 645 xpt_free_path(dpath); 646 } 647 } 648 649 static void 650 mvs_ch_intr_locked(void *data) 651 { 652 struct mvs_intr_arg *arg = (struct mvs_intr_arg *)data; 653 device_t dev = (device_t)arg->arg; 654 struct mvs_channel *ch = device_get_softc(dev); 655 656 mtx_lock(&ch->mtx); 657 mvs_ch_intr(data); 658 mtx_unlock(&ch->mtx); 659 } 660 661 static void 662 mvs_ch_pm(void *arg) 663 { 664 device_t dev = (device_t)arg; 665 struct mvs_channel *ch = device_get_softc(dev); 666 uint32_t work; 667 668 if (ch->numrslots != 0) 669 return; 670 /* If we are idle - request power state transition. */ 671 work = ATA_INL(ch->r_mem, SATA_SC); 672 work &= ~SATA_SC_SPM_MASK; 673 if (ch->pm_level == 4) 674 work |= SATA_SC_SPM_PARTIAL; 675 else 676 work |= SATA_SC_SPM_SLUMBER; 677 ATA_OUTL(ch->r_mem, SATA_SC, work); 678 } 679 680 static void 681 mvs_ch_pm_wake(device_t dev) 682 { 683 struct mvs_channel *ch = device_get_softc(dev); 684 uint32_t work; 685 int timeout = 0; 686 687 work = ATA_INL(ch->r_mem, SATA_SS); 688 if (work & SATA_SS_IPM_ACTIVE) 689 return; 690 /* If we are not in active state - request power state transition. */ 691 work = ATA_INL(ch->r_mem, SATA_SC); 692 work &= ~SATA_SC_SPM_MASK; 693 work |= SATA_SC_SPM_ACTIVE; 694 ATA_OUTL(ch->r_mem, SATA_SC, work); 695 /* Wait for transition to happen. */ 696 while ((ATA_INL(ch->r_mem, SATA_SS) & SATA_SS_IPM_ACTIVE) == 0 && 697 timeout++ < 100) { 698 DELAY(100); 699 } 700 } 701 702 static void 703 mvs_ch_intr(void *data) 704 { 705 struct mvs_intr_arg *arg = (struct mvs_intr_arg *)data; 706 device_t dev = (device_t)arg->arg; 707 struct mvs_channel *ch = device_get_softc(dev); 708 uint32_t iec, serr = 0, fisic = 0; 709 enum mvs_err_type et; 710 int i, ccs, port = -1, selfdis = 0; 711 int edma = (ch->numtslots != 0 || ch->numdslots != 0); 712 713 /* New item in response queue. */ 714 if ((arg->cause & 2) && edma) 715 mvs_crbq_intr(dev); 716 /* Some error or special event. */ 717 if (arg->cause & 1) { 718 iec = ATA_INL(ch->r_mem, EDMA_IEC); 719 if (iec & EDMA_IE_SERRINT) { 720 serr = ATA_INL(ch->r_mem, SATA_SE); 721 ATA_OUTL(ch->r_mem, SATA_SE, serr); 722 } 723 /* EDMA self-disabled due to error. */ 724 if (iec & EDMA_IE_ESELFDIS) 725 selfdis = 1; 726 /* Transport interrupt. */ 727 if (iec & EDMA_IE_ETRANSINT) { 728 /* For Gen-I this bit means self-disable. */ 729 if (ch->quirks & MVS_Q_GENI) 730 selfdis = 1; 731 /* For Gen-II this bit means SDB-N. */ 732 else if (ch->quirks & MVS_Q_GENII) 733 fisic = SATA_FISC_FISWAIT4HOSTRDYEN_B1; 734 else /* For Gen-IIe - read FIS interrupt cause. */ 735 fisic = ATA_INL(ch->r_mem, SATA_FISIC); 736 } 737 if (selfdis) 738 ch->curr_mode = MVS_EDMA_UNKNOWN; 739 ATA_OUTL(ch->r_mem, EDMA_IEC, ~iec); 740 /* Interface errors or Device error. */ 741 if (iec & (0xfc1e9000 | EDMA_IE_EDEVERR)) { 742 port = -1; 743 if (ch->numpslots != 0) { 744 ccs = 0; 745 } else { 746 if (ch->quirks & MVS_Q_GENIIE) 747 ccs = EDMA_S_EIOID(ATA_INL(ch->r_mem, EDMA_S)); 748 else 749 ccs = EDMA_S_EDEVQUETAG(ATA_INL(ch->r_mem, EDMA_S)); 750 /* Check if error is one-PMP-port-specific, */ 751 if (ch->fbs_enabled) { 752 /* Which ports were active. */ 753 for (i = 0; i < 16; i++) { 754 if (ch->numrslotspd[i] == 0) 755 continue; 756 if (port == -1) 757 port = i; 758 else if (port != i) { 759 port = -2; 760 break; 761 } 762 } 763 /* If several ports were active and EDMA still enabled - 764 * other ports are probably unaffected and may continue. 765 */ 766 if (port == -2 && !selfdis) { 767 uint16_t p = ATA_INL(ch->r_mem, SATA_SATAITC) >> 16; 768 port = ffs(p) - 1; 769 if (port != (fls(p) - 1)) 770 port = -2; 771 } 772 } 773 } 774 mvs_requeue_frozen(dev); 775 for (i = 0; i < MVS_MAX_SLOTS; i++) { 776 /* XXX: reqests in loading state. */ 777 if (((ch->rslots >> i) & 1) == 0) 778 continue; 779 if (port >= 0 && 780 ch->slot[i].ccb->ccb_h.target_id != port) 781 continue; 782 if (iec & EDMA_IE_EDEVERR) { /* Device error. */ 783 if (port != -2) { 784 if (ch->numtslots == 0) { 785 /* Untagged operation. */ 786 if (i == ccs) 787 et = MVS_ERR_TFE; 788 else 789 et = MVS_ERR_INNOCENT; 790 } else { 791 /* Tagged operation. */ 792 et = MVS_ERR_NCQ; 793 } 794 } else { 795 et = MVS_ERR_TFE; 796 ch->fatalerr = 1; 797 } 798 } else if (iec & 0xfc1e9000) { 799 if (ch->numtslots == 0 && 800 i != ccs && port != -2) 801 et = MVS_ERR_INNOCENT; 802 else 803 et = MVS_ERR_SATA; 804 } else 805 et = MVS_ERR_INVALID; 806 mvs_end_transaction(&ch->slot[i], et); 807 } 808 } 809 /* Process SDB-N. */ 810 if (fisic & SATA_FISC_FISWAIT4HOSTRDYEN_B1) 811 mvs_notify_events(dev); 812 if (fisic) 813 ATA_OUTL(ch->r_mem, SATA_FISIC, ~fisic); 814 /* Process hot-plug. */ 815 if ((iec & (EDMA_IE_EDEVDIS | EDMA_IE_EDEVCON)) || 816 (serr & SATA_SE_PHY_CHANGED)) 817 mvs_phy_check_events(dev, serr); 818 } 819 /* Legacy mode device interrupt. */ 820 if ((arg->cause & 2) && !edma) 821 mvs_legacy_intr(dev, arg->cause & 4); 822 } 823 824 static uint8_t 825 mvs_getstatus(device_t dev, int clear) 826 { 827 struct mvs_channel *ch = device_get_softc(dev); 828 uint8_t status = ATA_INB(ch->r_mem, clear ? ATA_STATUS : ATA_ALTSTAT); 829 830 if (ch->fake_busy) { 831 if (status & (ATA_S_BUSY | ATA_S_DRQ | ATA_S_ERROR)) 832 ch->fake_busy = 0; 833 else 834 status |= ATA_S_BUSY; 835 } 836 return (status); 837 } 838 839 static void 840 mvs_legacy_intr(device_t dev, int poll) 841 { 842 struct mvs_channel *ch = device_get_softc(dev); 843 struct mvs_slot *slot = &ch->slot[0]; /* PIO is always in slot 0. */ 844 union ccb *ccb = slot->ccb; 845 enum mvs_err_type et = MVS_ERR_NONE; 846 int port; 847 u_int length, resid, size; 848 uint8_t buf[2]; 849 uint8_t status, ireason; 850 851 /* Clear interrupt and get status. */ 852 status = mvs_getstatus(dev, 1); 853 if (slot->state < MVS_SLOT_RUNNING) 854 return; 855 port = ccb->ccb_h.target_id & 0x0f; 856 /* Wait a bit for late !BUSY status update. */ 857 if (status & ATA_S_BUSY) { 858 if (poll) 859 return; 860 DELAY(100); 861 if ((status = mvs_getstatus(dev, 1)) & ATA_S_BUSY) { 862 DELAY(1000); 863 if ((status = mvs_getstatus(dev, 1)) & ATA_S_BUSY) 864 return; 865 } 866 } 867 /* If we got an error, we are done. */ 868 if (status & ATA_S_ERROR) { 869 et = MVS_ERR_TFE; 870 goto end_finished; 871 } 872 if (ccb->ccb_h.func_code == XPT_ATA_IO) { /* ATA PIO */ 873 ccb->ataio.res.status = status; 874 /* Are we moving data? */ 875 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 876 /* If data read command - get them. */ 877 if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 878 if (mvs_wait(dev, ATA_S_DRQ, ATA_S_BUSY, 1000) < 0) { 879 device_printf(dev, "timeout waiting for read DRQ\n"); 880 et = MVS_ERR_TIMEOUT; 881 xpt_freeze_simq(ch->sim, 1); 882 ch->toslots |= (1 << slot->slot); 883 goto end_finished; 884 } 885 ATA_INSW_STRM(ch->r_mem, ATA_DATA, 886 (uint16_t *)(ccb->ataio.data_ptr + ch->donecount), 887 ch->transfersize / 2); 888 } 889 /* Update how far we've gotten. */ 890 ch->donecount += ch->transfersize; 891 /* Do we need more? */ 892 if (ccb->ataio.dxfer_len > ch->donecount) { 893 /* Set this transfer size according to HW capabilities */ 894 ch->transfersize = min(ccb->ataio.dxfer_len - ch->donecount, 895 ch->curr[ccb->ccb_h.target_id].bytecount); 896 /* If data write command - put them */ 897 if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_OUT) { 898 if (mvs_wait(dev, ATA_S_DRQ, ATA_S_BUSY, 1000) < 0) { 899 device_printf(dev, 900 "timeout waiting for write DRQ\n"); 901 et = MVS_ERR_TIMEOUT; 902 xpt_freeze_simq(ch->sim, 1); 903 ch->toslots |= (1 << slot->slot); 904 goto end_finished; 905 } 906 ATA_OUTSW_STRM(ch->r_mem, ATA_DATA, 907 (uint16_t *)(ccb->ataio.data_ptr + ch->donecount), 908 ch->transfersize / 2); 909 return; 910 } 911 /* If data read command, return & wait for interrupt */ 912 if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) 913 return; 914 } 915 } 916 } else if (ch->basic_dma) { /* ATAPI DMA */ 917 if (status & ATA_S_DWF) 918 et = MVS_ERR_TFE; 919 else if (ATA_INL(ch->r_mem, DMA_S) & DMA_S_ERR) 920 et = MVS_ERR_TFE; 921 /* Stop basic DMA. */ 922 ATA_OUTL(ch->r_mem, DMA_C, 0); 923 goto end_finished; 924 } else { /* ATAPI PIO */ 925 length = ATA_INB(ch->r_mem,ATA_CYL_LSB) | 926 (ATA_INB(ch->r_mem,ATA_CYL_MSB) << 8); 927 size = min(ch->transfersize, length); 928 ireason = ATA_INB(ch->r_mem,ATA_IREASON); 929 switch ((ireason & (ATA_I_CMD | ATA_I_IN)) | 930 (status & ATA_S_DRQ)) { 931 932 case ATAPI_P_CMDOUT: 933 device_printf(dev, "ATAPI CMDOUT\n"); 934 /* Return wait for interrupt */ 935 return; 936 937 case ATAPI_P_WRITE: 938 if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 939 device_printf(dev, "trying to write on read buffer\n"); 940 et = MVS_ERR_TFE; 941 goto end_finished; 942 break; 943 } 944 ATA_OUTSW_STRM(ch->r_mem, ATA_DATA, 945 (uint16_t *)(ccb->csio.data_ptr + ch->donecount), 946 (size + 1) / 2); 947 for (resid = ch->transfersize + (size & 1); 948 resid < length; resid += sizeof(int16_t)) 949 ATA_OUTW(ch->r_mem, ATA_DATA, 0); 950 ch->donecount += length; 951 /* Set next transfer size according to HW capabilities */ 952 ch->transfersize = min(ccb->csio.dxfer_len - ch->donecount, 953 ch->curr[ccb->ccb_h.target_id].bytecount); 954 /* Return wait for interrupt */ 955 return; 956 957 case ATAPI_P_READ: 958 if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_OUT) { 959 device_printf(dev, "trying to read on write buffer\n"); 960 et = MVS_ERR_TFE; 961 goto end_finished; 962 } 963 if (size >= 2) { 964 ATA_INSW_STRM(ch->r_mem, ATA_DATA, 965 (uint16_t *)(ccb->csio.data_ptr + ch->donecount), 966 size / 2); 967 } 968 if (size & 1) { 969 ATA_INSW_STRM(ch->r_mem, ATA_DATA, (void*)buf, 1); 970 ((uint8_t *)ccb->csio.data_ptr + ch->donecount + 971 (size & ~1))[0] = buf[0]; 972 } 973 for (resid = ch->transfersize + (size & 1); 974 resid < length; resid += sizeof(int16_t)) 975 ATA_INW(ch->r_mem, ATA_DATA); 976 ch->donecount += length; 977 /* Set next transfer size according to HW capabilities */ 978 ch->transfersize = min(ccb->csio.dxfer_len - ch->donecount, 979 ch->curr[ccb->ccb_h.target_id].bytecount); 980 /* Return wait for interrupt */ 981 return; 982 983 case ATAPI_P_DONEDRQ: 984 device_printf(dev, 985 "WARNING - DONEDRQ non conformant device\n"); 986 if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 987 ATA_INSW_STRM(ch->r_mem, ATA_DATA, 988 (uint16_t *)(ccb->csio.data_ptr + ch->donecount), 989 length / 2); 990 ch->donecount += length; 991 } 992 else if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_OUT) { 993 ATA_OUTSW_STRM(ch->r_mem, ATA_DATA, 994 (uint16_t *)(ccb->csio.data_ptr + ch->donecount), 995 length / 2); 996 ch->donecount += length; 997 } 998 else 999 et = MVS_ERR_TFE; 1000 /* FALLTHROUGH */ 1001 1002 case ATAPI_P_ABORT: 1003 case ATAPI_P_DONE: 1004 if (status & (ATA_S_ERROR | ATA_S_DWF)) 1005 et = MVS_ERR_TFE; 1006 goto end_finished; 1007 1008 default: 1009 device_printf(dev, "unknown transfer phase" 1010 " (status %02x, ireason %02x)\n", 1011 status, ireason); 1012 et = MVS_ERR_TFE; 1013 } 1014 } 1015 1016 end_finished: 1017 mvs_end_transaction(slot, et); 1018 } 1019 1020 static void 1021 mvs_crbq_intr(device_t dev) 1022 { 1023 struct mvs_channel *ch = device_get_softc(dev); 1024 struct mvs_crpb *crpb; 1025 union ccb *ccb; 1026 int in_idx, fin_idx, cin_idx, slot; 1027 uint32_t val; 1028 uint16_t flags; 1029 1030 val = ATA_INL(ch->r_mem, EDMA_RESQIP); 1031 if (val == 0) 1032 val = ATA_INL(ch->r_mem, EDMA_RESQIP); 1033 in_idx = (val & EDMA_RESQP_ERPQP_MASK) >> 1034 EDMA_RESQP_ERPQP_SHIFT; 1035 bus_dmamap_sync(ch->dma.workrp_tag, ch->dma.workrp_map, 1036 BUS_DMASYNC_POSTREAD); 1037 fin_idx = cin_idx = ch->in_idx; 1038 ch->in_idx = in_idx; 1039 while (in_idx != cin_idx) { 1040 crpb = (struct mvs_crpb *) 1041 (ch->dma.workrp + MVS_CRPB_OFFSET + 1042 (MVS_CRPB_SIZE * cin_idx)); 1043 slot = le16toh(crpb->id) & MVS_CRPB_TAG_MASK; 1044 flags = le16toh(crpb->rspflg); 1045 /* 1046 * Handle only successfull completions here. 1047 * Errors will be handled by main intr handler. 1048 */ 1049 if (crpb->id == 0xffff && crpb->rspflg == 0xffff) { 1050 device_printf(dev, "Unfilled CRPB " 1051 "%d (%d->%d) tag %d flags %04x rs %08x\n", 1052 cin_idx, fin_idx, in_idx, slot, flags, ch->rslots); 1053 } else if (ch->numtslots != 0 || 1054 (flags & EDMA_IE_EDEVERR) == 0) { 1055 crpb->id = 0xffff; 1056 crpb->rspflg = 0xffff; 1057 if (ch->slot[slot].state >= MVS_SLOT_RUNNING) { 1058 ccb = ch->slot[slot].ccb; 1059 ccb->ataio.res.status = 1060 (flags & MVS_CRPB_ATASTS_MASK) >> 1061 MVS_CRPB_ATASTS_SHIFT; 1062 mvs_end_transaction(&ch->slot[slot], MVS_ERR_NONE); 1063 } else { 1064 device_printf(dev, "Unused tag in CRPB " 1065 "%d (%d->%d) tag %d flags %04x rs %08x\n", 1066 cin_idx, fin_idx, in_idx, slot, flags, 1067 ch->rslots); 1068 } 1069 } else { 1070 device_printf(dev, 1071 "CRPB with error %d tag %d flags %04x\n", 1072 cin_idx, slot, flags); 1073 } 1074 cin_idx = (cin_idx + 1) & (MVS_MAX_SLOTS - 1); 1075 } 1076 bus_dmamap_sync(ch->dma.workrp_tag, ch->dma.workrp_map, 1077 BUS_DMASYNC_PREREAD); 1078 if (cin_idx == ch->in_idx) { 1079 ATA_OUTL(ch->r_mem, EDMA_RESQOP, 1080 ch->dma.workrp_bus | (cin_idx << EDMA_RESQP_ERPQP_SHIFT)); 1081 } 1082 } 1083 1084 /* Must be called with channel locked. */ 1085 static int 1086 mvs_check_collision(device_t dev, union ccb *ccb) 1087 { 1088 struct mvs_channel *ch = device_get_softc(dev); 1089 1090 if (ccb->ccb_h.func_code == XPT_ATA_IO) { 1091 /* NCQ DMA */ 1092 if (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) { 1093 /* Can't mix NCQ and non-NCQ DMA commands. */ 1094 if (ch->numdslots != 0) 1095 return (1); 1096 /* Can't mix NCQ and PIO commands. */ 1097 if (ch->numpslots != 0) 1098 return (1); 1099 /* If we have no FBS */ 1100 if (!ch->fbs_enabled) { 1101 /* Tagged command while tagged to other target is active. */ 1102 if (ch->numtslots != 0 && 1103 ch->taggedtarget != ccb->ccb_h.target_id) 1104 return (1); 1105 } 1106 /* Non-NCQ DMA */ 1107 } else if (ccb->ataio.cmd.flags & CAM_ATAIO_DMA) { 1108 /* Can't mix non-NCQ DMA and NCQ commands. */ 1109 if (ch->numtslots != 0) 1110 return (1); 1111 /* Can't mix non-NCQ DMA and PIO commands. */ 1112 if (ch->numpslots != 0) 1113 return (1); 1114 /* PIO */ 1115 } else { 1116 /* Can't mix PIO with anything. */ 1117 if (ch->numrslots != 0) 1118 return (1); 1119 } 1120 if (ccb->ataio.cmd.flags & (CAM_ATAIO_CONTROL | CAM_ATAIO_NEEDRESULT)) { 1121 /* Atomic command while anything active. */ 1122 if (ch->numrslots != 0) 1123 return (1); 1124 } 1125 } else { /* ATAPI */ 1126 /* ATAPI goes without EDMA, so can't mix it with anything. */ 1127 if (ch->numrslots != 0) 1128 return (1); 1129 } 1130 /* We have some atomic command running. */ 1131 if (ch->aslots != 0) 1132 return (1); 1133 return (0); 1134 } 1135 1136 static void 1137 mvs_tfd_read(device_t dev, union ccb *ccb) 1138 { 1139 struct mvs_channel *ch = device_get_softc(dev); 1140 struct ata_res *res = &ccb->ataio.res; 1141 1142 res->status = ATA_INB(ch->r_mem, ATA_ALTSTAT); 1143 res->error = ATA_INB(ch->r_mem, ATA_ERROR); 1144 res->device = ATA_INB(ch->r_mem, ATA_DRIVE); 1145 ATA_OUTB(ch->r_mem, ATA_CONTROL, ATA_A_HOB); 1146 res->sector_count_exp = ATA_INB(ch->r_mem, ATA_COUNT); 1147 res->lba_low_exp = ATA_INB(ch->r_mem, ATA_SECTOR); 1148 res->lba_mid_exp = ATA_INB(ch->r_mem, ATA_CYL_LSB); 1149 res->lba_high_exp = ATA_INB(ch->r_mem, ATA_CYL_MSB); 1150 ATA_OUTB(ch->r_mem, ATA_CONTROL, 0); 1151 res->sector_count = ATA_INB(ch->r_mem, ATA_COUNT); 1152 res->lba_low = ATA_INB(ch->r_mem, ATA_SECTOR); 1153 res->lba_mid = ATA_INB(ch->r_mem, ATA_CYL_LSB); 1154 res->lba_high = ATA_INB(ch->r_mem, ATA_CYL_MSB); 1155 } 1156 1157 static void 1158 mvs_tfd_write(device_t dev, union ccb *ccb) 1159 { 1160 struct mvs_channel *ch = device_get_softc(dev); 1161 struct ata_cmd *cmd = &ccb->ataio.cmd; 1162 1163 ATA_OUTB(ch->r_mem, ATA_DRIVE, cmd->device); 1164 ATA_OUTB(ch->r_mem, ATA_CONTROL, cmd->control); 1165 ATA_OUTB(ch->r_mem, ATA_FEATURE, cmd->features_exp); 1166 ATA_OUTB(ch->r_mem, ATA_FEATURE, cmd->features); 1167 ATA_OUTB(ch->r_mem, ATA_COUNT, cmd->sector_count_exp); 1168 ATA_OUTB(ch->r_mem, ATA_COUNT, cmd->sector_count); 1169 ATA_OUTB(ch->r_mem, ATA_SECTOR, cmd->lba_low_exp); 1170 ATA_OUTB(ch->r_mem, ATA_SECTOR, cmd->lba_low); 1171 ATA_OUTB(ch->r_mem, ATA_CYL_LSB, cmd->lba_mid_exp); 1172 ATA_OUTB(ch->r_mem, ATA_CYL_LSB, cmd->lba_mid); 1173 ATA_OUTB(ch->r_mem, ATA_CYL_MSB, cmd->lba_high_exp); 1174 ATA_OUTB(ch->r_mem, ATA_CYL_MSB, cmd->lba_high); 1175 ATA_OUTB(ch->r_mem, ATA_COMMAND, cmd->command); 1176 } 1177 1178 1179 /* Must be called with channel locked. */ 1180 static void 1181 mvs_begin_transaction(device_t dev, union ccb *ccb) 1182 { 1183 struct mvs_channel *ch = device_get_softc(dev); 1184 struct mvs_slot *slot; 1185 int slotn, tag; 1186 1187 if (ch->pm_level > 0) 1188 mvs_ch_pm_wake(dev); 1189 /* Softreset is a special case. */ 1190 if (ccb->ccb_h.func_code == XPT_ATA_IO && 1191 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL)) { 1192 mvs_softreset(dev, ccb); 1193 return; 1194 } 1195 /* Choose empty slot. */ 1196 slotn = ffs(~ch->oslots) - 1; 1197 if ((ccb->ccb_h.func_code == XPT_ATA_IO) && 1198 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) { 1199 if (ch->quirks & MVS_Q_GENIIE) 1200 tag = ffs(~ch->otagspd[ccb->ccb_h.target_id]) - 1; 1201 else 1202 tag = slotn; 1203 } else 1204 tag = 0; 1205 /* Occupy chosen slot. */ 1206 slot = &ch->slot[slotn]; 1207 slot->ccb = ccb; 1208 slot->tag = tag; 1209 /* Stop PM timer. */ 1210 if (ch->numrslots == 0 && ch->pm_level > 3) 1211 callout_stop(&ch->pm_timer); 1212 /* Update channel stats. */ 1213 ch->oslots |= (1 << slot->slot); 1214 ch->numrslots++; 1215 ch->numrslotspd[ccb->ccb_h.target_id]++; 1216 if (ccb->ccb_h.func_code == XPT_ATA_IO) { 1217 if (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) { 1218 ch->otagspd[ccb->ccb_h.target_id] |= (1 << slot->tag); 1219 ch->numtslots++; 1220 ch->numtslotspd[ccb->ccb_h.target_id]++; 1221 ch->taggedtarget = ccb->ccb_h.target_id; 1222 mvs_set_edma_mode(dev, MVS_EDMA_NCQ); 1223 } else if (ccb->ataio.cmd.flags & CAM_ATAIO_DMA) { 1224 ch->numdslots++; 1225 mvs_set_edma_mode(dev, MVS_EDMA_ON); 1226 } else { 1227 ch->numpslots++; 1228 mvs_set_edma_mode(dev, MVS_EDMA_OFF); 1229 } 1230 if (ccb->ataio.cmd.flags & 1231 (CAM_ATAIO_CONTROL | CAM_ATAIO_NEEDRESULT)) { 1232 ch->aslots |= (1 << slot->slot); 1233 } 1234 } else { 1235 uint8_t *cdb = (ccb->ccb_h.flags & CAM_CDB_POINTER) ? 1236 ccb->csio.cdb_io.cdb_ptr : ccb->csio.cdb_io.cdb_bytes; 1237 ch->numpslots++; 1238 /* Use ATAPI DMA only for commands without under-/overruns. */ 1239 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE && 1240 ch->curr[ccb->ccb_h.target_id].mode >= ATA_DMA && 1241 (ch->quirks & MVS_Q_SOC) == 0 && 1242 (cdb[0] == 0x08 || 1243 cdb[0] == 0x0a || 1244 cdb[0] == 0x28 || 1245 cdb[0] == 0x2a || 1246 cdb[0] == 0x88 || 1247 cdb[0] == 0x8a || 1248 cdb[0] == 0xa8 || 1249 cdb[0] == 0xaa || 1250 cdb[0] == 0xbe)) { 1251 ch->basic_dma = 1; 1252 } 1253 mvs_set_edma_mode(dev, MVS_EDMA_OFF); 1254 } 1255 if (ch->numpslots == 0 || ch->basic_dma) { 1256 void *buf; 1257 bus_size_t size; 1258 1259 slot->state = MVS_SLOT_LOADING; 1260 if (ccb->ccb_h.func_code == XPT_ATA_IO) { 1261 buf = ccb->ataio.data_ptr; 1262 size = ccb->ataio.dxfer_len; 1263 } else { 1264 buf = ccb->csio.data_ptr; 1265 size = ccb->csio.dxfer_len; 1266 } 1267 bus_dmamap_load(ch->dma.data_tag, slot->dma.data_map, 1268 buf, size, mvs_dmasetprd, slot, 0); 1269 } else 1270 mvs_legacy_execute_transaction(slot); 1271 } 1272 1273 /* Locked by busdma engine. */ 1274 static void 1275 mvs_dmasetprd(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1276 { 1277 struct mvs_slot *slot = arg; 1278 struct mvs_channel *ch = device_get_softc(slot->dev); 1279 struct mvs_eprd *eprd; 1280 int i; 1281 1282 if (error) { 1283 device_printf(slot->dev, "DMA load error\n"); 1284 mvs_end_transaction(slot, MVS_ERR_INVALID); 1285 return; 1286 } 1287 KASSERT(nsegs <= MVS_SG_ENTRIES, ("too many DMA segment entries\n")); 1288 /* If there is only one segment - no need to use S/G table on Gen-IIe. */ 1289 if (nsegs == 1 && ch->basic_dma == 0 && (ch->quirks & MVS_Q_GENIIE)) { 1290 slot->dma.addr = segs[0].ds_addr; 1291 slot->dma.len = segs[0].ds_len; 1292 } else { 1293 slot->dma.addr = 0; 1294 /* Get a piece of the workspace for this EPRD */ 1295 eprd = (struct mvs_eprd *) 1296 (ch->dma.workrq + MVS_EPRD_OFFSET + (MVS_EPRD_SIZE * slot->slot)); 1297 /* Fill S/G table */ 1298 for (i = 0; i < nsegs; i++) { 1299 eprd[i].prdbal = htole32(segs[i].ds_addr); 1300 eprd[i].bytecount = htole32(segs[i].ds_len & MVS_EPRD_MASK); 1301 eprd[i].prdbah = htole32((segs[i].ds_addr >> 16) >> 16); 1302 } 1303 eprd[i - 1].bytecount |= htole32(MVS_EPRD_EOF); 1304 } 1305 bus_dmamap_sync(ch->dma.data_tag, slot->dma.data_map, 1306 ((slot->ccb->ccb_h.flags & CAM_DIR_IN) ? 1307 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE)); 1308 if (ch->basic_dma) 1309 mvs_legacy_execute_transaction(slot); 1310 else 1311 mvs_execute_transaction(slot); 1312 } 1313 1314 static void 1315 mvs_legacy_execute_transaction(struct mvs_slot *slot) 1316 { 1317 device_t dev = slot->dev; 1318 struct mvs_channel *ch = device_get_softc(dev); 1319 bus_addr_t eprd; 1320 union ccb *ccb = slot->ccb; 1321 int port = ccb->ccb_h.target_id & 0x0f; 1322 int timeout; 1323 1324 slot->state = MVS_SLOT_RUNNING; 1325 ch->rslots |= (1 << slot->slot); 1326 ATA_OUTB(ch->r_mem, SATA_SATAICTL, port << SATA_SATAICTL_PMPTX_SHIFT); 1327 if (ccb->ccb_h.func_code == XPT_ATA_IO) { 1328 mvs_tfd_write(dev, ccb); 1329 /* Device reset doesn't interrupt. */ 1330 if (ccb->ataio.cmd.command == ATA_DEVICE_RESET) { 1331 int timeout = 1000000; 1332 do { 1333 DELAY(10); 1334 ccb->ataio.res.status = ATA_INB(ch->r_mem, ATA_STATUS); 1335 } while (ccb->ataio.res.status & ATA_S_BUSY && timeout--); 1336 mvs_legacy_intr(dev, 1); 1337 return; 1338 } 1339 ch->donecount = 0; 1340 ch->transfersize = min(ccb->ataio.dxfer_len, 1341 ch->curr[port].bytecount); 1342 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) 1343 ch->fake_busy = 1; 1344 /* If data write command - output the data */ 1345 if ((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_OUT) { 1346 if (mvs_wait(dev, ATA_S_DRQ, ATA_S_BUSY, 1000) < 0) { 1347 device_printf(dev, 1348 "timeout waiting for write DRQ\n"); 1349 xpt_freeze_simq(ch->sim, 1); 1350 ch->toslots |= (1 << slot->slot); 1351 mvs_end_transaction(slot, MVS_ERR_TIMEOUT); 1352 return; 1353 } 1354 ATA_OUTSW_STRM(ch->r_mem, ATA_DATA, 1355 (uint16_t *)(ccb->ataio.data_ptr + ch->donecount), 1356 ch->transfersize / 2); 1357 } 1358 } else { 1359 ch->donecount = 0; 1360 ch->transfersize = min(ccb->csio.dxfer_len, 1361 ch->curr[port].bytecount); 1362 /* Write ATA PACKET command. */ 1363 if (ch->basic_dma) { 1364 ATA_OUTB(ch->r_mem, ATA_FEATURE, ATA_F_DMA); 1365 ATA_OUTB(ch->r_mem, ATA_CYL_LSB, 0); 1366 ATA_OUTB(ch->r_mem, ATA_CYL_MSB, 0); 1367 } else { 1368 ATA_OUTB(ch->r_mem, ATA_FEATURE, 0); 1369 ATA_OUTB(ch->r_mem, ATA_CYL_LSB, ch->transfersize); 1370 ATA_OUTB(ch->r_mem, ATA_CYL_MSB, ch->transfersize >> 8); 1371 } 1372 ATA_OUTB(ch->r_mem, ATA_COMMAND, ATA_PACKET_CMD); 1373 ch->fake_busy = 1; 1374 /* Wait for ready to write ATAPI command block */ 1375 if (mvs_wait(dev, 0, ATA_S_BUSY, 1000) < 0) { 1376 device_printf(dev, "timeout waiting for ATAPI !BUSY\n"); 1377 xpt_freeze_simq(ch->sim, 1); 1378 ch->toslots |= (1 << slot->slot); 1379 mvs_end_transaction(slot, MVS_ERR_TIMEOUT); 1380 return; 1381 } 1382 timeout = 5000; 1383 while (timeout--) { 1384 int reason = ATA_INB(ch->r_mem, ATA_IREASON); 1385 int status = ATA_INB(ch->r_mem, ATA_STATUS); 1386 1387 if (((reason & (ATA_I_CMD | ATA_I_IN)) | 1388 (status & (ATA_S_DRQ | ATA_S_BUSY))) == ATAPI_P_CMDOUT) 1389 break; 1390 DELAY(20); 1391 } 1392 if (timeout <= 0) { 1393 device_printf(dev, 1394 "timeout waiting for ATAPI command ready\n"); 1395 xpt_freeze_simq(ch->sim, 1); 1396 ch->toslots |= (1 << slot->slot); 1397 mvs_end_transaction(slot, MVS_ERR_TIMEOUT); 1398 return; 1399 } 1400 /* Write ATAPI command. */ 1401 ATA_OUTSW_STRM(ch->r_mem, ATA_DATA, 1402 (uint16_t *)((ccb->ccb_h.flags & CAM_CDB_POINTER) ? 1403 ccb->csio.cdb_io.cdb_ptr : ccb->csio.cdb_io.cdb_bytes), 1404 ch->curr[port].atapi / 2); 1405 DELAY(10); 1406 if (ch->basic_dma) { 1407 /* Start basic DMA. */ 1408 eprd = ch->dma.workrq_bus + MVS_EPRD_OFFSET + 1409 (MVS_EPRD_SIZE * slot->slot); 1410 ATA_OUTL(ch->r_mem, DMA_DTLBA, eprd); 1411 ATA_OUTL(ch->r_mem, DMA_DTHBA, (eprd >> 16) >> 16); 1412 ATA_OUTL(ch->r_mem, DMA_C, DMA_C_START | 1413 (((ccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) ? 1414 DMA_C_READ : 0)); 1415 } 1416 } 1417 /* Start command execution timeout */ 1418 callout_reset(&slot->timeout, (int)ccb->ccb_h.timeout * hz / 1000, 1419 (timeout_t*)mvs_timeout, slot); 1420 } 1421 1422 /* Must be called with channel locked. */ 1423 static void 1424 mvs_execute_transaction(struct mvs_slot *slot) 1425 { 1426 device_t dev = slot->dev; 1427 struct mvs_channel *ch = device_get_softc(dev); 1428 bus_addr_t eprd; 1429 struct mvs_crqb *crqb; 1430 struct mvs_crqb_gen2e *crqb2e; 1431 union ccb *ccb = slot->ccb; 1432 int port = ccb->ccb_h.target_id & 0x0f; 1433 int i; 1434 1435 /* Get address of the prepared EPRD */ 1436 eprd = ch->dma.workrq_bus + MVS_EPRD_OFFSET + (MVS_EPRD_SIZE * slot->slot); 1437 /* Prepare CRQB. Gen IIe uses different CRQB format. */ 1438 if (ch->quirks & MVS_Q_GENIIE) { 1439 crqb2e = (struct mvs_crqb_gen2e *) 1440 (ch->dma.workrq + MVS_CRQB_OFFSET + (MVS_CRQB_SIZE * ch->out_idx)); 1441 crqb2e->ctrlflg = htole32( 1442 ((ccb->ccb_h.flags & CAM_DIR_IN) ? MVS_CRQB2E_READ : 0) | 1443 (slot->tag << MVS_CRQB2E_DTAG_SHIFT) | 1444 (port << MVS_CRQB2E_PMP_SHIFT) | 1445 (slot->slot << MVS_CRQB2E_HTAG_SHIFT)); 1446 /* If there is only one segment - no need to use S/G table. */ 1447 if (slot->dma.addr != 0) { 1448 eprd = slot->dma.addr; 1449 crqb2e->ctrlflg |= htole32(MVS_CRQB2E_CPRD); 1450 crqb2e->drbc = slot->dma.len; 1451 } 1452 crqb2e->cprdbl = htole32(eprd); 1453 crqb2e->cprdbh = htole32((eprd >> 16) >> 16); 1454 crqb2e->cmd[0] = 0; 1455 crqb2e->cmd[1] = 0; 1456 crqb2e->cmd[2] = ccb->ataio.cmd.command; 1457 crqb2e->cmd[3] = ccb->ataio.cmd.features; 1458 crqb2e->cmd[4] = ccb->ataio.cmd.lba_low; 1459 crqb2e->cmd[5] = ccb->ataio.cmd.lba_mid; 1460 crqb2e->cmd[6] = ccb->ataio.cmd.lba_high; 1461 crqb2e->cmd[7] = ccb->ataio.cmd.device; 1462 crqb2e->cmd[8] = ccb->ataio.cmd.lba_low_exp; 1463 crqb2e->cmd[9] = ccb->ataio.cmd.lba_mid_exp; 1464 crqb2e->cmd[10] = ccb->ataio.cmd.lba_high_exp; 1465 crqb2e->cmd[11] = ccb->ataio.cmd.features_exp; 1466 if (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) { 1467 crqb2e->cmd[12] = slot->tag << 3; 1468 crqb2e->cmd[13] = 0; 1469 } else { 1470 crqb2e->cmd[12] = ccb->ataio.cmd.sector_count; 1471 crqb2e->cmd[13] = ccb->ataio.cmd.sector_count_exp; 1472 } 1473 crqb2e->cmd[14] = 0; 1474 crqb2e->cmd[15] = 0; 1475 } else { 1476 crqb = (struct mvs_crqb *) 1477 (ch->dma.workrq + MVS_CRQB_OFFSET + (MVS_CRQB_SIZE * ch->out_idx)); 1478 crqb->cprdbl = htole32(eprd); 1479 crqb->cprdbh = htole32((eprd >> 16) >> 16); 1480 crqb->ctrlflg = htole16( 1481 ((ccb->ccb_h.flags & CAM_DIR_IN) ? MVS_CRQB_READ : 0) | 1482 (slot->slot << MVS_CRQB_TAG_SHIFT) | 1483 (port << MVS_CRQB_PMP_SHIFT)); 1484 i = 0; 1485 /* 1486 * Controller can handle only 11 of 12 ATA registers, 1487 * so we have to choose which one to skip. 1488 */ 1489 if (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) { 1490 crqb->cmd[i++] = ccb->ataio.cmd.features_exp; 1491 crqb->cmd[i++] = 0x11; 1492 } 1493 crqb->cmd[i++] = ccb->ataio.cmd.features; 1494 crqb->cmd[i++] = 0x11; 1495 if (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) { 1496 crqb->cmd[i++] = slot->tag << 3; 1497 crqb->cmd[i++] = 0x12; 1498 } else { 1499 crqb->cmd[i++] = ccb->ataio.cmd.sector_count_exp; 1500 crqb->cmd[i++] = 0x12; 1501 crqb->cmd[i++] = ccb->ataio.cmd.sector_count; 1502 crqb->cmd[i++] = 0x12; 1503 } 1504 crqb->cmd[i++] = ccb->ataio.cmd.lba_low_exp; 1505 crqb->cmd[i++] = 0x13; 1506 crqb->cmd[i++] = ccb->ataio.cmd.lba_low; 1507 crqb->cmd[i++] = 0x13; 1508 crqb->cmd[i++] = ccb->ataio.cmd.lba_mid_exp; 1509 crqb->cmd[i++] = 0x14; 1510 crqb->cmd[i++] = ccb->ataio.cmd.lba_mid; 1511 crqb->cmd[i++] = 0x14; 1512 crqb->cmd[i++] = ccb->ataio.cmd.lba_high_exp; 1513 crqb->cmd[i++] = 0x15; 1514 crqb->cmd[i++] = ccb->ataio.cmd.lba_high; 1515 crqb->cmd[i++] = 0x15; 1516 crqb->cmd[i++] = ccb->ataio.cmd.device; 1517 crqb->cmd[i++] = 0x16; 1518 crqb->cmd[i++] = ccb->ataio.cmd.command; 1519 crqb->cmd[i++] = 0x97; 1520 } 1521 bus_dmamap_sync(ch->dma.workrq_tag, ch->dma.workrq_map, 1522 BUS_DMASYNC_PREWRITE); 1523 bus_dmamap_sync(ch->dma.workrp_tag, ch->dma.workrp_map, 1524 BUS_DMASYNC_PREREAD); 1525 slot->state = MVS_SLOT_RUNNING; 1526 ch->rslots |= (1 << slot->slot); 1527 /* Issue command to the controller. */ 1528 ch->out_idx = (ch->out_idx + 1) & (MVS_MAX_SLOTS - 1); 1529 ATA_OUTL(ch->r_mem, EDMA_REQQIP, 1530 ch->dma.workrq_bus + MVS_CRQB_OFFSET + (MVS_CRQB_SIZE * ch->out_idx)); 1531 /* Start command execution timeout */ 1532 callout_reset(&slot->timeout, (int)ccb->ccb_h.timeout * hz / 1000, 1533 (timeout_t*)mvs_timeout, slot); 1534 return; 1535 } 1536 1537 /* Must be called with channel locked. */ 1538 static void 1539 mvs_process_timeout(device_t dev) 1540 { 1541 struct mvs_channel *ch = device_get_softc(dev); 1542 int i; 1543 1544 mtx_assert(&ch->mtx, MA_OWNED); 1545 /* Handle the rest of commands. */ 1546 for (i = 0; i < MVS_MAX_SLOTS; i++) { 1547 /* Do we have a running request on slot? */ 1548 if (ch->slot[i].state < MVS_SLOT_RUNNING) 1549 continue; 1550 mvs_end_transaction(&ch->slot[i], MVS_ERR_TIMEOUT); 1551 } 1552 } 1553 1554 /* Must be called with channel locked. */ 1555 static void 1556 mvs_rearm_timeout(device_t dev) 1557 { 1558 struct mvs_channel *ch = device_get_softc(dev); 1559 int i; 1560 1561 mtx_assert(&ch->mtx, MA_OWNED); 1562 for (i = 0; i < MVS_MAX_SLOTS; i++) { 1563 struct mvs_slot *slot = &ch->slot[i]; 1564 1565 /* Do we have a running request on slot? */ 1566 if (slot->state < MVS_SLOT_RUNNING) 1567 continue; 1568 if ((ch->toslots & (1 << i)) == 0) 1569 continue; 1570 callout_reset(&slot->timeout, 1571 (int)slot->ccb->ccb_h.timeout * hz / 2000, 1572 (timeout_t*)mvs_timeout, slot); 1573 } 1574 } 1575 1576 /* Locked by callout mechanism. */ 1577 static void 1578 mvs_timeout(struct mvs_slot *slot) 1579 { 1580 device_t dev = slot->dev; 1581 struct mvs_channel *ch = device_get_softc(dev); 1582 1583 /* Check for stale timeout. */ 1584 if (slot->state < MVS_SLOT_RUNNING) 1585 return; 1586 device_printf(dev, "Timeout on slot %d\n", slot->slot); 1587 device_printf(dev, "iec %08x sstat %08x serr %08x edma_s %08x " 1588 "dma_c %08x dma_s %08x rs %08x status %02x\n", 1589 ATA_INL(ch->r_mem, EDMA_IEC), 1590 ATA_INL(ch->r_mem, SATA_SS), ATA_INL(ch->r_mem, SATA_SE), 1591 ATA_INL(ch->r_mem, EDMA_S), ATA_INL(ch->r_mem, DMA_C), 1592 ATA_INL(ch->r_mem, DMA_S), ch->rslots, 1593 ATA_INB(ch->r_mem, ATA_ALTSTAT)); 1594 /* Handle frozen command. */ 1595 mvs_requeue_frozen(dev); 1596 /* We wait for other commands timeout and pray. */ 1597 if (ch->toslots == 0) 1598 xpt_freeze_simq(ch->sim, 1); 1599 ch->toslots |= (1 << slot->slot); 1600 if ((ch->rslots & ~ch->toslots) == 0) 1601 mvs_process_timeout(dev); 1602 else 1603 device_printf(dev, " ... waiting for slots %08x\n", 1604 ch->rslots & ~ch->toslots); 1605 } 1606 1607 /* Must be called with channel locked. */ 1608 static void 1609 mvs_end_transaction(struct mvs_slot *slot, enum mvs_err_type et) 1610 { 1611 device_t dev = slot->dev; 1612 struct mvs_channel *ch = device_get_softc(dev); 1613 union ccb *ccb = slot->ccb; 1614 int lastto; 1615 1616 bus_dmamap_sync(ch->dma.workrq_tag, ch->dma.workrq_map, 1617 BUS_DMASYNC_POSTWRITE); 1618 /* Read result registers to the result struct 1619 * May be incorrect if several commands finished same time, 1620 * so read only when sure or have to. 1621 */ 1622 if (ccb->ccb_h.func_code == XPT_ATA_IO) { 1623 struct ata_res *res = &ccb->ataio.res; 1624 1625 if ((et == MVS_ERR_TFE) || 1626 (ccb->ataio.cmd.flags & CAM_ATAIO_NEEDRESULT)) { 1627 mvs_tfd_read(dev, ccb); 1628 } else 1629 bzero(res, sizeof(*res)); 1630 } else { 1631 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE && 1632 ch->basic_dma == 0) 1633 ccb->csio.resid = ccb->csio.dxfer_len - ch->donecount; 1634 } 1635 if (ch->numpslots == 0 || ch->basic_dma) { 1636 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 1637 bus_dmamap_sync(ch->dma.data_tag, slot->dma.data_map, 1638 (ccb->ccb_h.flags & CAM_DIR_IN) ? 1639 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 1640 bus_dmamap_unload(ch->dma.data_tag, slot->dma.data_map); 1641 } 1642 } 1643 if (et != MVS_ERR_NONE) 1644 ch->eslots |= (1 << slot->slot); 1645 /* In case of error, freeze device for proper recovery. */ 1646 if ((et != MVS_ERR_NONE) && (!ch->recoverycmd) && 1647 !(ccb->ccb_h.status & CAM_DEV_QFRZN)) { 1648 xpt_freeze_devq(ccb->ccb_h.path, 1); 1649 ccb->ccb_h.status |= CAM_DEV_QFRZN; 1650 } 1651 /* Set proper result status. */ 1652 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 1653 switch (et) { 1654 case MVS_ERR_NONE: 1655 ccb->ccb_h.status |= CAM_REQ_CMP; 1656 if (ccb->ccb_h.func_code == XPT_SCSI_IO) 1657 ccb->csio.scsi_status = SCSI_STATUS_OK; 1658 break; 1659 case MVS_ERR_INVALID: 1660 ch->fatalerr = 1; 1661 ccb->ccb_h.status |= CAM_REQ_INVALID; 1662 break; 1663 case MVS_ERR_INNOCENT: 1664 ccb->ccb_h.status |= CAM_REQUEUE_REQ; 1665 break; 1666 case MVS_ERR_TFE: 1667 case MVS_ERR_NCQ: 1668 if (ccb->ccb_h.func_code == XPT_SCSI_IO) { 1669 ccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR; 1670 ccb->csio.scsi_status = SCSI_STATUS_CHECK_COND; 1671 } else { 1672 ccb->ccb_h.status |= CAM_ATA_STATUS_ERROR; 1673 } 1674 break; 1675 case MVS_ERR_SATA: 1676 ch->fatalerr = 1; 1677 if (!ch->recoverycmd) { 1678 xpt_freeze_simq(ch->sim, 1); 1679 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 1680 ccb->ccb_h.status |= CAM_RELEASE_SIMQ; 1681 } 1682 ccb->ccb_h.status |= CAM_UNCOR_PARITY; 1683 break; 1684 case MVS_ERR_TIMEOUT: 1685 if (!ch->recoverycmd) { 1686 xpt_freeze_simq(ch->sim, 1); 1687 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 1688 ccb->ccb_h.status |= CAM_RELEASE_SIMQ; 1689 } 1690 ccb->ccb_h.status |= CAM_CMD_TIMEOUT; 1691 break; 1692 default: 1693 ch->fatalerr = 1; 1694 ccb->ccb_h.status |= CAM_REQ_CMP_ERR; 1695 } 1696 /* Free slot. */ 1697 ch->oslots &= ~(1 << slot->slot); 1698 ch->rslots &= ~(1 << slot->slot); 1699 ch->aslots &= ~(1 << slot->slot); 1700 slot->state = MVS_SLOT_EMPTY; 1701 slot->ccb = NULL; 1702 /* Update channel stats. */ 1703 ch->numrslots--; 1704 ch->numrslotspd[ccb->ccb_h.target_id]--; 1705 if (ccb->ccb_h.func_code == XPT_ATA_IO) { 1706 if (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) { 1707 ch->otagspd[ccb->ccb_h.target_id] &= ~(1 << slot->tag); 1708 ch->numtslots--; 1709 ch->numtslotspd[ccb->ccb_h.target_id]--; 1710 } else if (ccb->ataio.cmd.flags & CAM_ATAIO_DMA) { 1711 ch->numdslots--; 1712 } else { 1713 ch->numpslots--; 1714 } 1715 } else { 1716 ch->numpslots--; 1717 ch->basic_dma = 0; 1718 } 1719 /* Cancel timeout state if request completed normally. */ 1720 if (et != MVS_ERR_TIMEOUT) { 1721 lastto = (ch->toslots == (1 << slot->slot)); 1722 ch->toslots &= ~(1 << slot->slot); 1723 if (lastto) 1724 xpt_release_simq(ch->sim, TRUE); 1725 } 1726 /* If it was our READ LOG command - process it. */ 1727 if (ccb->ccb_h.recovery_type == RECOVERY_READ_LOG) { 1728 mvs_process_read_log(dev, ccb); 1729 /* If it was our REQUEST SENSE command - process it. */ 1730 } else if (ccb->ccb_h.recovery_type == RECOVERY_REQUEST_SENSE) { 1731 mvs_process_request_sense(dev, ccb); 1732 /* If it was NCQ or ATAPI command error, put result on hold. */ 1733 } else if (et == MVS_ERR_NCQ || 1734 ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_SCSI_STATUS_ERROR && 1735 (ccb->ccb_h.flags & CAM_DIS_AUTOSENSE) == 0)) { 1736 ch->hold[slot->slot] = ccb; 1737 ch->holdtag[slot->slot] = slot->tag; 1738 ch->numhslots++; 1739 } else 1740 xpt_done(ccb); 1741 /* If we have no other active commands, ... */ 1742 if (ch->rslots == 0) { 1743 /* if there was fatal error - reset port. */ 1744 if (ch->toslots != 0 || ch->fatalerr) { 1745 mvs_reset(dev); 1746 } else { 1747 /* if we have slots in error, we can reinit port. */ 1748 if (ch->eslots != 0) { 1749 mvs_set_edma_mode(dev, MVS_EDMA_OFF); 1750 ch->eslots = 0; 1751 } 1752 /* if there commands on hold, we can do READ LOG. */ 1753 if (!ch->recoverycmd && ch->numhslots) 1754 mvs_issue_recovery(dev); 1755 } 1756 /* If all the rest of commands are in timeout - give them chance. */ 1757 } else if ((ch->rslots & ~ch->toslots) == 0 && 1758 et != MVS_ERR_TIMEOUT) 1759 mvs_rearm_timeout(dev); 1760 /* Unfreeze frozen command. */ 1761 if (ch->frozen && !mvs_check_collision(dev, ch->frozen)) { 1762 union ccb *fccb = ch->frozen; 1763 ch->frozen = NULL; 1764 mvs_begin_transaction(dev, fccb); 1765 xpt_release_simq(ch->sim, TRUE); 1766 } 1767 /* Start PM timer. */ 1768 if (ch->numrslots == 0 && ch->pm_level > 3 && 1769 (ch->curr[ch->pm_present ? 15 : 0].caps & CTS_SATA_CAPS_D_PMREQ)) { 1770 callout_schedule(&ch->pm_timer, 1771 (ch->pm_level == 4) ? hz / 1000 : hz / 8); 1772 } 1773 } 1774 1775 static void 1776 mvs_issue_recovery(device_t dev) 1777 { 1778 struct mvs_channel *ch = device_get_softc(dev); 1779 union ccb *ccb; 1780 struct ccb_ataio *ataio; 1781 struct ccb_scsiio *csio; 1782 int i; 1783 1784 /* Find some held command. */ 1785 for (i = 0; i < MVS_MAX_SLOTS; i++) { 1786 if (ch->hold[i]) 1787 break; 1788 } 1789 ccb = xpt_alloc_ccb_nowait(); 1790 if (ccb == NULL) { 1791 device_printf(dev, "Unable to allocate recovery command\n"); 1792 completeall: 1793 /* We can't do anything -- complete held commands. */ 1794 for (i = 0; i < MVS_MAX_SLOTS; i++) { 1795 if (ch->hold[i] == NULL) 1796 continue; 1797 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK; 1798 ch->hold[i]->ccb_h.status |= CAM_RESRC_UNAVAIL; 1799 xpt_done(ch->hold[i]); 1800 ch->hold[i] = NULL; 1801 ch->numhslots--; 1802 } 1803 mvs_reset(dev); 1804 return; 1805 } 1806 ccb->ccb_h = ch->hold[i]->ccb_h; /* Reuse old header. */ 1807 if (ccb->ccb_h.func_code == XPT_ATA_IO) { 1808 /* READ LOG */ 1809 ccb->ccb_h.recovery_type = RECOVERY_READ_LOG; 1810 ccb->ccb_h.func_code = XPT_ATA_IO; 1811 ccb->ccb_h.flags = CAM_DIR_IN; 1812 ccb->ccb_h.timeout = 1000; /* 1s should be enough. */ 1813 ataio = &ccb->ataio; 1814 ataio->data_ptr = malloc(512, M_MVS, M_NOWAIT); 1815 if (ataio->data_ptr == NULL) { 1816 xpt_free_ccb(ccb); 1817 device_printf(dev, 1818 "Unable to allocate memory for READ LOG command\n"); 1819 goto completeall; 1820 } 1821 ataio->dxfer_len = 512; 1822 bzero(&ataio->cmd, sizeof(ataio->cmd)); 1823 ataio->cmd.flags = CAM_ATAIO_48BIT; 1824 ataio->cmd.command = 0x2F; /* READ LOG EXT */ 1825 ataio->cmd.sector_count = 1; 1826 ataio->cmd.sector_count_exp = 0; 1827 ataio->cmd.lba_low = 0x10; 1828 ataio->cmd.lba_mid = 0; 1829 ataio->cmd.lba_mid_exp = 0; 1830 } else { 1831 /* REQUEST SENSE */ 1832 ccb->ccb_h.recovery_type = RECOVERY_REQUEST_SENSE; 1833 ccb->ccb_h.recovery_slot = i; 1834 ccb->ccb_h.func_code = XPT_SCSI_IO; 1835 ccb->ccb_h.flags = CAM_DIR_IN; 1836 ccb->ccb_h.status = 0; 1837 ccb->ccb_h.timeout = 1000; /* 1s should be enough. */ 1838 csio = &ccb->csio; 1839 csio->data_ptr = (void *)&ch->hold[i]->csio.sense_data; 1840 csio->dxfer_len = ch->hold[i]->csio.sense_len; 1841 csio->cdb_len = 6; 1842 bzero(&csio->cdb_io, sizeof(csio->cdb_io)); 1843 csio->cdb_io.cdb_bytes[0] = 0x03; 1844 csio->cdb_io.cdb_bytes[4] = csio->dxfer_len; 1845 } 1846 /* Freeze SIM while doing recovery. */ 1847 ch->recoverycmd = 1; 1848 xpt_freeze_simq(ch->sim, 1); 1849 mvs_begin_transaction(dev, ccb); 1850 } 1851 1852 static void 1853 mvs_process_read_log(device_t dev, union ccb *ccb) 1854 { 1855 struct mvs_channel *ch = device_get_softc(dev); 1856 uint8_t *data; 1857 struct ata_res *res; 1858 int i; 1859 1860 ch->recoverycmd = 0; 1861 1862 data = ccb->ataio.data_ptr; 1863 if ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_CMP && 1864 (data[0] & 0x80) == 0) { 1865 for (i = 0; i < MVS_MAX_SLOTS; i++) { 1866 if (!ch->hold[i]) 1867 continue; 1868 if (ch->hold[i]->ccb_h.target_id != ccb->ccb_h.target_id) 1869 continue; 1870 if ((data[0] & 0x1F) == ch->holdtag[i]) { 1871 res = &ch->hold[i]->ataio.res; 1872 res->status = data[2]; 1873 res->error = data[3]; 1874 res->lba_low = data[4]; 1875 res->lba_mid = data[5]; 1876 res->lba_high = data[6]; 1877 res->device = data[7]; 1878 res->lba_low_exp = data[8]; 1879 res->lba_mid_exp = data[9]; 1880 res->lba_high_exp = data[10]; 1881 res->sector_count = data[12]; 1882 res->sector_count_exp = data[13]; 1883 } else { 1884 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK; 1885 ch->hold[i]->ccb_h.status |= CAM_REQUEUE_REQ; 1886 } 1887 xpt_done(ch->hold[i]); 1888 ch->hold[i] = NULL; 1889 ch->numhslots--; 1890 } 1891 } else { 1892 if ((ccb->ccb_h.status & CAM_STATUS_MASK) != CAM_REQ_CMP) 1893 device_printf(dev, "Error while READ LOG EXT\n"); 1894 else if ((data[0] & 0x80) == 0) { 1895 device_printf(dev, 1896 "Non-queued command error in READ LOG EXT\n"); 1897 } 1898 for (i = 0; i < MVS_MAX_SLOTS; i++) { 1899 if (!ch->hold[i]) 1900 continue; 1901 if (ch->hold[i]->ccb_h.target_id != ccb->ccb_h.target_id) 1902 continue; 1903 xpt_done(ch->hold[i]); 1904 ch->hold[i] = NULL; 1905 ch->numhslots--; 1906 } 1907 } 1908 free(ccb->ataio.data_ptr, M_MVS); 1909 xpt_free_ccb(ccb); 1910 xpt_release_simq(ch->sim, TRUE); 1911 } 1912 1913 static void 1914 mvs_process_request_sense(device_t dev, union ccb *ccb) 1915 { 1916 struct mvs_channel *ch = device_get_softc(dev); 1917 int i; 1918 1919 ch->recoverycmd = 0; 1920 1921 i = ccb->ccb_h.recovery_slot; 1922 if ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_CMP) { 1923 ch->hold[i]->ccb_h.status |= CAM_AUTOSNS_VALID; 1924 } else { 1925 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK; 1926 ch->hold[i]->ccb_h.status |= CAM_AUTOSENSE_FAIL; 1927 } 1928 xpt_done(ch->hold[i]); 1929 ch->hold[i] = NULL; 1930 ch->numhslots--; 1931 xpt_free_ccb(ccb); 1932 xpt_release_simq(ch->sim, TRUE); 1933 } 1934 1935 static int 1936 mvs_wait(device_t dev, u_int s, u_int c, int t) 1937 { 1938 int timeout = 0; 1939 uint8_t st; 1940 1941 while (((st = mvs_getstatus(dev, 0)) & (s | c)) != s) { 1942 if (timeout >= t) { 1943 if (t != 0) 1944 device_printf(dev, "Wait status %02x\n", st); 1945 return (-1); 1946 } 1947 DELAY(1000); 1948 timeout++; 1949 } 1950 return (timeout); 1951 } 1952 1953 static void 1954 mvs_requeue_frozen(device_t dev) 1955 { 1956 struct mvs_channel *ch = device_get_softc(dev); 1957 union ccb *fccb = ch->frozen; 1958 1959 if (fccb) { 1960 ch->frozen = NULL; 1961 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ; 1962 if (!(fccb->ccb_h.status & CAM_DEV_QFRZN)) { 1963 xpt_freeze_devq(fccb->ccb_h.path, 1); 1964 fccb->ccb_h.status |= CAM_DEV_QFRZN; 1965 } 1966 xpt_done(fccb); 1967 } 1968 } 1969 1970 static void 1971 mvs_reset_to(void *arg) 1972 { 1973 device_t dev = arg; 1974 struct mvs_channel *ch = device_get_softc(dev); 1975 int t; 1976 1977 if (ch->resetting == 0) 1978 return; 1979 ch->resetting--; 1980 if ((t = mvs_wait(dev, 0, ATA_S_BUSY | ATA_S_DRQ, 0)) >= 0) { 1981 if (bootverbose) { 1982 device_printf(dev, 1983 "MVS reset: device ready after %dms\n", 1984 (310 - ch->resetting) * 100); 1985 } 1986 ch->resetting = 0; 1987 xpt_release_simq(ch->sim, TRUE); 1988 return; 1989 } 1990 if (ch->resetting == 0) { 1991 device_printf(dev, 1992 "MVS reset: device not ready after 31000ms\n"); 1993 xpt_release_simq(ch->sim, TRUE); 1994 return; 1995 } 1996 callout_schedule(&ch->reset_timer, hz / 10); 1997 } 1998 1999 static void 2000 mvs_reset(device_t dev) 2001 { 2002 struct mvs_channel *ch = device_get_softc(dev); 2003 int i; 2004 2005 xpt_freeze_simq(ch->sim, 1); 2006 if (bootverbose) 2007 device_printf(dev, "MVS reset...\n"); 2008 /* Forget about previous reset. */ 2009 if (ch->resetting) { 2010 ch->resetting = 0; 2011 callout_stop(&ch->reset_timer); 2012 xpt_release_simq(ch->sim, TRUE); 2013 } 2014 /* Requeue freezed command. */ 2015 mvs_requeue_frozen(dev); 2016 /* Kill the engine and requeue all running commands. */ 2017 mvs_set_edma_mode(dev, MVS_EDMA_OFF); 2018 ATA_OUTL(ch->r_mem, DMA_C, 0); 2019 for (i = 0; i < MVS_MAX_SLOTS; i++) { 2020 /* Do we have a running request on slot? */ 2021 if (ch->slot[i].state < MVS_SLOT_RUNNING) 2022 continue; 2023 /* XXX; Commands in loading state. */ 2024 mvs_end_transaction(&ch->slot[i], MVS_ERR_INNOCENT); 2025 } 2026 for (i = 0; i < MVS_MAX_SLOTS; i++) { 2027 if (!ch->hold[i]) 2028 continue; 2029 xpt_done(ch->hold[i]); 2030 ch->hold[i] = NULL; 2031 ch->numhslots--; 2032 } 2033 if (ch->toslots != 0) 2034 xpt_release_simq(ch->sim, TRUE); 2035 ch->eslots = 0; 2036 ch->toslots = 0; 2037 ch->fatalerr = 0; 2038 ch->fake_busy = 0; 2039 /* Tell the XPT about the event */ 2040 xpt_async(AC_BUS_RESET, ch->path, NULL); 2041 ATA_OUTL(ch->r_mem, EDMA_IEM, 0); 2042 ATA_OUTL(ch->r_mem, EDMA_CMD, EDMA_CMD_EATARST); 2043 DELAY(25); 2044 ATA_OUTL(ch->r_mem, EDMA_CMD, 0); 2045 /* Reset and reconnect PHY, */ 2046 if (!mvs_sata_phy_reset(dev)) { 2047 if (bootverbose) 2048 device_printf(dev, "MVS reset: device not found\n"); 2049 ch->devices = 0; 2050 ATA_OUTL(ch->r_mem, SATA_SE, 0xffffffff); 2051 ATA_OUTL(ch->r_mem, EDMA_IEC, 0); 2052 ATA_OUTL(ch->r_mem, EDMA_IEM, ~EDMA_IE_TRANSIENT); 2053 xpt_release_simq(ch->sim, TRUE); 2054 return; 2055 } 2056 if (bootverbose) 2057 device_printf(dev, "MVS reset: device found\n"); 2058 /* Wait for clearing busy status. */ 2059 if ((i = mvs_wait(dev, 0, ATA_S_BUSY | ATA_S_DRQ, 2060 dumping ? 31000 : 0)) < 0) { 2061 if (dumping) { 2062 device_printf(dev, 2063 "MVS reset: device not ready after 31000ms\n"); 2064 } else 2065 ch->resetting = 310; 2066 } else if (bootverbose) 2067 device_printf(dev, "MVS reset: device ready after %dms\n", i); 2068 ch->devices = 1; 2069 ATA_OUTL(ch->r_mem, SATA_SE, 0xffffffff); 2070 ATA_OUTL(ch->r_mem, EDMA_IEC, 0); 2071 ATA_OUTL(ch->r_mem, EDMA_IEM, ~EDMA_IE_TRANSIENT); 2072 if (ch->resetting) 2073 callout_reset(&ch->reset_timer, hz / 10, mvs_reset_to, dev); 2074 else 2075 xpt_release_simq(ch->sim, TRUE); 2076 } 2077 2078 static void 2079 mvs_softreset(device_t dev, union ccb *ccb) 2080 { 2081 struct mvs_channel *ch = device_get_softc(dev); 2082 int port = ccb->ccb_h.target_id & 0x0f; 2083 int i, stuck; 2084 uint8_t status; 2085 2086 mvs_set_edma_mode(dev, MVS_EDMA_OFF); 2087 ATA_OUTB(ch->r_mem, SATA_SATAICTL, port << SATA_SATAICTL_PMPTX_SHIFT); 2088 ATA_OUTB(ch->r_mem, ATA_CONTROL, ATA_A_RESET); 2089 DELAY(10000); 2090 ATA_OUTB(ch->r_mem, ATA_CONTROL, 0); 2091 ccb->ccb_h.status &= ~CAM_STATUS_MASK; 2092 /* Wait for clearing busy status. */ 2093 if ((i = mvs_wait(dev, 0, ATA_S_BUSY, ccb->ccb_h.timeout)) < 0) { 2094 ccb->ccb_h.status |= CAM_CMD_TIMEOUT; 2095 stuck = 1; 2096 } else { 2097 status = mvs_getstatus(dev, 0); 2098 if (status & ATA_S_ERROR) 2099 ccb->ccb_h.status |= CAM_ATA_STATUS_ERROR; 2100 else 2101 ccb->ccb_h.status |= CAM_REQ_CMP; 2102 if (status & ATA_S_DRQ) 2103 stuck = 1; 2104 else 2105 stuck = 0; 2106 } 2107 mvs_tfd_read(dev, ccb); 2108 2109 /* 2110 * XXX: If some device on PMP failed to soft-reset, 2111 * try to recover by sending dummy soft-reset to PMP. 2112 */ 2113 if (stuck && ch->pm_present && port != 15) { 2114 ATA_OUTB(ch->r_mem, SATA_SATAICTL, 2115 15 << SATA_SATAICTL_PMPTX_SHIFT); 2116 ATA_OUTB(ch->r_mem, ATA_CONTROL, ATA_A_RESET); 2117 DELAY(10000); 2118 ATA_OUTB(ch->r_mem, ATA_CONTROL, 0); 2119 mvs_wait(dev, 0, ATA_S_BUSY | ATA_S_DRQ, ccb->ccb_h.timeout); 2120 } 2121 2122 xpt_done(ccb); 2123 } 2124 2125 static int 2126 mvs_sata_connect(struct mvs_channel *ch) 2127 { 2128 u_int32_t status; 2129 int timeout, found = 0; 2130 2131 /* Wait up to 100ms for "connect well" */ 2132 for (timeout = 0; timeout < 1000 ; timeout++) { 2133 status = ATA_INL(ch->r_mem, SATA_SS); 2134 if ((status & SATA_SS_DET_MASK) != SATA_SS_DET_NO_DEVICE) 2135 found = 1; 2136 if (((status & SATA_SS_DET_MASK) == SATA_SS_DET_PHY_ONLINE) && 2137 ((status & SATA_SS_SPD_MASK) != SATA_SS_SPD_NO_SPEED) && 2138 ((status & SATA_SS_IPM_MASK) == SATA_SS_IPM_ACTIVE)) 2139 break; 2140 if ((status & SATA_SS_DET_MASK) == SATA_SS_DET_PHY_OFFLINE) { 2141 if (bootverbose) { 2142 device_printf(ch->dev, "SATA offline status=%08x\n", 2143 status); 2144 } 2145 return (0); 2146 } 2147 if (found == 0 && timeout >= 100) 2148 break; 2149 DELAY(100); 2150 } 2151 if (timeout >= 1000 || !found) { 2152 if (bootverbose) { 2153 device_printf(ch->dev, 2154 "SATA connect timeout time=%dus status=%08x\n", 2155 timeout * 100, status); 2156 } 2157 return (0); 2158 } 2159 if (bootverbose) { 2160 device_printf(ch->dev, "SATA connect time=%dus status=%08x\n", 2161 timeout * 100, status); 2162 } 2163 /* Clear SATA error register */ 2164 ATA_OUTL(ch->r_mem, SATA_SE, 0xffffffff); 2165 return (1); 2166 } 2167 2168 static int 2169 mvs_sata_phy_reset(device_t dev) 2170 { 2171 struct mvs_channel *ch = device_get_softc(dev); 2172 int sata_rev; 2173 uint32_t val; 2174 2175 sata_rev = ch->user[ch->pm_present ? 15 : 0].revision; 2176 if (sata_rev == 1) 2177 val = SATA_SC_SPD_SPEED_GEN1; 2178 else if (sata_rev == 2) 2179 val = SATA_SC_SPD_SPEED_GEN2; 2180 else if (sata_rev == 3) 2181 val = SATA_SC_SPD_SPEED_GEN3; 2182 else 2183 val = 0; 2184 ATA_OUTL(ch->r_mem, SATA_SC, 2185 SATA_SC_DET_RESET | val | 2186 SATA_SC_IPM_DIS_PARTIAL | SATA_SC_IPM_DIS_SLUMBER); 2187 DELAY(1000); 2188 ATA_OUTL(ch->r_mem, SATA_SC, 2189 SATA_SC_DET_IDLE | val | ((ch->pm_level > 0) ? 0 : 2190 (SATA_SC_IPM_DIS_PARTIAL | SATA_SC_IPM_DIS_SLUMBER))); 2191 if (!mvs_sata_connect(ch)) { 2192 if (ch->pm_level > 0) 2193 ATA_OUTL(ch->r_mem, SATA_SC, SATA_SC_DET_DISABLE); 2194 return (0); 2195 } 2196 return (1); 2197 } 2198 2199 static int 2200 mvs_check_ids(device_t dev, union ccb *ccb) 2201 { 2202 struct mvs_channel *ch = device_get_softc(dev); 2203 2204 if (ccb->ccb_h.target_id > ((ch->quirks & MVS_Q_GENI) ? 0 : 15)) { 2205 ccb->ccb_h.status = CAM_TID_INVALID; 2206 xpt_done(ccb); 2207 return (-1); 2208 } 2209 if (ccb->ccb_h.target_lun != 0) { 2210 ccb->ccb_h.status = CAM_LUN_INVALID; 2211 xpt_done(ccb); 2212 return (-1); 2213 } 2214 return (0); 2215 } 2216 2217 static void 2218 mvsaction(struct cam_sim *sim, union ccb *ccb) 2219 { 2220 device_t dev, parent; 2221 struct mvs_channel *ch; 2222 2223 CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_TRACE, ("mvsaction func_code=%x\n", 2224 ccb->ccb_h.func_code)); 2225 2226 ch = (struct mvs_channel *)cam_sim_softc(sim); 2227 dev = ch->dev; 2228 switch (ccb->ccb_h.func_code) { 2229 /* Common cases first */ 2230 case XPT_ATA_IO: /* Execute the requested I/O operation */ 2231 case XPT_SCSI_IO: 2232 if (mvs_check_ids(dev, ccb)) 2233 return; 2234 if (ch->devices == 0 || 2235 (ch->pm_present == 0 && 2236 ccb->ccb_h.target_id > 0 && ccb->ccb_h.target_id < 15)) { 2237 ccb->ccb_h.status = CAM_SEL_TIMEOUT; 2238 break; 2239 } 2240 ccb->ccb_h.recovery_type = RECOVERY_NONE; 2241 /* Check for command collision. */ 2242 if (mvs_check_collision(dev, ccb)) { 2243 /* Freeze command. */ 2244 ch->frozen = ccb; 2245 /* We have only one frozen slot, so freeze simq also. */ 2246 xpt_freeze_simq(ch->sim, 1); 2247 return; 2248 } 2249 mvs_begin_transaction(dev, ccb); 2250 return; 2251 case XPT_EN_LUN: /* Enable LUN as a target */ 2252 case XPT_TARGET_IO: /* Execute target I/O request */ 2253 case XPT_ACCEPT_TARGET_IO: /* Accept Host Target Mode CDB */ 2254 case XPT_CONT_TARGET_IO: /* Continue Host Target I/O Connection*/ 2255 case XPT_ABORT: /* Abort the specified CCB */ 2256 /* XXX Implement */ 2257 ccb->ccb_h.status = CAM_REQ_INVALID; 2258 break; 2259 case XPT_SET_TRAN_SETTINGS: 2260 { 2261 struct ccb_trans_settings *cts = &ccb->cts; 2262 struct mvs_device *d; 2263 2264 if (mvs_check_ids(dev, ccb)) 2265 return; 2266 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) 2267 d = &ch->curr[ccb->ccb_h.target_id]; 2268 else 2269 d = &ch->user[ccb->ccb_h.target_id]; 2270 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_REVISION) 2271 d->revision = cts->xport_specific.sata.revision; 2272 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_MODE) 2273 d->mode = cts->xport_specific.sata.mode; 2274 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_BYTECOUNT) { 2275 d->bytecount = min((ch->quirks & MVS_Q_GENIIE) ? 8192 : 2048, 2276 cts->xport_specific.sata.bytecount); 2277 } 2278 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_TAGS) 2279 d->tags = min(MVS_MAX_SLOTS, cts->xport_specific.sata.tags); 2280 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_PM) 2281 ch->pm_present = cts->xport_specific.sata.pm_present; 2282 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_ATAPI) 2283 d->atapi = cts->xport_specific.sata.atapi; 2284 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_CAPS) 2285 d->caps = cts->xport_specific.sata.caps; 2286 ccb->ccb_h.status = CAM_REQ_CMP; 2287 break; 2288 } 2289 case XPT_GET_TRAN_SETTINGS: 2290 /* Get default/user set transfer settings for the target */ 2291 { 2292 struct ccb_trans_settings *cts = &ccb->cts; 2293 struct mvs_device *d; 2294 uint32_t status; 2295 2296 if (mvs_check_ids(dev, ccb)) 2297 return; 2298 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) 2299 d = &ch->curr[ccb->ccb_h.target_id]; 2300 else 2301 d = &ch->user[ccb->ccb_h.target_id]; 2302 cts->protocol = PROTO_ATA; 2303 cts->protocol_version = PROTO_VERSION_UNSPECIFIED; 2304 cts->transport = XPORT_SATA; 2305 cts->transport_version = XPORT_VERSION_UNSPECIFIED; 2306 cts->proto_specific.valid = 0; 2307 cts->xport_specific.sata.valid = 0; 2308 if (cts->type == CTS_TYPE_CURRENT_SETTINGS && 2309 (ccb->ccb_h.target_id == 15 || 2310 (ccb->ccb_h.target_id == 0 && !ch->pm_present))) { 2311 status = ATA_INL(ch->r_mem, SATA_SS) & SATA_SS_SPD_MASK; 2312 if (status & 0x0f0) { 2313 cts->xport_specific.sata.revision = 2314 (status & 0x0f0) >> 4; 2315 cts->xport_specific.sata.valid |= 2316 CTS_SATA_VALID_REVISION; 2317 } 2318 cts->xport_specific.sata.caps = d->caps & CTS_SATA_CAPS_D; 2319 // if (ch->pm_level) 2320 // cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_PMREQ; 2321 cts->xport_specific.sata.caps |= CTS_SATA_CAPS_H_AN; 2322 cts->xport_specific.sata.caps &= 2323 ch->user[ccb->ccb_h.target_id].caps; 2324 cts->xport_specific.sata.valid |= CTS_SATA_VALID_CAPS; 2325 } else { 2326 cts->xport_specific.sata.revision = d->revision; 2327 cts->xport_specific.sata.valid |= CTS_SATA_VALID_REVISION; 2328 cts->xport_specific.sata.caps = d->caps; 2329 if (cts->type == CTS_TYPE_CURRENT_SETTINGS/* && 2330 (ch->quirks & MVS_Q_GENIIE) == 0*/) 2331 cts->xport_specific.sata.caps &= ~CTS_SATA_CAPS_H_AN; 2332 cts->xport_specific.sata.valid |= CTS_SATA_VALID_CAPS; 2333 } 2334 cts->xport_specific.sata.mode = d->mode; 2335 cts->xport_specific.sata.valid |= CTS_SATA_VALID_MODE; 2336 cts->xport_specific.sata.bytecount = d->bytecount; 2337 cts->xport_specific.sata.valid |= CTS_SATA_VALID_BYTECOUNT; 2338 cts->xport_specific.sata.pm_present = ch->pm_present; 2339 cts->xport_specific.sata.valid |= CTS_SATA_VALID_PM; 2340 cts->xport_specific.sata.tags = d->tags; 2341 cts->xport_specific.sata.valid |= CTS_SATA_VALID_TAGS; 2342 cts->xport_specific.sata.atapi = d->atapi; 2343 cts->xport_specific.sata.valid |= CTS_SATA_VALID_ATAPI; 2344 ccb->ccb_h.status = CAM_REQ_CMP; 2345 break; 2346 } 2347 case XPT_RESET_BUS: /* Reset the specified SCSI bus */ 2348 case XPT_RESET_DEV: /* Bus Device Reset the specified SCSI device */ 2349 mvs_reset(dev); 2350 ccb->ccb_h.status = CAM_REQ_CMP; 2351 break; 2352 case XPT_TERM_IO: /* Terminate the I/O process */ 2353 /* XXX Implement */ 2354 ccb->ccb_h.status = CAM_REQ_INVALID; 2355 break; 2356 case XPT_PATH_INQ: /* Path routing inquiry */ 2357 { 2358 struct ccb_pathinq *cpi = &ccb->cpi; 2359 2360 parent = device_get_parent(dev); 2361 cpi->version_num = 1; /* XXX??? */ 2362 cpi->hba_inquiry = PI_SDTR_ABLE; 2363 if (!(ch->quirks & MVS_Q_GENI)) { 2364 cpi->hba_inquiry |= PI_SATAPM; 2365 /* Gen-II is extremely slow with NCQ on PMP. */ 2366 if ((ch->quirks & MVS_Q_GENIIE) || ch->pm_present == 0) 2367 cpi->hba_inquiry |= PI_TAG_ABLE; 2368 } 2369 cpi->target_sprt = 0; 2370 cpi->hba_misc = PIM_SEQSCAN; 2371 cpi->hba_eng_cnt = 0; 2372 if (!(ch->quirks & MVS_Q_GENI)) 2373 cpi->max_target = 15; 2374 else 2375 cpi->max_target = 0; 2376 cpi->max_lun = 0; 2377 cpi->initiator_id = 0; 2378 cpi->bus_id = cam_sim_bus(sim); 2379 cpi->base_transfer_speed = 150000; 2380 strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN); 2381 strncpy(cpi->hba_vid, "Marvell", HBA_IDLEN); 2382 strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN); 2383 cpi->unit_number = cam_sim_unit(sim); 2384 cpi->transport = XPORT_SATA; 2385 cpi->transport_version = XPORT_VERSION_UNSPECIFIED; 2386 cpi->protocol = PROTO_ATA; 2387 cpi->protocol_version = PROTO_VERSION_UNSPECIFIED; 2388 cpi->maxio = MAXPHYS; 2389 if ((ch->quirks & MVS_Q_SOC) == 0) { 2390 cpi->hba_vendor = pci_get_vendor(parent); 2391 cpi->hba_device = pci_get_device(parent); 2392 cpi->hba_subvendor = pci_get_subvendor(parent); 2393 cpi->hba_subdevice = pci_get_subdevice(parent); 2394 } 2395 cpi->ccb_h.status = CAM_REQ_CMP; 2396 break; 2397 } 2398 default: 2399 ccb->ccb_h.status = CAM_REQ_INVALID; 2400 break; 2401 } 2402 xpt_done(ccb); 2403 } 2404 2405 static void 2406 mvspoll(struct cam_sim *sim) 2407 { 2408 struct mvs_channel *ch = (struct mvs_channel *)cam_sim_softc(sim); 2409 struct mvs_intr_arg arg; 2410 2411 arg.arg = ch->dev; 2412 arg.cause = 2 | 4; /* XXX */ 2413 mvs_ch_intr(&arg); 2414 if (ch->resetting != 0 && 2415 (--ch->resetpolldiv <= 0 || !callout_pending(&ch->reset_timer))) { 2416 ch->resetpolldiv = 1000; 2417 mvs_reset_to(ch->dev); 2418 } 2419 } 2420 2421