1 /****************************************************************************** 2 * 3 * Name: skgehw.h 4 * Project: Gigabit Ethernet Adapters, Common Modules 5 * Version: $Revision: 2.49 $ 6 * Date: $Date: 2005/01/20 13:01:35 $ 7 * Purpose: Defines and Macros for the Gigabit Ethernet Adapter Product Family 8 * 9 ******************************************************************************/ 10 11 /****************************************************************************** 12 * 13 * LICENSE: 14 * Copyright (C) Marvell International Ltd. and/or its affiliates 15 * 16 * The computer program files contained in this folder ("Files") 17 * are provided to you under the BSD-type license terms provided 18 * below, and any use of such Files and any derivative works 19 * thereof created by you shall be governed by the following terms 20 * and conditions: 21 * 22 * - Redistributions of source code must retain the above copyright 23 * notice, this list of conditions and the following disclaimer. 24 * - Redistributions in binary form must reproduce the above 25 * copyright notice, this list of conditions and the following 26 * disclaimer in the documentation and/or other materials provided 27 * with the distribution. 28 * - Neither the name of Marvell nor the names of its contributors 29 * may be used to endorse or promote products derived from this 30 * software without specific prior written permission. 31 * 32 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 33 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 34 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 35 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 36 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 37 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 38 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 39 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 40 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 41 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 42 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED 43 * OF THE POSSIBILITY OF SUCH DAMAGE. 44 * /LICENSE 45 * 46 ******************************************************************************/ 47 48 /*- 49 * Copyright (c) 1997, 1998, 1999, 2000 50 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 51 * 52 * Redistribution and use in source and binary forms, with or without 53 * modification, are permitted provided that the following conditions 54 * are met: 55 * 1. Redistributions of source code must retain the above copyright 56 * notice, this list of conditions and the following disclaimer. 57 * 2. Redistributions in binary form must reproduce the above copyright 58 * notice, this list of conditions and the following disclaimer in the 59 * documentation and/or other materials provided with the distribution. 60 * 3. All advertising materials mentioning features or use of this software 61 * must display the following acknowledgement: 62 * This product includes software developed by Bill Paul. 63 * 4. Neither the name of the author nor the names of any co-contributors 64 * may be used to endorse or promote products derived from this software 65 * without specific prior written permission. 66 * 67 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 68 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 69 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 70 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 71 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 72 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 73 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 74 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 75 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 76 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 77 * THE POSSIBILITY OF SUCH DAMAGE. 78 */ 79 80 /*- 81 * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu> 82 * 83 * Permission to use, copy, modify, and distribute this software for any 84 * purpose with or without fee is hereby granted, provided that the above 85 * copyright notice and this permission notice appear in all copies. 86 * 87 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 88 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 89 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 90 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 91 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 92 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 93 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 94 */ 95 96 /*$FreeBSD$*/ 97 98 /* 99 * SysKonnect PCI vendor ID 100 */ 101 #define VENDORID_SK 0x1148 102 103 /* 104 * Marvell PCI vendor ID 105 */ 106 #define VENDORID_MARVELL 0x11AB 107 108 /* 109 * D-Link PCI vendor ID 110 */ 111 #define VENDORID_DLINK 0x1186 112 113 /* 114 * SysKonnect ethernet device IDs 115 */ 116 #define DEVICEID_SK_YUKON2 0x9000 117 #define DEVICEID_SK_YUKON2_EXPR 0x9e00 118 119 /* 120 * Marvell gigabit ethernet device IDs 121 */ 122 #define DEVICEID_MRVL_8021CU 0x4340 123 #define DEVICEID_MRVL_8022CU 0x4341 124 #define DEVICEID_MRVL_8061CU 0x4342 125 #define DEVICEID_MRVL_8062CU 0x4343 126 #define DEVICEID_MRVL_8021X 0x4344 127 #define DEVICEID_MRVL_8022X 0x4345 128 #define DEVICEID_MRVL_8061X 0x4346 129 #define DEVICEID_MRVL_8062X 0x4347 130 #define DEVICEID_MRVL_8035 0x4350 131 #define DEVICEID_MRVL_8036 0x4351 132 #define DEVICEID_MRVL_8038 0x4352 133 #define DEVICEID_MRVL_8039 0x4353 134 #define DEVICEID_MRVL_8040 0x4354 135 #define DEVICEID_MRVL_8040T 0x4355 136 #define DEVICEID_MRVL_8042 0x4357 137 #define DEVICEID_MRVL_8048 0x435A 138 #define DEVICEID_MRVL_4360 0x4360 139 #define DEVICEID_MRVL_4361 0x4361 140 #define DEVICEID_MRVL_4362 0x4362 141 #define DEVICEID_MRVL_4363 0x4363 142 #define DEVICEID_MRVL_4364 0x4364 143 #define DEVICEID_MRVL_4365 0x4365 144 #define DEVICEID_MRVL_436A 0x436A 145 #define DEVICEID_MRVL_436B 0x436B 146 #define DEVICEID_MRVL_436C 0x436C 147 #define DEVICEID_MRVL_4380 0x4380 148 149 /* 150 * D-Link gigabit ethernet device ID 151 */ 152 #define DEVICEID_DLINK_DGE550SX 0x4001 153 #define DEVICEID_DLINK_DGE560SX 0x4002 154 #define DEVICEID_DLINK_DGE560T 0x4b00 155 156 #define BIT_31 (1 << 31) 157 #define BIT_30 (1 << 30) 158 #define BIT_29 (1 << 29) 159 #define BIT_28 (1 << 28) 160 #define BIT_27 (1 << 27) 161 #define BIT_26 (1 << 26) 162 #define BIT_25 (1 << 25) 163 #define BIT_24 (1 << 24) 164 #define BIT_23 (1 << 23) 165 #define BIT_22 (1 << 22) 166 #define BIT_21 (1 << 21) 167 #define BIT_20 (1 << 20) 168 #define BIT_19 (1 << 19) 169 #define BIT_18 (1 << 18) 170 #define BIT_17 (1 << 17) 171 #define BIT_16 (1 << 16) 172 #define BIT_15 (1 << 15) 173 #define BIT_14 (1 << 14) 174 #define BIT_13 (1 << 13) 175 #define BIT_12 (1 << 12) 176 #define BIT_11 (1 << 11) 177 #define BIT_10 (1 << 10) 178 #define BIT_9 (1 << 9) 179 #define BIT_8 (1 << 8) 180 #define BIT_7 (1 << 7) 181 #define BIT_6 (1 << 6) 182 #define BIT_5 (1 << 5) 183 #define BIT_4 (1 << 4) 184 #define BIT_3 (1 << 3) 185 #define BIT_2 (1 << 2) 186 #define BIT_1 (1 << 1) 187 #define BIT_0 (1 << 0) 188 189 #define SHIFT31(x) ((x) << 31) 190 #define SHIFT30(x) ((x) << 30) 191 #define SHIFT29(x) ((x) << 29) 192 #define SHIFT28(x) ((x) << 28) 193 #define SHIFT27(x) ((x) << 27) 194 #define SHIFT26(x) ((x) << 26) 195 #define SHIFT25(x) ((x) << 25) 196 #define SHIFT24(x) ((x) << 24) 197 #define SHIFT23(x) ((x) << 23) 198 #define SHIFT22(x) ((x) << 22) 199 #define SHIFT21(x) ((x) << 21) 200 #define SHIFT20(x) ((x) << 20) 201 #define SHIFT19(x) ((x) << 19) 202 #define SHIFT18(x) ((x) << 18) 203 #define SHIFT17(x) ((x) << 17) 204 #define SHIFT16(x) ((x) << 16) 205 #define SHIFT15(x) ((x) << 15) 206 #define SHIFT14(x) ((x) << 14) 207 #define SHIFT13(x) ((x) << 13) 208 #define SHIFT12(x) ((x) << 12) 209 #define SHIFT11(x) ((x) << 11) 210 #define SHIFT10(x) ((x) << 10) 211 #define SHIFT9(x) ((x) << 9) 212 #define SHIFT8(x) ((x) << 8) 213 #define SHIFT7(x) ((x) << 7) 214 #define SHIFT6(x) ((x) << 6) 215 #define SHIFT5(x) ((x) << 5) 216 #define SHIFT4(x) ((x) << 4) 217 #define SHIFT3(x) ((x) << 3) 218 #define SHIFT2(x) ((x) << 2) 219 #define SHIFT1(x) ((x) << 1) 220 #define SHIFT0(x) ((x) << 0) 221 222 /* 223 * PCI Configuration Space header 224 */ 225 #define PCI_BASE_1ST 0x10 /* 32 bit 1st Base address */ 226 #define PCI_BASE_2ND 0x14 /* 32 bit 2nd Base address */ 227 #define PCI_OUR_REG_1 0x40 /* 32 bit Our Register 1 */ 228 #define PCI_OUR_REG_2 0x44 /* 32 bit Our Register 2 */ 229 #define PCI_OUR_STATUS 0x7c /* 32 bit Adapter Status Register */ 230 #define PCI_OUR_REG_3 0x80 /* 32 bit Our Register 3 */ 231 #define PCI_OUR_REG_4 0x84 /* 32 bit Our Register 4 */ 232 #define PCI_OUR_REG_5 0x88 /* 32 bit Our Register 5 */ 233 #define PCI_CFG_REG_0 0x90 /* 32 bit Config Register 0 */ 234 #define PCI_CFG_REG_1 0x94 /* 32 bit Config Register 1 */ 235 236 /* PCI Express Capability */ 237 #define PEX_CAP_ID 0xe0 /* 8 bit PEX Capability ID */ 238 #define PEX_NITEM 0xe1 /* 8 bit PEX Next Item Pointer */ 239 #define PEX_CAP_REG 0xe2 /* 16 bit PEX Capability Register */ 240 #define PEX_DEV_CAP 0xe4 /* 32 bit PEX Device Capabilities */ 241 #define PEX_DEV_CTRL 0xe8 /* 16 bit PEX Device Control */ 242 #define PEX_DEV_STAT 0xea /* 16 bit PEX Device Status */ 243 #define PEX_LNK_CAP 0xec /* 32 bit PEX Link Capabilities */ 244 #define PEX_LNK_CTRL 0xf0 /* 16 bit PEX Link Control */ 245 #define PEX_LNK_STAT 0xf2 /* 16 bit PEX Link Status */ 246 247 /* PCI Express Extended Capabilities */ 248 #define PEX_ADV_ERR_REP 0x100 /* 32 bit PEX Advanced Error Reporting */ 249 #define PEX_UNC_ERR_STAT 0x104 /* 32 bit PEX Uncorr. Errors Status */ 250 #define PEX_UNC_ERR_MASK 0x108 /* 32 bit PEX Uncorr. Errors Mask */ 251 #define PEX_UNC_ERR_SEV 0x10c /* 32 bit PEX Uncorr. Errors Severity */ 252 #define PEX_COR_ERR_STAT 0x110 /* 32 bit PEX Correc. Errors Status */ 253 #define PEX_COR_ERR_MASK 0x114 /* 32 bit PEX Correc. Errors Mask */ 254 #define PEX_ADV_ERR_CAP_C 0x118 /* 32 bit PEX Advanced Error Cap./Ctrl */ 255 #define PEX_HEADER_LOG 0x11c /* 4x32 bit PEX Header Log Register */ 256 257 /* PCI_OUR_REG_1 32 bit Our Register 1 */ 258 #define PCI_Y2_PIG_ENA BIT_31 /* Enable Plug-in-Go (YUKON-2) */ 259 #define PCI_Y2_DLL_DIS BIT_30 /* Disable PCI DLL (YUKON-2) */ 260 #define PCI_Y2_PHY2_COMA BIT_29 /* Set PHY 2 to Coma Mode (YUKON-2) */ 261 #define PCI_Y2_PHY1_COMA BIT_28 /* Set PHY 1 to Coma Mode (YUKON-2) */ 262 #define PCI_Y2_PHY2_POWD BIT_27 /* Set PHY 2 to Power Down (YUKON-2) */ 263 #define PCI_Y2_PHY1_POWD BIT_26 /* Set PHY 1 to Power Down (YUKON-2) */ 264 #define PCI_DIS_BOOT BIT_24 /* Disable BOOT via ROM */ 265 #define PCI_EN_IO BIT_23 /* Mapping to I/O space */ 266 #define PCI_EN_FPROM BIT_22 /* Enable FLASH mapping to memory */ 267 /* 1 = Map Flash to memory */ 268 /* 0 = Disable addr. dec */ 269 #define PCI_PAGESIZE (3L<<20)/* Bit 21..20: FLASH Page Size */ 270 #define PCI_PAGE_16 (0L<<20)/* 16 k pages */ 271 #define PCI_PAGE_32K (1L<<20)/* 32 k pages */ 272 #define PCI_PAGE_64K (2L<<20)/* 64 k pages */ 273 #define PCI_PAGE_128K (3L<<20)/* 128 k pages */ 274 #define PCI_PAGEREG (7L<<16)/* Bit 18..16: Page Register */ 275 #define PCI_PEX_LEGNAT BIT_15 /* PEX PM legacy/native mode (YUKON-2) */ 276 #define PCI_FORCE_BE BIT_14 /* Assert all BEs on MR */ 277 #define PCI_DIS_MRL BIT_13 /* Disable Mem Read Line */ 278 #define PCI_DIS_MRM BIT_12 /* Disable Mem Read Multiple */ 279 #define PCI_DIS_MWI BIT_11 /* Disable Mem Write & Invalidate */ 280 #define PCI_DISC_CLS BIT_10 /* Disc: cacheLsz bound */ 281 #define PCI_BURST_DIS BIT_9 /* Burst Disable */ 282 #define PCI_DIS_PCI_CLK BIT_8 /* Disable PCI clock driving */ 283 #define PCI_SKEW_DAS (0xfL<<4)/* Bit 7.. 4: Skew Ctrl, DAS Ext */ 284 #define PCI_SKEW_BASE 0xfL /* Bit 3.. 0: Skew Ctrl, Base */ 285 #define PCI_CLS_OPT BIT_3 /* Cache Line Size opt. PCI-X (YUKON-2) */ 286 287 /* PCI_OUR_REG_2 32 bit Our Register 2 */ 288 #define PCI_VPD_WR_THR (0xff<<24) /* Bit 31..24: VPD Write Threshold */ 289 #define PCI_DEV_SEL (0x7f<<17) /* Bit 23..17: EEPROM Device Select */ 290 #define PCI_VPD_ROM_SZ (0x07<<14) /* Bit 16..14: VPD ROM Size */ 291 /* Bit 13..12: reserved */ 292 #define PCI_PATCH_DIR (0x0f<<8) /* Bit 11.. 8: Ext Patches dir 3..0 */ 293 #define PCI_PATCH_DIR_3 BIT_11 294 #define PCI_PATCH_DIR_2 BIT_10 295 #define PCI_PATCH_DIR_1 BIT_9 296 #define PCI_PATCH_DIR_0 BIT_8 297 #define PCI_EXT_PATCHS (0x0f<<4) /* Bit 7.. 4: Extended Patches 3..0 */ 298 #define PCI_EXT_PATCH_3 BIT_7 299 #define PCI_EXT_PATCH_2 BIT_6 300 #define PCI_EXT_PATCH_1 BIT_5 301 #define PCI_EXT_PATCH_0 BIT_4 302 #define PCI_EN_DUMMY_RD BIT_3 /* Enable Dummy Read */ 303 #define PCI_REV_DESC BIT_2 /* Reverse Desc. Bytes */ 304 #define PCI_USEDATA64 BIT_0 /* Use 64Bit Data bus ext */ 305 306 /* PCI_OUR_STATUS 32 bit Adapter Status Register (Yukon-2) */ 307 #define PCI_OS_PCI64B BIT_31 /* Conventional PCI 64 bits Bus */ 308 #define PCI_OS_PCIX BIT_30 /* PCI-X Bus */ 309 #define PCI_OS_MODE_MSK (3<<28) /* Bit 29..28: PCI-X Bus Mode Mask */ 310 #define PCI_OS_PCI66M BIT_27 /* PCI 66 MHz Bus */ 311 #define PCI_OS_PCI_X BIT_26 /* PCI/PCI-X Bus (0 = PEX) */ 312 #define PCI_OS_DLLE_MSK (3<<24) /* Bit 25..24: DLL Status Indication */ 313 #define PCI_OS_DLLR_MSK (0x0f<<20) /* Bit 23..20: DLL Row Counters Values */ 314 #define PCI_OS_DLLC_MSK (0x0f<<16) /* Bit 19..16: DLL Col. Counters Values */ 315 316 #define PCI_OS_SPEED(val) ((val & PCI_OS_MODE_MSK) >> 28) /* PCI-X Speed */ 317 /* possible values for the speed field of the register */ 318 #define PCI_OS_SPD_PCI 0 /* PCI Conventional Bus */ 319 #define PCI_OS_SPD_X66 1 /* PCI-X 66MHz Bus */ 320 #define PCI_OS_SPD_X100 2 /* PCI-X 100MHz Bus */ 321 #define PCI_OS_SPD_X133 3 /* PCI-X 133MHz Bus */ 322 323 /* PCI_OUR_REG_4 32 bit Our Register 4 (Yukon-ECU only) */ 324 #define PCI_TIMER_VALUE_MSK (0xff<<16) /* Bit 23..16: Timer Value Mask */ 325 #define PCI_FORCE_ASPM_REQUEST BIT_15 /* Force ASPM Request (A1 only) */ 326 #define PCI_ASPM_GPHY_LINK_DOWN BIT_14 /* GPHY Link Down (A1 only) */ 327 #define PCI_ASPM_INT_FIFO_EMPTY BIT_13 /* Internal FIFO Empty (A1 only) */ 328 #define PCI_ASPM_CLKRUN_REQUEST BIT_12 /* CLKRUN Request (A1 only) */ 329 #define PCI_ASPM_FORCE_CLKREQ_ENA BIT_4 /* Force CLKREQ Enable (A1b only) */ 330 #define PCI_ASPM_CLKREQ_PAD_CTL BIT_3 /* CLKREQ PAD Control (A1 only) */ 331 #define PCI_ASPM_A1_MODE_SELECT BIT_2 /* A1 Mode Select (A1 only) */ 332 #define PCI_CLK_GATE_PEX_UNIT_ENA BIT_1 /* Enable Gate PEX Unit Clock */ 333 #define PCI_CLK_GATE_ROOT_COR_ENA BIT_0 /* Enable Gate Root Core Clock */ 334 335 /* PCI_OUR_REG_5 32 bit Our Register 5 (Yukon-ECU only) */ 336 /* Bit 31..27: for A3 & later */ 337 #define PCI_CTL_DIV_CORE_CLK_ENA BIT_31 /* Divide Core Clock Enable */ 338 #define PCI_CTL_SRESET_VMAIN_AV BIT_30 /* Soft Reset for Vmain_av De-Glitch */ 339 #define PCI_CTL_BYPASS_VMAIN_AV BIT_29 /* Bypass En. for Vmain_av De-Glitch */ 340 #define PCI_CTL_TIM_VMAIN_AV1 BIT_28 /* Bit 28..27: Timer Vmain_av Mask */ 341 #define PCI_CTL_TIM_VMAIN_AV0 BIT_27 /* Bit 28..27: Timer Vmain_av Mask */ 342 #define PCI_CTL_TIM_VMAIN_AV_MSK (BIT_28 | BIT_27) 343 /* Bit 26..16: Release Clock on Event */ 344 #define PCI_REL_PCIE_RST_DE_ASS BIT_26 /* PCIe Reset De-Asserted */ 345 #define PCI_REL_GPHY_REC_PACKET BIT_25 /* GPHY Received Packet */ 346 #define PCI_REL_INT_FIFO_N_EMPTY BIT_24 /* Internal FIFO Not Empty */ 347 #define PCI_REL_MAIN_PWR_AVAIL BIT_23 /* Main Power Available */ 348 #define PCI_REL_CLKRUN_REQ_REL BIT_22 /* CLKRUN Request Release */ 349 #define PCI_REL_PCIE_RESET_ASS BIT_21 /* PCIe Reset Asserted */ 350 #define PCI_REL_PME_ASSERTED BIT_20 /* PME Asserted */ 351 #define PCI_REL_PCIE_EXIT_L1_ST BIT_19 /* PCIe Exit L1 State */ 352 #define PCI_REL_LOADER_NOT_FIN BIT_18 /* EPROM Loader Not Finished */ 353 #define PCI_REL_PCIE_RX_EX_IDLE BIT_17 /* PCIe Rx Exit Electrical Idle State */ 354 #define PCI_REL_GPHY_LINK_UP BIT_16 /* GPHY Link Up */ 355 /* Bit 10.. 0: Mask for Gate Clock */ 356 #define PCI_GAT_PCIE_RST_ASSERTED BIT_10 /* PCIe Reset Asserted */ 357 #define PCI_GAT_GPHY_N_REC_PACKET BIT_9 /* GPHY Not Received Packet */ 358 #define PCI_GAT_INT_FIFO_EMPTY BIT_8 /* Internal FIFO Empty */ 359 #define PCI_GAT_MAIN_PWR_N_AVAIL BIT_7 /* Main Power Not Available */ 360 #define PCI_GAT_CLKRUN_REQ_REL BIT_6 /* CLKRUN Not Requested */ 361 #define PCI_GAT_PCIE_RESET_ASS BIT_5 /* PCIe Reset Asserted */ 362 #define PCI_GAT_PME_DE_ASSERTED BIT_4 /* PME De-Asserted */ 363 #define PCI_GAT_PCIE_ENTER_L1_ST BIT_3 /* PCIe Enter L1 State */ 364 #define PCI_GAT_LOADER_FINISHED BIT_2 /* EPROM Loader Finished */ 365 #define PCI_GAT_PCIE_RX_EL_IDLE BIT_1 /* PCIe Rx Electrical Idle State */ 366 #define PCI_GAT_GPHY_LINK_DOWN BIT_0 /* GPHY Link Down */ 367 368 /* PCI_CFG_REG_1 32 bit Config Register 1 */ 369 #define PCI_CF1_DIS_REL_EVT_RST BIT_24 /* Dis. Rel. Event during PCIE reset */ 370 /* Bit 23..21: Release Clock on Event */ 371 #define PCI_CF1_REL_LDR_NOT_FIN BIT_23 /* EEPROM Loader Not Finished */ 372 #define PCI_CF1_REL_VMAIN_AVLBL BIT_22 /* Vmain available */ 373 #define PCI_CF1_REL_PCIE_RESET BIT_21 /* PCI-E reset */ 374 /* Bit 20..18: Gate Clock on Event */ 375 #define PCI_CF1_GAT_LDR_NOT_FIN BIT_20 /* EEPROM Loader Finished */ 376 #define PCI_CF1_GAT_PCIE_RX_IDLE BIT_19 /* PCI-E Rx Electrical idle */ 377 #define PCI_CF1_GAT_PCIE_RESET BIT_18 /* PCI-E Reset */ 378 #define PCI_CF1_PRST_PHY_CLKREQ BIT_17 /* Enable PCI-E rst & PM2PHY gen. CLKREQ */ 379 #define PCI_CF1_PCIE_RST_CLKREQ BIT_16 /* Enable PCI-E rst generate CLKREQ */ 380 381 #define PCI_CF1_ENA_CFG_LDR_DONE BIT_8 /* Enable core level Config loader done */ 382 #define PCI_CF1_ENA_TXBMU_RD_IDLE BIT_1 /* Enable TX BMU Read IDLE for ASPM */ 383 #define PCI_CF1_ENA_TXBMU_WR_IDLE BIT_0 /* Enable TX BMU Write IDLE for ASPM */ 384 385 /* PEX_DEV_CTRL 16 bit PEX Device Control (Yukon-2) */ 386 #define PEX_DC_MAX_RRS_MSK (7<<12) /* Bit 14..12: Max. Read Request Size */ 387 #define PEX_DC_EN_NO_SNOOP BIT_11 /* Enable No Snoop */ 388 #define PEX_DC_EN_AUX_POW BIT_10 /* Enable AUX Power */ 389 #define PEX_DC_EN_PHANTOM BIT_9 /* Enable Phantom Functions */ 390 #define PEX_DC_EN_EXT_TAG BIT_8 /* Enable Extended Tag Field */ 391 #define PEX_DC_MAX_PLS_MSK (7<<5) /* Bit 7.. 5: Max. Payload Size Mask */ 392 #define PEX_DC_EN_REL_ORD BIT_4 /* Enable Relaxed Ordering */ 393 #define PEX_DC_EN_UNS_RQ_RP BIT_3 /* Enable Unsupported Request Reporting */ 394 #define PEX_DC_EN_FAT_ER_RP BIT_2 /* Enable Fatal Error Reporting */ 395 #define PEX_DC_EN_NFA_ER_RP BIT_1 /* Enable Non-Fatal Error Reporting */ 396 #define PEX_DC_EN_COR_ER_RP BIT_0 /* Enable Correctable Error Reporting */ 397 398 #define PEX_DC_MAX_RD_RQ_SIZE(x) (SHIFT12(x) & PEX_DC_MAX_RRS_MSK) 399 400 /* PEX_LNK_STAT 16 bit PEX Link Status (Yukon-2) */ 401 #define PEX_LS_SLOT_CLK_CFG BIT_12 /* Slot Clock Config */ 402 #define PEX_LS_LINK_TRAIN BIT_11 /* Link Training */ 403 #define PEX_LS_TRAIN_ERROR BIT_10 /* Training Error */ 404 #define PEX_LS_LINK_WI_MSK (0x3f<<4) /* Bit 9.. 4: Neg. Link Width Mask */ 405 #define PEX_LS_LINK_SP_MSK 0x0f /* Bit 3.. 0: Link Speed Mask */ 406 407 /* PEX_UNC_ERR_STAT PEX Uncorrectable Errors Status Register (Yukon-2) */ 408 #define PEX_UNSUP_REQ BIT_20 /* Unsupported Request Error */ 409 #define PEX_MALFOR_TLP BIT_18 /* Malformed TLP */ 410 #define PEX_RX_OV BIT_17 /* Receiver Overflow (not supported) */ 411 #define PEX_UNEXP_COMP BIT_16 /* Unexpected Completion */ 412 #define PEX_COMP_TO BIT_14 /* Completion Timeout */ 413 #define PEX_FLOW_CTRL_P BIT_13 /* Flow Control Protocol Error */ 414 #define PEX_POIS_TLP BIT_12 /* Poisoned TLP */ 415 #define PEX_DATA_LINK_P BIT_4 /* Data Link Protocol Error */ 416 417 #define PEX_FATAL_ERRORS (PEX_MALFOR_TLP | PEX_FLOW_CTRL_P | PEX_DATA_LINK_P) 418 419 /* Control Register File (Address Map) */ 420 421 /* 422 * Bank 0 423 */ 424 #define B0_RAP 0x0000 /* 8 bit Register Address Port */ 425 #define B0_CTST 0x0004 /* 16 bit Control/Status register */ 426 #define B0_LED 0x0006 /* 8 Bit LED register */ 427 #define B0_POWER_CTRL 0x0007 /* 8 Bit Power Control reg (YUKON only) */ 428 #define B0_ISRC 0x0008 /* 32 bit Interrupt Source Register */ 429 #define B0_IMSK 0x000c /* 32 bit Interrupt Mask Register */ 430 #define B0_HWE_ISRC 0x0010 /* 32 bit HW Error Interrupt Src Reg */ 431 #define B0_HWE_IMSK 0x0014 /* 32 bit HW Error Interrupt Mask Reg */ 432 #define B0_SP_ISRC 0x0018 /* 32 bit Special Interrupt Source Reg 1 */ 433 434 /* Special ISR registers (Yukon-2 only) */ 435 #define B0_Y2_SP_ISRC2 0x001c /* 32 bit Special Interrupt Source Reg 2 */ 436 #define B0_Y2_SP_ISRC3 0x0020 /* 32 bit Special Interrupt Source Reg 3 */ 437 #define B0_Y2_SP_EISR 0x0024 /* 32 bit Enter ISR Reg */ 438 #define B0_Y2_SP_LISR 0x0028 /* 32 bit Leave ISR Reg */ 439 #define B0_Y2_SP_ICR 0x002c /* 32 bit Interrupt Control Reg */ 440 441 /* 442 * Bank 1 443 * - completely empty (this is the RAP Block window) 444 * Note: if RAP = 1 this page is reserved 445 */ 446 447 /* 448 * Bank 2 449 */ 450 /* NA reg = 48 bit Network Address Register, 3x16 or 8x8 bit readable */ 451 #define B2_MAC_1 0x0100 /* NA reg MAC Address 1 */ 452 #define B2_MAC_2 0x0108 /* NA reg MAC Address 2 */ 453 #define B2_MAC_3 0x0110 /* NA reg MAC Address 3 */ 454 #define B2_CONN_TYP 0x0118 /* 8 bit Connector type */ 455 #define B2_PMD_TYP 0x0119 /* 8 bit PMD type */ 456 #define B2_MAC_CFG 0x011a /* 8 bit MAC Configuration / Chip Revision */ 457 #define B2_CHIP_ID 0x011b /* 8 bit Chip Identification Number */ 458 #define B2_E_0 0x011c /* 8 bit EPROM Byte 0 (ext. SRAM size */ 459 #define B2_Y2_CLK_GATE 0x011d /* 8 bit Clock Gating (Yukon-2) */ 460 #define B2_Y2_HW_RES 0x011e /* 8 bit HW Resources (Yukon-2) */ 461 #define B2_E_3 0x011f /* 8 bit EPROM Byte 3 */ 462 #define B2_Y2_CLK_CTRL 0x0120 /* 32 bit Core Clock Frequency Control */ 463 #define B2_TI_INI 0x0130 /* 32 bit Timer Init Value */ 464 #define B2_TI_VAL 0x0134 /* 32 bit Timer Value */ 465 #define B2_TI_CTRL 0x0138 /* 8 bit Timer Control */ 466 #define B2_TI_TEST 0x0139 /* 8 Bit Timer Test */ 467 #define B2_IRQM_INI 0x0140 /* 32 bit IRQ Moderation Timer Init Reg.*/ 468 #define B2_IRQM_VAL 0x0144 /* 32 bit IRQ Moderation Timer Value */ 469 #define B2_IRQM_CTRL 0x0148 /* 8 bit IRQ Moderation Timer Control */ 470 #define B2_IRQM_TEST 0x0149 /* 8 bit IRQ Moderation Timer Test */ 471 #define B2_IRQM_MSK 0x014c /* 32 bit IRQ Moderation Mask */ 472 #define B2_IRQM_HWE_MSK 0x0150 /* 32 bit IRQ Moderation HW Error Mask */ 473 #define B2_TST_CTRL1 0x0158 /* 8 bit Test Control Register 1 */ 474 #define B2_TST_CTRL2 0x0159 /* 8 bit Test Control Register 2 */ 475 #define B2_GP_IO 0x015c /* 32 bit General Purpose I/O Register */ 476 #define B2_I2C_CTRL 0x0160 /* 32 bit I2C HW Control Register */ 477 #define B2_I2C_DATA 0x0164 /* 32 bit I2C HW Data Register */ 478 #define B2_I2C_IRQ 0x0168 /* 32 bit I2C HW IRQ Register */ 479 #define B2_I2C_SW 0x016c /* 32 bit I2C SW Port Register */ 480 481 #define Y2_PEX_PHY_DATA 0x0170 /* 16 bit PEX PHY Data Register */ 482 #define Y2_PEX_PHY_ADDR 0x0172 /* 16 bit PEX PHY Address Register */ 483 484 /* 485 * Bank 3 486 */ 487 /* RAM Random Registers */ 488 #define B3_RAM_ADDR 0x0180 /* 32 bit RAM Address, to read or write */ 489 #define B3_RAM_DATA_LO 0x0184 /* 32 bit RAM Data Word (low dWord) */ 490 #define B3_RAM_DATA_HI 0x0188 /* 32 bit RAM Data Word (high dWord) */ 491 492 #define SELECT_RAM_BUFFER(rb, addr) (addr | (rb << 6)) /* Yukon-2 only */ 493 494 /* RAM Interface Registers */ 495 /* Yukon-2: use SELECT_RAM_BUFFER() to access the RAM buffer */ 496 /* 497 * The HW-Spec. calls this registers Timeout Value 0..11. But this names are 498 * not usable in SW. Please notice these are NOT real timeouts, these are 499 * the number of qWords transferred continuously. 500 */ 501 #define B3_RI_WTO_R1 0x0190 /* 8 bit WR Timeout Queue R1 (TO0) */ 502 #define B3_RI_WTO_XA1 0x0191 /* 8 bit WR Timeout Queue XA1 (TO1) */ 503 #define B3_RI_WTO_XS1 0x0192 /* 8 bit WR Timeout Queue XS1 (TO2) */ 504 #define B3_RI_RTO_R1 0x0193 /* 8 bit RD Timeout Queue R1 (TO3) */ 505 #define B3_RI_RTO_XA1 0x0194 /* 8 bit RD Timeout Queue XA1 (TO4) */ 506 #define B3_RI_RTO_XS1 0x0195 /* 8 bit RD Timeout Queue XS1 (TO5) */ 507 #define B3_RI_WTO_R2 0x0196 /* 8 bit WR Timeout Queue R2 (TO6) */ 508 #define B3_RI_WTO_XA2 0x0197 /* 8 bit WR Timeout Queue XA2 (TO7) */ 509 #define B3_RI_WTO_XS2 0x0198 /* 8 bit WR Timeout Queue XS2 (TO8) */ 510 #define B3_RI_RTO_R2 0x0199 /* 8 bit RD Timeout Queue R2 (TO9) */ 511 #define B3_RI_RTO_XA2 0x019a /* 8 bit RD Timeout Queue XA2 (TO10)*/ 512 #define B3_RI_RTO_XS2 0x019b /* 8 bit RD Timeout Queue XS2 (TO11)*/ 513 #define B3_RI_TO_VAL 0x019c /* 8 bit Current Timeout Count Val */ 514 #define B3_RI_CTRL 0x01a0 /* 16 bit RAM Interface Control Register */ 515 #define B3_RI_TEST 0x01a2 /* 8 bit RAM Interface Test Register */ 516 517 /* 518 * Bank 4 - 5 519 */ 520 /* Transmit Arbiter Registers MAC 1 and 2, use MR_ADDR() to access */ 521 #define TXA_ITI_INI 0x0200 /* 32 bit Tx Arb Interval Timer Init Val*/ 522 #define TXA_ITI_VAL 0x0204 /* 32 bit Tx Arb Interval Timer Value */ 523 #define TXA_LIM_INI 0x0208 /* 32 bit Tx Arb Limit Counter Init Val */ 524 #define TXA_LIM_VAL 0x020c /* 32 bit Tx Arb Limit Counter Value */ 525 #define TXA_CTRL 0x0210 /* 8 bit Tx Arbiter Control Register */ 526 #define TXA_TEST 0x0211 /* 8 bit Tx Arbiter Test Register */ 527 #define TXA_STAT 0x0212 /* 8 bit Tx Arbiter Status Register */ 528 529 #define MR_ADDR(Mac, Offs) (((Mac) << 7) + (Offs)) 530 531 /* RSS key registers for Yukon-2 Family */ 532 #define B4_RSS_KEY 0x0220 /* 4x32 bit RSS Key register (Yukon-2) */ 533 /* RSS key register offsets */ 534 #define KEY_IDX_0 0 /* offset for location of KEY 0 */ 535 #define KEY_IDX_1 4 /* offset for location of KEY 1 */ 536 #define KEY_IDX_2 8 /* offset for location of KEY 2 */ 537 #define KEY_IDX_3 12 /* offset for location of KEY 3 */ 538 /* 0x0280 - 0x0292: MAC 2 */ 539 #define RSS_KEY_ADDR(Port, KeyIndex) \ 540 ((B4_RSS_KEY | ( ((Port) == 0) ? 0 : 0x80)) + (KeyIndex)) 541 542 /* 543 * Bank 8 - 15 544 */ 545 /* Receive and Transmit Queue Registers, use Q_ADDR() to access */ 546 #define B8_Q_REGS 0x0400 547 548 /* Queue Register Offsets, use Q_ADDR() to access */ 549 #define Q_D 0x00 /* 8*32 bit Current Descriptor */ 550 #define Q_DA_L 0x20 /* 32 bit Current Descriptor Address Low dWord */ 551 #define Q_DONE 0x24 /* 16 bit Done Index */ 552 #define Q_AC_L 0x28 /* 32 bit Current Address Counter Low dWord */ 553 #define Q_AC_H 0x2c /* 32 bit Current Address Counter High dWord */ 554 #define Q_BC 0x30 /* 32 bit Current Byte Counter */ 555 #define Q_CSR 0x34 /* 32 bit BMU Control/Status Register */ 556 #define Q_F 0x38 /* 32 bit Flag Register */ 557 #define Q_T1 0x3c /* 32 bit Test Register 1 */ 558 #define Q_T1_TR 0x3c /* 8 bit Test Register 1 Transfer SM */ 559 #define Q_T1_WR 0x3d /* 8 bit Test Register 1 Write Descriptor SM */ 560 #define Q_T1_RD 0x3e /* 8 bit Test Register 1 Read Descriptor SM */ 561 #define Q_T1_SV 0x3f /* 8 bit Test Register 1 Supervisor SM */ 562 #define Q_WM 0x40 /* 16 bit FIFO Watermark */ 563 #define Q_AL 0x42 /* 8 bit FIFO Alignment */ 564 #define Q_RSP 0x44 /* 16 bit FIFO Read Shadow Pointer */ 565 #define Q_RSL 0x46 /* 8 bit FIFO Read Shadow Level */ 566 #define Q_RP 0x48 /* 8 bit FIFO Read Pointer */ 567 #define Q_RL 0x4a /* 8 bit FIFO Read Level */ 568 #define Q_WP 0x4c /* 8 bit FIFO Write Pointer */ 569 #define Q_WSP 0x4d /* 8 bit FIFO Write Shadow Pointer */ 570 #define Q_WL 0x4e /* 8 bit FIFO Write Level */ 571 #define Q_WSL 0x4f /* 8 bit FIFO Write Shadow Level */ 572 573 #define Q_ADDR(Queue, Offs) (B8_Q_REGS + (Queue) + (Offs)) 574 575 /* Queue Prefetch Unit Offsets, use Y2_PREF_Q_ADDR() to address */ 576 #define Y2_B8_PREF_REGS 0x0450 577 578 #define PREF_UNIT_CTRL_REG 0x00 /* 32 bit Prefetch Control register */ 579 #define PREF_UNIT_LAST_IDX_REG 0x04 /* 16 bit Last Index */ 580 #define PREF_UNIT_ADDR_LOW_REG 0x08 /* 32 bit List start addr, low part */ 581 #define PREF_UNIT_ADDR_HI_REG 0x0c /* 32 bit List start addr, high part*/ 582 #define PREF_UNIT_GET_IDX_REG 0x10 /* 16 bit Get Index */ 583 #define PREF_UNIT_PUT_IDX_REG 0x14 /* 16 bit Put Index */ 584 #define PREF_UNIT_FIFO_WP_REG 0x20 /* 8 bit FIFO write pointer */ 585 #define PREF_UNIT_FIFO_RP_REG 0x24 /* 8 bit FIFO read pointer */ 586 #define PREF_UNIT_FIFO_WM_REG 0x28 /* 8 bit FIFO watermark */ 587 #define PREF_UNIT_FIFO_LEV_REG 0x2c /* 8 bit FIFO level */ 588 589 #define PREF_UNIT_MASK_IDX 0x0fff 590 591 #define Y2_PREF_Q_ADDR(Queue, Offs) (Y2_B8_PREF_REGS + (Queue) + (Offs)) 592 593 /* 594 * Bank 16 - 23 595 */ 596 /* RAM Buffer Registers */ 597 #define B16_RAM_REGS 0x0800 598 599 /* RAM Buffer Register Offsets, use RB_ADDR() to access */ 600 #define RB_START 0x00 /* 32 bit RAM Buffer Start Address */ 601 #define RB_END 0x04 /* 32 bit RAM Buffer End Address */ 602 #define RB_WP 0x08 /* 32 bit RAM Buffer Write Pointer */ 603 #define RB_RP 0x0c /* 32 bit RAM Buffer Read Pointer */ 604 #define RB_RX_UTPP 0x10 /* 32 bit Rx Upper Threshold, Pause Packet */ 605 #define RB_RX_LTPP 0x14 /* 32 bit Rx Lower Threshold, Pause Packet */ 606 #define RB_RX_UTHP 0x18 /* 32 bit Rx Upper Threshold, High Prio */ 607 #define RB_RX_LTHP 0x1c /* 32 bit Rx Lower Threshold, High Prio */ 608 #define RB_PC 0x20 /* 32 bit RAM Buffer Packet Counter */ 609 #define RB_LEV 0x24 /* 32 bit RAM Buffer Level Register */ 610 #define RB_CTRL 0x28 /* 8 bit RAM Buffer Control Register */ 611 #define RB_TST1 0x29 /* 8 bit RAM Buffer Test Register 1 */ 612 #define RB_TST2 0x2a /* 8 bit RAM Buffer Test Register 2 */ 613 614 /* 615 * Bank 24 616 */ 617 /* Receive GMAC FIFO (YUKON and Yukon-2), use MR_ADDR() to access */ 618 #define RX_GMF_EA 0x0c40 /* 32 bit Rx GMAC FIFO End Address */ 619 #define RX_GMF_AF_THR 0x0c44 /* 32 bit Rx GMAC FIFO Almost Full Thresh. */ 620 #define RX_GMF_CTRL_T 0x0c48 /* 32 bit Rx GMAC FIFO Control/Test */ 621 #define RX_GMF_FL_MSK 0x0c4c /* 32 bit Rx GMAC FIFO Flush Mask */ 622 #define RX_GMF_FL_THR 0x0c50 /* 32 bit Rx GMAC FIFO Flush Threshold */ 623 #define RX_GMF_TR_THR 0x0c54 /* 32 bit Rx Truncation Threshold (Yukon-2) */ 624 #define RX_GMF_UP_THR 0x0c58 /* 8 bit Rx Upper Pause Thr (Yukon-EC_U) */ 625 #define RX_GMF_LP_THR 0x0c5a /* 8 bit Rx Lower Pause Thr (Yukon-EC_U) */ 626 #define RX_GMF_VLAN 0x0c5c /* 32 bit Rx VLAN Type Register (Yukon-2) */ 627 #define RX_GMF_WP 0x0c60 /* 32 bit Rx GMAC FIFO Write Pointer */ 628 #define RX_GMF_WLEV 0x0c68 /* 32 bit Rx GMAC FIFO Write Level */ 629 #define RX_GMF_RP 0x0c70 /* 32 bit Rx GMAC FIFO Read Pointer */ 630 #define RX_GMF_RLEV 0x0c78 /* 32 bit Rx GMAC FIFO Read Level */ 631 632 /* 633 * Bank 25 634 */ 635 /* 0x0c80 - 0x0cbf: MAC 2 */ 636 /* 0x0cc0 - 0x0cff: reserved */ 637 638 /* 639 * Bank 26 640 */ 641 /* Transmit GMAC FIFO (YUKON and Yukon-2), use MR_ADDR() to access */ 642 #define TX_GMF_EA 0x0d40 /* 32 bit Tx GMAC FIFO End Address */ 643 #define TX_GMF_AE_THR 0x0d44 /* 32 bit Tx GMAC FIFO Almost Empty Thresh.*/ 644 #define TX_GMF_CTRL_T 0x0d48 /* 32 bit Tx GMAC FIFO Control/Test */ 645 #define TX_GMF_VLAN 0x0d5c /* 32 bit Tx VLAN Type Register (Yukon-2) */ 646 #define TX_GMF_WP 0x0d60 /* 32 bit Tx GMAC FIFO Write Pointer */ 647 #define TX_GMF_WSP 0x0d64 /* 32 bit Tx GMAC FIFO Write Shadow Pointer */ 648 #define TX_GMF_WLEV 0x0d68 /* 32 bit Tx GMAC FIFO Write Level */ 649 #define TX_GMF_RP 0x0d70 /* 32 bit Tx GMAC FIFO Read Pointer */ 650 #define TX_GMF_RSTP 0x0d74 /* 32 bit Tx GMAC FIFO Restart Pointer */ 651 #define TX_GMF_RLEV 0x0d78 /* 32 bit Tx GMAC FIFO Read Level */ 652 653 /* 654 * Bank 27 655 */ 656 /* 0x0d80 - 0x0dbf: MAC 2 */ 657 /* 0x0daa - 0x0dff: reserved */ 658 659 /* 660 * Bank 28 661 */ 662 /* Descriptor Poll Timer Registers */ 663 #define B28_DPT_INI 0x0e00 /* 24 bit Descriptor Poll Timer Init Val */ 664 #define B28_DPT_VAL 0x0e04 /* 24 bit Descriptor Poll Timer Curr Val */ 665 #define B28_DPT_CTRL 0x0e08 /* 8 bit Descriptor Poll Timer Ctrl Reg */ 666 #define B28_DPT_TST 0x0e0a /* 8 bit Descriptor Poll Timer Test Reg */ 667 /* Time Stamp Timer Registers (YUKON only) */ 668 #define GMAC_TI_ST_VAL 0x0e14 /* 32 bit Time Stamp Timer Curr Val */ 669 #define GMAC_TI_ST_CTRL 0x0e18 /* 8 bit Time Stamp Timer Ctrl Reg */ 670 #define GMAC_TI_ST_TST 0x0e1a /* 8 bit Time Stamp Timer Test Reg */ 671 /* Polling Unit Registers (Yukon-2 only) */ 672 #define POLL_CTRL 0x0e20 /* 32 bit Polling Unit Control Reg */ 673 #define POLL_LAST_IDX 0x0e24 /* 16 bit Polling Unit List Last Index */ 674 #define POLL_LIST_ADDR_LO 0x0e28 /* 32 bit Poll. List Start Addr (low) */ 675 #define POLL_LIST_ADDR_HI 0x0e2c /* 32 bit Poll. List Start Addr (high) */ 676 /* ASF Subsystem Registers (Yukon-2 only) */ 677 #define B28_Y2_SMB_CONFIG 0x0e40 /* 32 bit ASF SMBus Config Register */ 678 #define B28_Y2_SMB_CSD_REG 0x0e44 /* 32 bit ASF SMB Control/Status/Data */ 679 #define B28_Y2_ASF_IRQ_V_BASE 0x0e60 /* 32 bit ASF IRQ Vector Base */ 680 #define B28_Y2_ASF_STAT_CMD 0x0e68 /* 32 bit ASF Status and Command Reg */ 681 #define B28_Y2_ASF_HCU_CCSR 0x0e68 /* 32 bit ASF HCU CCSR (Yukon EX) */ 682 #define B28_Y2_ASF_HOST_COM 0x0e6c /* 32 bit ASF Host Communication Reg */ 683 #define B28_Y2_DATA_REG_1 0x0e70 /* 32 bit ASF/Host Data Register 1 */ 684 #define B28_Y2_DATA_REG_2 0x0e74 /* 32 bit ASF/Host Data Register 2 */ 685 #define B28_Y2_DATA_REG_3 0x0e78 /* 32 bit ASF/Host Data Register 3 */ 686 #define B28_Y2_DATA_REG_4 0x0e7c /* 32 bit ASF/Host Data Register 4 */ 687 688 /* 689 * Bank 29 690 */ 691 692 /* Status BMU Registers (Yukon-2 only)*/ 693 #define STAT_CTRL 0x0e80 /* 32 bit Status BMU Control Reg */ 694 #define STAT_LAST_IDX 0x0e84 /* 16 bit Status BMU Last Index */ 695 #define STAT_LIST_ADDR_LO 0x0e88 /* 32 bit Status List Start Addr (low) */ 696 #define STAT_LIST_ADDR_HI 0x0e8c /* 32 bit Status List Start Addr (high) */ 697 #define STAT_TXA1_RIDX 0x0e90 /* 16 bit Status TxA1 Report Index Reg */ 698 #define STAT_TXS1_RIDX 0x0e92 /* 16 bit Status TxS1 Report Index Reg */ 699 #define STAT_TXA2_RIDX 0x0e94 /* 16 bit Status TxA2 Report Index Reg */ 700 #define STAT_TXS2_RIDX 0x0e96 /* 16 bit Status TxS2 Report Index Reg */ 701 #define STAT_TX_IDX_TH 0x0e98 /* 16 bit Status Tx Index Threshold Reg */ 702 #define STAT_PUT_IDX 0x0e9c /* 16 bit Status Put Index Reg */ 703 /* FIFO Control/Status Registers (Yukon-2 only)*/ 704 #define STAT_FIFO_WP 0x0ea0 /* 8 bit Status FIFO Write Pointer Reg */ 705 #define STAT_FIFO_RP 0x0ea4 /* 8 bit Status FIFO Read Pointer Reg */ 706 #define STAT_FIFO_RSP 0x0ea6 /* 8 bit Status FIFO Read Shadow Ptr */ 707 #define STAT_FIFO_LEVEL 0x0ea8 /* 8 bit Status FIFO Level Reg */ 708 #define STAT_FIFO_SHLVL 0x0eaa /* 8 bit Status FIFO Shadow Level Reg */ 709 #define STAT_FIFO_WM 0x0eac /* 8 bit Status FIFO Watermark Reg */ 710 #define STAT_FIFO_ISR_WM 0x0ead /* 8 bit Status FIFO ISR Watermark Reg */ 711 /* Level and ISR Timer Registers (Yukon-2 only)*/ 712 #define STAT_LEV_TIMER_INI 0x0eb0 /* 32 bit Level Timer Init. Value Reg */ 713 #define STAT_LEV_TIMER_CNT 0x0eb4 /* 32 bit Level Timer Counter Reg */ 714 #define STAT_LEV_TIMER_CTRL 0x0eb8 /* 8 bit Level Timer Control Reg */ 715 #define STAT_LEV_TIMER_TEST 0x0eb9 /* 8 bit Level Timer Test Reg */ 716 #define STAT_TX_TIMER_INI 0x0ec0 /* 32 bit Tx Timer Init. Value Reg */ 717 #define STAT_TX_TIMER_CNT 0x0ec4 /* 32 bit Tx Timer Counter Reg */ 718 #define STAT_TX_TIMER_CTRL 0x0ec8 /* 8 bit Tx Timer Control Reg */ 719 #define STAT_TX_TIMER_TEST 0x0ec9 /* 8 bit Tx Timer Test Reg */ 720 #define STAT_ISR_TIMER_INI 0x0ed0 /* 32 bit ISR Timer Init. Value Reg */ 721 #define STAT_ISR_TIMER_CNT 0x0ed4 /* 32 bit ISR Timer Counter Reg */ 722 #define STAT_ISR_TIMER_CTRL 0x0ed8 /* 8 bit ISR Timer Control Reg */ 723 #define STAT_ISR_TIMER_TEST 0x0ed9 /* 8 bit ISR Timer Test Reg */ 724 725 #define ST_LAST_IDX_MASK 0x007f /* Last Index Mask */ 726 #define ST_TXRP_IDX_MASK 0x0fff /* Tx Report Index Mask */ 727 #define ST_TXTH_IDX_MASK 0x0fff /* Tx Threshold Index Mask */ 728 #define ST_WM_IDX_MASK 0x3f /* FIFO Watermark Index Mask */ 729 730 /* 731 * Bank 30 732 */ 733 /* GMAC and GPHY Control Registers (YUKON only) */ 734 #define GMAC_CTRL 0x0f00 /* 32 bit GMAC Control Reg */ 735 #define GPHY_CTRL 0x0f04 /* 32 bit GPHY Control Reg */ 736 #define GMAC_IRQ_SRC 0x0f08 /* 8 bit GMAC Interrupt Source Reg */ 737 #define GMAC_IRQ_MSK 0x0f0c /* 8 bit GMAC Interrupt Mask Reg */ 738 #define GMAC_LINK_CTRL 0x0f10 /* 16 bit Link Control Reg */ 739 740 /* Wake-up Frame Pattern Match Control Registers (YUKON only) */ 741 742 #define WOL_REG_OFFS 0x20 /* HW-Bug: Address is + 0x20 against spec. */ 743 744 #define WOL_CTRL_STAT 0x0f20 /* 16 bit WOL Control/Status Reg */ 745 #define WOL_MATCH_CTL 0x0f22 /* 8 bit WOL Match Control Reg */ 746 #define WOL_MATCH_RES 0x0f23 /* 8 bit WOL Match Result Reg */ 747 #define WOL_MAC_ADDR_LO 0x0f24 /* 32 bit WOL MAC Address Low */ 748 #define WOL_MAC_ADDR_HI 0x0f28 /* 16 bit WOL MAC Address High */ 749 #define WOL_PATT_PME 0x0f2a /* 8 bit WOL PME Match Enable (Yukon-2) */ 750 #define WOL_PATT_ASFM 0x0f2b /* 8 bit WOL ASF Match Enable (Yukon-2) */ 751 #define WOL_PATT_RPTR 0x0f2c /* 8 bit WOL Pattern Read Pointer */ 752 753 /* WOL Pattern Length Registers (YUKON only) */ 754 755 #define WOL_PATT_LEN_LO 0x0f30 /* 32 bit WOL Pattern Length 3..0 */ 756 #define WOL_PATT_LEN_HI 0x0f34 /* 24 bit WOL Pattern Length 6..4 */ 757 758 /* WOL Pattern Counter Registers (YUKON only) */ 759 760 #define WOL_PATT_CNT_0 0x0f38 /* 32 bit WOL Pattern Counter 3..0 */ 761 #define WOL_PATT_CNT_4 0x0f3c /* 24 bit WOL Pattern Counter 6..4 */ 762 763 /* 764 * Bank 32 - 33 765 */ 766 #define WOL_PATT_RAM_1 0x1000 /* WOL Pattern RAM Link 1 */ 767 #define WOL_PATT_RAM_2 0x1400 /* WOL Pattern RAM Link 2 */ 768 769 /* offset to configuration space on Yukon-2 */ 770 #define Y2_CFG_SPC 0x1c00 771 #define BASE_GMAC_1 0x2800 /* GMAC 1 registers */ 772 #define BASE_GMAC_2 0x3800 /* GMAC 2 registers */ 773 774 /* 775 * Control Register Bit Definitions: 776 */ 777 /* B0_CTST 24 bit Control/Status register */ 778 #define Y2_VMAIN_AVAIL BIT_17 /* VMAIN available (YUKON-2 only) */ 779 #define Y2_VAUX_AVAIL BIT_16 /* VAUX available (YUKON-2 only) */ 780 #define Y2_HW_WOL_ON BIT_15 /* HW WOL On (Yukon-EC Ultra A1 only) */ 781 #define Y2_HW_WOL_OFF BIT_14 /* HW WOL Off (Yukon-EC Ultra A1 only) */ 782 #define Y2_ASF_ENABLE BIT_13 /* ASF Unit Enable (YUKON-2 only) */ 783 #define Y2_ASF_DISABLE BIT_12 /* ASF Unit Disable (YUKON-2 only) */ 784 #define Y2_CLK_RUN_ENA BIT_11 /* CLK_RUN Enable (YUKON-2 only) */ 785 #define Y2_CLK_RUN_DIS BIT_10 /* CLK_RUN Disable (YUKON-2 only) */ 786 #define Y2_LED_STAT_ON BIT_9 /* Status LED On (YUKON-2 only) */ 787 #define Y2_LED_STAT_OFF BIT_8 /* Status LED Off (YUKON-2 only) */ 788 #define CS_ST_SW_IRQ BIT_7 /* Set IRQ SW Request */ 789 #define CS_CL_SW_IRQ BIT_6 /* Clear IRQ SW Request */ 790 #define CS_STOP_DONE BIT_5 /* Stop Master is finished */ 791 #define CS_STOP_MAST BIT_4 /* Command Bit to stop the master */ 792 #define CS_MRST_CLR BIT_3 /* Clear Master Reset */ 793 #define CS_MRST_SET BIT_2 /* Set Master Reset */ 794 #define CS_RST_CLR BIT_1 /* Clear Software Reset */ 795 #define CS_RST_SET BIT_0 /* Set Software Reset */ 796 797 #define LED_STAT_ON BIT_1 /* Status LED On */ 798 #define LED_STAT_OFF BIT_0 /* Status LED Off */ 799 800 /* B0_POWER_CTRL 8 Bit Power Control reg (YUKON only) */ 801 #define PC_VAUX_ENA BIT_7 /* Switch VAUX Enable */ 802 #define PC_VAUX_DIS BIT_6 /* Switch VAUX Disable */ 803 #define PC_VCC_ENA BIT_5 /* Switch VCC Enable */ 804 #define PC_VCC_DIS BIT_4 /* Switch VCC Disable */ 805 #define PC_VAUX_ON BIT_3 /* Switch VAUX On */ 806 #define PC_VAUX_OFF BIT_2 /* Switch VAUX Off */ 807 #define PC_VCC_ON BIT_1 /* Switch VCC On */ 808 #define PC_VCC_OFF BIT_0 /* Switch VCC Off */ 809 810 /* B0_ISRC 32 bit Interrupt Source Register */ 811 /* B0_IMSK 32 bit Interrupt Mask Register */ 812 /* B0_SP_ISRC 32 bit Special Interrupt Source Reg */ 813 /* B2_IRQM_MSK 32 bit IRQ Moderation Mask */ 814 /* B0_Y2_SP_ISRC2 32 bit Special Interrupt Source Reg 2 */ 815 /* B0_Y2_SP_ISRC3 32 bit Special Interrupt Source Reg 3 */ 816 /* B0_Y2_SP_EISR 32 bit Enter ISR Reg */ 817 /* B0_Y2_SP_LISR 32 bit Leave ISR Reg */ 818 #define Y2_IS_PORT_MASK(Port, Mask) ((Mask) << (Port*8)) 819 #define Y2_IS_HW_ERR BIT_31 /* Interrupt HW Error */ 820 #define Y2_IS_STAT_BMU BIT_30 /* Status BMU Interrupt */ 821 #define Y2_IS_ASF BIT_29 /* ASF subsystem Interrupt */ 822 #define Y2_IS_POLL_CHK BIT_27 /* Check IRQ from polling unit */ 823 #define Y2_IS_TWSI_RDY BIT_26 /* IRQ on end of TWSI Tx */ 824 #define Y2_IS_IRQ_SW BIT_25 /* SW forced IRQ */ 825 #define Y2_IS_TIMINT BIT_24 /* IRQ from Timer */ 826 #define Y2_IS_IRQ_PHY2 BIT_12 /* Interrupt from PHY 2 */ 827 #define Y2_IS_IRQ_MAC2 BIT_11 /* Interrupt from MAC 2 */ 828 #define Y2_IS_CHK_RX2 BIT_10 /* Descriptor error Rx 2 */ 829 #define Y2_IS_CHK_TXS2 BIT_9 /* Descriptor error TXS 2 */ 830 #define Y2_IS_CHK_TXA2 BIT_8 /* Descriptor error TXA 2 */ 831 #define Y2_IS_IRQ_PHY1 BIT_4 /* Interrupt from PHY 1 */ 832 #define Y2_IS_IRQ_MAC1 BIT_3 /* Interrupt from MAC 1 */ 833 #define Y2_IS_CHK_RX1 BIT_2 /* Descriptor error Rx 1 */ 834 #define Y2_IS_CHK_TXS1 BIT_1 /* Descriptor error TXS 1 */ 835 #define Y2_IS_CHK_TXA1 BIT_0 /* Descriptor error TXA 1 */ 836 837 #define Y2_IS_L1_MASK 0x0000001f /* IRQ Mask for port 1 */ 838 839 #define Y2_IS_L2_MASK 0x00001f00 /* IRQ Mask for port 2 */ 840 841 #define Y2_IS_ALL_MSK 0xef001f1f /* All Interrupt bits */ 842 843 #define Y2_IS_PORT_A \ 844 (Y2_IS_IRQ_PHY1 | Y2_IS_IRQ_MAC1 | Y2_IS_CHK_TXA1 | Y2_IS_CHK_RX1) 845 #define Y2_IS_PORT_B \ 846 (Y2_IS_IRQ_PHY2 | Y2_IS_IRQ_MAC2 | Y2_IS_CHK_TXA2 | Y2_IS_CHK_RX2) 847 848 /* B0_HWE_ISRC 32 bit HW Error Interrupt Src Reg */ 849 /* B0_HWE_IMSK 32 bit HW Error Interrupt Mask Reg */ 850 /* B2_IRQM_HWE_MSK 32 bit IRQ Moderation HW Error Mask */ 851 #define Y2_IS_TIST_OV BIT_29 /* Time Stamp Timer overflow interrupt */ 852 #define Y2_IS_SENSOR BIT_28 /* Sensor interrupt */ 853 #define Y2_IS_MST_ERR BIT_27 /* Master error interrupt */ 854 #define Y2_IS_IRQ_STAT BIT_26 /* Status exception interrupt */ 855 #define Y2_IS_PCI_EXP BIT_25 /* PCI-Express interrupt */ 856 #define Y2_IS_PCI_NEXP BIT_24 /* PCI-Express error similar to PCI error */ 857 #define Y2_IS_PAR_RD2 BIT_13 /* Read RAM parity error interrupt */ 858 #define Y2_IS_PAR_WR2 BIT_12 /* Write RAM parity error interrupt */ 859 #define Y2_IS_PAR_MAC2 BIT_11 /* MAC hardware fault interrupt */ 860 #define Y2_IS_PAR_RX2 BIT_10 /* Parity Error Rx Queue 2 */ 861 #define Y2_IS_TCP_TXS2 BIT_9 /* TCP length mismatch sync Tx queue IRQ */ 862 #define Y2_IS_TCP_TXA2 BIT_8 /* TCP length mismatch async Tx queue IRQ */ 863 #define Y2_IS_PAR_RD1 BIT_5 /* Read RAM parity error interrupt */ 864 #define Y2_IS_PAR_WR1 BIT_4 /* Write RAM parity error interrupt */ 865 #define Y2_IS_PAR_MAC1 BIT_3 /* MAC hardware fault interrupt */ 866 #define Y2_IS_PAR_RX1 BIT_2 /* Parity Error Rx Queue 1 */ 867 #define Y2_IS_TCP_TXS1 BIT_1 /* TCP length mismatch sync Tx queue IRQ */ 868 #define Y2_IS_TCP_TXA1 BIT_0 /* TCP length mismatch async Tx queue IRQ */ 869 870 #define Y2_HWE_L1_MASK (Y2_IS_PAR_RD1 | Y2_IS_PAR_WR1 | Y2_IS_PAR_MAC1 |\ 871 Y2_IS_PAR_RX1 | Y2_IS_TCP_TXS1| Y2_IS_TCP_TXA1) 872 #define Y2_HWE_L2_MASK (Y2_IS_PAR_RD2 | Y2_IS_PAR_WR2 | Y2_IS_PAR_MAC2 |\ 873 Y2_IS_PAR_RX2 | Y2_IS_TCP_TXS2| Y2_IS_TCP_TXA2) 874 875 #define Y2_HWE_ALL_MSK (Y2_IS_TIST_OV | /* Y2_IS_SENSOR | */ Y2_IS_MST_ERR |\ 876 Y2_IS_IRQ_STAT | Y2_IS_PCI_EXP | Y2_IS_PCI_NEXP |\ 877 Y2_HWE_L1_MASK | Y2_HWE_L2_MASK) 878 879 /* B2_MAC_CFG 8 bit MAC Configuration / Chip Revision */ 880 #define CFG_CHIP_R_MSK (0x0f<<4) /* Bit 7.. 4: Chip Revision */ 881 #define CFG_DIS_M2_CLK BIT_1 /* Disable Clock for 2nd MAC */ 882 #define CFG_SNG_MAC BIT_0 /* MAC Config: 0 = 2 MACs; 1 = 1 MAC */ 883 884 /* B2_CHIP_ID 8 bit Chip Identification Number */ 885 #define CHIP_ID_GENESIS 0x0a /* Chip ID for GENESIS */ 886 #define CHIP_ID_YUKON 0xb0 /* Chip ID for YUKON */ 887 #define CHIP_ID_YUKON_LITE 0xb1 /* Chip ID for YUKON-Lite (Rev. A1-A3) */ 888 #define CHIP_ID_YUKON_LP 0xb2 /* Chip ID for YUKON-LP */ 889 #define CHIP_ID_YUKON_XL 0xb3 /* Chip ID for YUKON-2 XL */ 890 #define CHIP_ID_YUKON_EC_U 0xb4 /* Chip ID for YUKON-2 EC Ultra */ 891 #define CHIP_ID_YUKON_EX 0xb5 /* Chip ID for YUKON-2 Extreme */ 892 #define CHIP_ID_YUKON_EC 0xb6 /* Chip ID for YUKON-2 EC */ 893 #define CHIP_ID_YUKON_FE 0xb7 /* Chip ID for YUKON-2 FE */ 894 #define CHIP_ID_YUKON_FE_P 0xb8 /* Chip ID for YUKON-2 FE+ */ 895 #define CHIP_ID_YUKON_SUPR 0xb9 /* Chip ID for YUKON-2 Supreme */ 896 #define CHIP_ID_YUKON_UL_2 0xba /* Chip ID for YUKON-2 Ultra 2 */ 897 898 #define CHIP_REV_YU_XL_A0 0 /* Chip Rev. for Yukon-2 A0 */ 899 #define CHIP_REV_YU_XL_A1 1 /* Chip Rev. for Yukon-2 A1 */ 900 #define CHIP_REV_YU_XL_A2 2 /* Chip Rev. for Yukon-2 A2 */ 901 #define CHIP_REV_YU_XL_A3 3 /* Chip Rev. for Yukon-2 A3 */ 902 903 #define CHIP_REV_YU_EC_A1 0 /* Chip Rev. for Yukon-EC A1/A0 */ 904 #define CHIP_REV_YU_EC_A2 1 /* Chip Rev. for Yukon-EC A2 */ 905 #define CHIP_REV_YU_EC_A3 2 /* Chip Rev. for Yukon-EC A3 */ 906 907 #define CHIP_REV_YU_EC_U_A0 1 908 #define CHIP_REV_YU_EC_U_A1 2 909 910 #define CHIP_REV_YU_FE_P_A0 0 /* Chip Rev. for Yukon-2 FE+ A0 */ 911 912 #define CHIP_REV_YU_EX_A0 1 /* Chip Rev. for Yukon-2 EX A0 */ 913 #define CHIP_REV_YU_EX_B0 2 /* Chip Rev. for Yukon-2 EX B0 */ 914 915 /* B2_Y2_CLK_GATE 8 bit Clock Gating (Yukon-2 only) */ 916 #define Y2_STATUS_LNK2_INAC BIT_7 /* Status Link 2 inactiv (0 = activ) */ 917 #define Y2_CLK_GAT_LNK2_DIS BIT_6 /* Disable clock gating Link 2 */ 918 #define Y2_COR_CLK_LNK2_DIS BIT_5 /* Disable Core clock Link 2 */ 919 #define Y2_PCI_CLK_LNK2_DIS BIT_4 /* Disable PCI clock Link 2 */ 920 #define Y2_STATUS_LNK1_INAC BIT_3 /* Status Link 1 inactiv (0 = activ) */ 921 #define Y2_CLK_GAT_LNK1_DIS BIT_2 /* Disable clock gating Link 1 */ 922 #define Y2_COR_CLK_LNK1_DIS BIT_1 /* Disable Core clock Link 1 */ 923 #define Y2_PCI_CLK_LNK1_DIS BIT_0 /* Disable PCI clock Link 1 */ 924 925 /* B2_Y2_HW_RES 8 bit HW Resources (Yukon-2 only) */ 926 #define CFG_LED_MODE_MSK (0x07<<2) /* Bit 4.. 2: LED Mode Mask */ 927 #define CFG_LINK_2_AVAIL BIT_1 /* Link 2 available */ 928 #define CFG_LINK_1_AVAIL BIT_0 /* Link 1 available */ 929 930 #define CFG_LED_MODE(x) (((x) & CFG_LED_MODE_MSK) >> 2) 931 #define CFG_DUAL_MAC_MSK (CFG_LINK_2_AVAIL | CFG_LINK_1_AVAIL) 932 933 /* B2_E_3 8 bit lower 4 bits used for HW self test result */ 934 #define B2_E3_RES_MASK 0x0f 935 936 /* B2_Y2_CLK_CTRL 32 bit Core Clock Frequency Control Register (Yukon-2/EC) */ 937 /* Yukon-EC/FE */ 938 #define Y2_CLK_DIV_VAL_MSK (0xff<<16) /* Bit 23..16: Clock Divisor Value */ 939 #define Y2_CLK_DIV_VAL(x) (SHIFT16(x) & Y2_CLK_DIV_VAL_MSK) 940 /* Yukon-2 */ 941 #define Y2_CLK_DIV_VAL2_MSK (0x07<<21) /* Bit 23..21: Clock Divisor Value */ 942 #define Y2_CLK_SELECT2_MSK (0x1f<<16) /* Bit 20..16: Clock Select */ 943 #define Y2_CLK_DIV_VAL_2(x) (SHIFT21(x) & Y2_CLK_DIV_VAL2_MSK) 944 #define Y2_CLK_SEL_VAL_2(x) (SHIFT16(x) & Y2_CLK_SELECT2_MSK) 945 #define Y2_CLK_DIV_ENA BIT_1 /* Enable Core Clock Division */ 946 #define Y2_CLK_DIV_DIS BIT_0 /* Disable Core Clock Division */ 947 948 /* B2_TI_CTRL 8 bit Timer control */ 949 /* B2_IRQM_CTRL 8 bit IRQ Moderation Timer Control */ 950 #define TIM_START BIT_2 /* Start Timer */ 951 #define TIM_STOP BIT_1 /* Stop Timer */ 952 #define TIM_CLR_IRQ BIT_0 /* Clear Timer IRQ (!IRQM) */ 953 954 /* B2_TI_TEST 8 Bit Timer Test */ 955 /* B2_IRQM_TEST 8 bit IRQ Moderation Timer Test */ 956 /* B28_DPT_TST 8 bit Descriptor Poll Timer Test Reg */ 957 #define TIM_T_ON BIT_2 /* Test mode on */ 958 #define TIM_T_OFF BIT_1 /* Test mode off */ 959 #define TIM_T_STEP BIT_0 /* Test step */ 960 961 /* B28_DPT_INI 32 bit Descriptor Poll Timer Init Val */ 962 /* B28_DPT_VAL 32 bit Descriptor Poll Timer Curr Val */ 963 #define DPT_MSK 0x00ffffff /* Bit 23.. 0: Desc Poll Timer Bits */ 964 965 /* B28_DPT_CTRL 8 bit Descriptor Poll Timer Ctrl Reg */ 966 #define DPT_START BIT_1 /* Start Descriptor Poll Timer */ 967 #define DPT_STOP BIT_0 /* Stop Descriptor Poll Timer */ 968 969 /* B2_TST_CTRL1 8 bit Test Control Register 1 */ 970 #define TST_FRC_DPERR_MR BIT_7 /* force DATAPERR on MST RD */ 971 #define TST_FRC_DPERR_MW BIT_6 /* force DATAPERR on MST WR */ 972 #define TST_FRC_DPERR_TR BIT_5 /* force DATAPERR on TRG RD */ 973 #define TST_FRC_DPERR_TW BIT_4 /* force DATAPERR on TRG WR */ 974 #define TST_FRC_APERR_M BIT_3 /* force ADDRPERR on MST */ 975 #define TST_FRC_APERR_T BIT_2 /* force ADDRPERR on TRG */ 976 #define TST_CFG_WRITE_ON BIT_1 /* Enable Config Reg WR */ 977 #define TST_CFG_WRITE_OFF BIT_0 /* Disable Config Reg WR */ 978 979 /* B2_GP_IO */ 980 #define GLB_GPIO_CLK_DEB_ENA BIT_31 /* Clock Debug Enable */ 981 #define GLB_GPIO_CLK_DBG_MSK 0x3c000000 /* Clock Debug */ 982 983 #define GLB_GPIO_INT_RST_D3_DIS BIT_15 /* Disable Internal Reset After D3 to D0 */ 984 #define GLB_GPIO_LED_PAD_SPEED_UP BIT_14 /* LED PAD Speed Up */ 985 #define GLB_GPIO_STAT_RACE_DIS BIT_13 /* Status Race Disable */ 986 #define GLB_GPIO_TEST_SEL_MSK 0x00001800 /* Testmode Select */ 987 #define GLB_GPIO_TEST_SEL_BASE BIT_11 988 #define GLB_GPIO_RAND_ENA BIT_10 /* Random Enable */ 989 #define GLB_GPIO_RAND_BIT_1 BIT_9 /* Random Bit 1 */ 990 991 /* B2_I2C_CTRL 32 bit I2C HW Control Register */ 992 #define I2C_FLAG BIT_31 /* Start read/write if WR */ 993 #define I2C_ADDR (0x7fff<<16) /* Bit 30..16: Addr to be RD/WR */ 994 #define I2C_DEV_SEL (0x7f<<9) /* Bit 15.. 9: I2C Device Select */ 995 #define I2C_BURST_LEN BIT_4 /* Burst Len, 1/4 bytes */ 996 #define I2C_DEV_SIZE (7<<1) /* Bit 3.. 1: I2C Device Size */ 997 #define I2C_025K_DEV (0<<1) /* 0: 256 Bytes or smal. */ 998 #define I2C_05K_DEV (1<<1) /* 1: 512 Bytes */ 999 #define I2C_1K_DEV (2<<1) /* 2: 1024 Bytes */ 1000 #define I2C_2K_DEV (3<<1) /* 3: 2048 Bytes */ 1001 #define I2C_4K_DEV (4<<1) /* 4: 4096 Bytes */ 1002 #define I2C_8K_DEV (5<<1) /* 5: 8192 Bytes */ 1003 #define I2C_16K_DEV (6<<1) /* 6: 16384 Bytes */ 1004 #define I2C_32K_DEV (7<<1) /* 7: 32768 Bytes */ 1005 #define I2C_STOP BIT_0 /* Interrupt I2C transfer */ 1006 1007 /* B2_I2C_IRQ 32 bit I2C HW IRQ Register */ 1008 #define I2C_CLR_IRQ BIT_0 /* Clear I2C IRQ */ 1009 1010 /* B2_I2C_SW 32 bit (8 bit access) I2C HW SW Port Register */ 1011 #define I2C_DATA_DIR BIT_2 /* direction of I2C_DATA */ 1012 #define I2C_DATA BIT_1 /* I2C Data Port */ 1013 #define I2C_CLK BIT_0 /* I2C Clock Port */ 1014 1015 /* I2C Address */ 1016 #define I2C_SENS_ADDR LM80_ADDR /* I2C Sensor Address (Volt and Temp) */ 1017 1018 1019 /* B2_BSC_CTRL 8 bit Blink Source Counter Control */ 1020 #define BSC_START BIT_1 /* Start Blink Source Counter */ 1021 #define BSC_STOP BIT_0 /* Stop Blink Source Counter */ 1022 1023 /* B2_BSC_STAT 8 bit Blink Source Counter Status */ 1024 #define BSC_SRC BIT_0 /* Blink Source, 0=Off / 1=On */ 1025 1026 /* B2_BSC_TST 16 bit Blink Source Counter Test Reg */ 1027 #define BSC_T_ON BIT_2 /* Test mode on */ 1028 #define BSC_T_OFF BIT_1 /* Test mode off */ 1029 #define BSC_T_STEP BIT_0 /* Test step */ 1030 1031 /* Y2_PEX_PHY_ADDR/DATA PEX PHY address and data reg (Yukon-2 only) */ 1032 #define PEX_RD_ACCESS BIT_31 /* Access Mode Read = 1, Write = 0 */ 1033 #define PEX_DB_ACCESS BIT_30 /* Access to debug register */ 1034 1035 /* B3_RAM_ADDR 32 bit RAM Address, to read or write */ 1036 #define RAM_ADR_RAN 0x0007ffff /* Bit 18.. 0: RAM Address Range */ 1037 1038 /* RAM Interface Registers */ 1039 /* B3_RI_CTRL 16 bit RAM Interface Control Register */ 1040 #define RI_CLR_RD_PERR BIT_9 /* Clear IRQ RAM Read Parity Err */ 1041 #define RI_CLR_WR_PERR BIT_8 /* Clear IRQ RAM Write Parity Err */ 1042 #define RI_RST_CLR BIT_1 /* Clear RAM Interface Reset */ 1043 #define RI_RST_SET BIT_0 /* Set RAM Interface Reset */ 1044 1045 #define MSK_RI_TO_53 36 /* RAM interface timeout */ 1046 1047 /* Transmit Arbiter Registers MAC 1 and 2, use MR_ADDR() to access */ 1048 /* TXA_ITI_INI 32 bit Tx Arb Interval Timer Init Val */ 1049 /* TXA_ITI_VAL 32 bit Tx Arb Interval Timer Value */ 1050 /* TXA_LIM_INI 32 bit Tx Arb Limit Counter Init Val */ 1051 /* TXA_LIM_VAL 32 bit Tx Arb Limit Counter Value */ 1052 #define TXA_MAX_VAL 0x00ffffff/* Bit 23.. 0: Max TXA Timer/Cnt Val */ 1053 1054 /* TXA_CTRL 8 bit Tx Arbiter Control Register */ 1055 #define TXA_ENA_FSYNC BIT_7 /* Enable force of sync Tx queue */ 1056 #define TXA_DIS_FSYNC BIT_6 /* Disable force of sync Tx queue */ 1057 #define TXA_ENA_ALLOC BIT_5 /* Enable alloc of free bandwidth */ 1058 #define TXA_DIS_ALLOC BIT_4 /* Disable alloc of free bandwidth */ 1059 #define TXA_START_RC BIT_3 /* Start sync Rate Control */ 1060 #define TXA_STOP_RC BIT_2 /* Stop sync Rate Control */ 1061 #define TXA_ENA_ARB BIT_1 /* Enable Tx Arbiter */ 1062 #define TXA_DIS_ARB BIT_0 /* Disable Tx Arbiter */ 1063 1064 /* TXA_TEST 8 bit Tx Arbiter Test Register */ 1065 #define TXA_INT_T_ON BIT_5 /* Tx Arb Interval Timer Test On */ 1066 #define TXA_INT_T_OFF BIT_4 /* Tx Arb Interval Timer Test Off */ 1067 #define TXA_INT_T_STEP BIT_3 /* Tx Arb Interval Timer Step */ 1068 #define TXA_LIM_T_ON BIT_2 /* Tx Arb Limit Timer Test On */ 1069 #define TXA_LIM_T_OFF BIT_1 /* Tx Arb Limit Timer Test Off */ 1070 #define TXA_LIM_T_STEP BIT_0 /* Tx Arb Limit Timer Step */ 1071 1072 /* TXA_STAT 8 bit Tx Arbiter Status Register */ 1073 #define TXA_PRIO_XS BIT_0 /* sync queue has prio to send */ 1074 1075 /* Q_BC 32 bit Current Byte Counter */ 1076 #define BC_MAX 0xffff /* Bit 15.. 0: Byte counter */ 1077 1078 /* Rx BMU Control / Status Registers (Yukon-2) */ 1079 #define BMU_IDLE BIT_31 /* BMU Idle State */ 1080 #define BMU_RX_TCP_PKT BIT_30 /* Rx TCP Packet (when RSS Hash enabled) */ 1081 #define BMU_RX_IP_PKT BIT_29 /* Rx IP Packet (when RSS Hash enabled) */ 1082 #define BMU_ENA_RX_RSS_HASH BIT_15 /* Enable Rx RSS Hash */ 1083 #define BMU_DIS_RX_RSS_HASH BIT_14 /* Disable Rx RSS Hash */ 1084 #define BMU_ENA_RX_CHKSUM BIT_13 /* Enable Rx TCP/IP Checksum Check */ 1085 #define BMU_DIS_RX_CHKSUM BIT_12 /* Disable Rx TCP/IP Checksum Check */ 1086 #define BMU_CLR_IRQ_PAR BIT_11 /* Clear IRQ on Parity errors (Rx) */ 1087 #define BMU_CLR_IRQ_TCP BIT_11 /* Clear IRQ on TCP segmen. error (Tx) */ 1088 #define BMU_CLR_IRQ_CHK BIT_10 /* Clear IRQ Check */ 1089 #define BMU_STOP BIT_9 /* Stop Rx/Tx Queue */ 1090 #define BMU_START BIT_8 /* Start Rx/Tx Queue */ 1091 #define BMU_FIFO_OP_ON BIT_7 /* FIFO Operational On */ 1092 #define BMU_FIFO_OP_OFF BIT_6 /* FIFO Operational Off */ 1093 #define BMU_FIFO_ENA BIT_5 /* Enable FIFO */ 1094 #define BMU_FIFO_RST BIT_4 /* Reset FIFO */ 1095 #define BMU_OP_ON BIT_3 /* BMU Operational On */ 1096 #define BMU_OP_OFF BIT_2 /* BMU Operational Off */ 1097 #define BMU_RST_CLR BIT_1 /* Clear BMU Reset (Enable) */ 1098 #define BMU_RST_SET BIT_0 /* Set BMU Reset */ 1099 1100 #define BMU_CLR_RESET (BMU_FIFO_RST | BMU_OP_OFF | BMU_RST_CLR) 1101 #define BMU_OPER_INIT (BMU_CLR_IRQ_PAR | BMU_CLR_IRQ_CHK | \ 1102 BMU_START | BMU_FIFO_ENA | BMU_OP_ON) 1103 1104 /* Tx BMU Control / Status Registers (Yukon-2) */ 1105 /* Bit 31: same as for Rx */ 1106 #define BMU_TX_IPIDINCR_ON BIT_13 /* Enable IP ID Increment */ 1107 #define BMU_TX_IPIDINCR_OFF BIT_12 /* Disable IP ID Increment */ 1108 #define BMU_TX_CLR_IRQ_TCP BIT_11 /* Clear IRQ on TCP segm. length mism. */ 1109 /* Bit 10..0: same as for Rx */ 1110 1111 /* Q_F 32 bit Flag Register */ 1112 #define F_TX_CHK_AUTO_OFF BIT_31 /* Tx checksum auto-calc Off(Yukon EX)*/ 1113 #define F_TX_CHK_AUTO_ON BIT_30 /* Tx checksum auto-calc On(Yukon EX)*/ 1114 #define F_ALM_FULL BIT_28 /* Rx FIFO: almost full */ 1115 #define F_EMPTY BIT_27 /* Tx FIFO: empty flag */ 1116 #define F_FIFO_EOF BIT_26 /* Tag (EOF Flag) bit in FIFO */ 1117 #define F_WM_REACHED BIT_25 /* Watermark reached */ 1118 #define F_M_RX_RAM_DIS BIT_24 /* MAC Rx RAM Read Port disable */ 1119 #define F_FIFO_LEVEL (0x1f<<16) 1120 /* Bit 23..16: # of Qwords in FIFO */ 1121 #define F_WATER_MARK 0x0007ff/* Bit 10.. 0: Watermark */ 1122 1123 /* Queue Prefetch Unit Offsets, use Y2_PREF_Q_ADDR() to address (Yukon-2 only)*/ 1124 /* PREF_UNIT_CTRL_REG 32 bit Prefetch Control register */ 1125 #define PREF_UNIT_OP_ON BIT_3 /* prefetch unit operational */ 1126 #define PREF_UNIT_OP_OFF BIT_2 /* prefetch unit not operational */ 1127 #define PREF_UNIT_RST_CLR BIT_1 /* Clear Prefetch Unit Reset */ 1128 #define PREF_UNIT_RST_SET BIT_0 /* Set Prefetch Unit Reset */ 1129 1130 /* RAM Buffer Register Offsets, use RB_ADDR(Queue, Offs) to access */ 1131 /* RB_START 32 bit RAM Buffer Start Address */ 1132 /* RB_END 32 bit RAM Buffer End Address */ 1133 /* RB_WP 32 bit RAM Buffer Write Pointer */ 1134 /* RB_RP 32 bit RAM Buffer Read Pointer */ 1135 /* RB_RX_UTPP 32 bit Rx Upper Threshold, Pause Pack */ 1136 /* RB_RX_LTPP 32 bit Rx Lower Threshold, Pause Pack */ 1137 /* RB_RX_UTHP 32 bit Rx Upper Threshold, High Prio */ 1138 /* RB_RX_LTHP 32 bit Rx Lower Threshold, High Prio */ 1139 /* RB_PC 32 bit RAM Buffer Packet Counter */ 1140 /* RB_LEV 32 bit RAM Buffer Level Register */ 1141 #define RB_MSK 0x0007ffff /* Bit 18.. 0: RAM Buffer Pointer Bits */ 1142 1143 /* RB_TST2 8 bit RAM Buffer Test Register 2 */ 1144 #define RB_PC_DEC BIT_3 /* Packet Counter Decrement */ 1145 #define RB_PC_T_ON BIT_2 /* Packet Counter Test On */ 1146 #define RB_PC_T_OFF BIT_1 /* Packet Counter Test Off */ 1147 #define RB_PC_INC BIT_0 /* Packet Counter Increment */ 1148 1149 /* RB_TST1 8 bit RAM Buffer Test Register 1 */ 1150 #define RB_WP_T_ON BIT_6 /* Write Pointer Test On */ 1151 #define RB_WP_T_OFF BIT_5 /* Write Pointer Test Off */ 1152 #define RB_WP_INC BIT_4 /* Write Pointer Increment */ 1153 #define RB_RP_T_ON BIT_2 /* Read Pointer Test On */ 1154 #define RB_RP_T_OFF BIT_1 /* Read Pointer Test Off */ 1155 #define RB_RP_INC BIT_0 /* Read Pointer Increment */ 1156 1157 /* RB_CTRL 8 bit RAM Buffer Control Register */ 1158 #define RB_ENA_STFWD BIT_5 /* Enable Store & Forward */ 1159 #define RB_DIS_STFWD BIT_4 /* Disable Store & Forward */ 1160 #define RB_ENA_OP_MD BIT_3 /* Enable Operation Mode */ 1161 #define RB_DIS_OP_MD BIT_2 /* Disable Operation Mode */ 1162 #define RB_RST_CLR BIT_1 /* Clear RAM Buf STM Reset */ 1163 #define RB_RST_SET BIT_0 /* Set RAM Buf STM Reset */ 1164 1165 /* RAM Buffer High Pause Threshold values */ 1166 #define MSK_RB_ULPP (8 * 1024) /* Upper Level in kB/8 */ 1167 #define MSK_RB_LLPP_S (10 * 1024) /* Lower Level for small Queues */ 1168 #define MSK_RB_LLPP_B (16 * 1024) /* Lower Level for big Queues */ 1169 1170 /* Threshold values for Yukon-EC Ultra */ 1171 #define MSK_ECU_ULPP 0x0080 /* Upper Pause Threshold (multiples of 8) */ 1172 #define MSK_ECU_LLPP 0x0060 /* Lower Pause Threshold (multiples of 8) */ 1173 #define MSK_ECU_AE_THR 0x0070 /* Almost Empty Threshold */ 1174 #define MSK_ECU_TXFF_LEV 0x01a0 /* Tx BMU FIFO Level */ 1175 #define MSK_ECU_JUMBO_WM 0x01 1176 1177 #define MSK_BMU_RX_WM 0x600 /* BMU Rx Watermark */ 1178 #define MSK_BMU_TX_WM 0x600 /* BMU Tx Watermark */ 1179 /* performance sensitive drivers should set this define to 0x80 */ 1180 #define MSK_BMU_RX_WM_PEX 0x600 /* BMU Rx Watermark for PEX */ 1181 1182 /* Receive and Transmit Queues */ 1183 #define Q_R1 0x0000 /* Receive Queue 1 */ 1184 #define Q_R2 0x0080 /* Receive Queue 2 */ 1185 #define Q_XS1 0x0200 /* Synchronous Transmit Queue 1 */ 1186 #define Q_XA1 0x0280 /* Asynchronous Transmit Queue 1 */ 1187 #define Q_XS2 0x0300 /* Synchronous Transmit Queue 2 */ 1188 #define Q_XA2 0x0380 /* Asynchronous Transmit Queue 2 */ 1189 1190 #define Q_ASF_R1 0x100 /* ASF Rx Queue 1 */ 1191 #define Q_ASF_R2 0x180 /* ASF Rx Queue 2 */ 1192 #define Q_ASF_T1 0x140 /* ASF Tx Queue 1 */ 1193 #define Q_ASF_T2 0x1c0 /* ASF Tx Queue 2 */ 1194 1195 #define RB_ADDR(Queue, Offs) (B16_RAM_REGS + (Queue) + (Offs)) 1196 1197 /* Minimum RAM Buffer Rx Queue Size */ 1198 #define MSK_MIN_RXQ_SIZE 10 1199 /* Minimum RAM Buffer Tx Queue Size */ 1200 #define MSK_MIN_TXQ_SIZE 10 1201 /* Percentage of queue size from whole memory. 80 % for receive */ 1202 #define MSK_RAM_QUOTA_RX 80 1203 1204 /* WOL_CTRL_STAT 16 bit WOL Control/Status Reg */ 1205 #define WOL_CTL_LINK_CHG_OCC BIT_15 1206 #define WOL_CTL_MAGIC_PKT_OCC BIT_14 1207 #define WOL_CTL_PATTERN_OCC BIT_13 1208 #define WOL_CTL_CLEAR_RESULT BIT_12 1209 #define WOL_CTL_ENA_PME_ON_LINK_CHG BIT_11 1210 #define WOL_CTL_DIS_PME_ON_LINK_CHG BIT_10 1211 #define WOL_CTL_ENA_PME_ON_MAGIC_PKT BIT_9 1212 #define WOL_CTL_DIS_PME_ON_MAGIC_PKT BIT_8 1213 #define WOL_CTL_ENA_PME_ON_PATTERN BIT_7 1214 #define WOL_CTL_DIS_PME_ON_PATTERN BIT_6 1215 #define WOL_CTL_ENA_LINK_CHG_UNIT BIT_5 1216 #define WOL_CTL_DIS_LINK_CHG_UNIT BIT_4 1217 #define WOL_CTL_ENA_MAGIC_PKT_UNIT BIT_3 1218 #define WOL_CTL_DIS_MAGIC_PKT_UNIT BIT_2 1219 #define WOL_CTL_ENA_PATTERN_UNIT BIT_1 1220 #define WOL_CTL_DIS_PATTERN_UNIT BIT_0 1221 1222 #define WOL_CTL_DEFAULT \ 1223 (WOL_CTL_DIS_PME_ON_LINK_CHG | \ 1224 WOL_CTL_DIS_PME_ON_PATTERN | \ 1225 WOL_CTL_DIS_PME_ON_MAGIC_PKT | \ 1226 WOL_CTL_DIS_LINK_CHG_UNIT | \ 1227 WOL_CTL_DIS_PATTERN_UNIT | \ 1228 WOL_CTL_DIS_MAGIC_PKT_UNIT) 1229 1230 /* WOL_MATCH_CTL 8 bit WOL Match Control Reg */ 1231 #define WOL_CTL_PATT_ENA(x) (BIT_0 << (x)) 1232 1233 /* WOL_PATT_PME 8 bit WOL PME Match Enable (Yukon-2) */ 1234 #define WOL_PATT_FORCE_PME BIT_7 /* Generates a PME */ 1235 #define WOL_PATT_MATCH_PME_ALL 0x7f 1236 1237 1238 /* 1239 * Marvel-PHY Registers, indirect addressed over GMAC 1240 */ 1241 #define PHY_MARV_CTRL 0x00 /* 16 bit r/w PHY Control Register */ 1242 #define PHY_MARV_STAT 0x01 /* 16 bit r/o PHY Status Register */ 1243 #define PHY_MARV_ID0 0x02 /* 16 bit r/o PHY ID0 Register */ 1244 #define PHY_MARV_ID1 0x03 /* 16 bit r/o PHY ID1 Register */ 1245 #define PHY_MARV_AUNE_ADV 0x04 /* 16 bit r/w Auto-Neg. Advertisement */ 1246 #define PHY_MARV_AUNE_LP 0x05 /* 16 bit r/o Link Part Ability Reg */ 1247 #define PHY_MARV_AUNE_EXP 0x06 /* 16 bit r/o Auto-Neg. Expansion Reg */ 1248 #define PHY_MARV_NEPG 0x07 /* 16 bit r/w Next Page Register */ 1249 #define PHY_MARV_NEPG_LP 0x08 /* 16 bit r/o Next Page Link Partner */ 1250 /* Marvel-specific registers */ 1251 #define PHY_MARV_1000T_CTRL 0x09 /* 16 bit r/w 1000Base-T Control Reg */ 1252 #define PHY_MARV_1000T_STAT 0x0a /* 16 bit r/o 1000Base-T Status Reg */ 1253 /* 0x0b - 0x0e: reserved */ 1254 #define PHY_MARV_EXT_STAT 0x0f /* 16 bit r/o Extended Status Reg */ 1255 #define PHY_MARV_PHY_CTRL 0x10 /* 16 bit r/w PHY Specific Control Reg */ 1256 #define PHY_MARV_PHY_STAT 0x11 /* 16 bit r/o PHY Specific Status Reg */ 1257 #define PHY_MARV_INT_MASK 0x12 /* 16 bit r/w Interrupt Mask Reg */ 1258 #define PHY_MARV_INT_STAT 0x13 /* 16 bit r/o Interrupt Status Reg */ 1259 #define PHY_MARV_EXT_CTRL 0x14 /* 16 bit r/w Ext. PHY Specific Ctrl */ 1260 #define PHY_MARV_RXE_CNT 0x15 /* 16 bit r/w Receive Error Counter */ 1261 #define PHY_MARV_EXT_ADR 0x16 /* 16 bit r/w Ext. Ad. for Cable Diag. */ 1262 #define PHY_MARV_PORT_IRQ 0x17 /* 16 bit r/o Port 0 IRQ (88E1111 only) */ 1263 #define PHY_MARV_LED_CTRL 0x18 /* 16 bit r/w LED Control Reg */ 1264 #define PHY_MARV_LED_OVER 0x19 /* 16 bit r/w Manual LED Override Reg */ 1265 #define PHY_MARV_EXT_CTRL_2 0x1a /* 16 bit r/w Ext. PHY Specific Ctrl 2 */ 1266 #define PHY_MARV_EXT_P_STAT 0x1b /* 16 bit r/w Ext. PHY Spec. Stat Reg */ 1267 #define PHY_MARV_CABLE_DIAG 0x1c /* 16 bit r/o Cable Diagnostic Reg */ 1268 #define PHY_MARV_PAGE_ADDR 0x1d /* 16 bit r/w Extended Page Address Reg */ 1269 #define PHY_MARV_PAGE_DATA 0x1e /* 16 bit r/w Extended Page Data Reg */ 1270 1271 /* for 10/100 Fast Ethernet PHY (88E3082 only) */ 1272 #define PHY_MARV_FE_LED_PAR 0x16 /* 16 bit r/w LED Parallel Select Reg. */ 1273 #define PHY_MARV_FE_LED_SER 0x17 /* 16 bit r/w LED Stream Select S. LED */ 1274 #define PHY_MARV_FE_VCT_TX 0x1a /* 16 bit r/w VCT Reg. for TXP/N Pins */ 1275 #define PHY_MARV_FE_VCT_RX 0x1b /* 16 bit r/o VCT Reg. for RXP/N Pins */ 1276 #define PHY_MARV_FE_SPEC_2 0x1c /* 16 bit r/w Specific Control Reg. 2 */ 1277 1278 #define PHY_CT_RESET (1<<15) /* Bit 15: (sc) clear all PHY related regs */ 1279 #define PHY_CT_LOOP (1<<14) /* Bit 14: enable Loopback over PHY */ 1280 #define PHY_CT_SPS_LSB (1<<13) /* Bit 13: Speed select, lower bit */ 1281 #define PHY_CT_ANE (1<<12) /* Bit 12: Auto-Negotiation Enabled */ 1282 #define PHY_CT_PDOWN (1<<11) /* Bit 11: Power Down Mode */ 1283 #define PHY_CT_ISOL (1<<10) /* Bit 10: Isolate Mode */ 1284 #define PHY_CT_RE_CFG (1<<9) /* Bit 9: (sc) Restart Auto-Negotiation */ 1285 #define PHY_CT_DUP_MD (1<<8) /* Bit 8: Duplex Mode */ 1286 #define PHY_CT_COL_TST (1<<7) /* Bit 7: Collision Test enabled */ 1287 #define PHY_CT_SPS_MSB (1<<6) /* Bit 6: Speed select, upper bit */ 1288 1289 #define PHY_CT_SP1000 PHY_CT_SPS_MSB /* enable speed of 1000 Mbps */ 1290 #define PHY_CT_SP100 PHY_CT_SPS_LSB /* enable speed of 100 Mbps */ 1291 #define PHY_CT_SP10 (0) /* enable speed of 10 Mbps */ 1292 1293 #define PHY_ST_EXT_ST (1<<8) /* Bit 8: Extended Status Present */ 1294 #define PHY_ST_PRE_SUP (1<<6) /* Bit 6: Preamble Suppression */ 1295 #define PHY_ST_AN_OVER (1<<5) /* Bit 5: Auto-Negotiation Over */ 1296 #define PHY_ST_REM_FLT (1<<4) /* Bit 4: Remote Fault Condition Occured */ 1297 #define PHY_ST_AN_CAP (1<<3) /* Bit 3: Auto-Negotiation Capability */ 1298 #define PHY_ST_LSYNC (1<<2) /* Bit 2: Link Synchronized */ 1299 #define PHY_ST_JAB_DET (1<<1) /* Bit 1: Jabber Detected */ 1300 #define PHY_ST_EXT_REG (1<<0) /* Bit 0: Extended Register available */ 1301 1302 #define PHY_I1_OUI_MSK (0x3f<<10) /* Bit 15..10: Organization Unique ID */ 1303 #define PHY_I1_MOD_NUM (0x3f<<4) /* Bit 9.. 4: Model Number */ 1304 #define PHY_I1_REV_MSK 0xf /* Bit 3.. 0: Revision Number */ 1305 1306 /* different Marvell PHY Ids */ 1307 #define PHY_MARV_ID0_VAL 0x0141 /* Marvell Unique Identifier */ 1308 1309 #define PHY_MARV_ID1_B0 0x0C23 /* Yukon (PHY 88E1011) */ 1310 #define PHY_MARV_ID1_B2 0x0C25 /* Yukon-Plus (PHY 88E1011) */ 1311 #define PHY_MARV_ID1_C2 0x0CC2 /* Yukon-EC (PHY 88E1111) */ 1312 #define PHY_MARV_ID1_Y2 0x0C91 /* Yukon-2 (PHY 88E1112) */ 1313 #define PHY_MARV_ID1_FE 0x0C83 /* Yukon-FE (PHY 88E3082 Rev.A1) */ 1314 #define PHY_MARV_ID1_ECU 0x0CB0 /* Yukon-2 (PHY 88E1149 Rev.B2?) */ 1315 1316 /***** PHY_MARV_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/ 1317 #define PHY_B_1000S_MSF (1<<15) /* Bit 15: Master/Slave Fault */ 1318 #define PHY_B_1000S_MSR (1<<14) /* Bit 14: Master/Slave Result */ 1319 #define PHY_B_1000S_LRS (1<<13) /* Bit 13: Local Receiver Status */ 1320 #define PHY_B_1000S_RRS (1<<12) /* Bit 12: Remote Receiver Status */ 1321 #define PHY_B_1000S_LP_FD (1<<11) /* Bit 11: Link Partner can FD */ 1322 #define PHY_B_1000S_LP_HD (1<<10) /* Bit 10: Link Partner can HD */ 1323 #define PHY_B_1000S_IEC 0xff /* Bit 7..0: Idle Error Count */ 1324 1325 /***** PHY_MARV_AUNE_ADV 16 bit r/w Auto-Negotiation Advertisement *****/ 1326 /***** PHY_MARV_AUNE_LP 16 bit r/w Link Part Ability Reg *****/ 1327 #define PHY_M_AN_NXT_PG BIT_15 /* Request Next Page */ 1328 #define PHY_M_AN_ACK BIT_14 /* (ro) Acknowledge Received */ 1329 #define PHY_M_AN_RF BIT_13 /* Remote Fault */ 1330 #define PHY_M_AN_ASP BIT_11 /* Asymmetric Pause */ 1331 #define PHY_M_AN_PC BIT_10 /* MAC Pause implemented */ 1332 #define PHY_M_AN_100_T4 BIT_9 /* Not cap. 100Base-T4 (always 0) */ 1333 #define PHY_M_AN_100_FD BIT_8 /* Advertise 100Base-TX Full Duplex */ 1334 #define PHY_M_AN_100_HD BIT_7 /* Advertise 100Base-TX Half Duplex */ 1335 #define PHY_M_AN_10_FD BIT_6 /* Advertise 10Base-TX Full Duplex */ 1336 #define PHY_M_AN_10_HD BIT_5 /* Advertise 10Base-TX Half Duplex */ 1337 #define PHY_M_AN_SEL_MSK (0x1f<<4) /* Bit 4.. 0: Selector Field Mask */ 1338 1339 /* special defines for FIBER (88E1011S only) */ 1340 #define PHY_M_AN_ASP_X BIT_8 /* Asymmetric Pause */ 1341 #define PHY_M_AN_PC_X BIT_7 /* MAC Pause implemented */ 1342 #define PHY_M_AN_1000X_AHD BIT_6 /* Advertise 10000Base-X Half Duplex */ 1343 #define PHY_M_AN_1000X_AFD BIT_5 /* Advertise 10000Base-X Full Duplex */ 1344 1345 /* Pause Bits (PHY_M_AN_ASP_X and PHY_M_AN_PC_X) encoding */ 1346 #define PHY_M_P_NO_PAUSE_X (0<<7) /* Bit 8.. 7: no Pause Mode */ 1347 #define PHY_M_P_SYM_MD_X (1<<7) /* Bit 8.. 7: symmetric Pause Mode */ 1348 #define PHY_M_P_ASYM_MD_X (2<<7) /* Bit 8.. 7: asymmetric Pause Mode */ 1349 #define PHY_M_P_BOTH_MD_X (3<<7) /* Bit 8.. 7: both Pause Mode */ 1350 1351 /***** PHY_MARV_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/ 1352 #define PHY_M_1000C_TEST (7<<13) /* Bit 15..13: Test Modes */ 1353 #define PHY_M_1000C_MSE BIT_12 /* Manual Master/Slave Enable */ 1354 #define PHY_M_1000C_MSC BIT_11 /* M/S Configuration (1=Master) */ 1355 #define PHY_M_1000C_MPD BIT_10 /* Multi-Port Device */ 1356 #define PHY_M_1000C_AFD BIT_9 /* Advertise Full Duplex */ 1357 #define PHY_M_1000C_AHD BIT_8 /* Advertise Half Duplex */ 1358 1359 /***** PHY_MARV_PHY_CTRL 16 bit r/w PHY Specific Ctrl Reg *****/ 1360 #define PHY_M_PC_TX_FFD_MSK (3<<14) /* Bit 15..14: Tx FIFO Depth Mask */ 1361 #define PHY_M_PC_RX_FFD_MSK (3<<12) /* Bit 13..12: Rx FIFO Depth Mask */ 1362 #define PHY_M_PC_ASS_CRS_TX BIT_11 /* Assert CRS on Transmit */ 1363 #define PHY_M_PC_FL_GOOD BIT_10 /* Force Link Good */ 1364 #define PHY_M_PC_EN_DET_MSK (3<<8) /* Bit 9.. 8: Energy Detect Mask */ 1365 #define PHY_M_PC_ENA_EXT_D BIT_7 /* Enable Ext. Distance (10BT) */ 1366 #define PHY_M_PC_MDIX_MSK (3<<5) /* Bit 6.. 5: MDI/MDIX Config. Mask */ 1367 #define PHY_M_PC_DIS_125CLK BIT_4 /* Disable 125 CLK */ 1368 #define PHY_M_PC_MAC_POW_UP BIT_3 /* MAC Power up */ 1369 #define PHY_M_PC_SQE_T_ENA BIT_2 /* SQE Test Enabled */ 1370 #define PHY_M_PC_POL_R_DIS BIT_1 /* Polarity Reversal Disabled */ 1371 #define PHY_M_PC_DIS_JABBER BIT_0 /* Disable Jabber */ 1372 1373 #define PHY_M_PC_EN_DET SHIFT8(2) /* Energy Detect (Mode 1) */ 1374 #define PHY_M_PC_EN_DET_PLUS SHIFT8(3) /* Energy Detect Plus (Mode 2) */ 1375 1376 #define PHY_M_PC_MDI_XMODE(x) (SHIFT5(x) & PHY_M_PC_MDIX_MSK) 1377 1378 #define PHY_M_PC_MAN_MDI 0 /* 00 = Manual MDI configuration */ 1379 #define PHY_M_PC_MAN_MDIX 1 /* 01 = Manual MDIX configuration */ 1380 #define PHY_M_PC_ENA_AUTO 3 /* 11 = Enable Automatic Crossover */ 1381 1382 /* for Yukon-2 Gigabit Ethernet PHY (88E1112 only) */ 1383 #define PHY_M_PC_DIS_LINK_P BIT_15 /* Disable Link Pulses */ 1384 #define PHY_M_PC_DSC_MSK (7<<12) /* Bit 14..12: Downshift Counter */ 1385 #define PHY_M_PC_DOWN_S_ENA BIT_11 /* Downshift Enable */ 1386 /* !!! Errata in spec. (1 = disable) */ 1387 1388 #define PHY_M_PC_DSC(x) (SHIFT12(x) & PHY_M_PC_DSC_MSK) 1389 /* 000=1x; 001=2x; 010=3x; 011=4x */ 1390 /* 100=5x; 101=6x; 110=7x; 111=8x */ 1391 1392 /* for 10/100 Fast Ethernet PHY (88E3082 only) */ 1393 #define PHY_M_PC_ENA_DTE_DT BIT_15 /* Enable Data Terminal Equ. (DTE) Detect */ 1394 #define PHY_M_PC_ENA_ENE_DT BIT_14 /* Enable Energy Detect (sense & pulse) */ 1395 #define PHY_M_PC_DIS_NLP_CK BIT_13 /* Disable Normal Link Puls (NLP) Check */ 1396 #define PHY_M_PC_ENA_LIP_NP BIT_12 /* Enable Link Partner Next Page Reg. */ 1397 #define PHY_M_PC_DIS_NLP_GN BIT_11 /* Disable Normal Link Puls Generation */ 1398 #define PHY_M_PC_DIS_SCRAMB BIT_9 /* Disable Scrambler */ 1399 #define PHY_M_PC_DIS_FEFI BIT_8 /* Disable Far End Fault Indic. (FEFI) */ 1400 #define PHY_M_PC_SH_TP_SEL BIT_6 /* Shielded Twisted Pair Select */ 1401 #define PHY_M_PC_RX_FD_MSK (3<<2) /* Bit 3.. 2: Rx FIFO Depth Mask */ 1402 1403 /***** PHY_MARV_PHY_STAT 16 bit r/o PHY Specific Status Reg *****/ 1404 #define PHY_M_PS_SPEED_MSK (3<<14) /* Bit 15..14: Speed Mask */ 1405 #define PHY_M_PS_SPEED_1000 BIT_15 /* 10 = 1000 Mbps */ 1406 #define PHY_M_PS_SPEED_100 BIT_14 /* 01 = 100 Mbps */ 1407 #define PHY_M_PS_SPEED_10 0 /* 00 = 10 Mbps */ 1408 #define PHY_M_PS_FULL_DUP BIT_13 /* Full Duplex */ 1409 #define PHY_M_PS_PAGE_REC BIT_12 /* Page Received */ 1410 #define PHY_M_PS_SPDUP_RES BIT_11 /* Speed & Duplex Resolved */ 1411 #define PHY_M_PS_LINK_UP BIT_10 /* Link Up */ 1412 #define PHY_M_PS_CABLE_MSK (7<<7) /* Bit 9.. 7: Cable Length Mask */ 1413 #define PHY_M_PS_MDI_X_STAT BIT_6 /* MDI Crossover Stat (1=MDIX) */ 1414 #define PHY_M_PS_DOWNS_STAT BIT_5 /* Downshift Status (1=downsh.) */ 1415 #define PHY_M_PS_ENDET_STAT BIT_4 /* Energy Detect Status (1=act) */ 1416 #define PHY_M_PS_TX_P_EN BIT_3 /* Tx Pause Enabled */ 1417 #define PHY_M_PS_RX_P_EN BIT_2 /* Rx Pause Enabled */ 1418 #define PHY_M_PS_POL_REV BIT_1 /* Polarity Reversed */ 1419 #define PHY_M_PS_JABBER BIT_0 /* Jabber */ 1420 1421 #define PHY_M_PS_PAUSE_MSK (PHY_M_PS_TX_P_EN | PHY_M_PS_RX_P_EN) 1422 1423 /* for 10/100 Fast Ethernet PHY (88E3082 only) */ 1424 #define PHY_M_PS_DTE_DETECT BIT_15 /* Data Terminal Equipment (DTE) Detected */ 1425 #define PHY_M_PS_RES_SPEED BIT_14 /* Resolved Speed (1=100 Mbps, 0=10 Mbps */ 1426 1427 /***** PHY_MARV_INT_MASK 16 bit r/w Interrupt Mask Reg *****/ 1428 /***** PHY_MARV_INT_STAT 16 bit r/o Interrupt Status Reg *****/ 1429 #define PHY_M_IS_AN_ERROR BIT_15 /* Auto-Negotiation Error */ 1430 #define PHY_M_IS_LSP_CHANGE BIT_14 /* Link Speed Changed */ 1431 #define PHY_M_IS_DUP_CHANGE BIT_13 /* Duplex Mode Changed */ 1432 #define PHY_M_IS_AN_PR BIT_12 /* Page Received */ 1433 #define PHY_M_IS_AN_COMPL BIT_11 /* Auto-Negotiation Completed */ 1434 #define PHY_M_IS_LST_CHANGE BIT_10 /* Link Status Changed */ 1435 #define PHY_M_IS_SYMB_ERROR BIT_9 /* Symbol Error */ 1436 #define PHY_M_IS_FALSE_CARR BIT_8 /* False Carrier */ 1437 #define PHY_M_IS_FIFO_ERROR BIT_7 /* FIFO Overflow/Underrun Error */ 1438 #define PHY_M_IS_MDI_CHANGE BIT_6 /* MDI Crossover Changed */ 1439 #define PHY_M_IS_DOWNSH_DET BIT_5 /* Downshift Detected */ 1440 #define PHY_M_IS_END_CHANGE BIT_4 /* Energy Detect Changed */ 1441 #define PHY_M_IS_DTE_CHANGE BIT_2 /* DTE Power Det. Status Changed */ 1442 #define PHY_M_IS_POL_CHANGE BIT_1 /* Polarity Changed */ 1443 #define PHY_M_IS_JABBER BIT_0 /* Jabber */ 1444 1445 #define PHY_M_DEF_MSK (PHY_M_IS_AN_ERROR | PHY_M_IS_AN_PR | \ 1446 PHY_M_IS_LST_CHANGE | PHY_M_IS_FIFO_ERROR) 1447 1448 /***** PHY_MARV_EXT_CTRL 16 bit r/w Ext. PHY Specific Ctrl *****/ 1449 #define PHY_M_EC_ENA_BC_EXT BIT_15 /* Enable Block Carr. Ext. (88E1111 only) */ 1450 #define PHY_M_EC_ENA_LIN_LB BIT_14 /* Enable Line Loopback (88E1111 only) */ 1451 #define PHY_M_EC_DIS_LINK_P BIT_12 /* Disable Link Pulses (88E1111 only) */ 1452 #define PHY_M_EC_M_DSC_MSK (3<<10) /* Bit 11..10: Master Downshift Counter */ 1453 /* (88E1011 only) */ 1454 #define PHY_M_EC_S_DSC_MSK (3<<8) /* Bit 9.. 8: Slave Downshift Counter */ 1455 /* (88E1011 only) */ 1456 #define PHY_M_EC_DSC_MSK_2 (7<<9) /* Bit 11.. 9: Downshift Counter */ 1457 /* (88E1111 only) */ 1458 #define PHY_M_EC_DOWN_S_ENA BIT_8 /* Downshift Enable (88E1111 only) */ 1459 /* !!! Errata in spec. (1 = disable) */ 1460 #define PHY_M_EC_RX_TIM_CT BIT_7 /* RGMII Rx Timing Control*/ 1461 #define PHY_M_EC_MAC_S_MSK (7<<4) /* Bit 6.. 4: Def. MAC interface speed */ 1462 #define PHY_M_EC_FIB_AN_ENA BIT_3 /* Fiber Auto-Neg. Enable (88E1011S only) */ 1463 #define PHY_M_EC_DTE_D_ENA BIT_2 /* DTE Detect Enable (88E1111 only) */ 1464 #define PHY_M_EC_TX_TIM_CT BIT_1 /* RGMII Tx Timing Control */ 1465 #define PHY_M_EC_TRANS_DIS BIT_0 /* Transmitter Disable (88E1111 only) */ 1466 1467 #define PHY_M_EC_M_DSC(x) (SHIFT10(x) & PHY_M_EC_M_DSC_MSK) 1468 /* 00=1x; 01=2x; 10=3x; 11=4x */ 1469 #define PHY_M_EC_S_DSC(x) (SHIFT8(x) & PHY_M_EC_S_DSC_MSK) 1470 /* 00=dis; 01=1x; 10=2x; 11=3x */ 1471 #define PHY_M_EC_MAC_S(x) (SHIFT4(x) & PHY_M_EC_MAC_S_MSK) 1472 /* 01X=0; 110=2.5; 111=25 (MHz) */ 1473 1474 #define PHY_M_EC_DSC_2(x) (SHIFT9(x) & PHY_M_EC_DSC_MSK_2) 1475 /* 000=1x; 001=2x; 010=3x; 011=4x */ 1476 /* 100=5x; 101=6x; 110=7x; 111=8x */ 1477 #define MAC_TX_CLK_0_MHZ 2 1478 #define MAC_TX_CLK_2_5_MHZ 6 1479 #define MAC_TX_CLK_25_MHZ 7 1480 1481 /***** PHY_MARV_LED_CTRL 16 bit r/w LED Control Reg *****/ 1482 #define PHY_M_LEDC_DIS_LED BIT_15 /* Disable LED */ 1483 #define PHY_M_LEDC_PULS_MSK (7<<12) /* Bit 14..12: Pulse Stretch Mask */ 1484 #define PHY_M_LEDC_F_INT BIT_11 /* Force Interrupt */ 1485 #define PHY_M_LEDC_BL_R_MSK (7<<8) /* Bit 10.. 8: Blink Rate Mask */ 1486 #define PHY_M_LEDC_DP_C_LSB BIT_7 /* Duplex Control (LSB, 88E1111 only) */ 1487 #define PHY_M_LEDC_TX_C_LSB BIT_6 /* Tx Control (LSB, 88E1111 only) */ 1488 #define PHY_M_LEDC_LK_C_MSK (7<<3) /* Bit 5.. 3: Link Control Mask */ 1489 /* (88E1111 only) */ 1490 #define PHY_M_LEDC_LINK_MSK (3<<3) /* Bit 4.. 3: Link Control Mask */ 1491 /* (88E1011 only) */ 1492 #define PHY_M_LEDC_DP_CTRL BIT_2 /* Duplex Control */ 1493 #define PHY_M_LEDC_DP_C_MSB BIT_2 /* Duplex Control (MSB, 88E1111 only) */ 1494 #define PHY_M_LEDC_RX_CTRL BIT_1 /* Rx Activity / Link */ 1495 #define PHY_M_LEDC_TX_CTRL BIT_0 /* Tx Activity / Link */ 1496 #define PHY_M_LEDC_TX_C_MSB BIT_0 /* Tx Control (MSB, 88E1111 only) */ 1497 1498 #define PHY_M_LED_PULS_DUR(x) (SHIFT12(x) & PHY_M_LEDC_PULS_MSK) 1499 1500 #define PULS_NO_STR 0 /* no pulse stretching */ 1501 #define PULS_21MS 1 /* 21 ms to 42 ms */ 1502 #define PULS_42MS 2 /* 42 ms to 84 ms */ 1503 #define PULS_84MS 3 /* 84 ms to 170 ms */ 1504 #define PULS_170MS 4 /* 170 ms to 340 ms */ 1505 #define PULS_340MS 5 /* 340 ms to 670 ms */ 1506 #define PULS_670MS 6 /* 670 ms to 1.3 s */ 1507 #define PULS_1300MS 7 /* 1.3 s to 2.7 s */ 1508 1509 #define PHY_M_LED_BLINK_RT(x) (SHIFT8(x) & PHY_M_LEDC_BL_R_MSK) 1510 1511 #define BLINK_42MS 0 /* 42 ms */ 1512 #define BLINK_84MS 1 /* 84 ms */ 1513 #define BLINK_170MS 2 /* 170 ms */ 1514 #define BLINK_340MS 3 /* 340 ms */ 1515 #define BLINK_670MS 4 /* 670 ms */ 1516 1517 /***** PHY_MARV_LED_OVER 16 bit r/w Manual LED Override Reg *****/ 1518 #define PHY_M_LED_MO_SGMII(x) SHIFT14(x) /* Bit 15..14: SGMII AN Timer */ 1519 #define PHY_M_LED_MO_DUP(x) SHIFT10(x) /* Bit 11..10: Duplex */ 1520 #define PHY_M_LED_MO_10(x) SHIFT8(x) /* Bit 9.. 8: Link 10 */ 1521 #define PHY_M_LED_MO_100(x) SHIFT6(x) /* Bit 7.. 6: Link 100 */ 1522 #define PHY_M_LED_MO_1000(x) SHIFT4(x) /* Bit 5.. 4: Link 1000 */ 1523 #define PHY_M_LED_MO_RX(x) SHIFT2(x) /* Bit 3.. 2: Rx */ 1524 #define PHY_M_LED_MO_TX(x) SHIFT0(x) /* Bit 1.. 0: Tx */ 1525 1526 #define MO_LED_NORM 0 1527 #define MO_LED_BLINK 1 1528 #define MO_LED_OFF 2 1529 #define MO_LED_ON 3 1530 1531 /***** PHY_MARV_EXT_CTRL_2 16 bit r/w Ext. PHY Specific Ctrl 2 *****/ 1532 #define PHY_M_EC2_FI_IMPED BIT_6 /* Fiber Input Impedance */ 1533 #define PHY_M_EC2_FO_IMPED BIT_5 /* Fiber Output Impedance */ 1534 #define PHY_M_EC2_FO_M_CLK BIT_4 /* Fiber Mode Clock Enable */ 1535 #define PHY_M_EC2_FO_BOOST BIT_3 /* Fiber Output Boost */ 1536 #define PHY_M_EC2_FO_AM_MSK 7 /* Bit 2.. 0: Fiber Output Amplitude */ 1537 1538 /***** PHY_MARV_EXT_P_STAT 16 bit r/w Ext. PHY Specific Status *****/ 1539 #define PHY_M_FC_AUTO_SEL BIT_15 /* Fiber/Copper Auto Sel. Dis. */ 1540 #define PHY_M_FC_AN_REG_ACC BIT_14 /* Fiber/Copper AN Reg. Access */ 1541 #define PHY_M_FC_RESOLUTION BIT_13 /* Fiber/Copper Resolution */ 1542 #define PHY_M_SER_IF_AN_BP BIT_12 /* Ser. IF AN Bypass Enable */ 1543 #define PHY_M_SER_IF_BP_ST BIT_11 /* Ser. IF AN Bypass Status */ 1544 #define PHY_M_IRQ_POLARITY BIT_10 /* IRQ polarity */ 1545 #define PHY_M_DIS_AUT_MED BIT_9 /* Disable Aut. Medium Reg. Selection */ 1546 /* (88E1111 only) */ 1547 #define PHY_M_UNDOC1 BIT_7 /* undocumented bit !! */ 1548 #define PHY_M_DTE_POW_STAT BIT_4 /* DTE Power Status (88E1111 only) */ 1549 #define PHY_M_MODE_MASK 0xf /* Bit 3.. 0: copy of HWCFG MODE[3:0] */ 1550 1551 /***** PHY_MARV_CABLE_DIAG 16 bit r/o Cable Diagnostic Reg *****/ 1552 #define PHY_M_CABD_ENA_TEST BIT_15 /* Enable Test (Page 0) */ 1553 #define PHY_M_CABD_DIS_WAIT BIT_15 /* Disable Waiting Period (Page 1) */ 1554 /* (88E1111 only) */ 1555 #define PHY_M_CABD_STAT_MSK (3<<13) /* Bit 14..13: Status Mask */ 1556 #define PHY_M_CABD_AMPL_MSK (0x1f<<8) /* Bit 12.. 8: Amplitude Mask */ 1557 /* (88E1111 only) */ 1558 #define PHY_M_CABD_DIST_MSK 0xff /* Bit 7.. 0: Distance Mask */ 1559 1560 /* values for Cable Diagnostic Status (11=fail; 00=OK; 10=open; 01=short) */ 1561 #define CABD_STAT_NORMAL 0 1562 #define CABD_STAT_SHORT 1 1563 #define CABD_STAT_OPEN 2 1564 #define CABD_STAT_FAIL 3 1565 1566 /* for 10/100 Fast Ethernet PHY (88E3082 only) */ 1567 /***** PHY_MARV_FE_LED_PAR 16 bit r/w LED Parallel Select Reg. *****/ 1568 #define PHY_M_FELP_LED2_MSK (0xf<<8) /* Bit 11.. 8: LED2 Mask (LINK) */ 1569 #define PHY_M_FELP_LED1_MSK (0xf<<4) /* Bit 7.. 4: LED1 Mask (ACT) */ 1570 #define PHY_M_FELP_LED0_MSK 0xf /* Bit 3.. 0: LED0 Mask (SPEED) */ 1571 1572 #define PHY_M_FELP_LED2_CTRL(x) (SHIFT8(x) & PHY_M_FELP_LED2_MSK) 1573 #define PHY_M_FELP_LED1_CTRL(x) (SHIFT4(x) & PHY_M_FELP_LED1_MSK) 1574 #define PHY_M_FELP_LED0_CTRL(x) (SHIFT0(x) & PHY_M_FELP_LED0_MSK) 1575 1576 #define LED_PAR_CTRL_COLX 0x00 1577 #define LED_PAR_CTRL_ERROR 0x01 1578 #define LED_PAR_CTRL_DUPLEX 0x02 1579 #define LED_PAR_CTRL_DP_COL 0x03 1580 #define LED_PAR_CTRL_SPEED 0x04 1581 #define LED_PAR_CTRL_LINK 0x05 1582 #define LED_PAR_CTRL_TX 0x06 1583 #define LED_PAR_CTRL_RX 0x07 1584 #define LED_PAR_CTRL_ACT 0x08 1585 #define LED_PAR_CTRL_LNK_RX 0x09 1586 #define LED_PAR_CTRL_LNK_AC 0x0a 1587 #define LED_PAR_CTRL_ACT_BL 0x0b 1588 #define LED_PAR_CTRL_TX_BL 0x0c 1589 #define LED_PAR_CTRL_RX_BL 0x0d 1590 #define LED_PAR_CTRL_COL_BL 0x0e 1591 #define LED_PAR_CTRL_INACT 0x0f 1592 1593 /***** PHY_MARV_FE_SPEC_2 16 bit r/w Specific Control Reg. 2 *****/ 1594 #define PHY_M_FESC_DIS_WAIT BIT_2 /* Disable TDR Waiting Period */ 1595 #define PHY_M_FESC_ENA_MCLK BIT_1 /* Enable MAC Rx Clock in sleep mode */ 1596 #define PHY_M_FESC_SEL_CL_A BIT_0 /* Select Class A driver (100B-TX) */ 1597 1598 /* for Yukon-2 Gigabit Ethernet PHY (88E1112 only) */ 1599 /***** PHY_MARV_PHY_CTRL (page 1) 16 bit r/w Fiber Specific Ctrl *****/ 1600 #define PHY_M_FIB_FORCE_LNK BIT_10 /* Force Link Good */ 1601 #define PHY_M_FIB_SIGD_POL BIT_9 /* SIGDET Polarity */ 1602 #define PHY_M_FIB_TX_DIS BIT_3 /* Transmitter Disable */ 1603 1604 /***** PHY_MARV_PHY_CTRL (page 2) 16 bit r/w MAC Specific Ctrl *****/ 1605 #define PHY_M_MAC_MD_MSK (7<<7) /* Bit 9.. 7: Mode Select Mask */ 1606 #define PHY_M_MAC_MD_AUTO 3 /* Auto Copper/1000Base-X */ 1607 #define PHY_M_MAC_MD_COPPER 5 /* Copper only */ 1608 #define PHY_M_MAC_MD_1000BX 7 /* 1000Base-X only */ 1609 #define PHY_M_MAC_MODE_SEL(x) (SHIFT7(x) & PHY_M_MAC_MD_MSK) 1610 1611 /***** PHY_MARV_PHY_CTRL (page 3) 16 bit r/w LED Control Reg. *****/ 1612 #define PHY_M_LEDC_LOS_MSK (0xf<<12) /* Bit 15..12: LOS LED Ctrl. Mask */ 1613 #define PHY_M_LEDC_INIT_MSK (0xf<<8) /* Bit 11.. 8: INIT LED Ctrl. Mask */ 1614 #define PHY_M_LEDC_STA1_MSK (0xf<<4) /* Bit 7.. 4: STAT1 LED Ctrl. Mask */ 1615 #define PHY_M_LEDC_STA0_MSK 0xf /* Bit 3.. 0: STAT0 LED Ctrl. Mask */ 1616 1617 #define PHY_M_LEDC_LOS_CTRL(x) (SHIFT12(x) & PHY_M_LEDC_LOS_MSK) 1618 #define PHY_M_LEDC_INIT_CTRL(x) (SHIFT8(x) & PHY_M_LEDC_INIT_MSK) 1619 #define PHY_M_LEDC_STA1_CTRL(x) (SHIFT4(x) & PHY_M_LEDC_STA1_MSK) 1620 #define PHY_M_LEDC_STA0_CTRL(x) (SHIFT0(x) & PHY_M_LEDC_STA0_MSK) 1621 1622 /***** PHY_MARV_PHY_STAT (page 3) 16 bit r/w Polarity Control Reg. *****/ 1623 #define PHY_M_POLC_LS1M_MSK (0xf<<12) /* Bit 15..12: LOS,STAT1 Mix % Mask */ 1624 #define PHY_M_POLC_IS0M_MSK (0xf<<8) /* Bit 11.. 8: INIT,STAT0 Mix % Mask */ 1625 #define PHY_M_POLC_LOS_MSK (0x3<<6) /* Bit 7.. 6: LOS Pol. Ctrl. Mask */ 1626 #define PHY_M_POLC_INIT_MSK (0x3<<4) /* Bit 5.. 4: INIT Pol. Ctrl. Mask */ 1627 #define PHY_M_POLC_STA1_MSK (0x3<<2) /* Bit 3.. 2: STAT1 Pol. Ctrl. Mask */ 1628 #define PHY_M_POLC_STA0_MSK 0x3 /* Bit 1.. 0: STAT0 Pol. Ctrl. Mask */ 1629 1630 #define PHY_M_POLC_LS1_P_MIX(x) (SHIFT12(x) & PHY_M_POLC_LS1M_MSK) 1631 #define PHY_M_POLC_IS0_P_MIX(x) (SHIFT8(x) & PHY_M_POLC_IS0M_MSK) 1632 #define PHY_M_POLC_LOS_CTRL(x) (SHIFT6(x) & PHY_M_POLC_LOS_MSK) 1633 #define PHY_M_POLC_INIT_CTRL(x) (SHIFT4(x) & PHY_M_POLC_INIT_MSK) 1634 #define PHY_M_POLC_STA1_CTRL(x) (SHIFT2(x) & PHY_M_POLC_STA1_MSK) 1635 #define PHY_M_POLC_STA0_CTRL(x) (SHIFT0(x) & PHY_M_POLC_STA0_MSK) 1636 1637 /* 1638 * GMAC registers 1639 * 1640 * The GMAC registers are 16 or 32 bits wide. 1641 * The GMACs host processor interface is 16 bits wide, 1642 * therefore ALL registers will be addressed with 16 bit accesses. 1643 * 1644 * Note: NA reg = Network Address e.g DA, SA etc. 1645 */ 1646 1647 /* Port Registers */ 1648 #define GM_GP_STAT 0x0000 /* 16 bit r/o General Purpose Status */ 1649 #define GM_GP_CTRL 0x0004 /* 16 bit r/w General Purpose Control */ 1650 #define GM_TX_CTRL 0x0008 /* 16 bit r/w Transmit Control Reg. */ 1651 #define GM_RX_CTRL 0x000c /* 16 bit r/w Receive Control Reg. */ 1652 #define GM_TX_FLOW_CTRL 0x0010 /* 16 bit r/w Transmit Flow-Control */ 1653 #define GM_TX_PARAM 0x0014 /* 16 bit r/w Transmit Parameter Reg. */ 1654 #define GM_SERIAL_MODE 0x0018 /* 16 bit r/w Serial Mode Register */ 1655 1656 /* Source Address Registers */ 1657 #define GM_SRC_ADDR_1L 0x001c /* 16 bit r/w Source Address 1 (low) */ 1658 #define GM_SRC_ADDR_1M 0x0020 /* 16 bit r/w Source Address 1 (middle) */ 1659 #define GM_SRC_ADDR_1H 0x0024 /* 16 bit r/w Source Address 1 (high) */ 1660 #define GM_SRC_ADDR_2L 0x0028 /* 16 bit r/w Source Address 2 (low) */ 1661 #define GM_SRC_ADDR_2M 0x002c /* 16 bit r/w Source Address 2 (middle) */ 1662 #define GM_SRC_ADDR_2H 0x0030 /* 16 bit r/w Source Address 2 (high) */ 1663 1664 /* Multicast Address Hash Registers */ 1665 #define GM_MC_ADDR_H1 0x0034 /* 16 bit r/w Multicast Address Hash 1 */ 1666 #define GM_MC_ADDR_H2 0x0038 /* 16 bit r/w Multicast Address Hash 2 */ 1667 #define GM_MC_ADDR_H3 0x003c /* 16 bit r/w Multicast Address Hash 3 */ 1668 #define GM_MC_ADDR_H4 0x0040 /* 16 bit r/w Multicast Address Hash 4 */ 1669 1670 /* Interrupt Source Registers */ 1671 #define GM_TX_IRQ_SRC 0x0044 /* 16 bit r/o Tx Overflow IRQ Source */ 1672 #define GM_RX_IRQ_SRC 0x0048 /* 16 bit r/o Rx Overflow IRQ Source */ 1673 #define GM_TR_IRQ_SRC 0x004c /* 16 bit r/o Tx/Rx Over. IRQ Source */ 1674 1675 /* Interrupt Mask Registers */ 1676 #define GM_TX_IRQ_MSK 0x0050 /* 16 bit r/w Tx Overflow IRQ Mask */ 1677 #define GM_RX_IRQ_MSK 0x0054 /* 16 bit r/w Rx Overflow IRQ Mask */ 1678 #define GM_TR_IRQ_MSK 0x0058 /* 16 bit r/w Tx/Rx Over. IRQ Mask */ 1679 1680 /* Serial Management Interface (SMI) Registers */ 1681 #define GM_SMI_CTRL 0x0080 /* 16 bit r/w SMI Control Register */ 1682 #define GM_SMI_DATA 0x0084 /* 16 bit r/w SMI Data Register */ 1683 #define GM_PHY_ADDR 0x0088 /* 16 bit r/w GPHY Address Register */ 1684 1685 /* MIB Counters */ 1686 #define GM_MIB_CNT_BASE 0x0100 /* Base Address of MIB Counters */ 1687 #define GM_MIB_CNT_SIZE 44 /* Number of MIB Counters */ 1688 1689 /* 1690 * MIB Counters base address definitions (low word) - 1691 * use offset 4 for access to high word (32 bit r/o) 1692 */ 1693 #define GM_RXF_UC_OK \ 1694 (GM_MIB_CNT_BASE + 0) /* Unicast Frames Received OK */ 1695 #define GM_RXF_BC_OK \ 1696 (GM_MIB_CNT_BASE + 8) /* Broadcast Frames Received OK */ 1697 #define GM_RXF_MPAUSE \ 1698 (GM_MIB_CNT_BASE + 16) /* Pause MAC Ctrl Frames Received */ 1699 #define GM_RXF_MC_OK \ 1700 (GM_MIB_CNT_BASE + 24) /* Multicast Frames Received OK */ 1701 #define GM_RXF_FCS_ERR \ 1702 (GM_MIB_CNT_BASE + 32) /* Rx Frame Check Seq. Error */ 1703 #define GM_RXF_SPARE1 \ 1704 (GM_MIB_CNT_BASE + 40) /* Rx spare 1 */ 1705 #define GM_RXO_OK_LO \ 1706 (GM_MIB_CNT_BASE + 48) /* Octets Received OK Low */ 1707 #define GM_RXO_OK_HI \ 1708 (GM_MIB_CNT_BASE + 56) /* Octets Received OK High */ 1709 #define GM_RXO_ERR_LO \ 1710 (GM_MIB_CNT_BASE + 64) /* Octets Received Invalid Low */ 1711 #define GM_RXO_ERR_HI \ 1712 (GM_MIB_CNT_BASE + 72) /* Octets Received Invalid High */ 1713 #define GM_RXF_SHT \ 1714 (GM_MIB_CNT_BASE + 80) /* Frames <64 Byte Received OK */ 1715 #define GM_RXE_FRAG \ 1716 (GM_MIB_CNT_BASE + 88) /* Frames <64 Byte Received with FCS Err */ 1717 #define GM_RXF_64B \ 1718 (GM_MIB_CNT_BASE + 96) /* 64 Byte Rx Frame */ 1719 #define GM_RXF_127B \ 1720 (GM_MIB_CNT_BASE + 104) /* 65-127 Byte Rx Frame */ 1721 #define GM_RXF_255B \ 1722 (GM_MIB_CNT_BASE + 112) /* 128-255 Byte Rx Frame */ 1723 #define GM_RXF_511B \ 1724 (GM_MIB_CNT_BASE + 120) /* 256-511 Byte Rx Frame */ 1725 #define GM_RXF_1023B \ 1726 (GM_MIB_CNT_BASE + 128) /* 512-1023 Byte Rx Frame */ 1727 #define GM_RXF_1518B \ 1728 (GM_MIB_CNT_BASE + 136) /* 1024-1518 Byte Rx Frame */ 1729 #define GM_RXF_MAX_SZ \ 1730 (GM_MIB_CNT_BASE + 144) /* 1519-MaxSize Byte Rx Frame */ 1731 #define GM_RXF_LNG_ERR \ 1732 (GM_MIB_CNT_BASE + 152) /* Rx Frame too Long Error */ 1733 #define GM_RXF_JAB_PKT \ 1734 (GM_MIB_CNT_BASE + 160) /* Rx Jabber Packet Frame */ 1735 #define GM_RXF_SPARE2 \ 1736 (GM_MIB_CNT_BASE + 168) /* Rx spare 2 */ 1737 #define GM_RXE_FIFO_OV \ 1738 (GM_MIB_CNT_BASE + 176) /* Rx FIFO overflow Event */ 1739 #define GM_RXF_SPARE3 \ 1740 (GM_MIB_CNT_BASE + 184) /* Rx spare 3 */ 1741 #define GM_TXF_UC_OK \ 1742 (GM_MIB_CNT_BASE + 192) /* Unicast Frames Xmitted OK */ 1743 #define GM_TXF_BC_OK \ 1744 (GM_MIB_CNT_BASE + 200) /* Broadcast Frames Xmitted OK */ 1745 #define GM_TXF_MPAUSE \ 1746 (GM_MIB_CNT_BASE + 208) /* Pause MAC Ctrl Frames Xmitted */ 1747 #define GM_TXF_MC_OK \ 1748 (GM_MIB_CNT_BASE + 216) /* Multicast Frames Xmitted OK */ 1749 #define GM_TXO_OK_LO \ 1750 (GM_MIB_CNT_BASE + 224) /* Octets Transmitted OK Low */ 1751 #define GM_TXO_OK_HI \ 1752 (GM_MIB_CNT_BASE + 232) /* Octets Transmitted OK High */ 1753 #define GM_TXF_64B \ 1754 (GM_MIB_CNT_BASE + 240) /* 64 Byte Tx Frame */ 1755 #define GM_TXF_127B \ 1756 (GM_MIB_CNT_BASE + 248) /* 65-127 Byte Tx Frame */ 1757 #define GM_TXF_255B \ 1758 (GM_MIB_CNT_BASE + 256) /* 128-255 Byte Tx Frame */ 1759 #define GM_TXF_511B \ 1760 (GM_MIB_CNT_BASE + 264) /* 256-511 Byte Tx Frame */ 1761 #define GM_TXF_1023B \ 1762 (GM_MIB_CNT_BASE + 272) /* 512-1023 Byte Tx Frame */ 1763 #define GM_TXF_1518B \ 1764 (GM_MIB_CNT_BASE + 280) /* 1024-1518 Byte Tx Frame */ 1765 #define GM_TXF_MAX_SZ \ 1766 (GM_MIB_CNT_BASE + 288) /* 1519-MaxSize Byte Tx Frame */ 1767 #define GM_TXF_SPARE1 \ 1768 (GM_MIB_CNT_BASE + 296) /* Tx spare 1 */ 1769 #define GM_TXF_COL \ 1770 (GM_MIB_CNT_BASE + 304) /* Tx Collision */ 1771 #define GM_TXF_LAT_COL \ 1772 (GM_MIB_CNT_BASE + 312) /* Tx Late Collision */ 1773 #define GM_TXF_ABO_COL \ 1774 (GM_MIB_CNT_BASE + 320) /* Tx aborted due to Exces. Col. */ 1775 #define GM_TXF_MUL_COL \ 1776 (GM_MIB_CNT_BASE + 328) /* Tx Multiple Collision */ 1777 #define GM_TXF_SNG_COL \ 1778 (GM_MIB_CNT_BASE + 336) /* Tx Single Collision */ 1779 #define GM_TXE_FIFO_UR \ 1780 (GM_MIB_CNT_BASE + 344) /* Tx FIFO Underrun Event */ 1781 1782 /*----------------------------------------------------------------------------*/ 1783 /* 1784 * GMAC Bit Definitions 1785 * 1786 * If the bit access behaviour differs from the register access behaviour 1787 * (r/w, r/o) this is documented after the bit number. 1788 * The following bit access behaviours are used: 1789 * (sc) self clearing 1790 * (r/o) read only 1791 */ 1792 1793 /* GM_GP_STAT 16 bit r/o General Purpose Status Register */ 1794 #define GM_GPSR_SPEED BIT_15 /* Port Speed (1 = 100 Mbps) */ 1795 #define GM_GPSR_DUPLEX BIT_14 /* Duplex Mode (1 = Full) */ 1796 #define GM_GPSR_FC_TX_DIS BIT_13 /* Tx Flow-Control Mode Disabled */ 1797 #define GM_GPSR_LINK_UP BIT_12 /* Link Up Status */ 1798 #define GM_GPSR_PAUSE BIT_11 /* Pause State */ 1799 #define GM_GPSR_TX_ACTIVE BIT_10 /* Tx in Progress */ 1800 #define GM_GPSR_EXC_COL BIT_9 /* Excessive Collisions Occured */ 1801 #define GM_GPSR_LAT_COL BIT_8 /* Late Collisions Occured */ 1802 #define GM_GPSR_PHY_ST_CH BIT_5 /* PHY Status Change */ 1803 #define GM_GPSR_GIG_SPEED BIT_4 /* Gigabit Speed (1 = 1000 Mbps) */ 1804 #define GM_GPSR_PART_MODE BIT_3 /* Partition mode */ 1805 #define GM_GPSR_FC_RX_DIS BIT_2 /* Rx Flow-Control Mode Disabled */ 1806 1807 /* GM_GP_CTRL 16 bit r/w General Purpose Control Register */ 1808 #define GM_GPCR_RMII_PH_ENA BIT_15 /* Enable RMII for PHY (Yukon-FE only) */ 1809 #define GM_GPCR_RMII_LB_ENA BIT_14 /* Enable RMII Loopback (Yukon-FE only) */ 1810 #define GM_GPCR_FC_TX_DIS BIT_13 /* Disable Tx Flow-Control Mode */ 1811 #define GM_GPCR_TX_ENA BIT_12 /* Enable Transmit */ 1812 #define GM_GPCR_RX_ENA BIT_11 /* Enable Receive */ 1813 #define GM_GPCR_LOOP_ENA BIT_9 /* Enable MAC Loopback Mode */ 1814 #define GM_GPCR_PART_ENA BIT_8 /* Enable Partition Mode */ 1815 #define GM_GPCR_GIGS_ENA BIT_7 /* Gigabit Speed (1000 Mbps) */ 1816 #define GM_GPCR_FL_PASS BIT_6 /* Force Link Pass */ 1817 #define GM_GPCR_DUP_FULL BIT_5 /* Full Duplex Mode */ 1818 #define GM_GPCR_FC_RX_DIS BIT_4 /* Disable Rx Flow-Control Mode */ 1819 #define GM_GPCR_SPEED_100 BIT_3 /* Port Speed 100 Mbps */ 1820 #define GM_GPCR_AU_DUP_DIS BIT_2 /* Disable Auto-Update Duplex */ 1821 #define GM_GPCR_AU_FCT_DIS BIT_1 /* Disable Auto-Update Flow-C. */ 1822 #define GM_GPCR_AU_SPD_DIS BIT_0 /* Disable Auto-Update Speed */ 1823 1824 #define GM_GPCR_SPEED_1000 (GM_GPCR_GIGS_ENA | GM_GPCR_SPEED_100) 1825 #define GM_GPCR_AU_ALL_DIS (GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS |\ 1826 GM_GPCR_AU_SPD_DIS) 1827 1828 /* GM_TX_CTRL 16 bit r/w Transmit Control Register */ 1829 #define GM_TXCR_FORCE_JAM BIT_15 /* Force Jam / Flow-Control */ 1830 #define GM_TXCR_CRC_DIS BIT_14 /* Disable insertion of CRC */ 1831 #define GM_TXCR_PAD_DIS BIT_13 /* Disable padding of packets */ 1832 #define GM_TXCR_COL_THR_MSK (7<<10) /* Bit 12..10: Collision Threshold Mask */ 1833 #define GM_TXCR_PAD_PAT_MSK 0xff /* Bit 7.. 0: Padding Pattern Mask */ 1834 /* (Yukon-2 only) */ 1835 1836 #define TX_COL_THR(x) (SHIFT10(x) & GM_TXCR_COL_THR_MSK) 1837 #define TX_COL_DEF 0x04 1838 1839 /* GM_RX_CTRL 16 bit r/w Receive Control Register */ 1840 #define GM_RXCR_UCF_ENA BIT_15 /* Enable Unicast filtering */ 1841 #define GM_RXCR_MCF_ENA BIT_14 /* Enable Multicast filtering */ 1842 #define GM_RXCR_CRC_DIS BIT_13 /* Remove 4-byte CRC */ 1843 #define GM_RXCR_PASS_FC BIT_12 /* Pass FC packets to FIFO (Yukon-1 only) */ 1844 1845 /* GM_TX_PARAM 16 bit r/w Transmit Parameter Register */ 1846 #define GM_TXPA_JAMLEN_MSK (3<<14) /* Bit 15..14: Jam Length Mask */ 1847 #define GM_TXPA_JAMIPG_MSK (0x1f<<9) /* Bit 13.. 9: Jam IPG Mask */ 1848 #define GM_TXPA_JAMDAT_MSK (0x1f<<4) /* Bit 8.. 4: IPG Jam to Data Mask */ 1849 #define GM_TXPA_BO_LIM_MSK 0x0f /* Bit 3.. 0: Backoff Limit Mask */ 1850 /* (Yukon-2 only) */ 1851 1852 #define TX_JAM_LEN_VAL(x) (SHIFT14(x) & GM_TXPA_JAMLEN_MSK) 1853 #define TX_JAM_IPG_VAL(x) (SHIFT9(x) & GM_TXPA_JAMIPG_MSK) 1854 #define TX_IPG_JAM_DATA(x) (SHIFT4(x) & GM_TXPA_JAMDAT_MSK) 1855 #define TX_BACK_OFF_LIM(x) ((x) & GM_TXPA_BO_LIM_MSK) 1856 1857 #define TX_JAM_LEN_DEF 0x03 1858 #define TX_JAM_IPG_DEF 0x0b 1859 #define TX_IPG_JAM_DEF 0x1c 1860 #define TX_BOF_LIM_DEF 0x04 1861 1862 /* GM_SERIAL_MODE 16 bit r/w Serial Mode Register */ 1863 #define GM_SMOD_DATABL_MSK (0x1f<<11) /* Bit 15..11: Data Blinder */ 1864 /* r/o on Yukon, r/w on Yukon-EC */ 1865 #define GM_SMOD_LIMIT_4 BIT_10 /* 4 consecutive Tx trials */ 1866 #define GM_SMOD_VLAN_ENA BIT_9 /* Enable VLAN (Max. Frame Len) */ 1867 #define GM_SMOD_JUMBO_ENA BIT_8 /* Enable Jumbo (Max. Frame Len) */ 1868 #define GM_SMOD_IPG_MSK 0x1f /* Bit 4.. 0: Inter-Packet Gap (IPG) */ 1869 1870 #define DATA_BLIND_VAL(x) (SHIFT11(x) & GM_SMOD_DATABL_MSK) 1871 #define IPG_DATA_VAL(x) ((x) & GM_SMOD_IPG_MSK) 1872 1873 #define DATA_BLIND_DEF 0x04 1874 #define IPG_DATA_DEF 0x1e 1875 1876 /* GM_SMI_CTRL 16 bit r/w SMI Control Register */ 1877 #define GM_SMI_CT_PHY_A_MSK (0x1f<<11) /* Bit 15..11: PHY Device Address */ 1878 #define GM_SMI_CT_REG_A_MSK (0x1f<<6) /* Bit 10.. 6: PHY Register Address */ 1879 #define GM_SMI_CT_OP_RD BIT_5 /* OpCode Read (0=Write)*/ 1880 #define GM_SMI_CT_RD_VAL BIT_4 /* Read Valid (Read completed) */ 1881 #define GM_SMI_CT_BUSY BIT_3 /* Busy (Operation in progress) */ 1882 1883 #define GM_SMI_CT_PHY_AD(x) (SHIFT11(x) & GM_SMI_CT_PHY_A_MSK) 1884 #define GM_SMI_CT_REG_AD(x) (SHIFT6(x) & GM_SMI_CT_REG_A_MSK) 1885 1886 /* GM_PHY_ADDR 16 bit r/w GPHY Address Register */ 1887 #define GM_PAR_MIB_CLR BIT_5 /* Set MIB Clear Counter Mode */ 1888 #define GM_PAR_MIB_TST BIT_4 /* MIB Load Counter (Test Mode) */ 1889 1890 /* Receive Frame Status Encoding */ 1891 #define GMR_FS_LEN_MSK (0xffff<<16) /* Bit 31..16: Rx Frame Length */ 1892 #define GMR_FS_VLAN BIT_13 /* VLAN Packet */ 1893 #define GMR_FS_JABBER BIT_12 /* Jabber Packet */ 1894 #define GMR_FS_UN_SIZE BIT_11 /* Undersize Packet */ 1895 #define GMR_FS_MC BIT_10 /* Multicast Packet */ 1896 #define GMR_FS_BC BIT_9 /* Broadcast Packet */ 1897 #define GMR_FS_RX_OK BIT_8 /* Receive OK (Good Packet) */ 1898 #define GMR_FS_GOOD_FC BIT_7 /* Good Flow-Control Packet */ 1899 #define GMR_FS_BAD_FC BIT_6 /* Bad Flow-Control Packet */ 1900 #define GMR_FS_MII_ERR BIT_5 /* MII Error */ 1901 #define GMR_FS_LONG_ERR BIT_4 /* Too Long Packet */ 1902 #define GMR_FS_FRAGMENT BIT_3 /* Fragment */ 1903 #define GMR_FS_CRC_ERR BIT_1 /* CRC Error */ 1904 #define GMR_FS_RX_FF_OV BIT_0 /* Rx FIFO Overflow */ 1905 1906 #define GMR_FS_LEN_SHIFT 16 1907 1908 #define GMR_FS_ANY_ERR ( \ 1909 GMR_FS_RX_FF_OV | \ 1910 GMR_FS_CRC_ERR | \ 1911 GMR_FS_FRAGMENT | \ 1912 GMR_FS_LONG_ERR | \ 1913 GMR_FS_MII_ERR | \ 1914 GMR_FS_BAD_FC | \ 1915 GMR_FS_GOOD_FC | \ 1916 GMR_FS_UN_SIZE | \ 1917 GMR_FS_JABBER) 1918 1919 /* Rx GMAC FIFO Flush Mask (default) */ 1920 #define RX_FF_FL_DEF_MSK GMR_FS_ANY_ERR 1921 1922 /* Receive and Transmit GMAC FIFO Registers (YUKON only) */ 1923 1924 /* RX_GMF_EA 32 bit Rx GMAC FIFO End Address */ 1925 /* RX_GMF_AF_THR 32 bit Rx GMAC FIFO Almost Full Thresh. */ 1926 /* RX_GMF_WP 32 bit Rx GMAC FIFO Write Pointer */ 1927 /* RX_GMF_WLEV 32 bit Rx GMAC FIFO Write Level */ 1928 /* RX_GMF_RP 32 bit Rx GMAC FIFO Read Pointer */ 1929 /* RX_GMF_RLEV 32 bit Rx GMAC FIFO Read Level */ 1930 /* TX_GMF_EA 32 bit Tx GMAC FIFO End Address */ 1931 /* TX_GMF_AE_THR 32 bit Tx GMAC FIFO Almost Empty Thresh.*/ 1932 /* TX_GMF_WP 32 bit Tx GMAC FIFO Write Pointer */ 1933 /* TX_GMF_WSP 32 bit Tx GMAC FIFO Write Shadow Pointer */ 1934 /* TX_GMF_WLEV 32 bit Tx GMAC FIFO Write Level */ 1935 /* TX_GMF_RP 32 bit Tx GMAC FIFO Read Pointer */ 1936 /* TX_GMF_RSTP 32 bit Tx GMAC FIFO Restart Pointer */ 1937 /* TX_GMF_RLEV 32 bit Tx GMAC FIFO Read Level */ 1938 1939 /* RX_GMF_CTRL_T 32 bit Rx GMAC FIFO Control/Test */ 1940 #define RX_TRUNC_ON BIT_27 /* enable packet truncation */ 1941 #define RX_TRUNC_OFF BIT_26 /* disable packet truncation */ 1942 #define RX_VLAN_STRIP_ON BIT_25 /* enable VLAN stripping */ 1943 #define RX_VLAN_STRIP_OFF BIT_24 /* disable VLAN stripping */ 1944 #define GMF_RX_OVER_ON BIT_19 /* enable flushing on receive overrun */ 1945 #define GMF_RX_OVER_OFF BIT_18 /* disable flushing on receive overrun */ 1946 #define GMF_ASF_RX_OVER_ON BIT_17 /* enable flushing of ASF when overrun */ 1947 #define GMF_ASF_RX_OVER_OFF BIT_16 /* disable flushing of ASF when overrun */ 1948 #define GMF_WP_TST_ON BIT_14 /* Write Pointer Test On */ 1949 #define GMF_WP_TST_OFF BIT_13 /* Write Pointer Test Off */ 1950 #define GMF_WP_STEP BIT_12 /* Write Pointer Step/Increment */ 1951 #define GMF_RP_TST_ON BIT_10 /* Read Pointer Test On */ 1952 #define GMF_RP_TST_OFF BIT_9 /* Read Pointer Test Off */ 1953 #define GMF_RP_STEP BIT_8 /* Read Pointer Step/Increment */ 1954 #define GMF_RX_F_FL_ON BIT_7 /* Rx FIFO Flush Mode On */ 1955 #define GMF_RX_F_FL_OFF BIT_6 /* Rx FIFO Flush Mode Off */ 1956 #define GMF_CLI_RX_FO BIT_5 /* Clear IRQ Rx FIFO Overrun */ 1957 #define GMF_CLI_RX_FC BIT_4 /* Clear IRQ Rx Frame Complete */ 1958 #define GMF_OPER_ON BIT_3 /* Operational Mode On */ 1959 #define GMF_OPER_OFF BIT_2 /* Operational Mode Off */ 1960 #define GMF_RST_CLR BIT_1 /* Clear GMAC FIFO Reset */ 1961 #define GMF_RST_SET BIT_0 /* Set GMAC FIFO Reset */ 1962 1963 /* TX_GMF_CTRL_T 32 bit Tx GMAC FIFO Control/Test (YUKON and Yukon-2) */ 1964 #define TX_STFW_DIS BIT_31 /* Disable Store & Forward (Yukon-EC Ultra) */ 1965 #define TX_STFW_ENA BIT_30 /* Enable Store & Forward (Yukon-EC Ultra) */ 1966 #define TX_VLAN_TAG_ON BIT_25 /* enable VLAN tagging */ 1967 #define TX_VLAN_TAG_OFF BIT_24 /* disable VLAN tagging */ 1968 #define TX_JUMBO_ENA BIT_23 /* Enable Jumbo Mode (Yukon-EC Ultra) */ 1969 #define TX_JUMBO_DIS BIT_22 /* Disable Jumbo Mode (Yukon-EC Ultra) */ 1970 #define GMF_WSP_TST_ON BIT_18 /* Write Shadow Pointer Test On */ 1971 #define GMF_WSP_TST_OFF BIT_17 /* Write Shadow Pointer Test Off */ 1972 #define GMF_WSP_STEP BIT_16 /* Write Shadow Pointer Step/Increment */ 1973 /* Bits 15..8: same as for RX_GMF_CTRL_T */ 1974 #define GMF_CLI_TX_FU BIT_6 /* Clear IRQ Tx FIFO Underrun */ 1975 #define GMF_CLI_TX_FC BIT_5 /* Clear IRQ Tx Frame Complete */ 1976 #define GMF_CLI_TX_PE BIT_4 /* Clear IRQ Tx Parity Error */ 1977 /* Bits 3..0: same as for RX_GMF_CTRL_T */ 1978 1979 #define GMF_RX_CTRL_DEF (GMF_OPER_ON | GMF_RX_F_FL_ON) 1980 #define GMF_TX_CTRL_DEF GMF_OPER_ON 1981 1982 #define RX_GMF_AF_THR_MIN 0x0c /* Rx GMAC FIFO Almost Full Thresh. min. */ 1983 #define RX_GMF_FL_THR_DEF 0x0a /* Rx GMAC FIFO Flush Threshold default */ 1984 1985 /* GMAC_TI_ST_CTRL 8 bit Time Stamp Timer Ctrl Reg (YUKON only) */ 1986 #define GMT_ST_START BIT_2 /* Start Time Stamp Timer */ 1987 #define GMT_ST_STOP BIT_1 /* Stop Time Stamp Timer */ 1988 #define GMT_ST_CLR_IRQ BIT_0 /* Clear Time Stamp Timer IRQ */ 1989 1990 /* POLL_CTRL 32 bit Polling Unit control register (Yukon-2 only) */ 1991 #define PC_CLR_IRQ_CHK BIT_5 /* Clear IRQ Check */ 1992 #define PC_POLL_RQ BIT_4 /* Poll Request Start */ 1993 #define PC_POLL_OP_ON BIT_3 /* Operational Mode On */ 1994 #define PC_POLL_OP_OFF BIT_2 /* Operational Mode Off */ 1995 #define PC_POLL_RST_CLR BIT_1 /* Clear Polling Unit Reset (Enable) */ 1996 #define PC_POLL_RST_SET BIT_0 /* Set Polling Unit Reset */ 1997 1998 /* B28_Y2_ASF_STAT_CMD 32 bit ASF Status and Command Reg */ 1999 /* This register is used by the host driver software */ 2000 #define Y2_ASF_OS_PRES BIT_4 /* ASF operation system present */ 2001 #define Y2_ASF_RESET BIT_3 /* ASF system in reset state */ 2002 #define Y2_ASF_RUNNING BIT_2 /* ASF system operational */ 2003 #define Y2_ASF_CLR_HSTI BIT_1 /* Clear ASF IRQ */ 2004 #define Y2_ASF_IRQ BIT_0 /* Issue an IRQ to ASF system */ 2005 2006 #define Y2_ASF_UC_STATE (3<<2) /* ASF uC State */ 2007 #define Y2_ASF_CLK_HALT 0 /* ASF system clock stopped */ 2008 2009 /* B28_Y2_ASF_HCU_CCSR 32bit CPU Control and Status Register (Yukon EX) */ 2010 #define Y2_ASF_HCU_CCSR_SMBALERT_MONITOR BIT_27 /* SMBALERT pin monitor */ 2011 #define Y2_ASF_HCU_CCSR_CPU_SLEEP BIT_26 /* CPU sleep status */ 2012 #define Y2_ASF_HCU_CCSR_CS_TO BIT_25 /* Clock Stretching Timeout */ 2013 #define Y2_ASF_HCU_CCSR_WDOG BIT_24 /* Watchdog Reset */ 2014 #define Y2_ASF_HCU_CCSR_CLR_IRQ_HOST BIT_17 /* Clear IRQ_HOST */ 2015 #define Y2_ASF_HCU_CCSR_SET_IRQ_HCU BIT_16 /* Set IRQ_HCU */ 2016 #define Y2_ASF_HCU_CCSR_AHB_RST BIT_9 /* Reset AHB bridge */ 2017 #define Y2_ASF_HCU_CCSR_CPU_RST_MODE BIT_8 /* CPU Reset Mode */ 2018 #define Y2_ASF_HCU_CCSR_SET_SYNC_CPU BIT_5 2019 #define Y2_ASF_HCU_CCSR_CPU_CLK_DIVIDE1 BIT_4 2020 #define Y2_ASF_HCU_CCSR_CPU_CLK_DIVIDE0 BIT_3 2021 #define Y2_ASF_HCU_CCSR_CPU_CLK_DIVIDE_MSK (BIT_4 | BIT_3) /* CPU Clock Divide */ 2022 #define Y2_ASF_HCU_CCSR_CPU_CLK_DIVIDE_BASE BIT_3 2023 #define Y2_ASF_HCU_CCSR_OS_PRSNT BIT_2 /* ASF OS Present */ 2024 /* Microcontroller State */ 2025 #define Y2_ASF_HCU_CCSR_UC_STATE_MSK 3 2026 #define Y2_ASF_HCU_CCSR_UC_STATE_BASE BIT_0 2027 #define Y2_ASF_HCU_CCSR_ASF_RESET 0 2028 #define Y2_ASF_HCU_CCSR_ASF_HALTED BIT_1 2029 #define Y2_ASF_HCU_CCSR_ASF_RUNNING BIT_0 2030 2031 /* B28_Y2_ASF_HOST_COM 32 bit ASF Host Communication Reg */ 2032 /* This register is used by the ASF firmware */ 2033 #define Y2_ASF_CLR_ASFI BIT_1 /* Clear host IRQ */ 2034 #define Y2_ASF_HOST_IRQ BIT_0 /* Issue an IRQ to HOST system */ 2035 2036 /* STAT_CTRL 32 bit Status BMU control register (Yukon-2 only) */ 2037 #define SC_STAT_CLR_IRQ BIT_4 /* Status Burst IRQ clear */ 2038 #define SC_STAT_OP_ON BIT_3 /* Operational Mode On */ 2039 #define SC_STAT_OP_OFF BIT_2 /* Operational Mode Off */ 2040 #define SC_STAT_RST_CLR BIT_1 /* Clear Status Unit Reset (Enable) */ 2041 #define SC_STAT_RST_SET BIT_0 /* Set Status Unit Reset */ 2042 2043 /* GMAC_CTRL 32 bit GMAC Control Reg (YUKON only) */ 2044 #define GMC_SEC_RST BIT_15 /* MAC SEC RST */ 2045 #define GMC_SEC_RST_OFF BIT_14 /* MAC SEC RST Off */ 2046 #define GMC_BYP_MACSECRX_ON BIT_13 /* Bypass MAC SEC RX */ 2047 #define GMC_BYP_MACSECRX_OFF BIT_12 /* Bypass MAC SEC RX Off */ 2048 #define GMC_BYP_MACSECTX_ON BIT_11 /* Bypass MAC SEC TX */ 2049 #define GMC_BYP_MACSECTX_OFF BIT_10 /* Bypass MAC SEC TX Off */ 2050 #define GMC_BYP_RETR_ON BIT_9 /* Bypass MAC retransmit FIFO On */ 2051 #define GMC_BYP_RETR_OFF BIT_8 /* Bypass MAC retransmit FIFO Off */ 2052 #define GMC_H_BURST_ON BIT_7 /* Half Duplex Burst Mode On */ 2053 #define GMC_H_BURST_OFF BIT_6 /* Half Duplex Burst Mode Off */ 2054 #define GMC_F_LOOPB_ON BIT_5 /* FIFO Loopback On */ 2055 #define GMC_F_LOOPB_OFF BIT_4 /* FIFO Loopback Off */ 2056 #define GMC_PAUSE_ON BIT_3 /* Pause On */ 2057 #define GMC_PAUSE_OFF BIT_2 /* Pause Off */ 2058 #define GMC_RST_CLR BIT_1 /* Clear GMAC Reset */ 2059 #define GMC_RST_SET BIT_0 /* Set GMAC Reset */ 2060 2061 /* GPHY_CTRL 32 bit GPHY Control Reg (YUKON only) */ 2062 #define GPC_SEL_BDT BIT_28 /* Select Bi-Dir. Transfer for MDC/MDIO */ 2063 #define GPC_INT_POL BIT_27 /* IRQ Polarity is Active Low */ 2064 #define GPC_75_OHM BIT_26 /* Use 75 Ohm Termination instead of 50 */ 2065 #define GPC_DIS_FC BIT_25 /* Disable Automatic Fiber/Copper Detection */ 2066 #define GPC_DIS_SLEEP BIT_24 /* Disable Energy Detect */ 2067 #define GPC_HWCFG_M_3 BIT_23 /* HWCFG_MODE[3] */ 2068 #define GPC_HWCFG_M_2 BIT_22 /* HWCFG_MODE[2] */ 2069 #define GPC_HWCFG_M_1 BIT_21 /* HWCFG_MODE[1] */ 2070 #define GPC_HWCFG_M_0 BIT_20 /* HWCFG_MODE[0] */ 2071 #define GPC_ANEG_0 BIT_19 /* ANEG[0] */ 2072 #define GPC_ENA_XC BIT_18 /* Enable MDI crossover */ 2073 #define GPC_DIS_125 BIT_17 /* Disable 125 MHz clock */ 2074 #define GPC_ANEG_3 BIT_16 /* ANEG[3] */ 2075 #define GPC_ANEG_2 BIT_15 /* ANEG[2] */ 2076 #define GPC_ANEG_1 BIT_14 /* ANEG[1] */ 2077 #define GPC_ENA_PAUSE BIT_13 /* Enable Pause (SYM_OR_REM) */ 2078 #define GPC_PHYADDR_4 BIT_12 /* Bit 4 of Phy Addr */ 2079 #define GPC_PHYADDR_3 BIT_11 /* Bit 3 of Phy Addr */ 2080 #define GPC_PHYADDR_2 BIT_10 /* Bit 2 of Phy Addr */ 2081 #define GPC_PHYADDR_1 BIT_9 /* Bit 1 of Phy Addr */ 2082 #define GPC_PHYADDR_0 BIT_8 /* Bit 0 of Phy Addr */ 2083 #define GPC_RST_CLR BIT_1 /* Clear GPHY Reset */ 2084 #define GPC_RST_SET BIT_0 /* Set GPHY Reset */ 2085 2086 /* GMAC_IRQ_SRC 8 bit GMAC Interrupt Source Reg (YUKON only) */ 2087 /* GMAC_IRQ_MSK 8 bit GMAC Interrupt Mask Reg (YUKON only) */ 2088 #define GM_IS_RX_CO_OV BIT_5 /* Receive Counter Overflow IRQ */ 2089 #define GM_IS_TX_CO_OV BIT_4 /* Transmit Counter Overflow IRQ */ 2090 #define GM_IS_TX_FF_UR BIT_3 /* Transmit FIFO Underrun */ 2091 #define GM_IS_TX_COMPL BIT_2 /* Frame Transmission Complete */ 2092 #define GM_IS_RX_FF_OR BIT_1 /* Receive FIFO Overrun */ 2093 #define GM_IS_RX_COMPL BIT_0 /* Frame Reception Complete */ 2094 2095 #define GMAC_DEF_MSK (GM_IS_RX_CO_OV | GM_IS_TX_CO_OV | GM_IS_TX_FF_UR) 2096 2097 /* GMAC_LINK_CTRL 16 bit GMAC Link Control Reg (YUKON only) */ 2098 #define GMLC_RST_CLR BIT_1 /* Clear GMAC Link Reset */ 2099 #define GMLC_RST_SET BIT_0 /* Set GMAC Link Reset */ 2100 2101 #define MSK_PORT_A 0 2102 #define MSK_PORT_B 1 2103 2104 /* Register access macros */ 2105 #define CSR_WRITE_4(sc, reg, val) \ 2106 bus_write_4((sc)->msk_res[0], (reg), (val)) 2107 #define CSR_WRITE_2(sc, reg, val) \ 2108 bus_write_2((sc)->msk_res[0], (reg), (val)) 2109 #define CSR_WRITE_1(sc, reg, val) \ 2110 bus_write_1((sc)->msk_res[0], (reg), (val)) 2111 2112 #define CSR_READ_4(sc, reg) \ 2113 bus_read_4((sc)->msk_res[0], (reg)) 2114 #define CSR_READ_2(sc, reg) \ 2115 bus_read_2((sc)->msk_res[0], (reg)) 2116 #define CSR_READ_1(sc, reg) \ 2117 bus_read_1((sc)->msk_res[0], (reg)) 2118 2119 #define CSR_PCI_WRITE_4(sc, reg, val) \ 2120 bus_write_4((sc)->msk_res[0], Y2_CFG_SPC + (reg), (val)) 2121 #define CSR_PCI_WRITE_2(sc, reg, val) \ 2122 bus_write_2((sc)->msk_res[0], Y2_CFG_SPC + (reg), (val)) 2123 #define CSR_PCI_WRITE_1(sc, reg, val) \ 2124 bus_write_1((sc)->msk_res[0], Y2_CFG_SPC + (reg), (val)) 2125 2126 #define CSR_PCI_READ_4(sc, reg) \ 2127 bus_read_4((sc)->msk_res[0], Y2_CFG_SPC + (reg)) 2128 #define CSR_PCI_READ_2(sc, reg) \ 2129 bus_read_2((sc)->msk_res[0], Y2_CFG_SPC + (reg)) 2130 #define CSR_PCI_READ_1(sc, reg) \ 2131 bus_read_1((sc)->msk_res[0], Y2_CFG_SPC + (reg)) 2132 2133 #define MSK_IF_READ_4(sc_if, reg) \ 2134 CSR_READ_4((sc_if)->msk_softc, (reg)) 2135 #define MSK_IF_READ_2(sc_if, reg) \ 2136 CSR_READ_2((sc_if)->msk_softc, (reg)) 2137 #define MSK_IF_READ_1(sc_if, reg) \ 2138 CSR_READ_1((sc_if)->msk_softc, (reg)) 2139 2140 #define MSK_IF_WRITE_4(sc_if, reg, val) \ 2141 CSR_WRITE_4((sc_if)->msk_softc, (reg), (val)) 2142 #define MSK_IF_WRITE_2(sc_if, reg, val) \ 2143 CSR_WRITE_2((sc_if)->msk_softc, (reg), (val)) 2144 #define MSK_IF_WRITE_1(sc_if, reg, val) \ 2145 CSR_WRITE_1((sc_if)->msk_softc, (reg), (val)) 2146 2147 #define GMAC_REG(port, reg) \ 2148 ((BASE_GMAC_1 + (port) * (BASE_GMAC_2 - BASE_GMAC_1)) | (reg)) 2149 #define GMAC_WRITE_2(sc, port, reg, val) \ 2150 CSR_WRITE_2((sc), GMAC_REG((port), (reg)), (val)) 2151 #define GMAC_READ_2(sc, port, reg) \ 2152 CSR_READ_2((sc), GMAC_REG((port), (reg))) 2153 2154 /* GPHY address (bits 15..11 of SMI control reg) */ 2155 #define PHY_ADDR_MARV 0 2156 2157 #define MSK_ADDR_LO(x) ((uint64_t) (x) & 0xffffffffUL) 2158 #define MSK_ADDR_HI(x) ((uint64_t) (x) >> 32) 2159 2160 /* 2161 * At first I guessed 8 bytes, the size of a single descriptor, would be 2162 * required alignment constraints. But, it seems that Yukon II have 4096 2163 * bytes boundary alignment constraints. 2164 */ 2165 #define MSK_RING_ALIGN 4096 2166 #define MSK_STAT_ALIGN 4096 2167 2168 /* Rx descriptor data structure */ 2169 struct msk_rx_desc { 2170 uint32_t msk_addr; 2171 uint32_t msk_control; 2172 }; 2173 2174 /* Tx descriptor data structure */ 2175 struct msk_tx_desc { 2176 uint32_t msk_addr; 2177 uint32_t msk_control; 2178 }; 2179 2180 /* Status descriptor data structure */ 2181 struct msk_stat_desc { 2182 uint32_t msk_status; 2183 uint32_t msk_control; 2184 }; 2185 2186 /* mask and shift value to get Tx async queue status for port 1 */ 2187 #define STLE_TXA1_MSKL 0x00000fff 2188 #define STLE_TXA1_SHIFTL 0 2189 2190 /* mask and shift value to get Tx sync queue status for port 1 */ 2191 #define STLE_TXS1_MSKL 0x00fff000 2192 #define STLE_TXS1_SHIFTL 12 2193 2194 /* mask and shift value to get Tx async queue status for port 2 */ 2195 #define STLE_TXA2_MSKL 0xff000000 2196 #define STLE_TXA2_SHIFTL 24 2197 #define STLE_TXA2_MSKH 0x000f 2198 /* this one shifts up */ 2199 #define STLE_TXA2_SHIFTH 8 2200 2201 /* mask and shift value to get Tx sync queue status for port 2 */ 2202 #define STLE_TXS2_MSKL 0x00000000 2203 #define STLE_TXS2_SHIFTL 0 2204 #define STLE_TXS2_MSKH 0xfff0 2205 #define STLE_TXS2_SHIFTH 4 2206 2207 /* YUKON-2 bit values */ 2208 #define HW_OWNER 0x80000000 2209 #define SW_OWNER 0x00000000 2210 2211 #define PU_PUTIDX_VALID 0x10000000 2212 2213 /* YUKON-2 Control flags */ 2214 #define UDPTCP 0x00010000 2215 #define CALSUM 0x00020000 2216 #define WR_SUM 0x00040000 2217 #define INIT_SUM 0x00080000 2218 #define LOCK_SUM 0x00100000 2219 #define INS_VLAN 0x00200000 2220 #define FRC_STAT 0x00400000 2221 #define EOP 0x00800000 2222 2223 #define TX_LOCK 0x01000000 2224 #define BUF_SEND 0x02000000 2225 #define PACKET_SEND 0x04000000 2226 2227 #define NO_WARNING 0x40000000 2228 #define NO_UPDATE 0x80000000 2229 2230 /* YUKON-2 Rx/Tx opcodes defines */ 2231 #define OP_TCPWRITE 0x11000000 2232 #define OP_TCPSTART 0x12000000 2233 #define OP_TCPINIT 0x14000000 2234 #define OP_TCPLCK 0x18000000 2235 #define OP_TCPCHKSUM OP_TCPSTART 2236 #define OP_TCPIS (OP_TCPINIT | OP_TCPSTART) 2237 #define OP_TCPLW (OP_TCPLCK | OP_TCPWRITE) 2238 #define OP_TCPLSW (OP_TCPLCK | OP_TCPSTART | OP_TCPWRITE) 2239 #define OP_TCPLISW (OP_TCPLCK | OP_TCPINIT | OP_TCPSTART | OP_TCPWRITE) 2240 #define OP_ADDR64 0x21000000 2241 #define OP_VLAN 0x22000000 2242 #define OP_ADDR64VLAN (OP_ADDR64 | OP_VLAN) 2243 #define OP_LRGLEN 0x24000000 2244 #define OP_LRGLENVLAN (OP_LRGLEN | OP_VLAN) 2245 #define OP_MSS 0x28000000 2246 #define OP_MSSVLAN (OP_MSS | OP_VLAN) 2247 #define OP_BUFFER 0x40000000 2248 #define OP_PACKET 0x41000000 2249 #define OP_LARGESEND 0x43000000 2250 2251 /* YUKON-2 STATUS opcodes defines */ 2252 #define OP_RXSTAT 0x60000000 2253 #define OP_RXTIMESTAMP 0x61000000 2254 #define OP_RXVLAN 0x62000000 2255 #define OP_RXCHKS 0x64000000 2256 #define OP_RXCHKSVLAN (OP_RXCHKS | OP_RXVLAN) 2257 #define OP_RXTIMEVLAN (OP_RXTIMESTAMP | OP_RXVLAN) 2258 #define OP_RSS_HASH 0x65000000 2259 #define OP_TXINDEXLE 0x68000000 2260 2261 /* YUKON-2 SPECIAL opcodes defines */ 2262 #define OP_PUTIDX 0x70000000 2263 2264 #define STLE_OP_MASK 0xff000000 2265 #define STLE_CSS_MASK 0x00ff0000 2266 #define STLE_LEN_MASK 0x0000ffff 2267 2268 /* CSS defined in status LE(valid for descriptor V2 format). */ 2269 #define CSS_TCPUDP_CSUM_OK 0x00800000 2270 #define CSS_UDP 0x00400000 2271 #define CSS_TCP 0x00200000 2272 #define CSS_IPFRAG 0x00100000 2273 #define CSS_IPV6 0x00080000 2274 #define CSS_IPV4_CSUM_OK 0x00040000 2275 #define CSS_IPV4 0x00020000 2276 #define CSS_PORT 0x00010000 2277 2278 /* Descriptor Bit Definition */ 2279 /* TxCtrl Transmit Buffer Control Field */ 2280 /* RxCtrl Receive Buffer Control Field */ 2281 #define BMU_OWN BIT_31 /* OWN bit: 0=host/1=BMU */ 2282 #define BMU_STF BIT_30 /* Start of Frame */ 2283 #define BMU_EOF BIT_29 /* End of Frame */ 2284 #define BMU_IRQ_EOB BIT_28 /* Req "End of Buffer" IRQ */ 2285 #define BMU_IRQ_EOF BIT_27 /* Req "End of Frame" IRQ */ 2286 /* TxCtrl specific bits */ 2287 #define BMU_STFWD BIT_26 /* (Tx) Store & Forward Frame */ 2288 #define BMU_NO_FCS BIT_25 /* (Tx) Disable MAC FCS (CRC) generation */ 2289 #define BMU_SW BIT_24 /* (Tx) 1 bit res. for SW use */ 2290 /* RxCtrl specific bits */ 2291 #define BMU_DEV_0 BIT_26 /* (Rx) Transfer data to Dev0 */ 2292 #define BMU_STAT_VAL BIT_25 /* (Rx) Rx Status Valid */ 2293 #define BMU_TIST_VAL BIT_24 /* (Rx) Rx TimeStamp Valid */ 2294 /* Bit 23..16: BMU Check Opcodes */ 2295 #define BMU_CHECK (0x55<<16) /* Default BMU check */ 2296 #define BMU_TCP_CHECK (0x56<<16) /* Descr with TCP ext */ 2297 #define BMU_UDP_CHECK (0x57<<16) /* Descr with UDP ext (YUKON only) */ 2298 #define BMU_BBC 0xffff /* Bit 15.. 0: Buffer Byte Counter */ 2299 2300 #define MSK_TX_RING_CNT 256 2301 #define MSK_RX_RING_CNT 256 2302 #define MSK_RX_BUF_ALIGN 8 2303 #define MSK_JUMBO_RX_RING_CNT MSK_RX_RING_CNT 2304 #define MSK_STAT_RING_CNT ((1 + 3) * (MSK_TX_RING_CNT + MSK_RX_RING_CNT)) 2305 #define MSK_MAXTXSEGS 32 2306 #define MSK_TSO_MAXSGSIZE 4096 2307 #define MSK_TSO_MAXSIZE (65535 + sizeof(struct ether_vlan_header)) 2308 2309 /* 2310 * It seems that the hardware requires extra decriptors(LEs) to offload 2311 * TCP/UDP checksum, VLAN hardware tag inserstion and TSO. 2312 * 2313 * 1 descriptor for TCP/UDP checksum offload. 2314 * 1 descriptor VLAN hardware tag insertion. 2315 * 1 descriptor for TSO(TCP Segmentation Offload) 2316 * 1 descriptor for 64bits DMA : Not applicatable due to the use of 2317 * BUS_SPACE_MAXADDR_32BIT in parent DMA tag creation. 2318 */ 2319 #define MSK_RESERVED_TX_DESC_CNT 3 2320 2321 /* 2322 * Jumbo buffer stuff. Note that we must allocate more jumbo 2323 * buffers than there are descriptors in the receive ring. This 2324 * is because we don't know how long it will take for a packet 2325 * to be released after we hand it off to the upper protocol 2326 * layers. To be safe, we allocate 1.5 times the number of 2327 * receive descriptors. 2328 */ 2329 #define MSK_JUMBO_FRAMELEN 9022 2330 #define MSK_JUMBO_MTU (MSK_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN) 2331 #define MSK_MAX_FRAMELEN \ 2332 (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN - ETHER_CRC_LEN) 2333 #define MSK_MIN_FRAMELEN (ETHER_MIN_LEN - ETHER_CRC_LEN) 2334 2335 struct msk_txdesc { 2336 struct mbuf *tx_m; 2337 bus_dmamap_t tx_dmamap; 2338 struct msk_tx_desc *tx_le; 2339 }; 2340 2341 struct msk_rxdesc { 2342 struct mbuf *rx_m; 2343 bus_dmamap_t rx_dmamap; 2344 struct msk_rx_desc *rx_le; 2345 }; 2346 2347 struct msk_chain_data { 2348 bus_dma_tag_t msk_parent_tag; 2349 bus_dma_tag_t msk_tx_tag; 2350 struct msk_txdesc msk_txdesc[MSK_TX_RING_CNT]; 2351 bus_dma_tag_t msk_rx_tag; 2352 struct msk_rxdesc msk_rxdesc[MSK_RX_RING_CNT]; 2353 bus_dma_tag_t msk_tx_ring_tag; 2354 bus_dma_tag_t msk_rx_ring_tag; 2355 bus_dmamap_t msk_tx_ring_map; 2356 bus_dmamap_t msk_rx_ring_map; 2357 bus_dmamap_t msk_rx_sparemap; 2358 bus_dma_tag_t msk_jumbo_rx_tag; 2359 struct msk_rxdesc msk_jumbo_rxdesc[MSK_JUMBO_RX_RING_CNT]; 2360 bus_dma_tag_t msk_jumbo_rx_ring_tag; 2361 bus_dmamap_t msk_jumbo_rx_ring_map; 2362 bus_dmamap_t msk_jumbo_rx_sparemap; 2363 uint16_t msk_tso_mtu; 2364 int msk_tx_prod; 2365 int msk_tx_cons; 2366 int msk_tx_cnt; 2367 int msk_tx_put; 2368 int msk_rx_cons; 2369 int msk_rx_prod; 2370 int msk_rx_putwm; 2371 }; 2372 2373 struct msk_ring_data { 2374 struct msk_tx_desc *msk_tx_ring; 2375 bus_addr_t msk_tx_ring_paddr; 2376 struct msk_rx_desc *msk_rx_ring; 2377 bus_addr_t msk_rx_ring_paddr; 2378 struct msk_rx_desc *msk_jumbo_rx_ring; 2379 bus_addr_t msk_jumbo_rx_ring_paddr; 2380 }; 2381 2382 #define MSK_TX_RING_ADDR(sc, i) \ 2383 ((sc)->msk_rdata.msk_tx_ring_paddr + sizeof(struct msk_tx_desc) * (i)) 2384 #define MSK_RX_RING_ADDR(sc, i) \ 2385 ((sc)->msk_rdata.msk_rx_ring_paddr + sizeof(struct msk_rx_desc) * (i)) 2386 #define MSK_JUMBO_RX_RING_ADDR(sc, i) \ 2387 ((sc)->msk_rdata.msk_jumbo_rx_ring_paddr + sizeof(struct msk_rx_desc) * (i)) 2388 2389 #define MSK_TX_RING_SZ \ 2390 (sizeof(struct msk_tx_desc) * MSK_TX_RING_CNT) 2391 #define MSK_RX_RING_SZ \ 2392 (sizeof(struct msk_rx_desc) * MSK_RX_RING_CNT) 2393 #define MSK_JUMBO_RX_RING_SZ \ 2394 (sizeof(struct msk_rx_desc) * MSK_JUMBO_RX_RING_CNT) 2395 #define MSK_STAT_RING_SZ \ 2396 (sizeof(struct msk_stat_desc) * MSK_STAT_RING_CNT) 2397 2398 #define MSK_INC(x, y) (x) = (x + 1) % y 2399 2400 #define MSK_PCI_BUS 0 2401 #define MSK_PCIX_BUS 1 2402 #define MSK_PEX_BUS 2 2403 2404 #define MSK_PROC_DEFAULT (MSK_RX_RING_CNT / 2) 2405 #define MSK_PROC_MIN 30 2406 #define MSK_PROC_MAX (MSK_RX_RING_CNT - 1) 2407 2408 #define MSK_TX_TIMEOUT 5 2409 #define MSK_PUT_WM 10 2410 2411 struct msk_mii_data { 2412 int port; 2413 uint32_t pmd; 2414 int mii_flags; 2415 }; 2416 2417 /* Forward decl. */ 2418 struct msk_if_softc; 2419 2420 struct msk_hw_stats { 2421 /* Rx stats. */ 2422 uint32_t rx_ucast_frames; 2423 uint32_t rx_bcast_frames; 2424 uint32_t rx_pause_frames; 2425 uint32_t rx_mcast_frames; 2426 uint32_t rx_crc_errs; 2427 uint32_t rx_spare1; 2428 uint64_t rx_good_octets; 2429 uint64_t rx_bad_octets; 2430 uint32_t rx_runts; 2431 uint32_t rx_runt_errs; 2432 uint32_t rx_pkts_64; 2433 uint32_t rx_pkts_65_127; 2434 uint32_t rx_pkts_128_255; 2435 uint32_t rx_pkts_256_511; 2436 uint32_t rx_pkts_512_1023; 2437 uint32_t rx_pkts_1024_1518; 2438 uint32_t rx_pkts_1519_max; 2439 uint32_t rx_pkts_too_long; 2440 uint32_t rx_pkts_jabbers; 2441 uint32_t rx_spare2; 2442 uint32_t rx_fifo_oflows; 2443 uint32_t rx_spare3; 2444 /* Tx stats. */ 2445 uint32_t tx_ucast_frames; 2446 uint32_t tx_bcast_frames; 2447 uint32_t tx_pause_frames; 2448 uint32_t tx_mcast_frames; 2449 uint64_t tx_octets; 2450 uint32_t tx_pkts_64; 2451 uint32_t tx_pkts_65_127; 2452 uint32_t tx_pkts_128_255; 2453 uint32_t tx_pkts_256_511; 2454 uint32_t tx_pkts_512_1023; 2455 uint32_t tx_pkts_1024_1518; 2456 uint32_t tx_pkts_1519_max; 2457 uint32_t tx_spare1; 2458 uint32_t tx_colls; 2459 uint32_t tx_late_colls; 2460 uint32_t tx_excess_colls; 2461 uint32_t tx_multi_colls; 2462 uint32_t tx_single_colls; 2463 uint32_t tx_underflows; 2464 }; 2465 2466 /* Softc for the Marvell Yukon II controller. */ 2467 struct msk_softc { 2468 struct resource *msk_res[1]; /* I/O resource */ 2469 struct resource_spec *msk_res_spec; 2470 struct resource *msk_irq[2]; /* IRQ resources */ 2471 struct resource_spec *msk_irq_spec; 2472 void *msk_intrhand[2]; /* irq handler handle */ 2473 device_t msk_dev; 2474 uint8_t msk_hw_id; 2475 uint8_t msk_hw_rev; 2476 uint8_t msk_bustype; 2477 uint8_t msk_num_port; 2478 int msk_ramsize; /* amount of SRAM on NIC */ 2479 uint32_t msk_pmd; /* physical media type */ 2480 uint32_t msk_intrmask; 2481 uint32_t msk_intrhwemask; 2482 uint32_t msk_pflags; 2483 int msk_clock; 2484 struct msk_if_softc *msk_if[2]; 2485 device_t msk_devs[2]; 2486 int msk_txqsize; 2487 int msk_rxqsize; 2488 int msk_txqstart[2]; 2489 int msk_txqend[2]; 2490 int msk_rxqstart[2]; 2491 int msk_rxqend[2]; 2492 bus_dma_tag_t msk_stat_tag; 2493 bus_dmamap_t msk_stat_map; 2494 struct msk_stat_desc *msk_stat_ring; 2495 bus_addr_t msk_stat_ring_paddr; 2496 int msk_process_limit; 2497 int msk_stat_cons; 2498 struct taskqueue *msk_tq; 2499 struct task msk_int_task; 2500 struct mtx msk_mtx; 2501 }; 2502 2503 #define MSK_LOCK(_sc) mtx_lock(&(_sc)->msk_mtx) 2504 #define MSK_UNLOCK(_sc) mtx_unlock(&(_sc)->msk_mtx) 2505 #define MSK_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->msk_mtx, MA_OWNED) 2506 #define MSK_IF_LOCK(_sc) MSK_LOCK((_sc)->msk_softc) 2507 #define MSK_IF_UNLOCK(_sc) MSK_UNLOCK((_sc)->msk_softc) 2508 #define MSK_IF_LOCK_ASSERT(_sc) MSK_LOCK_ASSERT((_sc)->msk_softc) 2509 2510 #define MSK_USECS(sc, us) ((sc)->msk_clock * (us)) 2511 2512 /* Softc for each logical interface. */ 2513 struct msk_if_softc { 2514 struct ifnet *msk_ifp; /* interface info */ 2515 device_t msk_miibus; 2516 device_t msk_if_dev; 2517 int32_t msk_port; /* port # on controller */ 2518 int msk_framesize; 2519 int msk_phytype; 2520 int msk_phyaddr; 2521 uint32_t msk_flags; 2522 #define MSK_FLAG_MSI 0x0001 2523 #define MSK_FLAG_FASTETHER 0x0004 2524 #define MSK_FLAG_JUMBO 0x0008 2525 #define MSK_FLAG_JUMBO_NOCSUM 0x0010 2526 #define MSK_FLAG_RAMBUF 0x0020 2527 #define MSK_FLAG_DESCV2 0x0040 2528 #define MSK_FLAG_AUTOTX_CSUM 0x0080 2529 #define MSK_FLAG_NOHWVLAN 0x0100 2530 #define MSK_FLAG_NORXCHK 0x0200 2531 #define MSK_FLAG_NORX_CSUM 0x0400 2532 #define MSK_FLAG_SUSPEND 0x2000 2533 #define MSK_FLAG_DETACH 0x4000 2534 #define MSK_FLAG_LINK 0x8000 2535 struct callout msk_tick_ch; 2536 int msk_watchdog_timer; 2537 uint32_t msk_txq; /* Tx. Async Queue offset */ 2538 uint32_t msk_txsq; /* Tx. Syn Queue offset */ 2539 uint32_t msk_rxq; /* Rx. Qeueue offset */ 2540 struct msk_chain_data msk_cdata; 2541 struct msk_ring_data msk_rdata; 2542 struct msk_softc *msk_softc; /* parent controller */ 2543 struct msk_hw_stats msk_stats; 2544 struct task msk_tx_task; 2545 int msk_if_flags; 2546 uint16_t msk_vtag; /* VLAN tag id. */ 2547 }; 2548 2549 #define MSK_TIMEOUT 1000 2550 #define MSK_PHY_POWERUP 1 2551 #define MSK_PHY_POWERDOWN 0 2552