1 /****************************************************************************** 2 * 3 * Name : sky2.c 4 * Project: Gigabit Ethernet Driver for FreeBSD 5.x/6.x 5 * Version: $Revision: 1.23 $ 6 * Date : $Date: 2005/12/22 09:04:11 $ 7 * Purpose: Main driver source file 8 * 9 *****************************************************************************/ 10 11 /****************************************************************************** 12 * 13 * LICENSE: 14 * Copyright (C) Marvell International Ltd. and/or its affiliates 15 * 16 * The computer program files contained in this folder ("Files") 17 * are provided to you under the BSD-type license terms provided 18 * below, and any use of such Files and any derivative works 19 * thereof created by you shall be governed by the following terms 20 * and conditions: 21 * 22 * - Redistributions of source code must retain the above copyright 23 * notice, this list of conditions and the following disclaimer. 24 * - Redistributions in binary form must reproduce the above 25 * copyright notice, this list of conditions and the following 26 * disclaimer in the documentation and/or other materials provided 27 * with the distribution. 28 * - Neither the name of Marvell nor the names of its contributors 29 * may be used to endorse or promote products derived from this 30 * software without specific prior written permission. 31 * 32 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 33 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 34 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 35 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 36 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 37 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 38 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 39 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 40 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 41 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 42 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED 43 * OF THE POSSIBILITY OF SUCH DAMAGE. 44 * /LICENSE 45 * 46 *****************************************************************************/ 47 48 /*- 49 * Copyright (c) 1997, 1998, 1999, 2000 50 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 51 * 52 * Redistribution and use in source and binary forms, with or without 53 * modification, are permitted provided that the following conditions 54 * are met: 55 * 1. Redistributions of source code must retain the above copyright 56 * notice, this list of conditions and the following disclaimer. 57 * 2. Redistributions in binary form must reproduce the above copyright 58 * notice, this list of conditions and the following disclaimer in the 59 * documentation and/or other materials provided with the distribution. 60 * 3. All advertising materials mentioning features or use of this software 61 * must display the following acknowledgement: 62 * This product includes software developed by Bill Paul. 63 * 4. Neither the name of the author nor the names of any co-contributors 64 * may be used to endorse or promote products derived from this software 65 * without specific prior written permission. 66 * 67 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 68 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 69 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 70 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 71 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 72 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 73 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 74 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 75 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 76 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 77 * THE POSSIBILITY OF SUCH DAMAGE. 78 */ 79 /*- 80 * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu> 81 * 82 * Permission to use, copy, modify, and distribute this software for any 83 * purpose with or without fee is hereby granted, provided that the above 84 * copyright notice and this permission notice appear in all copies. 85 * 86 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 87 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 88 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 89 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 90 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 91 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 92 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 93 */ 94 95 /* 96 * Device driver for the Marvell Yukon II Ethernet controller. 97 * Due to lack of documentation, this driver is based on the code from 98 * sk(4) and Marvell's myk(4) driver for FreeBSD 5.x. 99 */ 100 101 #include <sys/cdefs.h> 102 __FBSDID("$FreeBSD$"); 103 104 #include <sys/param.h> 105 #include <sys/systm.h> 106 #include <sys/bus.h> 107 #include <sys/endian.h> 108 #include <sys/mbuf.h> 109 #include <sys/malloc.h> 110 #include <sys/kernel.h> 111 #include <sys/module.h> 112 #include <sys/socket.h> 113 #include <sys/sockio.h> 114 #include <sys/queue.h> 115 #include <sys/sysctl.h> 116 117 #include <net/bpf.h> 118 #include <net/ethernet.h> 119 #include <net/if.h> 120 #include <net/if_arp.h> 121 #include <net/if_dl.h> 122 #include <net/if_media.h> 123 #include <net/if_types.h> 124 #include <net/if_vlan_var.h> 125 126 #include <netinet/in.h> 127 #include <netinet/in_systm.h> 128 #include <netinet/ip.h> 129 #include <netinet/tcp.h> 130 #include <netinet/udp.h> 131 132 #include <machine/bus.h> 133 #include <machine/in_cksum.h> 134 #include <machine/resource.h> 135 #include <sys/rman.h> 136 137 #include <dev/mii/mii.h> 138 #include <dev/mii/miivar.h> 139 140 #include <dev/pci/pcireg.h> 141 #include <dev/pci/pcivar.h> 142 143 #include <dev/msk/if_mskreg.h> 144 145 MODULE_DEPEND(msk, pci, 1, 1, 1); 146 MODULE_DEPEND(msk, ether, 1, 1, 1); 147 MODULE_DEPEND(msk, miibus, 1, 1, 1); 148 149 /* "device miibus" required. See GENERIC if you get errors here. */ 150 #include "miibus_if.h" 151 152 /* Tunables. */ 153 static int msi_disable = 0; 154 TUNABLE_INT("hw.msk.msi_disable", &msi_disable); 155 static int legacy_intr = 0; 156 TUNABLE_INT("hw.msk.legacy_intr", &legacy_intr); 157 static int jumbo_disable = 0; 158 TUNABLE_INT("hw.msk.jumbo_disable", &jumbo_disable); 159 160 #define MSK_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 161 162 /* 163 * Devices supported by this driver. 164 */ 165 static struct msk_product { 166 uint16_t msk_vendorid; 167 uint16_t msk_deviceid; 168 const char *msk_name; 169 } msk_products[] = { 170 { VENDORID_SK, DEVICEID_SK_YUKON2, 171 "SK-9Sxx Gigabit Ethernet" }, 172 { VENDORID_SK, DEVICEID_SK_YUKON2_EXPR, 173 "SK-9Exx Gigabit Ethernet"}, 174 { VENDORID_MARVELL, DEVICEID_MRVL_8021CU, 175 "Marvell Yukon 88E8021CU Gigabit Ethernet" }, 176 { VENDORID_MARVELL, DEVICEID_MRVL_8021X, 177 "Marvell Yukon 88E8021 SX/LX Gigabit Ethernet" }, 178 { VENDORID_MARVELL, DEVICEID_MRVL_8022CU, 179 "Marvell Yukon 88E8022CU Gigabit Ethernet" }, 180 { VENDORID_MARVELL, DEVICEID_MRVL_8022X, 181 "Marvell Yukon 88E8022 SX/LX Gigabit Ethernet" }, 182 { VENDORID_MARVELL, DEVICEID_MRVL_8061CU, 183 "Marvell Yukon 88E8061CU Gigabit Ethernet" }, 184 { VENDORID_MARVELL, DEVICEID_MRVL_8061X, 185 "Marvell Yukon 88E8061 SX/LX Gigabit Ethernet" }, 186 { VENDORID_MARVELL, DEVICEID_MRVL_8062CU, 187 "Marvell Yukon 88E8062CU Gigabit Ethernet" }, 188 { VENDORID_MARVELL, DEVICEID_MRVL_8062X, 189 "Marvell Yukon 88E8062 SX/LX Gigabit Ethernet" }, 190 { VENDORID_MARVELL, DEVICEID_MRVL_8035, 191 "Marvell Yukon 88E8035 Fast Ethernet" }, 192 { VENDORID_MARVELL, DEVICEID_MRVL_8036, 193 "Marvell Yukon 88E8036 Fast Ethernet" }, 194 { VENDORID_MARVELL, DEVICEID_MRVL_8038, 195 "Marvell Yukon 88E8038 Fast Ethernet" }, 196 { VENDORID_MARVELL, DEVICEID_MRVL_8039, 197 "Marvell Yukon 88E8039 Fast Ethernet" }, 198 { VENDORID_MARVELL, DEVICEID_MRVL_8040, 199 "Marvell Yukon 88E8040 Fast Ethernet" }, 200 { VENDORID_MARVELL, DEVICEID_MRVL_8040T, 201 "Marvell Yukon 88E8040T Fast Ethernet" }, 202 { VENDORID_MARVELL, DEVICEID_MRVL_8042, 203 "Marvell Yukon 88E8042 Fast Ethernet" }, 204 { VENDORID_MARVELL, DEVICEID_MRVL_8048, 205 "Marvell Yukon 88E8048 Fast Ethernet" }, 206 { VENDORID_MARVELL, DEVICEID_MRVL_4361, 207 "Marvell Yukon 88E8050 Gigabit Ethernet" }, 208 { VENDORID_MARVELL, DEVICEID_MRVL_4360, 209 "Marvell Yukon 88E8052 Gigabit Ethernet" }, 210 { VENDORID_MARVELL, DEVICEID_MRVL_4362, 211 "Marvell Yukon 88E8053 Gigabit Ethernet" }, 212 { VENDORID_MARVELL, DEVICEID_MRVL_4363, 213 "Marvell Yukon 88E8055 Gigabit Ethernet" }, 214 { VENDORID_MARVELL, DEVICEID_MRVL_4364, 215 "Marvell Yukon 88E8056 Gigabit Ethernet" }, 216 { VENDORID_MARVELL, DEVICEID_MRVL_4365, 217 "Marvell Yukon 88E8070 Gigabit Ethernet" }, 218 { VENDORID_MARVELL, DEVICEID_MRVL_436A, 219 "Marvell Yukon 88E8058 Gigabit Ethernet" }, 220 { VENDORID_MARVELL, DEVICEID_MRVL_436B, 221 "Marvell Yukon 88E8071 Gigabit Ethernet" }, 222 { VENDORID_MARVELL, DEVICEID_MRVL_436C, 223 "Marvell Yukon 88E8072 Gigabit Ethernet" }, 224 { VENDORID_MARVELL, DEVICEID_MRVL_4380, 225 "Marvell Yukon 88E8057 Gigabit Ethernet" }, 226 { VENDORID_MARVELL, DEVICEID_MRVL_4381, 227 "Marvell Yukon 88E8059 Gigabit Ethernet" }, 228 { VENDORID_DLINK, DEVICEID_DLINK_DGE550SX, 229 "D-Link 550SX Gigabit Ethernet" }, 230 { VENDORID_DLINK, DEVICEID_DLINK_DGE560SX, 231 "D-Link 560SX Gigabit Ethernet" }, 232 { VENDORID_DLINK, DEVICEID_DLINK_DGE560T, 233 "D-Link 560T Gigabit Ethernet" } 234 }; 235 236 static const char *model_name[] = { 237 "Yukon XL", 238 "Yukon EC Ultra", 239 "Yukon EX", 240 "Yukon EC", 241 "Yukon FE", 242 "Yukon FE+", 243 "Yukon Supreme", 244 "Yukon Ultra 2", 245 "Yukon Unknown", 246 "Yukon Optima", 247 }; 248 249 static int mskc_probe(device_t); 250 static int mskc_attach(device_t); 251 static int mskc_detach(device_t); 252 static int mskc_shutdown(device_t); 253 static int mskc_setup_rambuffer(struct msk_softc *); 254 static int mskc_suspend(device_t); 255 static int mskc_resume(device_t); 256 static void mskc_reset(struct msk_softc *); 257 258 static int msk_probe(device_t); 259 static int msk_attach(device_t); 260 static int msk_detach(device_t); 261 262 static void msk_tick(void *); 263 static void msk_intr(void *); 264 static void msk_intr_phy(struct msk_if_softc *); 265 static void msk_intr_gmac(struct msk_if_softc *); 266 static __inline void msk_rxput(struct msk_if_softc *); 267 static int msk_handle_events(struct msk_softc *); 268 static void msk_handle_hwerr(struct msk_if_softc *, uint32_t); 269 static void msk_intr_hwerr(struct msk_softc *); 270 #ifndef __NO_STRICT_ALIGNMENT 271 static __inline void msk_fixup_rx(struct mbuf *); 272 #endif 273 static __inline void msk_rxcsum(struct msk_if_softc *, uint32_t, struct mbuf *); 274 static void msk_rxeof(struct msk_if_softc *, uint32_t, uint32_t, int); 275 static void msk_jumbo_rxeof(struct msk_if_softc *, uint32_t, uint32_t, int); 276 static void msk_txeof(struct msk_if_softc *, int); 277 static int msk_encap(struct msk_if_softc *, struct mbuf **); 278 static void msk_start(struct ifnet *); 279 static void msk_start_locked(struct ifnet *); 280 static int msk_ioctl(struct ifnet *, u_long, caddr_t); 281 static void msk_set_prefetch(struct msk_softc *, int, bus_addr_t, uint32_t); 282 static void msk_set_rambuffer(struct msk_if_softc *); 283 static void msk_set_tx_stfwd(struct msk_if_softc *); 284 static void msk_init(void *); 285 static void msk_init_locked(struct msk_if_softc *); 286 static void msk_stop(struct msk_if_softc *); 287 static void msk_watchdog(struct msk_if_softc *); 288 static int msk_mediachange(struct ifnet *); 289 static void msk_mediastatus(struct ifnet *, struct ifmediareq *); 290 static void msk_phy_power(struct msk_softc *, int); 291 static void msk_dmamap_cb(void *, bus_dma_segment_t *, int, int); 292 static int msk_status_dma_alloc(struct msk_softc *); 293 static void msk_status_dma_free(struct msk_softc *); 294 static int msk_txrx_dma_alloc(struct msk_if_softc *); 295 static int msk_rx_dma_jalloc(struct msk_if_softc *); 296 static void msk_txrx_dma_free(struct msk_if_softc *); 297 static void msk_rx_dma_jfree(struct msk_if_softc *); 298 static int msk_rx_fill(struct msk_if_softc *, int); 299 static int msk_init_rx_ring(struct msk_if_softc *); 300 static int msk_init_jumbo_rx_ring(struct msk_if_softc *); 301 static void msk_init_tx_ring(struct msk_if_softc *); 302 static __inline void msk_discard_rxbuf(struct msk_if_softc *, int); 303 static __inline void msk_discard_jumbo_rxbuf(struct msk_if_softc *, int); 304 static int msk_newbuf(struct msk_if_softc *, int); 305 static int msk_jumbo_newbuf(struct msk_if_softc *, int); 306 307 static int msk_phy_readreg(struct msk_if_softc *, int, int); 308 static int msk_phy_writereg(struct msk_if_softc *, int, int, int); 309 static int msk_miibus_readreg(device_t, int, int); 310 static int msk_miibus_writereg(device_t, int, int, int); 311 static void msk_miibus_statchg(device_t); 312 313 static void msk_rxfilter(struct msk_if_softc *); 314 static void msk_setvlan(struct msk_if_softc *, struct ifnet *); 315 316 static void msk_stats_clear(struct msk_if_softc *); 317 static void msk_stats_update(struct msk_if_softc *); 318 static int msk_sysctl_stat32(SYSCTL_HANDLER_ARGS); 319 static int msk_sysctl_stat64(SYSCTL_HANDLER_ARGS); 320 static void msk_sysctl_node(struct msk_if_softc *); 321 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int); 322 static int sysctl_hw_msk_proc_limit(SYSCTL_HANDLER_ARGS); 323 324 static device_method_t mskc_methods[] = { 325 /* Device interface */ 326 DEVMETHOD(device_probe, mskc_probe), 327 DEVMETHOD(device_attach, mskc_attach), 328 DEVMETHOD(device_detach, mskc_detach), 329 DEVMETHOD(device_suspend, mskc_suspend), 330 DEVMETHOD(device_resume, mskc_resume), 331 DEVMETHOD(device_shutdown, mskc_shutdown), 332 333 /* bus interface */ 334 DEVMETHOD(bus_print_child, bus_generic_print_child), 335 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 336 337 { NULL, NULL } 338 }; 339 340 static driver_t mskc_driver = { 341 "mskc", 342 mskc_methods, 343 sizeof(struct msk_softc) 344 }; 345 346 static devclass_t mskc_devclass; 347 348 static device_method_t msk_methods[] = { 349 /* Device interface */ 350 DEVMETHOD(device_probe, msk_probe), 351 DEVMETHOD(device_attach, msk_attach), 352 DEVMETHOD(device_detach, msk_detach), 353 DEVMETHOD(device_shutdown, bus_generic_shutdown), 354 355 /* bus interface */ 356 DEVMETHOD(bus_print_child, bus_generic_print_child), 357 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 358 359 /* MII interface */ 360 DEVMETHOD(miibus_readreg, msk_miibus_readreg), 361 DEVMETHOD(miibus_writereg, msk_miibus_writereg), 362 DEVMETHOD(miibus_statchg, msk_miibus_statchg), 363 364 { NULL, NULL } 365 }; 366 367 static driver_t msk_driver = { 368 "msk", 369 msk_methods, 370 sizeof(struct msk_if_softc) 371 }; 372 373 static devclass_t msk_devclass; 374 375 DRIVER_MODULE(mskc, pci, mskc_driver, mskc_devclass, 0, 0); 376 DRIVER_MODULE(msk, mskc, msk_driver, msk_devclass, 0, 0); 377 DRIVER_MODULE(miibus, msk, miibus_driver, miibus_devclass, 0, 0); 378 379 static struct resource_spec msk_res_spec_io[] = { 380 { SYS_RES_IOPORT, PCIR_BAR(1), RF_ACTIVE }, 381 { -1, 0, 0 } 382 }; 383 384 static struct resource_spec msk_res_spec_mem[] = { 385 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 386 { -1, 0, 0 } 387 }; 388 389 static struct resource_spec msk_irq_spec_legacy[] = { 390 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 391 { -1, 0, 0 } 392 }; 393 394 static struct resource_spec msk_irq_spec_msi[] = { 395 { SYS_RES_IRQ, 1, RF_ACTIVE }, 396 { -1, 0, 0 } 397 }; 398 399 static int 400 msk_miibus_readreg(device_t dev, int phy, int reg) 401 { 402 struct msk_if_softc *sc_if; 403 404 if (phy != PHY_ADDR_MARV) 405 return (0); 406 407 sc_if = device_get_softc(dev); 408 409 return (msk_phy_readreg(sc_if, phy, reg)); 410 } 411 412 static int 413 msk_phy_readreg(struct msk_if_softc *sc_if, int phy, int reg) 414 { 415 struct msk_softc *sc; 416 int i, val; 417 418 sc = sc_if->msk_softc; 419 420 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SMI_CTRL, 421 GM_SMI_CT_PHY_AD(phy) | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD); 422 423 for (i = 0; i < MSK_TIMEOUT; i++) { 424 DELAY(1); 425 val = GMAC_READ_2(sc, sc_if->msk_port, GM_SMI_CTRL); 426 if ((val & GM_SMI_CT_RD_VAL) != 0) { 427 val = GMAC_READ_2(sc, sc_if->msk_port, GM_SMI_DATA); 428 break; 429 } 430 } 431 432 if (i == MSK_TIMEOUT) { 433 if_printf(sc_if->msk_ifp, "phy failed to come ready\n"); 434 val = 0; 435 } 436 437 return (val); 438 } 439 440 static int 441 msk_miibus_writereg(device_t dev, int phy, int reg, int val) 442 { 443 struct msk_if_softc *sc_if; 444 445 if (phy != PHY_ADDR_MARV) 446 return (0); 447 448 sc_if = device_get_softc(dev); 449 450 return (msk_phy_writereg(sc_if, phy, reg, val)); 451 } 452 453 static int 454 msk_phy_writereg(struct msk_if_softc *sc_if, int phy, int reg, int val) 455 { 456 struct msk_softc *sc; 457 int i; 458 459 sc = sc_if->msk_softc; 460 461 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SMI_DATA, val); 462 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SMI_CTRL, 463 GM_SMI_CT_PHY_AD(phy) | GM_SMI_CT_REG_AD(reg)); 464 for (i = 0; i < MSK_TIMEOUT; i++) { 465 DELAY(1); 466 if ((GMAC_READ_2(sc, sc_if->msk_port, GM_SMI_CTRL) & 467 GM_SMI_CT_BUSY) == 0) 468 break; 469 } 470 if (i == MSK_TIMEOUT) 471 if_printf(sc_if->msk_ifp, "phy write timeout\n"); 472 473 return (0); 474 } 475 476 static void 477 msk_miibus_statchg(device_t dev) 478 { 479 struct msk_softc *sc; 480 struct msk_if_softc *sc_if; 481 struct mii_data *mii; 482 struct ifnet *ifp; 483 uint32_t gmac; 484 485 sc_if = device_get_softc(dev); 486 sc = sc_if->msk_softc; 487 488 MSK_IF_LOCK_ASSERT(sc_if); 489 490 mii = device_get_softc(sc_if->msk_miibus); 491 ifp = sc_if->msk_ifp; 492 if (mii == NULL || ifp == NULL || 493 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 494 return; 495 496 sc_if->msk_flags &= ~MSK_FLAG_LINK; 497 if ((mii->mii_media_status & (IFM_AVALID | IFM_ACTIVE)) == 498 (IFM_AVALID | IFM_ACTIVE)) { 499 switch (IFM_SUBTYPE(mii->mii_media_active)) { 500 case IFM_10_T: 501 case IFM_100_TX: 502 sc_if->msk_flags |= MSK_FLAG_LINK; 503 break; 504 case IFM_1000_T: 505 case IFM_1000_SX: 506 case IFM_1000_LX: 507 case IFM_1000_CX: 508 if ((sc_if->msk_flags & MSK_FLAG_FASTETHER) == 0) 509 sc_if->msk_flags |= MSK_FLAG_LINK; 510 break; 511 default: 512 break; 513 } 514 } 515 516 if ((sc_if->msk_flags & MSK_FLAG_LINK) != 0) { 517 /* Enable Tx FIFO Underrun. */ 518 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_MSK), 519 GM_IS_TX_FF_UR | GM_IS_RX_FF_OR); 520 /* 521 * Because mii(4) notify msk(4) that it detected link status 522 * change, there is no need to enable automatic 523 * speed/flow-control/duplex updates. 524 */ 525 gmac = GM_GPCR_AU_ALL_DIS; 526 switch (IFM_SUBTYPE(mii->mii_media_active)) { 527 case IFM_1000_SX: 528 case IFM_1000_T: 529 gmac |= GM_GPCR_SPEED_1000; 530 break; 531 case IFM_100_TX: 532 gmac |= GM_GPCR_SPEED_100; 533 break; 534 case IFM_10_T: 535 break; 536 } 537 538 /* Disable Rx flow control. */ 539 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FLAG0) == 0) 540 gmac |= GM_GPCR_FC_RX_DIS; 541 /* Disable Tx flow control. */ 542 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FLAG1) == 0) 543 gmac |= GM_GPCR_FC_TX_DIS; 544 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) 545 gmac |= GM_GPCR_DUP_FULL; 546 else 547 gmac |= GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS; 548 gmac |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA; 549 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, gmac); 550 /* Read again to ensure writing. */ 551 GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL); 552 gmac = GMC_PAUSE_OFF; 553 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 554 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FLAG0) != 0) 555 gmac = GMC_PAUSE_ON; 556 } 557 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), gmac); 558 559 /* Enable PHY interrupt for FIFO underrun/overflow. */ 560 msk_phy_writereg(sc_if, PHY_ADDR_MARV, 561 PHY_MARV_INT_MASK, PHY_M_IS_FIFO_ERROR); 562 } else { 563 /* 564 * Link state changed to down. 565 * Disable PHY interrupts. 566 */ 567 msk_phy_writereg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_MASK, 0); 568 /* Disable Rx/Tx MAC. */ 569 gmac = GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL); 570 if ((GM_GPCR_RX_ENA | GM_GPCR_TX_ENA) != 0) { 571 gmac &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA); 572 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, gmac); 573 /* Read again to ensure writing. */ 574 GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL); 575 } 576 } 577 } 578 579 static void 580 msk_rxfilter(struct msk_if_softc *sc_if) 581 { 582 struct msk_softc *sc; 583 struct ifnet *ifp; 584 struct ifmultiaddr *ifma; 585 uint32_t mchash[2]; 586 uint32_t crc; 587 uint16_t mode; 588 589 sc = sc_if->msk_softc; 590 591 MSK_IF_LOCK_ASSERT(sc_if); 592 593 ifp = sc_if->msk_ifp; 594 595 bzero(mchash, sizeof(mchash)); 596 mode = GMAC_READ_2(sc, sc_if->msk_port, GM_RX_CTRL); 597 if ((ifp->if_flags & IFF_PROMISC) != 0) 598 mode &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA); 599 else if ((ifp->if_flags & IFF_ALLMULTI) != 0) { 600 mode |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA; 601 mchash[0] = 0xffff; 602 mchash[1] = 0xffff; 603 } else { 604 mode |= GM_RXCR_UCF_ENA; 605 if_maddr_rlock(ifp); 606 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 607 if (ifma->ifma_addr->sa_family != AF_LINK) 608 continue; 609 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *) 610 ifma->ifma_addr), ETHER_ADDR_LEN); 611 /* Just want the 6 least significant bits. */ 612 crc &= 0x3f; 613 /* Set the corresponding bit in the hash table. */ 614 mchash[crc >> 5] |= 1 << (crc & 0x1f); 615 } 616 if_maddr_runlock(ifp); 617 if (mchash[0] != 0 || mchash[1] != 0) 618 mode |= GM_RXCR_MCF_ENA; 619 } 620 621 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H1, 622 mchash[0] & 0xffff); 623 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H2, 624 (mchash[0] >> 16) & 0xffff); 625 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H3, 626 mchash[1] & 0xffff); 627 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H4, 628 (mchash[1] >> 16) & 0xffff); 629 GMAC_WRITE_2(sc, sc_if->msk_port, GM_RX_CTRL, mode); 630 } 631 632 static void 633 msk_setvlan(struct msk_if_softc *sc_if, struct ifnet *ifp) 634 { 635 struct msk_softc *sc; 636 637 sc = sc_if->msk_softc; 638 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) { 639 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), 640 RX_VLAN_STRIP_ON); 641 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 642 TX_VLAN_TAG_ON); 643 } else { 644 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), 645 RX_VLAN_STRIP_OFF); 646 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 647 TX_VLAN_TAG_OFF); 648 } 649 } 650 651 static int 652 msk_rx_fill(struct msk_if_softc *sc_if, int jumbo) 653 { 654 uint16_t idx; 655 int i; 656 657 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0 && 658 (sc_if->msk_ifp->if_capenable & IFCAP_RXCSUM) != 0) { 659 /* Wait until controller executes OP_TCPSTART command. */ 660 for (i = 10; i > 0; i--) { 661 DELAY(10); 662 idx = CSR_READ_2(sc_if->msk_softc, 663 Y2_PREF_Q_ADDR(sc_if->msk_rxq, 664 PREF_UNIT_GET_IDX_REG)); 665 if (idx != 0) 666 break; 667 } 668 if (i == 0) { 669 device_printf(sc_if->msk_if_dev, 670 "prefetch unit stuck?\n"); 671 return (ETIMEDOUT); 672 } 673 /* 674 * Fill consumed LE with free buffer. This can be done 675 * in Rx handler but we don't want to add special code 676 * in fast handler. 677 */ 678 if (jumbo > 0) { 679 if (msk_jumbo_newbuf(sc_if, 0) != 0) 680 return (ENOBUFS); 681 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 682 sc_if->msk_cdata.msk_jumbo_rx_ring_map, 683 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 684 } else { 685 if (msk_newbuf(sc_if, 0) != 0) 686 return (ENOBUFS); 687 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_ring_tag, 688 sc_if->msk_cdata.msk_rx_ring_map, 689 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 690 } 691 sc_if->msk_cdata.msk_rx_prod = 0; 692 CSR_WRITE_2(sc_if->msk_softc, 693 Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_PUT_IDX_REG), 694 sc_if->msk_cdata.msk_rx_prod); 695 } 696 return (0); 697 } 698 699 static int 700 msk_init_rx_ring(struct msk_if_softc *sc_if) 701 { 702 struct msk_ring_data *rd; 703 struct msk_rxdesc *rxd; 704 int i, prod; 705 706 MSK_IF_LOCK_ASSERT(sc_if); 707 708 sc_if->msk_cdata.msk_rx_cons = 0; 709 sc_if->msk_cdata.msk_rx_prod = 0; 710 sc_if->msk_cdata.msk_rx_putwm = MSK_PUT_WM; 711 712 rd = &sc_if->msk_rdata; 713 bzero(rd->msk_rx_ring, sizeof(struct msk_rx_desc) * MSK_RX_RING_CNT); 714 prod = sc_if->msk_cdata.msk_rx_prod; 715 i = 0; 716 /* Have controller know how to compute Rx checksum. */ 717 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0 && 718 (sc_if->msk_ifp->if_capenable & IFCAP_RXCSUM) != 0) { 719 rxd = &sc_if->msk_cdata.msk_rxdesc[prod]; 720 rxd->rx_m = NULL; 721 rxd->rx_le = &rd->msk_rx_ring[prod]; 722 rxd->rx_le->msk_addr = htole32(ETHER_HDR_LEN << 16 | 723 ETHER_HDR_LEN); 724 rxd->rx_le->msk_control = htole32(OP_TCPSTART | HW_OWNER); 725 MSK_INC(prod, MSK_RX_RING_CNT); 726 MSK_INC(sc_if->msk_cdata.msk_rx_cons, MSK_RX_RING_CNT); 727 i++; 728 } 729 for (; i < MSK_RX_RING_CNT; i++) { 730 rxd = &sc_if->msk_cdata.msk_rxdesc[prod]; 731 rxd->rx_m = NULL; 732 rxd->rx_le = &rd->msk_rx_ring[prod]; 733 if (msk_newbuf(sc_if, prod) != 0) 734 return (ENOBUFS); 735 MSK_INC(prod, MSK_RX_RING_CNT); 736 } 737 738 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_ring_tag, 739 sc_if->msk_cdata.msk_rx_ring_map, 740 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 741 742 /* Update prefetch unit. */ 743 sc_if->msk_cdata.msk_rx_prod = MSK_RX_RING_CNT - 1; 744 CSR_WRITE_2(sc_if->msk_softc, 745 Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_PUT_IDX_REG), 746 sc_if->msk_cdata.msk_rx_prod); 747 if (msk_rx_fill(sc_if, 0) != 0) 748 return (ENOBUFS); 749 return (0); 750 } 751 752 static int 753 msk_init_jumbo_rx_ring(struct msk_if_softc *sc_if) 754 { 755 struct msk_ring_data *rd; 756 struct msk_rxdesc *rxd; 757 int i, prod; 758 759 MSK_IF_LOCK_ASSERT(sc_if); 760 761 sc_if->msk_cdata.msk_rx_cons = 0; 762 sc_if->msk_cdata.msk_rx_prod = 0; 763 sc_if->msk_cdata.msk_rx_putwm = MSK_PUT_WM; 764 765 rd = &sc_if->msk_rdata; 766 bzero(rd->msk_jumbo_rx_ring, 767 sizeof(struct msk_rx_desc) * MSK_JUMBO_RX_RING_CNT); 768 prod = sc_if->msk_cdata.msk_rx_prod; 769 i = 0; 770 /* Have controller know how to compute Rx checksum. */ 771 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0 && 772 (sc_if->msk_ifp->if_capenable & IFCAP_RXCSUM) != 0) { 773 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[prod]; 774 rxd->rx_m = NULL; 775 rxd->rx_le = &rd->msk_jumbo_rx_ring[prod]; 776 rxd->rx_le->msk_addr = htole32(ETHER_HDR_LEN << 16 | 777 ETHER_HDR_LEN); 778 rxd->rx_le->msk_control = htole32(OP_TCPSTART | HW_OWNER); 779 MSK_INC(prod, MSK_JUMBO_RX_RING_CNT); 780 MSK_INC(sc_if->msk_cdata.msk_rx_cons, MSK_JUMBO_RX_RING_CNT); 781 i++; 782 } 783 for (; i < MSK_JUMBO_RX_RING_CNT; i++) { 784 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[prod]; 785 rxd->rx_m = NULL; 786 rxd->rx_le = &rd->msk_jumbo_rx_ring[prod]; 787 if (msk_jumbo_newbuf(sc_if, prod) != 0) 788 return (ENOBUFS); 789 MSK_INC(prod, MSK_JUMBO_RX_RING_CNT); 790 } 791 792 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 793 sc_if->msk_cdata.msk_jumbo_rx_ring_map, 794 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 795 796 sc_if->msk_cdata.msk_rx_prod = MSK_JUMBO_RX_RING_CNT - 1; 797 CSR_WRITE_2(sc_if->msk_softc, 798 Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_PUT_IDX_REG), 799 sc_if->msk_cdata.msk_rx_prod); 800 if (msk_rx_fill(sc_if, 1) != 0) 801 return (ENOBUFS); 802 return (0); 803 } 804 805 static void 806 msk_init_tx_ring(struct msk_if_softc *sc_if) 807 { 808 struct msk_ring_data *rd; 809 struct msk_txdesc *txd; 810 int i; 811 812 sc_if->msk_cdata.msk_tso_mtu = 0; 813 sc_if->msk_cdata.msk_last_csum = 0; 814 sc_if->msk_cdata.msk_tx_prod = 0; 815 sc_if->msk_cdata.msk_tx_cons = 0; 816 sc_if->msk_cdata.msk_tx_cnt = 0; 817 818 rd = &sc_if->msk_rdata; 819 bzero(rd->msk_tx_ring, sizeof(struct msk_tx_desc) * MSK_TX_RING_CNT); 820 for (i = 0; i < MSK_TX_RING_CNT; i++) { 821 txd = &sc_if->msk_cdata.msk_txdesc[i]; 822 txd->tx_m = NULL; 823 txd->tx_le = &rd->msk_tx_ring[i]; 824 } 825 826 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_ring_tag, 827 sc_if->msk_cdata.msk_tx_ring_map, 828 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 829 } 830 831 static __inline void 832 msk_discard_rxbuf(struct msk_if_softc *sc_if, int idx) 833 { 834 struct msk_rx_desc *rx_le; 835 struct msk_rxdesc *rxd; 836 struct mbuf *m; 837 838 rxd = &sc_if->msk_cdata.msk_rxdesc[idx]; 839 m = rxd->rx_m; 840 rx_le = rxd->rx_le; 841 rx_le->msk_control = htole32(m->m_len | OP_PACKET | HW_OWNER); 842 } 843 844 static __inline void 845 msk_discard_jumbo_rxbuf(struct msk_if_softc *sc_if, int idx) 846 { 847 struct msk_rx_desc *rx_le; 848 struct msk_rxdesc *rxd; 849 struct mbuf *m; 850 851 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[idx]; 852 m = rxd->rx_m; 853 rx_le = rxd->rx_le; 854 rx_le->msk_control = htole32(m->m_len | OP_PACKET | HW_OWNER); 855 } 856 857 static int 858 msk_newbuf(struct msk_if_softc *sc_if, int idx) 859 { 860 struct msk_rx_desc *rx_le; 861 struct msk_rxdesc *rxd; 862 struct mbuf *m; 863 bus_dma_segment_t segs[1]; 864 bus_dmamap_t map; 865 int nsegs; 866 867 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 868 if (m == NULL) 869 return (ENOBUFS); 870 871 m->m_len = m->m_pkthdr.len = MCLBYTES; 872 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) == 0) 873 m_adj(m, ETHER_ALIGN); 874 #ifndef __NO_STRICT_ALIGNMENT 875 else 876 m_adj(m, MSK_RX_BUF_ALIGN); 877 #endif 878 879 if (bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_rx_tag, 880 sc_if->msk_cdata.msk_rx_sparemap, m, segs, &nsegs, 881 BUS_DMA_NOWAIT) != 0) { 882 m_freem(m); 883 return (ENOBUFS); 884 } 885 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 886 887 rxd = &sc_if->msk_cdata.msk_rxdesc[idx]; 888 if (rxd->rx_m != NULL) { 889 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_tag, rxd->rx_dmamap, 890 BUS_DMASYNC_POSTREAD); 891 bus_dmamap_unload(sc_if->msk_cdata.msk_rx_tag, rxd->rx_dmamap); 892 } 893 map = rxd->rx_dmamap; 894 rxd->rx_dmamap = sc_if->msk_cdata.msk_rx_sparemap; 895 sc_if->msk_cdata.msk_rx_sparemap = map; 896 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_tag, rxd->rx_dmamap, 897 BUS_DMASYNC_PREREAD); 898 rxd->rx_m = m; 899 rx_le = rxd->rx_le; 900 rx_le->msk_addr = htole32(MSK_ADDR_LO(segs[0].ds_addr)); 901 rx_le->msk_control = 902 htole32(segs[0].ds_len | OP_PACKET | HW_OWNER); 903 904 return (0); 905 } 906 907 static int 908 msk_jumbo_newbuf(struct msk_if_softc *sc_if, int idx) 909 { 910 struct msk_rx_desc *rx_le; 911 struct msk_rxdesc *rxd; 912 struct mbuf *m; 913 bus_dma_segment_t segs[1]; 914 bus_dmamap_t map; 915 int nsegs; 916 917 m = m_getjcl(M_DONTWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES); 918 if (m == NULL) 919 return (ENOBUFS); 920 if ((m->m_flags & M_EXT) == 0) { 921 m_freem(m); 922 return (ENOBUFS); 923 } 924 m->m_len = m->m_pkthdr.len = MJUM9BYTES; 925 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) == 0) 926 m_adj(m, ETHER_ALIGN); 927 #ifndef __NO_STRICT_ALIGNMENT 928 else 929 m_adj(m, MSK_RX_BUF_ALIGN); 930 #endif 931 932 if (bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_jumbo_rx_tag, 933 sc_if->msk_cdata.msk_jumbo_rx_sparemap, m, segs, &nsegs, 934 BUS_DMA_NOWAIT) != 0) { 935 m_freem(m); 936 return (ENOBUFS); 937 } 938 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 939 940 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[idx]; 941 if (rxd->rx_m != NULL) { 942 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_tag, 943 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 944 bus_dmamap_unload(sc_if->msk_cdata.msk_jumbo_rx_tag, 945 rxd->rx_dmamap); 946 } 947 map = rxd->rx_dmamap; 948 rxd->rx_dmamap = sc_if->msk_cdata.msk_jumbo_rx_sparemap; 949 sc_if->msk_cdata.msk_jumbo_rx_sparemap = map; 950 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_tag, rxd->rx_dmamap, 951 BUS_DMASYNC_PREREAD); 952 rxd->rx_m = m; 953 rx_le = rxd->rx_le; 954 rx_le->msk_addr = htole32(MSK_ADDR_LO(segs[0].ds_addr)); 955 rx_le->msk_control = 956 htole32(segs[0].ds_len | OP_PACKET | HW_OWNER); 957 958 return (0); 959 } 960 961 /* 962 * Set media options. 963 */ 964 static int 965 msk_mediachange(struct ifnet *ifp) 966 { 967 struct msk_if_softc *sc_if; 968 struct mii_data *mii; 969 int error; 970 971 sc_if = ifp->if_softc; 972 973 MSK_IF_LOCK(sc_if); 974 mii = device_get_softc(sc_if->msk_miibus); 975 error = mii_mediachg(mii); 976 MSK_IF_UNLOCK(sc_if); 977 978 return (error); 979 } 980 981 /* 982 * Report current media status. 983 */ 984 static void 985 msk_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 986 { 987 struct msk_if_softc *sc_if; 988 struct mii_data *mii; 989 990 sc_if = ifp->if_softc; 991 MSK_IF_LOCK(sc_if); 992 if ((ifp->if_flags & IFF_UP) == 0) { 993 MSK_IF_UNLOCK(sc_if); 994 return; 995 } 996 mii = device_get_softc(sc_if->msk_miibus); 997 998 mii_pollstat(mii); 999 MSK_IF_UNLOCK(sc_if); 1000 ifmr->ifm_active = mii->mii_media_active; 1001 ifmr->ifm_status = mii->mii_media_status; 1002 } 1003 1004 static int 1005 msk_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1006 { 1007 struct msk_if_softc *sc_if; 1008 struct ifreq *ifr; 1009 struct mii_data *mii; 1010 int error, mask, reinit; 1011 1012 sc_if = ifp->if_softc; 1013 ifr = (struct ifreq *)data; 1014 error = 0; 1015 1016 switch(command) { 1017 case SIOCSIFMTU: 1018 MSK_IF_LOCK(sc_if); 1019 if (ifr->ifr_mtu > MSK_JUMBO_MTU || ifr->ifr_mtu < ETHERMIN) 1020 error = EINVAL; 1021 else if (ifp->if_mtu != ifr->ifr_mtu) { 1022 if (ifr->ifr_mtu > ETHERMTU) { 1023 if ((sc_if->msk_flags & MSK_FLAG_JUMBO) == 0) { 1024 error = EINVAL; 1025 MSK_IF_UNLOCK(sc_if); 1026 break; 1027 } 1028 if ((sc_if->msk_flags & 1029 MSK_FLAG_JUMBO_NOCSUM) != 0) { 1030 ifp->if_hwassist &= 1031 ~(MSK_CSUM_FEATURES | CSUM_TSO); 1032 ifp->if_capenable &= 1033 ~(IFCAP_TSO4 | IFCAP_TXCSUM); 1034 VLAN_CAPABILITIES(ifp); 1035 } 1036 } 1037 ifp->if_mtu = ifr->ifr_mtu; 1038 msk_init_locked(sc_if); 1039 } 1040 MSK_IF_UNLOCK(sc_if); 1041 break; 1042 case SIOCSIFFLAGS: 1043 MSK_IF_LOCK(sc_if); 1044 if ((ifp->if_flags & IFF_UP) != 0) { 1045 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 && 1046 ((ifp->if_flags ^ sc_if->msk_if_flags) & 1047 (IFF_PROMISC | IFF_ALLMULTI)) != 0) 1048 msk_rxfilter(sc_if); 1049 else if ((sc_if->msk_flags & MSK_FLAG_DETACH) == 0) 1050 msk_init_locked(sc_if); 1051 } else if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1052 msk_stop(sc_if); 1053 sc_if->msk_if_flags = ifp->if_flags; 1054 MSK_IF_UNLOCK(sc_if); 1055 break; 1056 case SIOCADDMULTI: 1057 case SIOCDELMULTI: 1058 MSK_IF_LOCK(sc_if); 1059 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1060 msk_rxfilter(sc_if); 1061 MSK_IF_UNLOCK(sc_if); 1062 break; 1063 case SIOCGIFMEDIA: 1064 case SIOCSIFMEDIA: 1065 mii = device_get_softc(sc_if->msk_miibus); 1066 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1067 break; 1068 case SIOCSIFCAP: 1069 reinit = 0; 1070 MSK_IF_LOCK(sc_if); 1071 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 1072 if ((mask & IFCAP_TXCSUM) != 0 && 1073 (IFCAP_TXCSUM & ifp->if_capabilities) != 0) { 1074 ifp->if_capenable ^= IFCAP_TXCSUM; 1075 if ((IFCAP_TXCSUM & ifp->if_capenable) != 0) 1076 ifp->if_hwassist |= MSK_CSUM_FEATURES; 1077 else 1078 ifp->if_hwassist &= ~MSK_CSUM_FEATURES; 1079 } 1080 if ((mask & IFCAP_RXCSUM) != 0 && 1081 (IFCAP_RXCSUM & ifp->if_capabilities) != 0) { 1082 ifp->if_capenable ^= IFCAP_RXCSUM; 1083 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0) 1084 reinit = 1; 1085 } 1086 if ((mask & IFCAP_VLAN_HWCSUM) != 0 && 1087 (IFCAP_VLAN_HWCSUM & ifp->if_capabilities) != 0) 1088 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; 1089 if ((mask & IFCAP_TSO4) != 0 && 1090 (IFCAP_TSO4 & ifp->if_capabilities) != 0) { 1091 ifp->if_capenable ^= IFCAP_TSO4; 1092 if ((IFCAP_TSO4 & ifp->if_capenable) != 0) 1093 ifp->if_hwassist |= CSUM_TSO; 1094 else 1095 ifp->if_hwassist &= ~CSUM_TSO; 1096 } 1097 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 1098 (IFCAP_VLAN_HWTSO & ifp->if_capabilities) != 0) 1099 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 1100 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 1101 (IFCAP_VLAN_HWTAGGING & ifp->if_capabilities) != 0) { 1102 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 1103 if ((IFCAP_VLAN_HWTAGGING & ifp->if_capenable) == 0) 1104 ifp->if_capenable &= ~IFCAP_VLAN_HWTSO; 1105 msk_setvlan(sc_if, ifp); 1106 } 1107 if (ifp->if_mtu > ETHERMTU && 1108 (sc_if->msk_flags & MSK_FLAG_JUMBO_NOCSUM) != 0) { 1109 ifp->if_hwassist &= ~(MSK_CSUM_FEATURES | CSUM_TSO); 1110 ifp->if_capenable &= ~(IFCAP_TSO4 | IFCAP_TXCSUM); 1111 } 1112 VLAN_CAPABILITIES(ifp); 1113 if (reinit > 0 && (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 1114 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1115 msk_init_locked(sc_if); 1116 } 1117 MSK_IF_UNLOCK(sc_if); 1118 break; 1119 default: 1120 error = ether_ioctl(ifp, command, data); 1121 break; 1122 } 1123 1124 return (error); 1125 } 1126 1127 static int 1128 mskc_probe(device_t dev) 1129 { 1130 struct msk_product *mp; 1131 uint16_t vendor, devid; 1132 int i; 1133 1134 vendor = pci_get_vendor(dev); 1135 devid = pci_get_device(dev); 1136 mp = msk_products; 1137 for (i = 0; i < sizeof(msk_products)/sizeof(msk_products[0]); 1138 i++, mp++) { 1139 if (vendor == mp->msk_vendorid && devid == mp->msk_deviceid) { 1140 device_set_desc(dev, mp->msk_name); 1141 return (BUS_PROBE_DEFAULT); 1142 } 1143 } 1144 1145 return (ENXIO); 1146 } 1147 1148 static int 1149 mskc_setup_rambuffer(struct msk_softc *sc) 1150 { 1151 int next; 1152 int i; 1153 1154 /* Get adapter SRAM size. */ 1155 sc->msk_ramsize = CSR_READ_1(sc, B2_E_0) * 4; 1156 if (bootverbose) 1157 device_printf(sc->msk_dev, 1158 "RAM buffer size : %dKB\n", sc->msk_ramsize); 1159 if (sc->msk_ramsize == 0) 1160 return (0); 1161 1162 sc->msk_pflags |= MSK_FLAG_RAMBUF; 1163 /* 1164 * Give receiver 2/3 of memory and round down to the multiple 1165 * of 1024. Tx/Rx RAM buffer size of Yukon II shoud be multiple 1166 * of 1024. 1167 */ 1168 sc->msk_rxqsize = rounddown((sc->msk_ramsize * 1024 * 2) / 3, 1024); 1169 sc->msk_txqsize = (sc->msk_ramsize * 1024) - sc->msk_rxqsize; 1170 for (i = 0, next = 0; i < sc->msk_num_port; i++) { 1171 sc->msk_rxqstart[i] = next; 1172 sc->msk_rxqend[i] = next + sc->msk_rxqsize - 1; 1173 next = sc->msk_rxqend[i] + 1; 1174 sc->msk_txqstart[i] = next; 1175 sc->msk_txqend[i] = next + sc->msk_txqsize - 1; 1176 next = sc->msk_txqend[i] + 1; 1177 if (bootverbose) { 1178 device_printf(sc->msk_dev, 1179 "Port %d : Rx Queue %dKB(0x%08x:0x%08x)\n", i, 1180 sc->msk_rxqsize / 1024, sc->msk_rxqstart[i], 1181 sc->msk_rxqend[i]); 1182 device_printf(sc->msk_dev, 1183 "Port %d : Tx Queue %dKB(0x%08x:0x%08x)\n", i, 1184 sc->msk_txqsize / 1024, sc->msk_txqstart[i], 1185 sc->msk_txqend[i]); 1186 } 1187 } 1188 1189 return (0); 1190 } 1191 1192 static void 1193 msk_phy_power(struct msk_softc *sc, int mode) 1194 { 1195 uint32_t our, val; 1196 int i; 1197 1198 switch (mode) { 1199 case MSK_PHY_POWERUP: 1200 /* Switch power to VCC (WA for VAUX problem). */ 1201 CSR_WRITE_1(sc, B0_POWER_CTRL, 1202 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON); 1203 /* Disable Core Clock Division, set Clock Select to 0. */ 1204 CSR_WRITE_4(sc, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS); 1205 1206 val = 0; 1207 if (sc->msk_hw_id == CHIP_ID_YUKON_XL && 1208 sc->msk_hw_rev > CHIP_REV_YU_XL_A1) { 1209 /* Enable bits are inverted. */ 1210 val = Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS | 1211 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS | 1212 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS; 1213 } 1214 /* 1215 * Enable PCI & Core Clock, enable clock gating for both Links. 1216 */ 1217 CSR_WRITE_1(sc, B2_Y2_CLK_GATE, val); 1218 1219 val = CSR_PCI_READ_4(sc, PCI_OUR_REG_1); 1220 val &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD); 1221 if (sc->msk_hw_id == CHIP_ID_YUKON_XL) { 1222 if (sc->msk_hw_rev > CHIP_REV_YU_XL_A1) { 1223 /* Deassert Low Power for 1st PHY. */ 1224 val |= PCI_Y2_PHY1_COMA; 1225 if (sc->msk_num_port > 1) 1226 val |= PCI_Y2_PHY2_COMA; 1227 } 1228 } 1229 /* Release PHY from PowerDown/COMA mode. */ 1230 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_1, val); 1231 switch (sc->msk_hw_id) { 1232 case CHIP_ID_YUKON_EC_U: 1233 case CHIP_ID_YUKON_EX: 1234 case CHIP_ID_YUKON_FE_P: 1235 case CHIP_ID_YUKON_UL_2: 1236 case CHIP_ID_YUKON_OPT: 1237 CSR_WRITE_2(sc, B0_CTST, Y2_HW_WOL_OFF); 1238 1239 /* Enable all clocks. */ 1240 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_3, 0); 1241 our = CSR_PCI_READ_4(sc, PCI_OUR_REG_4); 1242 our &= (PCI_FORCE_ASPM_REQUEST|PCI_ASPM_GPHY_LINK_DOWN| 1243 PCI_ASPM_INT_FIFO_EMPTY|PCI_ASPM_CLKRUN_REQUEST); 1244 /* Set all bits to 0 except bits 15..12. */ 1245 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_4, our); 1246 our = CSR_PCI_READ_4(sc, PCI_OUR_REG_5); 1247 our &= PCI_CTL_TIM_VMAIN_AV_MSK; 1248 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_5, our); 1249 CSR_PCI_WRITE_4(sc, PCI_CFG_REG_1, 0); 1250 /* 1251 * Disable status race, workaround for 1252 * Yukon EC Ultra & Yukon EX. 1253 */ 1254 val = CSR_READ_4(sc, B2_GP_IO); 1255 val |= GLB_GPIO_STAT_RACE_DIS; 1256 CSR_WRITE_4(sc, B2_GP_IO, val); 1257 CSR_READ_4(sc, B2_GP_IO); 1258 break; 1259 default: 1260 break; 1261 } 1262 for (i = 0; i < sc->msk_num_port; i++) { 1263 CSR_WRITE_2(sc, MR_ADDR(i, GMAC_LINK_CTRL), 1264 GMLC_RST_SET); 1265 CSR_WRITE_2(sc, MR_ADDR(i, GMAC_LINK_CTRL), 1266 GMLC_RST_CLR); 1267 } 1268 break; 1269 case MSK_PHY_POWERDOWN: 1270 val = CSR_PCI_READ_4(sc, PCI_OUR_REG_1); 1271 val |= PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD; 1272 if (sc->msk_hw_id == CHIP_ID_YUKON_XL && 1273 sc->msk_hw_rev > CHIP_REV_YU_XL_A1) { 1274 val &= ~PCI_Y2_PHY1_COMA; 1275 if (sc->msk_num_port > 1) 1276 val &= ~PCI_Y2_PHY2_COMA; 1277 } 1278 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_1, val); 1279 1280 val = Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS | 1281 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS | 1282 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS; 1283 if (sc->msk_hw_id == CHIP_ID_YUKON_XL && 1284 sc->msk_hw_rev > CHIP_REV_YU_XL_A1) { 1285 /* Enable bits are inverted. */ 1286 val = 0; 1287 } 1288 /* 1289 * Disable PCI & Core Clock, disable clock gating for 1290 * both Links. 1291 */ 1292 CSR_WRITE_1(sc, B2_Y2_CLK_GATE, val); 1293 CSR_WRITE_1(sc, B0_POWER_CTRL, 1294 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_ON | PC_VCC_OFF); 1295 break; 1296 default: 1297 break; 1298 } 1299 } 1300 1301 static void 1302 mskc_reset(struct msk_softc *sc) 1303 { 1304 bus_addr_t addr; 1305 uint16_t status; 1306 uint32_t val; 1307 int i; 1308 1309 CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR); 1310 1311 /* Disable ASF. */ 1312 if (sc->msk_hw_id == CHIP_ID_YUKON_EX) { 1313 status = CSR_READ_2(sc, B28_Y2_ASF_HCU_CCSR); 1314 /* Clear AHB bridge & microcontroller reset. */ 1315 status &= ~(Y2_ASF_HCU_CCSR_AHB_RST | 1316 Y2_ASF_HCU_CCSR_CPU_RST_MODE); 1317 /* Clear ASF microcontroller state. */ 1318 status &= ~ Y2_ASF_HCU_CCSR_UC_STATE_MSK; 1319 CSR_WRITE_2(sc, B28_Y2_ASF_HCU_CCSR, status); 1320 } else 1321 CSR_WRITE_1(sc, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET); 1322 CSR_WRITE_2(sc, B0_CTST, Y2_ASF_DISABLE); 1323 1324 /* 1325 * Since we disabled ASF, S/W reset is required for Power Management. 1326 */ 1327 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); 1328 CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR); 1329 1330 /* Clear all error bits in the PCI status register. */ 1331 status = pci_read_config(sc->msk_dev, PCIR_STATUS, 2); 1332 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON); 1333 1334 pci_write_config(sc->msk_dev, PCIR_STATUS, status | 1335 PCIM_STATUS_PERR | PCIM_STATUS_SERR | PCIM_STATUS_RMABORT | 1336 PCIM_STATUS_RTABORT | PCIM_STATUS_PERRREPORT, 2); 1337 CSR_WRITE_2(sc, B0_CTST, CS_MRST_CLR); 1338 1339 switch (sc->msk_bustype) { 1340 case MSK_PEX_BUS: 1341 /* Clear all PEX errors. */ 1342 CSR_PCI_WRITE_4(sc, PEX_UNC_ERR_STAT, 0xffffffff); 1343 val = CSR_PCI_READ_4(sc, PEX_UNC_ERR_STAT); 1344 if ((val & PEX_RX_OV) != 0) { 1345 sc->msk_intrmask &= ~Y2_IS_HW_ERR; 1346 sc->msk_intrhwemask &= ~Y2_IS_PCI_EXP; 1347 } 1348 break; 1349 case MSK_PCI_BUS: 1350 case MSK_PCIX_BUS: 1351 /* Set Cache Line Size to 2(8bytes) if configured to 0. */ 1352 val = pci_read_config(sc->msk_dev, PCIR_CACHELNSZ, 1); 1353 if (val == 0) 1354 pci_write_config(sc->msk_dev, PCIR_CACHELNSZ, 2, 1); 1355 if (sc->msk_bustype == MSK_PCIX_BUS) { 1356 /* Set Cache Line Size opt. */ 1357 val = pci_read_config(sc->msk_dev, PCI_OUR_REG_1, 4); 1358 val |= PCI_CLS_OPT; 1359 pci_write_config(sc->msk_dev, PCI_OUR_REG_1, val, 4); 1360 } 1361 break; 1362 } 1363 /* Set PHY power state. */ 1364 msk_phy_power(sc, MSK_PHY_POWERUP); 1365 1366 /* Reset GPHY/GMAC Control */ 1367 for (i = 0; i < sc->msk_num_port; i++) { 1368 /* GPHY Control reset. */ 1369 CSR_WRITE_4(sc, MR_ADDR(i, GPHY_CTRL), GPC_RST_SET); 1370 CSR_WRITE_4(sc, MR_ADDR(i, GPHY_CTRL), GPC_RST_CLR); 1371 /* GMAC Control reset. */ 1372 CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), GMC_RST_SET); 1373 CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), GMC_RST_CLR); 1374 CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), GMC_F_LOOPB_OFF); 1375 if (sc->msk_hw_id == CHIP_ID_YUKON_EX) 1376 CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), 1377 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON | 1378 GMC_BYP_RETR_ON); 1379 } 1380 if (sc->msk_hw_id == CHIP_ID_YUKON_OPT && sc->msk_hw_rev == 0) { 1381 /* Disable PCIe PHY powerdown(reg 0x80, bit7). */ 1382 CSR_WRITE_4(sc, Y2_PEX_PHY_DATA, (0x0080 << 16) | 0x0080); 1383 } 1384 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 1385 1386 /* LED On. */ 1387 CSR_WRITE_2(sc, B0_CTST, Y2_LED_STAT_ON); 1388 1389 /* Clear TWSI IRQ. */ 1390 CSR_WRITE_4(sc, B2_I2C_IRQ, I2C_CLR_IRQ); 1391 1392 /* Turn off hardware timer. */ 1393 CSR_WRITE_1(sc, B2_TI_CTRL, TIM_STOP); 1394 CSR_WRITE_1(sc, B2_TI_CTRL, TIM_CLR_IRQ); 1395 1396 /* Turn off descriptor polling. */ 1397 CSR_WRITE_1(sc, B28_DPT_CTRL, DPT_STOP); 1398 1399 /* Turn off time stamps. */ 1400 CSR_WRITE_1(sc, GMAC_TI_ST_CTRL, GMT_ST_STOP); 1401 CSR_WRITE_1(sc, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ); 1402 1403 /* Configure timeout values. */ 1404 for (i = 0; i < sc->msk_num_port; i++) { 1405 CSR_WRITE_2(sc, SELECT_RAM_BUFFER(i, B3_RI_CTRL), RI_RST_SET); 1406 CSR_WRITE_2(sc, SELECT_RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR); 1407 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_R1), 1408 MSK_RI_TO_53); 1409 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XA1), 1410 MSK_RI_TO_53); 1411 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XS1), 1412 MSK_RI_TO_53); 1413 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_R1), 1414 MSK_RI_TO_53); 1415 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XA1), 1416 MSK_RI_TO_53); 1417 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XS1), 1418 MSK_RI_TO_53); 1419 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_R2), 1420 MSK_RI_TO_53); 1421 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XA2), 1422 MSK_RI_TO_53); 1423 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XS2), 1424 MSK_RI_TO_53); 1425 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_R2), 1426 MSK_RI_TO_53); 1427 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XA2), 1428 MSK_RI_TO_53); 1429 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XS2), 1430 MSK_RI_TO_53); 1431 } 1432 1433 /* Disable all interrupts. */ 1434 CSR_WRITE_4(sc, B0_HWE_IMSK, 0); 1435 CSR_READ_4(sc, B0_HWE_IMSK); 1436 CSR_WRITE_4(sc, B0_IMSK, 0); 1437 CSR_READ_4(sc, B0_IMSK); 1438 1439 /* 1440 * On dual port PCI-X card, there is an problem where status 1441 * can be received out of order due to split transactions. 1442 */ 1443 if (sc->msk_pcixcap != 0 && sc->msk_num_port > 1) { 1444 uint16_t pcix_cmd; 1445 1446 pcix_cmd = pci_read_config(sc->msk_dev, 1447 sc->msk_pcixcap + PCIXR_COMMAND, 2); 1448 /* Clear Max Outstanding Split Transactions. */ 1449 pcix_cmd &= ~PCIXM_COMMAND_MAX_SPLITS; 1450 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON); 1451 pci_write_config(sc->msk_dev, 1452 sc->msk_pcixcap + PCIXR_COMMAND, pcix_cmd, 2); 1453 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 1454 } 1455 if (sc->msk_expcap != 0) { 1456 /* Change Max. Read Request Size to 2048 bytes. */ 1457 if (pci_get_max_read_req(sc->msk_dev) == 512) 1458 pci_set_max_read_req(sc->msk_dev, 2048); 1459 } 1460 1461 /* Clear status list. */ 1462 bzero(sc->msk_stat_ring, 1463 sizeof(struct msk_stat_desc) * MSK_STAT_RING_CNT); 1464 sc->msk_stat_cons = 0; 1465 bus_dmamap_sync(sc->msk_stat_tag, sc->msk_stat_map, 1466 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1467 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_RST_SET); 1468 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_RST_CLR); 1469 /* Set the status list base address. */ 1470 addr = sc->msk_stat_ring_paddr; 1471 CSR_WRITE_4(sc, STAT_LIST_ADDR_LO, MSK_ADDR_LO(addr)); 1472 CSR_WRITE_4(sc, STAT_LIST_ADDR_HI, MSK_ADDR_HI(addr)); 1473 /* Set the status list last index. */ 1474 CSR_WRITE_2(sc, STAT_LAST_IDX, MSK_STAT_RING_CNT - 1); 1475 if (sc->msk_hw_id == CHIP_ID_YUKON_EC && 1476 sc->msk_hw_rev == CHIP_REV_YU_EC_A1) { 1477 /* WA for dev. #4.3 */ 1478 CSR_WRITE_2(sc, STAT_TX_IDX_TH, ST_TXTH_IDX_MASK); 1479 /* WA for dev. #4.18 */ 1480 CSR_WRITE_1(sc, STAT_FIFO_WM, 0x21); 1481 CSR_WRITE_1(sc, STAT_FIFO_ISR_WM, 0x07); 1482 } else { 1483 CSR_WRITE_2(sc, STAT_TX_IDX_TH, 0x0a); 1484 CSR_WRITE_1(sc, STAT_FIFO_WM, 0x10); 1485 if (sc->msk_hw_id == CHIP_ID_YUKON_XL && 1486 sc->msk_hw_rev == CHIP_REV_YU_XL_A0) 1487 CSR_WRITE_1(sc, STAT_FIFO_ISR_WM, 0x04); 1488 else 1489 CSR_WRITE_1(sc, STAT_FIFO_ISR_WM, 0x10); 1490 CSR_WRITE_4(sc, STAT_ISR_TIMER_INI, 0x0190); 1491 } 1492 /* 1493 * Use default value for STAT_ISR_TIMER_INI, STAT_LEV_TIMER_INI. 1494 */ 1495 CSR_WRITE_4(sc, STAT_TX_TIMER_INI, MSK_USECS(sc, 1000)); 1496 1497 /* Enable status unit. */ 1498 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_OP_ON); 1499 1500 CSR_WRITE_1(sc, STAT_TX_TIMER_CTRL, TIM_START); 1501 CSR_WRITE_1(sc, STAT_LEV_TIMER_CTRL, TIM_START); 1502 CSR_WRITE_1(sc, STAT_ISR_TIMER_CTRL, TIM_START); 1503 } 1504 1505 static int 1506 msk_probe(device_t dev) 1507 { 1508 struct msk_softc *sc; 1509 char desc[100]; 1510 1511 sc = device_get_softc(device_get_parent(dev)); 1512 /* 1513 * Not much to do here. We always know there will be 1514 * at least one GMAC present, and if there are two, 1515 * mskc_attach() will create a second device instance 1516 * for us. 1517 */ 1518 snprintf(desc, sizeof(desc), 1519 "Marvell Technology Group Ltd. %s Id 0x%02x Rev 0x%02x", 1520 model_name[sc->msk_hw_id - CHIP_ID_YUKON_XL], sc->msk_hw_id, 1521 sc->msk_hw_rev); 1522 device_set_desc_copy(dev, desc); 1523 1524 return (BUS_PROBE_DEFAULT); 1525 } 1526 1527 static int 1528 msk_attach(device_t dev) 1529 { 1530 struct msk_softc *sc; 1531 struct msk_if_softc *sc_if; 1532 struct ifnet *ifp; 1533 struct msk_mii_data *mmd; 1534 int i, port, error; 1535 uint8_t eaddr[6]; 1536 1537 if (dev == NULL) 1538 return (EINVAL); 1539 1540 error = 0; 1541 sc_if = device_get_softc(dev); 1542 sc = device_get_softc(device_get_parent(dev)); 1543 mmd = device_get_ivars(dev); 1544 port = mmd->port; 1545 1546 sc_if->msk_if_dev = dev; 1547 sc_if->msk_port = port; 1548 sc_if->msk_softc = sc; 1549 sc_if->msk_flags = sc->msk_pflags; 1550 sc->msk_if[port] = sc_if; 1551 /* Setup Tx/Rx queue register offsets. */ 1552 if (port == MSK_PORT_A) { 1553 sc_if->msk_txq = Q_XA1; 1554 sc_if->msk_txsq = Q_XS1; 1555 sc_if->msk_rxq = Q_R1; 1556 } else { 1557 sc_if->msk_txq = Q_XA2; 1558 sc_if->msk_txsq = Q_XS2; 1559 sc_if->msk_rxq = Q_R2; 1560 } 1561 1562 callout_init_mtx(&sc_if->msk_tick_ch, &sc_if->msk_softc->msk_mtx, 0); 1563 msk_sysctl_node(sc_if); 1564 1565 if ((error = msk_txrx_dma_alloc(sc_if) != 0)) 1566 goto fail; 1567 msk_rx_dma_jalloc(sc_if); 1568 1569 ifp = sc_if->msk_ifp = if_alloc(IFT_ETHER); 1570 if (ifp == NULL) { 1571 device_printf(sc_if->msk_if_dev, "can not if_alloc()\n"); 1572 error = ENOSPC; 1573 goto fail; 1574 } 1575 ifp->if_softc = sc_if; 1576 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1577 ifp->if_mtu = ETHERMTU; 1578 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1579 ifp->if_capabilities = IFCAP_TXCSUM | IFCAP_TSO4; 1580 /* 1581 * Enable Rx checksum offloading if controller supports 1582 * new descriptor formant and controller is not Yukon XL. 1583 */ 1584 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0 && 1585 sc->msk_hw_id != CHIP_ID_YUKON_XL) 1586 ifp->if_capabilities |= IFCAP_RXCSUM; 1587 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) != 0 && 1588 (sc_if->msk_flags & MSK_FLAG_NORX_CSUM) == 0) 1589 ifp->if_capabilities |= IFCAP_RXCSUM; 1590 ifp->if_hwassist = MSK_CSUM_FEATURES | CSUM_TSO; 1591 ifp->if_capenable = ifp->if_capabilities; 1592 ifp->if_ioctl = msk_ioctl; 1593 ifp->if_start = msk_start; 1594 ifp->if_init = msk_init; 1595 IFQ_SET_MAXLEN(&ifp->if_snd, MSK_TX_RING_CNT - 1); 1596 ifp->if_snd.ifq_drv_maxlen = MSK_TX_RING_CNT - 1; 1597 IFQ_SET_READY(&ifp->if_snd); 1598 /* 1599 * Get station address for this interface. Note that 1600 * dual port cards actually come with three station 1601 * addresses: one for each port, plus an extra. The 1602 * extra one is used by the SysKonnect driver software 1603 * as a 'virtual' station address for when both ports 1604 * are operating in failover mode. Currently we don't 1605 * use this extra address. 1606 */ 1607 MSK_IF_LOCK(sc_if); 1608 for (i = 0; i < ETHER_ADDR_LEN; i++) 1609 eaddr[i] = CSR_READ_1(sc, B2_MAC_1 + (port * 8) + i); 1610 1611 /* 1612 * Call MI attach routine. Can't hold locks when calling into ether_*. 1613 */ 1614 MSK_IF_UNLOCK(sc_if); 1615 ether_ifattach(ifp, eaddr); 1616 MSK_IF_LOCK(sc_if); 1617 1618 /* VLAN capability setup */ 1619 ifp->if_capabilities |= IFCAP_VLAN_MTU; 1620 if ((sc_if->msk_flags & MSK_FLAG_NOHWVLAN) == 0) { 1621 /* 1622 * Due to Tx checksum offload hardware bugs, msk(4) manually 1623 * computes checksum for short frames. For VLAN tagged frames 1624 * this workaround does not work so disable checksum offload 1625 * for VLAN interface. 1626 */ 1627 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWTSO; 1628 /* 1629 * Enable Rx checksum offloading for VLAN taggedd frames 1630 * if controller support new descriptor format. 1631 */ 1632 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) != 0 && 1633 (sc_if->msk_flags & MSK_FLAG_NORX_CSUM) == 0) 1634 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM; 1635 } 1636 ifp->if_capenable = ifp->if_capabilities; 1637 1638 /* 1639 * Tell the upper layer(s) we support long frames. 1640 * Must appear after the call to ether_ifattach() because 1641 * ether_ifattach() sets ifi_hdrlen to the default value. 1642 */ 1643 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1644 1645 /* 1646 * Do miibus setup. 1647 */ 1648 MSK_IF_UNLOCK(sc_if); 1649 error = mii_phy_probe(dev, &sc_if->msk_miibus, msk_mediachange, 1650 msk_mediastatus); 1651 if (error != 0) { 1652 device_printf(sc_if->msk_if_dev, "no PHY found!\n"); 1653 ether_ifdetach(ifp); 1654 error = ENXIO; 1655 goto fail; 1656 } 1657 1658 fail: 1659 if (error != 0) { 1660 /* Access should be ok even though lock has been dropped */ 1661 sc->msk_if[port] = NULL; 1662 msk_detach(dev); 1663 } 1664 1665 return (error); 1666 } 1667 1668 /* 1669 * Attach the interface. Allocate softc structures, do ifmedia 1670 * setup and ethernet/BPF attach. 1671 */ 1672 static int 1673 mskc_attach(device_t dev) 1674 { 1675 struct msk_softc *sc; 1676 struct msk_mii_data *mmd; 1677 int error, msic, msir, reg; 1678 1679 sc = device_get_softc(dev); 1680 sc->msk_dev = dev; 1681 mtx_init(&sc->msk_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1682 MTX_DEF); 1683 1684 /* 1685 * Map control/status registers. 1686 */ 1687 pci_enable_busmaster(dev); 1688 1689 /* Allocate I/O resource */ 1690 #ifdef MSK_USEIOSPACE 1691 sc->msk_res_spec = msk_res_spec_io; 1692 #else 1693 sc->msk_res_spec = msk_res_spec_mem; 1694 #endif 1695 sc->msk_irq_spec = msk_irq_spec_legacy; 1696 error = bus_alloc_resources(dev, sc->msk_res_spec, sc->msk_res); 1697 if (error) { 1698 if (sc->msk_res_spec == msk_res_spec_mem) 1699 sc->msk_res_spec = msk_res_spec_io; 1700 else 1701 sc->msk_res_spec = msk_res_spec_mem; 1702 error = bus_alloc_resources(dev, sc->msk_res_spec, sc->msk_res); 1703 if (error) { 1704 device_printf(dev, "couldn't allocate %s resources\n", 1705 sc->msk_res_spec == msk_res_spec_mem ? "memory" : 1706 "I/O"); 1707 mtx_destroy(&sc->msk_mtx); 1708 return (ENXIO); 1709 } 1710 } 1711 1712 CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR); 1713 sc->msk_hw_id = CSR_READ_1(sc, B2_CHIP_ID); 1714 sc->msk_hw_rev = (CSR_READ_1(sc, B2_MAC_CFG) >> 4) & 0x0f; 1715 /* Bail out if chip is not recognized. */ 1716 if (sc->msk_hw_id < CHIP_ID_YUKON_XL || 1717 sc->msk_hw_id > CHIP_ID_YUKON_OPT || 1718 sc->msk_hw_id == CHIP_ID_YUKON_SUPR || 1719 sc->msk_hw_id == CHIP_ID_YUKON_UNKNOWN) { 1720 device_printf(dev, "unknown device: id=0x%02x, rev=0x%02x\n", 1721 sc->msk_hw_id, sc->msk_hw_rev); 1722 mtx_destroy(&sc->msk_mtx); 1723 return (ENXIO); 1724 } 1725 1726 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 1727 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 1728 OID_AUTO, "process_limit", CTLTYPE_INT | CTLFLAG_RW, 1729 &sc->msk_process_limit, 0, sysctl_hw_msk_proc_limit, "I", 1730 "max number of Rx events to process"); 1731 1732 sc->msk_process_limit = MSK_PROC_DEFAULT; 1733 error = resource_int_value(device_get_name(dev), device_get_unit(dev), 1734 "process_limit", &sc->msk_process_limit); 1735 if (error == 0) { 1736 if (sc->msk_process_limit < MSK_PROC_MIN || 1737 sc->msk_process_limit > MSK_PROC_MAX) { 1738 device_printf(dev, "process_limit value out of range; " 1739 "using default: %d\n", MSK_PROC_DEFAULT); 1740 sc->msk_process_limit = MSK_PROC_DEFAULT; 1741 } 1742 } 1743 1744 sc->msk_int_holdoff = MSK_INT_HOLDOFF_DEFAULT; 1745 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 1746 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 1747 "int_holdoff", CTLFLAG_RW, &sc->msk_int_holdoff, 0, 1748 "Maximum number of time to delay interrupts"); 1749 resource_int_value(device_get_name(dev), device_get_unit(dev), 1750 "int_holdoff", &sc->msk_int_holdoff); 1751 1752 /* Soft reset. */ 1753 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); 1754 CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR); 1755 sc->msk_pmd = CSR_READ_1(sc, B2_PMD_TYP); 1756 /* Check number of MACs. */ 1757 sc->msk_num_port = 1; 1758 if ((CSR_READ_1(sc, B2_Y2_HW_RES) & CFG_DUAL_MAC_MSK) == 1759 CFG_DUAL_MAC_MSK) { 1760 if (!(CSR_READ_1(sc, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC)) 1761 sc->msk_num_port++; 1762 } 1763 1764 /* Check bus type. */ 1765 if (pci_find_extcap(sc->msk_dev, PCIY_EXPRESS, ®) == 0) { 1766 sc->msk_bustype = MSK_PEX_BUS; 1767 sc->msk_expcap = reg; 1768 } else if (pci_find_extcap(sc->msk_dev, PCIY_PCIX, ®) == 0) { 1769 sc->msk_bustype = MSK_PCIX_BUS; 1770 sc->msk_pcixcap = reg; 1771 } else 1772 sc->msk_bustype = MSK_PCI_BUS; 1773 1774 switch (sc->msk_hw_id) { 1775 case CHIP_ID_YUKON_EC: 1776 sc->msk_clock = 125; /* 125 MHz */ 1777 sc->msk_pflags |= MSK_FLAG_JUMBO; 1778 break; 1779 case CHIP_ID_YUKON_EC_U: 1780 sc->msk_clock = 125; /* 125 MHz */ 1781 sc->msk_pflags |= MSK_FLAG_JUMBO | MSK_FLAG_JUMBO_NOCSUM; 1782 break; 1783 case CHIP_ID_YUKON_EX: 1784 sc->msk_clock = 125; /* 125 MHz */ 1785 sc->msk_pflags |= MSK_FLAG_JUMBO | MSK_FLAG_DESCV2 | 1786 MSK_FLAG_AUTOTX_CSUM; 1787 /* 1788 * Yukon Extreme seems to have silicon bug for 1789 * automatic Tx checksum calculation capability. 1790 */ 1791 if (sc->msk_hw_rev == CHIP_REV_YU_EX_B0) 1792 sc->msk_pflags &= ~MSK_FLAG_AUTOTX_CSUM; 1793 /* 1794 * Yukon Extreme A0 could not use store-and-forward 1795 * for jumbo frames, so disable Tx checksum 1796 * offloading for jumbo frames. 1797 */ 1798 if (sc->msk_hw_rev == CHIP_REV_YU_EX_A0) 1799 sc->msk_pflags |= MSK_FLAG_JUMBO_NOCSUM; 1800 break; 1801 case CHIP_ID_YUKON_FE: 1802 sc->msk_clock = 100; /* 100 MHz */ 1803 sc->msk_pflags |= MSK_FLAG_FASTETHER; 1804 break; 1805 case CHIP_ID_YUKON_FE_P: 1806 sc->msk_clock = 50; /* 50 MHz */ 1807 sc->msk_pflags |= MSK_FLAG_FASTETHER | MSK_FLAG_DESCV2 | 1808 MSK_FLAG_AUTOTX_CSUM; 1809 if (sc->msk_hw_rev == CHIP_REV_YU_FE_P_A0) { 1810 /* 1811 * XXX 1812 * FE+ A0 has status LE writeback bug so msk(4) 1813 * does not rely on status word of received frame 1814 * in msk_rxeof() which in turn disables all 1815 * hardware assistance bits reported by the status 1816 * word as well as validity of the recevied frame. 1817 * Just pass received frames to upper stack with 1818 * minimal test and let upper stack handle them. 1819 */ 1820 sc->msk_pflags |= MSK_FLAG_NOHWVLAN | 1821 MSK_FLAG_NORXCHK | MSK_FLAG_NORX_CSUM; 1822 } 1823 break; 1824 case CHIP_ID_YUKON_XL: 1825 sc->msk_clock = 156; /* 156 MHz */ 1826 sc->msk_pflags |= MSK_FLAG_JUMBO; 1827 break; 1828 case CHIP_ID_YUKON_UL_2: 1829 sc->msk_clock = 125; /* 125 MHz */ 1830 sc->msk_pflags |= MSK_FLAG_JUMBO; 1831 break; 1832 case CHIP_ID_YUKON_OPT: 1833 sc->msk_clock = 125; /* 125 MHz */ 1834 sc->msk_pflags |= MSK_FLAG_JUMBO | MSK_FLAG_DESCV2; 1835 break; 1836 default: 1837 sc->msk_clock = 156; /* 156 MHz */ 1838 break; 1839 } 1840 1841 /* Allocate IRQ resources. */ 1842 msic = pci_msi_count(dev); 1843 if (bootverbose) 1844 device_printf(dev, "MSI count : %d\n", msic); 1845 if (legacy_intr != 0) 1846 msi_disable = 1; 1847 if (msi_disable == 0 && msic > 0) { 1848 msir = 1; 1849 if (pci_alloc_msi(dev, &msir) == 0) { 1850 if (msir == 1) { 1851 sc->msk_pflags |= MSK_FLAG_MSI; 1852 sc->msk_irq_spec = msk_irq_spec_msi; 1853 } else 1854 pci_release_msi(dev); 1855 } 1856 } 1857 1858 error = bus_alloc_resources(dev, sc->msk_irq_spec, sc->msk_irq); 1859 if (error) { 1860 device_printf(dev, "couldn't allocate IRQ resources\n"); 1861 goto fail; 1862 } 1863 1864 if ((error = msk_status_dma_alloc(sc)) != 0) 1865 goto fail; 1866 1867 /* Set base interrupt mask. */ 1868 sc->msk_intrmask = Y2_IS_HW_ERR | Y2_IS_STAT_BMU; 1869 sc->msk_intrhwemask = Y2_IS_TIST_OV | Y2_IS_MST_ERR | 1870 Y2_IS_IRQ_STAT | Y2_IS_PCI_EXP | Y2_IS_PCI_NEXP; 1871 1872 /* Reset the adapter. */ 1873 mskc_reset(sc); 1874 1875 if ((error = mskc_setup_rambuffer(sc)) != 0) 1876 goto fail; 1877 1878 sc->msk_devs[MSK_PORT_A] = device_add_child(dev, "msk", -1); 1879 if (sc->msk_devs[MSK_PORT_A] == NULL) { 1880 device_printf(dev, "failed to add child for PORT_A\n"); 1881 error = ENXIO; 1882 goto fail; 1883 } 1884 mmd = malloc(sizeof(struct msk_mii_data), M_DEVBUF, M_WAITOK | M_ZERO); 1885 if (mmd == NULL) { 1886 device_printf(dev, "failed to allocate memory for " 1887 "ivars of PORT_A\n"); 1888 error = ENXIO; 1889 goto fail; 1890 } 1891 mmd->port = MSK_PORT_A; 1892 mmd->pmd = sc->msk_pmd; 1893 if (sc->msk_pmd == 'L' || sc->msk_pmd == 'S' || sc->msk_pmd == 'P') 1894 mmd->mii_flags |= MIIF_HAVEFIBER; 1895 device_set_ivars(sc->msk_devs[MSK_PORT_A], mmd); 1896 1897 if (sc->msk_num_port > 1) { 1898 sc->msk_devs[MSK_PORT_B] = device_add_child(dev, "msk", -1); 1899 if (sc->msk_devs[MSK_PORT_B] == NULL) { 1900 device_printf(dev, "failed to add child for PORT_B\n"); 1901 error = ENXIO; 1902 goto fail; 1903 } 1904 mmd = malloc(sizeof(struct msk_mii_data), M_DEVBUF, M_WAITOK | M_ZERO); 1905 if (mmd == NULL) { 1906 device_printf(dev, "failed to allocate memory for " 1907 "ivars of PORT_B\n"); 1908 error = ENXIO; 1909 goto fail; 1910 } 1911 mmd->port = MSK_PORT_B; 1912 mmd->pmd = sc->msk_pmd; 1913 if (sc->msk_pmd == 'L' || sc->msk_pmd == 'S' || sc->msk_pmd == 'P') 1914 mmd->mii_flags |= MIIF_HAVEFIBER; 1915 device_set_ivars(sc->msk_devs[MSK_PORT_B], mmd); 1916 } 1917 1918 error = bus_generic_attach(dev); 1919 if (error) { 1920 device_printf(dev, "failed to attach port(s)\n"); 1921 goto fail; 1922 } 1923 1924 /* Hook interrupt last to avoid having to lock softc. */ 1925 error = bus_setup_intr(dev, sc->msk_irq[0], INTR_TYPE_NET | 1926 INTR_MPSAFE, NULL, msk_intr, sc, &sc->msk_intrhand); 1927 if (error != 0) { 1928 device_printf(dev, "couldn't set up interrupt handler\n"); 1929 goto fail; 1930 } 1931 fail: 1932 if (error != 0) 1933 mskc_detach(dev); 1934 1935 return (error); 1936 } 1937 1938 /* 1939 * Shutdown hardware and free up resources. This can be called any 1940 * time after the mutex has been initialized. It is called in both 1941 * the error case in attach and the normal detach case so it needs 1942 * to be careful about only freeing resources that have actually been 1943 * allocated. 1944 */ 1945 static int 1946 msk_detach(device_t dev) 1947 { 1948 struct msk_softc *sc; 1949 struct msk_if_softc *sc_if; 1950 struct ifnet *ifp; 1951 1952 sc_if = device_get_softc(dev); 1953 KASSERT(mtx_initialized(&sc_if->msk_softc->msk_mtx), 1954 ("msk mutex not initialized in msk_detach")); 1955 MSK_IF_LOCK(sc_if); 1956 1957 ifp = sc_if->msk_ifp; 1958 if (device_is_attached(dev)) { 1959 /* XXX */ 1960 sc_if->msk_flags |= MSK_FLAG_DETACH; 1961 msk_stop(sc_if); 1962 /* Can't hold locks while calling detach. */ 1963 MSK_IF_UNLOCK(sc_if); 1964 callout_drain(&sc_if->msk_tick_ch); 1965 ether_ifdetach(ifp); 1966 MSK_IF_LOCK(sc_if); 1967 } 1968 1969 /* 1970 * We're generally called from mskc_detach() which is using 1971 * device_delete_child() to get to here. It's already trashed 1972 * miibus for us, so don't do it here or we'll panic. 1973 * 1974 * if (sc_if->msk_miibus != NULL) { 1975 * device_delete_child(dev, sc_if->msk_miibus); 1976 * sc_if->msk_miibus = NULL; 1977 * } 1978 */ 1979 1980 msk_rx_dma_jfree(sc_if); 1981 msk_txrx_dma_free(sc_if); 1982 bus_generic_detach(dev); 1983 1984 if (ifp) 1985 if_free(ifp); 1986 sc = sc_if->msk_softc; 1987 sc->msk_if[sc_if->msk_port] = NULL; 1988 MSK_IF_UNLOCK(sc_if); 1989 1990 return (0); 1991 } 1992 1993 static int 1994 mskc_detach(device_t dev) 1995 { 1996 struct msk_softc *sc; 1997 1998 sc = device_get_softc(dev); 1999 KASSERT(mtx_initialized(&sc->msk_mtx), ("msk mutex not initialized")); 2000 2001 if (device_is_alive(dev)) { 2002 if (sc->msk_devs[MSK_PORT_A] != NULL) { 2003 free(device_get_ivars(sc->msk_devs[MSK_PORT_A]), 2004 M_DEVBUF); 2005 device_delete_child(dev, sc->msk_devs[MSK_PORT_A]); 2006 } 2007 if (sc->msk_devs[MSK_PORT_B] != NULL) { 2008 free(device_get_ivars(sc->msk_devs[MSK_PORT_B]), 2009 M_DEVBUF); 2010 device_delete_child(dev, sc->msk_devs[MSK_PORT_B]); 2011 } 2012 bus_generic_detach(dev); 2013 } 2014 2015 /* Disable all interrupts. */ 2016 CSR_WRITE_4(sc, B0_IMSK, 0); 2017 CSR_READ_4(sc, B0_IMSK); 2018 CSR_WRITE_4(sc, B0_HWE_IMSK, 0); 2019 CSR_READ_4(sc, B0_HWE_IMSK); 2020 2021 /* LED Off. */ 2022 CSR_WRITE_2(sc, B0_CTST, Y2_LED_STAT_OFF); 2023 2024 /* Put hardware reset. */ 2025 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); 2026 2027 msk_status_dma_free(sc); 2028 2029 if (sc->msk_intrhand) { 2030 bus_teardown_intr(dev, sc->msk_irq[0], sc->msk_intrhand); 2031 sc->msk_intrhand = NULL; 2032 } 2033 bus_release_resources(dev, sc->msk_irq_spec, sc->msk_irq); 2034 if ((sc->msk_pflags & MSK_FLAG_MSI) != 0) 2035 pci_release_msi(dev); 2036 bus_release_resources(dev, sc->msk_res_spec, sc->msk_res); 2037 mtx_destroy(&sc->msk_mtx); 2038 2039 return (0); 2040 } 2041 2042 struct msk_dmamap_arg { 2043 bus_addr_t msk_busaddr; 2044 }; 2045 2046 static void 2047 msk_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 2048 { 2049 struct msk_dmamap_arg *ctx; 2050 2051 if (error != 0) 2052 return; 2053 ctx = arg; 2054 ctx->msk_busaddr = segs[0].ds_addr; 2055 } 2056 2057 /* Create status DMA region. */ 2058 static int 2059 msk_status_dma_alloc(struct msk_softc *sc) 2060 { 2061 struct msk_dmamap_arg ctx; 2062 int error; 2063 2064 error = bus_dma_tag_create( 2065 bus_get_dma_tag(sc->msk_dev), /* parent */ 2066 MSK_STAT_ALIGN, 0, /* alignment, boundary */ 2067 BUS_SPACE_MAXADDR, /* lowaddr */ 2068 BUS_SPACE_MAXADDR, /* highaddr */ 2069 NULL, NULL, /* filter, filterarg */ 2070 MSK_STAT_RING_SZ, /* maxsize */ 2071 1, /* nsegments */ 2072 MSK_STAT_RING_SZ, /* maxsegsize */ 2073 0, /* flags */ 2074 NULL, NULL, /* lockfunc, lockarg */ 2075 &sc->msk_stat_tag); 2076 if (error != 0) { 2077 device_printf(sc->msk_dev, 2078 "failed to create status DMA tag\n"); 2079 return (error); 2080 } 2081 2082 /* Allocate DMA'able memory and load the DMA map for status ring. */ 2083 error = bus_dmamem_alloc(sc->msk_stat_tag, 2084 (void **)&sc->msk_stat_ring, BUS_DMA_WAITOK | BUS_DMA_COHERENT | 2085 BUS_DMA_ZERO, &sc->msk_stat_map); 2086 if (error != 0) { 2087 device_printf(sc->msk_dev, 2088 "failed to allocate DMA'able memory for status ring\n"); 2089 return (error); 2090 } 2091 2092 ctx.msk_busaddr = 0; 2093 error = bus_dmamap_load(sc->msk_stat_tag, 2094 sc->msk_stat_map, sc->msk_stat_ring, MSK_STAT_RING_SZ, 2095 msk_dmamap_cb, &ctx, 0); 2096 if (error != 0) { 2097 device_printf(sc->msk_dev, 2098 "failed to load DMA'able memory for status ring\n"); 2099 return (error); 2100 } 2101 sc->msk_stat_ring_paddr = ctx.msk_busaddr; 2102 2103 return (0); 2104 } 2105 2106 static void 2107 msk_status_dma_free(struct msk_softc *sc) 2108 { 2109 2110 /* Destroy status block. */ 2111 if (sc->msk_stat_tag) { 2112 if (sc->msk_stat_map) { 2113 bus_dmamap_unload(sc->msk_stat_tag, sc->msk_stat_map); 2114 if (sc->msk_stat_ring) { 2115 bus_dmamem_free(sc->msk_stat_tag, 2116 sc->msk_stat_ring, sc->msk_stat_map); 2117 sc->msk_stat_ring = NULL; 2118 } 2119 sc->msk_stat_map = NULL; 2120 } 2121 bus_dma_tag_destroy(sc->msk_stat_tag); 2122 sc->msk_stat_tag = NULL; 2123 } 2124 } 2125 2126 static int 2127 msk_txrx_dma_alloc(struct msk_if_softc *sc_if) 2128 { 2129 struct msk_dmamap_arg ctx; 2130 struct msk_txdesc *txd; 2131 struct msk_rxdesc *rxd; 2132 bus_size_t rxalign; 2133 int error, i; 2134 2135 /* Create parent DMA tag. */ 2136 /* 2137 * XXX 2138 * It seems that Yukon II supports full 64bits DMA operations. But 2139 * it needs two descriptors(list elements) for 64bits DMA operations. 2140 * Since we don't know what DMA address mappings(32bits or 64bits) 2141 * would be used in advance for each mbufs, we limits its DMA space 2142 * to be in range of 32bits address space. Otherwise, we should check 2143 * what DMA address is used and chain another descriptor for the 2144 * 64bits DMA operation. This also means descriptor ring size is 2145 * variable. Limiting DMA address to be in 32bit address space greatly 2146 * simplyfies descriptor handling and possibly would increase 2147 * performance a bit due to efficient handling of descriptors. 2148 * Apart from harassing checksum offloading mechanisms, it seems 2149 * it's really bad idea to use a seperate descriptor for 64bit 2150 * DMA operation to save small descriptor memory. Anyway, I've 2151 * never seen these exotic scheme on ethernet interface hardware. 2152 */ 2153 error = bus_dma_tag_create( 2154 bus_get_dma_tag(sc_if->msk_if_dev), /* parent */ 2155 1, 0, /* alignment, boundary */ 2156 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 2157 BUS_SPACE_MAXADDR, /* highaddr */ 2158 NULL, NULL, /* filter, filterarg */ 2159 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 2160 0, /* nsegments */ 2161 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 2162 0, /* flags */ 2163 NULL, NULL, /* lockfunc, lockarg */ 2164 &sc_if->msk_cdata.msk_parent_tag); 2165 if (error != 0) { 2166 device_printf(sc_if->msk_if_dev, 2167 "failed to create parent DMA tag\n"); 2168 goto fail; 2169 } 2170 /* Create tag for Tx ring. */ 2171 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2172 MSK_RING_ALIGN, 0, /* alignment, boundary */ 2173 BUS_SPACE_MAXADDR, /* lowaddr */ 2174 BUS_SPACE_MAXADDR, /* highaddr */ 2175 NULL, NULL, /* filter, filterarg */ 2176 MSK_TX_RING_SZ, /* maxsize */ 2177 1, /* nsegments */ 2178 MSK_TX_RING_SZ, /* maxsegsize */ 2179 0, /* flags */ 2180 NULL, NULL, /* lockfunc, lockarg */ 2181 &sc_if->msk_cdata.msk_tx_ring_tag); 2182 if (error != 0) { 2183 device_printf(sc_if->msk_if_dev, 2184 "failed to create Tx ring DMA tag\n"); 2185 goto fail; 2186 } 2187 2188 /* Create tag for Rx ring. */ 2189 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2190 MSK_RING_ALIGN, 0, /* alignment, boundary */ 2191 BUS_SPACE_MAXADDR, /* lowaddr */ 2192 BUS_SPACE_MAXADDR, /* highaddr */ 2193 NULL, NULL, /* filter, filterarg */ 2194 MSK_RX_RING_SZ, /* maxsize */ 2195 1, /* nsegments */ 2196 MSK_RX_RING_SZ, /* maxsegsize */ 2197 0, /* flags */ 2198 NULL, NULL, /* lockfunc, lockarg */ 2199 &sc_if->msk_cdata.msk_rx_ring_tag); 2200 if (error != 0) { 2201 device_printf(sc_if->msk_if_dev, 2202 "failed to create Rx ring DMA tag\n"); 2203 goto fail; 2204 } 2205 2206 /* Create tag for Tx buffers. */ 2207 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2208 1, 0, /* alignment, boundary */ 2209 BUS_SPACE_MAXADDR, /* lowaddr */ 2210 BUS_SPACE_MAXADDR, /* highaddr */ 2211 NULL, NULL, /* filter, filterarg */ 2212 MSK_TSO_MAXSIZE, /* maxsize */ 2213 MSK_MAXTXSEGS, /* nsegments */ 2214 MSK_TSO_MAXSGSIZE, /* maxsegsize */ 2215 0, /* flags */ 2216 NULL, NULL, /* lockfunc, lockarg */ 2217 &sc_if->msk_cdata.msk_tx_tag); 2218 if (error != 0) { 2219 device_printf(sc_if->msk_if_dev, 2220 "failed to create Tx DMA tag\n"); 2221 goto fail; 2222 } 2223 2224 rxalign = 1; 2225 /* 2226 * Workaround hardware hang which seems to happen when Rx buffer 2227 * is not aligned on multiple of FIFO word(8 bytes). 2228 */ 2229 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) != 0) 2230 rxalign = MSK_RX_BUF_ALIGN; 2231 /* Create tag for Rx buffers. */ 2232 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2233 rxalign, 0, /* alignment, boundary */ 2234 BUS_SPACE_MAXADDR, /* lowaddr */ 2235 BUS_SPACE_MAXADDR, /* highaddr */ 2236 NULL, NULL, /* filter, filterarg */ 2237 MCLBYTES, /* maxsize */ 2238 1, /* nsegments */ 2239 MCLBYTES, /* maxsegsize */ 2240 0, /* flags */ 2241 NULL, NULL, /* lockfunc, lockarg */ 2242 &sc_if->msk_cdata.msk_rx_tag); 2243 if (error != 0) { 2244 device_printf(sc_if->msk_if_dev, 2245 "failed to create Rx DMA tag\n"); 2246 goto fail; 2247 } 2248 2249 /* Allocate DMA'able memory and load the DMA map for Tx ring. */ 2250 error = bus_dmamem_alloc(sc_if->msk_cdata.msk_tx_ring_tag, 2251 (void **)&sc_if->msk_rdata.msk_tx_ring, BUS_DMA_WAITOK | 2252 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc_if->msk_cdata.msk_tx_ring_map); 2253 if (error != 0) { 2254 device_printf(sc_if->msk_if_dev, 2255 "failed to allocate DMA'able memory for Tx ring\n"); 2256 goto fail; 2257 } 2258 2259 ctx.msk_busaddr = 0; 2260 error = bus_dmamap_load(sc_if->msk_cdata.msk_tx_ring_tag, 2261 sc_if->msk_cdata.msk_tx_ring_map, sc_if->msk_rdata.msk_tx_ring, 2262 MSK_TX_RING_SZ, msk_dmamap_cb, &ctx, 0); 2263 if (error != 0) { 2264 device_printf(sc_if->msk_if_dev, 2265 "failed to load DMA'able memory for Tx ring\n"); 2266 goto fail; 2267 } 2268 sc_if->msk_rdata.msk_tx_ring_paddr = ctx.msk_busaddr; 2269 2270 /* Allocate DMA'able memory and load the DMA map for Rx ring. */ 2271 error = bus_dmamem_alloc(sc_if->msk_cdata.msk_rx_ring_tag, 2272 (void **)&sc_if->msk_rdata.msk_rx_ring, BUS_DMA_WAITOK | 2273 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc_if->msk_cdata.msk_rx_ring_map); 2274 if (error != 0) { 2275 device_printf(sc_if->msk_if_dev, 2276 "failed to allocate DMA'able memory for Rx ring\n"); 2277 goto fail; 2278 } 2279 2280 ctx.msk_busaddr = 0; 2281 error = bus_dmamap_load(sc_if->msk_cdata.msk_rx_ring_tag, 2282 sc_if->msk_cdata.msk_rx_ring_map, sc_if->msk_rdata.msk_rx_ring, 2283 MSK_RX_RING_SZ, msk_dmamap_cb, &ctx, 0); 2284 if (error != 0) { 2285 device_printf(sc_if->msk_if_dev, 2286 "failed to load DMA'able memory for Rx ring\n"); 2287 goto fail; 2288 } 2289 sc_if->msk_rdata.msk_rx_ring_paddr = ctx.msk_busaddr; 2290 2291 /* Create DMA maps for Tx buffers. */ 2292 for (i = 0; i < MSK_TX_RING_CNT; i++) { 2293 txd = &sc_if->msk_cdata.msk_txdesc[i]; 2294 txd->tx_m = NULL; 2295 txd->tx_dmamap = NULL; 2296 error = bus_dmamap_create(sc_if->msk_cdata.msk_tx_tag, 0, 2297 &txd->tx_dmamap); 2298 if (error != 0) { 2299 device_printf(sc_if->msk_if_dev, 2300 "failed to create Tx dmamap\n"); 2301 goto fail; 2302 } 2303 } 2304 /* Create DMA maps for Rx buffers. */ 2305 if ((error = bus_dmamap_create(sc_if->msk_cdata.msk_rx_tag, 0, 2306 &sc_if->msk_cdata.msk_rx_sparemap)) != 0) { 2307 device_printf(sc_if->msk_if_dev, 2308 "failed to create spare Rx dmamap\n"); 2309 goto fail; 2310 } 2311 for (i = 0; i < MSK_RX_RING_CNT; i++) { 2312 rxd = &sc_if->msk_cdata.msk_rxdesc[i]; 2313 rxd->rx_m = NULL; 2314 rxd->rx_dmamap = NULL; 2315 error = bus_dmamap_create(sc_if->msk_cdata.msk_rx_tag, 0, 2316 &rxd->rx_dmamap); 2317 if (error != 0) { 2318 device_printf(sc_if->msk_if_dev, 2319 "failed to create Rx dmamap\n"); 2320 goto fail; 2321 } 2322 } 2323 2324 fail: 2325 return (error); 2326 } 2327 2328 static int 2329 msk_rx_dma_jalloc(struct msk_if_softc *sc_if) 2330 { 2331 struct msk_dmamap_arg ctx; 2332 struct msk_rxdesc *jrxd; 2333 bus_size_t rxalign; 2334 int error, i; 2335 2336 if (jumbo_disable != 0 || (sc_if->msk_flags & MSK_FLAG_JUMBO) == 0) { 2337 sc_if->msk_flags &= ~MSK_FLAG_JUMBO; 2338 device_printf(sc_if->msk_if_dev, 2339 "disabling jumbo frame support\n"); 2340 return (0); 2341 } 2342 /* Create tag for jumbo Rx ring. */ 2343 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2344 MSK_RING_ALIGN, 0, /* alignment, boundary */ 2345 BUS_SPACE_MAXADDR, /* lowaddr */ 2346 BUS_SPACE_MAXADDR, /* highaddr */ 2347 NULL, NULL, /* filter, filterarg */ 2348 MSK_JUMBO_RX_RING_SZ, /* maxsize */ 2349 1, /* nsegments */ 2350 MSK_JUMBO_RX_RING_SZ, /* maxsegsize */ 2351 0, /* flags */ 2352 NULL, NULL, /* lockfunc, lockarg */ 2353 &sc_if->msk_cdata.msk_jumbo_rx_ring_tag); 2354 if (error != 0) { 2355 device_printf(sc_if->msk_if_dev, 2356 "failed to create jumbo Rx ring DMA tag\n"); 2357 goto jumbo_fail; 2358 } 2359 2360 rxalign = 1; 2361 /* 2362 * Workaround hardware hang which seems to happen when Rx buffer 2363 * is not aligned on multiple of FIFO word(8 bytes). 2364 */ 2365 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) != 0) 2366 rxalign = MSK_RX_BUF_ALIGN; 2367 /* Create tag for jumbo Rx buffers. */ 2368 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2369 rxalign, 0, /* alignment, boundary */ 2370 BUS_SPACE_MAXADDR, /* lowaddr */ 2371 BUS_SPACE_MAXADDR, /* highaddr */ 2372 NULL, NULL, /* filter, filterarg */ 2373 MJUM9BYTES, /* maxsize */ 2374 1, /* nsegments */ 2375 MJUM9BYTES, /* maxsegsize */ 2376 0, /* flags */ 2377 NULL, NULL, /* lockfunc, lockarg */ 2378 &sc_if->msk_cdata.msk_jumbo_rx_tag); 2379 if (error != 0) { 2380 device_printf(sc_if->msk_if_dev, 2381 "failed to create jumbo Rx DMA tag\n"); 2382 goto jumbo_fail; 2383 } 2384 2385 /* Allocate DMA'able memory and load the DMA map for jumbo Rx ring. */ 2386 error = bus_dmamem_alloc(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 2387 (void **)&sc_if->msk_rdata.msk_jumbo_rx_ring, 2388 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 2389 &sc_if->msk_cdata.msk_jumbo_rx_ring_map); 2390 if (error != 0) { 2391 device_printf(sc_if->msk_if_dev, 2392 "failed to allocate DMA'able memory for jumbo Rx ring\n"); 2393 goto jumbo_fail; 2394 } 2395 2396 ctx.msk_busaddr = 0; 2397 error = bus_dmamap_load(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 2398 sc_if->msk_cdata.msk_jumbo_rx_ring_map, 2399 sc_if->msk_rdata.msk_jumbo_rx_ring, MSK_JUMBO_RX_RING_SZ, 2400 msk_dmamap_cb, &ctx, 0); 2401 if (error != 0) { 2402 device_printf(sc_if->msk_if_dev, 2403 "failed to load DMA'able memory for jumbo Rx ring\n"); 2404 goto jumbo_fail; 2405 } 2406 sc_if->msk_rdata.msk_jumbo_rx_ring_paddr = ctx.msk_busaddr; 2407 2408 /* Create DMA maps for jumbo Rx buffers. */ 2409 if ((error = bus_dmamap_create(sc_if->msk_cdata.msk_jumbo_rx_tag, 0, 2410 &sc_if->msk_cdata.msk_jumbo_rx_sparemap)) != 0) { 2411 device_printf(sc_if->msk_if_dev, 2412 "failed to create spare jumbo Rx dmamap\n"); 2413 goto jumbo_fail; 2414 } 2415 for (i = 0; i < MSK_JUMBO_RX_RING_CNT; i++) { 2416 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[i]; 2417 jrxd->rx_m = NULL; 2418 jrxd->rx_dmamap = NULL; 2419 error = bus_dmamap_create(sc_if->msk_cdata.msk_jumbo_rx_tag, 0, 2420 &jrxd->rx_dmamap); 2421 if (error != 0) { 2422 device_printf(sc_if->msk_if_dev, 2423 "failed to create jumbo Rx dmamap\n"); 2424 goto jumbo_fail; 2425 } 2426 } 2427 2428 return (0); 2429 2430 jumbo_fail: 2431 msk_rx_dma_jfree(sc_if); 2432 device_printf(sc_if->msk_if_dev, "disabling jumbo frame support " 2433 "due to resource shortage\n"); 2434 sc_if->msk_flags &= ~MSK_FLAG_JUMBO; 2435 return (error); 2436 } 2437 2438 static void 2439 msk_txrx_dma_free(struct msk_if_softc *sc_if) 2440 { 2441 struct msk_txdesc *txd; 2442 struct msk_rxdesc *rxd; 2443 int i; 2444 2445 /* Tx ring. */ 2446 if (sc_if->msk_cdata.msk_tx_ring_tag) { 2447 if (sc_if->msk_cdata.msk_tx_ring_map) 2448 bus_dmamap_unload(sc_if->msk_cdata.msk_tx_ring_tag, 2449 sc_if->msk_cdata.msk_tx_ring_map); 2450 if (sc_if->msk_cdata.msk_tx_ring_map && 2451 sc_if->msk_rdata.msk_tx_ring) 2452 bus_dmamem_free(sc_if->msk_cdata.msk_tx_ring_tag, 2453 sc_if->msk_rdata.msk_tx_ring, 2454 sc_if->msk_cdata.msk_tx_ring_map); 2455 sc_if->msk_rdata.msk_tx_ring = NULL; 2456 sc_if->msk_cdata.msk_tx_ring_map = NULL; 2457 bus_dma_tag_destroy(sc_if->msk_cdata.msk_tx_ring_tag); 2458 sc_if->msk_cdata.msk_tx_ring_tag = NULL; 2459 } 2460 /* Rx ring. */ 2461 if (sc_if->msk_cdata.msk_rx_ring_tag) { 2462 if (sc_if->msk_cdata.msk_rx_ring_map) 2463 bus_dmamap_unload(sc_if->msk_cdata.msk_rx_ring_tag, 2464 sc_if->msk_cdata.msk_rx_ring_map); 2465 if (sc_if->msk_cdata.msk_rx_ring_map && 2466 sc_if->msk_rdata.msk_rx_ring) 2467 bus_dmamem_free(sc_if->msk_cdata.msk_rx_ring_tag, 2468 sc_if->msk_rdata.msk_rx_ring, 2469 sc_if->msk_cdata.msk_rx_ring_map); 2470 sc_if->msk_rdata.msk_rx_ring = NULL; 2471 sc_if->msk_cdata.msk_rx_ring_map = NULL; 2472 bus_dma_tag_destroy(sc_if->msk_cdata.msk_rx_ring_tag); 2473 sc_if->msk_cdata.msk_rx_ring_tag = NULL; 2474 } 2475 /* Tx buffers. */ 2476 if (sc_if->msk_cdata.msk_tx_tag) { 2477 for (i = 0; i < MSK_TX_RING_CNT; i++) { 2478 txd = &sc_if->msk_cdata.msk_txdesc[i]; 2479 if (txd->tx_dmamap) { 2480 bus_dmamap_destroy(sc_if->msk_cdata.msk_tx_tag, 2481 txd->tx_dmamap); 2482 txd->tx_dmamap = NULL; 2483 } 2484 } 2485 bus_dma_tag_destroy(sc_if->msk_cdata.msk_tx_tag); 2486 sc_if->msk_cdata.msk_tx_tag = NULL; 2487 } 2488 /* Rx buffers. */ 2489 if (sc_if->msk_cdata.msk_rx_tag) { 2490 for (i = 0; i < MSK_RX_RING_CNT; i++) { 2491 rxd = &sc_if->msk_cdata.msk_rxdesc[i]; 2492 if (rxd->rx_dmamap) { 2493 bus_dmamap_destroy(sc_if->msk_cdata.msk_rx_tag, 2494 rxd->rx_dmamap); 2495 rxd->rx_dmamap = NULL; 2496 } 2497 } 2498 if (sc_if->msk_cdata.msk_rx_sparemap) { 2499 bus_dmamap_destroy(sc_if->msk_cdata.msk_rx_tag, 2500 sc_if->msk_cdata.msk_rx_sparemap); 2501 sc_if->msk_cdata.msk_rx_sparemap = 0; 2502 } 2503 bus_dma_tag_destroy(sc_if->msk_cdata.msk_rx_tag); 2504 sc_if->msk_cdata.msk_rx_tag = NULL; 2505 } 2506 if (sc_if->msk_cdata.msk_parent_tag) { 2507 bus_dma_tag_destroy(sc_if->msk_cdata.msk_parent_tag); 2508 sc_if->msk_cdata.msk_parent_tag = NULL; 2509 } 2510 } 2511 2512 static void 2513 msk_rx_dma_jfree(struct msk_if_softc *sc_if) 2514 { 2515 struct msk_rxdesc *jrxd; 2516 int i; 2517 2518 /* Jumbo Rx ring. */ 2519 if (sc_if->msk_cdata.msk_jumbo_rx_ring_tag) { 2520 if (sc_if->msk_cdata.msk_jumbo_rx_ring_map) 2521 bus_dmamap_unload(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 2522 sc_if->msk_cdata.msk_jumbo_rx_ring_map); 2523 if (sc_if->msk_cdata.msk_jumbo_rx_ring_map && 2524 sc_if->msk_rdata.msk_jumbo_rx_ring) 2525 bus_dmamem_free(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 2526 sc_if->msk_rdata.msk_jumbo_rx_ring, 2527 sc_if->msk_cdata.msk_jumbo_rx_ring_map); 2528 sc_if->msk_rdata.msk_jumbo_rx_ring = NULL; 2529 sc_if->msk_cdata.msk_jumbo_rx_ring_map = NULL; 2530 bus_dma_tag_destroy(sc_if->msk_cdata.msk_jumbo_rx_ring_tag); 2531 sc_if->msk_cdata.msk_jumbo_rx_ring_tag = NULL; 2532 } 2533 /* Jumbo Rx buffers. */ 2534 if (sc_if->msk_cdata.msk_jumbo_rx_tag) { 2535 for (i = 0; i < MSK_JUMBO_RX_RING_CNT; i++) { 2536 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[i]; 2537 if (jrxd->rx_dmamap) { 2538 bus_dmamap_destroy( 2539 sc_if->msk_cdata.msk_jumbo_rx_tag, 2540 jrxd->rx_dmamap); 2541 jrxd->rx_dmamap = NULL; 2542 } 2543 } 2544 if (sc_if->msk_cdata.msk_jumbo_rx_sparemap) { 2545 bus_dmamap_destroy(sc_if->msk_cdata.msk_jumbo_rx_tag, 2546 sc_if->msk_cdata.msk_jumbo_rx_sparemap); 2547 sc_if->msk_cdata.msk_jumbo_rx_sparemap = 0; 2548 } 2549 bus_dma_tag_destroy(sc_if->msk_cdata.msk_jumbo_rx_tag); 2550 sc_if->msk_cdata.msk_jumbo_rx_tag = NULL; 2551 } 2552 } 2553 2554 static int 2555 msk_encap(struct msk_if_softc *sc_if, struct mbuf **m_head) 2556 { 2557 struct msk_txdesc *txd, *txd_last; 2558 struct msk_tx_desc *tx_le; 2559 struct mbuf *m; 2560 bus_dmamap_t map; 2561 bus_dma_segment_t txsegs[MSK_MAXTXSEGS]; 2562 uint32_t control, csum, prod, si; 2563 uint16_t offset, tcp_offset, tso_mtu; 2564 int error, i, nseg, tso; 2565 2566 MSK_IF_LOCK_ASSERT(sc_if); 2567 2568 tcp_offset = offset = 0; 2569 m = *m_head; 2570 if (((sc_if->msk_flags & MSK_FLAG_AUTOTX_CSUM) == 0 && 2571 (m->m_pkthdr.csum_flags & MSK_CSUM_FEATURES) != 0) || 2572 ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0 && 2573 (m->m_pkthdr.csum_flags & CSUM_TSO) != 0)) { 2574 /* 2575 * Since mbuf has no protocol specific structure information 2576 * in it we have to inspect protocol information here to 2577 * setup TSO and checksum offload. I don't know why Marvell 2578 * made a such decision in chip design because other GigE 2579 * hardwares normally takes care of all these chores in 2580 * hardware. However, TSO performance of Yukon II is very 2581 * good such that it's worth to implement it. 2582 */ 2583 struct ether_header *eh; 2584 struct ip *ip; 2585 struct tcphdr *tcp; 2586 2587 if (M_WRITABLE(m) == 0) { 2588 /* Get a writable copy. */ 2589 m = m_dup(*m_head, M_DONTWAIT); 2590 m_freem(*m_head); 2591 if (m == NULL) { 2592 *m_head = NULL; 2593 return (ENOBUFS); 2594 } 2595 *m_head = m; 2596 } 2597 2598 offset = sizeof(struct ether_header); 2599 m = m_pullup(m, offset); 2600 if (m == NULL) { 2601 *m_head = NULL; 2602 return (ENOBUFS); 2603 } 2604 eh = mtod(m, struct ether_header *); 2605 /* Check if hardware VLAN insertion is off. */ 2606 if (eh->ether_type == htons(ETHERTYPE_VLAN)) { 2607 offset = sizeof(struct ether_vlan_header); 2608 m = m_pullup(m, offset); 2609 if (m == NULL) { 2610 *m_head = NULL; 2611 return (ENOBUFS); 2612 } 2613 } 2614 m = m_pullup(m, offset + sizeof(struct ip)); 2615 if (m == NULL) { 2616 *m_head = NULL; 2617 return (ENOBUFS); 2618 } 2619 ip = (struct ip *)(mtod(m, char *) + offset); 2620 offset += (ip->ip_hl << 2); 2621 tcp_offset = offset; 2622 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 2623 m = m_pullup(m, offset + sizeof(struct tcphdr)); 2624 if (m == NULL) { 2625 *m_head = NULL; 2626 return (ENOBUFS); 2627 } 2628 tcp = (struct tcphdr *)(mtod(m, char *) + offset); 2629 offset += (tcp->th_off << 2); 2630 } else if ((sc_if->msk_flags & MSK_FLAG_AUTOTX_CSUM) == 0 && 2631 (m->m_pkthdr.len < MSK_MIN_FRAMELEN) && 2632 (m->m_pkthdr.csum_flags & CSUM_TCP) != 0) { 2633 /* 2634 * It seems that Yukon II has Tx checksum offload bug 2635 * for small TCP packets that's less than 60 bytes in 2636 * size (e.g. TCP window probe packet, pure ACK packet). 2637 * Common work around like padding with zeros to make 2638 * the frame minimum ethernet frame size didn't work at 2639 * all. 2640 * Instead of disabling checksum offload completely we 2641 * resort to S/W checksum routine when we encounter 2642 * short TCP frames. 2643 * Short UDP packets appear to be handled correctly by 2644 * Yukon II. Also I assume this bug does not happen on 2645 * controllers that use newer descriptor format or 2646 * automatic Tx checksum calaulcation. 2647 */ 2648 m = m_pullup(m, offset + sizeof(struct tcphdr)); 2649 if (m == NULL) { 2650 *m_head = NULL; 2651 return (ENOBUFS); 2652 } 2653 *(uint16_t *)(m->m_data + offset + 2654 m->m_pkthdr.csum_data) = in_cksum_skip(m, 2655 m->m_pkthdr.len, offset); 2656 m->m_pkthdr.csum_flags &= ~CSUM_TCP; 2657 } 2658 *m_head = m; 2659 } 2660 2661 prod = sc_if->msk_cdata.msk_tx_prod; 2662 txd = &sc_if->msk_cdata.msk_txdesc[prod]; 2663 txd_last = txd; 2664 map = txd->tx_dmamap; 2665 error = bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_tx_tag, map, 2666 *m_head, txsegs, &nseg, BUS_DMA_NOWAIT); 2667 if (error == EFBIG) { 2668 m = m_collapse(*m_head, M_DONTWAIT, MSK_MAXTXSEGS); 2669 if (m == NULL) { 2670 m_freem(*m_head); 2671 *m_head = NULL; 2672 return (ENOBUFS); 2673 } 2674 *m_head = m; 2675 error = bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_tx_tag, 2676 map, *m_head, txsegs, &nseg, BUS_DMA_NOWAIT); 2677 if (error != 0) { 2678 m_freem(*m_head); 2679 *m_head = NULL; 2680 return (error); 2681 } 2682 } else if (error != 0) 2683 return (error); 2684 if (nseg == 0) { 2685 m_freem(*m_head); 2686 *m_head = NULL; 2687 return (EIO); 2688 } 2689 2690 /* Check number of available descriptors. */ 2691 if (sc_if->msk_cdata.msk_tx_cnt + nseg >= 2692 (MSK_TX_RING_CNT - MSK_RESERVED_TX_DESC_CNT)) { 2693 bus_dmamap_unload(sc_if->msk_cdata.msk_tx_tag, map); 2694 return (ENOBUFS); 2695 } 2696 2697 control = 0; 2698 tso = 0; 2699 tx_le = NULL; 2700 2701 /* Check TSO support. */ 2702 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 2703 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) != 0) 2704 tso_mtu = m->m_pkthdr.tso_segsz; 2705 else 2706 tso_mtu = offset + m->m_pkthdr.tso_segsz; 2707 if (tso_mtu != sc_if->msk_cdata.msk_tso_mtu) { 2708 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2709 tx_le->msk_addr = htole32(tso_mtu); 2710 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) != 0) 2711 tx_le->msk_control = htole32(OP_MSS | HW_OWNER); 2712 else 2713 tx_le->msk_control = 2714 htole32(OP_LRGLEN | HW_OWNER); 2715 sc_if->msk_cdata.msk_tx_cnt++; 2716 MSK_INC(prod, MSK_TX_RING_CNT); 2717 sc_if->msk_cdata.msk_tso_mtu = tso_mtu; 2718 } 2719 tso++; 2720 } 2721 /* Check if we have a VLAN tag to insert. */ 2722 if ((m->m_flags & M_VLANTAG) != 0) { 2723 if (tx_le == NULL) { 2724 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2725 tx_le->msk_addr = htole32(0); 2726 tx_le->msk_control = htole32(OP_VLAN | HW_OWNER | 2727 htons(m->m_pkthdr.ether_vtag)); 2728 sc_if->msk_cdata.msk_tx_cnt++; 2729 MSK_INC(prod, MSK_TX_RING_CNT); 2730 } else { 2731 tx_le->msk_control |= htole32(OP_VLAN | 2732 htons(m->m_pkthdr.ether_vtag)); 2733 } 2734 control |= INS_VLAN; 2735 } 2736 /* Check if we have to handle checksum offload. */ 2737 if (tso == 0 && (m->m_pkthdr.csum_flags & MSK_CSUM_FEATURES) != 0) { 2738 if ((sc_if->msk_flags & MSK_FLAG_AUTOTX_CSUM) != 0) 2739 control |= CALSUM; 2740 else { 2741 control |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM; 2742 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0) 2743 control |= UDPTCP; 2744 /* Checksum write position. */ 2745 csum = (tcp_offset + m->m_pkthdr.csum_data) & 0xffff; 2746 /* Checksum start position. */ 2747 csum |= (uint32_t)tcp_offset << 16; 2748 if (csum != sc_if->msk_cdata.msk_last_csum) { 2749 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2750 tx_le->msk_addr = htole32(csum); 2751 tx_le->msk_control = htole32(1 << 16 | 2752 (OP_TCPLISW | HW_OWNER)); 2753 sc_if->msk_cdata.msk_tx_cnt++; 2754 MSK_INC(prod, MSK_TX_RING_CNT); 2755 sc_if->msk_cdata.msk_last_csum = csum; 2756 } 2757 } 2758 } 2759 2760 si = prod; 2761 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2762 tx_le->msk_addr = htole32(MSK_ADDR_LO(txsegs[0].ds_addr)); 2763 if (tso == 0) 2764 tx_le->msk_control = htole32(txsegs[0].ds_len | control | 2765 OP_PACKET); 2766 else 2767 tx_le->msk_control = htole32(txsegs[0].ds_len | control | 2768 OP_LARGESEND); 2769 sc_if->msk_cdata.msk_tx_cnt++; 2770 MSK_INC(prod, MSK_TX_RING_CNT); 2771 2772 for (i = 1; i < nseg; i++) { 2773 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2774 tx_le->msk_addr = htole32(MSK_ADDR_LO(txsegs[i].ds_addr)); 2775 tx_le->msk_control = htole32(txsegs[i].ds_len | control | 2776 OP_BUFFER | HW_OWNER); 2777 sc_if->msk_cdata.msk_tx_cnt++; 2778 MSK_INC(prod, MSK_TX_RING_CNT); 2779 } 2780 /* Update producer index. */ 2781 sc_if->msk_cdata.msk_tx_prod = prod; 2782 2783 /* Set EOP on the last desciptor. */ 2784 prod = (prod + MSK_TX_RING_CNT - 1) % MSK_TX_RING_CNT; 2785 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2786 tx_le->msk_control |= htole32(EOP); 2787 2788 /* Turn the first descriptor ownership to hardware. */ 2789 tx_le = &sc_if->msk_rdata.msk_tx_ring[si]; 2790 tx_le->msk_control |= htole32(HW_OWNER); 2791 2792 txd = &sc_if->msk_cdata.msk_txdesc[prod]; 2793 map = txd_last->tx_dmamap; 2794 txd_last->tx_dmamap = txd->tx_dmamap; 2795 txd->tx_dmamap = map; 2796 txd->tx_m = m; 2797 2798 /* Sync descriptors. */ 2799 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_tag, map, BUS_DMASYNC_PREWRITE); 2800 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_ring_tag, 2801 sc_if->msk_cdata.msk_tx_ring_map, 2802 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2803 2804 return (0); 2805 } 2806 2807 static void 2808 msk_start(struct ifnet *ifp) 2809 { 2810 struct msk_if_softc *sc_if; 2811 2812 sc_if = ifp->if_softc; 2813 MSK_IF_LOCK(sc_if); 2814 msk_start_locked(ifp); 2815 MSK_IF_UNLOCK(sc_if); 2816 } 2817 2818 static void 2819 msk_start_locked(struct ifnet *ifp) 2820 { 2821 struct msk_if_softc *sc_if; 2822 struct mbuf *m_head; 2823 int enq; 2824 2825 sc_if = ifp->if_softc; 2826 MSK_IF_LOCK_ASSERT(sc_if); 2827 2828 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2829 IFF_DRV_RUNNING || (sc_if->msk_flags & MSK_FLAG_LINK) == 0) 2830 return; 2831 2832 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 2833 sc_if->msk_cdata.msk_tx_cnt < 2834 (MSK_TX_RING_CNT - MSK_RESERVED_TX_DESC_CNT); ) { 2835 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2836 if (m_head == NULL) 2837 break; 2838 /* 2839 * Pack the data into the transmit ring. If we 2840 * don't have room, set the OACTIVE flag and wait 2841 * for the NIC to drain the ring. 2842 */ 2843 if (msk_encap(sc_if, &m_head) != 0) { 2844 if (m_head == NULL) 2845 break; 2846 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2847 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2848 break; 2849 } 2850 2851 enq++; 2852 /* 2853 * If there's a BPF listener, bounce a copy of this frame 2854 * to him. 2855 */ 2856 ETHER_BPF_MTAP(ifp, m_head); 2857 } 2858 2859 if (enq > 0) { 2860 /* Transmit */ 2861 CSR_WRITE_2(sc_if->msk_softc, 2862 Y2_PREF_Q_ADDR(sc_if->msk_txq, PREF_UNIT_PUT_IDX_REG), 2863 sc_if->msk_cdata.msk_tx_prod); 2864 2865 /* Set a timeout in case the chip goes out to lunch. */ 2866 sc_if->msk_watchdog_timer = MSK_TX_TIMEOUT; 2867 } 2868 } 2869 2870 static void 2871 msk_watchdog(struct msk_if_softc *sc_if) 2872 { 2873 struct ifnet *ifp; 2874 2875 MSK_IF_LOCK_ASSERT(sc_if); 2876 2877 if (sc_if->msk_watchdog_timer == 0 || --sc_if->msk_watchdog_timer) 2878 return; 2879 ifp = sc_if->msk_ifp; 2880 if ((sc_if->msk_flags & MSK_FLAG_LINK) == 0) { 2881 if (bootverbose) 2882 if_printf(sc_if->msk_ifp, "watchdog timeout " 2883 "(missed link)\n"); 2884 ifp->if_oerrors++; 2885 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2886 msk_init_locked(sc_if); 2887 return; 2888 } 2889 2890 if_printf(ifp, "watchdog timeout\n"); 2891 ifp->if_oerrors++; 2892 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2893 msk_init_locked(sc_if); 2894 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2895 msk_start_locked(ifp); 2896 } 2897 2898 static int 2899 mskc_shutdown(device_t dev) 2900 { 2901 struct msk_softc *sc; 2902 int i; 2903 2904 sc = device_get_softc(dev); 2905 MSK_LOCK(sc); 2906 for (i = 0; i < sc->msk_num_port; i++) { 2907 if (sc->msk_if[i] != NULL) 2908 msk_stop(sc->msk_if[i]); 2909 } 2910 2911 /* Disable all interrupts. */ 2912 CSR_WRITE_4(sc, B0_IMSK, 0); 2913 CSR_READ_4(sc, B0_IMSK); 2914 CSR_WRITE_4(sc, B0_HWE_IMSK, 0); 2915 CSR_READ_4(sc, B0_HWE_IMSK); 2916 2917 /* Put hardware reset. */ 2918 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); 2919 2920 MSK_UNLOCK(sc); 2921 return (0); 2922 } 2923 2924 static int 2925 mskc_suspend(device_t dev) 2926 { 2927 struct msk_softc *sc; 2928 int i; 2929 2930 sc = device_get_softc(dev); 2931 2932 MSK_LOCK(sc); 2933 2934 for (i = 0; i < sc->msk_num_port; i++) { 2935 if (sc->msk_if[i] != NULL && sc->msk_if[i]->msk_ifp != NULL && 2936 ((sc->msk_if[i]->msk_ifp->if_drv_flags & 2937 IFF_DRV_RUNNING) != 0)) 2938 msk_stop(sc->msk_if[i]); 2939 } 2940 2941 /* Disable all interrupts. */ 2942 CSR_WRITE_4(sc, B0_IMSK, 0); 2943 CSR_READ_4(sc, B0_IMSK); 2944 CSR_WRITE_4(sc, B0_HWE_IMSK, 0); 2945 CSR_READ_4(sc, B0_HWE_IMSK); 2946 2947 msk_phy_power(sc, MSK_PHY_POWERDOWN); 2948 2949 /* Put hardware reset. */ 2950 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); 2951 sc->msk_pflags |= MSK_FLAG_SUSPEND; 2952 2953 MSK_UNLOCK(sc); 2954 2955 return (0); 2956 } 2957 2958 static int 2959 mskc_resume(device_t dev) 2960 { 2961 struct msk_softc *sc; 2962 int i; 2963 2964 sc = device_get_softc(dev); 2965 2966 MSK_LOCK(sc); 2967 2968 mskc_reset(sc); 2969 for (i = 0; i < sc->msk_num_port; i++) { 2970 if (sc->msk_if[i] != NULL && sc->msk_if[i]->msk_ifp != NULL && 2971 ((sc->msk_if[i]->msk_ifp->if_flags & IFF_UP) != 0)) { 2972 sc->msk_if[i]->msk_ifp->if_drv_flags &= 2973 ~IFF_DRV_RUNNING; 2974 msk_init_locked(sc->msk_if[i]); 2975 } 2976 } 2977 sc->msk_pflags &= ~MSK_FLAG_SUSPEND; 2978 2979 MSK_UNLOCK(sc); 2980 2981 return (0); 2982 } 2983 2984 #ifndef __NO_STRICT_ALIGNMENT 2985 static __inline void 2986 msk_fixup_rx(struct mbuf *m) 2987 { 2988 int i; 2989 uint16_t *src, *dst; 2990 2991 src = mtod(m, uint16_t *); 2992 dst = src - 3; 2993 2994 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 2995 *dst++ = *src++; 2996 2997 m->m_data -= (MSK_RX_BUF_ALIGN - ETHER_ALIGN); 2998 } 2999 #endif 3000 3001 static __inline void 3002 msk_rxcsum(struct msk_if_softc *sc_if, uint32_t control, struct mbuf *m) 3003 { 3004 struct ether_header *eh; 3005 struct ip *ip; 3006 struct udphdr *uh; 3007 int32_t hlen, len, pktlen, temp32; 3008 uint16_t csum, *opts; 3009 3010 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) != 0) { 3011 if ((control & (CSS_IPV4 | CSS_IPFRAG)) == CSS_IPV4) { 3012 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 3013 if ((control & CSS_IPV4_CSUM_OK) != 0) 3014 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 3015 if ((control & (CSS_TCP | CSS_UDP)) != 0 && 3016 (control & (CSS_TCPUDP_CSUM_OK)) != 0) { 3017 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID | 3018 CSUM_PSEUDO_HDR; 3019 m->m_pkthdr.csum_data = 0xffff; 3020 } 3021 } 3022 return; 3023 } 3024 /* 3025 * Marvell Yukon controllers that support OP_RXCHKS has known 3026 * to have various Rx checksum offloading bugs. These 3027 * controllers can be configured to compute simple checksum 3028 * at two different positions. So we can compute IP and TCP/UDP 3029 * checksum at the same time. We intentionally have controller 3030 * compute TCP/UDP checksum twice by specifying the same 3031 * checksum start position and compare the result. If the value 3032 * is different it would indicate the hardware logic was wrong. 3033 */ 3034 if ((sc_if->msk_csum & 0xFFFF) != (sc_if->msk_csum >> 16)) { 3035 if (bootverbose) 3036 device_printf(sc_if->msk_if_dev, 3037 "Rx checksum value mismatch!\n"); 3038 return; 3039 } 3040 pktlen = m->m_pkthdr.len; 3041 if (pktlen < sizeof(struct ether_header) + sizeof(struct ip)) 3042 return; 3043 eh = mtod(m, struct ether_header *); 3044 if (eh->ether_type != htons(ETHERTYPE_IP)) 3045 return; 3046 ip = (struct ip *)(eh + 1); 3047 if (ip->ip_v != IPVERSION) 3048 return; 3049 3050 hlen = ip->ip_hl << 2; 3051 pktlen -= sizeof(struct ether_header); 3052 if (hlen < sizeof(struct ip)) 3053 return; 3054 if (ntohs(ip->ip_len) < hlen) 3055 return; 3056 if (ntohs(ip->ip_len) != pktlen) 3057 return; 3058 if (ip->ip_off & htons(IP_MF | IP_OFFMASK)) 3059 return; /* can't handle fragmented packet. */ 3060 3061 switch (ip->ip_p) { 3062 case IPPROTO_TCP: 3063 if (pktlen < (hlen + sizeof(struct tcphdr))) 3064 return; 3065 break; 3066 case IPPROTO_UDP: 3067 if (pktlen < (hlen + sizeof(struct udphdr))) 3068 return; 3069 uh = (struct udphdr *)((caddr_t)ip + hlen); 3070 if (uh->uh_sum == 0) 3071 return; /* no checksum */ 3072 break; 3073 default: 3074 return; 3075 } 3076 csum = ntohs(sc_if->msk_csum & 0xFFFF); 3077 /* Checksum fixup for IP options. */ 3078 len = hlen - sizeof(struct ip); 3079 if (len > 0) { 3080 opts = (uint16_t *)(ip + 1); 3081 for (; len > 0; len -= sizeof(uint16_t), opts++) { 3082 temp32 = csum - *opts; 3083 temp32 = (temp32 >> 16) + (temp32 & 65535); 3084 csum = temp32 & 65535; 3085 } 3086 } 3087 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID; 3088 m->m_pkthdr.csum_data = csum; 3089 } 3090 3091 static void 3092 msk_rxeof(struct msk_if_softc *sc_if, uint32_t status, uint32_t control, 3093 int len) 3094 { 3095 struct mbuf *m; 3096 struct ifnet *ifp; 3097 struct msk_rxdesc *rxd; 3098 int cons, rxlen; 3099 3100 ifp = sc_if->msk_ifp; 3101 3102 MSK_IF_LOCK_ASSERT(sc_if); 3103 3104 cons = sc_if->msk_cdata.msk_rx_cons; 3105 do { 3106 rxlen = status >> 16; 3107 if ((status & GMR_FS_VLAN) != 0 && 3108 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 3109 rxlen -= ETHER_VLAN_ENCAP_LEN; 3110 if ((sc_if->msk_flags & MSK_FLAG_NORXCHK) != 0) { 3111 /* 3112 * For controllers that returns bogus status code 3113 * just do minimal check and let upper stack 3114 * handle this frame. 3115 */ 3116 if (len > MSK_MAX_FRAMELEN || len < ETHER_HDR_LEN) { 3117 ifp->if_ierrors++; 3118 msk_discard_rxbuf(sc_if, cons); 3119 break; 3120 } 3121 } else if (len > sc_if->msk_framesize || 3122 ((status & GMR_FS_ANY_ERR) != 0) || 3123 ((status & GMR_FS_RX_OK) == 0) || (rxlen != len)) { 3124 /* Don't count flow-control packet as errors. */ 3125 if ((status & GMR_FS_GOOD_FC) == 0) 3126 ifp->if_ierrors++; 3127 msk_discard_rxbuf(sc_if, cons); 3128 break; 3129 } 3130 rxd = &sc_if->msk_cdata.msk_rxdesc[cons]; 3131 m = rxd->rx_m; 3132 if (msk_newbuf(sc_if, cons) != 0) { 3133 ifp->if_iqdrops++; 3134 /* Reuse old buffer. */ 3135 msk_discard_rxbuf(sc_if, cons); 3136 break; 3137 } 3138 m->m_pkthdr.rcvif = ifp; 3139 m->m_pkthdr.len = m->m_len = len; 3140 #ifndef __NO_STRICT_ALIGNMENT 3141 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) != 0) 3142 msk_fixup_rx(m); 3143 #endif 3144 ifp->if_ipackets++; 3145 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 3146 msk_rxcsum(sc_if, control, m); 3147 /* Check for VLAN tagged packets. */ 3148 if ((status & GMR_FS_VLAN) != 0 && 3149 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) { 3150 m->m_pkthdr.ether_vtag = sc_if->msk_vtag; 3151 m->m_flags |= M_VLANTAG; 3152 } 3153 MSK_IF_UNLOCK(sc_if); 3154 (*ifp->if_input)(ifp, m); 3155 MSK_IF_LOCK(sc_if); 3156 } while (0); 3157 3158 MSK_INC(sc_if->msk_cdata.msk_rx_cons, MSK_RX_RING_CNT); 3159 MSK_INC(sc_if->msk_cdata.msk_rx_prod, MSK_RX_RING_CNT); 3160 } 3161 3162 static void 3163 msk_jumbo_rxeof(struct msk_if_softc *sc_if, uint32_t status, uint32_t control, 3164 int len) 3165 { 3166 struct mbuf *m; 3167 struct ifnet *ifp; 3168 struct msk_rxdesc *jrxd; 3169 int cons, rxlen; 3170 3171 ifp = sc_if->msk_ifp; 3172 3173 MSK_IF_LOCK_ASSERT(sc_if); 3174 3175 cons = sc_if->msk_cdata.msk_rx_cons; 3176 do { 3177 rxlen = status >> 16; 3178 if ((status & GMR_FS_VLAN) != 0 && 3179 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 3180 rxlen -= ETHER_VLAN_ENCAP_LEN; 3181 if (len > sc_if->msk_framesize || 3182 ((status & GMR_FS_ANY_ERR) != 0) || 3183 ((status & GMR_FS_RX_OK) == 0) || (rxlen != len)) { 3184 /* Don't count flow-control packet as errors. */ 3185 if ((status & GMR_FS_GOOD_FC) == 0) 3186 ifp->if_ierrors++; 3187 msk_discard_jumbo_rxbuf(sc_if, cons); 3188 break; 3189 } 3190 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[cons]; 3191 m = jrxd->rx_m; 3192 if (msk_jumbo_newbuf(sc_if, cons) != 0) { 3193 ifp->if_iqdrops++; 3194 /* Reuse old buffer. */ 3195 msk_discard_jumbo_rxbuf(sc_if, cons); 3196 break; 3197 } 3198 m->m_pkthdr.rcvif = ifp; 3199 m->m_pkthdr.len = m->m_len = len; 3200 #ifndef __NO_STRICT_ALIGNMENT 3201 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) != 0) 3202 msk_fixup_rx(m); 3203 #endif 3204 ifp->if_ipackets++; 3205 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 3206 msk_rxcsum(sc_if, control, m); 3207 /* Check for VLAN tagged packets. */ 3208 if ((status & GMR_FS_VLAN) != 0 && 3209 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) { 3210 m->m_pkthdr.ether_vtag = sc_if->msk_vtag; 3211 m->m_flags |= M_VLANTAG; 3212 } 3213 MSK_IF_UNLOCK(sc_if); 3214 (*ifp->if_input)(ifp, m); 3215 MSK_IF_LOCK(sc_if); 3216 } while (0); 3217 3218 MSK_INC(sc_if->msk_cdata.msk_rx_cons, MSK_JUMBO_RX_RING_CNT); 3219 MSK_INC(sc_if->msk_cdata.msk_rx_prod, MSK_JUMBO_RX_RING_CNT); 3220 } 3221 3222 static void 3223 msk_txeof(struct msk_if_softc *sc_if, int idx) 3224 { 3225 struct msk_txdesc *txd; 3226 struct msk_tx_desc *cur_tx; 3227 struct ifnet *ifp; 3228 uint32_t control; 3229 int cons, prog; 3230 3231 MSK_IF_LOCK_ASSERT(sc_if); 3232 3233 ifp = sc_if->msk_ifp; 3234 3235 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_ring_tag, 3236 sc_if->msk_cdata.msk_tx_ring_map, 3237 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3238 /* 3239 * Go through our tx ring and free mbufs for those 3240 * frames that have been sent. 3241 */ 3242 cons = sc_if->msk_cdata.msk_tx_cons; 3243 prog = 0; 3244 for (; cons != idx; MSK_INC(cons, MSK_TX_RING_CNT)) { 3245 if (sc_if->msk_cdata.msk_tx_cnt <= 0) 3246 break; 3247 prog++; 3248 cur_tx = &sc_if->msk_rdata.msk_tx_ring[cons]; 3249 control = le32toh(cur_tx->msk_control); 3250 sc_if->msk_cdata.msk_tx_cnt--; 3251 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3252 if ((control & EOP) == 0) 3253 continue; 3254 txd = &sc_if->msk_cdata.msk_txdesc[cons]; 3255 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_tag, txd->tx_dmamap, 3256 BUS_DMASYNC_POSTWRITE); 3257 bus_dmamap_unload(sc_if->msk_cdata.msk_tx_tag, txd->tx_dmamap); 3258 3259 ifp->if_opackets++; 3260 KASSERT(txd->tx_m != NULL, ("%s: freeing NULL mbuf!", 3261 __func__)); 3262 m_freem(txd->tx_m); 3263 txd->tx_m = NULL; 3264 } 3265 3266 if (prog > 0) { 3267 sc_if->msk_cdata.msk_tx_cons = cons; 3268 if (sc_if->msk_cdata.msk_tx_cnt == 0) 3269 sc_if->msk_watchdog_timer = 0; 3270 /* No need to sync LEs as we didn't update LEs. */ 3271 } 3272 } 3273 3274 static void 3275 msk_tick(void *xsc_if) 3276 { 3277 struct msk_if_softc *sc_if; 3278 struct mii_data *mii; 3279 3280 sc_if = xsc_if; 3281 3282 MSK_IF_LOCK_ASSERT(sc_if); 3283 3284 mii = device_get_softc(sc_if->msk_miibus); 3285 3286 mii_tick(mii); 3287 if ((sc_if->msk_flags & MSK_FLAG_LINK) == 0) 3288 msk_miibus_statchg(sc_if->msk_if_dev); 3289 msk_handle_events(sc_if->msk_softc); 3290 msk_watchdog(sc_if); 3291 callout_reset(&sc_if->msk_tick_ch, hz, msk_tick, sc_if); 3292 } 3293 3294 static void 3295 msk_intr_phy(struct msk_if_softc *sc_if) 3296 { 3297 uint16_t status; 3298 3299 msk_phy_readreg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_STAT); 3300 status = msk_phy_readreg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_STAT); 3301 /* Handle FIFO Underrun/Overflow? */ 3302 if ((status & PHY_M_IS_FIFO_ERROR)) 3303 device_printf(sc_if->msk_if_dev, 3304 "PHY FIFO underrun/overflow.\n"); 3305 } 3306 3307 static void 3308 msk_intr_gmac(struct msk_if_softc *sc_if) 3309 { 3310 struct msk_softc *sc; 3311 uint8_t status; 3312 3313 sc = sc_if->msk_softc; 3314 status = CSR_READ_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_SRC)); 3315 3316 /* GMAC Rx FIFO overrun. */ 3317 if ((status & GM_IS_RX_FF_OR) != 0) 3318 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), 3319 GMF_CLI_RX_FO); 3320 /* GMAC Tx FIFO underrun. */ 3321 if ((status & GM_IS_TX_FF_UR) != 0) { 3322 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 3323 GMF_CLI_TX_FU); 3324 device_printf(sc_if->msk_if_dev, "Tx FIFO underrun!\n"); 3325 /* 3326 * XXX 3327 * In case of Tx underrun, we may need to flush/reset 3328 * Tx MAC but that would also require resynchronization 3329 * with status LEs. Reintializing status LEs would 3330 * affect other port in dual MAC configuration so it 3331 * should be avoided as possible as we can. 3332 * Due to lack of documentation it's all vague guess but 3333 * it needs more investigation. 3334 */ 3335 } 3336 } 3337 3338 static void 3339 msk_handle_hwerr(struct msk_if_softc *sc_if, uint32_t status) 3340 { 3341 struct msk_softc *sc; 3342 3343 sc = sc_if->msk_softc; 3344 if ((status & Y2_IS_PAR_RD1) != 0) { 3345 device_printf(sc_if->msk_if_dev, 3346 "RAM buffer read parity error\n"); 3347 /* Clear IRQ. */ 3348 CSR_WRITE_2(sc, SELECT_RAM_BUFFER(sc_if->msk_port, B3_RI_CTRL), 3349 RI_CLR_RD_PERR); 3350 } 3351 if ((status & Y2_IS_PAR_WR1) != 0) { 3352 device_printf(sc_if->msk_if_dev, 3353 "RAM buffer write parity error\n"); 3354 /* Clear IRQ. */ 3355 CSR_WRITE_2(sc, SELECT_RAM_BUFFER(sc_if->msk_port, B3_RI_CTRL), 3356 RI_CLR_WR_PERR); 3357 } 3358 if ((status & Y2_IS_PAR_MAC1) != 0) { 3359 device_printf(sc_if->msk_if_dev, "Tx MAC parity error\n"); 3360 /* Clear IRQ. */ 3361 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 3362 GMF_CLI_TX_PE); 3363 } 3364 if ((status & Y2_IS_PAR_RX1) != 0) { 3365 device_printf(sc_if->msk_if_dev, "Rx parity error\n"); 3366 /* Clear IRQ. */ 3367 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_CLR_IRQ_PAR); 3368 } 3369 if ((status & (Y2_IS_TCP_TXS1 | Y2_IS_TCP_TXA1)) != 0) { 3370 device_printf(sc_if->msk_if_dev, "TCP segmentation error\n"); 3371 /* Clear IRQ. */ 3372 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_CLR_IRQ_TCP); 3373 } 3374 } 3375 3376 static void 3377 msk_intr_hwerr(struct msk_softc *sc) 3378 { 3379 uint32_t status; 3380 uint32_t tlphead[4]; 3381 3382 status = CSR_READ_4(sc, B0_HWE_ISRC); 3383 /* Time Stamp timer overflow. */ 3384 if ((status & Y2_IS_TIST_OV) != 0) 3385 CSR_WRITE_1(sc, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ); 3386 if ((status & Y2_IS_PCI_NEXP) != 0) { 3387 /* 3388 * PCI Express Error occured which is not described in PEX 3389 * spec. 3390 * This error is also mapped either to Master Abort( 3391 * Y2_IS_MST_ERR) or Target Abort (Y2_IS_IRQ_STAT) bit and 3392 * can only be cleared there. 3393 */ 3394 device_printf(sc->msk_dev, 3395 "PCI Express protocol violation error\n"); 3396 } 3397 3398 if ((status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) != 0) { 3399 uint16_t v16; 3400 3401 if ((status & Y2_IS_MST_ERR) != 0) 3402 device_printf(sc->msk_dev, 3403 "unexpected IRQ Status error\n"); 3404 else 3405 device_printf(sc->msk_dev, 3406 "unexpected IRQ Master error\n"); 3407 /* Reset all bits in the PCI status register. */ 3408 v16 = pci_read_config(sc->msk_dev, PCIR_STATUS, 2); 3409 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON); 3410 pci_write_config(sc->msk_dev, PCIR_STATUS, v16 | 3411 PCIM_STATUS_PERR | PCIM_STATUS_SERR | PCIM_STATUS_RMABORT | 3412 PCIM_STATUS_RTABORT | PCIM_STATUS_PERRREPORT, 2); 3413 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 3414 } 3415 3416 /* Check for PCI Express Uncorrectable Error. */ 3417 if ((status & Y2_IS_PCI_EXP) != 0) { 3418 uint32_t v32; 3419 3420 /* 3421 * On PCI Express bus bridges are called root complexes (RC). 3422 * PCI Express errors are recognized by the root complex too, 3423 * which requests the system to handle the problem. After 3424 * error occurence it may be that no access to the adapter 3425 * may be performed any longer. 3426 */ 3427 3428 v32 = CSR_PCI_READ_4(sc, PEX_UNC_ERR_STAT); 3429 if ((v32 & PEX_UNSUP_REQ) != 0) { 3430 /* Ignore unsupported request error. */ 3431 device_printf(sc->msk_dev, 3432 "Uncorrectable PCI Express error\n"); 3433 } 3434 if ((v32 & (PEX_FATAL_ERRORS | PEX_POIS_TLP)) != 0) { 3435 int i; 3436 3437 /* Get TLP header form Log Registers. */ 3438 for (i = 0; i < 4; i++) 3439 tlphead[i] = CSR_PCI_READ_4(sc, 3440 PEX_HEADER_LOG + i * 4); 3441 /* Check for vendor defined broadcast message. */ 3442 if (!(tlphead[0] == 0x73004001 && tlphead[1] == 0x7f)) { 3443 sc->msk_intrhwemask &= ~Y2_IS_PCI_EXP; 3444 CSR_WRITE_4(sc, B0_HWE_IMSK, 3445 sc->msk_intrhwemask); 3446 CSR_READ_4(sc, B0_HWE_IMSK); 3447 } 3448 } 3449 /* Clear the interrupt. */ 3450 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON); 3451 CSR_PCI_WRITE_4(sc, PEX_UNC_ERR_STAT, 0xffffffff); 3452 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 3453 } 3454 3455 if ((status & Y2_HWE_L1_MASK) != 0 && sc->msk_if[MSK_PORT_A] != NULL) 3456 msk_handle_hwerr(sc->msk_if[MSK_PORT_A], status); 3457 if ((status & Y2_HWE_L2_MASK) != 0 && sc->msk_if[MSK_PORT_B] != NULL) 3458 msk_handle_hwerr(sc->msk_if[MSK_PORT_B], status >> 8); 3459 } 3460 3461 static __inline void 3462 msk_rxput(struct msk_if_softc *sc_if) 3463 { 3464 struct msk_softc *sc; 3465 3466 sc = sc_if->msk_softc; 3467 if (sc_if->msk_framesize > (MCLBYTES - MSK_RX_BUF_ALIGN)) 3468 bus_dmamap_sync( 3469 sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 3470 sc_if->msk_cdata.msk_jumbo_rx_ring_map, 3471 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3472 else 3473 bus_dmamap_sync( 3474 sc_if->msk_cdata.msk_rx_ring_tag, 3475 sc_if->msk_cdata.msk_rx_ring_map, 3476 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3477 CSR_WRITE_2(sc, Y2_PREF_Q_ADDR(sc_if->msk_rxq, 3478 PREF_UNIT_PUT_IDX_REG), sc_if->msk_cdata.msk_rx_prod); 3479 } 3480 3481 static int 3482 msk_handle_events(struct msk_softc *sc) 3483 { 3484 struct msk_if_softc *sc_if; 3485 int rxput[2]; 3486 struct msk_stat_desc *sd; 3487 uint32_t control, status; 3488 int cons, len, port, rxprog; 3489 3490 if (sc->msk_stat_cons == CSR_READ_2(sc, STAT_PUT_IDX)) 3491 return (0); 3492 3493 /* Sync status LEs. */ 3494 bus_dmamap_sync(sc->msk_stat_tag, sc->msk_stat_map, 3495 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3496 3497 rxput[MSK_PORT_A] = rxput[MSK_PORT_B] = 0; 3498 rxprog = 0; 3499 cons = sc->msk_stat_cons; 3500 for (;;) { 3501 sd = &sc->msk_stat_ring[cons]; 3502 control = le32toh(sd->msk_control); 3503 if ((control & HW_OWNER) == 0) 3504 break; 3505 control &= ~HW_OWNER; 3506 sd->msk_control = htole32(control); 3507 status = le32toh(sd->msk_status); 3508 len = control & STLE_LEN_MASK; 3509 port = (control >> 16) & 0x01; 3510 sc_if = sc->msk_if[port]; 3511 if (sc_if == NULL) { 3512 device_printf(sc->msk_dev, "invalid port opcode " 3513 "0x%08x\n", control & STLE_OP_MASK); 3514 continue; 3515 } 3516 3517 switch (control & STLE_OP_MASK) { 3518 case OP_RXVLAN: 3519 sc_if->msk_vtag = ntohs(len); 3520 break; 3521 case OP_RXCHKSVLAN: 3522 sc_if->msk_vtag = ntohs(len); 3523 /* FALLTHROUGH */ 3524 case OP_RXCHKS: 3525 sc_if->msk_csum = status; 3526 break; 3527 case OP_RXSTAT: 3528 if (sc_if->msk_framesize > 3529 (MCLBYTES - MSK_RX_BUF_ALIGN)) 3530 msk_jumbo_rxeof(sc_if, status, control, len); 3531 else 3532 msk_rxeof(sc_if, status, control, len); 3533 rxprog++; 3534 /* 3535 * Because there is no way to sync single Rx LE 3536 * put the DMA sync operation off until the end of 3537 * event processing. 3538 */ 3539 rxput[port]++; 3540 /* Update prefetch unit if we've passed water mark. */ 3541 if (rxput[port] >= sc_if->msk_cdata.msk_rx_putwm) { 3542 msk_rxput(sc_if); 3543 rxput[port] = 0; 3544 } 3545 break; 3546 case OP_TXINDEXLE: 3547 if (sc->msk_if[MSK_PORT_A] != NULL) 3548 msk_txeof(sc->msk_if[MSK_PORT_A], 3549 status & STLE_TXA1_MSKL); 3550 if (sc->msk_if[MSK_PORT_B] != NULL) 3551 msk_txeof(sc->msk_if[MSK_PORT_B], 3552 ((status & STLE_TXA2_MSKL) >> 3553 STLE_TXA2_SHIFTL) | 3554 ((len & STLE_TXA2_MSKH) << 3555 STLE_TXA2_SHIFTH)); 3556 break; 3557 default: 3558 device_printf(sc->msk_dev, "unhandled opcode 0x%08x\n", 3559 control & STLE_OP_MASK); 3560 break; 3561 } 3562 MSK_INC(cons, MSK_STAT_RING_CNT); 3563 if (rxprog > sc->msk_process_limit) 3564 break; 3565 } 3566 3567 sc->msk_stat_cons = cons; 3568 bus_dmamap_sync(sc->msk_stat_tag, sc->msk_stat_map, 3569 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3570 3571 if (rxput[MSK_PORT_A] > 0) 3572 msk_rxput(sc->msk_if[MSK_PORT_A]); 3573 if (rxput[MSK_PORT_B] > 0) 3574 msk_rxput(sc->msk_if[MSK_PORT_B]); 3575 3576 return (sc->msk_stat_cons != CSR_READ_2(sc, STAT_PUT_IDX)); 3577 } 3578 3579 static void 3580 msk_intr(void *xsc) 3581 { 3582 struct msk_softc *sc; 3583 struct msk_if_softc *sc_if0, *sc_if1; 3584 struct ifnet *ifp0, *ifp1; 3585 uint32_t status; 3586 int domore; 3587 3588 sc = xsc; 3589 MSK_LOCK(sc); 3590 3591 /* Reading B0_Y2_SP_ISRC2 masks further interrupts. */ 3592 status = CSR_READ_4(sc, B0_Y2_SP_ISRC2); 3593 if (status == 0 || status == 0xffffffff || 3594 (sc->msk_pflags & MSK_FLAG_SUSPEND) != 0 || 3595 (status & sc->msk_intrmask) == 0) { 3596 CSR_WRITE_4(sc, B0_Y2_SP_ICR, 2); 3597 return; 3598 } 3599 3600 sc_if0 = sc->msk_if[MSK_PORT_A]; 3601 sc_if1 = sc->msk_if[MSK_PORT_B]; 3602 ifp0 = ifp1 = NULL; 3603 if (sc_if0 != NULL) 3604 ifp0 = sc_if0->msk_ifp; 3605 if (sc_if1 != NULL) 3606 ifp1 = sc_if1->msk_ifp; 3607 3608 if ((status & Y2_IS_IRQ_PHY1) != 0 && sc_if0 != NULL) 3609 msk_intr_phy(sc_if0); 3610 if ((status & Y2_IS_IRQ_PHY2) != 0 && sc_if1 != NULL) 3611 msk_intr_phy(sc_if1); 3612 if ((status & Y2_IS_IRQ_MAC1) != 0 && sc_if0 != NULL) 3613 msk_intr_gmac(sc_if0); 3614 if ((status & Y2_IS_IRQ_MAC2) != 0 && sc_if1 != NULL) 3615 msk_intr_gmac(sc_if1); 3616 if ((status & (Y2_IS_CHK_RX1 | Y2_IS_CHK_RX2)) != 0) { 3617 device_printf(sc->msk_dev, "Rx descriptor error\n"); 3618 sc->msk_intrmask &= ~(Y2_IS_CHK_RX1 | Y2_IS_CHK_RX2); 3619 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask); 3620 CSR_READ_4(sc, B0_IMSK); 3621 } 3622 if ((status & (Y2_IS_CHK_TXA1 | Y2_IS_CHK_TXA2)) != 0) { 3623 device_printf(sc->msk_dev, "Tx descriptor error\n"); 3624 sc->msk_intrmask &= ~(Y2_IS_CHK_TXA1 | Y2_IS_CHK_TXA2); 3625 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask); 3626 CSR_READ_4(sc, B0_IMSK); 3627 } 3628 if ((status & Y2_IS_HW_ERR) != 0) 3629 msk_intr_hwerr(sc); 3630 3631 domore = msk_handle_events(sc); 3632 if ((status & Y2_IS_STAT_BMU) != 0 && domore == 0) 3633 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_CLR_IRQ); 3634 3635 /* Reenable interrupts. */ 3636 CSR_WRITE_4(sc, B0_Y2_SP_ICR, 2); 3637 3638 if (ifp0 != NULL && (ifp0->if_drv_flags & IFF_DRV_RUNNING) != 0 && 3639 !IFQ_DRV_IS_EMPTY(&ifp0->if_snd)) 3640 msk_start_locked(ifp0); 3641 if (ifp1 != NULL && (ifp1->if_drv_flags & IFF_DRV_RUNNING) != 0 && 3642 !IFQ_DRV_IS_EMPTY(&ifp1->if_snd)) 3643 msk_start_locked(ifp1); 3644 3645 MSK_UNLOCK(sc); 3646 } 3647 3648 static void 3649 msk_set_tx_stfwd(struct msk_if_softc *sc_if) 3650 { 3651 struct msk_softc *sc; 3652 struct ifnet *ifp; 3653 3654 ifp = sc_if->msk_ifp; 3655 sc = sc_if->msk_softc; 3656 switch (sc->msk_hw_id) { 3657 case CHIP_ID_YUKON_EX: 3658 if (sc->msk_hw_rev == CHIP_REV_YU_EX_A0) 3659 goto yukon_ex_workaround; 3660 if (ifp->if_mtu > ETHERMTU) 3661 CSR_WRITE_4(sc, 3662 MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 3663 TX_JUMBO_ENA | TX_STFW_ENA); 3664 else 3665 CSR_WRITE_4(sc, 3666 MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 3667 TX_JUMBO_DIS | TX_STFW_ENA); 3668 break; 3669 default: 3670 yukon_ex_workaround: 3671 if (ifp->if_mtu > ETHERMTU) { 3672 /* Set Tx GMAC FIFO Almost Empty Threshold. */ 3673 CSR_WRITE_4(sc, 3674 MR_ADDR(sc_if->msk_port, TX_GMF_AE_THR), 3675 MSK_ECU_JUMBO_WM << 16 | MSK_ECU_AE_THR); 3676 /* Disable Store & Forward mode for Tx. */ 3677 CSR_WRITE_4(sc, 3678 MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 3679 TX_JUMBO_ENA | TX_STFW_DIS); 3680 } else { 3681 /* Enable Store & Forward mode for Tx. */ 3682 CSR_WRITE_4(sc, 3683 MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 3684 TX_JUMBO_DIS | TX_STFW_ENA); 3685 } 3686 break; 3687 } 3688 } 3689 3690 static void 3691 msk_init(void *xsc) 3692 { 3693 struct msk_if_softc *sc_if = xsc; 3694 3695 MSK_IF_LOCK(sc_if); 3696 msk_init_locked(sc_if); 3697 MSK_IF_UNLOCK(sc_if); 3698 } 3699 3700 static void 3701 msk_init_locked(struct msk_if_softc *sc_if) 3702 { 3703 struct msk_softc *sc; 3704 struct ifnet *ifp; 3705 struct mii_data *mii; 3706 uint8_t *eaddr; 3707 uint16_t gmac; 3708 uint32_t reg; 3709 int error; 3710 3711 MSK_IF_LOCK_ASSERT(sc_if); 3712 3713 ifp = sc_if->msk_ifp; 3714 sc = sc_if->msk_softc; 3715 mii = device_get_softc(sc_if->msk_miibus); 3716 3717 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 3718 return; 3719 3720 error = 0; 3721 /* Cancel pending I/O and free all Rx/Tx buffers. */ 3722 msk_stop(sc_if); 3723 3724 if (ifp->if_mtu < ETHERMTU) 3725 sc_if->msk_framesize = ETHERMTU; 3726 else 3727 sc_if->msk_framesize = ifp->if_mtu; 3728 sc_if->msk_framesize += ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 3729 if (ifp->if_mtu > ETHERMTU && 3730 (sc_if->msk_flags & MSK_FLAG_JUMBO_NOCSUM) != 0) { 3731 ifp->if_hwassist &= ~(MSK_CSUM_FEATURES | CSUM_TSO); 3732 ifp->if_capenable &= ~(IFCAP_TSO4 | IFCAP_TXCSUM); 3733 } 3734 3735 /* GMAC Control reset. */ 3736 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_RST_SET); 3737 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_RST_CLR); 3738 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_F_LOOPB_OFF); 3739 if (sc->msk_hw_id == CHIP_ID_YUKON_EX) 3740 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), 3741 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON | 3742 GMC_BYP_RETR_ON); 3743 3744 /* 3745 * Initialize GMAC first such that speed/duplex/flow-control 3746 * parameters are renegotiated when interface is brought up. 3747 */ 3748 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, 0); 3749 3750 /* Dummy read the Interrupt Source Register. */ 3751 CSR_READ_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_SRC)); 3752 3753 /* Clear MIB stats. */ 3754 msk_stats_clear(sc_if); 3755 3756 /* Disable FCS. */ 3757 GMAC_WRITE_2(sc, sc_if->msk_port, GM_RX_CTRL, GM_RXCR_CRC_DIS); 3758 3759 /* Setup Transmit Control Register. */ 3760 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF)); 3761 3762 /* Setup Transmit Flow Control Register. */ 3763 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_FLOW_CTRL, 0xffff); 3764 3765 /* Setup Transmit Parameter Register. */ 3766 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_PARAM, 3767 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) | TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) | 3768 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) | TX_BACK_OFF_LIM(TX_BOF_LIM_DEF)); 3769 3770 gmac = DATA_BLIND_VAL(DATA_BLIND_DEF) | 3771 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF); 3772 3773 if (ifp->if_mtu > ETHERMTU) 3774 gmac |= GM_SMOD_JUMBO_ENA; 3775 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SERIAL_MODE, gmac); 3776 3777 /* Set station address. */ 3778 eaddr = IF_LLADDR(ifp); 3779 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_1L, 3780 eaddr[0] | (eaddr[1] << 8)); 3781 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_1M, 3782 eaddr[2] | (eaddr[3] << 8)); 3783 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_1H, 3784 eaddr[4] | (eaddr[5] << 8)); 3785 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_2L, 3786 eaddr[0] | (eaddr[1] << 8)); 3787 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_2M, 3788 eaddr[2] | (eaddr[3] << 8)); 3789 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_2H, 3790 eaddr[4] | (eaddr[5] << 8)); 3791 3792 /* Disable interrupts for counter overflows. */ 3793 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_IRQ_MSK, 0); 3794 GMAC_WRITE_2(sc, sc_if->msk_port, GM_RX_IRQ_MSK, 0); 3795 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TR_IRQ_MSK, 0); 3796 3797 /* Configure Rx MAC FIFO. */ 3798 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), GMF_RST_SET); 3799 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), GMF_RST_CLR); 3800 reg = GMF_OPER_ON | GMF_RX_F_FL_ON; 3801 if (sc->msk_hw_id == CHIP_ID_YUKON_FE_P || 3802 sc->msk_hw_id == CHIP_ID_YUKON_EX) 3803 reg |= GMF_RX_OVER_ON; 3804 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), reg); 3805 3806 /* Set receive filter. */ 3807 msk_rxfilter(sc_if); 3808 3809 if (sc->msk_hw_id == CHIP_ID_YUKON_XL) { 3810 /* Clear flush mask - HW bug. */ 3811 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_FL_MSK), 0); 3812 } else { 3813 /* Flush Rx MAC FIFO on any flow control or error. */ 3814 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_FL_MSK), 3815 GMR_FS_ANY_ERR); 3816 } 3817 3818 /* 3819 * Set Rx FIFO flush threshold to 64 bytes + 1 FIFO word 3820 * due to hardware hang on receipt of pause frames. 3821 */ 3822 reg = RX_GMF_FL_THR_DEF + 1; 3823 /* Another magic for Yukon FE+ - From Linux. */ 3824 if (sc->msk_hw_id == CHIP_ID_YUKON_FE_P && 3825 sc->msk_hw_rev == CHIP_REV_YU_FE_P_A0) 3826 reg = 0x178; 3827 CSR_WRITE_2(sc, MR_ADDR(sc_if->msk_port, RX_GMF_FL_THR), reg); 3828 3829 /* Configure Tx MAC FIFO. */ 3830 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_RST_SET); 3831 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_RST_CLR); 3832 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_OPER_ON); 3833 3834 /* Configure hardware VLAN tag insertion/stripping. */ 3835 msk_setvlan(sc_if, ifp); 3836 3837 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) == 0) { 3838 /* Set Rx Pause threshould. */ 3839 CSR_WRITE_2(sc, MR_ADDR(sc_if->msk_port, RX_GMF_LP_THR), 3840 MSK_ECU_LLPP); 3841 CSR_WRITE_2(sc, MR_ADDR(sc_if->msk_port, RX_GMF_UP_THR), 3842 MSK_ECU_ULPP); 3843 /* Configure store-and-forward for Tx. */ 3844 msk_set_tx_stfwd(sc_if); 3845 } 3846 3847 if (sc->msk_hw_id == CHIP_ID_YUKON_FE_P && 3848 sc->msk_hw_rev == CHIP_REV_YU_FE_P_A0) { 3849 /* Disable dynamic watermark - from Linux. */ 3850 reg = CSR_READ_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_EA)); 3851 reg &= ~0x03; 3852 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_EA), reg); 3853 } 3854 3855 /* 3856 * Disable Force Sync bit and Alloc bit in Tx RAM interface 3857 * arbiter as we don't use Sync Tx queue. 3858 */ 3859 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, TXA_CTRL), 3860 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC); 3861 /* Enable the RAM Interface Arbiter. */ 3862 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, TXA_CTRL), TXA_ENA_ARB); 3863 3864 /* Setup RAM buffer. */ 3865 msk_set_rambuffer(sc_if); 3866 3867 /* Disable Tx sync Queue. */ 3868 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txsq, RB_CTRL), RB_RST_SET); 3869 3870 /* Setup Tx Queue Bus Memory Interface. */ 3871 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_CLR_RESET); 3872 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_OPER_INIT); 3873 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_FIFO_OP_ON); 3874 CSR_WRITE_2(sc, Q_ADDR(sc_if->msk_txq, Q_WM), MSK_BMU_TX_WM); 3875 switch (sc->msk_hw_id) { 3876 case CHIP_ID_YUKON_EC_U: 3877 if (sc->msk_hw_rev == CHIP_REV_YU_EC_U_A0) { 3878 /* Fix for Yukon-EC Ultra: set BMU FIFO level */ 3879 CSR_WRITE_2(sc, Q_ADDR(sc_if->msk_txq, Q_AL), 3880 MSK_ECU_TXFF_LEV); 3881 } 3882 break; 3883 case CHIP_ID_YUKON_EX: 3884 /* 3885 * Yukon Extreme seems to have silicon bug for 3886 * automatic Tx checksum calculation capability. 3887 */ 3888 if (sc->msk_hw_rev == CHIP_REV_YU_EX_B0) 3889 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_F), 3890 F_TX_CHK_AUTO_OFF); 3891 break; 3892 } 3893 3894 /* Setup Rx Queue Bus Memory Interface. */ 3895 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_CLR_RESET); 3896 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_OPER_INIT); 3897 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_FIFO_OP_ON); 3898 CSR_WRITE_2(sc, Q_ADDR(sc_if->msk_rxq, Q_WM), MSK_BMU_RX_WM); 3899 if (sc->msk_hw_id == CHIP_ID_YUKON_EC_U && 3900 sc->msk_hw_rev >= CHIP_REV_YU_EC_U_A1) { 3901 /* MAC Rx RAM Read is controlled by hardware. */ 3902 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_F), F_M_RX_RAM_DIS); 3903 } 3904 3905 msk_set_prefetch(sc, sc_if->msk_txq, 3906 sc_if->msk_rdata.msk_tx_ring_paddr, MSK_TX_RING_CNT - 1); 3907 msk_init_tx_ring(sc_if); 3908 3909 /* Disable Rx checksum offload and RSS hash. */ 3910 reg = BMU_DIS_RX_RSS_HASH; 3911 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0 && 3912 (ifp->if_capenable & IFCAP_RXCSUM) != 0) 3913 reg |= BMU_ENA_RX_CHKSUM; 3914 else 3915 reg |= BMU_DIS_RX_CHKSUM; 3916 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), reg); 3917 if (sc_if->msk_framesize > (MCLBYTES - MSK_RX_BUF_ALIGN)) { 3918 msk_set_prefetch(sc, sc_if->msk_rxq, 3919 sc_if->msk_rdata.msk_jumbo_rx_ring_paddr, 3920 MSK_JUMBO_RX_RING_CNT - 1); 3921 error = msk_init_jumbo_rx_ring(sc_if); 3922 } else { 3923 msk_set_prefetch(sc, sc_if->msk_rxq, 3924 sc_if->msk_rdata.msk_rx_ring_paddr, 3925 MSK_RX_RING_CNT - 1); 3926 error = msk_init_rx_ring(sc_if); 3927 } 3928 if (error != 0) { 3929 device_printf(sc_if->msk_if_dev, 3930 "initialization failed: no memory for Rx buffers\n"); 3931 msk_stop(sc_if); 3932 return; 3933 } 3934 if (sc->msk_hw_id == CHIP_ID_YUKON_EX) { 3935 /* Disable flushing of non-ASF packets. */ 3936 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), 3937 GMF_RX_MACSEC_FLUSH_OFF); 3938 } 3939 3940 /* Configure interrupt handling. */ 3941 if (sc_if->msk_port == MSK_PORT_A) { 3942 sc->msk_intrmask |= Y2_IS_PORT_A; 3943 sc->msk_intrhwemask |= Y2_HWE_L1_MASK; 3944 } else { 3945 sc->msk_intrmask |= Y2_IS_PORT_B; 3946 sc->msk_intrhwemask |= Y2_HWE_L2_MASK; 3947 } 3948 /* Configure IRQ moderation mask. */ 3949 CSR_WRITE_4(sc, B2_IRQM_MSK, sc->msk_intrmask); 3950 if (sc->msk_int_holdoff > 0) { 3951 /* Configure initial IRQ moderation timer value. */ 3952 CSR_WRITE_4(sc, B2_IRQM_INI, 3953 MSK_USECS(sc, sc->msk_int_holdoff)); 3954 CSR_WRITE_4(sc, B2_IRQM_VAL, 3955 MSK_USECS(sc, sc->msk_int_holdoff)); 3956 /* Start IRQ moderation. */ 3957 CSR_WRITE_1(sc, B2_IRQM_CTRL, TIM_START); 3958 } 3959 CSR_WRITE_4(sc, B0_HWE_IMSK, sc->msk_intrhwemask); 3960 CSR_READ_4(sc, B0_HWE_IMSK); 3961 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask); 3962 CSR_READ_4(sc, B0_IMSK); 3963 3964 sc_if->msk_flags &= ~MSK_FLAG_LINK; 3965 mii_mediachg(mii); 3966 3967 ifp->if_drv_flags |= IFF_DRV_RUNNING; 3968 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3969 3970 callout_reset(&sc_if->msk_tick_ch, hz, msk_tick, sc_if); 3971 } 3972 3973 static void 3974 msk_set_rambuffer(struct msk_if_softc *sc_if) 3975 { 3976 struct msk_softc *sc; 3977 int ltpp, utpp; 3978 3979 sc = sc_if->msk_softc; 3980 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) == 0) 3981 return; 3982 3983 /* Setup Rx Queue. */ 3984 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_RST_CLR); 3985 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_START), 3986 sc->msk_rxqstart[sc_if->msk_port] / 8); 3987 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_END), 3988 sc->msk_rxqend[sc_if->msk_port] / 8); 3989 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_WP), 3990 sc->msk_rxqstart[sc_if->msk_port] / 8); 3991 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_RP), 3992 sc->msk_rxqstart[sc_if->msk_port] / 8); 3993 3994 utpp = (sc->msk_rxqend[sc_if->msk_port] + 1 - 3995 sc->msk_rxqstart[sc_if->msk_port] - MSK_RB_ULPP) / 8; 3996 ltpp = (sc->msk_rxqend[sc_if->msk_port] + 1 - 3997 sc->msk_rxqstart[sc_if->msk_port] - MSK_RB_LLPP_B) / 8; 3998 if (sc->msk_rxqsize < MSK_MIN_RXQ_SIZE) 3999 ltpp += (MSK_RB_LLPP_B - MSK_RB_LLPP_S) / 8; 4000 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_RX_UTPP), utpp); 4001 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_RX_LTPP), ltpp); 4002 /* Set Rx priority(RB_RX_UTHP/RB_RX_LTHP) thresholds? */ 4003 4004 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_ENA_OP_MD); 4005 CSR_READ_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL)); 4006 4007 /* Setup Tx Queue. */ 4008 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_RST_CLR); 4009 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_START), 4010 sc->msk_txqstart[sc_if->msk_port] / 8); 4011 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_END), 4012 sc->msk_txqend[sc_if->msk_port] / 8); 4013 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_WP), 4014 sc->msk_txqstart[sc_if->msk_port] / 8); 4015 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_RP), 4016 sc->msk_txqstart[sc_if->msk_port] / 8); 4017 /* Enable Store & Forward for Tx side. */ 4018 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_ENA_STFWD); 4019 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_ENA_OP_MD); 4020 CSR_READ_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL)); 4021 } 4022 4023 static void 4024 msk_set_prefetch(struct msk_softc *sc, int qaddr, bus_addr_t addr, 4025 uint32_t count) 4026 { 4027 4028 /* Reset the prefetch unit. */ 4029 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG), 4030 PREF_UNIT_RST_SET); 4031 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG), 4032 PREF_UNIT_RST_CLR); 4033 /* Set LE base address. */ 4034 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_ADDR_LOW_REG), 4035 MSK_ADDR_LO(addr)); 4036 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_ADDR_HI_REG), 4037 MSK_ADDR_HI(addr)); 4038 /* Set the list last index. */ 4039 CSR_WRITE_2(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_LAST_IDX_REG), 4040 count); 4041 /* Turn on prefetch unit. */ 4042 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG), 4043 PREF_UNIT_OP_ON); 4044 /* Dummy read to ensure write. */ 4045 CSR_READ_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG)); 4046 } 4047 4048 static void 4049 msk_stop(struct msk_if_softc *sc_if) 4050 { 4051 struct msk_softc *sc; 4052 struct msk_txdesc *txd; 4053 struct msk_rxdesc *rxd; 4054 struct msk_rxdesc *jrxd; 4055 struct ifnet *ifp; 4056 uint32_t val; 4057 int i; 4058 4059 MSK_IF_LOCK_ASSERT(sc_if); 4060 sc = sc_if->msk_softc; 4061 ifp = sc_if->msk_ifp; 4062 4063 callout_stop(&sc_if->msk_tick_ch); 4064 sc_if->msk_watchdog_timer = 0; 4065 4066 /* Disable interrupts. */ 4067 if (sc_if->msk_port == MSK_PORT_A) { 4068 sc->msk_intrmask &= ~Y2_IS_PORT_A; 4069 sc->msk_intrhwemask &= ~Y2_HWE_L1_MASK; 4070 } else { 4071 sc->msk_intrmask &= ~Y2_IS_PORT_B; 4072 sc->msk_intrhwemask &= ~Y2_HWE_L2_MASK; 4073 } 4074 CSR_WRITE_4(sc, B0_HWE_IMSK, sc->msk_intrhwemask); 4075 CSR_READ_4(sc, B0_HWE_IMSK); 4076 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask); 4077 CSR_READ_4(sc, B0_IMSK); 4078 4079 /* Disable Tx/Rx MAC. */ 4080 val = GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL); 4081 val &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA); 4082 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, val); 4083 /* Read again to ensure writing. */ 4084 GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL); 4085 /* Update stats and clear counters. */ 4086 msk_stats_update(sc_if); 4087 4088 /* Stop Tx BMU. */ 4089 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_STOP); 4090 val = CSR_READ_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR)); 4091 for (i = 0; i < MSK_TIMEOUT; i++) { 4092 if ((val & (BMU_STOP | BMU_IDLE)) == 0) { 4093 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), 4094 BMU_STOP); 4095 val = CSR_READ_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR)); 4096 } else 4097 break; 4098 DELAY(1); 4099 } 4100 if (i == MSK_TIMEOUT) 4101 device_printf(sc_if->msk_if_dev, "Tx BMU stop failed\n"); 4102 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), 4103 RB_RST_SET | RB_DIS_OP_MD); 4104 4105 /* Disable all GMAC interrupt. */ 4106 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_MSK), 0); 4107 /* Disable PHY interrupt. */ 4108 msk_phy_writereg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_MASK, 0); 4109 4110 /* Disable the RAM Interface Arbiter. */ 4111 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, TXA_CTRL), TXA_DIS_ARB); 4112 4113 /* Reset the PCI FIFO of the async Tx queue */ 4114 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), 4115 BMU_RST_SET | BMU_FIFO_RST); 4116 4117 /* Reset the Tx prefetch units. */ 4118 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(sc_if->msk_txq, PREF_UNIT_CTRL_REG), 4119 PREF_UNIT_RST_SET); 4120 4121 /* Reset the RAM Buffer async Tx queue. */ 4122 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_RST_SET); 4123 4124 /* Reset Tx MAC FIFO. */ 4125 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_RST_SET); 4126 /* Set Pause Off. */ 4127 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_PAUSE_OFF); 4128 4129 /* 4130 * The Rx Stop command will not work for Yukon-2 if the BMU does not 4131 * reach the end of packet and since we can't make sure that we have 4132 * incoming data, we must reset the BMU while it is not during a DMA 4133 * transfer. Since it is possible that the Rx path is still active, 4134 * the Rx RAM buffer will be stopped first, so any possible incoming 4135 * data will not trigger a DMA. After the RAM buffer is stopped, the 4136 * BMU is polled until any DMA in progress is ended and only then it 4137 * will be reset. 4138 */ 4139 4140 /* Disable the RAM Buffer receive queue. */ 4141 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_DIS_OP_MD); 4142 for (i = 0; i < MSK_TIMEOUT; i++) { 4143 if (CSR_READ_1(sc, RB_ADDR(sc_if->msk_rxq, Q_RSL)) == 4144 CSR_READ_1(sc, RB_ADDR(sc_if->msk_rxq, Q_RL))) 4145 break; 4146 DELAY(1); 4147 } 4148 if (i == MSK_TIMEOUT) 4149 device_printf(sc_if->msk_if_dev, "Rx BMU stop failed\n"); 4150 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), 4151 BMU_RST_SET | BMU_FIFO_RST); 4152 /* Reset the Rx prefetch unit. */ 4153 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_CTRL_REG), 4154 PREF_UNIT_RST_SET); 4155 /* Reset the RAM Buffer receive queue. */ 4156 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_RST_SET); 4157 /* Reset Rx MAC FIFO. */ 4158 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), GMF_RST_SET); 4159 4160 /* Free Rx and Tx mbufs still in the queues. */ 4161 for (i = 0; i < MSK_RX_RING_CNT; i++) { 4162 rxd = &sc_if->msk_cdata.msk_rxdesc[i]; 4163 if (rxd->rx_m != NULL) { 4164 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_tag, 4165 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 4166 bus_dmamap_unload(sc_if->msk_cdata.msk_rx_tag, 4167 rxd->rx_dmamap); 4168 m_freem(rxd->rx_m); 4169 rxd->rx_m = NULL; 4170 } 4171 } 4172 for (i = 0; i < MSK_JUMBO_RX_RING_CNT; i++) { 4173 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[i]; 4174 if (jrxd->rx_m != NULL) { 4175 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_tag, 4176 jrxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 4177 bus_dmamap_unload(sc_if->msk_cdata.msk_jumbo_rx_tag, 4178 jrxd->rx_dmamap); 4179 m_freem(jrxd->rx_m); 4180 jrxd->rx_m = NULL; 4181 } 4182 } 4183 for (i = 0; i < MSK_TX_RING_CNT; i++) { 4184 txd = &sc_if->msk_cdata.msk_txdesc[i]; 4185 if (txd->tx_m != NULL) { 4186 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_tag, 4187 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 4188 bus_dmamap_unload(sc_if->msk_cdata.msk_tx_tag, 4189 txd->tx_dmamap); 4190 m_freem(txd->tx_m); 4191 txd->tx_m = NULL; 4192 } 4193 } 4194 4195 /* 4196 * Mark the interface down. 4197 */ 4198 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 4199 sc_if->msk_flags &= ~MSK_FLAG_LINK; 4200 } 4201 4202 /* 4203 * When GM_PAR_MIB_CLR bit of GM_PHY_ADDR is set, reading lower 4204 * counter clears high 16 bits of the counter such that accessing 4205 * lower 16 bits should be the last operation. 4206 */ 4207 #define MSK_READ_MIB32(x, y) \ 4208 (((uint32_t)GMAC_READ_2(sc, x, (y) + 4)) << 16) + \ 4209 (uint32_t)GMAC_READ_2(sc, x, y) 4210 #define MSK_READ_MIB64(x, y) \ 4211 (((uint64_t)MSK_READ_MIB32(x, (y) + 8)) << 32) + \ 4212 (uint64_t)MSK_READ_MIB32(x, y) 4213 4214 static void 4215 msk_stats_clear(struct msk_if_softc *sc_if) 4216 { 4217 struct msk_softc *sc; 4218 uint32_t reg; 4219 uint16_t gmac; 4220 int i; 4221 4222 MSK_IF_LOCK_ASSERT(sc_if); 4223 4224 sc = sc_if->msk_softc; 4225 /* Set MIB Clear Counter Mode. */ 4226 gmac = GMAC_READ_2(sc, sc_if->msk_port, GM_PHY_ADDR); 4227 GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac | GM_PAR_MIB_CLR); 4228 /* Read all MIB Counters with Clear Mode set. */ 4229 for (i = GM_RXF_UC_OK; i <= GM_TXE_FIFO_UR; i += sizeof(uint32_t)) 4230 reg = MSK_READ_MIB32(sc_if->msk_port, i); 4231 /* Clear MIB Clear Counter Mode. */ 4232 gmac &= ~GM_PAR_MIB_CLR; 4233 GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac); 4234 } 4235 4236 static void 4237 msk_stats_update(struct msk_if_softc *sc_if) 4238 { 4239 struct msk_softc *sc; 4240 struct ifnet *ifp; 4241 struct msk_hw_stats *stats; 4242 uint16_t gmac; 4243 uint32_t reg; 4244 4245 MSK_IF_LOCK_ASSERT(sc_if); 4246 4247 ifp = sc_if->msk_ifp; 4248 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 4249 return; 4250 sc = sc_if->msk_softc; 4251 stats = &sc_if->msk_stats; 4252 /* Set MIB Clear Counter Mode. */ 4253 gmac = GMAC_READ_2(sc, sc_if->msk_port, GM_PHY_ADDR); 4254 GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac | GM_PAR_MIB_CLR); 4255 4256 /* Rx stats. */ 4257 stats->rx_ucast_frames += 4258 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_UC_OK); 4259 stats->rx_bcast_frames += 4260 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_BC_OK); 4261 stats->rx_pause_frames += 4262 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_MPAUSE); 4263 stats->rx_mcast_frames += 4264 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_MC_OK); 4265 stats->rx_crc_errs += 4266 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_FCS_ERR); 4267 reg = MSK_READ_MIB32(sc_if->msk_port, GM_RXF_SPARE1); 4268 stats->rx_good_octets += 4269 MSK_READ_MIB64(sc_if->msk_port, GM_RXO_OK_LO); 4270 stats->rx_bad_octets += 4271 MSK_READ_MIB64(sc_if->msk_port, GM_RXO_ERR_LO); 4272 stats->rx_runts += 4273 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_SHT); 4274 stats->rx_runt_errs += 4275 MSK_READ_MIB32(sc_if->msk_port, GM_RXE_FRAG); 4276 stats->rx_pkts_64 += 4277 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_64B); 4278 stats->rx_pkts_65_127 += 4279 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_127B); 4280 stats->rx_pkts_128_255 += 4281 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_255B); 4282 stats->rx_pkts_256_511 += 4283 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_511B); 4284 stats->rx_pkts_512_1023 += 4285 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_1023B); 4286 stats->rx_pkts_1024_1518 += 4287 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_1518B); 4288 stats->rx_pkts_1519_max += 4289 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_MAX_SZ); 4290 stats->rx_pkts_too_long += 4291 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_LNG_ERR); 4292 stats->rx_pkts_jabbers += 4293 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_JAB_PKT); 4294 reg = MSK_READ_MIB32(sc_if->msk_port, GM_RXF_SPARE2); 4295 stats->rx_fifo_oflows += 4296 MSK_READ_MIB32(sc_if->msk_port, GM_RXE_FIFO_OV); 4297 reg = MSK_READ_MIB32(sc_if->msk_port, GM_RXF_SPARE3); 4298 4299 /* Tx stats. */ 4300 stats->tx_ucast_frames += 4301 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_UC_OK); 4302 stats->tx_bcast_frames += 4303 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_BC_OK); 4304 stats->tx_pause_frames += 4305 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_MPAUSE); 4306 stats->tx_mcast_frames += 4307 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_MC_OK); 4308 stats->tx_octets += 4309 MSK_READ_MIB64(sc_if->msk_port, GM_TXO_OK_LO); 4310 stats->tx_pkts_64 += 4311 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_64B); 4312 stats->tx_pkts_65_127 += 4313 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_127B); 4314 stats->tx_pkts_128_255 += 4315 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_255B); 4316 stats->tx_pkts_256_511 += 4317 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_511B); 4318 stats->tx_pkts_512_1023 += 4319 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_1023B); 4320 stats->tx_pkts_1024_1518 += 4321 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_1518B); 4322 stats->tx_pkts_1519_max += 4323 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_MAX_SZ); 4324 reg = MSK_READ_MIB32(sc_if->msk_port, GM_TXF_SPARE1); 4325 stats->tx_colls += 4326 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_COL); 4327 stats->tx_late_colls += 4328 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_LAT_COL); 4329 stats->tx_excess_colls += 4330 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_ABO_COL); 4331 stats->tx_multi_colls += 4332 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_MUL_COL); 4333 stats->tx_single_colls += 4334 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_SNG_COL); 4335 stats->tx_underflows += 4336 MSK_READ_MIB32(sc_if->msk_port, GM_TXE_FIFO_UR); 4337 /* Clear MIB Clear Counter Mode. */ 4338 gmac &= ~GM_PAR_MIB_CLR; 4339 GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac); 4340 } 4341 4342 static int 4343 msk_sysctl_stat32(SYSCTL_HANDLER_ARGS) 4344 { 4345 struct msk_softc *sc; 4346 struct msk_if_softc *sc_if; 4347 uint32_t result, *stat; 4348 int off; 4349 4350 sc_if = (struct msk_if_softc *)arg1; 4351 sc = sc_if->msk_softc; 4352 off = arg2; 4353 stat = (uint32_t *)((uint8_t *)&sc_if->msk_stats + off); 4354 4355 MSK_IF_LOCK(sc_if); 4356 result = MSK_READ_MIB32(sc_if->msk_port, GM_MIB_CNT_BASE + off * 2); 4357 result += *stat; 4358 MSK_IF_UNLOCK(sc_if); 4359 4360 return (sysctl_handle_int(oidp, &result, 0, req)); 4361 } 4362 4363 static int 4364 msk_sysctl_stat64(SYSCTL_HANDLER_ARGS) 4365 { 4366 struct msk_softc *sc; 4367 struct msk_if_softc *sc_if; 4368 uint64_t result, *stat; 4369 int off; 4370 4371 sc_if = (struct msk_if_softc *)arg1; 4372 sc = sc_if->msk_softc; 4373 off = arg2; 4374 stat = (uint64_t *)((uint8_t *)&sc_if->msk_stats + off); 4375 4376 MSK_IF_LOCK(sc_if); 4377 result = MSK_READ_MIB64(sc_if->msk_port, GM_MIB_CNT_BASE + off * 2); 4378 result += *stat; 4379 MSK_IF_UNLOCK(sc_if); 4380 4381 return (sysctl_handle_quad(oidp, &result, 0, req)); 4382 } 4383 4384 #undef MSK_READ_MIB32 4385 #undef MSK_READ_MIB64 4386 4387 #define MSK_SYSCTL_STAT32(sc, c, o, p, n, d) \ 4388 SYSCTL_ADD_PROC(c, p, OID_AUTO, o, CTLTYPE_UINT | CTLFLAG_RD, \ 4389 sc, offsetof(struct msk_hw_stats, n), msk_sysctl_stat32, \ 4390 "IU", d) 4391 #define MSK_SYSCTL_STAT64(sc, c, o, p, n, d) \ 4392 SYSCTL_ADD_PROC(c, p, OID_AUTO, o, CTLTYPE_UINT | CTLFLAG_RD, \ 4393 sc, offsetof(struct msk_hw_stats, n), msk_sysctl_stat64, \ 4394 "Q", d) 4395 4396 static void 4397 msk_sysctl_node(struct msk_if_softc *sc_if) 4398 { 4399 struct sysctl_ctx_list *ctx; 4400 struct sysctl_oid_list *child, *schild; 4401 struct sysctl_oid *tree; 4402 4403 ctx = device_get_sysctl_ctx(sc_if->msk_if_dev); 4404 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc_if->msk_if_dev)); 4405 4406 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD, 4407 NULL, "MSK Statistics"); 4408 schild = child = SYSCTL_CHILDREN(tree); 4409 tree = SYSCTL_ADD_NODE(ctx, schild, OID_AUTO, "rx", CTLFLAG_RD, 4410 NULL, "MSK RX Statistics"); 4411 child = SYSCTL_CHILDREN(tree); 4412 MSK_SYSCTL_STAT32(sc_if, ctx, "ucast_frames", 4413 child, rx_ucast_frames, "Good unicast frames"); 4414 MSK_SYSCTL_STAT32(sc_if, ctx, "bcast_frames", 4415 child, rx_bcast_frames, "Good broadcast frames"); 4416 MSK_SYSCTL_STAT32(sc_if, ctx, "pause_frames", 4417 child, rx_pause_frames, "Pause frames"); 4418 MSK_SYSCTL_STAT32(sc_if, ctx, "mcast_frames", 4419 child, rx_mcast_frames, "Multicast frames"); 4420 MSK_SYSCTL_STAT32(sc_if, ctx, "crc_errs", 4421 child, rx_crc_errs, "CRC errors"); 4422 MSK_SYSCTL_STAT64(sc_if, ctx, "good_octets", 4423 child, rx_good_octets, "Good octets"); 4424 MSK_SYSCTL_STAT64(sc_if, ctx, "bad_octets", 4425 child, rx_bad_octets, "Bad octets"); 4426 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_64", 4427 child, rx_pkts_64, "64 bytes frames"); 4428 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_65_127", 4429 child, rx_pkts_65_127, "65 to 127 bytes frames"); 4430 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_128_255", 4431 child, rx_pkts_128_255, "128 to 255 bytes frames"); 4432 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_256_511", 4433 child, rx_pkts_256_511, "256 to 511 bytes frames"); 4434 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_512_1023", 4435 child, rx_pkts_512_1023, "512 to 1023 bytes frames"); 4436 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_1024_1518", 4437 child, rx_pkts_1024_1518, "1024 to 1518 bytes frames"); 4438 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_1519_max", 4439 child, rx_pkts_1519_max, "1519 to max frames"); 4440 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_too_long", 4441 child, rx_pkts_too_long, "frames too long"); 4442 MSK_SYSCTL_STAT32(sc_if, ctx, "jabbers", 4443 child, rx_pkts_jabbers, "Jabber errors"); 4444 MSK_SYSCTL_STAT32(sc_if, ctx, "overflows", 4445 child, rx_fifo_oflows, "FIFO overflows"); 4446 4447 tree = SYSCTL_ADD_NODE(ctx, schild, OID_AUTO, "tx", CTLFLAG_RD, 4448 NULL, "MSK TX Statistics"); 4449 child = SYSCTL_CHILDREN(tree); 4450 MSK_SYSCTL_STAT32(sc_if, ctx, "ucast_frames", 4451 child, tx_ucast_frames, "Unicast frames"); 4452 MSK_SYSCTL_STAT32(sc_if, ctx, "bcast_frames", 4453 child, tx_bcast_frames, "Broadcast frames"); 4454 MSK_SYSCTL_STAT32(sc_if, ctx, "pause_frames", 4455 child, tx_pause_frames, "Pause frames"); 4456 MSK_SYSCTL_STAT32(sc_if, ctx, "mcast_frames", 4457 child, tx_mcast_frames, "Multicast frames"); 4458 MSK_SYSCTL_STAT64(sc_if, ctx, "octets", 4459 child, tx_octets, "Octets"); 4460 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_64", 4461 child, tx_pkts_64, "64 bytes frames"); 4462 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_65_127", 4463 child, tx_pkts_65_127, "65 to 127 bytes frames"); 4464 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_128_255", 4465 child, tx_pkts_128_255, "128 to 255 bytes frames"); 4466 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_256_511", 4467 child, tx_pkts_256_511, "256 to 511 bytes frames"); 4468 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_512_1023", 4469 child, tx_pkts_512_1023, "512 to 1023 bytes frames"); 4470 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_1024_1518", 4471 child, tx_pkts_1024_1518, "1024 to 1518 bytes frames"); 4472 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_1519_max", 4473 child, tx_pkts_1519_max, "1519 to max frames"); 4474 MSK_SYSCTL_STAT32(sc_if, ctx, "colls", 4475 child, tx_colls, "Collisions"); 4476 MSK_SYSCTL_STAT32(sc_if, ctx, "late_colls", 4477 child, tx_late_colls, "Late collisions"); 4478 MSK_SYSCTL_STAT32(sc_if, ctx, "excess_colls", 4479 child, tx_excess_colls, "Excessive collisions"); 4480 MSK_SYSCTL_STAT32(sc_if, ctx, "multi_colls", 4481 child, tx_multi_colls, "Multiple collisions"); 4482 MSK_SYSCTL_STAT32(sc_if, ctx, "single_colls", 4483 child, tx_single_colls, "Single collisions"); 4484 MSK_SYSCTL_STAT32(sc_if, ctx, "underflows", 4485 child, tx_underflows, "FIFO underflows"); 4486 } 4487 4488 #undef MSK_SYSCTL_STAT32 4489 #undef MSK_SYSCTL_STAT64 4490 4491 static int 4492 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 4493 { 4494 int error, value; 4495 4496 if (!arg1) 4497 return (EINVAL); 4498 value = *(int *)arg1; 4499 error = sysctl_handle_int(oidp, &value, 0, req); 4500 if (error || !req->newptr) 4501 return (error); 4502 if (value < low || value > high) 4503 return (EINVAL); 4504 *(int *)arg1 = value; 4505 4506 return (0); 4507 } 4508 4509 static int 4510 sysctl_hw_msk_proc_limit(SYSCTL_HANDLER_ARGS) 4511 { 4512 4513 return (sysctl_int_range(oidp, arg1, arg2, req, MSK_PROC_MIN, 4514 MSK_PROC_MAX)); 4515 } 4516