1 /****************************************************************************** 2 * 3 * Name : sky2.c 4 * Project: Gigabit Ethernet Driver for FreeBSD 5.x/6.x 5 * Version: $Revision: 1.23 $ 6 * Date : $Date: 2005/12/22 09:04:11 $ 7 * Purpose: Main driver source file 8 * 9 *****************************************************************************/ 10 11 /****************************************************************************** 12 * 13 * LICENSE: 14 * Copyright (C) Marvell International Ltd. and/or its affiliates 15 * 16 * The computer program files contained in this folder ("Files") 17 * are provided to you under the BSD-type license terms provided 18 * below, and any use of such Files and any derivative works 19 * thereof created by you shall be governed by the following terms 20 * and conditions: 21 * 22 * - Redistributions of source code must retain the above copyright 23 * notice, this list of conditions and the following disclaimer. 24 * - Redistributions in binary form must reproduce the above 25 * copyright notice, this list of conditions and the following 26 * disclaimer in the documentation and/or other materials provided 27 * with the distribution. 28 * - Neither the name of Marvell nor the names of its contributors 29 * may be used to endorse or promote products derived from this 30 * software without specific prior written permission. 31 * 32 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 33 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 34 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 35 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 36 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 37 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 38 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 39 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 40 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 41 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 42 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED 43 * OF THE POSSIBILITY OF SUCH DAMAGE. 44 * /LICENSE 45 * 46 *****************************************************************************/ 47 48 /*- 49 * SPDX-License-Identifier: BSD-4-Clause AND BSD-3-Clause 50 * 51 * Copyright (c) 1997, 1998, 1999, 2000 52 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 53 * 54 * Redistribution and use in source and binary forms, with or without 55 * modification, are permitted provided that the following conditions 56 * are met: 57 * 1. Redistributions of source code must retain the above copyright 58 * notice, this list of conditions and the following disclaimer. 59 * 2. Redistributions in binary form must reproduce the above copyright 60 * notice, this list of conditions and the following disclaimer in the 61 * documentation and/or other materials provided with the distribution. 62 * 3. All advertising materials mentioning features or use of this software 63 * must display the following acknowledgement: 64 * This product includes software developed by Bill Paul. 65 * 4. Neither the name of the author nor the names of any co-contributors 66 * may be used to endorse or promote products derived from this software 67 * without specific prior written permission. 68 * 69 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 70 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 71 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 72 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 73 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 74 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 75 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 76 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 77 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 78 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 79 * THE POSSIBILITY OF SUCH DAMAGE. 80 */ 81 /*- 82 * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu> 83 * 84 * Permission to use, copy, modify, and distribute this software for any 85 * purpose with or without fee is hereby granted, provided that the above 86 * copyright notice and this permission notice appear in all copies. 87 * 88 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 89 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 90 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 91 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 92 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 93 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 94 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 95 */ 96 97 /* 98 * Device driver for the Marvell Yukon II Ethernet controller. 99 * Due to lack of documentation, this driver is based on the code from 100 * sk(4) and Marvell's myk(4) driver for FreeBSD 5.x. 101 */ 102 103 #include <sys/param.h> 104 #include <sys/systm.h> 105 #include <sys/bus.h> 106 #include <sys/endian.h> 107 #include <sys/mbuf.h> 108 #include <sys/malloc.h> 109 #include <sys/kernel.h> 110 #include <sys/module.h> 111 #include <sys/socket.h> 112 #include <sys/sockio.h> 113 #include <sys/queue.h> 114 #include <sys/sysctl.h> 115 116 #include <net/bpf.h> 117 #include <net/ethernet.h> 118 #include <net/if.h> 119 #include <net/if_var.h> 120 #include <net/if_arp.h> 121 #include <net/if_dl.h> 122 #include <net/if_media.h> 123 #include <net/if_types.h> 124 #include <net/if_vlan_var.h> 125 126 #include <netinet/in.h> 127 #include <netinet/in_systm.h> 128 #include <netinet/ip.h> 129 #include <netinet/tcp.h> 130 #include <netinet/udp.h> 131 132 #include <machine/bus.h> 133 #include <machine/in_cksum.h> 134 #include <machine/resource.h> 135 #include <sys/rman.h> 136 137 #include <dev/mii/mii.h> 138 #include <dev/mii/miivar.h> 139 140 #include <dev/pci/pcireg.h> 141 #include <dev/pci/pcivar.h> 142 143 #include <dev/msk/if_mskreg.h> 144 145 MODULE_DEPEND(msk, pci, 1, 1, 1); 146 MODULE_DEPEND(msk, ether, 1, 1, 1); 147 MODULE_DEPEND(msk, miibus, 1, 1, 1); 148 149 /* "device miibus" required. See GENERIC if you get errors here. */ 150 #include "miibus_if.h" 151 152 /* Tunables. */ 153 static int msi_disable = 0; 154 TUNABLE_INT("hw.msk.msi_disable", &msi_disable); 155 static int legacy_intr = 0; 156 TUNABLE_INT("hw.msk.legacy_intr", &legacy_intr); 157 static int jumbo_disable = 0; 158 TUNABLE_INT("hw.msk.jumbo_disable", &jumbo_disable); 159 160 #define MSK_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 161 162 /* 163 * Devices supported by this driver. 164 */ 165 static const struct msk_product { 166 uint16_t msk_vendorid; 167 uint16_t msk_deviceid; 168 const char *msk_name; 169 } msk_products[] = { 170 { VENDORID_SK, DEVICEID_SK_YUKON2, 171 "SK-9Sxx Gigabit Ethernet" }, 172 { VENDORID_SK, DEVICEID_SK_YUKON2_EXPR, 173 "SK-9Exx Gigabit Ethernet"}, 174 { VENDORID_MARVELL, DEVICEID_MRVL_8021CU, 175 "Marvell Yukon 88E8021CU Gigabit Ethernet" }, 176 { VENDORID_MARVELL, DEVICEID_MRVL_8021X, 177 "Marvell Yukon 88E8021 SX/LX Gigabit Ethernet" }, 178 { VENDORID_MARVELL, DEVICEID_MRVL_8022CU, 179 "Marvell Yukon 88E8022CU Gigabit Ethernet" }, 180 { VENDORID_MARVELL, DEVICEID_MRVL_8022X, 181 "Marvell Yukon 88E8022 SX/LX Gigabit Ethernet" }, 182 { VENDORID_MARVELL, DEVICEID_MRVL_8061CU, 183 "Marvell Yukon 88E8061CU Gigabit Ethernet" }, 184 { VENDORID_MARVELL, DEVICEID_MRVL_8061X, 185 "Marvell Yukon 88E8061 SX/LX Gigabit Ethernet" }, 186 { VENDORID_MARVELL, DEVICEID_MRVL_8062CU, 187 "Marvell Yukon 88E8062CU Gigabit Ethernet" }, 188 { VENDORID_MARVELL, DEVICEID_MRVL_8062X, 189 "Marvell Yukon 88E8062 SX/LX Gigabit Ethernet" }, 190 { VENDORID_MARVELL, DEVICEID_MRVL_8035, 191 "Marvell Yukon 88E8035 Fast Ethernet" }, 192 { VENDORID_MARVELL, DEVICEID_MRVL_8036, 193 "Marvell Yukon 88E8036 Fast Ethernet" }, 194 { VENDORID_MARVELL, DEVICEID_MRVL_8038, 195 "Marvell Yukon 88E8038 Fast Ethernet" }, 196 { VENDORID_MARVELL, DEVICEID_MRVL_8039, 197 "Marvell Yukon 88E8039 Fast Ethernet" }, 198 { VENDORID_MARVELL, DEVICEID_MRVL_8040, 199 "Marvell Yukon 88E8040 Fast Ethernet" }, 200 { VENDORID_MARVELL, DEVICEID_MRVL_8040T, 201 "Marvell Yukon 88E8040T Fast Ethernet" }, 202 { VENDORID_MARVELL, DEVICEID_MRVL_8042, 203 "Marvell Yukon 88E8042 Fast Ethernet" }, 204 { VENDORID_MARVELL, DEVICEID_MRVL_8048, 205 "Marvell Yukon 88E8048 Fast Ethernet" }, 206 { VENDORID_MARVELL, DEVICEID_MRVL_4361, 207 "Marvell Yukon 88E8050 Gigabit Ethernet" }, 208 { VENDORID_MARVELL, DEVICEID_MRVL_4360, 209 "Marvell Yukon 88E8052 Gigabit Ethernet" }, 210 { VENDORID_MARVELL, DEVICEID_MRVL_4362, 211 "Marvell Yukon 88E8053 Gigabit Ethernet" }, 212 { VENDORID_MARVELL, DEVICEID_MRVL_4363, 213 "Marvell Yukon 88E8055 Gigabit Ethernet" }, 214 { VENDORID_MARVELL, DEVICEID_MRVL_4364, 215 "Marvell Yukon 88E8056 Gigabit Ethernet" }, 216 { VENDORID_MARVELL, DEVICEID_MRVL_4365, 217 "Marvell Yukon 88E8070 Gigabit Ethernet" }, 218 { VENDORID_MARVELL, DEVICEID_MRVL_436A, 219 "Marvell Yukon 88E8058 Gigabit Ethernet" }, 220 { VENDORID_MARVELL, DEVICEID_MRVL_436B, 221 "Marvell Yukon 88E8071 Gigabit Ethernet" }, 222 { VENDORID_MARVELL, DEVICEID_MRVL_436C, 223 "Marvell Yukon 88E8072 Gigabit Ethernet" }, 224 { VENDORID_MARVELL, DEVICEID_MRVL_436D, 225 "Marvell Yukon 88E8055 Gigabit Ethernet" }, 226 { VENDORID_MARVELL, DEVICEID_MRVL_4370, 227 "Marvell Yukon 88E8075 Gigabit Ethernet" }, 228 { VENDORID_MARVELL, DEVICEID_MRVL_4380, 229 "Marvell Yukon 88E8057 Gigabit Ethernet" }, 230 { VENDORID_MARVELL, DEVICEID_MRVL_4381, 231 "Marvell Yukon 88E8059 Gigabit Ethernet" }, 232 { VENDORID_DLINK, DEVICEID_DLINK_DGE550SX, 233 "D-Link 550SX Gigabit Ethernet" }, 234 { VENDORID_DLINK, DEVICEID_DLINK_DGE560SX, 235 "D-Link 560SX Gigabit Ethernet" }, 236 { VENDORID_DLINK, DEVICEID_DLINK_DGE560T, 237 "D-Link 560T Gigabit Ethernet" } 238 }; 239 240 static const char *model_name[] = { 241 "Yukon XL", 242 "Yukon EC Ultra", 243 "Yukon EX", 244 "Yukon EC", 245 "Yukon FE", 246 "Yukon FE+", 247 "Yukon Supreme", 248 "Yukon Ultra 2", 249 "Yukon Unknown", 250 "Yukon Optima", 251 }; 252 253 static int mskc_probe(device_t); 254 static int mskc_attach(device_t); 255 static void mskc_child_deleted(device_t, device_t); 256 static int mskc_detach(device_t); 257 static int mskc_shutdown(device_t); 258 static int mskc_setup_rambuffer(struct msk_softc *); 259 static int mskc_suspend(device_t); 260 static int mskc_resume(device_t); 261 static bus_dma_tag_t mskc_get_dma_tag(device_t, device_t); 262 static void mskc_reset(struct msk_softc *); 263 264 static int msk_probe(device_t); 265 static int msk_attach(device_t); 266 static int msk_detach(device_t); 267 268 static void msk_tick(void *); 269 static void msk_intr(void *); 270 static void msk_intr_phy(struct msk_if_softc *); 271 static void msk_intr_gmac(struct msk_if_softc *); 272 static __inline void msk_rxput(struct msk_if_softc *); 273 static int msk_handle_events(struct msk_softc *); 274 static void msk_handle_hwerr(struct msk_if_softc *, uint32_t); 275 static void msk_intr_hwerr(struct msk_softc *); 276 #ifndef __NO_STRICT_ALIGNMENT 277 static __inline void msk_fixup_rx(struct mbuf *); 278 #endif 279 static __inline void msk_rxcsum(struct msk_if_softc *, uint32_t, struct mbuf *); 280 static void msk_rxeof(struct msk_if_softc *, uint32_t, uint32_t, int); 281 static void msk_jumbo_rxeof(struct msk_if_softc *, uint32_t, uint32_t, int); 282 static void msk_txeof(struct msk_if_softc *, int); 283 static int msk_encap(struct msk_if_softc *, struct mbuf **); 284 static void msk_start(if_t); 285 static void msk_start_locked(if_t); 286 static int msk_ioctl(if_t, u_long, caddr_t); 287 static void msk_set_prefetch(struct msk_softc *, int, bus_addr_t, uint32_t); 288 static void msk_set_rambuffer(struct msk_if_softc *); 289 static void msk_set_tx_stfwd(struct msk_if_softc *); 290 static void msk_init(void *); 291 static void msk_init_locked(struct msk_if_softc *); 292 static void msk_stop(struct msk_if_softc *); 293 static void msk_watchdog(struct msk_if_softc *); 294 static int msk_mediachange(if_t); 295 static void msk_mediastatus(if_t, struct ifmediareq *); 296 static void msk_phy_power(struct msk_softc *, int); 297 static void msk_dmamap_cb(void *, bus_dma_segment_t *, int, int); 298 static int msk_status_dma_alloc(struct msk_softc *); 299 static void msk_status_dma_free(struct msk_softc *); 300 static int msk_txrx_dma_alloc(struct msk_if_softc *); 301 static int msk_rx_dma_jalloc(struct msk_if_softc *); 302 static void msk_txrx_dma_free(struct msk_if_softc *); 303 static void msk_rx_dma_jfree(struct msk_if_softc *); 304 static int msk_rx_fill(struct msk_if_softc *, int); 305 static int msk_init_rx_ring(struct msk_if_softc *); 306 static int msk_init_jumbo_rx_ring(struct msk_if_softc *); 307 static void msk_init_tx_ring(struct msk_if_softc *); 308 static __inline void msk_discard_rxbuf(struct msk_if_softc *, int); 309 static __inline void msk_discard_jumbo_rxbuf(struct msk_if_softc *, int); 310 static int msk_newbuf(struct msk_if_softc *, int); 311 static int msk_jumbo_newbuf(struct msk_if_softc *, int); 312 313 static int msk_phy_readreg(struct msk_if_softc *, int, int); 314 static int msk_phy_writereg(struct msk_if_softc *, int, int, int); 315 static int msk_miibus_readreg(device_t, int, int); 316 static int msk_miibus_writereg(device_t, int, int, int); 317 static void msk_miibus_statchg(device_t); 318 319 static void msk_rxfilter(struct msk_if_softc *); 320 static void msk_setvlan(struct msk_if_softc *, if_t); 321 322 static void msk_stats_clear(struct msk_if_softc *); 323 static void msk_stats_update(struct msk_if_softc *); 324 static int msk_sysctl_stat32(SYSCTL_HANDLER_ARGS); 325 static int msk_sysctl_stat64(SYSCTL_HANDLER_ARGS); 326 static void msk_sysctl_node(struct msk_if_softc *); 327 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int); 328 static int sysctl_hw_msk_proc_limit(SYSCTL_HANDLER_ARGS); 329 330 static device_method_t mskc_methods[] = { 331 /* Device interface */ 332 DEVMETHOD(device_probe, mskc_probe), 333 DEVMETHOD(device_attach, mskc_attach), 334 DEVMETHOD(device_detach, mskc_detach), 335 DEVMETHOD(device_suspend, mskc_suspend), 336 DEVMETHOD(device_resume, mskc_resume), 337 DEVMETHOD(device_shutdown, mskc_shutdown), 338 339 DEVMETHOD(bus_child_deleted, mskc_child_deleted), 340 DEVMETHOD(bus_get_dma_tag, mskc_get_dma_tag), 341 342 DEVMETHOD_END 343 }; 344 345 static driver_t mskc_driver = { 346 "mskc", 347 mskc_methods, 348 sizeof(struct msk_softc) 349 }; 350 351 static device_method_t msk_methods[] = { 352 /* Device interface */ 353 DEVMETHOD(device_probe, msk_probe), 354 DEVMETHOD(device_attach, msk_attach), 355 DEVMETHOD(device_detach, msk_detach), 356 DEVMETHOD(device_shutdown, bus_generic_shutdown), 357 358 /* MII interface */ 359 DEVMETHOD(miibus_readreg, msk_miibus_readreg), 360 DEVMETHOD(miibus_writereg, msk_miibus_writereg), 361 DEVMETHOD(miibus_statchg, msk_miibus_statchg), 362 363 DEVMETHOD_END 364 }; 365 366 static driver_t msk_driver = { 367 "msk", 368 msk_methods, 369 sizeof(struct msk_if_softc) 370 }; 371 372 DRIVER_MODULE(mskc, pci, mskc_driver, NULL, NULL); 373 DRIVER_MODULE(msk, mskc, msk_driver, NULL, NULL); 374 DRIVER_MODULE(miibus, msk, miibus_driver, NULL, NULL); 375 376 static struct resource_spec msk_res_spec_io[] = { 377 { SYS_RES_IOPORT, PCIR_BAR(1), RF_ACTIVE }, 378 { -1, 0, 0 } 379 }; 380 381 static struct resource_spec msk_res_spec_mem[] = { 382 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 383 { -1, 0, 0 } 384 }; 385 386 static struct resource_spec msk_irq_spec_legacy[] = { 387 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 388 { -1, 0, 0 } 389 }; 390 391 static struct resource_spec msk_irq_spec_msi[] = { 392 { SYS_RES_IRQ, 1, RF_ACTIVE }, 393 { -1, 0, 0 } 394 }; 395 396 static int 397 msk_miibus_readreg(device_t dev, int phy, int reg) 398 { 399 struct msk_if_softc *sc_if; 400 401 sc_if = device_get_softc(dev); 402 403 return (msk_phy_readreg(sc_if, phy, reg)); 404 } 405 406 static int 407 msk_phy_readreg(struct msk_if_softc *sc_if, int phy, int reg) 408 { 409 struct msk_softc *sc; 410 int i, val; 411 412 sc = sc_if->msk_softc; 413 414 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SMI_CTRL, 415 GM_SMI_CT_PHY_AD(phy) | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD); 416 417 for (i = 0; i < MSK_TIMEOUT; i++) { 418 DELAY(1); 419 val = GMAC_READ_2(sc, sc_if->msk_port, GM_SMI_CTRL); 420 if ((val & GM_SMI_CT_RD_VAL) != 0) { 421 val = GMAC_READ_2(sc, sc_if->msk_port, GM_SMI_DATA); 422 break; 423 } 424 } 425 426 if (i == MSK_TIMEOUT) { 427 if_printf(sc_if->msk_ifp, "phy failed to come ready\n"); 428 val = 0; 429 } 430 431 return (val); 432 } 433 434 static int 435 msk_miibus_writereg(device_t dev, int phy, int reg, int val) 436 { 437 struct msk_if_softc *sc_if; 438 439 sc_if = device_get_softc(dev); 440 441 return (msk_phy_writereg(sc_if, phy, reg, val)); 442 } 443 444 static int 445 msk_phy_writereg(struct msk_if_softc *sc_if, int phy, int reg, int val) 446 { 447 struct msk_softc *sc; 448 int i; 449 450 sc = sc_if->msk_softc; 451 452 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SMI_DATA, val); 453 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SMI_CTRL, 454 GM_SMI_CT_PHY_AD(phy) | GM_SMI_CT_REG_AD(reg)); 455 for (i = 0; i < MSK_TIMEOUT; i++) { 456 DELAY(1); 457 if ((GMAC_READ_2(sc, sc_if->msk_port, GM_SMI_CTRL) & 458 GM_SMI_CT_BUSY) == 0) 459 break; 460 } 461 if (i == MSK_TIMEOUT) 462 if_printf(sc_if->msk_ifp, "phy write timeout\n"); 463 464 return (0); 465 } 466 467 static void 468 msk_miibus_statchg(device_t dev) 469 { 470 struct msk_softc *sc; 471 struct msk_if_softc *sc_if; 472 struct mii_data *mii; 473 if_t ifp; 474 uint32_t gmac; 475 476 sc_if = device_get_softc(dev); 477 sc = sc_if->msk_softc; 478 479 MSK_IF_LOCK_ASSERT(sc_if); 480 481 mii = device_get_softc(sc_if->msk_miibus); 482 ifp = sc_if->msk_ifp; 483 if (mii == NULL || ifp == NULL || 484 (if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) 485 return; 486 487 sc_if->msk_flags &= ~MSK_FLAG_LINK; 488 if ((mii->mii_media_status & (IFM_AVALID | IFM_ACTIVE)) == 489 (IFM_AVALID | IFM_ACTIVE)) { 490 switch (IFM_SUBTYPE(mii->mii_media_active)) { 491 case IFM_10_T: 492 case IFM_100_TX: 493 sc_if->msk_flags |= MSK_FLAG_LINK; 494 break; 495 case IFM_1000_T: 496 case IFM_1000_SX: 497 case IFM_1000_LX: 498 case IFM_1000_CX: 499 if ((sc_if->msk_flags & MSK_FLAG_FASTETHER) == 0) 500 sc_if->msk_flags |= MSK_FLAG_LINK; 501 break; 502 default: 503 break; 504 } 505 } 506 507 if ((sc_if->msk_flags & MSK_FLAG_LINK) != 0) { 508 /* Enable Tx FIFO Underrun. */ 509 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_MSK), 510 GM_IS_TX_FF_UR | GM_IS_RX_FF_OR); 511 /* 512 * Because mii(4) notify msk(4) that it detected link status 513 * change, there is no need to enable automatic 514 * speed/flow-control/duplex updates. 515 */ 516 gmac = GM_GPCR_AU_ALL_DIS; 517 switch (IFM_SUBTYPE(mii->mii_media_active)) { 518 case IFM_1000_SX: 519 case IFM_1000_T: 520 gmac |= GM_GPCR_SPEED_1000; 521 break; 522 case IFM_100_TX: 523 gmac |= GM_GPCR_SPEED_100; 524 break; 525 case IFM_10_T: 526 break; 527 } 528 529 if ((IFM_OPTIONS(mii->mii_media_active) & 530 IFM_ETH_RXPAUSE) == 0) 531 gmac |= GM_GPCR_FC_RX_DIS; 532 if ((IFM_OPTIONS(mii->mii_media_active) & 533 IFM_ETH_TXPAUSE) == 0) 534 gmac |= GM_GPCR_FC_TX_DIS; 535 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) 536 gmac |= GM_GPCR_DUP_FULL; 537 else 538 gmac |= GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS; 539 gmac |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA; 540 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, gmac); 541 /* Read again to ensure writing. */ 542 GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL); 543 gmac = GMC_PAUSE_OFF; 544 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 545 if ((IFM_OPTIONS(mii->mii_media_active) & 546 IFM_ETH_RXPAUSE) != 0) 547 gmac = GMC_PAUSE_ON; 548 } 549 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), gmac); 550 551 /* Enable PHY interrupt for FIFO underrun/overflow. */ 552 msk_phy_writereg(sc_if, PHY_ADDR_MARV, 553 PHY_MARV_INT_MASK, PHY_M_IS_FIFO_ERROR); 554 } else { 555 /* 556 * Link state changed to down. 557 * Disable PHY interrupts. 558 */ 559 msk_phy_writereg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_MASK, 0); 560 /* Disable Rx/Tx MAC. */ 561 gmac = GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL); 562 if ((gmac & (GM_GPCR_RX_ENA | GM_GPCR_TX_ENA)) != 0) { 563 gmac &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA); 564 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, gmac); 565 /* Read again to ensure writing. */ 566 GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL); 567 } 568 } 569 } 570 571 static u_int 572 msk_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) 573 { 574 uint32_t *mchash = arg; 575 uint32_t crc; 576 577 crc = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN); 578 /* Just want the 6 least significant bits. */ 579 crc &= 0x3f; 580 /* Set the corresponding bit in the hash table. */ 581 mchash[crc >> 5] |= 1 << (crc & 0x1f); 582 583 return (1); 584 } 585 586 static void 587 msk_rxfilter(struct msk_if_softc *sc_if) 588 { 589 struct msk_softc *sc; 590 if_t ifp; 591 uint32_t mchash[2]; 592 uint16_t mode; 593 594 sc = sc_if->msk_softc; 595 596 MSK_IF_LOCK_ASSERT(sc_if); 597 598 ifp = sc_if->msk_ifp; 599 600 bzero(mchash, sizeof(mchash)); 601 mode = GMAC_READ_2(sc, sc_if->msk_port, GM_RX_CTRL); 602 if ((if_getflags(ifp) & IFF_PROMISC) != 0) 603 mode &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA); 604 else if ((if_getflags(ifp) & IFF_ALLMULTI) != 0) { 605 mode |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA; 606 mchash[0] = 0xffff; 607 mchash[1] = 0xffff; 608 } else { 609 mode |= GM_RXCR_UCF_ENA; 610 if_foreach_llmaddr(ifp, msk_hash_maddr, mchash); 611 if (mchash[0] != 0 || mchash[1] != 0) 612 mode |= GM_RXCR_MCF_ENA; 613 } 614 615 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H1, 616 mchash[0] & 0xffff); 617 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H2, 618 (mchash[0] >> 16) & 0xffff); 619 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H3, 620 mchash[1] & 0xffff); 621 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H4, 622 (mchash[1] >> 16) & 0xffff); 623 GMAC_WRITE_2(sc, sc_if->msk_port, GM_RX_CTRL, mode); 624 } 625 626 static void 627 msk_setvlan(struct msk_if_softc *sc_if, if_t ifp) 628 { 629 struct msk_softc *sc; 630 631 sc = sc_if->msk_softc; 632 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0) { 633 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), 634 RX_VLAN_STRIP_ON); 635 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 636 TX_VLAN_TAG_ON); 637 } else { 638 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), 639 RX_VLAN_STRIP_OFF); 640 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 641 TX_VLAN_TAG_OFF); 642 } 643 } 644 645 static int 646 msk_rx_fill(struct msk_if_softc *sc_if, int jumbo) 647 { 648 uint16_t idx; 649 int i; 650 651 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0 && 652 (if_getcapenable(sc_if->msk_ifp) & IFCAP_RXCSUM) != 0) { 653 /* Wait until controller executes OP_TCPSTART command. */ 654 for (i = 100; i > 0; i--) { 655 DELAY(100); 656 idx = CSR_READ_2(sc_if->msk_softc, 657 Y2_PREF_Q_ADDR(sc_if->msk_rxq, 658 PREF_UNIT_GET_IDX_REG)); 659 if (idx != 0) 660 break; 661 } 662 if (i == 0) { 663 device_printf(sc_if->msk_if_dev, 664 "prefetch unit stuck?\n"); 665 return (ETIMEDOUT); 666 } 667 /* 668 * Fill consumed LE with free buffer. This can be done 669 * in Rx handler but we don't want to add special code 670 * in fast handler. 671 */ 672 if (jumbo > 0) { 673 if (msk_jumbo_newbuf(sc_if, 0) != 0) 674 return (ENOBUFS); 675 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 676 sc_if->msk_cdata.msk_jumbo_rx_ring_map, 677 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 678 } else { 679 if (msk_newbuf(sc_if, 0) != 0) 680 return (ENOBUFS); 681 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_ring_tag, 682 sc_if->msk_cdata.msk_rx_ring_map, 683 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 684 } 685 sc_if->msk_cdata.msk_rx_prod = 0; 686 CSR_WRITE_2(sc_if->msk_softc, 687 Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_PUT_IDX_REG), 688 sc_if->msk_cdata.msk_rx_prod); 689 } 690 return (0); 691 } 692 693 static int 694 msk_init_rx_ring(struct msk_if_softc *sc_if) 695 { 696 struct msk_ring_data *rd; 697 struct msk_rxdesc *rxd; 698 int i, nbuf, prod; 699 700 MSK_IF_LOCK_ASSERT(sc_if); 701 702 sc_if->msk_cdata.msk_rx_cons = 0; 703 sc_if->msk_cdata.msk_rx_prod = 0; 704 sc_if->msk_cdata.msk_rx_putwm = MSK_PUT_WM; 705 706 rd = &sc_if->msk_rdata; 707 bzero(rd->msk_rx_ring, sizeof(struct msk_rx_desc) * MSK_RX_RING_CNT); 708 for (i = prod = 0; i < MSK_RX_RING_CNT; i++) { 709 rxd = &sc_if->msk_cdata.msk_rxdesc[prod]; 710 rxd->rx_m = NULL; 711 rxd->rx_le = &rd->msk_rx_ring[prod]; 712 MSK_INC(prod, MSK_RX_RING_CNT); 713 } 714 nbuf = MSK_RX_BUF_CNT; 715 prod = 0; 716 /* Have controller know how to compute Rx checksum. */ 717 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0 && 718 (if_getcapenable(sc_if->msk_ifp) & IFCAP_RXCSUM) != 0) { 719 #ifdef MSK_64BIT_DMA 720 rxd = &sc_if->msk_cdata.msk_rxdesc[prod]; 721 rxd->rx_m = NULL; 722 rxd->rx_le = &rd->msk_rx_ring[prod]; 723 rxd->rx_le->msk_addr = htole32(ETHER_HDR_LEN << 16 | 724 ETHER_HDR_LEN); 725 rxd->rx_le->msk_control = htole32(OP_TCPSTART | HW_OWNER); 726 MSK_INC(prod, MSK_RX_RING_CNT); 727 MSK_INC(sc_if->msk_cdata.msk_rx_cons, MSK_RX_RING_CNT); 728 #endif 729 rxd = &sc_if->msk_cdata.msk_rxdesc[prod]; 730 rxd->rx_m = NULL; 731 rxd->rx_le = &rd->msk_rx_ring[prod]; 732 rxd->rx_le->msk_addr = htole32(ETHER_HDR_LEN << 16 | 733 ETHER_HDR_LEN); 734 rxd->rx_le->msk_control = htole32(OP_TCPSTART | HW_OWNER); 735 MSK_INC(prod, MSK_RX_RING_CNT); 736 MSK_INC(sc_if->msk_cdata.msk_rx_cons, MSK_RX_RING_CNT); 737 nbuf--; 738 } 739 for (i = 0; i < nbuf; i++) { 740 if (msk_newbuf(sc_if, prod) != 0) 741 return (ENOBUFS); 742 MSK_RX_INC(prod, MSK_RX_RING_CNT); 743 } 744 745 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_ring_tag, 746 sc_if->msk_cdata.msk_rx_ring_map, 747 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 748 749 /* Update prefetch unit. */ 750 sc_if->msk_cdata.msk_rx_prod = prod; 751 CSR_WRITE_2(sc_if->msk_softc, 752 Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_PUT_IDX_REG), 753 (sc_if->msk_cdata.msk_rx_prod + MSK_RX_RING_CNT - 1) % 754 MSK_RX_RING_CNT); 755 if (msk_rx_fill(sc_if, 0) != 0) 756 return (ENOBUFS); 757 return (0); 758 } 759 760 static int 761 msk_init_jumbo_rx_ring(struct msk_if_softc *sc_if) 762 { 763 struct msk_ring_data *rd; 764 struct msk_rxdesc *rxd; 765 int i, nbuf, prod; 766 767 MSK_IF_LOCK_ASSERT(sc_if); 768 769 sc_if->msk_cdata.msk_rx_cons = 0; 770 sc_if->msk_cdata.msk_rx_prod = 0; 771 sc_if->msk_cdata.msk_rx_putwm = MSK_PUT_WM; 772 773 rd = &sc_if->msk_rdata; 774 bzero(rd->msk_jumbo_rx_ring, 775 sizeof(struct msk_rx_desc) * MSK_JUMBO_RX_RING_CNT); 776 for (i = prod = 0; i < MSK_JUMBO_RX_RING_CNT; i++) { 777 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[prod]; 778 rxd->rx_m = NULL; 779 rxd->rx_le = &rd->msk_jumbo_rx_ring[prod]; 780 MSK_INC(prod, MSK_JUMBO_RX_RING_CNT); 781 } 782 nbuf = MSK_RX_BUF_CNT; 783 prod = 0; 784 /* Have controller know how to compute Rx checksum. */ 785 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0 && 786 (if_getcapenable(sc_if->msk_ifp) & IFCAP_RXCSUM) != 0) { 787 #ifdef MSK_64BIT_DMA 788 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[prod]; 789 rxd->rx_m = NULL; 790 rxd->rx_le = &rd->msk_jumbo_rx_ring[prod]; 791 rxd->rx_le->msk_addr = htole32(ETHER_HDR_LEN << 16 | 792 ETHER_HDR_LEN); 793 rxd->rx_le->msk_control = htole32(OP_TCPSTART | HW_OWNER); 794 MSK_INC(prod, MSK_JUMBO_RX_RING_CNT); 795 MSK_INC(sc_if->msk_cdata.msk_rx_cons, MSK_JUMBO_RX_RING_CNT); 796 #endif 797 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[prod]; 798 rxd->rx_m = NULL; 799 rxd->rx_le = &rd->msk_jumbo_rx_ring[prod]; 800 rxd->rx_le->msk_addr = htole32(ETHER_HDR_LEN << 16 | 801 ETHER_HDR_LEN); 802 rxd->rx_le->msk_control = htole32(OP_TCPSTART | HW_OWNER); 803 MSK_INC(prod, MSK_JUMBO_RX_RING_CNT); 804 MSK_INC(sc_if->msk_cdata.msk_rx_cons, MSK_JUMBO_RX_RING_CNT); 805 nbuf--; 806 } 807 for (i = 0; i < nbuf; i++) { 808 if (msk_jumbo_newbuf(sc_if, prod) != 0) 809 return (ENOBUFS); 810 MSK_RX_INC(prod, MSK_JUMBO_RX_RING_CNT); 811 } 812 813 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 814 sc_if->msk_cdata.msk_jumbo_rx_ring_map, 815 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 816 817 /* Update prefetch unit. */ 818 sc_if->msk_cdata.msk_rx_prod = prod; 819 CSR_WRITE_2(sc_if->msk_softc, 820 Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_PUT_IDX_REG), 821 (sc_if->msk_cdata.msk_rx_prod + MSK_JUMBO_RX_RING_CNT - 1) % 822 MSK_JUMBO_RX_RING_CNT); 823 if (msk_rx_fill(sc_if, 1) != 0) 824 return (ENOBUFS); 825 return (0); 826 } 827 828 static void 829 msk_init_tx_ring(struct msk_if_softc *sc_if) 830 { 831 struct msk_ring_data *rd; 832 struct msk_txdesc *txd; 833 int i; 834 835 sc_if->msk_cdata.msk_tso_mtu = 0; 836 sc_if->msk_cdata.msk_last_csum = 0; 837 sc_if->msk_cdata.msk_tx_prod = 0; 838 sc_if->msk_cdata.msk_tx_cons = 0; 839 sc_if->msk_cdata.msk_tx_cnt = 0; 840 sc_if->msk_cdata.msk_tx_high_addr = 0; 841 842 rd = &sc_if->msk_rdata; 843 bzero(rd->msk_tx_ring, sizeof(struct msk_tx_desc) * MSK_TX_RING_CNT); 844 for (i = 0; i < MSK_TX_RING_CNT; i++) { 845 txd = &sc_if->msk_cdata.msk_txdesc[i]; 846 txd->tx_m = NULL; 847 txd->tx_le = &rd->msk_tx_ring[i]; 848 } 849 850 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_ring_tag, 851 sc_if->msk_cdata.msk_tx_ring_map, 852 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 853 } 854 855 static __inline void 856 msk_discard_rxbuf(struct msk_if_softc *sc_if, int idx) 857 { 858 struct msk_rx_desc *rx_le; 859 struct msk_rxdesc *rxd; 860 struct mbuf *m; 861 862 #ifdef MSK_64BIT_DMA 863 rxd = &sc_if->msk_cdata.msk_rxdesc[idx]; 864 rx_le = rxd->rx_le; 865 rx_le->msk_control = htole32(OP_ADDR64 | HW_OWNER); 866 MSK_INC(idx, MSK_RX_RING_CNT); 867 #endif 868 rxd = &sc_if->msk_cdata.msk_rxdesc[idx]; 869 m = rxd->rx_m; 870 rx_le = rxd->rx_le; 871 rx_le->msk_control = htole32(m->m_len | OP_PACKET | HW_OWNER); 872 } 873 874 static __inline void 875 msk_discard_jumbo_rxbuf(struct msk_if_softc *sc_if, int idx) 876 { 877 struct msk_rx_desc *rx_le; 878 struct msk_rxdesc *rxd; 879 struct mbuf *m; 880 881 #ifdef MSK_64BIT_DMA 882 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[idx]; 883 rx_le = rxd->rx_le; 884 rx_le->msk_control = htole32(OP_ADDR64 | HW_OWNER); 885 MSK_INC(idx, MSK_JUMBO_RX_RING_CNT); 886 #endif 887 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[idx]; 888 m = rxd->rx_m; 889 rx_le = rxd->rx_le; 890 rx_le->msk_control = htole32(m->m_len | OP_PACKET | HW_OWNER); 891 } 892 893 static int 894 msk_newbuf(struct msk_if_softc *sc_if, int idx) 895 { 896 struct msk_rx_desc *rx_le; 897 struct msk_rxdesc *rxd; 898 struct mbuf *m; 899 bus_dma_segment_t segs[1]; 900 bus_dmamap_t map; 901 int nsegs; 902 903 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 904 if (m == NULL) 905 return (ENOBUFS); 906 907 m->m_len = m->m_pkthdr.len = MCLBYTES; 908 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) == 0) 909 m_adj(m, ETHER_ALIGN); 910 #ifndef __NO_STRICT_ALIGNMENT 911 else 912 m_adj(m, MSK_RX_BUF_ALIGN); 913 #endif 914 915 if (bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_rx_tag, 916 sc_if->msk_cdata.msk_rx_sparemap, m, segs, &nsegs, 917 BUS_DMA_NOWAIT) != 0) { 918 m_freem(m); 919 return (ENOBUFS); 920 } 921 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 922 923 rxd = &sc_if->msk_cdata.msk_rxdesc[idx]; 924 #ifdef MSK_64BIT_DMA 925 rx_le = rxd->rx_le; 926 rx_le->msk_addr = htole32(MSK_ADDR_HI(segs[0].ds_addr)); 927 rx_le->msk_control = htole32(OP_ADDR64 | HW_OWNER); 928 MSK_INC(idx, MSK_RX_RING_CNT); 929 rxd = &sc_if->msk_cdata.msk_rxdesc[idx]; 930 #endif 931 if (rxd->rx_m != NULL) { 932 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_tag, rxd->rx_dmamap, 933 BUS_DMASYNC_POSTREAD); 934 bus_dmamap_unload(sc_if->msk_cdata.msk_rx_tag, rxd->rx_dmamap); 935 rxd->rx_m = NULL; 936 } 937 map = rxd->rx_dmamap; 938 rxd->rx_dmamap = sc_if->msk_cdata.msk_rx_sparemap; 939 sc_if->msk_cdata.msk_rx_sparemap = map; 940 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_tag, rxd->rx_dmamap, 941 BUS_DMASYNC_PREREAD); 942 rxd->rx_m = m; 943 rx_le = rxd->rx_le; 944 rx_le->msk_addr = htole32(MSK_ADDR_LO(segs[0].ds_addr)); 945 rx_le->msk_control = 946 htole32(segs[0].ds_len | OP_PACKET | HW_OWNER); 947 948 return (0); 949 } 950 951 static int 952 msk_jumbo_newbuf(struct msk_if_softc *sc_if, int idx) 953 { 954 struct msk_rx_desc *rx_le; 955 struct msk_rxdesc *rxd; 956 struct mbuf *m; 957 bus_dma_segment_t segs[1]; 958 bus_dmamap_t map; 959 int nsegs; 960 961 m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES); 962 if (m == NULL) 963 return (ENOBUFS); 964 m->m_len = m->m_pkthdr.len = MJUM9BYTES; 965 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) == 0) 966 m_adj(m, ETHER_ALIGN); 967 #ifndef __NO_STRICT_ALIGNMENT 968 else 969 m_adj(m, MSK_RX_BUF_ALIGN); 970 #endif 971 972 if (bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_jumbo_rx_tag, 973 sc_if->msk_cdata.msk_jumbo_rx_sparemap, m, segs, &nsegs, 974 BUS_DMA_NOWAIT) != 0) { 975 m_freem(m); 976 return (ENOBUFS); 977 } 978 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 979 980 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[idx]; 981 #ifdef MSK_64BIT_DMA 982 rx_le = rxd->rx_le; 983 rx_le->msk_addr = htole32(MSK_ADDR_HI(segs[0].ds_addr)); 984 rx_le->msk_control = htole32(OP_ADDR64 | HW_OWNER); 985 MSK_INC(idx, MSK_JUMBO_RX_RING_CNT); 986 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[idx]; 987 #endif 988 if (rxd->rx_m != NULL) { 989 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_tag, 990 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 991 bus_dmamap_unload(sc_if->msk_cdata.msk_jumbo_rx_tag, 992 rxd->rx_dmamap); 993 rxd->rx_m = NULL; 994 } 995 map = rxd->rx_dmamap; 996 rxd->rx_dmamap = sc_if->msk_cdata.msk_jumbo_rx_sparemap; 997 sc_if->msk_cdata.msk_jumbo_rx_sparemap = map; 998 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_tag, rxd->rx_dmamap, 999 BUS_DMASYNC_PREREAD); 1000 rxd->rx_m = m; 1001 rx_le = rxd->rx_le; 1002 rx_le->msk_addr = htole32(MSK_ADDR_LO(segs[0].ds_addr)); 1003 rx_le->msk_control = 1004 htole32(segs[0].ds_len | OP_PACKET | HW_OWNER); 1005 1006 return (0); 1007 } 1008 1009 /* 1010 * Set media options. 1011 */ 1012 static int 1013 msk_mediachange(if_t ifp) 1014 { 1015 struct msk_if_softc *sc_if; 1016 struct mii_data *mii; 1017 int error; 1018 1019 sc_if = if_getsoftc(ifp); 1020 1021 MSK_IF_LOCK(sc_if); 1022 mii = device_get_softc(sc_if->msk_miibus); 1023 error = mii_mediachg(mii); 1024 MSK_IF_UNLOCK(sc_if); 1025 1026 return (error); 1027 } 1028 1029 /* 1030 * Report current media status. 1031 */ 1032 static void 1033 msk_mediastatus(if_t ifp, struct ifmediareq *ifmr) 1034 { 1035 struct msk_if_softc *sc_if; 1036 struct mii_data *mii; 1037 1038 sc_if = if_getsoftc(ifp); 1039 MSK_IF_LOCK(sc_if); 1040 if ((if_getflags(ifp) & IFF_UP) == 0) { 1041 MSK_IF_UNLOCK(sc_if); 1042 return; 1043 } 1044 mii = device_get_softc(sc_if->msk_miibus); 1045 1046 mii_pollstat(mii); 1047 ifmr->ifm_active = mii->mii_media_active; 1048 ifmr->ifm_status = mii->mii_media_status; 1049 MSK_IF_UNLOCK(sc_if); 1050 } 1051 1052 static int 1053 msk_ioctl(if_t ifp, u_long command, caddr_t data) 1054 { 1055 struct msk_if_softc *sc_if; 1056 struct ifreq *ifr; 1057 struct mii_data *mii; 1058 int error, mask, reinit; 1059 1060 sc_if = if_getsoftc(ifp); 1061 ifr = (struct ifreq *)data; 1062 error = 0; 1063 1064 switch(command) { 1065 case SIOCSIFMTU: 1066 MSK_IF_LOCK(sc_if); 1067 if (ifr->ifr_mtu > MSK_JUMBO_MTU || ifr->ifr_mtu < ETHERMIN) 1068 error = EINVAL; 1069 else if (if_getmtu(ifp) != ifr->ifr_mtu) { 1070 if (ifr->ifr_mtu > ETHERMTU) { 1071 if ((sc_if->msk_flags & MSK_FLAG_JUMBO) == 0) { 1072 error = EINVAL; 1073 MSK_IF_UNLOCK(sc_if); 1074 break; 1075 } 1076 if ((sc_if->msk_flags & 1077 MSK_FLAG_JUMBO_NOCSUM) != 0) { 1078 if_sethwassistbits(ifp, 0, 1079 MSK_CSUM_FEATURES | CSUM_TSO); 1080 if_setcapenablebit(ifp, 0, 1081 IFCAP_TSO4 | IFCAP_TXCSUM); 1082 VLAN_CAPABILITIES(ifp); 1083 } 1084 } 1085 if_setmtu(ifp, ifr->ifr_mtu); 1086 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 1087 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 1088 msk_init_locked(sc_if); 1089 } 1090 } 1091 MSK_IF_UNLOCK(sc_if); 1092 break; 1093 case SIOCSIFFLAGS: 1094 MSK_IF_LOCK(sc_if); 1095 if ((if_getflags(ifp) & IFF_UP) != 0) { 1096 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0 && 1097 ((if_getflags(ifp) ^ sc_if->msk_if_flags) & 1098 (IFF_PROMISC | IFF_ALLMULTI)) != 0) 1099 msk_rxfilter(sc_if); 1100 else if ((sc_if->msk_flags & MSK_FLAG_DETACH) == 0) 1101 msk_init_locked(sc_if); 1102 } else if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 1103 msk_stop(sc_if); 1104 sc_if->msk_if_flags = if_getflags(ifp); 1105 MSK_IF_UNLOCK(sc_if); 1106 break; 1107 case SIOCADDMULTI: 1108 case SIOCDELMULTI: 1109 MSK_IF_LOCK(sc_if); 1110 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 1111 msk_rxfilter(sc_if); 1112 MSK_IF_UNLOCK(sc_if); 1113 break; 1114 case SIOCGIFMEDIA: 1115 case SIOCSIFMEDIA: 1116 mii = device_get_softc(sc_if->msk_miibus); 1117 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1118 break; 1119 case SIOCSIFCAP: 1120 reinit = 0; 1121 MSK_IF_LOCK(sc_if); 1122 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp); 1123 if ((mask & IFCAP_TXCSUM) != 0 && 1124 (IFCAP_TXCSUM & if_getcapabilities(ifp)) != 0) { 1125 if_togglecapenable(ifp, IFCAP_TXCSUM); 1126 if ((IFCAP_TXCSUM & if_getcapenable(ifp)) != 0) 1127 if_sethwassistbits(ifp, MSK_CSUM_FEATURES, 0); 1128 else 1129 if_sethwassistbits(ifp, 0, MSK_CSUM_FEATURES); 1130 } 1131 if ((mask & IFCAP_RXCSUM) != 0 && 1132 (IFCAP_RXCSUM & if_getcapabilities(ifp)) != 0) { 1133 if_togglecapenable(ifp, IFCAP_RXCSUM); 1134 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0) 1135 reinit = 1; 1136 } 1137 if ((mask & IFCAP_VLAN_HWCSUM) != 0 && 1138 (IFCAP_VLAN_HWCSUM & if_getcapabilities(ifp)) != 0) 1139 if_togglecapenable(ifp, IFCAP_VLAN_HWCSUM); 1140 if ((mask & IFCAP_TSO4) != 0 && 1141 (IFCAP_TSO4 & if_getcapabilities(ifp)) != 0) { 1142 if_togglecapenable(ifp, IFCAP_TSO4); 1143 if ((IFCAP_TSO4 & if_getcapenable(ifp)) != 0) 1144 if_sethwassistbits(ifp, CSUM_TSO, 0); 1145 else 1146 if_sethwassistbits(ifp, 0, CSUM_TSO); 1147 } 1148 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 1149 (IFCAP_VLAN_HWTSO & if_getcapabilities(ifp)) != 0) 1150 if_togglecapenable(ifp, IFCAP_VLAN_HWTSO); 1151 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 1152 (IFCAP_VLAN_HWTAGGING & if_getcapabilities(ifp)) != 0) { 1153 if_togglecapenable(ifp, IFCAP_VLAN_HWTAGGING); 1154 if ((IFCAP_VLAN_HWTAGGING & if_getcapenable(ifp)) == 0) 1155 if_setcapenablebit(ifp, 0, 1156 IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM); 1157 msk_setvlan(sc_if, ifp); 1158 } 1159 if (if_getmtu(ifp) > ETHERMTU && 1160 (sc_if->msk_flags & MSK_FLAG_JUMBO_NOCSUM) != 0) { 1161 if_sethwassistbits(ifp, 0, (MSK_CSUM_FEATURES | CSUM_TSO)); 1162 if_setcapenablebit(ifp, 0, (IFCAP_TSO4 | IFCAP_TXCSUM)); 1163 } 1164 VLAN_CAPABILITIES(ifp); 1165 if (reinit > 0 && (if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 1166 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 1167 msk_init_locked(sc_if); 1168 } 1169 MSK_IF_UNLOCK(sc_if); 1170 break; 1171 default: 1172 error = ether_ioctl(ifp, command, data); 1173 break; 1174 } 1175 1176 return (error); 1177 } 1178 1179 static int 1180 mskc_probe(device_t dev) 1181 { 1182 const struct msk_product *mp; 1183 uint16_t vendor, devid; 1184 int i; 1185 1186 vendor = pci_get_vendor(dev); 1187 devid = pci_get_device(dev); 1188 mp = msk_products; 1189 for (i = 0; i < nitems(msk_products); i++, mp++) { 1190 if (vendor == mp->msk_vendorid && devid == mp->msk_deviceid) { 1191 device_set_desc(dev, mp->msk_name); 1192 return (BUS_PROBE_DEFAULT); 1193 } 1194 } 1195 1196 return (ENXIO); 1197 } 1198 1199 static int 1200 mskc_setup_rambuffer(struct msk_softc *sc) 1201 { 1202 int next; 1203 int i; 1204 1205 /* Get adapter SRAM size. */ 1206 sc->msk_ramsize = CSR_READ_1(sc, B2_E_0) * 4; 1207 if (bootverbose) 1208 device_printf(sc->msk_dev, 1209 "RAM buffer size : %dKB\n", sc->msk_ramsize); 1210 if (sc->msk_ramsize == 0) 1211 return (0); 1212 1213 sc->msk_pflags |= MSK_FLAG_RAMBUF; 1214 /* 1215 * Give receiver 2/3 of memory and round down to the multiple 1216 * of 1024. Tx/Rx RAM buffer size of Yukon II should be multiple 1217 * of 1024. 1218 */ 1219 sc->msk_rxqsize = rounddown((sc->msk_ramsize * 1024 * 2) / 3, 1024); 1220 sc->msk_txqsize = (sc->msk_ramsize * 1024) - sc->msk_rxqsize; 1221 for (i = 0, next = 0; i < sc->msk_num_port; i++) { 1222 sc->msk_rxqstart[i] = next; 1223 sc->msk_rxqend[i] = next + sc->msk_rxqsize - 1; 1224 next = sc->msk_rxqend[i] + 1; 1225 sc->msk_txqstart[i] = next; 1226 sc->msk_txqend[i] = next + sc->msk_txqsize - 1; 1227 next = sc->msk_txqend[i] + 1; 1228 if (bootverbose) { 1229 device_printf(sc->msk_dev, 1230 "Port %d : Rx Queue %dKB(0x%08x:0x%08x)\n", i, 1231 sc->msk_rxqsize / 1024, sc->msk_rxqstart[i], 1232 sc->msk_rxqend[i]); 1233 device_printf(sc->msk_dev, 1234 "Port %d : Tx Queue %dKB(0x%08x:0x%08x)\n", i, 1235 sc->msk_txqsize / 1024, sc->msk_txqstart[i], 1236 sc->msk_txqend[i]); 1237 } 1238 } 1239 1240 return (0); 1241 } 1242 1243 static void 1244 msk_phy_power(struct msk_softc *sc, int mode) 1245 { 1246 uint32_t our, val; 1247 int i; 1248 1249 switch (mode) { 1250 case MSK_PHY_POWERUP: 1251 /* Switch power to VCC (WA for VAUX problem). */ 1252 CSR_WRITE_1(sc, B0_POWER_CTRL, 1253 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON); 1254 /* Disable Core Clock Division, set Clock Select to 0. */ 1255 CSR_WRITE_4(sc, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS); 1256 1257 val = 0; 1258 if (sc->msk_hw_id == CHIP_ID_YUKON_XL && 1259 sc->msk_hw_rev > CHIP_REV_YU_XL_A1) { 1260 /* Enable bits are inverted. */ 1261 val = Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS | 1262 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS | 1263 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS; 1264 } 1265 /* 1266 * Enable PCI & Core Clock, enable clock gating for both Links. 1267 */ 1268 CSR_WRITE_1(sc, B2_Y2_CLK_GATE, val); 1269 1270 our = CSR_PCI_READ_4(sc, PCI_OUR_REG_1); 1271 our &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD); 1272 if (sc->msk_hw_id == CHIP_ID_YUKON_XL) { 1273 if (sc->msk_hw_rev > CHIP_REV_YU_XL_A1) { 1274 /* Deassert Low Power for 1st PHY. */ 1275 our |= PCI_Y2_PHY1_COMA; 1276 if (sc->msk_num_port > 1) 1277 our |= PCI_Y2_PHY2_COMA; 1278 } 1279 } 1280 if (sc->msk_hw_id == CHIP_ID_YUKON_EC_U || 1281 sc->msk_hw_id == CHIP_ID_YUKON_EX || 1282 sc->msk_hw_id >= CHIP_ID_YUKON_FE_P) { 1283 val = CSR_PCI_READ_4(sc, PCI_OUR_REG_4); 1284 val &= (PCI_FORCE_ASPM_REQUEST | 1285 PCI_ASPM_GPHY_LINK_DOWN | PCI_ASPM_INT_FIFO_EMPTY | 1286 PCI_ASPM_CLKRUN_REQUEST); 1287 /* Set all bits to 0 except bits 15..12. */ 1288 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_4, val); 1289 val = CSR_PCI_READ_4(sc, PCI_OUR_REG_5); 1290 val &= PCI_CTL_TIM_VMAIN_AV_MSK; 1291 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_5, val); 1292 CSR_PCI_WRITE_4(sc, PCI_CFG_REG_1, 0); 1293 CSR_WRITE_2(sc, B0_CTST, Y2_HW_WOL_ON); 1294 /* 1295 * Disable status race, workaround for 1296 * Yukon EC Ultra & Yukon EX. 1297 */ 1298 val = CSR_READ_4(sc, B2_GP_IO); 1299 val |= GLB_GPIO_STAT_RACE_DIS; 1300 CSR_WRITE_4(sc, B2_GP_IO, val); 1301 CSR_READ_4(sc, B2_GP_IO); 1302 } 1303 /* Release PHY from PowerDown/COMA mode. */ 1304 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_1, our); 1305 1306 for (i = 0; i < sc->msk_num_port; i++) { 1307 CSR_WRITE_2(sc, MR_ADDR(i, GMAC_LINK_CTRL), 1308 GMLC_RST_SET); 1309 CSR_WRITE_2(sc, MR_ADDR(i, GMAC_LINK_CTRL), 1310 GMLC_RST_CLR); 1311 } 1312 break; 1313 case MSK_PHY_POWERDOWN: 1314 val = CSR_PCI_READ_4(sc, PCI_OUR_REG_1); 1315 val |= PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD; 1316 if (sc->msk_hw_id == CHIP_ID_YUKON_XL && 1317 sc->msk_hw_rev > CHIP_REV_YU_XL_A1) { 1318 val &= ~PCI_Y2_PHY1_COMA; 1319 if (sc->msk_num_port > 1) 1320 val &= ~PCI_Y2_PHY2_COMA; 1321 } 1322 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_1, val); 1323 1324 val = Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS | 1325 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS | 1326 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS; 1327 if (sc->msk_hw_id == CHIP_ID_YUKON_XL && 1328 sc->msk_hw_rev > CHIP_REV_YU_XL_A1) { 1329 /* Enable bits are inverted. */ 1330 val = 0; 1331 } 1332 /* 1333 * Disable PCI & Core Clock, disable clock gating for 1334 * both Links. 1335 */ 1336 CSR_WRITE_1(sc, B2_Y2_CLK_GATE, val); 1337 CSR_WRITE_1(sc, B0_POWER_CTRL, 1338 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_ON | PC_VCC_OFF); 1339 break; 1340 default: 1341 break; 1342 } 1343 } 1344 1345 static void 1346 mskc_reset(struct msk_softc *sc) 1347 { 1348 bus_addr_t addr; 1349 uint16_t status; 1350 uint32_t val; 1351 int i, initram; 1352 1353 /* Disable ASF. */ 1354 if (sc->msk_hw_id >= CHIP_ID_YUKON_XL && 1355 sc->msk_hw_id <= CHIP_ID_YUKON_SUPR) { 1356 if (sc->msk_hw_id == CHIP_ID_YUKON_EX || 1357 sc->msk_hw_id == CHIP_ID_YUKON_SUPR) { 1358 CSR_WRITE_4(sc, B28_Y2_CPU_WDOG, 0); 1359 status = CSR_READ_2(sc, B28_Y2_ASF_HCU_CCSR); 1360 /* Clear AHB bridge & microcontroller reset. */ 1361 status &= ~(Y2_ASF_HCU_CCSR_AHB_RST | 1362 Y2_ASF_HCU_CCSR_CPU_RST_MODE); 1363 /* Clear ASF microcontroller state. */ 1364 status &= ~Y2_ASF_HCU_CCSR_UC_STATE_MSK; 1365 status &= ~Y2_ASF_HCU_CCSR_CPU_CLK_DIVIDE_MSK; 1366 CSR_WRITE_2(sc, B28_Y2_ASF_HCU_CCSR, status); 1367 CSR_WRITE_4(sc, B28_Y2_CPU_WDOG, 0); 1368 } else 1369 CSR_WRITE_1(sc, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET); 1370 CSR_WRITE_2(sc, B0_CTST, Y2_ASF_DISABLE); 1371 /* 1372 * Since we disabled ASF, S/W reset is required for 1373 * Power Management. 1374 */ 1375 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); 1376 CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR); 1377 } 1378 1379 /* Clear all error bits in the PCI status register. */ 1380 status = pci_read_config(sc->msk_dev, PCIR_STATUS, 2); 1381 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON); 1382 1383 pci_write_config(sc->msk_dev, PCIR_STATUS, status | 1384 PCIM_STATUS_PERR | PCIM_STATUS_SERR | PCIM_STATUS_RMABORT | 1385 PCIM_STATUS_RTABORT | PCIM_STATUS_MDPERR, 2); 1386 CSR_WRITE_2(sc, B0_CTST, CS_MRST_CLR); 1387 1388 switch (sc->msk_bustype) { 1389 case MSK_PEX_BUS: 1390 /* Clear all PEX errors. */ 1391 CSR_PCI_WRITE_4(sc, PEX_UNC_ERR_STAT, 0xffffffff); 1392 val = CSR_PCI_READ_4(sc, PEX_UNC_ERR_STAT); 1393 if ((val & PEX_RX_OV) != 0) { 1394 sc->msk_intrmask &= ~Y2_IS_HW_ERR; 1395 sc->msk_intrhwemask &= ~Y2_IS_PCI_EXP; 1396 } 1397 break; 1398 case MSK_PCI_BUS: 1399 case MSK_PCIX_BUS: 1400 /* Set Cache Line Size to 2(8bytes) if configured to 0. */ 1401 val = pci_read_config(sc->msk_dev, PCIR_CACHELNSZ, 1); 1402 if (val == 0) 1403 pci_write_config(sc->msk_dev, PCIR_CACHELNSZ, 2, 1); 1404 if (sc->msk_bustype == MSK_PCIX_BUS) { 1405 /* Set Cache Line Size opt. */ 1406 val = pci_read_config(sc->msk_dev, PCI_OUR_REG_1, 4); 1407 val |= PCI_CLS_OPT; 1408 pci_write_config(sc->msk_dev, PCI_OUR_REG_1, val, 4); 1409 } 1410 break; 1411 } 1412 /* Set PHY power state. */ 1413 msk_phy_power(sc, MSK_PHY_POWERUP); 1414 1415 /* Reset GPHY/GMAC Control */ 1416 for (i = 0; i < sc->msk_num_port; i++) { 1417 /* GPHY Control reset. */ 1418 CSR_WRITE_1(sc, MR_ADDR(i, GPHY_CTRL), GPC_RST_SET); 1419 CSR_WRITE_1(sc, MR_ADDR(i, GPHY_CTRL), GPC_RST_CLR); 1420 /* GMAC Control reset. */ 1421 CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), GMC_RST_SET); 1422 CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), GMC_RST_CLR); 1423 CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), GMC_F_LOOPB_OFF); 1424 if (sc->msk_hw_id == CHIP_ID_YUKON_EX || 1425 sc->msk_hw_id == CHIP_ID_YUKON_SUPR) 1426 CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), 1427 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON | 1428 GMC_BYP_RETR_ON); 1429 } 1430 1431 if (sc->msk_hw_id == CHIP_ID_YUKON_SUPR && 1432 sc->msk_hw_rev > CHIP_REV_YU_SU_B0) 1433 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_3, PCI_CLK_MACSEC_DIS); 1434 if (sc->msk_hw_id == CHIP_ID_YUKON_OPT && sc->msk_hw_rev == 0) { 1435 /* Disable PCIe PHY powerdown(reg 0x80, bit7). */ 1436 CSR_WRITE_4(sc, Y2_PEX_PHY_DATA, (0x0080 << 16) | 0x0080); 1437 } 1438 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 1439 1440 /* LED On. */ 1441 CSR_WRITE_2(sc, B0_CTST, Y2_LED_STAT_ON); 1442 1443 /* Clear TWSI IRQ. */ 1444 CSR_WRITE_4(sc, B2_I2C_IRQ, I2C_CLR_IRQ); 1445 1446 /* Turn off hardware timer. */ 1447 CSR_WRITE_1(sc, B2_TI_CTRL, TIM_STOP); 1448 CSR_WRITE_1(sc, B2_TI_CTRL, TIM_CLR_IRQ); 1449 1450 /* Turn off descriptor polling. */ 1451 CSR_WRITE_1(sc, B28_DPT_CTRL, DPT_STOP); 1452 1453 /* Turn off time stamps. */ 1454 CSR_WRITE_1(sc, GMAC_TI_ST_CTRL, GMT_ST_STOP); 1455 CSR_WRITE_1(sc, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ); 1456 1457 initram = 0; 1458 if (sc->msk_hw_id == CHIP_ID_YUKON_XL || 1459 sc->msk_hw_id == CHIP_ID_YUKON_EC || 1460 sc->msk_hw_id == CHIP_ID_YUKON_FE) 1461 initram++; 1462 1463 /* Configure timeout values. */ 1464 for (i = 0; initram > 0 && i < sc->msk_num_port; i++) { 1465 CSR_WRITE_2(sc, SELECT_RAM_BUFFER(i, B3_RI_CTRL), RI_RST_SET); 1466 CSR_WRITE_2(sc, SELECT_RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR); 1467 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_R1), 1468 MSK_RI_TO_53); 1469 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XA1), 1470 MSK_RI_TO_53); 1471 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XS1), 1472 MSK_RI_TO_53); 1473 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_R1), 1474 MSK_RI_TO_53); 1475 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XA1), 1476 MSK_RI_TO_53); 1477 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XS1), 1478 MSK_RI_TO_53); 1479 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_R2), 1480 MSK_RI_TO_53); 1481 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XA2), 1482 MSK_RI_TO_53); 1483 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XS2), 1484 MSK_RI_TO_53); 1485 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_R2), 1486 MSK_RI_TO_53); 1487 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XA2), 1488 MSK_RI_TO_53); 1489 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XS2), 1490 MSK_RI_TO_53); 1491 } 1492 1493 /* Disable all interrupts. */ 1494 CSR_WRITE_4(sc, B0_HWE_IMSK, 0); 1495 CSR_READ_4(sc, B0_HWE_IMSK); 1496 CSR_WRITE_4(sc, B0_IMSK, 0); 1497 CSR_READ_4(sc, B0_IMSK); 1498 1499 /* 1500 * On dual port PCI-X card, there is an problem where status 1501 * can be received out of order due to split transactions. 1502 */ 1503 if (sc->msk_pcixcap != 0 && sc->msk_num_port > 1) { 1504 uint16_t pcix_cmd; 1505 1506 pcix_cmd = pci_read_config(sc->msk_dev, 1507 sc->msk_pcixcap + PCIXR_COMMAND, 2); 1508 /* Clear Max Outstanding Split Transactions. */ 1509 pcix_cmd &= ~PCIXM_COMMAND_MAX_SPLITS; 1510 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON); 1511 pci_write_config(sc->msk_dev, 1512 sc->msk_pcixcap + PCIXR_COMMAND, pcix_cmd, 2); 1513 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 1514 } 1515 if (sc->msk_expcap != 0) { 1516 /* Change Max. Read Request Size to 2048 bytes. */ 1517 if (pci_get_max_read_req(sc->msk_dev) == 512) 1518 pci_set_max_read_req(sc->msk_dev, 2048); 1519 } 1520 1521 /* Clear status list. */ 1522 bzero(sc->msk_stat_ring, 1523 sizeof(struct msk_stat_desc) * sc->msk_stat_count); 1524 sc->msk_stat_cons = 0; 1525 bus_dmamap_sync(sc->msk_stat_tag, sc->msk_stat_map, 1526 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1527 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_RST_SET); 1528 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_RST_CLR); 1529 /* Set the status list base address. */ 1530 addr = sc->msk_stat_ring_paddr; 1531 CSR_WRITE_4(sc, STAT_LIST_ADDR_LO, MSK_ADDR_LO(addr)); 1532 CSR_WRITE_4(sc, STAT_LIST_ADDR_HI, MSK_ADDR_HI(addr)); 1533 /* Set the status list last index. */ 1534 CSR_WRITE_2(sc, STAT_LAST_IDX, sc->msk_stat_count - 1); 1535 if (sc->msk_hw_id == CHIP_ID_YUKON_EC && 1536 sc->msk_hw_rev == CHIP_REV_YU_EC_A1) { 1537 /* WA for dev. #4.3 */ 1538 CSR_WRITE_2(sc, STAT_TX_IDX_TH, ST_TXTH_IDX_MASK); 1539 /* WA for dev. #4.18 */ 1540 CSR_WRITE_1(sc, STAT_FIFO_WM, 0x21); 1541 CSR_WRITE_1(sc, STAT_FIFO_ISR_WM, 0x07); 1542 } else { 1543 CSR_WRITE_2(sc, STAT_TX_IDX_TH, 0x0a); 1544 CSR_WRITE_1(sc, STAT_FIFO_WM, 0x10); 1545 if (sc->msk_hw_id == CHIP_ID_YUKON_XL && 1546 sc->msk_hw_rev == CHIP_REV_YU_XL_A0) 1547 CSR_WRITE_1(sc, STAT_FIFO_ISR_WM, 0x04); 1548 else 1549 CSR_WRITE_1(sc, STAT_FIFO_ISR_WM, 0x10); 1550 CSR_WRITE_4(sc, STAT_ISR_TIMER_INI, 0x0190); 1551 } 1552 /* 1553 * Use default value for STAT_ISR_TIMER_INI, STAT_LEV_TIMER_INI. 1554 */ 1555 CSR_WRITE_4(sc, STAT_TX_TIMER_INI, MSK_USECS(sc, 1000)); 1556 1557 /* Enable status unit. */ 1558 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_OP_ON); 1559 1560 CSR_WRITE_1(sc, STAT_TX_TIMER_CTRL, TIM_START); 1561 CSR_WRITE_1(sc, STAT_LEV_TIMER_CTRL, TIM_START); 1562 CSR_WRITE_1(sc, STAT_ISR_TIMER_CTRL, TIM_START); 1563 } 1564 1565 static int 1566 msk_probe(device_t dev) 1567 { 1568 struct msk_softc *sc; 1569 1570 sc = device_get_softc(device_get_parent(dev)); 1571 /* 1572 * Not much to do here. We always know there will be 1573 * at least one GMAC present, and if there are two, 1574 * mskc_attach() will create a second device instance 1575 * for us. 1576 */ 1577 device_set_descf(dev, 1578 "Marvell Technology Group Ltd. %s Id 0x%02x Rev 0x%02x", 1579 model_name[sc->msk_hw_id - CHIP_ID_YUKON_XL], sc->msk_hw_id, 1580 sc->msk_hw_rev); 1581 1582 return (BUS_PROBE_DEFAULT); 1583 } 1584 1585 static int 1586 msk_attach(device_t dev) 1587 { 1588 struct msk_softc *sc; 1589 struct msk_if_softc *sc_if; 1590 if_t ifp; 1591 struct msk_mii_data *mmd; 1592 int i, port, error; 1593 uint8_t eaddr[6]; 1594 1595 if (dev == NULL) 1596 return (EINVAL); 1597 1598 error = 0; 1599 sc_if = device_get_softc(dev); 1600 sc = device_get_softc(device_get_parent(dev)); 1601 mmd = device_get_ivars(dev); 1602 port = mmd->port; 1603 1604 sc_if->msk_if_dev = dev; 1605 sc_if->msk_port = port; 1606 sc_if->msk_softc = sc; 1607 sc_if->msk_flags = sc->msk_pflags; 1608 sc->msk_if[port] = sc_if; 1609 /* Setup Tx/Rx queue register offsets. */ 1610 if (port == MSK_PORT_A) { 1611 sc_if->msk_txq = Q_XA1; 1612 sc_if->msk_txsq = Q_XS1; 1613 sc_if->msk_rxq = Q_R1; 1614 } else { 1615 sc_if->msk_txq = Q_XA2; 1616 sc_if->msk_txsq = Q_XS2; 1617 sc_if->msk_rxq = Q_R2; 1618 } 1619 1620 callout_init_mtx(&sc_if->msk_tick_ch, &sc_if->msk_softc->msk_mtx, 0); 1621 msk_sysctl_node(sc_if); 1622 1623 if ((error = msk_txrx_dma_alloc(sc_if)) != 0) 1624 goto fail; 1625 msk_rx_dma_jalloc(sc_if); 1626 1627 ifp = sc_if->msk_ifp = if_alloc(IFT_ETHER); 1628 if_setsoftc(ifp, sc_if); 1629 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1630 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 1631 if_setcapabilities(ifp, IFCAP_TXCSUM | IFCAP_TSO4); 1632 /* 1633 * Enable Rx checksum offloading if controller supports 1634 * new descriptor formant and controller is not Yukon XL. 1635 */ 1636 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0 && 1637 sc->msk_hw_id != CHIP_ID_YUKON_XL) 1638 if_setcapabilitiesbit(ifp, IFCAP_RXCSUM, 0); 1639 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) != 0 && 1640 (sc_if->msk_flags & MSK_FLAG_NORX_CSUM) == 0) 1641 if_setcapabilitiesbit(ifp, IFCAP_RXCSUM, 0); 1642 if_sethwassist(ifp, MSK_CSUM_FEATURES | CSUM_TSO); 1643 if_setcapenable(ifp, if_getcapabilities(ifp)); 1644 if_setioctlfn(ifp, msk_ioctl); 1645 if_setstartfn(ifp, msk_start); 1646 if_setinitfn(ifp, msk_init); 1647 if_setsendqlen(ifp, MSK_TX_RING_CNT - 1); 1648 if_setsendqready(ifp); 1649 /* 1650 * Get station address for this interface. Note that 1651 * dual port cards actually come with three station 1652 * addresses: one for each port, plus an extra. The 1653 * extra one is used by the SysKonnect driver software 1654 * as a 'virtual' station address for when both ports 1655 * are operating in failover mode. Currently we don't 1656 * use this extra address. 1657 */ 1658 MSK_IF_LOCK(sc_if); 1659 for (i = 0; i < ETHER_ADDR_LEN; i++) 1660 eaddr[i] = CSR_READ_1(sc, B2_MAC_1 + (port * 8) + i); 1661 1662 /* 1663 * Call MI attach routine. Can't hold locks when calling into ether_*. 1664 */ 1665 MSK_IF_UNLOCK(sc_if); 1666 ether_ifattach(ifp, eaddr); 1667 MSK_IF_LOCK(sc_if); 1668 1669 /* VLAN capability setup */ 1670 if_setcapabilitiesbit(ifp, IFCAP_VLAN_MTU, 0); 1671 if ((sc_if->msk_flags & MSK_FLAG_NOHWVLAN) == 0) { 1672 /* 1673 * Due to Tx checksum offload hardware bugs, msk(4) manually 1674 * computes checksum for short frames. For VLAN tagged frames 1675 * this workaround does not work so disable checksum offload 1676 * for VLAN interface. 1677 */ 1678 if_setcapabilitiesbit(ifp, IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWTSO, 0); 1679 /* 1680 * Enable Rx checksum offloading for VLAN tagged frames 1681 * if controller support new descriptor format. 1682 */ 1683 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) != 0 && 1684 (sc_if->msk_flags & MSK_FLAG_NORX_CSUM) == 0) 1685 if_setcapabilitiesbit(ifp, IFCAP_VLAN_HWCSUM, 0); 1686 } 1687 if_setcapenable(ifp, if_getcapabilities(ifp)); 1688 /* 1689 * Disable RX checksum offloading on controllers that don't use 1690 * new descriptor format but give chance to enable it. 1691 */ 1692 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0) 1693 if_setcapenablebit(ifp, 0, IFCAP_RXCSUM); 1694 1695 /* 1696 * Tell the upper layer(s) we support long frames. 1697 * Must appear after the call to ether_ifattach() because 1698 * ether_ifattach() sets ifi_hdrlen to the default value. 1699 */ 1700 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 1701 1702 /* 1703 * Do miibus setup. 1704 */ 1705 MSK_IF_UNLOCK(sc_if); 1706 error = mii_attach(dev, &sc_if->msk_miibus, ifp, msk_mediachange, 1707 msk_mediastatus, BMSR_DEFCAPMASK, PHY_ADDR_MARV, MII_OFFSET_ANY, 1708 mmd->mii_flags); 1709 if (error != 0) { 1710 device_printf(sc_if->msk_if_dev, "attaching PHYs failed\n"); 1711 ether_ifdetach(ifp); 1712 error = ENXIO; 1713 goto fail; 1714 } 1715 1716 fail: 1717 if (error != 0) { 1718 /* Access should be ok even though lock has been dropped */ 1719 sc->msk_if[port] = NULL; 1720 msk_detach(dev); 1721 } 1722 1723 return (error); 1724 } 1725 1726 /* 1727 * Attach the interface. Allocate softc structures, do ifmedia 1728 * setup and ethernet/BPF attach. 1729 */ 1730 static int 1731 mskc_attach(device_t dev) 1732 { 1733 struct msk_softc *sc; 1734 struct msk_mii_data *mmd; 1735 int error, msic, msir, reg; 1736 1737 sc = device_get_softc(dev); 1738 sc->msk_dev = dev; 1739 mtx_init(&sc->msk_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1740 MTX_DEF); 1741 1742 /* 1743 * Map control/status registers. 1744 */ 1745 pci_enable_busmaster(dev); 1746 1747 /* Allocate I/O resource */ 1748 #ifdef MSK_USEIOSPACE 1749 sc->msk_res_spec = msk_res_spec_io; 1750 #else 1751 sc->msk_res_spec = msk_res_spec_mem; 1752 #endif 1753 sc->msk_irq_spec = msk_irq_spec_legacy; 1754 error = bus_alloc_resources(dev, sc->msk_res_spec, sc->msk_res); 1755 if (error) { 1756 if (sc->msk_res_spec == msk_res_spec_mem) 1757 sc->msk_res_spec = msk_res_spec_io; 1758 else 1759 sc->msk_res_spec = msk_res_spec_mem; 1760 error = bus_alloc_resources(dev, sc->msk_res_spec, sc->msk_res); 1761 if (error) { 1762 device_printf(dev, "couldn't allocate %s resources\n", 1763 sc->msk_res_spec == msk_res_spec_mem ? "memory" : 1764 "I/O"); 1765 mtx_destroy(&sc->msk_mtx); 1766 return (ENXIO); 1767 } 1768 } 1769 1770 /* Enable all clocks before accessing any registers. */ 1771 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_3, 0); 1772 1773 CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR); 1774 sc->msk_hw_id = CSR_READ_1(sc, B2_CHIP_ID); 1775 sc->msk_hw_rev = (CSR_READ_1(sc, B2_MAC_CFG) >> 4) & 0x0f; 1776 /* Bail out if chip is not recognized. */ 1777 if (sc->msk_hw_id < CHIP_ID_YUKON_XL || 1778 sc->msk_hw_id > CHIP_ID_YUKON_OPT || 1779 sc->msk_hw_id == CHIP_ID_YUKON_UNKNOWN) { 1780 device_printf(dev, "unknown device: id=0x%02x, rev=0x%02x\n", 1781 sc->msk_hw_id, sc->msk_hw_rev); 1782 mtx_destroy(&sc->msk_mtx); 1783 return (ENXIO); 1784 } 1785 1786 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 1787 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 1788 OID_AUTO, "process_limit", 1789 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 1790 &sc->msk_process_limit, 0, sysctl_hw_msk_proc_limit, "I", 1791 "max number of Rx events to process"); 1792 1793 sc->msk_process_limit = MSK_PROC_DEFAULT; 1794 error = resource_int_value(device_get_name(dev), device_get_unit(dev), 1795 "process_limit", &sc->msk_process_limit); 1796 if (error == 0) { 1797 if (sc->msk_process_limit < MSK_PROC_MIN || 1798 sc->msk_process_limit > MSK_PROC_MAX) { 1799 device_printf(dev, "process_limit value out of range; " 1800 "using default: %d\n", MSK_PROC_DEFAULT); 1801 sc->msk_process_limit = MSK_PROC_DEFAULT; 1802 } 1803 } 1804 1805 sc->msk_int_holdoff = MSK_INT_HOLDOFF_DEFAULT; 1806 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 1807 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 1808 "int_holdoff", CTLFLAG_RW, &sc->msk_int_holdoff, 0, 1809 "Maximum number of time to delay interrupts"); 1810 resource_int_value(device_get_name(dev), device_get_unit(dev), 1811 "int_holdoff", &sc->msk_int_holdoff); 1812 1813 sc->msk_pmd = CSR_READ_1(sc, B2_PMD_TYP); 1814 /* Check number of MACs. */ 1815 sc->msk_num_port = 1; 1816 if ((CSR_READ_1(sc, B2_Y2_HW_RES) & CFG_DUAL_MAC_MSK) == 1817 CFG_DUAL_MAC_MSK) { 1818 if (!(CSR_READ_1(sc, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC)) 1819 sc->msk_num_port++; 1820 } 1821 1822 /* Check bus type. */ 1823 if (pci_find_cap(sc->msk_dev, PCIY_EXPRESS, ®) == 0) { 1824 sc->msk_bustype = MSK_PEX_BUS; 1825 sc->msk_expcap = reg; 1826 } else if (pci_find_cap(sc->msk_dev, PCIY_PCIX, ®) == 0) { 1827 sc->msk_bustype = MSK_PCIX_BUS; 1828 sc->msk_pcixcap = reg; 1829 } else 1830 sc->msk_bustype = MSK_PCI_BUS; 1831 1832 switch (sc->msk_hw_id) { 1833 case CHIP_ID_YUKON_EC: 1834 sc->msk_clock = 125; /* 125 MHz */ 1835 sc->msk_pflags |= MSK_FLAG_JUMBO; 1836 break; 1837 case CHIP_ID_YUKON_EC_U: 1838 sc->msk_clock = 125; /* 125 MHz */ 1839 sc->msk_pflags |= MSK_FLAG_JUMBO | MSK_FLAG_JUMBO_NOCSUM; 1840 break; 1841 case CHIP_ID_YUKON_EX: 1842 sc->msk_clock = 125; /* 125 MHz */ 1843 sc->msk_pflags |= MSK_FLAG_JUMBO | MSK_FLAG_DESCV2 | 1844 MSK_FLAG_AUTOTX_CSUM; 1845 /* 1846 * Yukon Extreme seems to have silicon bug for 1847 * automatic Tx checksum calculation capability. 1848 */ 1849 if (sc->msk_hw_rev == CHIP_REV_YU_EX_B0) 1850 sc->msk_pflags &= ~MSK_FLAG_AUTOTX_CSUM; 1851 /* 1852 * Yukon Extreme A0 could not use store-and-forward 1853 * for jumbo frames, so disable Tx checksum 1854 * offloading for jumbo frames. 1855 */ 1856 if (sc->msk_hw_rev == CHIP_REV_YU_EX_A0) 1857 sc->msk_pflags |= MSK_FLAG_JUMBO_NOCSUM; 1858 break; 1859 case CHIP_ID_YUKON_FE: 1860 sc->msk_clock = 100; /* 100 MHz */ 1861 sc->msk_pflags |= MSK_FLAG_FASTETHER; 1862 break; 1863 case CHIP_ID_YUKON_FE_P: 1864 sc->msk_clock = 50; /* 50 MHz */ 1865 sc->msk_pflags |= MSK_FLAG_FASTETHER | MSK_FLAG_DESCV2 | 1866 MSK_FLAG_AUTOTX_CSUM; 1867 if (sc->msk_hw_rev == CHIP_REV_YU_FE_P_A0) { 1868 /* 1869 * XXX 1870 * FE+ A0 has status LE writeback bug so msk(4) 1871 * does not rely on status word of received frame 1872 * in msk_rxeof() which in turn disables all 1873 * hardware assistance bits reported by the status 1874 * word as well as validity of the received frame. 1875 * Just pass received frames to upper stack with 1876 * minimal test and let upper stack handle them. 1877 */ 1878 sc->msk_pflags |= MSK_FLAG_NOHWVLAN | 1879 MSK_FLAG_NORXCHK | MSK_FLAG_NORX_CSUM; 1880 } 1881 break; 1882 case CHIP_ID_YUKON_XL: 1883 sc->msk_clock = 156; /* 156 MHz */ 1884 sc->msk_pflags |= MSK_FLAG_JUMBO; 1885 break; 1886 case CHIP_ID_YUKON_SUPR: 1887 sc->msk_clock = 125; /* 125 MHz */ 1888 sc->msk_pflags |= MSK_FLAG_JUMBO | MSK_FLAG_DESCV2 | 1889 MSK_FLAG_AUTOTX_CSUM; 1890 break; 1891 case CHIP_ID_YUKON_UL_2: 1892 sc->msk_clock = 125; /* 125 MHz */ 1893 sc->msk_pflags |= MSK_FLAG_JUMBO; 1894 break; 1895 case CHIP_ID_YUKON_OPT: 1896 sc->msk_clock = 125; /* 125 MHz */ 1897 sc->msk_pflags |= MSK_FLAG_JUMBO | MSK_FLAG_DESCV2; 1898 break; 1899 default: 1900 sc->msk_clock = 156; /* 156 MHz */ 1901 break; 1902 } 1903 1904 /* Allocate IRQ resources. */ 1905 msic = pci_msi_count(dev); 1906 if (bootverbose) 1907 device_printf(dev, "MSI count : %d\n", msic); 1908 if (legacy_intr != 0) 1909 msi_disable = 1; 1910 if (msi_disable == 0 && msic > 0) { 1911 msir = 1; 1912 if (pci_alloc_msi(dev, &msir) == 0) { 1913 if (msir == 1) { 1914 sc->msk_pflags |= MSK_FLAG_MSI; 1915 sc->msk_irq_spec = msk_irq_spec_msi; 1916 } else 1917 pci_release_msi(dev); 1918 } 1919 } 1920 1921 error = bus_alloc_resources(dev, sc->msk_irq_spec, sc->msk_irq); 1922 if (error) { 1923 device_printf(dev, "couldn't allocate IRQ resources\n"); 1924 goto fail; 1925 } 1926 1927 if ((error = msk_status_dma_alloc(sc)) != 0) 1928 goto fail; 1929 1930 /* Set base interrupt mask. */ 1931 sc->msk_intrmask = Y2_IS_HW_ERR | Y2_IS_STAT_BMU; 1932 sc->msk_intrhwemask = Y2_IS_TIST_OV | Y2_IS_MST_ERR | 1933 Y2_IS_IRQ_STAT | Y2_IS_PCI_EXP | Y2_IS_PCI_NEXP; 1934 1935 /* Reset the adapter. */ 1936 mskc_reset(sc); 1937 1938 if ((error = mskc_setup_rambuffer(sc)) != 0) 1939 goto fail; 1940 1941 sc->msk_devs[MSK_PORT_A] = device_add_child(dev, "msk", DEVICE_UNIT_ANY); 1942 if (sc->msk_devs[MSK_PORT_A] == NULL) { 1943 device_printf(dev, "failed to add child for PORT_A\n"); 1944 error = ENXIO; 1945 goto fail; 1946 } 1947 mmd = malloc(sizeof(struct msk_mii_data), M_DEVBUF, M_WAITOK | M_ZERO); 1948 mmd->port = MSK_PORT_A; 1949 mmd->pmd = sc->msk_pmd; 1950 mmd->mii_flags |= MIIF_DOPAUSE; 1951 if (sc->msk_pmd == 'L' || sc->msk_pmd == 'S') 1952 mmd->mii_flags |= MIIF_HAVEFIBER; 1953 if (sc->msk_pmd == 'P') 1954 mmd->mii_flags |= MIIF_HAVEFIBER | MIIF_MACPRIV0; 1955 device_set_ivars(sc->msk_devs[MSK_PORT_A], mmd); 1956 1957 if (sc->msk_num_port > 1) { 1958 sc->msk_devs[MSK_PORT_B] = device_add_child(dev, "msk", DEVICE_UNIT_ANY); 1959 if (sc->msk_devs[MSK_PORT_B] == NULL) { 1960 device_printf(dev, "failed to add child for PORT_B\n"); 1961 error = ENXIO; 1962 goto fail; 1963 } 1964 mmd = malloc(sizeof(struct msk_mii_data), M_DEVBUF, M_WAITOK | 1965 M_ZERO); 1966 mmd->port = MSK_PORT_B; 1967 mmd->pmd = sc->msk_pmd; 1968 if (sc->msk_pmd == 'L' || sc->msk_pmd == 'S') 1969 mmd->mii_flags |= MIIF_HAVEFIBER; 1970 if (sc->msk_pmd == 'P') 1971 mmd->mii_flags |= MIIF_HAVEFIBER | MIIF_MACPRIV0; 1972 device_set_ivars(sc->msk_devs[MSK_PORT_B], mmd); 1973 } 1974 1975 bus_attach_children(dev); 1976 1977 /* Hook interrupt last to avoid having to lock softc. */ 1978 error = bus_setup_intr(dev, sc->msk_irq[0], INTR_TYPE_NET | 1979 INTR_MPSAFE, NULL, msk_intr, sc, &sc->msk_intrhand); 1980 if (error != 0) { 1981 device_printf(dev, "couldn't set up interrupt handler\n"); 1982 goto fail; 1983 } 1984 fail: 1985 if (error != 0) 1986 mskc_detach(dev); 1987 1988 return (error); 1989 } 1990 1991 /* 1992 * Shutdown hardware and free up resources. This can be called any 1993 * time after the mutex has been initialized. It is called in both 1994 * the error case in attach and the normal detach case so it needs 1995 * to be careful about only freeing resources that have actually been 1996 * allocated. 1997 */ 1998 static int 1999 msk_detach(device_t dev) 2000 { 2001 struct msk_softc *sc; 2002 struct msk_if_softc *sc_if; 2003 if_t ifp; 2004 2005 sc_if = device_get_softc(dev); 2006 KASSERT(mtx_initialized(&sc_if->msk_softc->msk_mtx), 2007 ("msk mutex not initialized in msk_detach")); 2008 MSK_IF_LOCK(sc_if); 2009 2010 ifp = sc_if->msk_ifp; 2011 if (device_is_attached(dev)) { 2012 /* XXX */ 2013 sc_if->msk_flags |= MSK_FLAG_DETACH; 2014 msk_stop(sc_if); 2015 /* Can't hold locks while calling detach. */ 2016 MSK_IF_UNLOCK(sc_if); 2017 callout_drain(&sc_if->msk_tick_ch); 2018 if (ifp) 2019 ether_ifdetach(ifp); 2020 MSK_IF_LOCK(sc_if); 2021 } 2022 2023 msk_rx_dma_jfree(sc_if); 2024 msk_txrx_dma_free(sc_if); 2025 bus_generic_detach(dev); 2026 2027 sc = sc_if->msk_softc; 2028 sc->msk_if[sc_if->msk_port] = NULL; 2029 MSK_IF_UNLOCK(sc_if); 2030 if (ifp) 2031 if_free(ifp); 2032 2033 return (0); 2034 } 2035 2036 static void 2037 mskc_child_deleted(device_t dev, device_t child) 2038 { 2039 free(device_get_ivars(child), M_DEVBUF); 2040 } 2041 2042 static int 2043 mskc_detach(device_t dev) 2044 { 2045 struct msk_softc *sc; 2046 2047 sc = device_get_softc(dev); 2048 KASSERT(mtx_initialized(&sc->msk_mtx), ("msk mutex not initialized")); 2049 2050 bus_generic_detach(dev); 2051 2052 /* Disable all interrupts. */ 2053 CSR_WRITE_4(sc, B0_IMSK, 0); 2054 CSR_READ_4(sc, B0_IMSK); 2055 CSR_WRITE_4(sc, B0_HWE_IMSK, 0); 2056 CSR_READ_4(sc, B0_HWE_IMSK); 2057 2058 /* LED Off. */ 2059 CSR_WRITE_2(sc, B0_CTST, Y2_LED_STAT_OFF); 2060 2061 /* Put hardware reset. */ 2062 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); 2063 2064 msk_status_dma_free(sc); 2065 2066 if (sc->msk_intrhand) { 2067 bus_teardown_intr(dev, sc->msk_irq[0], sc->msk_intrhand); 2068 sc->msk_intrhand = NULL; 2069 } 2070 bus_release_resources(dev, sc->msk_irq_spec, sc->msk_irq); 2071 if ((sc->msk_pflags & MSK_FLAG_MSI) != 0) 2072 pci_release_msi(dev); 2073 bus_release_resources(dev, sc->msk_res_spec, sc->msk_res); 2074 mtx_destroy(&sc->msk_mtx); 2075 2076 return (0); 2077 } 2078 2079 static bus_dma_tag_t 2080 mskc_get_dma_tag(device_t bus, device_t child __unused) 2081 { 2082 2083 return (bus_get_dma_tag(bus)); 2084 } 2085 2086 struct msk_dmamap_arg { 2087 bus_addr_t msk_busaddr; 2088 }; 2089 2090 static void 2091 msk_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 2092 { 2093 struct msk_dmamap_arg *ctx; 2094 2095 if (error != 0) 2096 return; 2097 ctx = arg; 2098 ctx->msk_busaddr = segs[0].ds_addr; 2099 } 2100 2101 /* Create status DMA region. */ 2102 static int 2103 msk_status_dma_alloc(struct msk_softc *sc) 2104 { 2105 struct msk_dmamap_arg ctx; 2106 bus_size_t stat_sz; 2107 int count, error; 2108 2109 /* 2110 * It seems controller requires number of status LE entries 2111 * is power of 2 and the maximum number of status LE entries 2112 * is 4096. For dual-port controllers, the number of status 2113 * LE entries should be large enough to hold both port's 2114 * status updates. 2115 */ 2116 count = 3 * MSK_RX_RING_CNT + MSK_TX_RING_CNT; 2117 count = imin(4096, roundup2(count, 1024)); 2118 sc->msk_stat_count = count; 2119 stat_sz = count * sizeof(struct msk_stat_desc); 2120 error = bus_dma_tag_create( 2121 bus_get_dma_tag(sc->msk_dev), /* parent */ 2122 MSK_STAT_ALIGN, 0, /* alignment, boundary */ 2123 BUS_SPACE_MAXADDR, /* lowaddr */ 2124 BUS_SPACE_MAXADDR, /* highaddr */ 2125 NULL, NULL, /* filter, filterarg */ 2126 stat_sz, /* maxsize */ 2127 1, /* nsegments */ 2128 stat_sz, /* maxsegsize */ 2129 0, /* flags */ 2130 NULL, NULL, /* lockfunc, lockarg */ 2131 &sc->msk_stat_tag); 2132 if (error != 0) { 2133 device_printf(sc->msk_dev, 2134 "failed to create status DMA tag\n"); 2135 return (error); 2136 } 2137 2138 /* Allocate DMA'able memory and load the DMA map for status ring. */ 2139 error = bus_dmamem_alloc(sc->msk_stat_tag, 2140 (void **)&sc->msk_stat_ring, BUS_DMA_WAITOK | BUS_DMA_COHERENT | 2141 BUS_DMA_ZERO, &sc->msk_stat_map); 2142 if (error != 0) { 2143 device_printf(sc->msk_dev, 2144 "failed to allocate DMA'able memory for status ring\n"); 2145 return (error); 2146 } 2147 2148 ctx.msk_busaddr = 0; 2149 error = bus_dmamap_load(sc->msk_stat_tag, sc->msk_stat_map, 2150 sc->msk_stat_ring, stat_sz, msk_dmamap_cb, &ctx, BUS_DMA_NOWAIT); 2151 if (error != 0) { 2152 device_printf(sc->msk_dev, 2153 "failed to load DMA'able memory for status ring\n"); 2154 return (error); 2155 } 2156 sc->msk_stat_ring_paddr = ctx.msk_busaddr; 2157 2158 return (0); 2159 } 2160 2161 static void 2162 msk_status_dma_free(struct msk_softc *sc) 2163 { 2164 2165 /* Destroy status block. */ 2166 if (sc->msk_stat_tag) { 2167 if (sc->msk_stat_ring_paddr) { 2168 bus_dmamap_unload(sc->msk_stat_tag, sc->msk_stat_map); 2169 sc->msk_stat_ring_paddr = 0; 2170 } 2171 if (sc->msk_stat_ring) { 2172 bus_dmamem_free(sc->msk_stat_tag, 2173 sc->msk_stat_ring, sc->msk_stat_map); 2174 sc->msk_stat_ring = NULL; 2175 } 2176 bus_dma_tag_destroy(sc->msk_stat_tag); 2177 sc->msk_stat_tag = NULL; 2178 } 2179 } 2180 2181 static int 2182 msk_txrx_dma_alloc(struct msk_if_softc *sc_if) 2183 { 2184 struct msk_dmamap_arg ctx; 2185 struct msk_txdesc *txd; 2186 struct msk_rxdesc *rxd; 2187 bus_size_t rxalign; 2188 int error, i; 2189 2190 /* Create parent DMA tag. */ 2191 error = bus_dma_tag_create( 2192 bus_get_dma_tag(sc_if->msk_if_dev), /* parent */ 2193 1, 0, /* alignment, boundary */ 2194 BUS_SPACE_MAXADDR, /* lowaddr */ 2195 BUS_SPACE_MAXADDR, /* highaddr */ 2196 NULL, NULL, /* filter, filterarg */ 2197 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 2198 0, /* nsegments */ 2199 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 2200 0, /* flags */ 2201 NULL, NULL, /* lockfunc, lockarg */ 2202 &sc_if->msk_cdata.msk_parent_tag); 2203 if (error != 0) { 2204 device_printf(sc_if->msk_if_dev, 2205 "failed to create parent DMA tag\n"); 2206 goto fail; 2207 } 2208 /* Create tag for Tx ring. */ 2209 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2210 MSK_RING_ALIGN, 0, /* alignment, boundary */ 2211 BUS_SPACE_MAXADDR, /* lowaddr */ 2212 BUS_SPACE_MAXADDR, /* highaddr */ 2213 NULL, NULL, /* filter, filterarg */ 2214 MSK_TX_RING_SZ, /* maxsize */ 2215 1, /* nsegments */ 2216 MSK_TX_RING_SZ, /* maxsegsize */ 2217 0, /* flags */ 2218 NULL, NULL, /* lockfunc, lockarg */ 2219 &sc_if->msk_cdata.msk_tx_ring_tag); 2220 if (error != 0) { 2221 device_printf(sc_if->msk_if_dev, 2222 "failed to create Tx ring DMA tag\n"); 2223 goto fail; 2224 } 2225 2226 /* Create tag for Rx ring. */ 2227 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2228 MSK_RING_ALIGN, 0, /* alignment, boundary */ 2229 BUS_SPACE_MAXADDR, /* lowaddr */ 2230 BUS_SPACE_MAXADDR, /* highaddr */ 2231 NULL, NULL, /* filter, filterarg */ 2232 MSK_RX_RING_SZ, /* maxsize */ 2233 1, /* nsegments */ 2234 MSK_RX_RING_SZ, /* maxsegsize */ 2235 0, /* flags */ 2236 NULL, NULL, /* lockfunc, lockarg */ 2237 &sc_if->msk_cdata.msk_rx_ring_tag); 2238 if (error != 0) { 2239 device_printf(sc_if->msk_if_dev, 2240 "failed to create Rx ring DMA tag\n"); 2241 goto fail; 2242 } 2243 2244 /* Create tag for Tx buffers. */ 2245 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2246 1, 0, /* alignment, boundary */ 2247 BUS_SPACE_MAXADDR, /* lowaddr */ 2248 BUS_SPACE_MAXADDR, /* highaddr */ 2249 NULL, NULL, /* filter, filterarg */ 2250 MSK_TSO_MAXSIZE, /* maxsize */ 2251 MSK_MAXTXSEGS, /* nsegments */ 2252 MSK_TSO_MAXSGSIZE, /* maxsegsize */ 2253 0, /* flags */ 2254 NULL, NULL, /* lockfunc, lockarg */ 2255 &sc_if->msk_cdata.msk_tx_tag); 2256 if (error != 0) { 2257 device_printf(sc_if->msk_if_dev, 2258 "failed to create Tx DMA tag\n"); 2259 goto fail; 2260 } 2261 2262 rxalign = 1; 2263 /* 2264 * Workaround hardware hang which seems to happen when Rx buffer 2265 * is not aligned on multiple of FIFO word(8 bytes). 2266 */ 2267 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) != 0) 2268 rxalign = MSK_RX_BUF_ALIGN; 2269 /* Create tag for Rx buffers. */ 2270 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2271 rxalign, 0, /* alignment, boundary */ 2272 BUS_SPACE_MAXADDR, /* lowaddr */ 2273 BUS_SPACE_MAXADDR, /* highaddr */ 2274 NULL, NULL, /* filter, filterarg */ 2275 MCLBYTES, /* maxsize */ 2276 1, /* nsegments */ 2277 MCLBYTES, /* maxsegsize */ 2278 0, /* flags */ 2279 NULL, NULL, /* lockfunc, lockarg */ 2280 &sc_if->msk_cdata.msk_rx_tag); 2281 if (error != 0) { 2282 device_printf(sc_if->msk_if_dev, 2283 "failed to create Rx DMA tag\n"); 2284 goto fail; 2285 } 2286 2287 /* Allocate DMA'able memory and load the DMA map for Tx ring. */ 2288 error = bus_dmamem_alloc(sc_if->msk_cdata.msk_tx_ring_tag, 2289 (void **)&sc_if->msk_rdata.msk_tx_ring, BUS_DMA_WAITOK | 2290 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc_if->msk_cdata.msk_tx_ring_map); 2291 if (error != 0) { 2292 device_printf(sc_if->msk_if_dev, 2293 "failed to allocate DMA'able memory for Tx ring\n"); 2294 goto fail; 2295 } 2296 2297 ctx.msk_busaddr = 0; 2298 error = bus_dmamap_load(sc_if->msk_cdata.msk_tx_ring_tag, 2299 sc_if->msk_cdata.msk_tx_ring_map, sc_if->msk_rdata.msk_tx_ring, 2300 MSK_TX_RING_SZ, msk_dmamap_cb, &ctx, BUS_DMA_NOWAIT); 2301 if (error != 0) { 2302 device_printf(sc_if->msk_if_dev, 2303 "failed to load DMA'able memory for Tx ring\n"); 2304 goto fail; 2305 } 2306 sc_if->msk_rdata.msk_tx_ring_paddr = ctx.msk_busaddr; 2307 2308 /* Allocate DMA'able memory and load the DMA map for Rx ring. */ 2309 error = bus_dmamem_alloc(sc_if->msk_cdata.msk_rx_ring_tag, 2310 (void **)&sc_if->msk_rdata.msk_rx_ring, BUS_DMA_WAITOK | 2311 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc_if->msk_cdata.msk_rx_ring_map); 2312 if (error != 0) { 2313 device_printf(sc_if->msk_if_dev, 2314 "failed to allocate DMA'able memory for Rx ring\n"); 2315 goto fail; 2316 } 2317 2318 ctx.msk_busaddr = 0; 2319 error = bus_dmamap_load(sc_if->msk_cdata.msk_rx_ring_tag, 2320 sc_if->msk_cdata.msk_rx_ring_map, sc_if->msk_rdata.msk_rx_ring, 2321 MSK_RX_RING_SZ, msk_dmamap_cb, &ctx, BUS_DMA_NOWAIT); 2322 if (error != 0) { 2323 device_printf(sc_if->msk_if_dev, 2324 "failed to load DMA'able memory for Rx ring\n"); 2325 goto fail; 2326 } 2327 sc_if->msk_rdata.msk_rx_ring_paddr = ctx.msk_busaddr; 2328 2329 /* Create DMA maps for Tx buffers. */ 2330 for (i = 0; i < MSK_TX_RING_CNT; i++) { 2331 txd = &sc_if->msk_cdata.msk_txdesc[i]; 2332 txd->tx_m = NULL; 2333 txd->tx_dmamap = NULL; 2334 error = bus_dmamap_create(sc_if->msk_cdata.msk_tx_tag, 0, 2335 &txd->tx_dmamap); 2336 if (error != 0) { 2337 device_printf(sc_if->msk_if_dev, 2338 "failed to create Tx dmamap\n"); 2339 goto fail; 2340 } 2341 } 2342 /* Create DMA maps for Rx buffers. */ 2343 if ((error = bus_dmamap_create(sc_if->msk_cdata.msk_rx_tag, 0, 2344 &sc_if->msk_cdata.msk_rx_sparemap)) != 0) { 2345 device_printf(sc_if->msk_if_dev, 2346 "failed to create spare Rx dmamap\n"); 2347 goto fail; 2348 } 2349 for (i = 0; i < MSK_RX_RING_CNT; i++) { 2350 rxd = &sc_if->msk_cdata.msk_rxdesc[i]; 2351 rxd->rx_m = NULL; 2352 rxd->rx_dmamap = NULL; 2353 error = bus_dmamap_create(sc_if->msk_cdata.msk_rx_tag, 0, 2354 &rxd->rx_dmamap); 2355 if (error != 0) { 2356 device_printf(sc_if->msk_if_dev, 2357 "failed to create Rx dmamap\n"); 2358 goto fail; 2359 } 2360 } 2361 2362 fail: 2363 return (error); 2364 } 2365 2366 static int 2367 msk_rx_dma_jalloc(struct msk_if_softc *sc_if) 2368 { 2369 struct msk_dmamap_arg ctx; 2370 struct msk_rxdesc *jrxd; 2371 bus_size_t rxalign; 2372 int error, i; 2373 2374 if (jumbo_disable != 0 || (sc_if->msk_flags & MSK_FLAG_JUMBO) == 0) { 2375 sc_if->msk_flags &= ~MSK_FLAG_JUMBO; 2376 device_printf(sc_if->msk_if_dev, 2377 "disabling jumbo frame support\n"); 2378 return (0); 2379 } 2380 /* Create tag for jumbo Rx ring. */ 2381 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2382 MSK_RING_ALIGN, 0, /* alignment, boundary */ 2383 BUS_SPACE_MAXADDR, /* lowaddr */ 2384 BUS_SPACE_MAXADDR, /* highaddr */ 2385 NULL, NULL, /* filter, filterarg */ 2386 MSK_JUMBO_RX_RING_SZ, /* maxsize */ 2387 1, /* nsegments */ 2388 MSK_JUMBO_RX_RING_SZ, /* maxsegsize */ 2389 0, /* flags */ 2390 NULL, NULL, /* lockfunc, lockarg */ 2391 &sc_if->msk_cdata.msk_jumbo_rx_ring_tag); 2392 if (error != 0) { 2393 device_printf(sc_if->msk_if_dev, 2394 "failed to create jumbo Rx ring DMA tag\n"); 2395 goto jumbo_fail; 2396 } 2397 2398 rxalign = 1; 2399 /* 2400 * Workaround hardware hang which seems to happen when Rx buffer 2401 * is not aligned on multiple of FIFO word(8 bytes). 2402 */ 2403 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) != 0) 2404 rxalign = MSK_RX_BUF_ALIGN; 2405 /* Create tag for jumbo Rx buffers. */ 2406 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2407 rxalign, 0, /* alignment, boundary */ 2408 BUS_SPACE_MAXADDR, /* lowaddr */ 2409 BUS_SPACE_MAXADDR, /* highaddr */ 2410 NULL, NULL, /* filter, filterarg */ 2411 MJUM9BYTES, /* maxsize */ 2412 1, /* nsegments */ 2413 MJUM9BYTES, /* maxsegsize */ 2414 0, /* flags */ 2415 NULL, NULL, /* lockfunc, lockarg */ 2416 &sc_if->msk_cdata.msk_jumbo_rx_tag); 2417 if (error != 0) { 2418 device_printf(sc_if->msk_if_dev, 2419 "failed to create jumbo Rx DMA tag\n"); 2420 goto jumbo_fail; 2421 } 2422 2423 /* Allocate DMA'able memory and load the DMA map for jumbo Rx ring. */ 2424 error = bus_dmamem_alloc(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 2425 (void **)&sc_if->msk_rdata.msk_jumbo_rx_ring, 2426 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 2427 &sc_if->msk_cdata.msk_jumbo_rx_ring_map); 2428 if (error != 0) { 2429 device_printf(sc_if->msk_if_dev, 2430 "failed to allocate DMA'able memory for jumbo Rx ring\n"); 2431 goto jumbo_fail; 2432 } 2433 2434 ctx.msk_busaddr = 0; 2435 error = bus_dmamap_load(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 2436 sc_if->msk_cdata.msk_jumbo_rx_ring_map, 2437 sc_if->msk_rdata.msk_jumbo_rx_ring, MSK_JUMBO_RX_RING_SZ, 2438 msk_dmamap_cb, &ctx, BUS_DMA_NOWAIT); 2439 if (error != 0) { 2440 device_printf(sc_if->msk_if_dev, 2441 "failed to load DMA'able memory for jumbo Rx ring\n"); 2442 goto jumbo_fail; 2443 } 2444 sc_if->msk_rdata.msk_jumbo_rx_ring_paddr = ctx.msk_busaddr; 2445 2446 /* Create DMA maps for jumbo Rx buffers. */ 2447 if ((error = bus_dmamap_create(sc_if->msk_cdata.msk_jumbo_rx_tag, 0, 2448 &sc_if->msk_cdata.msk_jumbo_rx_sparemap)) != 0) { 2449 device_printf(sc_if->msk_if_dev, 2450 "failed to create spare jumbo Rx dmamap\n"); 2451 goto jumbo_fail; 2452 } 2453 for (i = 0; i < MSK_JUMBO_RX_RING_CNT; i++) { 2454 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[i]; 2455 jrxd->rx_m = NULL; 2456 jrxd->rx_dmamap = NULL; 2457 error = bus_dmamap_create(sc_if->msk_cdata.msk_jumbo_rx_tag, 0, 2458 &jrxd->rx_dmamap); 2459 if (error != 0) { 2460 device_printf(sc_if->msk_if_dev, 2461 "failed to create jumbo Rx dmamap\n"); 2462 goto jumbo_fail; 2463 } 2464 } 2465 2466 return (0); 2467 2468 jumbo_fail: 2469 msk_rx_dma_jfree(sc_if); 2470 device_printf(sc_if->msk_if_dev, "disabling jumbo frame support " 2471 "due to resource shortage\n"); 2472 sc_if->msk_flags &= ~MSK_FLAG_JUMBO; 2473 return (error); 2474 } 2475 2476 static void 2477 msk_txrx_dma_free(struct msk_if_softc *sc_if) 2478 { 2479 struct msk_txdesc *txd; 2480 struct msk_rxdesc *rxd; 2481 int i; 2482 2483 /* Tx ring. */ 2484 if (sc_if->msk_cdata.msk_tx_ring_tag) { 2485 if (sc_if->msk_rdata.msk_tx_ring_paddr) 2486 bus_dmamap_unload(sc_if->msk_cdata.msk_tx_ring_tag, 2487 sc_if->msk_cdata.msk_tx_ring_map); 2488 if (sc_if->msk_rdata.msk_tx_ring) 2489 bus_dmamem_free(sc_if->msk_cdata.msk_tx_ring_tag, 2490 sc_if->msk_rdata.msk_tx_ring, 2491 sc_if->msk_cdata.msk_tx_ring_map); 2492 sc_if->msk_rdata.msk_tx_ring = NULL; 2493 sc_if->msk_rdata.msk_tx_ring_paddr = 0; 2494 bus_dma_tag_destroy(sc_if->msk_cdata.msk_tx_ring_tag); 2495 sc_if->msk_cdata.msk_tx_ring_tag = NULL; 2496 } 2497 /* Rx ring. */ 2498 if (sc_if->msk_cdata.msk_rx_ring_tag) { 2499 if (sc_if->msk_rdata.msk_rx_ring_paddr) 2500 bus_dmamap_unload(sc_if->msk_cdata.msk_rx_ring_tag, 2501 sc_if->msk_cdata.msk_rx_ring_map); 2502 if (sc_if->msk_rdata.msk_rx_ring) 2503 bus_dmamem_free(sc_if->msk_cdata.msk_rx_ring_tag, 2504 sc_if->msk_rdata.msk_rx_ring, 2505 sc_if->msk_cdata.msk_rx_ring_map); 2506 sc_if->msk_rdata.msk_rx_ring = NULL; 2507 sc_if->msk_rdata.msk_rx_ring_paddr = 0; 2508 bus_dma_tag_destroy(sc_if->msk_cdata.msk_rx_ring_tag); 2509 sc_if->msk_cdata.msk_rx_ring_tag = NULL; 2510 } 2511 /* Tx buffers. */ 2512 if (sc_if->msk_cdata.msk_tx_tag) { 2513 for (i = 0; i < MSK_TX_RING_CNT; i++) { 2514 txd = &sc_if->msk_cdata.msk_txdesc[i]; 2515 if (txd->tx_dmamap) { 2516 bus_dmamap_destroy(sc_if->msk_cdata.msk_tx_tag, 2517 txd->tx_dmamap); 2518 txd->tx_dmamap = NULL; 2519 } 2520 } 2521 bus_dma_tag_destroy(sc_if->msk_cdata.msk_tx_tag); 2522 sc_if->msk_cdata.msk_tx_tag = NULL; 2523 } 2524 /* Rx buffers. */ 2525 if (sc_if->msk_cdata.msk_rx_tag) { 2526 for (i = 0; i < MSK_RX_RING_CNT; i++) { 2527 rxd = &sc_if->msk_cdata.msk_rxdesc[i]; 2528 if (rxd->rx_dmamap) { 2529 bus_dmamap_destroy(sc_if->msk_cdata.msk_rx_tag, 2530 rxd->rx_dmamap); 2531 rxd->rx_dmamap = NULL; 2532 } 2533 } 2534 if (sc_if->msk_cdata.msk_rx_sparemap) { 2535 bus_dmamap_destroy(sc_if->msk_cdata.msk_rx_tag, 2536 sc_if->msk_cdata.msk_rx_sparemap); 2537 sc_if->msk_cdata.msk_rx_sparemap = 0; 2538 } 2539 bus_dma_tag_destroy(sc_if->msk_cdata.msk_rx_tag); 2540 sc_if->msk_cdata.msk_rx_tag = NULL; 2541 } 2542 if (sc_if->msk_cdata.msk_parent_tag) { 2543 bus_dma_tag_destroy(sc_if->msk_cdata.msk_parent_tag); 2544 sc_if->msk_cdata.msk_parent_tag = NULL; 2545 } 2546 } 2547 2548 static void 2549 msk_rx_dma_jfree(struct msk_if_softc *sc_if) 2550 { 2551 struct msk_rxdesc *jrxd; 2552 int i; 2553 2554 /* Jumbo Rx ring. */ 2555 if (sc_if->msk_cdata.msk_jumbo_rx_ring_tag) { 2556 if (sc_if->msk_rdata.msk_jumbo_rx_ring_paddr) 2557 bus_dmamap_unload(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 2558 sc_if->msk_cdata.msk_jumbo_rx_ring_map); 2559 if (sc_if->msk_rdata.msk_jumbo_rx_ring) 2560 bus_dmamem_free(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 2561 sc_if->msk_rdata.msk_jumbo_rx_ring, 2562 sc_if->msk_cdata.msk_jumbo_rx_ring_map); 2563 sc_if->msk_rdata.msk_jumbo_rx_ring = NULL; 2564 sc_if->msk_rdata.msk_jumbo_rx_ring_paddr = 0; 2565 bus_dma_tag_destroy(sc_if->msk_cdata.msk_jumbo_rx_ring_tag); 2566 sc_if->msk_cdata.msk_jumbo_rx_ring_tag = NULL; 2567 } 2568 /* Jumbo Rx buffers. */ 2569 if (sc_if->msk_cdata.msk_jumbo_rx_tag) { 2570 for (i = 0; i < MSK_JUMBO_RX_RING_CNT; i++) { 2571 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[i]; 2572 if (jrxd->rx_dmamap) { 2573 bus_dmamap_destroy( 2574 sc_if->msk_cdata.msk_jumbo_rx_tag, 2575 jrxd->rx_dmamap); 2576 jrxd->rx_dmamap = NULL; 2577 } 2578 } 2579 if (sc_if->msk_cdata.msk_jumbo_rx_sparemap) { 2580 bus_dmamap_destroy(sc_if->msk_cdata.msk_jumbo_rx_tag, 2581 sc_if->msk_cdata.msk_jumbo_rx_sparemap); 2582 sc_if->msk_cdata.msk_jumbo_rx_sparemap = 0; 2583 } 2584 bus_dma_tag_destroy(sc_if->msk_cdata.msk_jumbo_rx_tag); 2585 sc_if->msk_cdata.msk_jumbo_rx_tag = NULL; 2586 } 2587 } 2588 2589 static int 2590 msk_encap(struct msk_if_softc *sc_if, struct mbuf **m_head) 2591 { 2592 struct msk_txdesc *txd, *txd_last; 2593 struct msk_tx_desc *tx_le; 2594 struct mbuf *m; 2595 bus_dmamap_t map; 2596 bus_dma_segment_t txsegs[MSK_MAXTXSEGS]; 2597 uint32_t control, csum, prod, si; 2598 uint16_t offset, tcp_offset, tso_mtu; 2599 int error, i, nseg, tso; 2600 2601 MSK_IF_LOCK_ASSERT(sc_if); 2602 2603 tcp_offset = offset = 0; 2604 m = *m_head; 2605 if (((sc_if->msk_flags & MSK_FLAG_AUTOTX_CSUM) == 0 && 2606 (m->m_pkthdr.csum_flags & MSK_CSUM_FEATURES) != 0) || 2607 ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0 && 2608 (m->m_pkthdr.csum_flags & CSUM_TSO) != 0)) { 2609 /* 2610 * Since mbuf has no protocol specific structure information 2611 * in it we have to inspect protocol information here to 2612 * setup TSO and checksum offload. I don't know why Marvell 2613 * made a such decision in chip design because other GigE 2614 * hardwares normally takes care of all these chores in 2615 * hardware. However, TSO performance of Yukon II is very 2616 * good such that it's worth to implement it. 2617 */ 2618 struct ether_header *eh; 2619 struct ip *ip; 2620 struct tcphdr *tcp; 2621 2622 if (M_WRITABLE(m) == 0) { 2623 /* Get a writable copy. */ 2624 m = m_dup(*m_head, M_NOWAIT); 2625 m_freem(*m_head); 2626 if (m == NULL) { 2627 *m_head = NULL; 2628 return (ENOBUFS); 2629 } 2630 *m_head = m; 2631 } 2632 2633 offset = sizeof(struct ether_header); 2634 m = m_pullup(m, offset); 2635 if (m == NULL) { 2636 *m_head = NULL; 2637 return (ENOBUFS); 2638 } 2639 eh = mtod(m, struct ether_header *); 2640 /* Check if hardware VLAN insertion is off. */ 2641 if (eh->ether_type == htons(ETHERTYPE_VLAN)) { 2642 offset = sizeof(struct ether_vlan_header); 2643 m = m_pullup(m, offset); 2644 if (m == NULL) { 2645 *m_head = NULL; 2646 return (ENOBUFS); 2647 } 2648 } 2649 m = m_pullup(m, offset + sizeof(struct ip)); 2650 if (m == NULL) { 2651 *m_head = NULL; 2652 return (ENOBUFS); 2653 } 2654 ip = (struct ip *)(mtod(m, char *) + offset); 2655 offset += (ip->ip_hl << 2); 2656 tcp_offset = offset; 2657 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 2658 m = m_pullup(m, offset + sizeof(struct tcphdr)); 2659 if (m == NULL) { 2660 *m_head = NULL; 2661 return (ENOBUFS); 2662 } 2663 tcp = (struct tcphdr *)(mtod(m, char *) + offset); 2664 offset += (tcp->th_off << 2); 2665 } else if ((sc_if->msk_flags & MSK_FLAG_AUTOTX_CSUM) == 0 && 2666 (m->m_pkthdr.len < MSK_MIN_FRAMELEN) && 2667 (m->m_pkthdr.csum_flags & CSUM_TCP) != 0) { 2668 /* 2669 * It seems that Yukon II has Tx checksum offload bug 2670 * for small TCP packets that's less than 60 bytes in 2671 * size (e.g. TCP window probe packet, pure ACK packet). 2672 * Common work around like padding with zeros to make 2673 * the frame minimum ethernet frame size didn't work at 2674 * all. 2675 * Instead of disabling checksum offload completely we 2676 * resort to S/W checksum routine when we encounter 2677 * short TCP frames. 2678 * Short UDP packets appear to be handled correctly by 2679 * Yukon II. Also I assume this bug does not happen on 2680 * controllers that use newer descriptor format or 2681 * automatic Tx checksum calculation. 2682 */ 2683 m = m_pullup(m, offset + sizeof(struct tcphdr)); 2684 if (m == NULL) { 2685 *m_head = NULL; 2686 return (ENOBUFS); 2687 } 2688 *(uint16_t *)(m->m_data + offset + 2689 m->m_pkthdr.csum_data) = in_cksum_skip(m, 2690 m->m_pkthdr.len, offset); 2691 m->m_pkthdr.csum_flags &= ~CSUM_TCP; 2692 } 2693 *m_head = m; 2694 } 2695 2696 prod = sc_if->msk_cdata.msk_tx_prod; 2697 txd = &sc_if->msk_cdata.msk_txdesc[prod]; 2698 txd_last = txd; 2699 map = txd->tx_dmamap; 2700 error = bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_tx_tag, map, 2701 *m_head, txsegs, &nseg, BUS_DMA_NOWAIT); 2702 if (error == EFBIG) { 2703 m = m_collapse(*m_head, M_NOWAIT, MSK_MAXTXSEGS); 2704 if (m == NULL) { 2705 m_freem(*m_head); 2706 *m_head = NULL; 2707 return (ENOBUFS); 2708 } 2709 *m_head = m; 2710 error = bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_tx_tag, 2711 map, *m_head, txsegs, &nseg, BUS_DMA_NOWAIT); 2712 if (error != 0) { 2713 m_freem(*m_head); 2714 *m_head = NULL; 2715 return (error); 2716 } 2717 } else if (error != 0) 2718 return (error); 2719 if (nseg == 0) { 2720 m_freem(*m_head); 2721 *m_head = NULL; 2722 return (EIO); 2723 } 2724 2725 /* Check number of available descriptors. */ 2726 if (sc_if->msk_cdata.msk_tx_cnt + nseg >= 2727 (MSK_TX_RING_CNT - MSK_RESERVED_TX_DESC_CNT)) { 2728 bus_dmamap_unload(sc_if->msk_cdata.msk_tx_tag, map); 2729 return (ENOBUFS); 2730 } 2731 2732 control = 0; 2733 tso = 0; 2734 tx_le = NULL; 2735 2736 /* Check TSO support. */ 2737 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 2738 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) != 0) 2739 tso_mtu = m->m_pkthdr.tso_segsz; 2740 else 2741 tso_mtu = offset + m->m_pkthdr.tso_segsz; 2742 if (tso_mtu != sc_if->msk_cdata.msk_tso_mtu) { 2743 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2744 tx_le->msk_addr = htole32(tso_mtu); 2745 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) != 0) 2746 tx_le->msk_control = htole32(OP_MSS | HW_OWNER); 2747 else 2748 tx_le->msk_control = 2749 htole32(OP_LRGLEN | HW_OWNER); 2750 sc_if->msk_cdata.msk_tx_cnt++; 2751 MSK_INC(prod, MSK_TX_RING_CNT); 2752 sc_if->msk_cdata.msk_tso_mtu = tso_mtu; 2753 } 2754 tso++; 2755 } 2756 /* Check if we have a VLAN tag to insert. */ 2757 if ((m->m_flags & M_VLANTAG) != 0) { 2758 if (tx_le == NULL) { 2759 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2760 tx_le->msk_addr = htole32(0); 2761 tx_le->msk_control = htole32(OP_VLAN | HW_OWNER | 2762 htons(m->m_pkthdr.ether_vtag)); 2763 sc_if->msk_cdata.msk_tx_cnt++; 2764 MSK_INC(prod, MSK_TX_RING_CNT); 2765 } else { 2766 tx_le->msk_control |= htole32(OP_VLAN | 2767 htons(m->m_pkthdr.ether_vtag)); 2768 } 2769 control |= INS_VLAN; 2770 } 2771 /* Check if we have to handle checksum offload. */ 2772 if (tso == 0 && (m->m_pkthdr.csum_flags & MSK_CSUM_FEATURES) != 0) { 2773 if ((sc_if->msk_flags & MSK_FLAG_AUTOTX_CSUM) != 0) 2774 control |= CALSUM; 2775 else { 2776 control |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM; 2777 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0) 2778 control |= UDPTCP; 2779 /* Checksum write position. */ 2780 csum = (tcp_offset + m->m_pkthdr.csum_data) & 0xffff; 2781 /* Checksum start position. */ 2782 csum |= (uint32_t)tcp_offset << 16; 2783 if (csum != sc_if->msk_cdata.msk_last_csum) { 2784 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2785 tx_le->msk_addr = htole32(csum); 2786 tx_le->msk_control = htole32(1 << 16 | 2787 (OP_TCPLISW | HW_OWNER)); 2788 sc_if->msk_cdata.msk_tx_cnt++; 2789 MSK_INC(prod, MSK_TX_RING_CNT); 2790 sc_if->msk_cdata.msk_last_csum = csum; 2791 } 2792 } 2793 } 2794 2795 #ifdef MSK_64BIT_DMA 2796 if (MSK_ADDR_HI(txsegs[0].ds_addr) != 2797 sc_if->msk_cdata.msk_tx_high_addr) { 2798 sc_if->msk_cdata.msk_tx_high_addr = 2799 MSK_ADDR_HI(txsegs[0].ds_addr); 2800 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2801 tx_le->msk_addr = htole32(MSK_ADDR_HI(txsegs[0].ds_addr)); 2802 tx_le->msk_control = htole32(OP_ADDR64 | HW_OWNER); 2803 sc_if->msk_cdata.msk_tx_cnt++; 2804 MSK_INC(prod, MSK_TX_RING_CNT); 2805 } 2806 #endif 2807 si = prod; 2808 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2809 tx_le->msk_addr = htole32(MSK_ADDR_LO(txsegs[0].ds_addr)); 2810 if (tso == 0) 2811 tx_le->msk_control = htole32(txsegs[0].ds_len | control | 2812 OP_PACKET); 2813 else 2814 tx_le->msk_control = htole32(txsegs[0].ds_len | control | 2815 OP_LARGESEND); 2816 sc_if->msk_cdata.msk_tx_cnt++; 2817 MSK_INC(prod, MSK_TX_RING_CNT); 2818 2819 for (i = 1; i < nseg; i++) { 2820 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2821 #ifdef MSK_64BIT_DMA 2822 if (MSK_ADDR_HI(txsegs[i].ds_addr) != 2823 sc_if->msk_cdata.msk_tx_high_addr) { 2824 sc_if->msk_cdata.msk_tx_high_addr = 2825 MSK_ADDR_HI(txsegs[i].ds_addr); 2826 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2827 tx_le->msk_addr = 2828 htole32(MSK_ADDR_HI(txsegs[i].ds_addr)); 2829 tx_le->msk_control = htole32(OP_ADDR64 | HW_OWNER); 2830 sc_if->msk_cdata.msk_tx_cnt++; 2831 MSK_INC(prod, MSK_TX_RING_CNT); 2832 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2833 } 2834 #endif 2835 tx_le->msk_addr = htole32(MSK_ADDR_LO(txsegs[i].ds_addr)); 2836 tx_le->msk_control = htole32(txsegs[i].ds_len | control | 2837 OP_BUFFER | HW_OWNER); 2838 sc_if->msk_cdata.msk_tx_cnt++; 2839 MSK_INC(prod, MSK_TX_RING_CNT); 2840 } 2841 /* Update producer index. */ 2842 sc_if->msk_cdata.msk_tx_prod = prod; 2843 2844 /* Set EOP on the last descriptor. */ 2845 prod = (prod + MSK_TX_RING_CNT - 1) % MSK_TX_RING_CNT; 2846 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2847 tx_le->msk_control |= htole32(EOP); 2848 2849 /* Turn the first descriptor ownership to hardware. */ 2850 tx_le = &sc_if->msk_rdata.msk_tx_ring[si]; 2851 tx_le->msk_control |= htole32(HW_OWNER); 2852 2853 txd = &sc_if->msk_cdata.msk_txdesc[prod]; 2854 map = txd_last->tx_dmamap; 2855 txd_last->tx_dmamap = txd->tx_dmamap; 2856 txd->tx_dmamap = map; 2857 txd->tx_m = m; 2858 2859 /* Sync descriptors. */ 2860 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_tag, map, BUS_DMASYNC_PREWRITE); 2861 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_ring_tag, 2862 sc_if->msk_cdata.msk_tx_ring_map, 2863 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2864 2865 return (0); 2866 } 2867 2868 static void 2869 msk_start(if_t ifp) 2870 { 2871 struct msk_if_softc *sc_if; 2872 2873 sc_if = if_getsoftc(ifp); 2874 MSK_IF_LOCK(sc_if); 2875 msk_start_locked(ifp); 2876 MSK_IF_UNLOCK(sc_if); 2877 } 2878 2879 static void 2880 msk_start_locked(if_t ifp) 2881 { 2882 struct msk_if_softc *sc_if; 2883 struct mbuf *m_head; 2884 int enq; 2885 2886 sc_if = if_getsoftc(ifp); 2887 MSK_IF_LOCK_ASSERT(sc_if); 2888 2889 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2890 IFF_DRV_RUNNING || (sc_if->msk_flags & MSK_FLAG_LINK) == 0) 2891 return; 2892 2893 for (enq = 0; !if_sendq_empty(ifp) && 2894 sc_if->msk_cdata.msk_tx_cnt < 2895 (MSK_TX_RING_CNT - MSK_RESERVED_TX_DESC_CNT); ) { 2896 m_head = if_dequeue(ifp); 2897 if (m_head == NULL) 2898 break; 2899 /* 2900 * Pack the data into the transmit ring. If we 2901 * don't have room, set the OACTIVE flag and wait 2902 * for the NIC to drain the ring. 2903 */ 2904 if (msk_encap(sc_if, &m_head) != 0) { 2905 if (m_head == NULL) 2906 break; 2907 if_sendq_prepend(ifp, m_head); 2908 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); 2909 break; 2910 } 2911 2912 enq++; 2913 /* 2914 * If there's a BPF listener, bounce a copy of this frame 2915 * to him. 2916 */ 2917 ETHER_BPF_MTAP(ifp, m_head); 2918 } 2919 2920 if (enq > 0) { 2921 /* Transmit */ 2922 CSR_WRITE_2(sc_if->msk_softc, 2923 Y2_PREF_Q_ADDR(sc_if->msk_txq, PREF_UNIT_PUT_IDX_REG), 2924 sc_if->msk_cdata.msk_tx_prod); 2925 2926 /* Set a timeout in case the chip goes out to lunch. */ 2927 sc_if->msk_watchdog_timer = MSK_TX_TIMEOUT; 2928 } 2929 } 2930 2931 static void 2932 msk_watchdog(struct msk_if_softc *sc_if) 2933 { 2934 if_t ifp; 2935 2936 MSK_IF_LOCK_ASSERT(sc_if); 2937 2938 if (sc_if->msk_watchdog_timer == 0 || --sc_if->msk_watchdog_timer) 2939 return; 2940 ifp = sc_if->msk_ifp; 2941 if ((sc_if->msk_flags & MSK_FLAG_LINK) == 0) { 2942 if (bootverbose) 2943 if_printf(sc_if->msk_ifp, "watchdog timeout " 2944 "(missed link)\n"); 2945 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 2946 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 2947 msk_init_locked(sc_if); 2948 return; 2949 } 2950 2951 if_printf(ifp, "watchdog timeout\n"); 2952 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 2953 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 2954 msk_init_locked(sc_if); 2955 if (!if_sendq_empty(ifp)) 2956 msk_start_locked(ifp); 2957 } 2958 2959 static int 2960 mskc_shutdown(device_t dev) 2961 { 2962 struct msk_softc *sc; 2963 int i; 2964 2965 sc = device_get_softc(dev); 2966 MSK_LOCK(sc); 2967 for (i = 0; i < sc->msk_num_port; i++) { 2968 if (sc->msk_if[i] != NULL && sc->msk_if[i]->msk_ifp != NULL && 2969 ((if_getdrvflags(sc->msk_if[i]->msk_ifp) & 2970 IFF_DRV_RUNNING) != 0)) 2971 msk_stop(sc->msk_if[i]); 2972 } 2973 MSK_UNLOCK(sc); 2974 2975 /* Put hardware reset. */ 2976 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); 2977 return (0); 2978 } 2979 2980 static int 2981 mskc_suspend(device_t dev) 2982 { 2983 struct msk_softc *sc; 2984 int i; 2985 2986 sc = device_get_softc(dev); 2987 2988 MSK_LOCK(sc); 2989 2990 for (i = 0; i < sc->msk_num_port; i++) { 2991 if (sc->msk_if[i] != NULL && sc->msk_if[i]->msk_ifp != NULL && 2992 ((if_getdrvflags(sc->msk_if[i]->msk_ifp) & 2993 IFF_DRV_RUNNING) != 0)) 2994 msk_stop(sc->msk_if[i]); 2995 } 2996 2997 /* Disable all interrupts. */ 2998 CSR_WRITE_4(sc, B0_IMSK, 0); 2999 CSR_READ_4(sc, B0_IMSK); 3000 CSR_WRITE_4(sc, B0_HWE_IMSK, 0); 3001 CSR_READ_4(sc, B0_HWE_IMSK); 3002 3003 msk_phy_power(sc, MSK_PHY_POWERDOWN); 3004 3005 /* Put hardware reset. */ 3006 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); 3007 sc->msk_pflags |= MSK_FLAG_SUSPEND; 3008 3009 MSK_UNLOCK(sc); 3010 3011 return (0); 3012 } 3013 3014 static int 3015 mskc_resume(device_t dev) 3016 { 3017 struct msk_softc *sc; 3018 int i; 3019 3020 sc = device_get_softc(dev); 3021 3022 MSK_LOCK(sc); 3023 3024 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_3, 0); 3025 mskc_reset(sc); 3026 for (i = 0; i < sc->msk_num_port; i++) { 3027 if (sc->msk_if[i] != NULL && sc->msk_if[i]->msk_ifp != NULL && 3028 ((if_getflags(sc->msk_if[i]->msk_ifp) & IFF_UP) != 0)) { 3029 if_setdrvflagbits(sc->msk_if[i]->msk_ifp, 0, 3030 IFF_DRV_RUNNING); 3031 msk_init_locked(sc->msk_if[i]); 3032 } 3033 } 3034 sc->msk_pflags &= ~MSK_FLAG_SUSPEND; 3035 3036 MSK_UNLOCK(sc); 3037 3038 return (0); 3039 } 3040 3041 #ifndef __NO_STRICT_ALIGNMENT 3042 static __inline void 3043 msk_fixup_rx(struct mbuf *m) 3044 { 3045 int i; 3046 uint16_t *src, *dst; 3047 3048 src = mtod(m, uint16_t *); 3049 dst = src - 3; 3050 3051 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 3052 *dst++ = *src++; 3053 3054 m->m_data -= (MSK_RX_BUF_ALIGN - ETHER_ALIGN); 3055 } 3056 #endif 3057 3058 static __inline void 3059 msk_rxcsum(struct msk_if_softc *sc_if, uint32_t control, struct mbuf *m) 3060 { 3061 struct ether_header *eh; 3062 struct ip *ip; 3063 struct udphdr *uh; 3064 int32_t hlen, len, pktlen, temp32; 3065 uint16_t csum, *opts; 3066 3067 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) != 0) { 3068 if ((control & (CSS_IPV4 | CSS_IPFRAG)) == CSS_IPV4) { 3069 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 3070 if ((control & CSS_IPV4_CSUM_OK) != 0) 3071 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 3072 if ((control & (CSS_TCP | CSS_UDP)) != 0 && 3073 (control & (CSS_TCPUDP_CSUM_OK)) != 0) { 3074 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID | 3075 CSUM_PSEUDO_HDR; 3076 m->m_pkthdr.csum_data = 0xffff; 3077 } 3078 } 3079 return; 3080 } 3081 /* 3082 * Marvell Yukon controllers that support OP_RXCHKS has known 3083 * to have various Rx checksum offloading bugs. These 3084 * controllers can be configured to compute simple checksum 3085 * at two different positions. So we can compute IP and TCP/UDP 3086 * checksum at the same time. We intentionally have controller 3087 * compute TCP/UDP checksum twice by specifying the same 3088 * checksum start position and compare the result. If the value 3089 * is different it would indicate the hardware logic was wrong. 3090 */ 3091 if ((sc_if->msk_csum & 0xFFFF) != (sc_if->msk_csum >> 16)) { 3092 if (bootverbose) 3093 device_printf(sc_if->msk_if_dev, 3094 "Rx checksum value mismatch!\n"); 3095 return; 3096 } 3097 pktlen = m->m_pkthdr.len; 3098 if (pktlen < sizeof(struct ether_header) + sizeof(struct ip)) 3099 return; 3100 eh = mtod(m, struct ether_header *); 3101 if (eh->ether_type != htons(ETHERTYPE_IP)) 3102 return; 3103 ip = (struct ip *)(eh + 1); 3104 if (ip->ip_v != IPVERSION) 3105 return; 3106 3107 hlen = ip->ip_hl << 2; 3108 pktlen -= sizeof(struct ether_header); 3109 if (hlen < sizeof(struct ip)) 3110 return; 3111 if (ntohs(ip->ip_len) < hlen) 3112 return; 3113 if (ntohs(ip->ip_len) != pktlen) 3114 return; 3115 if (ip->ip_off & htons(IP_MF | IP_OFFMASK)) 3116 return; /* can't handle fragmented packet. */ 3117 3118 switch (ip->ip_p) { 3119 case IPPROTO_TCP: 3120 if (pktlen < (hlen + sizeof(struct tcphdr))) 3121 return; 3122 break; 3123 case IPPROTO_UDP: 3124 if (pktlen < (hlen + sizeof(struct udphdr))) 3125 return; 3126 uh = (struct udphdr *)((caddr_t)ip + hlen); 3127 if (uh->uh_sum == 0) 3128 return; /* no checksum */ 3129 break; 3130 default: 3131 return; 3132 } 3133 csum = bswap16(sc_if->msk_csum & 0xFFFF); 3134 /* Checksum fixup for IP options. */ 3135 len = hlen - sizeof(struct ip); 3136 if (len > 0) { 3137 opts = (uint16_t *)(ip + 1); 3138 for (; len > 0; len -= sizeof(uint16_t), opts++) { 3139 temp32 = csum - *opts; 3140 temp32 = (temp32 >> 16) + (temp32 & 65535); 3141 csum = temp32 & 65535; 3142 } 3143 } 3144 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID; 3145 m->m_pkthdr.csum_data = csum; 3146 } 3147 3148 static void 3149 msk_rxeof(struct msk_if_softc *sc_if, uint32_t status, uint32_t control, 3150 int len) 3151 { 3152 struct mbuf *m; 3153 if_t ifp; 3154 struct msk_rxdesc *rxd; 3155 int cons, rxlen; 3156 3157 ifp = sc_if->msk_ifp; 3158 3159 MSK_IF_LOCK_ASSERT(sc_if); 3160 3161 cons = sc_if->msk_cdata.msk_rx_cons; 3162 do { 3163 rxlen = status >> 16; 3164 if ((status & GMR_FS_VLAN) != 0 && 3165 (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0) 3166 rxlen -= ETHER_VLAN_ENCAP_LEN; 3167 if ((sc_if->msk_flags & MSK_FLAG_NORXCHK) != 0) { 3168 /* 3169 * For controllers that returns bogus status code 3170 * just do minimal check and let upper stack 3171 * handle this frame. 3172 */ 3173 if (len > MSK_MAX_FRAMELEN || len < ETHER_HDR_LEN) { 3174 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 3175 msk_discard_rxbuf(sc_if, cons); 3176 break; 3177 } 3178 } else if (len > sc_if->msk_framesize || 3179 ((status & GMR_FS_ANY_ERR) != 0) || 3180 ((status & GMR_FS_RX_OK) == 0) || (rxlen != len)) { 3181 /* Don't count flow-control packet as errors. */ 3182 if ((status & GMR_FS_GOOD_FC) == 0) 3183 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 3184 msk_discard_rxbuf(sc_if, cons); 3185 break; 3186 } 3187 #ifdef MSK_64BIT_DMA 3188 rxd = &sc_if->msk_cdata.msk_rxdesc[(cons + 1) % 3189 MSK_RX_RING_CNT]; 3190 #else 3191 rxd = &sc_if->msk_cdata.msk_rxdesc[cons]; 3192 #endif 3193 m = rxd->rx_m; 3194 if (msk_newbuf(sc_if, cons) != 0) { 3195 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 3196 /* Reuse old buffer. */ 3197 msk_discard_rxbuf(sc_if, cons); 3198 break; 3199 } 3200 m->m_pkthdr.rcvif = ifp; 3201 m->m_pkthdr.len = m->m_len = len; 3202 #ifndef __NO_STRICT_ALIGNMENT 3203 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) != 0) 3204 msk_fixup_rx(m); 3205 #endif 3206 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 3207 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0) 3208 msk_rxcsum(sc_if, control, m); 3209 /* Check for VLAN tagged packets. */ 3210 if ((status & GMR_FS_VLAN) != 0 && 3211 (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0) { 3212 m->m_pkthdr.ether_vtag = sc_if->msk_vtag; 3213 m->m_flags |= M_VLANTAG; 3214 } 3215 MSK_IF_UNLOCK(sc_if); 3216 if_input(ifp, m); 3217 MSK_IF_LOCK(sc_if); 3218 } while (0); 3219 3220 MSK_RX_INC(sc_if->msk_cdata.msk_rx_cons, MSK_RX_RING_CNT); 3221 MSK_RX_INC(sc_if->msk_cdata.msk_rx_prod, MSK_RX_RING_CNT); 3222 } 3223 3224 static void 3225 msk_jumbo_rxeof(struct msk_if_softc *sc_if, uint32_t status, uint32_t control, 3226 int len) 3227 { 3228 struct mbuf *m; 3229 if_t ifp; 3230 struct msk_rxdesc *jrxd; 3231 int cons, rxlen; 3232 3233 ifp = sc_if->msk_ifp; 3234 3235 MSK_IF_LOCK_ASSERT(sc_if); 3236 3237 cons = sc_if->msk_cdata.msk_rx_cons; 3238 do { 3239 rxlen = status >> 16; 3240 if ((status & GMR_FS_VLAN) != 0 && 3241 (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0) 3242 rxlen -= ETHER_VLAN_ENCAP_LEN; 3243 if (len > sc_if->msk_framesize || 3244 ((status & GMR_FS_ANY_ERR) != 0) || 3245 ((status & GMR_FS_RX_OK) == 0) || (rxlen != len)) { 3246 /* Don't count flow-control packet as errors. */ 3247 if ((status & GMR_FS_GOOD_FC) == 0) 3248 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 3249 msk_discard_jumbo_rxbuf(sc_if, cons); 3250 break; 3251 } 3252 #ifdef MSK_64BIT_DMA 3253 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[(cons + 1) % 3254 MSK_JUMBO_RX_RING_CNT]; 3255 #else 3256 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[cons]; 3257 #endif 3258 m = jrxd->rx_m; 3259 if (msk_jumbo_newbuf(sc_if, cons) != 0) { 3260 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 3261 /* Reuse old buffer. */ 3262 msk_discard_jumbo_rxbuf(sc_if, cons); 3263 break; 3264 } 3265 m->m_pkthdr.rcvif = ifp; 3266 m->m_pkthdr.len = m->m_len = len; 3267 #ifndef __NO_STRICT_ALIGNMENT 3268 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) != 0) 3269 msk_fixup_rx(m); 3270 #endif 3271 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 3272 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0) 3273 msk_rxcsum(sc_if, control, m); 3274 /* Check for VLAN tagged packets. */ 3275 if ((status & GMR_FS_VLAN) != 0 && 3276 (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0) { 3277 m->m_pkthdr.ether_vtag = sc_if->msk_vtag; 3278 m->m_flags |= M_VLANTAG; 3279 } 3280 MSK_IF_UNLOCK(sc_if); 3281 if_input(ifp, m); 3282 MSK_IF_LOCK(sc_if); 3283 } while (0); 3284 3285 MSK_RX_INC(sc_if->msk_cdata.msk_rx_cons, MSK_JUMBO_RX_RING_CNT); 3286 MSK_RX_INC(sc_if->msk_cdata.msk_rx_prod, MSK_JUMBO_RX_RING_CNT); 3287 } 3288 3289 static void 3290 msk_txeof(struct msk_if_softc *sc_if, int idx) 3291 { 3292 struct msk_txdesc *txd; 3293 struct msk_tx_desc *cur_tx; 3294 if_t ifp; 3295 uint32_t control; 3296 int cons, prog; 3297 3298 MSK_IF_LOCK_ASSERT(sc_if); 3299 3300 ifp = sc_if->msk_ifp; 3301 3302 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_ring_tag, 3303 sc_if->msk_cdata.msk_tx_ring_map, 3304 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3305 /* 3306 * Go through our tx ring and free mbufs for those 3307 * frames that have been sent. 3308 */ 3309 cons = sc_if->msk_cdata.msk_tx_cons; 3310 prog = 0; 3311 for (; cons != idx; MSK_INC(cons, MSK_TX_RING_CNT)) { 3312 if (sc_if->msk_cdata.msk_tx_cnt <= 0) 3313 break; 3314 prog++; 3315 cur_tx = &sc_if->msk_rdata.msk_tx_ring[cons]; 3316 control = le32toh(cur_tx->msk_control); 3317 sc_if->msk_cdata.msk_tx_cnt--; 3318 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 3319 if ((control & EOP) == 0) 3320 continue; 3321 txd = &sc_if->msk_cdata.msk_txdesc[cons]; 3322 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_tag, txd->tx_dmamap, 3323 BUS_DMASYNC_POSTWRITE); 3324 bus_dmamap_unload(sc_if->msk_cdata.msk_tx_tag, txd->tx_dmamap); 3325 3326 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 3327 KASSERT(txd->tx_m != NULL, ("%s: freeing NULL mbuf!", 3328 __func__)); 3329 m_freem(txd->tx_m); 3330 txd->tx_m = NULL; 3331 } 3332 3333 if (prog > 0) { 3334 sc_if->msk_cdata.msk_tx_cons = cons; 3335 if (sc_if->msk_cdata.msk_tx_cnt == 0) 3336 sc_if->msk_watchdog_timer = 0; 3337 /* No need to sync LEs as we didn't update LEs. */ 3338 } 3339 } 3340 3341 static void 3342 msk_tick(void *xsc_if) 3343 { 3344 struct epoch_tracker et; 3345 struct msk_if_softc *sc_if; 3346 struct mii_data *mii; 3347 3348 sc_if = xsc_if; 3349 3350 MSK_IF_LOCK_ASSERT(sc_if); 3351 3352 mii = device_get_softc(sc_if->msk_miibus); 3353 3354 mii_tick(mii); 3355 if ((sc_if->msk_flags & MSK_FLAG_LINK) == 0) 3356 msk_miibus_statchg(sc_if->msk_if_dev); 3357 NET_EPOCH_ENTER(et); 3358 msk_handle_events(sc_if->msk_softc); 3359 NET_EPOCH_EXIT(et); 3360 msk_watchdog(sc_if); 3361 callout_reset(&sc_if->msk_tick_ch, hz, msk_tick, sc_if); 3362 } 3363 3364 static void 3365 msk_intr_phy(struct msk_if_softc *sc_if) 3366 { 3367 uint16_t status; 3368 3369 msk_phy_readreg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_STAT); 3370 status = msk_phy_readreg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_STAT); 3371 /* Handle FIFO Underrun/Overflow? */ 3372 if ((status & PHY_M_IS_FIFO_ERROR)) 3373 device_printf(sc_if->msk_if_dev, 3374 "PHY FIFO underrun/overflow.\n"); 3375 } 3376 3377 static void 3378 msk_intr_gmac(struct msk_if_softc *sc_if) 3379 { 3380 struct msk_softc *sc; 3381 uint8_t status; 3382 3383 sc = sc_if->msk_softc; 3384 status = CSR_READ_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_SRC)); 3385 3386 /* GMAC Rx FIFO overrun. */ 3387 if ((status & GM_IS_RX_FF_OR) != 0) 3388 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), 3389 GMF_CLI_RX_FO); 3390 /* GMAC Tx FIFO underrun. */ 3391 if ((status & GM_IS_TX_FF_UR) != 0) { 3392 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 3393 GMF_CLI_TX_FU); 3394 device_printf(sc_if->msk_if_dev, "Tx FIFO underrun!\n"); 3395 /* 3396 * XXX 3397 * In case of Tx underrun, we may need to flush/reset 3398 * Tx MAC but that would also require resynchronization 3399 * with status LEs. Reinitializing status LEs would 3400 * affect other port in dual MAC configuration so it 3401 * should be avoided as possible as we can. 3402 * Due to lack of documentation it's all vague guess but 3403 * it needs more investigation. 3404 */ 3405 } 3406 } 3407 3408 static void 3409 msk_handle_hwerr(struct msk_if_softc *sc_if, uint32_t status) 3410 { 3411 struct msk_softc *sc; 3412 3413 sc = sc_if->msk_softc; 3414 if ((status & Y2_IS_PAR_RD1) != 0) { 3415 device_printf(sc_if->msk_if_dev, 3416 "RAM buffer read parity error\n"); 3417 /* Clear IRQ. */ 3418 CSR_WRITE_2(sc, SELECT_RAM_BUFFER(sc_if->msk_port, B3_RI_CTRL), 3419 RI_CLR_RD_PERR); 3420 } 3421 if ((status & Y2_IS_PAR_WR1) != 0) { 3422 device_printf(sc_if->msk_if_dev, 3423 "RAM buffer write parity error\n"); 3424 /* Clear IRQ. */ 3425 CSR_WRITE_2(sc, SELECT_RAM_BUFFER(sc_if->msk_port, B3_RI_CTRL), 3426 RI_CLR_WR_PERR); 3427 } 3428 if ((status & Y2_IS_PAR_MAC1) != 0) { 3429 device_printf(sc_if->msk_if_dev, "Tx MAC parity error\n"); 3430 /* Clear IRQ. */ 3431 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 3432 GMF_CLI_TX_PE); 3433 } 3434 if ((status & Y2_IS_PAR_RX1) != 0) { 3435 device_printf(sc_if->msk_if_dev, "Rx parity error\n"); 3436 /* Clear IRQ. */ 3437 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_CLR_IRQ_PAR); 3438 } 3439 if ((status & (Y2_IS_TCP_TXS1 | Y2_IS_TCP_TXA1)) != 0) { 3440 device_printf(sc_if->msk_if_dev, "TCP segmentation error\n"); 3441 /* Clear IRQ. */ 3442 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_CLR_IRQ_TCP); 3443 } 3444 } 3445 3446 static void 3447 msk_intr_hwerr(struct msk_softc *sc) 3448 { 3449 uint32_t status; 3450 uint32_t tlphead[4]; 3451 3452 status = CSR_READ_4(sc, B0_HWE_ISRC); 3453 /* Time Stamp timer overflow. */ 3454 if ((status & Y2_IS_TIST_OV) != 0) 3455 CSR_WRITE_1(sc, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ); 3456 if ((status & Y2_IS_PCI_NEXP) != 0) { 3457 /* 3458 * PCI Express Error occurred which is not described in PEX 3459 * spec. 3460 * This error is also mapped either to Master Abort( 3461 * Y2_IS_MST_ERR) or Target Abort (Y2_IS_IRQ_STAT) bit and 3462 * can only be cleared there. 3463 */ 3464 device_printf(sc->msk_dev, 3465 "PCI Express protocol violation error\n"); 3466 } 3467 3468 if ((status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) != 0) { 3469 uint16_t v16; 3470 3471 if ((status & Y2_IS_MST_ERR) != 0) 3472 device_printf(sc->msk_dev, 3473 "unexpected IRQ Status error\n"); 3474 else 3475 device_printf(sc->msk_dev, 3476 "unexpected IRQ Master error\n"); 3477 /* Reset all bits in the PCI status register. */ 3478 v16 = pci_read_config(sc->msk_dev, PCIR_STATUS, 2); 3479 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON); 3480 pci_write_config(sc->msk_dev, PCIR_STATUS, v16 | 3481 PCIM_STATUS_PERR | PCIM_STATUS_SERR | PCIM_STATUS_RMABORT | 3482 PCIM_STATUS_RTABORT | PCIM_STATUS_MDPERR, 2); 3483 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 3484 } 3485 3486 /* Check for PCI Express Uncorrectable Error. */ 3487 if ((status & Y2_IS_PCI_EXP) != 0) { 3488 uint32_t v32; 3489 3490 /* 3491 * On PCI Express bus bridges are called root complexes (RC). 3492 * PCI Express errors are recognized by the root complex too, 3493 * which requests the system to handle the problem. After 3494 * error occurrence it may be that no access to the adapter 3495 * may be performed any longer. 3496 */ 3497 3498 v32 = CSR_PCI_READ_4(sc, PEX_UNC_ERR_STAT); 3499 if ((v32 & PEX_UNSUP_REQ) != 0) { 3500 /* Ignore unsupported request error. */ 3501 device_printf(sc->msk_dev, 3502 "Uncorrectable PCI Express error\n"); 3503 } 3504 if ((v32 & (PEX_FATAL_ERRORS | PEX_POIS_TLP)) != 0) { 3505 int i; 3506 3507 /* Get TLP header form Log Registers. */ 3508 for (i = 0; i < 4; i++) 3509 tlphead[i] = CSR_PCI_READ_4(sc, 3510 PEX_HEADER_LOG + i * 4); 3511 /* Check for vendor defined broadcast message. */ 3512 if (!(tlphead[0] == 0x73004001 && tlphead[1] == 0x7f)) { 3513 sc->msk_intrhwemask &= ~Y2_IS_PCI_EXP; 3514 CSR_WRITE_4(sc, B0_HWE_IMSK, 3515 sc->msk_intrhwemask); 3516 CSR_READ_4(sc, B0_HWE_IMSK); 3517 } 3518 } 3519 /* Clear the interrupt. */ 3520 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON); 3521 CSR_PCI_WRITE_4(sc, PEX_UNC_ERR_STAT, 0xffffffff); 3522 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 3523 } 3524 3525 if ((status & Y2_HWE_L1_MASK) != 0 && sc->msk_if[MSK_PORT_A] != NULL) 3526 msk_handle_hwerr(sc->msk_if[MSK_PORT_A], status); 3527 if ((status & Y2_HWE_L2_MASK) != 0 && sc->msk_if[MSK_PORT_B] != NULL) 3528 msk_handle_hwerr(sc->msk_if[MSK_PORT_B], status >> 8); 3529 } 3530 3531 static __inline void 3532 msk_rxput(struct msk_if_softc *sc_if) 3533 { 3534 struct msk_softc *sc; 3535 3536 sc = sc_if->msk_softc; 3537 if (sc_if->msk_framesize > (MCLBYTES - MSK_RX_BUF_ALIGN)) 3538 bus_dmamap_sync( 3539 sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 3540 sc_if->msk_cdata.msk_jumbo_rx_ring_map, 3541 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3542 else 3543 bus_dmamap_sync( 3544 sc_if->msk_cdata.msk_rx_ring_tag, 3545 sc_if->msk_cdata.msk_rx_ring_map, 3546 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3547 CSR_WRITE_2(sc, Y2_PREF_Q_ADDR(sc_if->msk_rxq, 3548 PREF_UNIT_PUT_IDX_REG), sc_if->msk_cdata.msk_rx_prod); 3549 } 3550 3551 static int 3552 msk_handle_events(struct msk_softc *sc) 3553 { 3554 struct msk_if_softc *sc_if; 3555 int rxput[2]; 3556 struct msk_stat_desc *sd; 3557 uint32_t control, status; 3558 int cons, len, port, rxprog; 3559 3560 if (sc->msk_stat_cons == CSR_READ_2(sc, STAT_PUT_IDX)) 3561 return (0); 3562 3563 /* Sync status LEs. */ 3564 bus_dmamap_sync(sc->msk_stat_tag, sc->msk_stat_map, 3565 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3566 3567 rxput[MSK_PORT_A] = rxput[MSK_PORT_B] = 0; 3568 rxprog = 0; 3569 cons = sc->msk_stat_cons; 3570 for (;;) { 3571 sd = &sc->msk_stat_ring[cons]; 3572 control = le32toh(sd->msk_control); 3573 if ((control & HW_OWNER) == 0) 3574 break; 3575 control &= ~HW_OWNER; 3576 sd->msk_control = htole32(control); 3577 status = le32toh(sd->msk_status); 3578 len = control & STLE_LEN_MASK; 3579 port = (control >> 16) & 0x01; 3580 sc_if = sc->msk_if[port]; 3581 if (sc_if == NULL) { 3582 device_printf(sc->msk_dev, "invalid port opcode " 3583 "0x%08x\n", control & STLE_OP_MASK); 3584 continue; 3585 } 3586 3587 switch (control & STLE_OP_MASK) { 3588 case OP_RXVLAN: 3589 sc_if->msk_vtag = ntohs(len); 3590 break; 3591 case OP_RXCHKSVLAN: 3592 sc_if->msk_vtag = ntohs(len); 3593 /* FALLTHROUGH */ 3594 case OP_RXCHKS: 3595 sc_if->msk_csum = status; 3596 break; 3597 case OP_RXSTAT: 3598 if (!(if_getdrvflags(sc_if->msk_ifp) & IFF_DRV_RUNNING)) 3599 break; 3600 if (sc_if->msk_framesize > 3601 (MCLBYTES - MSK_RX_BUF_ALIGN)) 3602 msk_jumbo_rxeof(sc_if, status, control, len); 3603 else 3604 msk_rxeof(sc_if, status, control, len); 3605 rxprog++; 3606 /* 3607 * Because there is no way to sync single Rx LE 3608 * put the DMA sync operation off until the end of 3609 * event processing. 3610 */ 3611 rxput[port]++; 3612 /* Update prefetch unit if we've passed water mark. */ 3613 if (rxput[port] >= sc_if->msk_cdata.msk_rx_putwm) { 3614 msk_rxput(sc_if); 3615 rxput[port] = 0; 3616 } 3617 break; 3618 case OP_TXINDEXLE: 3619 if (sc->msk_if[MSK_PORT_A] != NULL) 3620 msk_txeof(sc->msk_if[MSK_PORT_A], 3621 status & STLE_TXA1_MSKL); 3622 if (sc->msk_if[MSK_PORT_B] != NULL) 3623 msk_txeof(sc->msk_if[MSK_PORT_B], 3624 ((status & STLE_TXA2_MSKL) >> 3625 STLE_TXA2_SHIFTL) | 3626 ((len & STLE_TXA2_MSKH) << 3627 STLE_TXA2_SHIFTH)); 3628 break; 3629 default: 3630 device_printf(sc->msk_dev, "unhandled opcode 0x%08x\n", 3631 control & STLE_OP_MASK); 3632 break; 3633 } 3634 MSK_INC(cons, sc->msk_stat_count); 3635 if (rxprog > sc->msk_process_limit) 3636 break; 3637 } 3638 3639 sc->msk_stat_cons = cons; 3640 bus_dmamap_sync(sc->msk_stat_tag, sc->msk_stat_map, 3641 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3642 3643 if (rxput[MSK_PORT_A] > 0) 3644 msk_rxput(sc->msk_if[MSK_PORT_A]); 3645 if (rxput[MSK_PORT_B] > 0) 3646 msk_rxput(sc->msk_if[MSK_PORT_B]); 3647 3648 return (sc->msk_stat_cons != CSR_READ_2(sc, STAT_PUT_IDX)); 3649 } 3650 3651 static void 3652 msk_intr(void *xsc) 3653 { 3654 struct msk_softc *sc; 3655 struct msk_if_softc *sc_if0, *sc_if1; 3656 if_t ifp0, ifp1; 3657 uint32_t status; 3658 int domore; 3659 3660 sc = xsc; 3661 MSK_LOCK(sc); 3662 3663 /* Reading B0_Y2_SP_ISRC2 masks further interrupts. */ 3664 status = CSR_READ_4(sc, B0_Y2_SP_ISRC2); 3665 if (status == 0 || status == 0xffffffff || 3666 (sc->msk_pflags & MSK_FLAG_SUSPEND) != 0 || 3667 (status & sc->msk_intrmask) == 0) { 3668 CSR_WRITE_4(sc, B0_Y2_SP_ICR, 2); 3669 MSK_UNLOCK(sc); 3670 return; 3671 } 3672 3673 sc_if0 = sc->msk_if[MSK_PORT_A]; 3674 sc_if1 = sc->msk_if[MSK_PORT_B]; 3675 ifp0 = ifp1 = NULL; 3676 if (sc_if0 != NULL) 3677 ifp0 = sc_if0->msk_ifp; 3678 if (sc_if1 != NULL) 3679 ifp1 = sc_if1->msk_ifp; 3680 3681 if ((status & Y2_IS_IRQ_PHY1) != 0 && sc_if0 != NULL) 3682 msk_intr_phy(sc_if0); 3683 if ((status & Y2_IS_IRQ_PHY2) != 0 && sc_if1 != NULL) 3684 msk_intr_phy(sc_if1); 3685 if ((status & Y2_IS_IRQ_MAC1) != 0 && sc_if0 != NULL) 3686 msk_intr_gmac(sc_if0); 3687 if ((status & Y2_IS_IRQ_MAC2) != 0 && sc_if1 != NULL) 3688 msk_intr_gmac(sc_if1); 3689 if ((status & (Y2_IS_CHK_RX1 | Y2_IS_CHK_RX2)) != 0) { 3690 device_printf(sc->msk_dev, "Rx descriptor error\n"); 3691 sc->msk_intrmask &= ~(Y2_IS_CHK_RX1 | Y2_IS_CHK_RX2); 3692 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask); 3693 CSR_READ_4(sc, B0_IMSK); 3694 } 3695 if ((status & (Y2_IS_CHK_TXA1 | Y2_IS_CHK_TXA2)) != 0) { 3696 device_printf(sc->msk_dev, "Tx descriptor error\n"); 3697 sc->msk_intrmask &= ~(Y2_IS_CHK_TXA1 | Y2_IS_CHK_TXA2); 3698 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask); 3699 CSR_READ_4(sc, B0_IMSK); 3700 } 3701 if ((status & Y2_IS_HW_ERR) != 0) 3702 msk_intr_hwerr(sc); 3703 3704 domore = msk_handle_events(sc); 3705 if ((status & Y2_IS_STAT_BMU) != 0 && domore == 0) 3706 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_CLR_IRQ); 3707 3708 /* Reenable interrupts. */ 3709 CSR_WRITE_4(sc, B0_Y2_SP_ICR, 2); 3710 3711 if (ifp0 != NULL && (if_getdrvflags(ifp0) & IFF_DRV_RUNNING) != 0 && 3712 !if_sendq_empty(ifp0)) 3713 msk_start_locked(ifp0); 3714 if (ifp1 != NULL && (if_getdrvflags(ifp1) & IFF_DRV_RUNNING) != 0 && 3715 !if_sendq_empty(ifp1)) 3716 msk_start_locked(ifp1); 3717 3718 MSK_UNLOCK(sc); 3719 } 3720 3721 static void 3722 msk_set_tx_stfwd(struct msk_if_softc *sc_if) 3723 { 3724 struct msk_softc *sc; 3725 if_t ifp; 3726 3727 ifp = sc_if->msk_ifp; 3728 sc = sc_if->msk_softc; 3729 if ((sc->msk_hw_id == CHIP_ID_YUKON_EX && 3730 sc->msk_hw_rev != CHIP_REV_YU_EX_A0) || 3731 sc->msk_hw_id >= CHIP_ID_YUKON_SUPR) { 3732 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 3733 TX_STFW_ENA); 3734 } else { 3735 if (if_getmtu(ifp) > ETHERMTU) { 3736 /* Set Tx GMAC FIFO Almost Empty Threshold. */ 3737 CSR_WRITE_4(sc, 3738 MR_ADDR(sc_if->msk_port, TX_GMF_AE_THR), 3739 MSK_ECU_JUMBO_WM << 16 | MSK_ECU_AE_THR); 3740 /* Disable Store & Forward mode for Tx. */ 3741 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 3742 TX_STFW_DIS); 3743 } else { 3744 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 3745 TX_STFW_ENA); 3746 } 3747 } 3748 } 3749 3750 static void 3751 msk_init(void *xsc) 3752 { 3753 struct msk_if_softc *sc_if = xsc; 3754 3755 MSK_IF_LOCK(sc_if); 3756 msk_init_locked(sc_if); 3757 MSK_IF_UNLOCK(sc_if); 3758 } 3759 3760 static void 3761 msk_init_locked(struct msk_if_softc *sc_if) 3762 { 3763 struct msk_softc *sc; 3764 if_t ifp; 3765 struct mii_data *mii; 3766 uint8_t *eaddr; 3767 uint16_t gmac; 3768 uint32_t reg; 3769 int error; 3770 3771 MSK_IF_LOCK_ASSERT(sc_if); 3772 3773 ifp = sc_if->msk_ifp; 3774 sc = sc_if->msk_softc; 3775 mii = device_get_softc(sc_if->msk_miibus); 3776 3777 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 3778 return; 3779 3780 error = 0; 3781 /* Cancel pending I/O and free all Rx/Tx buffers. */ 3782 msk_stop(sc_if); 3783 3784 if (if_getmtu(ifp) < ETHERMTU) 3785 sc_if->msk_framesize = ETHERMTU; 3786 else 3787 sc_if->msk_framesize = if_getmtu(ifp); 3788 sc_if->msk_framesize += ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 3789 if (if_getmtu(ifp) > ETHERMTU && 3790 (sc_if->msk_flags & MSK_FLAG_JUMBO_NOCSUM) != 0) { 3791 if_sethwassistbits(ifp, 0, (MSK_CSUM_FEATURES | CSUM_TSO)); 3792 if_setcapenablebit(ifp, 0, (IFCAP_TSO4 | IFCAP_TXCSUM)); 3793 } 3794 3795 /* GMAC Control reset. */ 3796 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_RST_SET); 3797 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_RST_CLR); 3798 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_F_LOOPB_OFF); 3799 if (sc->msk_hw_id == CHIP_ID_YUKON_EX || 3800 sc->msk_hw_id == CHIP_ID_YUKON_SUPR) 3801 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), 3802 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON | 3803 GMC_BYP_RETR_ON); 3804 3805 /* 3806 * Initialize GMAC first such that speed/duplex/flow-control 3807 * parameters are renegotiated when interface is brought up. 3808 */ 3809 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, 0); 3810 3811 /* Dummy read the Interrupt Source Register. */ 3812 CSR_READ_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_SRC)); 3813 3814 /* Clear MIB stats. */ 3815 msk_stats_clear(sc_if); 3816 3817 /* Disable FCS. */ 3818 GMAC_WRITE_2(sc, sc_if->msk_port, GM_RX_CTRL, GM_RXCR_CRC_DIS); 3819 3820 /* Setup Transmit Control Register. */ 3821 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF)); 3822 3823 /* Setup Transmit Flow Control Register. */ 3824 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_FLOW_CTRL, 0xffff); 3825 3826 /* Setup Transmit Parameter Register. */ 3827 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_PARAM, 3828 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) | TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) | 3829 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) | TX_BACK_OFF_LIM(TX_BOF_LIM_DEF)); 3830 3831 gmac = DATA_BLIND_VAL(DATA_BLIND_DEF) | 3832 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF); 3833 3834 if (if_getmtu(ifp) > ETHERMTU) 3835 gmac |= GM_SMOD_JUMBO_ENA; 3836 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SERIAL_MODE, gmac); 3837 3838 /* Set station address. */ 3839 eaddr = if_getlladdr(ifp); 3840 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_1L, 3841 eaddr[0] | (eaddr[1] << 8)); 3842 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_1M, 3843 eaddr[2] | (eaddr[3] << 8)); 3844 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_1H, 3845 eaddr[4] | (eaddr[5] << 8)); 3846 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_2L, 3847 eaddr[0] | (eaddr[1] << 8)); 3848 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_2M, 3849 eaddr[2] | (eaddr[3] << 8)); 3850 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_2H, 3851 eaddr[4] | (eaddr[5] << 8)); 3852 3853 /* Disable interrupts for counter overflows. */ 3854 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_IRQ_MSK, 0); 3855 GMAC_WRITE_2(sc, sc_if->msk_port, GM_RX_IRQ_MSK, 0); 3856 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TR_IRQ_MSK, 0); 3857 3858 /* Configure Rx MAC FIFO. */ 3859 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), GMF_RST_SET); 3860 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), GMF_RST_CLR); 3861 reg = GMF_OPER_ON | GMF_RX_F_FL_ON; 3862 if (sc->msk_hw_id == CHIP_ID_YUKON_FE_P || 3863 sc->msk_hw_id == CHIP_ID_YUKON_EX) 3864 reg |= GMF_RX_OVER_ON; 3865 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), reg); 3866 3867 /* Set receive filter. */ 3868 msk_rxfilter(sc_if); 3869 3870 if (sc->msk_hw_id == CHIP_ID_YUKON_XL) { 3871 /* Clear flush mask - HW bug. */ 3872 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_FL_MSK), 0); 3873 } else { 3874 /* Flush Rx MAC FIFO on any flow control or error. */ 3875 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_FL_MSK), 3876 GMR_FS_ANY_ERR); 3877 } 3878 3879 /* 3880 * Set Rx FIFO flush threshold to 64 bytes + 1 FIFO word 3881 * due to hardware hang on receipt of pause frames. 3882 */ 3883 reg = RX_GMF_FL_THR_DEF + 1; 3884 /* Another magic for Yukon FE+ - From Linux. */ 3885 if (sc->msk_hw_id == CHIP_ID_YUKON_FE_P && 3886 sc->msk_hw_rev == CHIP_REV_YU_FE_P_A0) 3887 reg = 0x178; 3888 CSR_WRITE_2(sc, MR_ADDR(sc_if->msk_port, RX_GMF_FL_THR), reg); 3889 3890 /* Configure Tx MAC FIFO. */ 3891 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_RST_SET); 3892 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_RST_CLR); 3893 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_OPER_ON); 3894 3895 /* Configure hardware VLAN tag insertion/stripping. */ 3896 msk_setvlan(sc_if, ifp); 3897 3898 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) == 0) { 3899 /* Set Rx Pause threshold. */ 3900 CSR_WRITE_2(sc, MR_ADDR(sc_if->msk_port, RX_GMF_LP_THR), 3901 MSK_ECU_LLPP); 3902 CSR_WRITE_2(sc, MR_ADDR(sc_if->msk_port, RX_GMF_UP_THR), 3903 MSK_ECU_ULPP); 3904 /* Configure store-and-forward for Tx. */ 3905 msk_set_tx_stfwd(sc_if); 3906 } 3907 3908 if (sc->msk_hw_id == CHIP_ID_YUKON_FE_P && 3909 sc->msk_hw_rev == CHIP_REV_YU_FE_P_A0) { 3910 /* Disable dynamic watermark - from Linux. */ 3911 reg = CSR_READ_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_EA)); 3912 reg &= ~0x03; 3913 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_EA), reg); 3914 } 3915 3916 /* 3917 * Disable Force Sync bit and Alloc bit in Tx RAM interface 3918 * arbiter as we don't use Sync Tx queue. 3919 */ 3920 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, TXA_CTRL), 3921 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC); 3922 /* Enable the RAM Interface Arbiter. */ 3923 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, TXA_CTRL), TXA_ENA_ARB); 3924 3925 /* Setup RAM buffer. */ 3926 msk_set_rambuffer(sc_if); 3927 3928 /* Disable Tx sync Queue. */ 3929 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txsq, RB_CTRL), RB_RST_SET); 3930 3931 /* Setup Tx Queue Bus Memory Interface. */ 3932 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_CLR_RESET); 3933 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_OPER_INIT); 3934 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_FIFO_OP_ON); 3935 CSR_WRITE_2(sc, Q_ADDR(sc_if->msk_txq, Q_WM), MSK_BMU_TX_WM); 3936 switch (sc->msk_hw_id) { 3937 case CHIP_ID_YUKON_EC_U: 3938 if (sc->msk_hw_rev == CHIP_REV_YU_EC_U_A0) { 3939 /* Fix for Yukon-EC Ultra: set BMU FIFO level */ 3940 CSR_WRITE_2(sc, Q_ADDR(sc_if->msk_txq, Q_AL), 3941 MSK_ECU_TXFF_LEV); 3942 } 3943 break; 3944 case CHIP_ID_YUKON_EX: 3945 /* 3946 * Yukon Extreme seems to have silicon bug for 3947 * automatic Tx checksum calculation capability. 3948 */ 3949 if (sc->msk_hw_rev == CHIP_REV_YU_EX_B0) 3950 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_F), 3951 F_TX_CHK_AUTO_OFF); 3952 break; 3953 } 3954 3955 /* Setup Rx Queue Bus Memory Interface. */ 3956 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_CLR_RESET); 3957 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_OPER_INIT); 3958 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_FIFO_OP_ON); 3959 CSR_WRITE_2(sc, Q_ADDR(sc_if->msk_rxq, Q_WM), MSK_BMU_RX_WM); 3960 if (sc->msk_hw_id == CHIP_ID_YUKON_EC_U && 3961 sc->msk_hw_rev >= CHIP_REV_YU_EC_U_A1) { 3962 /* MAC Rx RAM Read is controlled by hardware. */ 3963 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_F), F_M_RX_RAM_DIS); 3964 } 3965 3966 msk_set_prefetch(sc, sc_if->msk_txq, 3967 sc_if->msk_rdata.msk_tx_ring_paddr, MSK_TX_RING_CNT - 1); 3968 msk_init_tx_ring(sc_if); 3969 3970 /* Disable Rx checksum offload and RSS hash. */ 3971 reg = BMU_DIS_RX_RSS_HASH; 3972 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0 && 3973 (if_getcapenable(ifp) & IFCAP_RXCSUM) != 0) 3974 reg |= BMU_ENA_RX_CHKSUM; 3975 else 3976 reg |= BMU_DIS_RX_CHKSUM; 3977 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), reg); 3978 if (sc_if->msk_framesize > (MCLBYTES - MSK_RX_BUF_ALIGN)) { 3979 msk_set_prefetch(sc, sc_if->msk_rxq, 3980 sc_if->msk_rdata.msk_jumbo_rx_ring_paddr, 3981 MSK_JUMBO_RX_RING_CNT - 1); 3982 error = msk_init_jumbo_rx_ring(sc_if); 3983 } else { 3984 msk_set_prefetch(sc, sc_if->msk_rxq, 3985 sc_if->msk_rdata.msk_rx_ring_paddr, 3986 MSK_RX_RING_CNT - 1); 3987 error = msk_init_rx_ring(sc_if); 3988 } 3989 if (error != 0) { 3990 device_printf(sc_if->msk_if_dev, 3991 "initialization failed: no memory for Rx buffers\n"); 3992 msk_stop(sc_if); 3993 return; 3994 } 3995 if (sc->msk_hw_id == CHIP_ID_YUKON_EX || 3996 sc->msk_hw_id == CHIP_ID_YUKON_SUPR) { 3997 /* Disable flushing of non-ASF packets. */ 3998 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), 3999 GMF_RX_MACSEC_FLUSH_OFF); 4000 } 4001 4002 /* Configure interrupt handling. */ 4003 if (sc_if->msk_port == MSK_PORT_A) { 4004 sc->msk_intrmask |= Y2_IS_PORT_A; 4005 sc->msk_intrhwemask |= Y2_HWE_L1_MASK; 4006 } else { 4007 sc->msk_intrmask |= Y2_IS_PORT_B; 4008 sc->msk_intrhwemask |= Y2_HWE_L2_MASK; 4009 } 4010 /* Configure IRQ moderation mask. */ 4011 CSR_WRITE_4(sc, B2_IRQM_MSK, sc->msk_intrmask); 4012 if (sc->msk_int_holdoff > 0) { 4013 /* Configure initial IRQ moderation timer value. */ 4014 CSR_WRITE_4(sc, B2_IRQM_INI, 4015 MSK_USECS(sc, sc->msk_int_holdoff)); 4016 CSR_WRITE_4(sc, B2_IRQM_VAL, 4017 MSK_USECS(sc, sc->msk_int_holdoff)); 4018 /* Start IRQ moderation. */ 4019 CSR_WRITE_1(sc, B2_IRQM_CTRL, TIM_START); 4020 } 4021 CSR_WRITE_4(sc, B0_HWE_IMSK, sc->msk_intrhwemask); 4022 CSR_READ_4(sc, B0_HWE_IMSK); 4023 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask); 4024 CSR_READ_4(sc, B0_IMSK); 4025 4026 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0); 4027 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 4028 4029 sc_if->msk_flags &= ~MSK_FLAG_LINK; 4030 mii_mediachg(mii); 4031 4032 callout_reset(&sc_if->msk_tick_ch, hz, msk_tick, sc_if); 4033 } 4034 4035 static void 4036 msk_set_rambuffer(struct msk_if_softc *sc_if) 4037 { 4038 struct msk_softc *sc; 4039 int ltpp, utpp; 4040 4041 sc = sc_if->msk_softc; 4042 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) == 0) 4043 return; 4044 4045 /* Setup Rx Queue. */ 4046 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_RST_CLR); 4047 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_START), 4048 sc->msk_rxqstart[sc_if->msk_port] / 8); 4049 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_END), 4050 sc->msk_rxqend[sc_if->msk_port] / 8); 4051 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_WP), 4052 sc->msk_rxqstart[sc_if->msk_port] / 8); 4053 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_RP), 4054 sc->msk_rxqstart[sc_if->msk_port] / 8); 4055 4056 utpp = (sc->msk_rxqend[sc_if->msk_port] + 1 - 4057 sc->msk_rxqstart[sc_if->msk_port] - MSK_RB_ULPP) / 8; 4058 ltpp = (sc->msk_rxqend[sc_if->msk_port] + 1 - 4059 sc->msk_rxqstart[sc_if->msk_port] - MSK_RB_LLPP_B) / 8; 4060 if (sc->msk_rxqsize < MSK_MIN_RXQ_SIZE) 4061 ltpp += (MSK_RB_LLPP_B - MSK_RB_LLPP_S) / 8; 4062 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_RX_UTPP), utpp); 4063 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_RX_LTPP), ltpp); 4064 /* Set Rx priority(RB_RX_UTHP/RB_RX_LTHP) thresholds? */ 4065 4066 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_ENA_OP_MD); 4067 CSR_READ_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL)); 4068 4069 /* Setup Tx Queue. */ 4070 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_RST_CLR); 4071 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_START), 4072 sc->msk_txqstart[sc_if->msk_port] / 8); 4073 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_END), 4074 sc->msk_txqend[sc_if->msk_port] / 8); 4075 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_WP), 4076 sc->msk_txqstart[sc_if->msk_port] / 8); 4077 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_RP), 4078 sc->msk_txqstart[sc_if->msk_port] / 8); 4079 /* Enable Store & Forward for Tx side. */ 4080 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_ENA_STFWD); 4081 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_ENA_OP_MD); 4082 CSR_READ_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL)); 4083 } 4084 4085 static void 4086 msk_set_prefetch(struct msk_softc *sc, int qaddr, bus_addr_t addr, 4087 uint32_t count) 4088 { 4089 4090 /* Reset the prefetch unit. */ 4091 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG), 4092 PREF_UNIT_RST_SET); 4093 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG), 4094 PREF_UNIT_RST_CLR); 4095 /* Set LE base address. */ 4096 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_ADDR_LOW_REG), 4097 MSK_ADDR_LO(addr)); 4098 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_ADDR_HI_REG), 4099 MSK_ADDR_HI(addr)); 4100 /* Set the list last index. */ 4101 CSR_WRITE_2(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_LAST_IDX_REG), 4102 count); 4103 /* Turn on prefetch unit. */ 4104 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG), 4105 PREF_UNIT_OP_ON); 4106 /* Dummy read to ensure write. */ 4107 CSR_READ_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG)); 4108 } 4109 4110 static void 4111 msk_stop(struct msk_if_softc *sc_if) 4112 { 4113 struct msk_softc *sc; 4114 struct msk_txdesc *txd; 4115 struct msk_rxdesc *rxd; 4116 struct msk_rxdesc *jrxd; 4117 if_t ifp; 4118 uint32_t val; 4119 int i; 4120 4121 MSK_IF_LOCK_ASSERT(sc_if); 4122 sc = sc_if->msk_softc; 4123 ifp = sc_if->msk_ifp; 4124 4125 callout_stop(&sc_if->msk_tick_ch); 4126 sc_if->msk_watchdog_timer = 0; 4127 4128 /* Disable interrupts. */ 4129 if (sc_if->msk_port == MSK_PORT_A) { 4130 sc->msk_intrmask &= ~Y2_IS_PORT_A; 4131 sc->msk_intrhwemask &= ~Y2_HWE_L1_MASK; 4132 } else { 4133 sc->msk_intrmask &= ~Y2_IS_PORT_B; 4134 sc->msk_intrhwemask &= ~Y2_HWE_L2_MASK; 4135 } 4136 CSR_WRITE_4(sc, B0_HWE_IMSK, sc->msk_intrhwemask); 4137 CSR_READ_4(sc, B0_HWE_IMSK); 4138 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask); 4139 CSR_READ_4(sc, B0_IMSK); 4140 4141 /* Disable Tx/Rx MAC. */ 4142 val = GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL); 4143 val &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA); 4144 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, val); 4145 /* Read again to ensure writing. */ 4146 GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL); 4147 /* Update stats and clear counters. */ 4148 msk_stats_update(sc_if); 4149 4150 /* Stop Tx BMU. */ 4151 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_STOP); 4152 val = CSR_READ_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR)); 4153 for (i = 0; i < MSK_TIMEOUT; i++) { 4154 if ((val & (BMU_STOP | BMU_IDLE)) == 0) { 4155 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), 4156 BMU_STOP); 4157 val = CSR_READ_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR)); 4158 } else 4159 break; 4160 DELAY(1); 4161 } 4162 if (i == MSK_TIMEOUT) 4163 device_printf(sc_if->msk_if_dev, "Tx BMU stop failed\n"); 4164 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), 4165 RB_RST_SET | RB_DIS_OP_MD); 4166 4167 /* Disable all GMAC interrupt. */ 4168 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_MSK), 0); 4169 /* Disable PHY interrupt. */ 4170 msk_phy_writereg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_MASK, 0); 4171 4172 /* Disable the RAM Interface Arbiter. */ 4173 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, TXA_CTRL), TXA_DIS_ARB); 4174 4175 /* Reset the PCI FIFO of the async Tx queue */ 4176 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), 4177 BMU_RST_SET | BMU_FIFO_RST); 4178 4179 /* Reset the Tx prefetch units. */ 4180 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(sc_if->msk_txq, PREF_UNIT_CTRL_REG), 4181 PREF_UNIT_RST_SET); 4182 4183 /* Reset the RAM Buffer async Tx queue. */ 4184 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_RST_SET); 4185 4186 /* Reset Tx MAC FIFO. */ 4187 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_RST_SET); 4188 /* Set Pause Off. */ 4189 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_PAUSE_OFF); 4190 4191 /* 4192 * The Rx Stop command will not work for Yukon-2 if the BMU does not 4193 * reach the end of packet and since we can't make sure that we have 4194 * incoming data, we must reset the BMU while it is not during a DMA 4195 * transfer. Since it is possible that the Rx path is still active, 4196 * the Rx RAM buffer will be stopped first, so any possible incoming 4197 * data will not trigger a DMA. After the RAM buffer is stopped, the 4198 * BMU is polled until any DMA in progress is ended and only then it 4199 * will be reset. 4200 */ 4201 4202 /* Disable the RAM Buffer receive queue. */ 4203 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_DIS_OP_MD); 4204 for (i = 0; i < MSK_TIMEOUT; i++) { 4205 if (CSR_READ_1(sc, RB_ADDR(sc_if->msk_rxq, Q_RSL)) == 4206 CSR_READ_1(sc, RB_ADDR(sc_if->msk_rxq, Q_RL))) 4207 break; 4208 DELAY(1); 4209 } 4210 if (i == MSK_TIMEOUT) 4211 device_printf(sc_if->msk_if_dev, "Rx BMU stop failed\n"); 4212 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), 4213 BMU_RST_SET | BMU_FIFO_RST); 4214 /* Reset the Rx prefetch unit. */ 4215 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_CTRL_REG), 4216 PREF_UNIT_RST_SET); 4217 /* Reset the RAM Buffer receive queue. */ 4218 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_RST_SET); 4219 /* Reset Rx MAC FIFO. */ 4220 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), GMF_RST_SET); 4221 4222 /* Free Rx and Tx mbufs still in the queues. */ 4223 for (i = 0; i < MSK_RX_RING_CNT; i++) { 4224 rxd = &sc_if->msk_cdata.msk_rxdesc[i]; 4225 if (rxd->rx_m != NULL) { 4226 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_tag, 4227 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 4228 bus_dmamap_unload(sc_if->msk_cdata.msk_rx_tag, 4229 rxd->rx_dmamap); 4230 m_freem(rxd->rx_m); 4231 rxd->rx_m = NULL; 4232 } 4233 } 4234 for (i = 0; i < MSK_JUMBO_RX_RING_CNT; i++) { 4235 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[i]; 4236 if (jrxd->rx_m != NULL) { 4237 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_tag, 4238 jrxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 4239 bus_dmamap_unload(sc_if->msk_cdata.msk_jumbo_rx_tag, 4240 jrxd->rx_dmamap); 4241 m_freem(jrxd->rx_m); 4242 jrxd->rx_m = NULL; 4243 } 4244 } 4245 for (i = 0; i < MSK_TX_RING_CNT; i++) { 4246 txd = &sc_if->msk_cdata.msk_txdesc[i]; 4247 if (txd->tx_m != NULL) { 4248 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_tag, 4249 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 4250 bus_dmamap_unload(sc_if->msk_cdata.msk_tx_tag, 4251 txd->tx_dmamap); 4252 m_freem(txd->tx_m); 4253 txd->tx_m = NULL; 4254 } 4255 } 4256 4257 /* 4258 * Mark the interface down. 4259 */ 4260 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)); 4261 sc_if->msk_flags &= ~MSK_FLAG_LINK; 4262 } 4263 4264 /* 4265 * When GM_PAR_MIB_CLR bit of GM_PHY_ADDR is set, reading lower 4266 * counter clears high 16 bits of the counter such that accessing 4267 * lower 16 bits should be the last operation. 4268 */ 4269 #define MSK_READ_MIB32(x, y) \ 4270 ((((uint32_t)GMAC_READ_2(sc, x, (y) + 4)) << 16) + \ 4271 (uint32_t)GMAC_READ_2(sc, x, y)) 4272 #define MSK_READ_MIB64(x, y) \ 4273 ((((uint64_t)MSK_READ_MIB32(x, (y) + 8)) << 32) + \ 4274 (uint64_t)MSK_READ_MIB32(x, y)) 4275 4276 static void 4277 msk_stats_clear(struct msk_if_softc *sc_if) 4278 { 4279 struct msk_softc *sc; 4280 uint16_t gmac; 4281 int i; 4282 4283 MSK_IF_LOCK_ASSERT(sc_if); 4284 4285 sc = sc_if->msk_softc; 4286 /* Set MIB Clear Counter Mode. */ 4287 gmac = GMAC_READ_2(sc, sc_if->msk_port, GM_PHY_ADDR); 4288 GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac | GM_PAR_MIB_CLR); 4289 /* Read all MIB Counters with Clear Mode set. */ 4290 for (i = GM_RXF_UC_OK; i <= GM_TXE_FIFO_UR; i += sizeof(uint32_t)) 4291 (void)MSK_READ_MIB32(sc_if->msk_port, i); 4292 /* Clear MIB Clear Counter Mode. */ 4293 gmac &= ~GM_PAR_MIB_CLR; 4294 GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac); 4295 } 4296 4297 static void 4298 msk_stats_update(struct msk_if_softc *sc_if) 4299 { 4300 struct msk_softc *sc; 4301 if_t ifp; 4302 struct msk_hw_stats *stats; 4303 uint16_t gmac; 4304 4305 MSK_IF_LOCK_ASSERT(sc_if); 4306 4307 ifp = sc_if->msk_ifp; 4308 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) 4309 return; 4310 sc = sc_if->msk_softc; 4311 stats = &sc_if->msk_stats; 4312 /* Set MIB Clear Counter Mode. */ 4313 gmac = GMAC_READ_2(sc, sc_if->msk_port, GM_PHY_ADDR); 4314 GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac | GM_PAR_MIB_CLR); 4315 4316 /* Rx stats. */ 4317 stats->rx_ucast_frames += 4318 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_UC_OK); 4319 stats->rx_bcast_frames += 4320 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_BC_OK); 4321 stats->rx_pause_frames += 4322 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_MPAUSE); 4323 stats->rx_mcast_frames += 4324 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_MC_OK); 4325 stats->rx_crc_errs += 4326 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_FCS_ERR); 4327 stats->rx_good_octets += 4328 MSK_READ_MIB64(sc_if->msk_port, GM_RXO_OK_LO); 4329 stats->rx_bad_octets += 4330 MSK_READ_MIB64(sc_if->msk_port, GM_RXO_ERR_LO); 4331 stats->rx_runts += 4332 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_SHT); 4333 stats->rx_runt_errs += 4334 MSK_READ_MIB32(sc_if->msk_port, GM_RXE_FRAG); 4335 stats->rx_pkts_64 += 4336 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_64B); 4337 stats->rx_pkts_65_127 += 4338 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_127B); 4339 stats->rx_pkts_128_255 += 4340 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_255B); 4341 stats->rx_pkts_256_511 += 4342 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_511B); 4343 stats->rx_pkts_512_1023 += 4344 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_1023B); 4345 stats->rx_pkts_1024_1518 += 4346 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_1518B); 4347 stats->rx_pkts_1519_max += 4348 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_MAX_SZ); 4349 stats->rx_pkts_too_long += 4350 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_LNG_ERR); 4351 stats->rx_pkts_jabbers += 4352 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_JAB_PKT); 4353 stats->rx_fifo_oflows += 4354 MSK_READ_MIB32(sc_if->msk_port, GM_RXE_FIFO_OV); 4355 4356 /* Tx stats. */ 4357 stats->tx_ucast_frames += 4358 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_UC_OK); 4359 stats->tx_bcast_frames += 4360 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_BC_OK); 4361 stats->tx_pause_frames += 4362 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_MPAUSE); 4363 stats->tx_mcast_frames += 4364 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_MC_OK); 4365 stats->tx_octets += 4366 MSK_READ_MIB64(sc_if->msk_port, GM_TXO_OK_LO); 4367 stats->tx_pkts_64 += 4368 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_64B); 4369 stats->tx_pkts_65_127 += 4370 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_127B); 4371 stats->tx_pkts_128_255 += 4372 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_255B); 4373 stats->tx_pkts_256_511 += 4374 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_511B); 4375 stats->tx_pkts_512_1023 += 4376 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_1023B); 4377 stats->tx_pkts_1024_1518 += 4378 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_1518B); 4379 stats->tx_pkts_1519_max += 4380 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_MAX_SZ); 4381 stats->tx_colls += 4382 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_COL); 4383 stats->tx_late_colls += 4384 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_LAT_COL); 4385 stats->tx_excess_colls += 4386 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_ABO_COL); 4387 stats->tx_multi_colls += 4388 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_MUL_COL); 4389 stats->tx_single_colls += 4390 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_SNG_COL); 4391 stats->tx_underflows += 4392 MSK_READ_MIB32(sc_if->msk_port, GM_TXE_FIFO_UR); 4393 /* Clear MIB Clear Counter Mode. */ 4394 gmac &= ~GM_PAR_MIB_CLR; 4395 GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac); 4396 } 4397 4398 static int 4399 msk_sysctl_stat32(SYSCTL_HANDLER_ARGS) 4400 { 4401 struct msk_softc *sc; 4402 struct msk_if_softc *sc_if; 4403 uint32_t result, *stat; 4404 int off; 4405 4406 sc_if = (struct msk_if_softc *)arg1; 4407 sc = sc_if->msk_softc; 4408 off = arg2; 4409 stat = (uint32_t *)((uint8_t *)&sc_if->msk_stats + off); 4410 4411 MSK_IF_LOCK(sc_if); 4412 result = MSK_READ_MIB32(sc_if->msk_port, GM_MIB_CNT_BASE + off * 2); 4413 result += *stat; 4414 MSK_IF_UNLOCK(sc_if); 4415 4416 return (sysctl_handle_int(oidp, &result, 0, req)); 4417 } 4418 4419 static int 4420 msk_sysctl_stat64(SYSCTL_HANDLER_ARGS) 4421 { 4422 struct msk_softc *sc; 4423 struct msk_if_softc *sc_if; 4424 uint64_t result, *stat; 4425 int off; 4426 4427 sc_if = (struct msk_if_softc *)arg1; 4428 sc = sc_if->msk_softc; 4429 off = arg2; 4430 stat = (uint64_t *)((uint8_t *)&sc_if->msk_stats + off); 4431 4432 MSK_IF_LOCK(sc_if); 4433 result = MSK_READ_MIB64(sc_if->msk_port, GM_MIB_CNT_BASE + off * 2); 4434 result += *stat; 4435 MSK_IF_UNLOCK(sc_if); 4436 4437 return (sysctl_handle_64(oidp, &result, 0, req)); 4438 } 4439 4440 #undef MSK_READ_MIB32 4441 #undef MSK_READ_MIB64 4442 4443 #define MSK_SYSCTL_STAT32(sc, c, o, p, n, d) \ 4444 SYSCTL_ADD_PROC(c, p, OID_AUTO, o, \ 4445 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, \ 4446 sc, offsetof(struct msk_hw_stats, n), msk_sysctl_stat32, \ 4447 "IU", d) 4448 #define MSK_SYSCTL_STAT64(sc, c, o, p, n, d) \ 4449 SYSCTL_ADD_PROC(c, p, OID_AUTO, o, \ 4450 CTLTYPE_U64 | CTLFLAG_RD | CTLFLAG_NEEDGIANT, \ 4451 sc, offsetof(struct msk_hw_stats, n), msk_sysctl_stat64, \ 4452 "QU", d) 4453 4454 static void 4455 msk_sysctl_node(struct msk_if_softc *sc_if) 4456 { 4457 struct sysctl_ctx_list *ctx; 4458 struct sysctl_oid_list *child, *schild; 4459 struct sysctl_oid *tree; 4460 4461 ctx = device_get_sysctl_ctx(sc_if->msk_if_dev); 4462 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc_if->msk_if_dev)); 4463 4464 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", 4465 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "MSK Statistics"); 4466 schild = SYSCTL_CHILDREN(tree); 4467 tree = SYSCTL_ADD_NODE(ctx, schild, OID_AUTO, "rx", 4468 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "MSK RX Statistics"); 4469 child = SYSCTL_CHILDREN(tree); 4470 MSK_SYSCTL_STAT32(sc_if, ctx, "ucast_frames", 4471 child, rx_ucast_frames, "Good unicast frames"); 4472 MSK_SYSCTL_STAT32(sc_if, ctx, "bcast_frames", 4473 child, rx_bcast_frames, "Good broadcast frames"); 4474 MSK_SYSCTL_STAT32(sc_if, ctx, "pause_frames", 4475 child, rx_pause_frames, "Pause frames"); 4476 MSK_SYSCTL_STAT32(sc_if, ctx, "mcast_frames", 4477 child, rx_mcast_frames, "Multicast frames"); 4478 MSK_SYSCTL_STAT32(sc_if, ctx, "crc_errs", 4479 child, rx_crc_errs, "CRC errors"); 4480 MSK_SYSCTL_STAT64(sc_if, ctx, "good_octets", 4481 child, rx_good_octets, "Good octets"); 4482 MSK_SYSCTL_STAT64(sc_if, ctx, "bad_octets", 4483 child, rx_bad_octets, "Bad octets"); 4484 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_64", 4485 child, rx_pkts_64, "64 bytes frames"); 4486 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_65_127", 4487 child, rx_pkts_65_127, "65 to 127 bytes frames"); 4488 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_128_255", 4489 child, rx_pkts_128_255, "128 to 255 bytes frames"); 4490 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_256_511", 4491 child, rx_pkts_256_511, "256 to 511 bytes frames"); 4492 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_512_1023", 4493 child, rx_pkts_512_1023, "512 to 1023 bytes frames"); 4494 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_1024_1518", 4495 child, rx_pkts_1024_1518, "1024 to 1518 bytes frames"); 4496 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_1519_max", 4497 child, rx_pkts_1519_max, "1519 to max frames"); 4498 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_too_long", 4499 child, rx_pkts_too_long, "frames too long"); 4500 MSK_SYSCTL_STAT32(sc_if, ctx, "jabbers", 4501 child, rx_pkts_jabbers, "Jabber errors"); 4502 MSK_SYSCTL_STAT32(sc_if, ctx, "overflows", 4503 child, rx_fifo_oflows, "FIFO overflows"); 4504 4505 tree = SYSCTL_ADD_NODE(ctx, schild, OID_AUTO, "tx", 4506 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "MSK TX Statistics"); 4507 child = SYSCTL_CHILDREN(tree); 4508 MSK_SYSCTL_STAT32(sc_if, ctx, "ucast_frames", 4509 child, tx_ucast_frames, "Unicast frames"); 4510 MSK_SYSCTL_STAT32(sc_if, ctx, "bcast_frames", 4511 child, tx_bcast_frames, "Broadcast frames"); 4512 MSK_SYSCTL_STAT32(sc_if, ctx, "pause_frames", 4513 child, tx_pause_frames, "Pause frames"); 4514 MSK_SYSCTL_STAT32(sc_if, ctx, "mcast_frames", 4515 child, tx_mcast_frames, "Multicast frames"); 4516 MSK_SYSCTL_STAT64(sc_if, ctx, "octets", 4517 child, tx_octets, "Octets"); 4518 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_64", 4519 child, tx_pkts_64, "64 bytes frames"); 4520 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_65_127", 4521 child, tx_pkts_65_127, "65 to 127 bytes frames"); 4522 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_128_255", 4523 child, tx_pkts_128_255, "128 to 255 bytes frames"); 4524 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_256_511", 4525 child, tx_pkts_256_511, "256 to 511 bytes frames"); 4526 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_512_1023", 4527 child, tx_pkts_512_1023, "512 to 1023 bytes frames"); 4528 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_1024_1518", 4529 child, tx_pkts_1024_1518, "1024 to 1518 bytes frames"); 4530 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_1519_max", 4531 child, tx_pkts_1519_max, "1519 to max frames"); 4532 MSK_SYSCTL_STAT32(sc_if, ctx, "colls", 4533 child, tx_colls, "Collisions"); 4534 MSK_SYSCTL_STAT32(sc_if, ctx, "late_colls", 4535 child, tx_late_colls, "Late collisions"); 4536 MSK_SYSCTL_STAT32(sc_if, ctx, "excess_colls", 4537 child, tx_excess_colls, "Excessive collisions"); 4538 MSK_SYSCTL_STAT32(sc_if, ctx, "multi_colls", 4539 child, tx_multi_colls, "Multiple collisions"); 4540 MSK_SYSCTL_STAT32(sc_if, ctx, "single_colls", 4541 child, tx_single_colls, "Single collisions"); 4542 MSK_SYSCTL_STAT32(sc_if, ctx, "underflows", 4543 child, tx_underflows, "FIFO underflows"); 4544 } 4545 4546 #undef MSK_SYSCTL_STAT32 4547 #undef MSK_SYSCTL_STAT64 4548 4549 static int 4550 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 4551 { 4552 int error, value; 4553 4554 if (!arg1) 4555 return (EINVAL); 4556 value = *(int *)arg1; 4557 error = sysctl_handle_int(oidp, &value, 0, req); 4558 if (error || !req->newptr) 4559 return (error); 4560 if (value < low || value > high) 4561 return (EINVAL); 4562 *(int *)arg1 = value; 4563 4564 return (0); 4565 } 4566 4567 static int 4568 sysctl_hw_msk_proc_limit(SYSCTL_HANDLER_ARGS) 4569 { 4570 4571 return (sysctl_int_range(oidp, arg1, arg2, req, MSK_PROC_MIN, 4572 MSK_PROC_MAX)); 4573 } 4574