1 /****************************************************************************** 2 * 3 * Name : sky2.c 4 * Project: Gigabit Ethernet Driver for FreeBSD 5.x/6.x 5 * Version: $Revision: 1.23 $ 6 * Date : $Date: 2005/12/22 09:04:11 $ 7 * Purpose: Main driver source file 8 * 9 *****************************************************************************/ 10 11 /****************************************************************************** 12 * 13 * LICENSE: 14 * Copyright (C) Marvell International Ltd. and/or its affiliates 15 * 16 * The computer program files contained in this folder ("Files") 17 * are provided to you under the BSD-type license terms provided 18 * below, and any use of such Files and any derivative works 19 * thereof created by you shall be governed by the following terms 20 * and conditions: 21 * 22 * - Redistributions of source code must retain the above copyright 23 * notice, this list of conditions and the following disclaimer. 24 * - Redistributions in binary form must reproduce the above 25 * copyright notice, this list of conditions and the following 26 * disclaimer in the documentation and/or other materials provided 27 * with the distribution. 28 * - Neither the name of Marvell nor the names of its contributors 29 * may be used to endorse or promote products derived from this 30 * software without specific prior written permission. 31 * 32 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 33 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 34 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 35 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 36 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 37 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 38 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 39 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 40 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 41 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 42 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED 43 * OF THE POSSIBILITY OF SUCH DAMAGE. 44 * /LICENSE 45 * 46 *****************************************************************************/ 47 48 /*- 49 * SPDX-License-Identifier: BSD-4-Clause AND BSD-3-Clause 50 * 51 * Copyright (c) 1997, 1998, 1999, 2000 52 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 53 * 54 * Redistribution and use in source and binary forms, with or without 55 * modification, are permitted provided that the following conditions 56 * are met: 57 * 1. Redistributions of source code must retain the above copyright 58 * notice, this list of conditions and the following disclaimer. 59 * 2. Redistributions in binary form must reproduce the above copyright 60 * notice, this list of conditions and the following disclaimer in the 61 * documentation and/or other materials provided with the distribution. 62 * 3. All advertising materials mentioning features or use of this software 63 * must display the following acknowledgement: 64 * This product includes software developed by Bill Paul. 65 * 4. Neither the name of the author nor the names of any co-contributors 66 * may be used to endorse or promote products derived from this software 67 * without specific prior written permission. 68 * 69 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 70 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 71 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 72 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 73 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 74 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 75 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 76 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 77 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 78 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 79 * THE POSSIBILITY OF SUCH DAMAGE. 80 */ 81 /*- 82 * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu> 83 * 84 * Permission to use, copy, modify, and distribute this software for any 85 * purpose with or without fee is hereby granted, provided that the above 86 * copyright notice and this permission notice appear in all copies. 87 * 88 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 89 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 90 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 91 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 92 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 93 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 94 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 95 */ 96 97 /* 98 * Device driver for the Marvell Yukon II Ethernet controller. 99 * Due to lack of documentation, this driver is based on the code from 100 * sk(4) and Marvell's myk(4) driver for FreeBSD 5.x. 101 */ 102 103 #include <sys/cdefs.h> 104 #include <sys/param.h> 105 #include <sys/systm.h> 106 #include <sys/bus.h> 107 #include <sys/endian.h> 108 #include <sys/mbuf.h> 109 #include <sys/malloc.h> 110 #include <sys/kernel.h> 111 #include <sys/module.h> 112 #include <sys/socket.h> 113 #include <sys/sockio.h> 114 #include <sys/queue.h> 115 #include <sys/sysctl.h> 116 117 #include <net/bpf.h> 118 #include <net/ethernet.h> 119 #include <net/if.h> 120 #include <net/if_var.h> 121 #include <net/if_arp.h> 122 #include <net/if_dl.h> 123 #include <net/if_media.h> 124 #include <net/if_types.h> 125 #include <net/if_vlan_var.h> 126 127 #include <netinet/in.h> 128 #include <netinet/in_systm.h> 129 #include <netinet/ip.h> 130 #include <netinet/tcp.h> 131 #include <netinet/udp.h> 132 133 #include <machine/bus.h> 134 #include <machine/in_cksum.h> 135 #include <machine/resource.h> 136 #include <sys/rman.h> 137 138 #include <dev/mii/mii.h> 139 #include <dev/mii/miivar.h> 140 141 #include <dev/pci/pcireg.h> 142 #include <dev/pci/pcivar.h> 143 144 #include <dev/msk/if_mskreg.h> 145 146 MODULE_DEPEND(msk, pci, 1, 1, 1); 147 MODULE_DEPEND(msk, ether, 1, 1, 1); 148 MODULE_DEPEND(msk, miibus, 1, 1, 1); 149 150 /* "device miibus" required. See GENERIC if you get errors here. */ 151 #include "miibus_if.h" 152 153 /* Tunables. */ 154 static int msi_disable = 0; 155 TUNABLE_INT("hw.msk.msi_disable", &msi_disable); 156 static int legacy_intr = 0; 157 TUNABLE_INT("hw.msk.legacy_intr", &legacy_intr); 158 static int jumbo_disable = 0; 159 TUNABLE_INT("hw.msk.jumbo_disable", &jumbo_disable); 160 161 #define MSK_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 162 163 /* 164 * Devices supported by this driver. 165 */ 166 static const struct msk_product { 167 uint16_t msk_vendorid; 168 uint16_t msk_deviceid; 169 const char *msk_name; 170 } msk_products[] = { 171 { VENDORID_SK, DEVICEID_SK_YUKON2, 172 "SK-9Sxx Gigabit Ethernet" }, 173 { VENDORID_SK, DEVICEID_SK_YUKON2_EXPR, 174 "SK-9Exx Gigabit Ethernet"}, 175 { VENDORID_MARVELL, DEVICEID_MRVL_8021CU, 176 "Marvell Yukon 88E8021CU Gigabit Ethernet" }, 177 { VENDORID_MARVELL, DEVICEID_MRVL_8021X, 178 "Marvell Yukon 88E8021 SX/LX Gigabit Ethernet" }, 179 { VENDORID_MARVELL, DEVICEID_MRVL_8022CU, 180 "Marvell Yukon 88E8022CU Gigabit Ethernet" }, 181 { VENDORID_MARVELL, DEVICEID_MRVL_8022X, 182 "Marvell Yukon 88E8022 SX/LX Gigabit Ethernet" }, 183 { VENDORID_MARVELL, DEVICEID_MRVL_8061CU, 184 "Marvell Yukon 88E8061CU Gigabit Ethernet" }, 185 { VENDORID_MARVELL, DEVICEID_MRVL_8061X, 186 "Marvell Yukon 88E8061 SX/LX Gigabit Ethernet" }, 187 { VENDORID_MARVELL, DEVICEID_MRVL_8062CU, 188 "Marvell Yukon 88E8062CU Gigabit Ethernet" }, 189 { VENDORID_MARVELL, DEVICEID_MRVL_8062X, 190 "Marvell Yukon 88E8062 SX/LX Gigabit Ethernet" }, 191 { VENDORID_MARVELL, DEVICEID_MRVL_8035, 192 "Marvell Yukon 88E8035 Fast Ethernet" }, 193 { VENDORID_MARVELL, DEVICEID_MRVL_8036, 194 "Marvell Yukon 88E8036 Fast Ethernet" }, 195 { VENDORID_MARVELL, DEVICEID_MRVL_8038, 196 "Marvell Yukon 88E8038 Fast Ethernet" }, 197 { VENDORID_MARVELL, DEVICEID_MRVL_8039, 198 "Marvell Yukon 88E8039 Fast Ethernet" }, 199 { VENDORID_MARVELL, DEVICEID_MRVL_8040, 200 "Marvell Yukon 88E8040 Fast Ethernet" }, 201 { VENDORID_MARVELL, DEVICEID_MRVL_8040T, 202 "Marvell Yukon 88E8040T Fast Ethernet" }, 203 { VENDORID_MARVELL, DEVICEID_MRVL_8042, 204 "Marvell Yukon 88E8042 Fast Ethernet" }, 205 { VENDORID_MARVELL, DEVICEID_MRVL_8048, 206 "Marvell Yukon 88E8048 Fast Ethernet" }, 207 { VENDORID_MARVELL, DEVICEID_MRVL_4361, 208 "Marvell Yukon 88E8050 Gigabit Ethernet" }, 209 { VENDORID_MARVELL, DEVICEID_MRVL_4360, 210 "Marvell Yukon 88E8052 Gigabit Ethernet" }, 211 { VENDORID_MARVELL, DEVICEID_MRVL_4362, 212 "Marvell Yukon 88E8053 Gigabit Ethernet" }, 213 { VENDORID_MARVELL, DEVICEID_MRVL_4363, 214 "Marvell Yukon 88E8055 Gigabit Ethernet" }, 215 { VENDORID_MARVELL, DEVICEID_MRVL_4364, 216 "Marvell Yukon 88E8056 Gigabit Ethernet" }, 217 { VENDORID_MARVELL, DEVICEID_MRVL_4365, 218 "Marvell Yukon 88E8070 Gigabit Ethernet" }, 219 { VENDORID_MARVELL, DEVICEID_MRVL_436A, 220 "Marvell Yukon 88E8058 Gigabit Ethernet" }, 221 { VENDORID_MARVELL, DEVICEID_MRVL_436B, 222 "Marvell Yukon 88E8071 Gigabit Ethernet" }, 223 { VENDORID_MARVELL, DEVICEID_MRVL_436C, 224 "Marvell Yukon 88E8072 Gigabit Ethernet" }, 225 { VENDORID_MARVELL, DEVICEID_MRVL_436D, 226 "Marvell Yukon 88E8055 Gigabit Ethernet" }, 227 { VENDORID_MARVELL, DEVICEID_MRVL_4370, 228 "Marvell Yukon 88E8075 Gigabit Ethernet" }, 229 { VENDORID_MARVELL, DEVICEID_MRVL_4380, 230 "Marvell Yukon 88E8057 Gigabit Ethernet" }, 231 { VENDORID_MARVELL, DEVICEID_MRVL_4381, 232 "Marvell Yukon 88E8059 Gigabit Ethernet" }, 233 { VENDORID_DLINK, DEVICEID_DLINK_DGE550SX, 234 "D-Link 550SX Gigabit Ethernet" }, 235 { VENDORID_DLINK, DEVICEID_DLINK_DGE560SX, 236 "D-Link 560SX Gigabit Ethernet" }, 237 { VENDORID_DLINK, DEVICEID_DLINK_DGE560T, 238 "D-Link 560T Gigabit Ethernet" } 239 }; 240 241 static const char *model_name[] = { 242 "Yukon XL", 243 "Yukon EC Ultra", 244 "Yukon EX", 245 "Yukon EC", 246 "Yukon FE", 247 "Yukon FE+", 248 "Yukon Supreme", 249 "Yukon Ultra 2", 250 "Yukon Unknown", 251 "Yukon Optima", 252 }; 253 254 static int mskc_probe(device_t); 255 static int mskc_attach(device_t); 256 static int mskc_detach(device_t); 257 static int mskc_shutdown(device_t); 258 static int mskc_setup_rambuffer(struct msk_softc *); 259 static int mskc_suspend(device_t); 260 static int mskc_resume(device_t); 261 static bus_dma_tag_t mskc_get_dma_tag(device_t, device_t); 262 static void mskc_reset(struct msk_softc *); 263 264 static int msk_probe(device_t); 265 static int msk_attach(device_t); 266 static int msk_detach(device_t); 267 268 static void msk_tick(void *); 269 static void msk_intr(void *); 270 static void msk_intr_phy(struct msk_if_softc *); 271 static void msk_intr_gmac(struct msk_if_softc *); 272 static __inline void msk_rxput(struct msk_if_softc *); 273 static int msk_handle_events(struct msk_softc *); 274 static void msk_handle_hwerr(struct msk_if_softc *, uint32_t); 275 static void msk_intr_hwerr(struct msk_softc *); 276 #ifndef __NO_STRICT_ALIGNMENT 277 static __inline void msk_fixup_rx(struct mbuf *); 278 #endif 279 static __inline void msk_rxcsum(struct msk_if_softc *, uint32_t, struct mbuf *); 280 static void msk_rxeof(struct msk_if_softc *, uint32_t, uint32_t, int); 281 static void msk_jumbo_rxeof(struct msk_if_softc *, uint32_t, uint32_t, int); 282 static void msk_txeof(struct msk_if_softc *, int); 283 static int msk_encap(struct msk_if_softc *, struct mbuf **); 284 static void msk_start(if_t); 285 static void msk_start_locked(if_t); 286 static int msk_ioctl(if_t, u_long, caddr_t); 287 static void msk_set_prefetch(struct msk_softc *, int, bus_addr_t, uint32_t); 288 static void msk_set_rambuffer(struct msk_if_softc *); 289 static void msk_set_tx_stfwd(struct msk_if_softc *); 290 static void msk_init(void *); 291 static void msk_init_locked(struct msk_if_softc *); 292 static void msk_stop(struct msk_if_softc *); 293 static void msk_watchdog(struct msk_if_softc *); 294 static int msk_mediachange(if_t); 295 static void msk_mediastatus(if_t, struct ifmediareq *); 296 static void msk_phy_power(struct msk_softc *, int); 297 static void msk_dmamap_cb(void *, bus_dma_segment_t *, int, int); 298 static int msk_status_dma_alloc(struct msk_softc *); 299 static void msk_status_dma_free(struct msk_softc *); 300 static int msk_txrx_dma_alloc(struct msk_if_softc *); 301 static int msk_rx_dma_jalloc(struct msk_if_softc *); 302 static void msk_txrx_dma_free(struct msk_if_softc *); 303 static void msk_rx_dma_jfree(struct msk_if_softc *); 304 static int msk_rx_fill(struct msk_if_softc *, int); 305 static int msk_init_rx_ring(struct msk_if_softc *); 306 static int msk_init_jumbo_rx_ring(struct msk_if_softc *); 307 static void msk_init_tx_ring(struct msk_if_softc *); 308 static __inline void msk_discard_rxbuf(struct msk_if_softc *, int); 309 static __inline void msk_discard_jumbo_rxbuf(struct msk_if_softc *, int); 310 static int msk_newbuf(struct msk_if_softc *, int); 311 static int msk_jumbo_newbuf(struct msk_if_softc *, int); 312 313 static int msk_phy_readreg(struct msk_if_softc *, int, int); 314 static int msk_phy_writereg(struct msk_if_softc *, int, int, int); 315 static int msk_miibus_readreg(device_t, int, int); 316 static int msk_miibus_writereg(device_t, int, int, int); 317 static void msk_miibus_statchg(device_t); 318 319 static void msk_rxfilter(struct msk_if_softc *); 320 static void msk_setvlan(struct msk_if_softc *, if_t); 321 322 static void msk_stats_clear(struct msk_if_softc *); 323 static void msk_stats_update(struct msk_if_softc *); 324 static int msk_sysctl_stat32(SYSCTL_HANDLER_ARGS); 325 static int msk_sysctl_stat64(SYSCTL_HANDLER_ARGS); 326 static void msk_sysctl_node(struct msk_if_softc *); 327 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int); 328 static int sysctl_hw_msk_proc_limit(SYSCTL_HANDLER_ARGS); 329 330 static device_method_t mskc_methods[] = { 331 /* Device interface */ 332 DEVMETHOD(device_probe, mskc_probe), 333 DEVMETHOD(device_attach, mskc_attach), 334 DEVMETHOD(device_detach, mskc_detach), 335 DEVMETHOD(device_suspend, mskc_suspend), 336 DEVMETHOD(device_resume, mskc_resume), 337 DEVMETHOD(device_shutdown, mskc_shutdown), 338 339 DEVMETHOD(bus_get_dma_tag, mskc_get_dma_tag), 340 341 DEVMETHOD_END 342 }; 343 344 static driver_t mskc_driver = { 345 "mskc", 346 mskc_methods, 347 sizeof(struct msk_softc) 348 }; 349 350 static device_method_t msk_methods[] = { 351 /* Device interface */ 352 DEVMETHOD(device_probe, msk_probe), 353 DEVMETHOD(device_attach, msk_attach), 354 DEVMETHOD(device_detach, msk_detach), 355 DEVMETHOD(device_shutdown, bus_generic_shutdown), 356 357 /* MII interface */ 358 DEVMETHOD(miibus_readreg, msk_miibus_readreg), 359 DEVMETHOD(miibus_writereg, msk_miibus_writereg), 360 DEVMETHOD(miibus_statchg, msk_miibus_statchg), 361 362 DEVMETHOD_END 363 }; 364 365 static driver_t msk_driver = { 366 "msk", 367 msk_methods, 368 sizeof(struct msk_if_softc) 369 }; 370 371 DRIVER_MODULE(mskc, pci, mskc_driver, NULL, NULL); 372 DRIVER_MODULE(msk, mskc, msk_driver, NULL, NULL); 373 DRIVER_MODULE(miibus, msk, miibus_driver, NULL, NULL); 374 375 static struct resource_spec msk_res_spec_io[] = { 376 { SYS_RES_IOPORT, PCIR_BAR(1), RF_ACTIVE }, 377 { -1, 0, 0 } 378 }; 379 380 static struct resource_spec msk_res_spec_mem[] = { 381 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 382 { -1, 0, 0 } 383 }; 384 385 static struct resource_spec msk_irq_spec_legacy[] = { 386 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 387 { -1, 0, 0 } 388 }; 389 390 static struct resource_spec msk_irq_spec_msi[] = { 391 { SYS_RES_IRQ, 1, RF_ACTIVE }, 392 { -1, 0, 0 } 393 }; 394 395 static int 396 msk_miibus_readreg(device_t dev, int phy, int reg) 397 { 398 struct msk_if_softc *sc_if; 399 400 sc_if = device_get_softc(dev); 401 402 return (msk_phy_readreg(sc_if, phy, reg)); 403 } 404 405 static int 406 msk_phy_readreg(struct msk_if_softc *sc_if, int phy, int reg) 407 { 408 struct msk_softc *sc; 409 int i, val; 410 411 sc = sc_if->msk_softc; 412 413 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SMI_CTRL, 414 GM_SMI_CT_PHY_AD(phy) | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD); 415 416 for (i = 0; i < MSK_TIMEOUT; i++) { 417 DELAY(1); 418 val = GMAC_READ_2(sc, sc_if->msk_port, GM_SMI_CTRL); 419 if ((val & GM_SMI_CT_RD_VAL) != 0) { 420 val = GMAC_READ_2(sc, sc_if->msk_port, GM_SMI_DATA); 421 break; 422 } 423 } 424 425 if (i == MSK_TIMEOUT) { 426 if_printf(sc_if->msk_ifp, "phy failed to come ready\n"); 427 val = 0; 428 } 429 430 return (val); 431 } 432 433 static int 434 msk_miibus_writereg(device_t dev, int phy, int reg, int val) 435 { 436 struct msk_if_softc *sc_if; 437 438 sc_if = device_get_softc(dev); 439 440 return (msk_phy_writereg(sc_if, phy, reg, val)); 441 } 442 443 static int 444 msk_phy_writereg(struct msk_if_softc *sc_if, int phy, int reg, int val) 445 { 446 struct msk_softc *sc; 447 int i; 448 449 sc = sc_if->msk_softc; 450 451 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SMI_DATA, val); 452 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SMI_CTRL, 453 GM_SMI_CT_PHY_AD(phy) | GM_SMI_CT_REG_AD(reg)); 454 for (i = 0; i < MSK_TIMEOUT; i++) { 455 DELAY(1); 456 if ((GMAC_READ_2(sc, sc_if->msk_port, GM_SMI_CTRL) & 457 GM_SMI_CT_BUSY) == 0) 458 break; 459 } 460 if (i == MSK_TIMEOUT) 461 if_printf(sc_if->msk_ifp, "phy write timeout\n"); 462 463 return (0); 464 } 465 466 static void 467 msk_miibus_statchg(device_t dev) 468 { 469 struct msk_softc *sc; 470 struct msk_if_softc *sc_if; 471 struct mii_data *mii; 472 if_t ifp; 473 uint32_t gmac; 474 475 sc_if = device_get_softc(dev); 476 sc = sc_if->msk_softc; 477 478 MSK_IF_LOCK_ASSERT(sc_if); 479 480 mii = device_get_softc(sc_if->msk_miibus); 481 ifp = sc_if->msk_ifp; 482 if (mii == NULL || ifp == NULL || 483 (if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) 484 return; 485 486 sc_if->msk_flags &= ~MSK_FLAG_LINK; 487 if ((mii->mii_media_status & (IFM_AVALID | IFM_ACTIVE)) == 488 (IFM_AVALID | IFM_ACTIVE)) { 489 switch (IFM_SUBTYPE(mii->mii_media_active)) { 490 case IFM_10_T: 491 case IFM_100_TX: 492 sc_if->msk_flags |= MSK_FLAG_LINK; 493 break; 494 case IFM_1000_T: 495 case IFM_1000_SX: 496 case IFM_1000_LX: 497 case IFM_1000_CX: 498 if ((sc_if->msk_flags & MSK_FLAG_FASTETHER) == 0) 499 sc_if->msk_flags |= MSK_FLAG_LINK; 500 break; 501 default: 502 break; 503 } 504 } 505 506 if ((sc_if->msk_flags & MSK_FLAG_LINK) != 0) { 507 /* Enable Tx FIFO Underrun. */ 508 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_MSK), 509 GM_IS_TX_FF_UR | GM_IS_RX_FF_OR); 510 /* 511 * Because mii(4) notify msk(4) that it detected link status 512 * change, there is no need to enable automatic 513 * speed/flow-control/duplex updates. 514 */ 515 gmac = GM_GPCR_AU_ALL_DIS; 516 switch (IFM_SUBTYPE(mii->mii_media_active)) { 517 case IFM_1000_SX: 518 case IFM_1000_T: 519 gmac |= GM_GPCR_SPEED_1000; 520 break; 521 case IFM_100_TX: 522 gmac |= GM_GPCR_SPEED_100; 523 break; 524 case IFM_10_T: 525 break; 526 } 527 528 if ((IFM_OPTIONS(mii->mii_media_active) & 529 IFM_ETH_RXPAUSE) == 0) 530 gmac |= GM_GPCR_FC_RX_DIS; 531 if ((IFM_OPTIONS(mii->mii_media_active) & 532 IFM_ETH_TXPAUSE) == 0) 533 gmac |= GM_GPCR_FC_TX_DIS; 534 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) 535 gmac |= GM_GPCR_DUP_FULL; 536 else 537 gmac |= GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS; 538 gmac |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA; 539 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, gmac); 540 /* Read again to ensure writing. */ 541 GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL); 542 gmac = GMC_PAUSE_OFF; 543 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 544 if ((IFM_OPTIONS(mii->mii_media_active) & 545 IFM_ETH_RXPAUSE) != 0) 546 gmac = GMC_PAUSE_ON; 547 } 548 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), gmac); 549 550 /* Enable PHY interrupt for FIFO underrun/overflow. */ 551 msk_phy_writereg(sc_if, PHY_ADDR_MARV, 552 PHY_MARV_INT_MASK, PHY_M_IS_FIFO_ERROR); 553 } else { 554 /* 555 * Link state changed to down. 556 * Disable PHY interrupts. 557 */ 558 msk_phy_writereg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_MASK, 0); 559 /* Disable Rx/Tx MAC. */ 560 gmac = GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL); 561 if ((gmac & (GM_GPCR_RX_ENA | GM_GPCR_TX_ENA)) != 0) { 562 gmac &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA); 563 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, gmac); 564 /* Read again to ensure writing. */ 565 GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL); 566 } 567 } 568 } 569 570 static u_int 571 msk_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) 572 { 573 uint32_t *mchash = arg; 574 uint32_t crc; 575 576 crc = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN); 577 /* Just want the 6 least significant bits. */ 578 crc &= 0x3f; 579 /* Set the corresponding bit in the hash table. */ 580 mchash[crc >> 5] |= 1 << (crc & 0x1f); 581 582 return (1); 583 } 584 585 static void 586 msk_rxfilter(struct msk_if_softc *sc_if) 587 { 588 struct msk_softc *sc; 589 if_t ifp; 590 uint32_t mchash[2]; 591 uint16_t mode; 592 593 sc = sc_if->msk_softc; 594 595 MSK_IF_LOCK_ASSERT(sc_if); 596 597 ifp = sc_if->msk_ifp; 598 599 bzero(mchash, sizeof(mchash)); 600 mode = GMAC_READ_2(sc, sc_if->msk_port, GM_RX_CTRL); 601 if ((if_getflags(ifp) & IFF_PROMISC) != 0) 602 mode &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA); 603 else if ((if_getflags(ifp) & IFF_ALLMULTI) != 0) { 604 mode |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA; 605 mchash[0] = 0xffff; 606 mchash[1] = 0xffff; 607 } else { 608 mode |= GM_RXCR_UCF_ENA; 609 if_foreach_llmaddr(ifp, msk_hash_maddr, mchash); 610 if (mchash[0] != 0 || mchash[1] != 0) 611 mode |= GM_RXCR_MCF_ENA; 612 } 613 614 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H1, 615 mchash[0] & 0xffff); 616 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H2, 617 (mchash[0] >> 16) & 0xffff); 618 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H3, 619 mchash[1] & 0xffff); 620 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H4, 621 (mchash[1] >> 16) & 0xffff); 622 GMAC_WRITE_2(sc, sc_if->msk_port, GM_RX_CTRL, mode); 623 } 624 625 static void 626 msk_setvlan(struct msk_if_softc *sc_if, if_t ifp) 627 { 628 struct msk_softc *sc; 629 630 sc = sc_if->msk_softc; 631 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0) { 632 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), 633 RX_VLAN_STRIP_ON); 634 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 635 TX_VLAN_TAG_ON); 636 } else { 637 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), 638 RX_VLAN_STRIP_OFF); 639 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 640 TX_VLAN_TAG_OFF); 641 } 642 } 643 644 static int 645 msk_rx_fill(struct msk_if_softc *sc_if, int jumbo) 646 { 647 uint16_t idx; 648 int i; 649 650 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0 && 651 (if_getcapenable(sc_if->msk_ifp) & IFCAP_RXCSUM) != 0) { 652 /* Wait until controller executes OP_TCPSTART command. */ 653 for (i = 100; i > 0; i--) { 654 DELAY(100); 655 idx = CSR_READ_2(sc_if->msk_softc, 656 Y2_PREF_Q_ADDR(sc_if->msk_rxq, 657 PREF_UNIT_GET_IDX_REG)); 658 if (idx != 0) 659 break; 660 } 661 if (i == 0) { 662 device_printf(sc_if->msk_if_dev, 663 "prefetch unit stuck?\n"); 664 return (ETIMEDOUT); 665 } 666 /* 667 * Fill consumed LE with free buffer. This can be done 668 * in Rx handler but we don't want to add special code 669 * in fast handler. 670 */ 671 if (jumbo > 0) { 672 if (msk_jumbo_newbuf(sc_if, 0) != 0) 673 return (ENOBUFS); 674 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 675 sc_if->msk_cdata.msk_jumbo_rx_ring_map, 676 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 677 } else { 678 if (msk_newbuf(sc_if, 0) != 0) 679 return (ENOBUFS); 680 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_ring_tag, 681 sc_if->msk_cdata.msk_rx_ring_map, 682 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 683 } 684 sc_if->msk_cdata.msk_rx_prod = 0; 685 CSR_WRITE_2(sc_if->msk_softc, 686 Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_PUT_IDX_REG), 687 sc_if->msk_cdata.msk_rx_prod); 688 } 689 return (0); 690 } 691 692 static int 693 msk_init_rx_ring(struct msk_if_softc *sc_if) 694 { 695 struct msk_ring_data *rd; 696 struct msk_rxdesc *rxd; 697 int i, nbuf, prod; 698 699 MSK_IF_LOCK_ASSERT(sc_if); 700 701 sc_if->msk_cdata.msk_rx_cons = 0; 702 sc_if->msk_cdata.msk_rx_prod = 0; 703 sc_if->msk_cdata.msk_rx_putwm = MSK_PUT_WM; 704 705 rd = &sc_if->msk_rdata; 706 bzero(rd->msk_rx_ring, sizeof(struct msk_rx_desc) * MSK_RX_RING_CNT); 707 for (i = prod = 0; i < MSK_RX_RING_CNT; i++) { 708 rxd = &sc_if->msk_cdata.msk_rxdesc[prod]; 709 rxd->rx_m = NULL; 710 rxd->rx_le = &rd->msk_rx_ring[prod]; 711 MSK_INC(prod, MSK_RX_RING_CNT); 712 } 713 nbuf = MSK_RX_BUF_CNT; 714 prod = 0; 715 /* Have controller know how to compute Rx checksum. */ 716 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0 && 717 (if_getcapenable(sc_if->msk_ifp) & IFCAP_RXCSUM) != 0) { 718 #ifdef MSK_64BIT_DMA 719 rxd = &sc_if->msk_cdata.msk_rxdesc[prod]; 720 rxd->rx_m = NULL; 721 rxd->rx_le = &rd->msk_rx_ring[prod]; 722 rxd->rx_le->msk_addr = htole32(ETHER_HDR_LEN << 16 | 723 ETHER_HDR_LEN); 724 rxd->rx_le->msk_control = htole32(OP_TCPSTART | HW_OWNER); 725 MSK_INC(prod, MSK_RX_RING_CNT); 726 MSK_INC(sc_if->msk_cdata.msk_rx_cons, MSK_RX_RING_CNT); 727 #endif 728 rxd = &sc_if->msk_cdata.msk_rxdesc[prod]; 729 rxd->rx_m = NULL; 730 rxd->rx_le = &rd->msk_rx_ring[prod]; 731 rxd->rx_le->msk_addr = htole32(ETHER_HDR_LEN << 16 | 732 ETHER_HDR_LEN); 733 rxd->rx_le->msk_control = htole32(OP_TCPSTART | HW_OWNER); 734 MSK_INC(prod, MSK_RX_RING_CNT); 735 MSK_INC(sc_if->msk_cdata.msk_rx_cons, MSK_RX_RING_CNT); 736 nbuf--; 737 } 738 for (i = 0; i < nbuf; i++) { 739 if (msk_newbuf(sc_if, prod) != 0) 740 return (ENOBUFS); 741 MSK_RX_INC(prod, MSK_RX_RING_CNT); 742 } 743 744 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_ring_tag, 745 sc_if->msk_cdata.msk_rx_ring_map, 746 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 747 748 /* Update prefetch unit. */ 749 sc_if->msk_cdata.msk_rx_prod = prod; 750 CSR_WRITE_2(sc_if->msk_softc, 751 Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_PUT_IDX_REG), 752 (sc_if->msk_cdata.msk_rx_prod + MSK_RX_RING_CNT - 1) % 753 MSK_RX_RING_CNT); 754 if (msk_rx_fill(sc_if, 0) != 0) 755 return (ENOBUFS); 756 return (0); 757 } 758 759 static int 760 msk_init_jumbo_rx_ring(struct msk_if_softc *sc_if) 761 { 762 struct msk_ring_data *rd; 763 struct msk_rxdesc *rxd; 764 int i, nbuf, prod; 765 766 MSK_IF_LOCK_ASSERT(sc_if); 767 768 sc_if->msk_cdata.msk_rx_cons = 0; 769 sc_if->msk_cdata.msk_rx_prod = 0; 770 sc_if->msk_cdata.msk_rx_putwm = MSK_PUT_WM; 771 772 rd = &sc_if->msk_rdata; 773 bzero(rd->msk_jumbo_rx_ring, 774 sizeof(struct msk_rx_desc) * MSK_JUMBO_RX_RING_CNT); 775 for (i = prod = 0; i < MSK_JUMBO_RX_RING_CNT; i++) { 776 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[prod]; 777 rxd->rx_m = NULL; 778 rxd->rx_le = &rd->msk_jumbo_rx_ring[prod]; 779 MSK_INC(prod, MSK_JUMBO_RX_RING_CNT); 780 } 781 nbuf = MSK_RX_BUF_CNT; 782 prod = 0; 783 /* Have controller know how to compute Rx checksum. */ 784 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0 && 785 (if_getcapenable(sc_if->msk_ifp) & IFCAP_RXCSUM) != 0) { 786 #ifdef MSK_64BIT_DMA 787 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[prod]; 788 rxd->rx_m = NULL; 789 rxd->rx_le = &rd->msk_jumbo_rx_ring[prod]; 790 rxd->rx_le->msk_addr = htole32(ETHER_HDR_LEN << 16 | 791 ETHER_HDR_LEN); 792 rxd->rx_le->msk_control = htole32(OP_TCPSTART | HW_OWNER); 793 MSK_INC(prod, MSK_JUMBO_RX_RING_CNT); 794 MSK_INC(sc_if->msk_cdata.msk_rx_cons, MSK_JUMBO_RX_RING_CNT); 795 #endif 796 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[prod]; 797 rxd->rx_m = NULL; 798 rxd->rx_le = &rd->msk_jumbo_rx_ring[prod]; 799 rxd->rx_le->msk_addr = htole32(ETHER_HDR_LEN << 16 | 800 ETHER_HDR_LEN); 801 rxd->rx_le->msk_control = htole32(OP_TCPSTART | HW_OWNER); 802 MSK_INC(prod, MSK_JUMBO_RX_RING_CNT); 803 MSK_INC(sc_if->msk_cdata.msk_rx_cons, MSK_JUMBO_RX_RING_CNT); 804 nbuf--; 805 } 806 for (i = 0; i < nbuf; i++) { 807 if (msk_jumbo_newbuf(sc_if, prod) != 0) 808 return (ENOBUFS); 809 MSK_RX_INC(prod, MSK_JUMBO_RX_RING_CNT); 810 } 811 812 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 813 sc_if->msk_cdata.msk_jumbo_rx_ring_map, 814 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 815 816 /* Update prefetch unit. */ 817 sc_if->msk_cdata.msk_rx_prod = prod; 818 CSR_WRITE_2(sc_if->msk_softc, 819 Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_PUT_IDX_REG), 820 (sc_if->msk_cdata.msk_rx_prod + MSK_JUMBO_RX_RING_CNT - 1) % 821 MSK_JUMBO_RX_RING_CNT); 822 if (msk_rx_fill(sc_if, 1) != 0) 823 return (ENOBUFS); 824 return (0); 825 } 826 827 static void 828 msk_init_tx_ring(struct msk_if_softc *sc_if) 829 { 830 struct msk_ring_data *rd; 831 struct msk_txdesc *txd; 832 int i; 833 834 sc_if->msk_cdata.msk_tso_mtu = 0; 835 sc_if->msk_cdata.msk_last_csum = 0; 836 sc_if->msk_cdata.msk_tx_prod = 0; 837 sc_if->msk_cdata.msk_tx_cons = 0; 838 sc_if->msk_cdata.msk_tx_cnt = 0; 839 sc_if->msk_cdata.msk_tx_high_addr = 0; 840 841 rd = &sc_if->msk_rdata; 842 bzero(rd->msk_tx_ring, sizeof(struct msk_tx_desc) * MSK_TX_RING_CNT); 843 for (i = 0; i < MSK_TX_RING_CNT; i++) { 844 txd = &sc_if->msk_cdata.msk_txdesc[i]; 845 txd->tx_m = NULL; 846 txd->tx_le = &rd->msk_tx_ring[i]; 847 } 848 849 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_ring_tag, 850 sc_if->msk_cdata.msk_tx_ring_map, 851 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 852 } 853 854 static __inline void 855 msk_discard_rxbuf(struct msk_if_softc *sc_if, int idx) 856 { 857 struct msk_rx_desc *rx_le; 858 struct msk_rxdesc *rxd; 859 struct mbuf *m; 860 861 #ifdef MSK_64BIT_DMA 862 rxd = &sc_if->msk_cdata.msk_rxdesc[idx]; 863 rx_le = rxd->rx_le; 864 rx_le->msk_control = htole32(OP_ADDR64 | HW_OWNER); 865 MSK_INC(idx, MSK_RX_RING_CNT); 866 #endif 867 rxd = &sc_if->msk_cdata.msk_rxdesc[idx]; 868 m = rxd->rx_m; 869 rx_le = rxd->rx_le; 870 rx_le->msk_control = htole32(m->m_len | OP_PACKET | HW_OWNER); 871 } 872 873 static __inline void 874 msk_discard_jumbo_rxbuf(struct msk_if_softc *sc_if, int idx) 875 { 876 struct msk_rx_desc *rx_le; 877 struct msk_rxdesc *rxd; 878 struct mbuf *m; 879 880 #ifdef MSK_64BIT_DMA 881 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[idx]; 882 rx_le = rxd->rx_le; 883 rx_le->msk_control = htole32(OP_ADDR64 | HW_OWNER); 884 MSK_INC(idx, MSK_JUMBO_RX_RING_CNT); 885 #endif 886 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[idx]; 887 m = rxd->rx_m; 888 rx_le = rxd->rx_le; 889 rx_le->msk_control = htole32(m->m_len | OP_PACKET | HW_OWNER); 890 } 891 892 static int 893 msk_newbuf(struct msk_if_softc *sc_if, int idx) 894 { 895 struct msk_rx_desc *rx_le; 896 struct msk_rxdesc *rxd; 897 struct mbuf *m; 898 bus_dma_segment_t segs[1]; 899 bus_dmamap_t map; 900 int nsegs; 901 902 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 903 if (m == NULL) 904 return (ENOBUFS); 905 906 m->m_len = m->m_pkthdr.len = MCLBYTES; 907 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) == 0) 908 m_adj(m, ETHER_ALIGN); 909 #ifndef __NO_STRICT_ALIGNMENT 910 else 911 m_adj(m, MSK_RX_BUF_ALIGN); 912 #endif 913 914 if (bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_rx_tag, 915 sc_if->msk_cdata.msk_rx_sparemap, m, segs, &nsegs, 916 BUS_DMA_NOWAIT) != 0) { 917 m_freem(m); 918 return (ENOBUFS); 919 } 920 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 921 922 rxd = &sc_if->msk_cdata.msk_rxdesc[idx]; 923 #ifdef MSK_64BIT_DMA 924 rx_le = rxd->rx_le; 925 rx_le->msk_addr = htole32(MSK_ADDR_HI(segs[0].ds_addr)); 926 rx_le->msk_control = htole32(OP_ADDR64 | HW_OWNER); 927 MSK_INC(idx, MSK_RX_RING_CNT); 928 rxd = &sc_if->msk_cdata.msk_rxdesc[idx]; 929 #endif 930 if (rxd->rx_m != NULL) { 931 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_tag, rxd->rx_dmamap, 932 BUS_DMASYNC_POSTREAD); 933 bus_dmamap_unload(sc_if->msk_cdata.msk_rx_tag, rxd->rx_dmamap); 934 rxd->rx_m = NULL; 935 } 936 map = rxd->rx_dmamap; 937 rxd->rx_dmamap = sc_if->msk_cdata.msk_rx_sparemap; 938 sc_if->msk_cdata.msk_rx_sparemap = map; 939 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_tag, rxd->rx_dmamap, 940 BUS_DMASYNC_PREREAD); 941 rxd->rx_m = m; 942 rx_le = rxd->rx_le; 943 rx_le->msk_addr = htole32(MSK_ADDR_LO(segs[0].ds_addr)); 944 rx_le->msk_control = 945 htole32(segs[0].ds_len | OP_PACKET | HW_OWNER); 946 947 return (0); 948 } 949 950 static int 951 msk_jumbo_newbuf(struct msk_if_softc *sc_if, int idx) 952 { 953 struct msk_rx_desc *rx_le; 954 struct msk_rxdesc *rxd; 955 struct mbuf *m; 956 bus_dma_segment_t segs[1]; 957 bus_dmamap_t map; 958 int nsegs; 959 960 m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES); 961 if (m == NULL) 962 return (ENOBUFS); 963 m->m_len = m->m_pkthdr.len = MJUM9BYTES; 964 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) == 0) 965 m_adj(m, ETHER_ALIGN); 966 #ifndef __NO_STRICT_ALIGNMENT 967 else 968 m_adj(m, MSK_RX_BUF_ALIGN); 969 #endif 970 971 if (bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_jumbo_rx_tag, 972 sc_if->msk_cdata.msk_jumbo_rx_sparemap, m, segs, &nsegs, 973 BUS_DMA_NOWAIT) != 0) { 974 m_freem(m); 975 return (ENOBUFS); 976 } 977 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 978 979 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[idx]; 980 #ifdef MSK_64BIT_DMA 981 rx_le = rxd->rx_le; 982 rx_le->msk_addr = htole32(MSK_ADDR_HI(segs[0].ds_addr)); 983 rx_le->msk_control = htole32(OP_ADDR64 | HW_OWNER); 984 MSK_INC(idx, MSK_JUMBO_RX_RING_CNT); 985 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[idx]; 986 #endif 987 if (rxd->rx_m != NULL) { 988 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_tag, 989 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 990 bus_dmamap_unload(sc_if->msk_cdata.msk_jumbo_rx_tag, 991 rxd->rx_dmamap); 992 rxd->rx_m = NULL; 993 } 994 map = rxd->rx_dmamap; 995 rxd->rx_dmamap = sc_if->msk_cdata.msk_jumbo_rx_sparemap; 996 sc_if->msk_cdata.msk_jumbo_rx_sparemap = map; 997 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_tag, rxd->rx_dmamap, 998 BUS_DMASYNC_PREREAD); 999 rxd->rx_m = m; 1000 rx_le = rxd->rx_le; 1001 rx_le->msk_addr = htole32(MSK_ADDR_LO(segs[0].ds_addr)); 1002 rx_le->msk_control = 1003 htole32(segs[0].ds_len | OP_PACKET | HW_OWNER); 1004 1005 return (0); 1006 } 1007 1008 /* 1009 * Set media options. 1010 */ 1011 static int 1012 msk_mediachange(if_t ifp) 1013 { 1014 struct msk_if_softc *sc_if; 1015 struct mii_data *mii; 1016 int error; 1017 1018 sc_if = if_getsoftc(ifp); 1019 1020 MSK_IF_LOCK(sc_if); 1021 mii = device_get_softc(sc_if->msk_miibus); 1022 error = mii_mediachg(mii); 1023 MSK_IF_UNLOCK(sc_if); 1024 1025 return (error); 1026 } 1027 1028 /* 1029 * Report current media status. 1030 */ 1031 static void 1032 msk_mediastatus(if_t ifp, struct ifmediareq *ifmr) 1033 { 1034 struct msk_if_softc *sc_if; 1035 struct mii_data *mii; 1036 1037 sc_if = if_getsoftc(ifp); 1038 MSK_IF_LOCK(sc_if); 1039 if ((if_getflags(ifp) & IFF_UP) == 0) { 1040 MSK_IF_UNLOCK(sc_if); 1041 return; 1042 } 1043 mii = device_get_softc(sc_if->msk_miibus); 1044 1045 mii_pollstat(mii); 1046 ifmr->ifm_active = mii->mii_media_active; 1047 ifmr->ifm_status = mii->mii_media_status; 1048 MSK_IF_UNLOCK(sc_if); 1049 } 1050 1051 static int 1052 msk_ioctl(if_t ifp, u_long command, caddr_t data) 1053 { 1054 struct msk_if_softc *sc_if; 1055 struct ifreq *ifr; 1056 struct mii_data *mii; 1057 int error, mask, reinit; 1058 1059 sc_if = if_getsoftc(ifp); 1060 ifr = (struct ifreq *)data; 1061 error = 0; 1062 1063 switch(command) { 1064 case SIOCSIFMTU: 1065 MSK_IF_LOCK(sc_if); 1066 if (ifr->ifr_mtu > MSK_JUMBO_MTU || ifr->ifr_mtu < ETHERMIN) 1067 error = EINVAL; 1068 else if (if_getmtu(ifp) != ifr->ifr_mtu) { 1069 if (ifr->ifr_mtu > ETHERMTU) { 1070 if ((sc_if->msk_flags & MSK_FLAG_JUMBO) == 0) { 1071 error = EINVAL; 1072 MSK_IF_UNLOCK(sc_if); 1073 break; 1074 } 1075 if ((sc_if->msk_flags & 1076 MSK_FLAG_JUMBO_NOCSUM) != 0) { 1077 if_sethwassistbits(ifp, 0, 1078 MSK_CSUM_FEATURES | CSUM_TSO); 1079 if_setcapenablebit(ifp, 0, 1080 IFCAP_TSO4 | IFCAP_TXCSUM); 1081 VLAN_CAPABILITIES(ifp); 1082 } 1083 } 1084 if_setmtu(ifp, ifr->ifr_mtu); 1085 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 1086 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 1087 msk_init_locked(sc_if); 1088 } 1089 } 1090 MSK_IF_UNLOCK(sc_if); 1091 break; 1092 case SIOCSIFFLAGS: 1093 MSK_IF_LOCK(sc_if); 1094 if ((if_getflags(ifp) & IFF_UP) != 0) { 1095 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0 && 1096 ((if_getflags(ifp) ^ sc_if->msk_if_flags) & 1097 (IFF_PROMISC | IFF_ALLMULTI)) != 0) 1098 msk_rxfilter(sc_if); 1099 else if ((sc_if->msk_flags & MSK_FLAG_DETACH) == 0) 1100 msk_init_locked(sc_if); 1101 } else if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 1102 msk_stop(sc_if); 1103 sc_if->msk_if_flags = if_getflags(ifp); 1104 MSK_IF_UNLOCK(sc_if); 1105 break; 1106 case SIOCADDMULTI: 1107 case SIOCDELMULTI: 1108 MSK_IF_LOCK(sc_if); 1109 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 1110 msk_rxfilter(sc_if); 1111 MSK_IF_UNLOCK(sc_if); 1112 break; 1113 case SIOCGIFMEDIA: 1114 case SIOCSIFMEDIA: 1115 mii = device_get_softc(sc_if->msk_miibus); 1116 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1117 break; 1118 case SIOCSIFCAP: 1119 reinit = 0; 1120 MSK_IF_LOCK(sc_if); 1121 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp); 1122 if ((mask & IFCAP_TXCSUM) != 0 && 1123 (IFCAP_TXCSUM & if_getcapabilities(ifp)) != 0) { 1124 if_togglecapenable(ifp, IFCAP_TXCSUM); 1125 if ((IFCAP_TXCSUM & if_getcapenable(ifp)) != 0) 1126 if_sethwassistbits(ifp, MSK_CSUM_FEATURES, 0); 1127 else 1128 if_sethwassistbits(ifp, 0, MSK_CSUM_FEATURES); 1129 } 1130 if ((mask & IFCAP_RXCSUM) != 0 && 1131 (IFCAP_RXCSUM & if_getcapabilities(ifp)) != 0) { 1132 if_togglecapenable(ifp, IFCAP_RXCSUM); 1133 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0) 1134 reinit = 1; 1135 } 1136 if ((mask & IFCAP_VLAN_HWCSUM) != 0 && 1137 (IFCAP_VLAN_HWCSUM & if_getcapabilities(ifp)) != 0) 1138 if_togglecapenable(ifp, IFCAP_VLAN_HWCSUM); 1139 if ((mask & IFCAP_TSO4) != 0 && 1140 (IFCAP_TSO4 & if_getcapabilities(ifp)) != 0) { 1141 if_togglecapenable(ifp, IFCAP_TSO4); 1142 if ((IFCAP_TSO4 & if_getcapenable(ifp)) != 0) 1143 if_sethwassistbits(ifp, CSUM_TSO, 0); 1144 else 1145 if_sethwassistbits(ifp, 0, CSUM_TSO); 1146 } 1147 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 1148 (IFCAP_VLAN_HWTSO & if_getcapabilities(ifp)) != 0) 1149 if_togglecapenable(ifp, IFCAP_VLAN_HWTSO); 1150 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 1151 (IFCAP_VLAN_HWTAGGING & if_getcapabilities(ifp)) != 0) { 1152 if_togglecapenable(ifp, IFCAP_VLAN_HWTAGGING); 1153 if ((IFCAP_VLAN_HWTAGGING & if_getcapenable(ifp)) == 0) 1154 if_setcapenablebit(ifp, 0, 1155 IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM); 1156 msk_setvlan(sc_if, ifp); 1157 } 1158 if (if_getmtu(ifp) > ETHERMTU && 1159 (sc_if->msk_flags & MSK_FLAG_JUMBO_NOCSUM) != 0) { 1160 if_sethwassistbits(ifp, 0, (MSK_CSUM_FEATURES | CSUM_TSO)); 1161 if_setcapenablebit(ifp, 0, (IFCAP_TSO4 | IFCAP_TXCSUM)); 1162 } 1163 VLAN_CAPABILITIES(ifp); 1164 if (reinit > 0 && (if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 1165 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 1166 msk_init_locked(sc_if); 1167 } 1168 MSK_IF_UNLOCK(sc_if); 1169 break; 1170 default: 1171 error = ether_ioctl(ifp, command, data); 1172 break; 1173 } 1174 1175 return (error); 1176 } 1177 1178 static int 1179 mskc_probe(device_t dev) 1180 { 1181 const struct msk_product *mp; 1182 uint16_t vendor, devid; 1183 int i; 1184 1185 vendor = pci_get_vendor(dev); 1186 devid = pci_get_device(dev); 1187 mp = msk_products; 1188 for (i = 0; i < nitems(msk_products); i++, mp++) { 1189 if (vendor == mp->msk_vendorid && devid == mp->msk_deviceid) { 1190 device_set_desc(dev, mp->msk_name); 1191 return (BUS_PROBE_DEFAULT); 1192 } 1193 } 1194 1195 return (ENXIO); 1196 } 1197 1198 static int 1199 mskc_setup_rambuffer(struct msk_softc *sc) 1200 { 1201 int next; 1202 int i; 1203 1204 /* Get adapter SRAM size. */ 1205 sc->msk_ramsize = CSR_READ_1(sc, B2_E_0) * 4; 1206 if (bootverbose) 1207 device_printf(sc->msk_dev, 1208 "RAM buffer size : %dKB\n", sc->msk_ramsize); 1209 if (sc->msk_ramsize == 0) 1210 return (0); 1211 1212 sc->msk_pflags |= MSK_FLAG_RAMBUF; 1213 /* 1214 * Give receiver 2/3 of memory and round down to the multiple 1215 * of 1024. Tx/Rx RAM buffer size of Yukon II should be multiple 1216 * of 1024. 1217 */ 1218 sc->msk_rxqsize = rounddown((sc->msk_ramsize * 1024 * 2) / 3, 1024); 1219 sc->msk_txqsize = (sc->msk_ramsize * 1024) - sc->msk_rxqsize; 1220 for (i = 0, next = 0; i < sc->msk_num_port; i++) { 1221 sc->msk_rxqstart[i] = next; 1222 sc->msk_rxqend[i] = next + sc->msk_rxqsize - 1; 1223 next = sc->msk_rxqend[i] + 1; 1224 sc->msk_txqstart[i] = next; 1225 sc->msk_txqend[i] = next + sc->msk_txqsize - 1; 1226 next = sc->msk_txqend[i] + 1; 1227 if (bootverbose) { 1228 device_printf(sc->msk_dev, 1229 "Port %d : Rx Queue %dKB(0x%08x:0x%08x)\n", i, 1230 sc->msk_rxqsize / 1024, sc->msk_rxqstart[i], 1231 sc->msk_rxqend[i]); 1232 device_printf(sc->msk_dev, 1233 "Port %d : Tx Queue %dKB(0x%08x:0x%08x)\n", i, 1234 sc->msk_txqsize / 1024, sc->msk_txqstart[i], 1235 sc->msk_txqend[i]); 1236 } 1237 } 1238 1239 return (0); 1240 } 1241 1242 static void 1243 msk_phy_power(struct msk_softc *sc, int mode) 1244 { 1245 uint32_t our, val; 1246 int i; 1247 1248 switch (mode) { 1249 case MSK_PHY_POWERUP: 1250 /* Switch power to VCC (WA for VAUX problem). */ 1251 CSR_WRITE_1(sc, B0_POWER_CTRL, 1252 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON); 1253 /* Disable Core Clock Division, set Clock Select to 0. */ 1254 CSR_WRITE_4(sc, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS); 1255 1256 val = 0; 1257 if (sc->msk_hw_id == CHIP_ID_YUKON_XL && 1258 sc->msk_hw_rev > CHIP_REV_YU_XL_A1) { 1259 /* Enable bits are inverted. */ 1260 val = Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS | 1261 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS | 1262 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS; 1263 } 1264 /* 1265 * Enable PCI & Core Clock, enable clock gating for both Links. 1266 */ 1267 CSR_WRITE_1(sc, B2_Y2_CLK_GATE, val); 1268 1269 our = CSR_PCI_READ_4(sc, PCI_OUR_REG_1); 1270 our &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD); 1271 if (sc->msk_hw_id == CHIP_ID_YUKON_XL) { 1272 if (sc->msk_hw_rev > CHIP_REV_YU_XL_A1) { 1273 /* Deassert Low Power for 1st PHY. */ 1274 our |= PCI_Y2_PHY1_COMA; 1275 if (sc->msk_num_port > 1) 1276 our |= PCI_Y2_PHY2_COMA; 1277 } 1278 } 1279 if (sc->msk_hw_id == CHIP_ID_YUKON_EC_U || 1280 sc->msk_hw_id == CHIP_ID_YUKON_EX || 1281 sc->msk_hw_id >= CHIP_ID_YUKON_FE_P) { 1282 val = CSR_PCI_READ_4(sc, PCI_OUR_REG_4); 1283 val &= (PCI_FORCE_ASPM_REQUEST | 1284 PCI_ASPM_GPHY_LINK_DOWN | PCI_ASPM_INT_FIFO_EMPTY | 1285 PCI_ASPM_CLKRUN_REQUEST); 1286 /* Set all bits to 0 except bits 15..12. */ 1287 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_4, val); 1288 val = CSR_PCI_READ_4(sc, PCI_OUR_REG_5); 1289 val &= PCI_CTL_TIM_VMAIN_AV_MSK; 1290 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_5, val); 1291 CSR_PCI_WRITE_4(sc, PCI_CFG_REG_1, 0); 1292 CSR_WRITE_2(sc, B0_CTST, Y2_HW_WOL_ON); 1293 /* 1294 * Disable status race, workaround for 1295 * Yukon EC Ultra & Yukon EX. 1296 */ 1297 val = CSR_READ_4(sc, B2_GP_IO); 1298 val |= GLB_GPIO_STAT_RACE_DIS; 1299 CSR_WRITE_4(sc, B2_GP_IO, val); 1300 CSR_READ_4(sc, B2_GP_IO); 1301 } 1302 /* Release PHY from PowerDown/COMA mode. */ 1303 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_1, our); 1304 1305 for (i = 0; i < sc->msk_num_port; i++) { 1306 CSR_WRITE_2(sc, MR_ADDR(i, GMAC_LINK_CTRL), 1307 GMLC_RST_SET); 1308 CSR_WRITE_2(sc, MR_ADDR(i, GMAC_LINK_CTRL), 1309 GMLC_RST_CLR); 1310 } 1311 break; 1312 case MSK_PHY_POWERDOWN: 1313 val = CSR_PCI_READ_4(sc, PCI_OUR_REG_1); 1314 val |= PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD; 1315 if (sc->msk_hw_id == CHIP_ID_YUKON_XL && 1316 sc->msk_hw_rev > CHIP_REV_YU_XL_A1) { 1317 val &= ~PCI_Y2_PHY1_COMA; 1318 if (sc->msk_num_port > 1) 1319 val &= ~PCI_Y2_PHY2_COMA; 1320 } 1321 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_1, val); 1322 1323 val = Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS | 1324 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS | 1325 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS; 1326 if (sc->msk_hw_id == CHIP_ID_YUKON_XL && 1327 sc->msk_hw_rev > CHIP_REV_YU_XL_A1) { 1328 /* Enable bits are inverted. */ 1329 val = 0; 1330 } 1331 /* 1332 * Disable PCI & Core Clock, disable clock gating for 1333 * both Links. 1334 */ 1335 CSR_WRITE_1(sc, B2_Y2_CLK_GATE, val); 1336 CSR_WRITE_1(sc, B0_POWER_CTRL, 1337 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_ON | PC_VCC_OFF); 1338 break; 1339 default: 1340 break; 1341 } 1342 } 1343 1344 static void 1345 mskc_reset(struct msk_softc *sc) 1346 { 1347 bus_addr_t addr; 1348 uint16_t status; 1349 uint32_t val; 1350 int i, initram; 1351 1352 /* Disable ASF. */ 1353 if (sc->msk_hw_id >= CHIP_ID_YUKON_XL && 1354 sc->msk_hw_id <= CHIP_ID_YUKON_SUPR) { 1355 if (sc->msk_hw_id == CHIP_ID_YUKON_EX || 1356 sc->msk_hw_id == CHIP_ID_YUKON_SUPR) { 1357 CSR_WRITE_4(sc, B28_Y2_CPU_WDOG, 0); 1358 status = CSR_READ_2(sc, B28_Y2_ASF_HCU_CCSR); 1359 /* Clear AHB bridge & microcontroller reset. */ 1360 status &= ~(Y2_ASF_HCU_CCSR_AHB_RST | 1361 Y2_ASF_HCU_CCSR_CPU_RST_MODE); 1362 /* Clear ASF microcontroller state. */ 1363 status &= ~Y2_ASF_HCU_CCSR_UC_STATE_MSK; 1364 status &= ~Y2_ASF_HCU_CCSR_CPU_CLK_DIVIDE_MSK; 1365 CSR_WRITE_2(sc, B28_Y2_ASF_HCU_CCSR, status); 1366 CSR_WRITE_4(sc, B28_Y2_CPU_WDOG, 0); 1367 } else 1368 CSR_WRITE_1(sc, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET); 1369 CSR_WRITE_2(sc, B0_CTST, Y2_ASF_DISABLE); 1370 /* 1371 * Since we disabled ASF, S/W reset is required for 1372 * Power Management. 1373 */ 1374 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); 1375 CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR); 1376 } 1377 1378 /* Clear all error bits in the PCI status register. */ 1379 status = pci_read_config(sc->msk_dev, PCIR_STATUS, 2); 1380 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON); 1381 1382 pci_write_config(sc->msk_dev, PCIR_STATUS, status | 1383 PCIM_STATUS_PERR | PCIM_STATUS_SERR | PCIM_STATUS_RMABORT | 1384 PCIM_STATUS_RTABORT | PCIM_STATUS_MDPERR, 2); 1385 CSR_WRITE_2(sc, B0_CTST, CS_MRST_CLR); 1386 1387 switch (sc->msk_bustype) { 1388 case MSK_PEX_BUS: 1389 /* Clear all PEX errors. */ 1390 CSR_PCI_WRITE_4(sc, PEX_UNC_ERR_STAT, 0xffffffff); 1391 val = CSR_PCI_READ_4(sc, PEX_UNC_ERR_STAT); 1392 if ((val & PEX_RX_OV) != 0) { 1393 sc->msk_intrmask &= ~Y2_IS_HW_ERR; 1394 sc->msk_intrhwemask &= ~Y2_IS_PCI_EXP; 1395 } 1396 break; 1397 case MSK_PCI_BUS: 1398 case MSK_PCIX_BUS: 1399 /* Set Cache Line Size to 2(8bytes) if configured to 0. */ 1400 val = pci_read_config(sc->msk_dev, PCIR_CACHELNSZ, 1); 1401 if (val == 0) 1402 pci_write_config(sc->msk_dev, PCIR_CACHELNSZ, 2, 1); 1403 if (sc->msk_bustype == MSK_PCIX_BUS) { 1404 /* Set Cache Line Size opt. */ 1405 val = pci_read_config(sc->msk_dev, PCI_OUR_REG_1, 4); 1406 val |= PCI_CLS_OPT; 1407 pci_write_config(sc->msk_dev, PCI_OUR_REG_1, val, 4); 1408 } 1409 break; 1410 } 1411 /* Set PHY power state. */ 1412 msk_phy_power(sc, MSK_PHY_POWERUP); 1413 1414 /* Reset GPHY/GMAC Control */ 1415 for (i = 0; i < sc->msk_num_port; i++) { 1416 /* GPHY Control reset. */ 1417 CSR_WRITE_1(sc, MR_ADDR(i, GPHY_CTRL), GPC_RST_SET); 1418 CSR_WRITE_1(sc, MR_ADDR(i, GPHY_CTRL), GPC_RST_CLR); 1419 /* GMAC Control reset. */ 1420 CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), GMC_RST_SET); 1421 CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), GMC_RST_CLR); 1422 CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), GMC_F_LOOPB_OFF); 1423 if (sc->msk_hw_id == CHIP_ID_YUKON_EX || 1424 sc->msk_hw_id == CHIP_ID_YUKON_SUPR) 1425 CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), 1426 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON | 1427 GMC_BYP_RETR_ON); 1428 } 1429 1430 if (sc->msk_hw_id == CHIP_ID_YUKON_SUPR && 1431 sc->msk_hw_rev > CHIP_REV_YU_SU_B0) 1432 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_3, PCI_CLK_MACSEC_DIS); 1433 if (sc->msk_hw_id == CHIP_ID_YUKON_OPT && sc->msk_hw_rev == 0) { 1434 /* Disable PCIe PHY powerdown(reg 0x80, bit7). */ 1435 CSR_WRITE_4(sc, Y2_PEX_PHY_DATA, (0x0080 << 16) | 0x0080); 1436 } 1437 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 1438 1439 /* LED On. */ 1440 CSR_WRITE_2(sc, B0_CTST, Y2_LED_STAT_ON); 1441 1442 /* Clear TWSI IRQ. */ 1443 CSR_WRITE_4(sc, B2_I2C_IRQ, I2C_CLR_IRQ); 1444 1445 /* Turn off hardware timer. */ 1446 CSR_WRITE_1(sc, B2_TI_CTRL, TIM_STOP); 1447 CSR_WRITE_1(sc, B2_TI_CTRL, TIM_CLR_IRQ); 1448 1449 /* Turn off descriptor polling. */ 1450 CSR_WRITE_1(sc, B28_DPT_CTRL, DPT_STOP); 1451 1452 /* Turn off time stamps. */ 1453 CSR_WRITE_1(sc, GMAC_TI_ST_CTRL, GMT_ST_STOP); 1454 CSR_WRITE_1(sc, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ); 1455 1456 initram = 0; 1457 if (sc->msk_hw_id == CHIP_ID_YUKON_XL || 1458 sc->msk_hw_id == CHIP_ID_YUKON_EC || 1459 sc->msk_hw_id == CHIP_ID_YUKON_FE) 1460 initram++; 1461 1462 /* Configure timeout values. */ 1463 for (i = 0; initram > 0 && i < sc->msk_num_port; i++) { 1464 CSR_WRITE_2(sc, SELECT_RAM_BUFFER(i, B3_RI_CTRL), RI_RST_SET); 1465 CSR_WRITE_2(sc, SELECT_RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR); 1466 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_R1), 1467 MSK_RI_TO_53); 1468 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XA1), 1469 MSK_RI_TO_53); 1470 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XS1), 1471 MSK_RI_TO_53); 1472 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_R1), 1473 MSK_RI_TO_53); 1474 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XA1), 1475 MSK_RI_TO_53); 1476 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XS1), 1477 MSK_RI_TO_53); 1478 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_R2), 1479 MSK_RI_TO_53); 1480 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XA2), 1481 MSK_RI_TO_53); 1482 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XS2), 1483 MSK_RI_TO_53); 1484 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_R2), 1485 MSK_RI_TO_53); 1486 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XA2), 1487 MSK_RI_TO_53); 1488 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XS2), 1489 MSK_RI_TO_53); 1490 } 1491 1492 /* Disable all interrupts. */ 1493 CSR_WRITE_4(sc, B0_HWE_IMSK, 0); 1494 CSR_READ_4(sc, B0_HWE_IMSK); 1495 CSR_WRITE_4(sc, B0_IMSK, 0); 1496 CSR_READ_4(sc, B0_IMSK); 1497 1498 /* 1499 * On dual port PCI-X card, there is an problem where status 1500 * can be received out of order due to split transactions. 1501 */ 1502 if (sc->msk_pcixcap != 0 && sc->msk_num_port > 1) { 1503 uint16_t pcix_cmd; 1504 1505 pcix_cmd = pci_read_config(sc->msk_dev, 1506 sc->msk_pcixcap + PCIXR_COMMAND, 2); 1507 /* Clear Max Outstanding Split Transactions. */ 1508 pcix_cmd &= ~PCIXM_COMMAND_MAX_SPLITS; 1509 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON); 1510 pci_write_config(sc->msk_dev, 1511 sc->msk_pcixcap + PCIXR_COMMAND, pcix_cmd, 2); 1512 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 1513 } 1514 if (sc->msk_expcap != 0) { 1515 /* Change Max. Read Request Size to 2048 bytes. */ 1516 if (pci_get_max_read_req(sc->msk_dev) == 512) 1517 pci_set_max_read_req(sc->msk_dev, 2048); 1518 } 1519 1520 /* Clear status list. */ 1521 bzero(sc->msk_stat_ring, 1522 sizeof(struct msk_stat_desc) * sc->msk_stat_count); 1523 sc->msk_stat_cons = 0; 1524 bus_dmamap_sync(sc->msk_stat_tag, sc->msk_stat_map, 1525 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1526 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_RST_SET); 1527 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_RST_CLR); 1528 /* Set the status list base address. */ 1529 addr = sc->msk_stat_ring_paddr; 1530 CSR_WRITE_4(sc, STAT_LIST_ADDR_LO, MSK_ADDR_LO(addr)); 1531 CSR_WRITE_4(sc, STAT_LIST_ADDR_HI, MSK_ADDR_HI(addr)); 1532 /* Set the status list last index. */ 1533 CSR_WRITE_2(sc, STAT_LAST_IDX, sc->msk_stat_count - 1); 1534 if (sc->msk_hw_id == CHIP_ID_YUKON_EC && 1535 sc->msk_hw_rev == CHIP_REV_YU_EC_A1) { 1536 /* WA for dev. #4.3 */ 1537 CSR_WRITE_2(sc, STAT_TX_IDX_TH, ST_TXTH_IDX_MASK); 1538 /* WA for dev. #4.18 */ 1539 CSR_WRITE_1(sc, STAT_FIFO_WM, 0x21); 1540 CSR_WRITE_1(sc, STAT_FIFO_ISR_WM, 0x07); 1541 } else { 1542 CSR_WRITE_2(sc, STAT_TX_IDX_TH, 0x0a); 1543 CSR_WRITE_1(sc, STAT_FIFO_WM, 0x10); 1544 if (sc->msk_hw_id == CHIP_ID_YUKON_XL && 1545 sc->msk_hw_rev == CHIP_REV_YU_XL_A0) 1546 CSR_WRITE_1(sc, STAT_FIFO_ISR_WM, 0x04); 1547 else 1548 CSR_WRITE_1(sc, STAT_FIFO_ISR_WM, 0x10); 1549 CSR_WRITE_4(sc, STAT_ISR_TIMER_INI, 0x0190); 1550 } 1551 /* 1552 * Use default value for STAT_ISR_TIMER_INI, STAT_LEV_TIMER_INI. 1553 */ 1554 CSR_WRITE_4(sc, STAT_TX_TIMER_INI, MSK_USECS(sc, 1000)); 1555 1556 /* Enable status unit. */ 1557 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_OP_ON); 1558 1559 CSR_WRITE_1(sc, STAT_TX_TIMER_CTRL, TIM_START); 1560 CSR_WRITE_1(sc, STAT_LEV_TIMER_CTRL, TIM_START); 1561 CSR_WRITE_1(sc, STAT_ISR_TIMER_CTRL, TIM_START); 1562 } 1563 1564 static int 1565 msk_probe(device_t dev) 1566 { 1567 struct msk_softc *sc; 1568 char desc[100]; 1569 1570 sc = device_get_softc(device_get_parent(dev)); 1571 /* 1572 * Not much to do here. We always know there will be 1573 * at least one GMAC present, and if there are two, 1574 * mskc_attach() will create a second device instance 1575 * for us. 1576 */ 1577 snprintf(desc, sizeof(desc), 1578 "Marvell Technology Group Ltd. %s Id 0x%02x Rev 0x%02x", 1579 model_name[sc->msk_hw_id - CHIP_ID_YUKON_XL], sc->msk_hw_id, 1580 sc->msk_hw_rev); 1581 device_set_desc_copy(dev, desc); 1582 1583 return (BUS_PROBE_DEFAULT); 1584 } 1585 1586 static int 1587 msk_attach(device_t dev) 1588 { 1589 struct msk_softc *sc; 1590 struct msk_if_softc *sc_if; 1591 if_t ifp; 1592 struct msk_mii_data *mmd; 1593 int i, port, error; 1594 uint8_t eaddr[6]; 1595 1596 if (dev == NULL) 1597 return (EINVAL); 1598 1599 error = 0; 1600 sc_if = device_get_softc(dev); 1601 sc = device_get_softc(device_get_parent(dev)); 1602 mmd = device_get_ivars(dev); 1603 port = mmd->port; 1604 1605 sc_if->msk_if_dev = dev; 1606 sc_if->msk_port = port; 1607 sc_if->msk_softc = sc; 1608 sc_if->msk_flags = sc->msk_pflags; 1609 sc->msk_if[port] = sc_if; 1610 /* Setup Tx/Rx queue register offsets. */ 1611 if (port == MSK_PORT_A) { 1612 sc_if->msk_txq = Q_XA1; 1613 sc_if->msk_txsq = Q_XS1; 1614 sc_if->msk_rxq = Q_R1; 1615 } else { 1616 sc_if->msk_txq = Q_XA2; 1617 sc_if->msk_txsq = Q_XS2; 1618 sc_if->msk_rxq = Q_R2; 1619 } 1620 1621 callout_init_mtx(&sc_if->msk_tick_ch, &sc_if->msk_softc->msk_mtx, 0); 1622 msk_sysctl_node(sc_if); 1623 1624 if ((error = msk_txrx_dma_alloc(sc_if)) != 0) 1625 goto fail; 1626 msk_rx_dma_jalloc(sc_if); 1627 1628 ifp = sc_if->msk_ifp = if_alloc(IFT_ETHER); 1629 if (ifp == NULL) { 1630 device_printf(sc_if->msk_if_dev, "can not if_alloc()\n"); 1631 error = ENOSPC; 1632 goto fail; 1633 } 1634 if_setsoftc(ifp, sc_if); 1635 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1636 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 1637 if_setcapabilities(ifp, IFCAP_TXCSUM | IFCAP_TSO4); 1638 /* 1639 * Enable Rx checksum offloading if controller supports 1640 * new descriptor formant and controller is not Yukon XL. 1641 */ 1642 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0 && 1643 sc->msk_hw_id != CHIP_ID_YUKON_XL) 1644 if_setcapabilitiesbit(ifp, IFCAP_RXCSUM, 0); 1645 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) != 0 && 1646 (sc_if->msk_flags & MSK_FLAG_NORX_CSUM) == 0) 1647 if_setcapabilitiesbit(ifp, IFCAP_RXCSUM, 0); 1648 if_sethwassist(ifp, MSK_CSUM_FEATURES | CSUM_TSO); 1649 if_setcapenable(ifp, if_getcapabilities(ifp)); 1650 if_setioctlfn(ifp, msk_ioctl); 1651 if_setstartfn(ifp, msk_start); 1652 if_setinitfn(ifp, msk_init); 1653 if_setsendqlen(ifp, MSK_TX_RING_CNT - 1); 1654 if_setsendqready(ifp); 1655 /* 1656 * Get station address for this interface. Note that 1657 * dual port cards actually come with three station 1658 * addresses: one for each port, plus an extra. The 1659 * extra one is used by the SysKonnect driver software 1660 * as a 'virtual' station address for when both ports 1661 * are operating in failover mode. Currently we don't 1662 * use this extra address. 1663 */ 1664 MSK_IF_LOCK(sc_if); 1665 for (i = 0; i < ETHER_ADDR_LEN; i++) 1666 eaddr[i] = CSR_READ_1(sc, B2_MAC_1 + (port * 8) + i); 1667 1668 /* 1669 * Call MI attach routine. Can't hold locks when calling into ether_*. 1670 */ 1671 MSK_IF_UNLOCK(sc_if); 1672 ether_ifattach(ifp, eaddr); 1673 MSK_IF_LOCK(sc_if); 1674 1675 /* VLAN capability setup */ 1676 if_setcapabilitiesbit(ifp, IFCAP_VLAN_MTU, 0); 1677 if ((sc_if->msk_flags & MSK_FLAG_NOHWVLAN) == 0) { 1678 /* 1679 * Due to Tx checksum offload hardware bugs, msk(4) manually 1680 * computes checksum for short frames. For VLAN tagged frames 1681 * this workaround does not work so disable checksum offload 1682 * for VLAN interface. 1683 */ 1684 if_setcapabilitiesbit(ifp, IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWTSO, 0); 1685 /* 1686 * Enable Rx checksum offloading for VLAN tagged frames 1687 * if controller support new descriptor format. 1688 */ 1689 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) != 0 && 1690 (sc_if->msk_flags & MSK_FLAG_NORX_CSUM) == 0) 1691 if_setcapabilitiesbit(ifp, IFCAP_VLAN_HWCSUM, 0); 1692 } 1693 if_setcapenable(ifp, if_getcapabilities(ifp)); 1694 /* 1695 * Disable RX checksum offloading on controllers that don't use 1696 * new descriptor format but give chance to enable it. 1697 */ 1698 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0) 1699 if_setcapenablebit(ifp, 0, IFCAP_RXCSUM); 1700 1701 /* 1702 * Tell the upper layer(s) we support long frames. 1703 * Must appear after the call to ether_ifattach() because 1704 * ether_ifattach() sets ifi_hdrlen to the default value. 1705 */ 1706 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 1707 1708 /* 1709 * Do miibus setup. 1710 */ 1711 MSK_IF_UNLOCK(sc_if); 1712 error = mii_attach(dev, &sc_if->msk_miibus, ifp, msk_mediachange, 1713 msk_mediastatus, BMSR_DEFCAPMASK, PHY_ADDR_MARV, MII_OFFSET_ANY, 1714 mmd->mii_flags); 1715 if (error != 0) { 1716 device_printf(sc_if->msk_if_dev, "attaching PHYs failed\n"); 1717 ether_ifdetach(ifp); 1718 error = ENXIO; 1719 goto fail; 1720 } 1721 1722 fail: 1723 if (error != 0) { 1724 /* Access should be ok even though lock has been dropped */ 1725 sc->msk_if[port] = NULL; 1726 msk_detach(dev); 1727 } 1728 1729 return (error); 1730 } 1731 1732 /* 1733 * Attach the interface. Allocate softc structures, do ifmedia 1734 * setup and ethernet/BPF attach. 1735 */ 1736 static int 1737 mskc_attach(device_t dev) 1738 { 1739 struct msk_softc *sc; 1740 struct msk_mii_data *mmd; 1741 int error, msic, msir, reg; 1742 1743 sc = device_get_softc(dev); 1744 sc->msk_dev = dev; 1745 mtx_init(&sc->msk_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1746 MTX_DEF); 1747 1748 /* 1749 * Map control/status registers. 1750 */ 1751 pci_enable_busmaster(dev); 1752 1753 /* Allocate I/O resource */ 1754 #ifdef MSK_USEIOSPACE 1755 sc->msk_res_spec = msk_res_spec_io; 1756 #else 1757 sc->msk_res_spec = msk_res_spec_mem; 1758 #endif 1759 sc->msk_irq_spec = msk_irq_spec_legacy; 1760 error = bus_alloc_resources(dev, sc->msk_res_spec, sc->msk_res); 1761 if (error) { 1762 if (sc->msk_res_spec == msk_res_spec_mem) 1763 sc->msk_res_spec = msk_res_spec_io; 1764 else 1765 sc->msk_res_spec = msk_res_spec_mem; 1766 error = bus_alloc_resources(dev, sc->msk_res_spec, sc->msk_res); 1767 if (error) { 1768 device_printf(dev, "couldn't allocate %s resources\n", 1769 sc->msk_res_spec == msk_res_spec_mem ? "memory" : 1770 "I/O"); 1771 mtx_destroy(&sc->msk_mtx); 1772 return (ENXIO); 1773 } 1774 } 1775 1776 /* Enable all clocks before accessing any registers. */ 1777 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_3, 0); 1778 1779 CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR); 1780 sc->msk_hw_id = CSR_READ_1(sc, B2_CHIP_ID); 1781 sc->msk_hw_rev = (CSR_READ_1(sc, B2_MAC_CFG) >> 4) & 0x0f; 1782 /* Bail out if chip is not recognized. */ 1783 if (sc->msk_hw_id < CHIP_ID_YUKON_XL || 1784 sc->msk_hw_id > CHIP_ID_YUKON_OPT || 1785 sc->msk_hw_id == CHIP_ID_YUKON_UNKNOWN) { 1786 device_printf(dev, "unknown device: id=0x%02x, rev=0x%02x\n", 1787 sc->msk_hw_id, sc->msk_hw_rev); 1788 mtx_destroy(&sc->msk_mtx); 1789 return (ENXIO); 1790 } 1791 1792 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 1793 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 1794 OID_AUTO, "process_limit", 1795 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 1796 &sc->msk_process_limit, 0, sysctl_hw_msk_proc_limit, "I", 1797 "max number of Rx events to process"); 1798 1799 sc->msk_process_limit = MSK_PROC_DEFAULT; 1800 error = resource_int_value(device_get_name(dev), device_get_unit(dev), 1801 "process_limit", &sc->msk_process_limit); 1802 if (error == 0) { 1803 if (sc->msk_process_limit < MSK_PROC_MIN || 1804 sc->msk_process_limit > MSK_PROC_MAX) { 1805 device_printf(dev, "process_limit value out of range; " 1806 "using default: %d\n", MSK_PROC_DEFAULT); 1807 sc->msk_process_limit = MSK_PROC_DEFAULT; 1808 } 1809 } 1810 1811 sc->msk_int_holdoff = MSK_INT_HOLDOFF_DEFAULT; 1812 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 1813 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 1814 "int_holdoff", CTLFLAG_RW, &sc->msk_int_holdoff, 0, 1815 "Maximum number of time to delay interrupts"); 1816 resource_int_value(device_get_name(dev), device_get_unit(dev), 1817 "int_holdoff", &sc->msk_int_holdoff); 1818 1819 sc->msk_pmd = CSR_READ_1(sc, B2_PMD_TYP); 1820 /* Check number of MACs. */ 1821 sc->msk_num_port = 1; 1822 if ((CSR_READ_1(sc, B2_Y2_HW_RES) & CFG_DUAL_MAC_MSK) == 1823 CFG_DUAL_MAC_MSK) { 1824 if (!(CSR_READ_1(sc, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC)) 1825 sc->msk_num_port++; 1826 } 1827 1828 /* Check bus type. */ 1829 if (pci_find_cap(sc->msk_dev, PCIY_EXPRESS, ®) == 0) { 1830 sc->msk_bustype = MSK_PEX_BUS; 1831 sc->msk_expcap = reg; 1832 } else if (pci_find_cap(sc->msk_dev, PCIY_PCIX, ®) == 0) { 1833 sc->msk_bustype = MSK_PCIX_BUS; 1834 sc->msk_pcixcap = reg; 1835 } else 1836 sc->msk_bustype = MSK_PCI_BUS; 1837 1838 switch (sc->msk_hw_id) { 1839 case CHIP_ID_YUKON_EC: 1840 sc->msk_clock = 125; /* 125 MHz */ 1841 sc->msk_pflags |= MSK_FLAG_JUMBO; 1842 break; 1843 case CHIP_ID_YUKON_EC_U: 1844 sc->msk_clock = 125; /* 125 MHz */ 1845 sc->msk_pflags |= MSK_FLAG_JUMBO | MSK_FLAG_JUMBO_NOCSUM; 1846 break; 1847 case CHIP_ID_YUKON_EX: 1848 sc->msk_clock = 125; /* 125 MHz */ 1849 sc->msk_pflags |= MSK_FLAG_JUMBO | MSK_FLAG_DESCV2 | 1850 MSK_FLAG_AUTOTX_CSUM; 1851 /* 1852 * Yukon Extreme seems to have silicon bug for 1853 * automatic Tx checksum calculation capability. 1854 */ 1855 if (sc->msk_hw_rev == CHIP_REV_YU_EX_B0) 1856 sc->msk_pflags &= ~MSK_FLAG_AUTOTX_CSUM; 1857 /* 1858 * Yukon Extreme A0 could not use store-and-forward 1859 * for jumbo frames, so disable Tx checksum 1860 * offloading for jumbo frames. 1861 */ 1862 if (sc->msk_hw_rev == CHIP_REV_YU_EX_A0) 1863 sc->msk_pflags |= MSK_FLAG_JUMBO_NOCSUM; 1864 break; 1865 case CHIP_ID_YUKON_FE: 1866 sc->msk_clock = 100; /* 100 MHz */ 1867 sc->msk_pflags |= MSK_FLAG_FASTETHER; 1868 break; 1869 case CHIP_ID_YUKON_FE_P: 1870 sc->msk_clock = 50; /* 50 MHz */ 1871 sc->msk_pflags |= MSK_FLAG_FASTETHER | MSK_FLAG_DESCV2 | 1872 MSK_FLAG_AUTOTX_CSUM; 1873 if (sc->msk_hw_rev == CHIP_REV_YU_FE_P_A0) { 1874 /* 1875 * XXX 1876 * FE+ A0 has status LE writeback bug so msk(4) 1877 * does not rely on status word of received frame 1878 * in msk_rxeof() which in turn disables all 1879 * hardware assistance bits reported by the status 1880 * word as well as validity of the received frame. 1881 * Just pass received frames to upper stack with 1882 * minimal test and let upper stack handle them. 1883 */ 1884 sc->msk_pflags |= MSK_FLAG_NOHWVLAN | 1885 MSK_FLAG_NORXCHK | MSK_FLAG_NORX_CSUM; 1886 } 1887 break; 1888 case CHIP_ID_YUKON_XL: 1889 sc->msk_clock = 156; /* 156 MHz */ 1890 sc->msk_pflags |= MSK_FLAG_JUMBO; 1891 break; 1892 case CHIP_ID_YUKON_SUPR: 1893 sc->msk_clock = 125; /* 125 MHz */ 1894 sc->msk_pflags |= MSK_FLAG_JUMBO | MSK_FLAG_DESCV2 | 1895 MSK_FLAG_AUTOTX_CSUM; 1896 break; 1897 case CHIP_ID_YUKON_UL_2: 1898 sc->msk_clock = 125; /* 125 MHz */ 1899 sc->msk_pflags |= MSK_FLAG_JUMBO; 1900 break; 1901 case CHIP_ID_YUKON_OPT: 1902 sc->msk_clock = 125; /* 125 MHz */ 1903 sc->msk_pflags |= MSK_FLAG_JUMBO | MSK_FLAG_DESCV2; 1904 break; 1905 default: 1906 sc->msk_clock = 156; /* 156 MHz */ 1907 break; 1908 } 1909 1910 /* Allocate IRQ resources. */ 1911 msic = pci_msi_count(dev); 1912 if (bootverbose) 1913 device_printf(dev, "MSI count : %d\n", msic); 1914 if (legacy_intr != 0) 1915 msi_disable = 1; 1916 if (msi_disable == 0 && msic > 0) { 1917 msir = 1; 1918 if (pci_alloc_msi(dev, &msir) == 0) { 1919 if (msir == 1) { 1920 sc->msk_pflags |= MSK_FLAG_MSI; 1921 sc->msk_irq_spec = msk_irq_spec_msi; 1922 } else 1923 pci_release_msi(dev); 1924 } 1925 } 1926 1927 error = bus_alloc_resources(dev, sc->msk_irq_spec, sc->msk_irq); 1928 if (error) { 1929 device_printf(dev, "couldn't allocate IRQ resources\n"); 1930 goto fail; 1931 } 1932 1933 if ((error = msk_status_dma_alloc(sc)) != 0) 1934 goto fail; 1935 1936 /* Set base interrupt mask. */ 1937 sc->msk_intrmask = Y2_IS_HW_ERR | Y2_IS_STAT_BMU; 1938 sc->msk_intrhwemask = Y2_IS_TIST_OV | Y2_IS_MST_ERR | 1939 Y2_IS_IRQ_STAT | Y2_IS_PCI_EXP | Y2_IS_PCI_NEXP; 1940 1941 /* Reset the adapter. */ 1942 mskc_reset(sc); 1943 1944 if ((error = mskc_setup_rambuffer(sc)) != 0) 1945 goto fail; 1946 1947 sc->msk_devs[MSK_PORT_A] = device_add_child(dev, "msk", -1); 1948 if (sc->msk_devs[MSK_PORT_A] == NULL) { 1949 device_printf(dev, "failed to add child for PORT_A\n"); 1950 error = ENXIO; 1951 goto fail; 1952 } 1953 mmd = malloc(sizeof(struct msk_mii_data), M_DEVBUF, M_WAITOK | M_ZERO); 1954 mmd->port = MSK_PORT_A; 1955 mmd->pmd = sc->msk_pmd; 1956 mmd->mii_flags |= MIIF_DOPAUSE; 1957 if (sc->msk_pmd == 'L' || sc->msk_pmd == 'S') 1958 mmd->mii_flags |= MIIF_HAVEFIBER; 1959 if (sc->msk_pmd == 'P') 1960 mmd->mii_flags |= MIIF_HAVEFIBER | MIIF_MACPRIV0; 1961 device_set_ivars(sc->msk_devs[MSK_PORT_A], mmd); 1962 1963 if (sc->msk_num_port > 1) { 1964 sc->msk_devs[MSK_PORT_B] = device_add_child(dev, "msk", -1); 1965 if (sc->msk_devs[MSK_PORT_B] == NULL) { 1966 device_printf(dev, "failed to add child for PORT_B\n"); 1967 error = ENXIO; 1968 goto fail; 1969 } 1970 mmd = malloc(sizeof(struct msk_mii_data), M_DEVBUF, M_WAITOK | 1971 M_ZERO); 1972 mmd->port = MSK_PORT_B; 1973 mmd->pmd = sc->msk_pmd; 1974 if (sc->msk_pmd == 'L' || sc->msk_pmd == 'S') 1975 mmd->mii_flags |= MIIF_HAVEFIBER; 1976 if (sc->msk_pmd == 'P') 1977 mmd->mii_flags |= MIIF_HAVEFIBER | MIIF_MACPRIV0; 1978 device_set_ivars(sc->msk_devs[MSK_PORT_B], mmd); 1979 } 1980 1981 error = bus_generic_attach(dev); 1982 if (error) { 1983 device_printf(dev, "failed to attach port(s)\n"); 1984 goto fail; 1985 } 1986 1987 /* Hook interrupt last to avoid having to lock softc. */ 1988 error = bus_setup_intr(dev, sc->msk_irq[0], INTR_TYPE_NET | 1989 INTR_MPSAFE, NULL, msk_intr, sc, &sc->msk_intrhand); 1990 if (error != 0) { 1991 device_printf(dev, "couldn't set up interrupt handler\n"); 1992 goto fail; 1993 } 1994 fail: 1995 if (error != 0) 1996 mskc_detach(dev); 1997 1998 return (error); 1999 } 2000 2001 /* 2002 * Shutdown hardware and free up resources. This can be called any 2003 * time after the mutex has been initialized. It is called in both 2004 * the error case in attach and the normal detach case so it needs 2005 * to be careful about only freeing resources that have actually been 2006 * allocated. 2007 */ 2008 static int 2009 msk_detach(device_t dev) 2010 { 2011 struct msk_softc *sc; 2012 struct msk_if_softc *sc_if; 2013 if_t ifp; 2014 2015 sc_if = device_get_softc(dev); 2016 KASSERT(mtx_initialized(&sc_if->msk_softc->msk_mtx), 2017 ("msk mutex not initialized in msk_detach")); 2018 MSK_IF_LOCK(sc_if); 2019 2020 ifp = sc_if->msk_ifp; 2021 if (device_is_attached(dev)) { 2022 /* XXX */ 2023 sc_if->msk_flags |= MSK_FLAG_DETACH; 2024 msk_stop(sc_if); 2025 /* Can't hold locks while calling detach. */ 2026 MSK_IF_UNLOCK(sc_if); 2027 callout_drain(&sc_if->msk_tick_ch); 2028 if (ifp) 2029 ether_ifdetach(ifp); 2030 MSK_IF_LOCK(sc_if); 2031 } 2032 2033 /* 2034 * We're generally called from mskc_detach() which is using 2035 * device_delete_child() to get to here. It's already trashed 2036 * miibus for us, so don't do it here or we'll panic. 2037 * 2038 * if (sc_if->msk_miibus != NULL) { 2039 * device_delete_child(dev, sc_if->msk_miibus); 2040 * sc_if->msk_miibus = NULL; 2041 * } 2042 */ 2043 2044 msk_rx_dma_jfree(sc_if); 2045 msk_txrx_dma_free(sc_if); 2046 bus_generic_detach(dev); 2047 2048 sc = sc_if->msk_softc; 2049 sc->msk_if[sc_if->msk_port] = NULL; 2050 MSK_IF_UNLOCK(sc_if); 2051 if (ifp) 2052 if_free(ifp); 2053 2054 return (0); 2055 } 2056 2057 static int 2058 mskc_detach(device_t dev) 2059 { 2060 struct msk_softc *sc; 2061 2062 sc = device_get_softc(dev); 2063 KASSERT(mtx_initialized(&sc->msk_mtx), ("msk mutex not initialized")); 2064 2065 if (device_is_alive(dev)) { 2066 if (sc->msk_devs[MSK_PORT_A] != NULL) { 2067 free(device_get_ivars(sc->msk_devs[MSK_PORT_A]), 2068 M_DEVBUF); 2069 device_delete_child(dev, sc->msk_devs[MSK_PORT_A]); 2070 } 2071 if (sc->msk_devs[MSK_PORT_B] != NULL) { 2072 free(device_get_ivars(sc->msk_devs[MSK_PORT_B]), 2073 M_DEVBUF); 2074 device_delete_child(dev, sc->msk_devs[MSK_PORT_B]); 2075 } 2076 bus_generic_detach(dev); 2077 } 2078 2079 /* Disable all interrupts. */ 2080 CSR_WRITE_4(sc, B0_IMSK, 0); 2081 CSR_READ_4(sc, B0_IMSK); 2082 CSR_WRITE_4(sc, B0_HWE_IMSK, 0); 2083 CSR_READ_4(sc, B0_HWE_IMSK); 2084 2085 /* LED Off. */ 2086 CSR_WRITE_2(sc, B0_CTST, Y2_LED_STAT_OFF); 2087 2088 /* Put hardware reset. */ 2089 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); 2090 2091 msk_status_dma_free(sc); 2092 2093 if (sc->msk_intrhand) { 2094 bus_teardown_intr(dev, sc->msk_irq[0], sc->msk_intrhand); 2095 sc->msk_intrhand = NULL; 2096 } 2097 bus_release_resources(dev, sc->msk_irq_spec, sc->msk_irq); 2098 if ((sc->msk_pflags & MSK_FLAG_MSI) != 0) 2099 pci_release_msi(dev); 2100 bus_release_resources(dev, sc->msk_res_spec, sc->msk_res); 2101 mtx_destroy(&sc->msk_mtx); 2102 2103 return (0); 2104 } 2105 2106 static bus_dma_tag_t 2107 mskc_get_dma_tag(device_t bus, device_t child __unused) 2108 { 2109 2110 return (bus_get_dma_tag(bus)); 2111 } 2112 2113 struct msk_dmamap_arg { 2114 bus_addr_t msk_busaddr; 2115 }; 2116 2117 static void 2118 msk_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 2119 { 2120 struct msk_dmamap_arg *ctx; 2121 2122 if (error != 0) 2123 return; 2124 ctx = arg; 2125 ctx->msk_busaddr = segs[0].ds_addr; 2126 } 2127 2128 /* Create status DMA region. */ 2129 static int 2130 msk_status_dma_alloc(struct msk_softc *sc) 2131 { 2132 struct msk_dmamap_arg ctx; 2133 bus_size_t stat_sz; 2134 int count, error; 2135 2136 /* 2137 * It seems controller requires number of status LE entries 2138 * is power of 2 and the maximum number of status LE entries 2139 * is 4096. For dual-port controllers, the number of status 2140 * LE entries should be large enough to hold both port's 2141 * status updates. 2142 */ 2143 count = 3 * MSK_RX_RING_CNT + MSK_TX_RING_CNT; 2144 count = imin(4096, roundup2(count, 1024)); 2145 sc->msk_stat_count = count; 2146 stat_sz = count * sizeof(struct msk_stat_desc); 2147 error = bus_dma_tag_create( 2148 bus_get_dma_tag(sc->msk_dev), /* parent */ 2149 MSK_STAT_ALIGN, 0, /* alignment, boundary */ 2150 BUS_SPACE_MAXADDR, /* lowaddr */ 2151 BUS_SPACE_MAXADDR, /* highaddr */ 2152 NULL, NULL, /* filter, filterarg */ 2153 stat_sz, /* maxsize */ 2154 1, /* nsegments */ 2155 stat_sz, /* maxsegsize */ 2156 0, /* flags */ 2157 NULL, NULL, /* lockfunc, lockarg */ 2158 &sc->msk_stat_tag); 2159 if (error != 0) { 2160 device_printf(sc->msk_dev, 2161 "failed to create status DMA tag\n"); 2162 return (error); 2163 } 2164 2165 /* Allocate DMA'able memory and load the DMA map for status ring. */ 2166 error = bus_dmamem_alloc(sc->msk_stat_tag, 2167 (void **)&sc->msk_stat_ring, BUS_DMA_WAITOK | BUS_DMA_COHERENT | 2168 BUS_DMA_ZERO, &sc->msk_stat_map); 2169 if (error != 0) { 2170 device_printf(sc->msk_dev, 2171 "failed to allocate DMA'able memory for status ring\n"); 2172 return (error); 2173 } 2174 2175 ctx.msk_busaddr = 0; 2176 error = bus_dmamap_load(sc->msk_stat_tag, sc->msk_stat_map, 2177 sc->msk_stat_ring, stat_sz, msk_dmamap_cb, &ctx, BUS_DMA_NOWAIT); 2178 if (error != 0) { 2179 device_printf(sc->msk_dev, 2180 "failed to load DMA'able memory for status ring\n"); 2181 return (error); 2182 } 2183 sc->msk_stat_ring_paddr = ctx.msk_busaddr; 2184 2185 return (0); 2186 } 2187 2188 static void 2189 msk_status_dma_free(struct msk_softc *sc) 2190 { 2191 2192 /* Destroy status block. */ 2193 if (sc->msk_stat_tag) { 2194 if (sc->msk_stat_ring_paddr) { 2195 bus_dmamap_unload(sc->msk_stat_tag, sc->msk_stat_map); 2196 sc->msk_stat_ring_paddr = 0; 2197 } 2198 if (sc->msk_stat_ring) { 2199 bus_dmamem_free(sc->msk_stat_tag, 2200 sc->msk_stat_ring, sc->msk_stat_map); 2201 sc->msk_stat_ring = NULL; 2202 } 2203 bus_dma_tag_destroy(sc->msk_stat_tag); 2204 sc->msk_stat_tag = NULL; 2205 } 2206 } 2207 2208 static int 2209 msk_txrx_dma_alloc(struct msk_if_softc *sc_if) 2210 { 2211 struct msk_dmamap_arg ctx; 2212 struct msk_txdesc *txd; 2213 struct msk_rxdesc *rxd; 2214 bus_size_t rxalign; 2215 int error, i; 2216 2217 /* Create parent DMA tag. */ 2218 error = bus_dma_tag_create( 2219 bus_get_dma_tag(sc_if->msk_if_dev), /* parent */ 2220 1, 0, /* alignment, boundary */ 2221 BUS_SPACE_MAXADDR, /* lowaddr */ 2222 BUS_SPACE_MAXADDR, /* highaddr */ 2223 NULL, NULL, /* filter, filterarg */ 2224 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 2225 0, /* nsegments */ 2226 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 2227 0, /* flags */ 2228 NULL, NULL, /* lockfunc, lockarg */ 2229 &sc_if->msk_cdata.msk_parent_tag); 2230 if (error != 0) { 2231 device_printf(sc_if->msk_if_dev, 2232 "failed to create parent DMA tag\n"); 2233 goto fail; 2234 } 2235 /* Create tag for Tx ring. */ 2236 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2237 MSK_RING_ALIGN, 0, /* alignment, boundary */ 2238 BUS_SPACE_MAXADDR, /* lowaddr */ 2239 BUS_SPACE_MAXADDR, /* highaddr */ 2240 NULL, NULL, /* filter, filterarg */ 2241 MSK_TX_RING_SZ, /* maxsize */ 2242 1, /* nsegments */ 2243 MSK_TX_RING_SZ, /* maxsegsize */ 2244 0, /* flags */ 2245 NULL, NULL, /* lockfunc, lockarg */ 2246 &sc_if->msk_cdata.msk_tx_ring_tag); 2247 if (error != 0) { 2248 device_printf(sc_if->msk_if_dev, 2249 "failed to create Tx ring DMA tag\n"); 2250 goto fail; 2251 } 2252 2253 /* Create tag for Rx ring. */ 2254 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2255 MSK_RING_ALIGN, 0, /* alignment, boundary */ 2256 BUS_SPACE_MAXADDR, /* lowaddr */ 2257 BUS_SPACE_MAXADDR, /* highaddr */ 2258 NULL, NULL, /* filter, filterarg */ 2259 MSK_RX_RING_SZ, /* maxsize */ 2260 1, /* nsegments */ 2261 MSK_RX_RING_SZ, /* maxsegsize */ 2262 0, /* flags */ 2263 NULL, NULL, /* lockfunc, lockarg */ 2264 &sc_if->msk_cdata.msk_rx_ring_tag); 2265 if (error != 0) { 2266 device_printf(sc_if->msk_if_dev, 2267 "failed to create Rx ring DMA tag\n"); 2268 goto fail; 2269 } 2270 2271 /* Create tag for Tx buffers. */ 2272 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2273 1, 0, /* alignment, boundary */ 2274 BUS_SPACE_MAXADDR, /* lowaddr */ 2275 BUS_SPACE_MAXADDR, /* highaddr */ 2276 NULL, NULL, /* filter, filterarg */ 2277 MSK_TSO_MAXSIZE, /* maxsize */ 2278 MSK_MAXTXSEGS, /* nsegments */ 2279 MSK_TSO_MAXSGSIZE, /* maxsegsize */ 2280 0, /* flags */ 2281 NULL, NULL, /* lockfunc, lockarg */ 2282 &sc_if->msk_cdata.msk_tx_tag); 2283 if (error != 0) { 2284 device_printf(sc_if->msk_if_dev, 2285 "failed to create Tx DMA tag\n"); 2286 goto fail; 2287 } 2288 2289 rxalign = 1; 2290 /* 2291 * Workaround hardware hang which seems to happen when Rx buffer 2292 * is not aligned on multiple of FIFO word(8 bytes). 2293 */ 2294 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) != 0) 2295 rxalign = MSK_RX_BUF_ALIGN; 2296 /* Create tag for Rx buffers. */ 2297 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2298 rxalign, 0, /* alignment, boundary */ 2299 BUS_SPACE_MAXADDR, /* lowaddr */ 2300 BUS_SPACE_MAXADDR, /* highaddr */ 2301 NULL, NULL, /* filter, filterarg */ 2302 MCLBYTES, /* maxsize */ 2303 1, /* nsegments */ 2304 MCLBYTES, /* maxsegsize */ 2305 0, /* flags */ 2306 NULL, NULL, /* lockfunc, lockarg */ 2307 &sc_if->msk_cdata.msk_rx_tag); 2308 if (error != 0) { 2309 device_printf(sc_if->msk_if_dev, 2310 "failed to create Rx DMA tag\n"); 2311 goto fail; 2312 } 2313 2314 /* Allocate DMA'able memory and load the DMA map for Tx ring. */ 2315 error = bus_dmamem_alloc(sc_if->msk_cdata.msk_tx_ring_tag, 2316 (void **)&sc_if->msk_rdata.msk_tx_ring, BUS_DMA_WAITOK | 2317 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc_if->msk_cdata.msk_tx_ring_map); 2318 if (error != 0) { 2319 device_printf(sc_if->msk_if_dev, 2320 "failed to allocate DMA'able memory for Tx ring\n"); 2321 goto fail; 2322 } 2323 2324 ctx.msk_busaddr = 0; 2325 error = bus_dmamap_load(sc_if->msk_cdata.msk_tx_ring_tag, 2326 sc_if->msk_cdata.msk_tx_ring_map, sc_if->msk_rdata.msk_tx_ring, 2327 MSK_TX_RING_SZ, msk_dmamap_cb, &ctx, BUS_DMA_NOWAIT); 2328 if (error != 0) { 2329 device_printf(sc_if->msk_if_dev, 2330 "failed to load DMA'able memory for Tx ring\n"); 2331 goto fail; 2332 } 2333 sc_if->msk_rdata.msk_tx_ring_paddr = ctx.msk_busaddr; 2334 2335 /* Allocate DMA'able memory and load the DMA map for Rx ring. */ 2336 error = bus_dmamem_alloc(sc_if->msk_cdata.msk_rx_ring_tag, 2337 (void **)&sc_if->msk_rdata.msk_rx_ring, BUS_DMA_WAITOK | 2338 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc_if->msk_cdata.msk_rx_ring_map); 2339 if (error != 0) { 2340 device_printf(sc_if->msk_if_dev, 2341 "failed to allocate DMA'able memory for Rx ring\n"); 2342 goto fail; 2343 } 2344 2345 ctx.msk_busaddr = 0; 2346 error = bus_dmamap_load(sc_if->msk_cdata.msk_rx_ring_tag, 2347 sc_if->msk_cdata.msk_rx_ring_map, sc_if->msk_rdata.msk_rx_ring, 2348 MSK_RX_RING_SZ, msk_dmamap_cb, &ctx, BUS_DMA_NOWAIT); 2349 if (error != 0) { 2350 device_printf(sc_if->msk_if_dev, 2351 "failed to load DMA'able memory for Rx ring\n"); 2352 goto fail; 2353 } 2354 sc_if->msk_rdata.msk_rx_ring_paddr = ctx.msk_busaddr; 2355 2356 /* Create DMA maps for Tx buffers. */ 2357 for (i = 0; i < MSK_TX_RING_CNT; i++) { 2358 txd = &sc_if->msk_cdata.msk_txdesc[i]; 2359 txd->tx_m = NULL; 2360 txd->tx_dmamap = NULL; 2361 error = bus_dmamap_create(sc_if->msk_cdata.msk_tx_tag, 0, 2362 &txd->tx_dmamap); 2363 if (error != 0) { 2364 device_printf(sc_if->msk_if_dev, 2365 "failed to create Tx dmamap\n"); 2366 goto fail; 2367 } 2368 } 2369 /* Create DMA maps for Rx buffers. */ 2370 if ((error = bus_dmamap_create(sc_if->msk_cdata.msk_rx_tag, 0, 2371 &sc_if->msk_cdata.msk_rx_sparemap)) != 0) { 2372 device_printf(sc_if->msk_if_dev, 2373 "failed to create spare Rx dmamap\n"); 2374 goto fail; 2375 } 2376 for (i = 0; i < MSK_RX_RING_CNT; i++) { 2377 rxd = &sc_if->msk_cdata.msk_rxdesc[i]; 2378 rxd->rx_m = NULL; 2379 rxd->rx_dmamap = NULL; 2380 error = bus_dmamap_create(sc_if->msk_cdata.msk_rx_tag, 0, 2381 &rxd->rx_dmamap); 2382 if (error != 0) { 2383 device_printf(sc_if->msk_if_dev, 2384 "failed to create Rx dmamap\n"); 2385 goto fail; 2386 } 2387 } 2388 2389 fail: 2390 return (error); 2391 } 2392 2393 static int 2394 msk_rx_dma_jalloc(struct msk_if_softc *sc_if) 2395 { 2396 struct msk_dmamap_arg ctx; 2397 struct msk_rxdesc *jrxd; 2398 bus_size_t rxalign; 2399 int error, i; 2400 2401 if (jumbo_disable != 0 || (sc_if->msk_flags & MSK_FLAG_JUMBO) == 0) { 2402 sc_if->msk_flags &= ~MSK_FLAG_JUMBO; 2403 device_printf(sc_if->msk_if_dev, 2404 "disabling jumbo frame support\n"); 2405 return (0); 2406 } 2407 /* Create tag for jumbo Rx ring. */ 2408 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2409 MSK_RING_ALIGN, 0, /* alignment, boundary */ 2410 BUS_SPACE_MAXADDR, /* lowaddr */ 2411 BUS_SPACE_MAXADDR, /* highaddr */ 2412 NULL, NULL, /* filter, filterarg */ 2413 MSK_JUMBO_RX_RING_SZ, /* maxsize */ 2414 1, /* nsegments */ 2415 MSK_JUMBO_RX_RING_SZ, /* maxsegsize */ 2416 0, /* flags */ 2417 NULL, NULL, /* lockfunc, lockarg */ 2418 &sc_if->msk_cdata.msk_jumbo_rx_ring_tag); 2419 if (error != 0) { 2420 device_printf(sc_if->msk_if_dev, 2421 "failed to create jumbo Rx ring DMA tag\n"); 2422 goto jumbo_fail; 2423 } 2424 2425 rxalign = 1; 2426 /* 2427 * Workaround hardware hang which seems to happen when Rx buffer 2428 * is not aligned on multiple of FIFO word(8 bytes). 2429 */ 2430 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) != 0) 2431 rxalign = MSK_RX_BUF_ALIGN; 2432 /* Create tag for jumbo Rx buffers. */ 2433 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2434 rxalign, 0, /* alignment, boundary */ 2435 BUS_SPACE_MAXADDR, /* lowaddr */ 2436 BUS_SPACE_MAXADDR, /* highaddr */ 2437 NULL, NULL, /* filter, filterarg */ 2438 MJUM9BYTES, /* maxsize */ 2439 1, /* nsegments */ 2440 MJUM9BYTES, /* maxsegsize */ 2441 0, /* flags */ 2442 NULL, NULL, /* lockfunc, lockarg */ 2443 &sc_if->msk_cdata.msk_jumbo_rx_tag); 2444 if (error != 0) { 2445 device_printf(sc_if->msk_if_dev, 2446 "failed to create jumbo Rx DMA tag\n"); 2447 goto jumbo_fail; 2448 } 2449 2450 /* Allocate DMA'able memory and load the DMA map for jumbo Rx ring. */ 2451 error = bus_dmamem_alloc(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 2452 (void **)&sc_if->msk_rdata.msk_jumbo_rx_ring, 2453 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 2454 &sc_if->msk_cdata.msk_jumbo_rx_ring_map); 2455 if (error != 0) { 2456 device_printf(sc_if->msk_if_dev, 2457 "failed to allocate DMA'able memory for jumbo Rx ring\n"); 2458 goto jumbo_fail; 2459 } 2460 2461 ctx.msk_busaddr = 0; 2462 error = bus_dmamap_load(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 2463 sc_if->msk_cdata.msk_jumbo_rx_ring_map, 2464 sc_if->msk_rdata.msk_jumbo_rx_ring, MSK_JUMBO_RX_RING_SZ, 2465 msk_dmamap_cb, &ctx, BUS_DMA_NOWAIT); 2466 if (error != 0) { 2467 device_printf(sc_if->msk_if_dev, 2468 "failed to load DMA'able memory for jumbo Rx ring\n"); 2469 goto jumbo_fail; 2470 } 2471 sc_if->msk_rdata.msk_jumbo_rx_ring_paddr = ctx.msk_busaddr; 2472 2473 /* Create DMA maps for jumbo Rx buffers. */ 2474 if ((error = bus_dmamap_create(sc_if->msk_cdata.msk_jumbo_rx_tag, 0, 2475 &sc_if->msk_cdata.msk_jumbo_rx_sparemap)) != 0) { 2476 device_printf(sc_if->msk_if_dev, 2477 "failed to create spare jumbo Rx dmamap\n"); 2478 goto jumbo_fail; 2479 } 2480 for (i = 0; i < MSK_JUMBO_RX_RING_CNT; i++) { 2481 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[i]; 2482 jrxd->rx_m = NULL; 2483 jrxd->rx_dmamap = NULL; 2484 error = bus_dmamap_create(sc_if->msk_cdata.msk_jumbo_rx_tag, 0, 2485 &jrxd->rx_dmamap); 2486 if (error != 0) { 2487 device_printf(sc_if->msk_if_dev, 2488 "failed to create jumbo Rx dmamap\n"); 2489 goto jumbo_fail; 2490 } 2491 } 2492 2493 return (0); 2494 2495 jumbo_fail: 2496 msk_rx_dma_jfree(sc_if); 2497 device_printf(sc_if->msk_if_dev, "disabling jumbo frame support " 2498 "due to resource shortage\n"); 2499 sc_if->msk_flags &= ~MSK_FLAG_JUMBO; 2500 return (error); 2501 } 2502 2503 static void 2504 msk_txrx_dma_free(struct msk_if_softc *sc_if) 2505 { 2506 struct msk_txdesc *txd; 2507 struct msk_rxdesc *rxd; 2508 int i; 2509 2510 /* Tx ring. */ 2511 if (sc_if->msk_cdata.msk_tx_ring_tag) { 2512 if (sc_if->msk_rdata.msk_tx_ring_paddr) 2513 bus_dmamap_unload(sc_if->msk_cdata.msk_tx_ring_tag, 2514 sc_if->msk_cdata.msk_tx_ring_map); 2515 if (sc_if->msk_rdata.msk_tx_ring) 2516 bus_dmamem_free(sc_if->msk_cdata.msk_tx_ring_tag, 2517 sc_if->msk_rdata.msk_tx_ring, 2518 sc_if->msk_cdata.msk_tx_ring_map); 2519 sc_if->msk_rdata.msk_tx_ring = NULL; 2520 sc_if->msk_rdata.msk_tx_ring_paddr = 0; 2521 bus_dma_tag_destroy(sc_if->msk_cdata.msk_tx_ring_tag); 2522 sc_if->msk_cdata.msk_tx_ring_tag = NULL; 2523 } 2524 /* Rx ring. */ 2525 if (sc_if->msk_cdata.msk_rx_ring_tag) { 2526 if (sc_if->msk_rdata.msk_rx_ring_paddr) 2527 bus_dmamap_unload(sc_if->msk_cdata.msk_rx_ring_tag, 2528 sc_if->msk_cdata.msk_rx_ring_map); 2529 if (sc_if->msk_rdata.msk_rx_ring) 2530 bus_dmamem_free(sc_if->msk_cdata.msk_rx_ring_tag, 2531 sc_if->msk_rdata.msk_rx_ring, 2532 sc_if->msk_cdata.msk_rx_ring_map); 2533 sc_if->msk_rdata.msk_rx_ring = NULL; 2534 sc_if->msk_rdata.msk_rx_ring_paddr = 0; 2535 bus_dma_tag_destroy(sc_if->msk_cdata.msk_rx_ring_tag); 2536 sc_if->msk_cdata.msk_rx_ring_tag = NULL; 2537 } 2538 /* Tx buffers. */ 2539 if (sc_if->msk_cdata.msk_tx_tag) { 2540 for (i = 0; i < MSK_TX_RING_CNT; i++) { 2541 txd = &sc_if->msk_cdata.msk_txdesc[i]; 2542 if (txd->tx_dmamap) { 2543 bus_dmamap_destroy(sc_if->msk_cdata.msk_tx_tag, 2544 txd->tx_dmamap); 2545 txd->tx_dmamap = NULL; 2546 } 2547 } 2548 bus_dma_tag_destroy(sc_if->msk_cdata.msk_tx_tag); 2549 sc_if->msk_cdata.msk_tx_tag = NULL; 2550 } 2551 /* Rx buffers. */ 2552 if (sc_if->msk_cdata.msk_rx_tag) { 2553 for (i = 0; i < MSK_RX_RING_CNT; i++) { 2554 rxd = &sc_if->msk_cdata.msk_rxdesc[i]; 2555 if (rxd->rx_dmamap) { 2556 bus_dmamap_destroy(sc_if->msk_cdata.msk_rx_tag, 2557 rxd->rx_dmamap); 2558 rxd->rx_dmamap = NULL; 2559 } 2560 } 2561 if (sc_if->msk_cdata.msk_rx_sparemap) { 2562 bus_dmamap_destroy(sc_if->msk_cdata.msk_rx_tag, 2563 sc_if->msk_cdata.msk_rx_sparemap); 2564 sc_if->msk_cdata.msk_rx_sparemap = 0; 2565 } 2566 bus_dma_tag_destroy(sc_if->msk_cdata.msk_rx_tag); 2567 sc_if->msk_cdata.msk_rx_tag = NULL; 2568 } 2569 if (sc_if->msk_cdata.msk_parent_tag) { 2570 bus_dma_tag_destroy(sc_if->msk_cdata.msk_parent_tag); 2571 sc_if->msk_cdata.msk_parent_tag = NULL; 2572 } 2573 } 2574 2575 static void 2576 msk_rx_dma_jfree(struct msk_if_softc *sc_if) 2577 { 2578 struct msk_rxdesc *jrxd; 2579 int i; 2580 2581 /* Jumbo Rx ring. */ 2582 if (sc_if->msk_cdata.msk_jumbo_rx_ring_tag) { 2583 if (sc_if->msk_rdata.msk_jumbo_rx_ring_paddr) 2584 bus_dmamap_unload(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 2585 sc_if->msk_cdata.msk_jumbo_rx_ring_map); 2586 if (sc_if->msk_rdata.msk_jumbo_rx_ring) 2587 bus_dmamem_free(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 2588 sc_if->msk_rdata.msk_jumbo_rx_ring, 2589 sc_if->msk_cdata.msk_jumbo_rx_ring_map); 2590 sc_if->msk_rdata.msk_jumbo_rx_ring = NULL; 2591 sc_if->msk_rdata.msk_jumbo_rx_ring_paddr = 0; 2592 bus_dma_tag_destroy(sc_if->msk_cdata.msk_jumbo_rx_ring_tag); 2593 sc_if->msk_cdata.msk_jumbo_rx_ring_tag = NULL; 2594 } 2595 /* Jumbo Rx buffers. */ 2596 if (sc_if->msk_cdata.msk_jumbo_rx_tag) { 2597 for (i = 0; i < MSK_JUMBO_RX_RING_CNT; i++) { 2598 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[i]; 2599 if (jrxd->rx_dmamap) { 2600 bus_dmamap_destroy( 2601 sc_if->msk_cdata.msk_jumbo_rx_tag, 2602 jrxd->rx_dmamap); 2603 jrxd->rx_dmamap = NULL; 2604 } 2605 } 2606 if (sc_if->msk_cdata.msk_jumbo_rx_sparemap) { 2607 bus_dmamap_destroy(sc_if->msk_cdata.msk_jumbo_rx_tag, 2608 sc_if->msk_cdata.msk_jumbo_rx_sparemap); 2609 sc_if->msk_cdata.msk_jumbo_rx_sparemap = 0; 2610 } 2611 bus_dma_tag_destroy(sc_if->msk_cdata.msk_jumbo_rx_tag); 2612 sc_if->msk_cdata.msk_jumbo_rx_tag = NULL; 2613 } 2614 } 2615 2616 static int 2617 msk_encap(struct msk_if_softc *sc_if, struct mbuf **m_head) 2618 { 2619 struct msk_txdesc *txd, *txd_last; 2620 struct msk_tx_desc *tx_le; 2621 struct mbuf *m; 2622 bus_dmamap_t map; 2623 bus_dma_segment_t txsegs[MSK_MAXTXSEGS]; 2624 uint32_t control, csum, prod, si; 2625 uint16_t offset, tcp_offset, tso_mtu; 2626 int error, i, nseg, tso; 2627 2628 MSK_IF_LOCK_ASSERT(sc_if); 2629 2630 tcp_offset = offset = 0; 2631 m = *m_head; 2632 if (((sc_if->msk_flags & MSK_FLAG_AUTOTX_CSUM) == 0 && 2633 (m->m_pkthdr.csum_flags & MSK_CSUM_FEATURES) != 0) || 2634 ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0 && 2635 (m->m_pkthdr.csum_flags & CSUM_TSO) != 0)) { 2636 /* 2637 * Since mbuf has no protocol specific structure information 2638 * in it we have to inspect protocol information here to 2639 * setup TSO and checksum offload. I don't know why Marvell 2640 * made a such decision in chip design because other GigE 2641 * hardwares normally takes care of all these chores in 2642 * hardware. However, TSO performance of Yukon II is very 2643 * good such that it's worth to implement it. 2644 */ 2645 struct ether_header *eh; 2646 struct ip *ip; 2647 struct tcphdr *tcp; 2648 2649 if (M_WRITABLE(m) == 0) { 2650 /* Get a writable copy. */ 2651 m = m_dup(*m_head, M_NOWAIT); 2652 m_freem(*m_head); 2653 if (m == NULL) { 2654 *m_head = NULL; 2655 return (ENOBUFS); 2656 } 2657 *m_head = m; 2658 } 2659 2660 offset = sizeof(struct ether_header); 2661 m = m_pullup(m, offset); 2662 if (m == NULL) { 2663 *m_head = NULL; 2664 return (ENOBUFS); 2665 } 2666 eh = mtod(m, struct ether_header *); 2667 /* Check if hardware VLAN insertion is off. */ 2668 if (eh->ether_type == htons(ETHERTYPE_VLAN)) { 2669 offset = sizeof(struct ether_vlan_header); 2670 m = m_pullup(m, offset); 2671 if (m == NULL) { 2672 *m_head = NULL; 2673 return (ENOBUFS); 2674 } 2675 } 2676 m = m_pullup(m, offset + sizeof(struct ip)); 2677 if (m == NULL) { 2678 *m_head = NULL; 2679 return (ENOBUFS); 2680 } 2681 ip = (struct ip *)(mtod(m, char *) + offset); 2682 offset += (ip->ip_hl << 2); 2683 tcp_offset = offset; 2684 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 2685 m = m_pullup(m, offset + sizeof(struct tcphdr)); 2686 if (m == NULL) { 2687 *m_head = NULL; 2688 return (ENOBUFS); 2689 } 2690 tcp = (struct tcphdr *)(mtod(m, char *) + offset); 2691 offset += (tcp->th_off << 2); 2692 } else if ((sc_if->msk_flags & MSK_FLAG_AUTOTX_CSUM) == 0 && 2693 (m->m_pkthdr.len < MSK_MIN_FRAMELEN) && 2694 (m->m_pkthdr.csum_flags & CSUM_TCP) != 0) { 2695 /* 2696 * It seems that Yukon II has Tx checksum offload bug 2697 * for small TCP packets that's less than 60 bytes in 2698 * size (e.g. TCP window probe packet, pure ACK packet). 2699 * Common work around like padding with zeros to make 2700 * the frame minimum ethernet frame size didn't work at 2701 * all. 2702 * Instead of disabling checksum offload completely we 2703 * resort to S/W checksum routine when we encounter 2704 * short TCP frames. 2705 * Short UDP packets appear to be handled correctly by 2706 * Yukon II. Also I assume this bug does not happen on 2707 * controllers that use newer descriptor format or 2708 * automatic Tx checksum calculation. 2709 */ 2710 m = m_pullup(m, offset + sizeof(struct tcphdr)); 2711 if (m == NULL) { 2712 *m_head = NULL; 2713 return (ENOBUFS); 2714 } 2715 *(uint16_t *)(m->m_data + offset + 2716 m->m_pkthdr.csum_data) = in_cksum_skip(m, 2717 m->m_pkthdr.len, offset); 2718 m->m_pkthdr.csum_flags &= ~CSUM_TCP; 2719 } 2720 *m_head = m; 2721 } 2722 2723 prod = sc_if->msk_cdata.msk_tx_prod; 2724 txd = &sc_if->msk_cdata.msk_txdesc[prod]; 2725 txd_last = txd; 2726 map = txd->tx_dmamap; 2727 error = bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_tx_tag, map, 2728 *m_head, txsegs, &nseg, BUS_DMA_NOWAIT); 2729 if (error == EFBIG) { 2730 m = m_collapse(*m_head, M_NOWAIT, MSK_MAXTXSEGS); 2731 if (m == NULL) { 2732 m_freem(*m_head); 2733 *m_head = NULL; 2734 return (ENOBUFS); 2735 } 2736 *m_head = m; 2737 error = bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_tx_tag, 2738 map, *m_head, txsegs, &nseg, BUS_DMA_NOWAIT); 2739 if (error != 0) { 2740 m_freem(*m_head); 2741 *m_head = NULL; 2742 return (error); 2743 } 2744 } else if (error != 0) 2745 return (error); 2746 if (nseg == 0) { 2747 m_freem(*m_head); 2748 *m_head = NULL; 2749 return (EIO); 2750 } 2751 2752 /* Check number of available descriptors. */ 2753 if (sc_if->msk_cdata.msk_tx_cnt + nseg >= 2754 (MSK_TX_RING_CNT - MSK_RESERVED_TX_DESC_CNT)) { 2755 bus_dmamap_unload(sc_if->msk_cdata.msk_tx_tag, map); 2756 return (ENOBUFS); 2757 } 2758 2759 control = 0; 2760 tso = 0; 2761 tx_le = NULL; 2762 2763 /* Check TSO support. */ 2764 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 2765 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) != 0) 2766 tso_mtu = m->m_pkthdr.tso_segsz; 2767 else 2768 tso_mtu = offset + m->m_pkthdr.tso_segsz; 2769 if (tso_mtu != sc_if->msk_cdata.msk_tso_mtu) { 2770 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2771 tx_le->msk_addr = htole32(tso_mtu); 2772 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) != 0) 2773 tx_le->msk_control = htole32(OP_MSS | HW_OWNER); 2774 else 2775 tx_le->msk_control = 2776 htole32(OP_LRGLEN | HW_OWNER); 2777 sc_if->msk_cdata.msk_tx_cnt++; 2778 MSK_INC(prod, MSK_TX_RING_CNT); 2779 sc_if->msk_cdata.msk_tso_mtu = tso_mtu; 2780 } 2781 tso++; 2782 } 2783 /* Check if we have a VLAN tag to insert. */ 2784 if ((m->m_flags & M_VLANTAG) != 0) { 2785 if (tx_le == NULL) { 2786 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2787 tx_le->msk_addr = htole32(0); 2788 tx_le->msk_control = htole32(OP_VLAN | HW_OWNER | 2789 htons(m->m_pkthdr.ether_vtag)); 2790 sc_if->msk_cdata.msk_tx_cnt++; 2791 MSK_INC(prod, MSK_TX_RING_CNT); 2792 } else { 2793 tx_le->msk_control |= htole32(OP_VLAN | 2794 htons(m->m_pkthdr.ether_vtag)); 2795 } 2796 control |= INS_VLAN; 2797 } 2798 /* Check if we have to handle checksum offload. */ 2799 if (tso == 0 && (m->m_pkthdr.csum_flags & MSK_CSUM_FEATURES) != 0) { 2800 if ((sc_if->msk_flags & MSK_FLAG_AUTOTX_CSUM) != 0) 2801 control |= CALSUM; 2802 else { 2803 control |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM; 2804 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0) 2805 control |= UDPTCP; 2806 /* Checksum write position. */ 2807 csum = (tcp_offset + m->m_pkthdr.csum_data) & 0xffff; 2808 /* Checksum start position. */ 2809 csum |= (uint32_t)tcp_offset << 16; 2810 if (csum != sc_if->msk_cdata.msk_last_csum) { 2811 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2812 tx_le->msk_addr = htole32(csum); 2813 tx_le->msk_control = htole32(1 << 16 | 2814 (OP_TCPLISW | HW_OWNER)); 2815 sc_if->msk_cdata.msk_tx_cnt++; 2816 MSK_INC(prod, MSK_TX_RING_CNT); 2817 sc_if->msk_cdata.msk_last_csum = csum; 2818 } 2819 } 2820 } 2821 2822 #ifdef MSK_64BIT_DMA 2823 if (MSK_ADDR_HI(txsegs[0].ds_addr) != 2824 sc_if->msk_cdata.msk_tx_high_addr) { 2825 sc_if->msk_cdata.msk_tx_high_addr = 2826 MSK_ADDR_HI(txsegs[0].ds_addr); 2827 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2828 tx_le->msk_addr = htole32(MSK_ADDR_HI(txsegs[0].ds_addr)); 2829 tx_le->msk_control = htole32(OP_ADDR64 | HW_OWNER); 2830 sc_if->msk_cdata.msk_tx_cnt++; 2831 MSK_INC(prod, MSK_TX_RING_CNT); 2832 } 2833 #endif 2834 si = prod; 2835 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2836 tx_le->msk_addr = htole32(MSK_ADDR_LO(txsegs[0].ds_addr)); 2837 if (tso == 0) 2838 tx_le->msk_control = htole32(txsegs[0].ds_len | control | 2839 OP_PACKET); 2840 else 2841 tx_le->msk_control = htole32(txsegs[0].ds_len | control | 2842 OP_LARGESEND); 2843 sc_if->msk_cdata.msk_tx_cnt++; 2844 MSK_INC(prod, MSK_TX_RING_CNT); 2845 2846 for (i = 1; i < nseg; i++) { 2847 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2848 #ifdef MSK_64BIT_DMA 2849 if (MSK_ADDR_HI(txsegs[i].ds_addr) != 2850 sc_if->msk_cdata.msk_tx_high_addr) { 2851 sc_if->msk_cdata.msk_tx_high_addr = 2852 MSK_ADDR_HI(txsegs[i].ds_addr); 2853 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2854 tx_le->msk_addr = 2855 htole32(MSK_ADDR_HI(txsegs[i].ds_addr)); 2856 tx_le->msk_control = htole32(OP_ADDR64 | HW_OWNER); 2857 sc_if->msk_cdata.msk_tx_cnt++; 2858 MSK_INC(prod, MSK_TX_RING_CNT); 2859 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2860 } 2861 #endif 2862 tx_le->msk_addr = htole32(MSK_ADDR_LO(txsegs[i].ds_addr)); 2863 tx_le->msk_control = htole32(txsegs[i].ds_len | control | 2864 OP_BUFFER | HW_OWNER); 2865 sc_if->msk_cdata.msk_tx_cnt++; 2866 MSK_INC(prod, MSK_TX_RING_CNT); 2867 } 2868 /* Update producer index. */ 2869 sc_if->msk_cdata.msk_tx_prod = prod; 2870 2871 /* Set EOP on the last descriptor. */ 2872 prod = (prod + MSK_TX_RING_CNT - 1) % MSK_TX_RING_CNT; 2873 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2874 tx_le->msk_control |= htole32(EOP); 2875 2876 /* Turn the first descriptor ownership to hardware. */ 2877 tx_le = &sc_if->msk_rdata.msk_tx_ring[si]; 2878 tx_le->msk_control |= htole32(HW_OWNER); 2879 2880 txd = &sc_if->msk_cdata.msk_txdesc[prod]; 2881 map = txd_last->tx_dmamap; 2882 txd_last->tx_dmamap = txd->tx_dmamap; 2883 txd->tx_dmamap = map; 2884 txd->tx_m = m; 2885 2886 /* Sync descriptors. */ 2887 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_tag, map, BUS_DMASYNC_PREWRITE); 2888 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_ring_tag, 2889 sc_if->msk_cdata.msk_tx_ring_map, 2890 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2891 2892 return (0); 2893 } 2894 2895 static void 2896 msk_start(if_t ifp) 2897 { 2898 struct msk_if_softc *sc_if; 2899 2900 sc_if = if_getsoftc(ifp); 2901 MSK_IF_LOCK(sc_if); 2902 msk_start_locked(ifp); 2903 MSK_IF_UNLOCK(sc_if); 2904 } 2905 2906 static void 2907 msk_start_locked(if_t ifp) 2908 { 2909 struct msk_if_softc *sc_if; 2910 struct mbuf *m_head; 2911 int enq; 2912 2913 sc_if = if_getsoftc(ifp); 2914 MSK_IF_LOCK_ASSERT(sc_if); 2915 2916 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2917 IFF_DRV_RUNNING || (sc_if->msk_flags & MSK_FLAG_LINK) == 0) 2918 return; 2919 2920 for (enq = 0; !if_sendq_empty(ifp) && 2921 sc_if->msk_cdata.msk_tx_cnt < 2922 (MSK_TX_RING_CNT - MSK_RESERVED_TX_DESC_CNT); ) { 2923 m_head = if_dequeue(ifp); 2924 if (m_head == NULL) 2925 break; 2926 /* 2927 * Pack the data into the transmit ring. If we 2928 * don't have room, set the OACTIVE flag and wait 2929 * for the NIC to drain the ring. 2930 */ 2931 if (msk_encap(sc_if, &m_head) != 0) { 2932 if (m_head == NULL) 2933 break; 2934 if_sendq_prepend(ifp, m_head); 2935 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); 2936 break; 2937 } 2938 2939 enq++; 2940 /* 2941 * If there's a BPF listener, bounce a copy of this frame 2942 * to him. 2943 */ 2944 ETHER_BPF_MTAP(ifp, m_head); 2945 } 2946 2947 if (enq > 0) { 2948 /* Transmit */ 2949 CSR_WRITE_2(sc_if->msk_softc, 2950 Y2_PREF_Q_ADDR(sc_if->msk_txq, PREF_UNIT_PUT_IDX_REG), 2951 sc_if->msk_cdata.msk_tx_prod); 2952 2953 /* Set a timeout in case the chip goes out to lunch. */ 2954 sc_if->msk_watchdog_timer = MSK_TX_TIMEOUT; 2955 } 2956 } 2957 2958 static void 2959 msk_watchdog(struct msk_if_softc *sc_if) 2960 { 2961 if_t ifp; 2962 2963 MSK_IF_LOCK_ASSERT(sc_if); 2964 2965 if (sc_if->msk_watchdog_timer == 0 || --sc_if->msk_watchdog_timer) 2966 return; 2967 ifp = sc_if->msk_ifp; 2968 if ((sc_if->msk_flags & MSK_FLAG_LINK) == 0) { 2969 if (bootverbose) 2970 if_printf(sc_if->msk_ifp, "watchdog timeout " 2971 "(missed link)\n"); 2972 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 2973 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 2974 msk_init_locked(sc_if); 2975 return; 2976 } 2977 2978 if_printf(ifp, "watchdog timeout\n"); 2979 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 2980 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 2981 msk_init_locked(sc_if); 2982 if (!if_sendq_empty(ifp)) 2983 msk_start_locked(ifp); 2984 } 2985 2986 static int 2987 mskc_shutdown(device_t dev) 2988 { 2989 struct msk_softc *sc; 2990 int i; 2991 2992 sc = device_get_softc(dev); 2993 MSK_LOCK(sc); 2994 for (i = 0; i < sc->msk_num_port; i++) { 2995 if (sc->msk_if[i] != NULL && sc->msk_if[i]->msk_ifp != NULL && 2996 ((if_getdrvflags(sc->msk_if[i]->msk_ifp) & 2997 IFF_DRV_RUNNING) != 0)) 2998 msk_stop(sc->msk_if[i]); 2999 } 3000 MSK_UNLOCK(sc); 3001 3002 /* Put hardware reset. */ 3003 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); 3004 return (0); 3005 } 3006 3007 static int 3008 mskc_suspend(device_t dev) 3009 { 3010 struct msk_softc *sc; 3011 int i; 3012 3013 sc = device_get_softc(dev); 3014 3015 MSK_LOCK(sc); 3016 3017 for (i = 0; i < sc->msk_num_port; i++) { 3018 if (sc->msk_if[i] != NULL && sc->msk_if[i]->msk_ifp != NULL && 3019 ((if_getdrvflags(sc->msk_if[i]->msk_ifp) & 3020 IFF_DRV_RUNNING) != 0)) 3021 msk_stop(sc->msk_if[i]); 3022 } 3023 3024 /* Disable all interrupts. */ 3025 CSR_WRITE_4(sc, B0_IMSK, 0); 3026 CSR_READ_4(sc, B0_IMSK); 3027 CSR_WRITE_4(sc, B0_HWE_IMSK, 0); 3028 CSR_READ_4(sc, B0_HWE_IMSK); 3029 3030 msk_phy_power(sc, MSK_PHY_POWERDOWN); 3031 3032 /* Put hardware reset. */ 3033 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); 3034 sc->msk_pflags |= MSK_FLAG_SUSPEND; 3035 3036 MSK_UNLOCK(sc); 3037 3038 return (0); 3039 } 3040 3041 static int 3042 mskc_resume(device_t dev) 3043 { 3044 struct msk_softc *sc; 3045 int i; 3046 3047 sc = device_get_softc(dev); 3048 3049 MSK_LOCK(sc); 3050 3051 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_3, 0); 3052 mskc_reset(sc); 3053 for (i = 0; i < sc->msk_num_port; i++) { 3054 if (sc->msk_if[i] != NULL && sc->msk_if[i]->msk_ifp != NULL && 3055 ((if_getflags(sc->msk_if[i]->msk_ifp) & IFF_UP) != 0)) { 3056 if_setdrvflagbits(sc->msk_if[i]->msk_ifp, 0, 3057 IFF_DRV_RUNNING); 3058 msk_init_locked(sc->msk_if[i]); 3059 } 3060 } 3061 sc->msk_pflags &= ~MSK_FLAG_SUSPEND; 3062 3063 MSK_UNLOCK(sc); 3064 3065 return (0); 3066 } 3067 3068 #ifndef __NO_STRICT_ALIGNMENT 3069 static __inline void 3070 msk_fixup_rx(struct mbuf *m) 3071 { 3072 int i; 3073 uint16_t *src, *dst; 3074 3075 src = mtod(m, uint16_t *); 3076 dst = src - 3; 3077 3078 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 3079 *dst++ = *src++; 3080 3081 m->m_data -= (MSK_RX_BUF_ALIGN - ETHER_ALIGN); 3082 } 3083 #endif 3084 3085 static __inline void 3086 msk_rxcsum(struct msk_if_softc *sc_if, uint32_t control, struct mbuf *m) 3087 { 3088 struct ether_header *eh; 3089 struct ip *ip; 3090 struct udphdr *uh; 3091 int32_t hlen, len, pktlen, temp32; 3092 uint16_t csum, *opts; 3093 3094 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) != 0) { 3095 if ((control & (CSS_IPV4 | CSS_IPFRAG)) == CSS_IPV4) { 3096 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 3097 if ((control & CSS_IPV4_CSUM_OK) != 0) 3098 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 3099 if ((control & (CSS_TCP | CSS_UDP)) != 0 && 3100 (control & (CSS_TCPUDP_CSUM_OK)) != 0) { 3101 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID | 3102 CSUM_PSEUDO_HDR; 3103 m->m_pkthdr.csum_data = 0xffff; 3104 } 3105 } 3106 return; 3107 } 3108 /* 3109 * Marvell Yukon controllers that support OP_RXCHKS has known 3110 * to have various Rx checksum offloading bugs. These 3111 * controllers can be configured to compute simple checksum 3112 * at two different positions. So we can compute IP and TCP/UDP 3113 * checksum at the same time. We intentionally have controller 3114 * compute TCP/UDP checksum twice by specifying the same 3115 * checksum start position and compare the result. If the value 3116 * is different it would indicate the hardware logic was wrong. 3117 */ 3118 if ((sc_if->msk_csum & 0xFFFF) != (sc_if->msk_csum >> 16)) { 3119 if (bootverbose) 3120 device_printf(sc_if->msk_if_dev, 3121 "Rx checksum value mismatch!\n"); 3122 return; 3123 } 3124 pktlen = m->m_pkthdr.len; 3125 if (pktlen < sizeof(struct ether_header) + sizeof(struct ip)) 3126 return; 3127 eh = mtod(m, struct ether_header *); 3128 if (eh->ether_type != htons(ETHERTYPE_IP)) 3129 return; 3130 ip = (struct ip *)(eh + 1); 3131 if (ip->ip_v != IPVERSION) 3132 return; 3133 3134 hlen = ip->ip_hl << 2; 3135 pktlen -= sizeof(struct ether_header); 3136 if (hlen < sizeof(struct ip)) 3137 return; 3138 if (ntohs(ip->ip_len) < hlen) 3139 return; 3140 if (ntohs(ip->ip_len) != pktlen) 3141 return; 3142 if (ip->ip_off & htons(IP_MF | IP_OFFMASK)) 3143 return; /* can't handle fragmented packet. */ 3144 3145 switch (ip->ip_p) { 3146 case IPPROTO_TCP: 3147 if (pktlen < (hlen + sizeof(struct tcphdr))) 3148 return; 3149 break; 3150 case IPPROTO_UDP: 3151 if (pktlen < (hlen + sizeof(struct udphdr))) 3152 return; 3153 uh = (struct udphdr *)((caddr_t)ip + hlen); 3154 if (uh->uh_sum == 0) 3155 return; /* no checksum */ 3156 break; 3157 default: 3158 return; 3159 } 3160 csum = bswap16(sc_if->msk_csum & 0xFFFF); 3161 /* Checksum fixup for IP options. */ 3162 len = hlen - sizeof(struct ip); 3163 if (len > 0) { 3164 opts = (uint16_t *)(ip + 1); 3165 for (; len > 0; len -= sizeof(uint16_t), opts++) { 3166 temp32 = csum - *opts; 3167 temp32 = (temp32 >> 16) + (temp32 & 65535); 3168 csum = temp32 & 65535; 3169 } 3170 } 3171 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID; 3172 m->m_pkthdr.csum_data = csum; 3173 } 3174 3175 static void 3176 msk_rxeof(struct msk_if_softc *sc_if, uint32_t status, uint32_t control, 3177 int len) 3178 { 3179 struct mbuf *m; 3180 if_t ifp; 3181 struct msk_rxdesc *rxd; 3182 int cons, rxlen; 3183 3184 ifp = sc_if->msk_ifp; 3185 3186 MSK_IF_LOCK_ASSERT(sc_if); 3187 3188 cons = sc_if->msk_cdata.msk_rx_cons; 3189 do { 3190 rxlen = status >> 16; 3191 if ((status & GMR_FS_VLAN) != 0 && 3192 (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0) 3193 rxlen -= ETHER_VLAN_ENCAP_LEN; 3194 if ((sc_if->msk_flags & MSK_FLAG_NORXCHK) != 0) { 3195 /* 3196 * For controllers that returns bogus status code 3197 * just do minimal check and let upper stack 3198 * handle this frame. 3199 */ 3200 if (len > MSK_MAX_FRAMELEN || len < ETHER_HDR_LEN) { 3201 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 3202 msk_discard_rxbuf(sc_if, cons); 3203 break; 3204 } 3205 } else if (len > sc_if->msk_framesize || 3206 ((status & GMR_FS_ANY_ERR) != 0) || 3207 ((status & GMR_FS_RX_OK) == 0) || (rxlen != len)) { 3208 /* Don't count flow-control packet as errors. */ 3209 if ((status & GMR_FS_GOOD_FC) == 0) 3210 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 3211 msk_discard_rxbuf(sc_if, cons); 3212 break; 3213 } 3214 #ifdef MSK_64BIT_DMA 3215 rxd = &sc_if->msk_cdata.msk_rxdesc[(cons + 1) % 3216 MSK_RX_RING_CNT]; 3217 #else 3218 rxd = &sc_if->msk_cdata.msk_rxdesc[cons]; 3219 #endif 3220 m = rxd->rx_m; 3221 if (msk_newbuf(sc_if, cons) != 0) { 3222 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 3223 /* Reuse old buffer. */ 3224 msk_discard_rxbuf(sc_if, cons); 3225 break; 3226 } 3227 m->m_pkthdr.rcvif = ifp; 3228 m->m_pkthdr.len = m->m_len = len; 3229 #ifndef __NO_STRICT_ALIGNMENT 3230 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) != 0) 3231 msk_fixup_rx(m); 3232 #endif 3233 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 3234 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0) 3235 msk_rxcsum(sc_if, control, m); 3236 /* Check for VLAN tagged packets. */ 3237 if ((status & GMR_FS_VLAN) != 0 && 3238 (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0) { 3239 m->m_pkthdr.ether_vtag = sc_if->msk_vtag; 3240 m->m_flags |= M_VLANTAG; 3241 } 3242 MSK_IF_UNLOCK(sc_if); 3243 if_input(ifp, m); 3244 MSK_IF_LOCK(sc_if); 3245 } while (0); 3246 3247 MSK_RX_INC(sc_if->msk_cdata.msk_rx_cons, MSK_RX_RING_CNT); 3248 MSK_RX_INC(sc_if->msk_cdata.msk_rx_prod, MSK_RX_RING_CNT); 3249 } 3250 3251 static void 3252 msk_jumbo_rxeof(struct msk_if_softc *sc_if, uint32_t status, uint32_t control, 3253 int len) 3254 { 3255 struct mbuf *m; 3256 if_t ifp; 3257 struct msk_rxdesc *jrxd; 3258 int cons, rxlen; 3259 3260 ifp = sc_if->msk_ifp; 3261 3262 MSK_IF_LOCK_ASSERT(sc_if); 3263 3264 cons = sc_if->msk_cdata.msk_rx_cons; 3265 do { 3266 rxlen = status >> 16; 3267 if ((status & GMR_FS_VLAN) != 0 && 3268 (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0) 3269 rxlen -= ETHER_VLAN_ENCAP_LEN; 3270 if (len > sc_if->msk_framesize || 3271 ((status & GMR_FS_ANY_ERR) != 0) || 3272 ((status & GMR_FS_RX_OK) == 0) || (rxlen != len)) { 3273 /* Don't count flow-control packet as errors. */ 3274 if ((status & GMR_FS_GOOD_FC) == 0) 3275 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 3276 msk_discard_jumbo_rxbuf(sc_if, cons); 3277 break; 3278 } 3279 #ifdef MSK_64BIT_DMA 3280 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[(cons + 1) % 3281 MSK_JUMBO_RX_RING_CNT]; 3282 #else 3283 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[cons]; 3284 #endif 3285 m = jrxd->rx_m; 3286 if (msk_jumbo_newbuf(sc_if, cons) != 0) { 3287 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 3288 /* Reuse old buffer. */ 3289 msk_discard_jumbo_rxbuf(sc_if, cons); 3290 break; 3291 } 3292 m->m_pkthdr.rcvif = ifp; 3293 m->m_pkthdr.len = m->m_len = len; 3294 #ifndef __NO_STRICT_ALIGNMENT 3295 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) != 0) 3296 msk_fixup_rx(m); 3297 #endif 3298 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 3299 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0) 3300 msk_rxcsum(sc_if, control, m); 3301 /* Check for VLAN tagged packets. */ 3302 if ((status & GMR_FS_VLAN) != 0 && 3303 (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0) { 3304 m->m_pkthdr.ether_vtag = sc_if->msk_vtag; 3305 m->m_flags |= M_VLANTAG; 3306 } 3307 MSK_IF_UNLOCK(sc_if); 3308 if_input(ifp, m); 3309 MSK_IF_LOCK(sc_if); 3310 } while (0); 3311 3312 MSK_RX_INC(sc_if->msk_cdata.msk_rx_cons, MSK_JUMBO_RX_RING_CNT); 3313 MSK_RX_INC(sc_if->msk_cdata.msk_rx_prod, MSK_JUMBO_RX_RING_CNT); 3314 } 3315 3316 static void 3317 msk_txeof(struct msk_if_softc *sc_if, int idx) 3318 { 3319 struct msk_txdesc *txd; 3320 struct msk_tx_desc *cur_tx; 3321 if_t ifp; 3322 uint32_t control; 3323 int cons, prog; 3324 3325 MSK_IF_LOCK_ASSERT(sc_if); 3326 3327 ifp = sc_if->msk_ifp; 3328 3329 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_ring_tag, 3330 sc_if->msk_cdata.msk_tx_ring_map, 3331 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3332 /* 3333 * Go through our tx ring and free mbufs for those 3334 * frames that have been sent. 3335 */ 3336 cons = sc_if->msk_cdata.msk_tx_cons; 3337 prog = 0; 3338 for (; cons != idx; MSK_INC(cons, MSK_TX_RING_CNT)) { 3339 if (sc_if->msk_cdata.msk_tx_cnt <= 0) 3340 break; 3341 prog++; 3342 cur_tx = &sc_if->msk_rdata.msk_tx_ring[cons]; 3343 control = le32toh(cur_tx->msk_control); 3344 sc_if->msk_cdata.msk_tx_cnt--; 3345 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 3346 if ((control & EOP) == 0) 3347 continue; 3348 txd = &sc_if->msk_cdata.msk_txdesc[cons]; 3349 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_tag, txd->tx_dmamap, 3350 BUS_DMASYNC_POSTWRITE); 3351 bus_dmamap_unload(sc_if->msk_cdata.msk_tx_tag, txd->tx_dmamap); 3352 3353 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 3354 KASSERT(txd->tx_m != NULL, ("%s: freeing NULL mbuf!", 3355 __func__)); 3356 m_freem(txd->tx_m); 3357 txd->tx_m = NULL; 3358 } 3359 3360 if (prog > 0) { 3361 sc_if->msk_cdata.msk_tx_cons = cons; 3362 if (sc_if->msk_cdata.msk_tx_cnt == 0) 3363 sc_if->msk_watchdog_timer = 0; 3364 /* No need to sync LEs as we didn't update LEs. */ 3365 } 3366 } 3367 3368 static void 3369 msk_tick(void *xsc_if) 3370 { 3371 struct epoch_tracker et; 3372 struct msk_if_softc *sc_if; 3373 struct mii_data *mii; 3374 3375 sc_if = xsc_if; 3376 3377 MSK_IF_LOCK_ASSERT(sc_if); 3378 3379 mii = device_get_softc(sc_if->msk_miibus); 3380 3381 mii_tick(mii); 3382 if ((sc_if->msk_flags & MSK_FLAG_LINK) == 0) 3383 msk_miibus_statchg(sc_if->msk_if_dev); 3384 NET_EPOCH_ENTER(et); 3385 msk_handle_events(sc_if->msk_softc); 3386 NET_EPOCH_EXIT(et); 3387 msk_watchdog(sc_if); 3388 callout_reset(&sc_if->msk_tick_ch, hz, msk_tick, sc_if); 3389 } 3390 3391 static void 3392 msk_intr_phy(struct msk_if_softc *sc_if) 3393 { 3394 uint16_t status; 3395 3396 msk_phy_readreg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_STAT); 3397 status = msk_phy_readreg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_STAT); 3398 /* Handle FIFO Underrun/Overflow? */ 3399 if ((status & PHY_M_IS_FIFO_ERROR)) 3400 device_printf(sc_if->msk_if_dev, 3401 "PHY FIFO underrun/overflow.\n"); 3402 } 3403 3404 static void 3405 msk_intr_gmac(struct msk_if_softc *sc_if) 3406 { 3407 struct msk_softc *sc; 3408 uint8_t status; 3409 3410 sc = sc_if->msk_softc; 3411 status = CSR_READ_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_SRC)); 3412 3413 /* GMAC Rx FIFO overrun. */ 3414 if ((status & GM_IS_RX_FF_OR) != 0) 3415 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), 3416 GMF_CLI_RX_FO); 3417 /* GMAC Tx FIFO underrun. */ 3418 if ((status & GM_IS_TX_FF_UR) != 0) { 3419 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 3420 GMF_CLI_TX_FU); 3421 device_printf(sc_if->msk_if_dev, "Tx FIFO underrun!\n"); 3422 /* 3423 * XXX 3424 * In case of Tx underrun, we may need to flush/reset 3425 * Tx MAC but that would also require resynchronization 3426 * with status LEs. Reinitializing status LEs would 3427 * affect other port in dual MAC configuration so it 3428 * should be avoided as possible as we can. 3429 * Due to lack of documentation it's all vague guess but 3430 * it needs more investigation. 3431 */ 3432 } 3433 } 3434 3435 static void 3436 msk_handle_hwerr(struct msk_if_softc *sc_if, uint32_t status) 3437 { 3438 struct msk_softc *sc; 3439 3440 sc = sc_if->msk_softc; 3441 if ((status & Y2_IS_PAR_RD1) != 0) { 3442 device_printf(sc_if->msk_if_dev, 3443 "RAM buffer read parity error\n"); 3444 /* Clear IRQ. */ 3445 CSR_WRITE_2(sc, SELECT_RAM_BUFFER(sc_if->msk_port, B3_RI_CTRL), 3446 RI_CLR_RD_PERR); 3447 } 3448 if ((status & Y2_IS_PAR_WR1) != 0) { 3449 device_printf(sc_if->msk_if_dev, 3450 "RAM buffer write parity error\n"); 3451 /* Clear IRQ. */ 3452 CSR_WRITE_2(sc, SELECT_RAM_BUFFER(sc_if->msk_port, B3_RI_CTRL), 3453 RI_CLR_WR_PERR); 3454 } 3455 if ((status & Y2_IS_PAR_MAC1) != 0) { 3456 device_printf(sc_if->msk_if_dev, "Tx MAC parity error\n"); 3457 /* Clear IRQ. */ 3458 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 3459 GMF_CLI_TX_PE); 3460 } 3461 if ((status & Y2_IS_PAR_RX1) != 0) { 3462 device_printf(sc_if->msk_if_dev, "Rx parity error\n"); 3463 /* Clear IRQ. */ 3464 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_CLR_IRQ_PAR); 3465 } 3466 if ((status & (Y2_IS_TCP_TXS1 | Y2_IS_TCP_TXA1)) != 0) { 3467 device_printf(sc_if->msk_if_dev, "TCP segmentation error\n"); 3468 /* Clear IRQ. */ 3469 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_CLR_IRQ_TCP); 3470 } 3471 } 3472 3473 static void 3474 msk_intr_hwerr(struct msk_softc *sc) 3475 { 3476 uint32_t status; 3477 uint32_t tlphead[4]; 3478 3479 status = CSR_READ_4(sc, B0_HWE_ISRC); 3480 /* Time Stamp timer overflow. */ 3481 if ((status & Y2_IS_TIST_OV) != 0) 3482 CSR_WRITE_1(sc, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ); 3483 if ((status & Y2_IS_PCI_NEXP) != 0) { 3484 /* 3485 * PCI Express Error occurred which is not described in PEX 3486 * spec. 3487 * This error is also mapped either to Master Abort( 3488 * Y2_IS_MST_ERR) or Target Abort (Y2_IS_IRQ_STAT) bit and 3489 * can only be cleared there. 3490 */ 3491 device_printf(sc->msk_dev, 3492 "PCI Express protocol violation error\n"); 3493 } 3494 3495 if ((status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) != 0) { 3496 uint16_t v16; 3497 3498 if ((status & Y2_IS_MST_ERR) != 0) 3499 device_printf(sc->msk_dev, 3500 "unexpected IRQ Status error\n"); 3501 else 3502 device_printf(sc->msk_dev, 3503 "unexpected IRQ Master error\n"); 3504 /* Reset all bits in the PCI status register. */ 3505 v16 = pci_read_config(sc->msk_dev, PCIR_STATUS, 2); 3506 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON); 3507 pci_write_config(sc->msk_dev, PCIR_STATUS, v16 | 3508 PCIM_STATUS_PERR | PCIM_STATUS_SERR | PCIM_STATUS_RMABORT | 3509 PCIM_STATUS_RTABORT | PCIM_STATUS_MDPERR, 2); 3510 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 3511 } 3512 3513 /* Check for PCI Express Uncorrectable Error. */ 3514 if ((status & Y2_IS_PCI_EXP) != 0) { 3515 uint32_t v32; 3516 3517 /* 3518 * On PCI Express bus bridges are called root complexes (RC). 3519 * PCI Express errors are recognized by the root complex too, 3520 * which requests the system to handle the problem. After 3521 * error occurrence it may be that no access to the adapter 3522 * may be performed any longer. 3523 */ 3524 3525 v32 = CSR_PCI_READ_4(sc, PEX_UNC_ERR_STAT); 3526 if ((v32 & PEX_UNSUP_REQ) != 0) { 3527 /* Ignore unsupported request error. */ 3528 device_printf(sc->msk_dev, 3529 "Uncorrectable PCI Express error\n"); 3530 } 3531 if ((v32 & (PEX_FATAL_ERRORS | PEX_POIS_TLP)) != 0) { 3532 int i; 3533 3534 /* Get TLP header form Log Registers. */ 3535 for (i = 0; i < 4; i++) 3536 tlphead[i] = CSR_PCI_READ_4(sc, 3537 PEX_HEADER_LOG + i * 4); 3538 /* Check for vendor defined broadcast message. */ 3539 if (!(tlphead[0] == 0x73004001 && tlphead[1] == 0x7f)) { 3540 sc->msk_intrhwemask &= ~Y2_IS_PCI_EXP; 3541 CSR_WRITE_4(sc, B0_HWE_IMSK, 3542 sc->msk_intrhwemask); 3543 CSR_READ_4(sc, B0_HWE_IMSK); 3544 } 3545 } 3546 /* Clear the interrupt. */ 3547 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON); 3548 CSR_PCI_WRITE_4(sc, PEX_UNC_ERR_STAT, 0xffffffff); 3549 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 3550 } 3551 3552 if ((status & Y2_HWE_L1_MASK) != 0 && sc->msk_if[MSK_PORT_A] != NULL) 3553 msk_handle_hwerr(sc->msk_if[MSK_PORT_A], status); 3554 if ((status & Y2_HWE_L2_MASK) != 0 && sc->msk_if[MSK_PORT_B] != NULL) 3555 msk_handle_hwerr(sc->msk_if[MSK_PORT_B], status >> 8); 3556 } 3557 3558 static __inline void 3559 msk_rxput(struct msk_if_softc *sc_if) 3560 { 3561 struct msk_softc *sc; 3562 3563 sc = sc_if->msk_softc; 3564 if (sc_if->msk_framesize > (MCLBYTES - MSK_RX_BUF_ALIGN)) 3565 bus_dmamap_sync( 3566 sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 3567 sc_if->msk_cdata.msk_jumbo_rx_ring_map, 3568 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3569 else 3570 bus_dmamap_sync( 3571 sc_if->msk_cdata.msk_rx_ring_tag, 3572 sc_if->msk_cdata.msk_rx_ring_map, 3573 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3574 CSR_WRITE_2(sc, Y2_PREF_Q_ADDR(sc_if->msk_rxq, 3575 PREF_UNIT_PUT_IDX_REG), sc_if->msk_cdata.msk_rx_prod); 3576 } 3577 3578 static int 3579 msk_handle_events(struct msk_softc *sc) 3580 { 3581 struct msk_if_softc *sc_if; 3582 int rxput[2]; 3583 struct msk_stat_desc *sd; 3584 uint32_t control, status; 3585 int cons, len, port, rxprog; 3586 3587 if (sc->msk_stat_cons == CSR_READ_2(sc, STAT_PUT_IDX)) 3588 return (0); 3589 3590 /* Sync status LEs. */ 3591 bus_dmamap_sync(sc->msk_stat_tag, sc->msk_stat_map, 3592 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3593 3594 rxput[MSK_PORT_A] = rxput[MSK_PORT_B] = 0; 3595 rxprog = 0; 3596 cons = sc->msk_stat_cons; 3597 for (;;) { 3598 sd = &sc->msk_stat_ring[cons]; 3599 control = le32toh(sd->msk_control); 3600 if ((control & HW_OWNER) == 0) 3601 break; 3602 control &= ~HW_OWNER; 3603 sd->msk_control = htole32(control); 3604 status = le32toh(sd->msk_status); 3605 len = control & STLE_LEN_MASK; 3606 port = (control >> 16) & 0x01; 3607 sc_if = sc->msk_if[port]; 3608 if (sc_if == NULL) { 3609 device_printf(sc->msk_dev, "invalid port opcode " 3610 "0x%08x\n", control & STLE_OP_MASK); 3611 continue; 3612 } 3613 3614 switch (control & STLE_OP_MASK) { 3615 case OP_RXVLAN: 3616 sc_if->msk_vtag = ntohs(len); 3617 break; 3618 case OP_RXCHKSVLAN: 3619 sc_if->msk_vtag = ntohs(len); 3620 /* FALLTHROUGH */ 3621 case OP_RXCHKS: 3622 sc_if->msk_csum = status; 3623 break; 3624 case OP_RXSTAT: 3625 if (!(if_getdrvflags(sc_if->msk_ifp) & IFF_DRV_RUNNING)) 3626 break; 3627 if (sc_if->msk_framesize > 3628 (MCLBYTES - MSK_RX_BUF_ALIGN)) 3629 msk_jumbo_rxeof(sc_if, status, control, len); 3630 else 3631 msk_rxeof(sc_if, status, control, len); 3632 rxprog++; 3633 /* 3634 * Because there is no way to sync single Rx LE 3635 * put the DMA sync operation off until the end of 3636 * event processing. 3637 */ 3638 rxput[port]++; 3639 /* Update prefetch unit if we've passed water mark. */ 3640 if (rxput[port] >= sc_if->msk_cdata.msk_rx_putwm) { 3641 msk_rxput(sc_if); 3642 rxput[port] = 0; 3643 } 3644 break; 3645 case OP_TXINDEXLE: 3646 if (sc->msk_if[MSK_PORT_A] != NULL) 3647 msk_txeof(sc->msk_if[MSK_PORT_A], 3648 status & STLE_TXA1_MSKL); 3649 if (sc->msk_if[MSK_PORT_B] != NULL) 3650 msk_txeof(sc->msk_if[MSK_PORT_B], 3651 ((status & STLE_TXA2_MSKL) >> 3652 STLE_TXA2_SHIFTL) | 3653 ((len & STLE_TXA2_MSKH) << 3654 STLE_TXA2_SHIFTH)); 3655 break; 3656 default: 3657 device_printf(sc->msk_dev, "unhandled opcode 0x%08x\n", 3658 control & STLE_OP_MASK); 3659 break; 3660 } 3661 MSK_INC(cons, sc->msk_stat_count); 3662 if (rxprog > sc->msk_process_limit) 3663 break; 3664 } 3665 3666 sc->msk_stat_cons = cons; 3667 bus_dmamap_sync(sc->msk_stat_tag, sc->msk_stat_map, 3668 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3669 3670 if (rxput[MSK_PORT_A] > 0) 3671 msk_rxput(sc->msk_if[MSK_PORT_A]); 3672 if (rxput[MSK_PORT_B] > 0) 3673 msk_rxput(sc->msk_if[MSK_PORT_B]); 3674 3675 return (sc->msk_stat_cons != CSR_READ_2(sc, STAT_PUT_IDX)); 3676 } 3677 3678 static void 3679 msk_intr(void *xsc) 3680 { 3681 struct msk_softc *sc; 3682 struct msk_if_softc *sc_if0, *sc_if1; 3683 if_t ifp0, ifp1; 3684 uint32_t status; 3685 int domore; 3686 3687 sc = xsc; 3688 MSK_LOCK(sc); 3689 3690 /* Reading B0_Y2_SP_ISRC2 masks further interrupts. */ 3691 status = CSR_READ_4(sc, B0_Y2_SP_ISRC2); 3692 if (status == 0 || status == 0xffffffff || 3693 (sc->msk_pflags & MSK_FLAG_SUSPEND) != 0 || 3694 (status & sc->msk_intrmask) == 0) { 3695 CSR_WRITE_4(sc, B0_Y2_SP_ICR, 2); 3696 MSK_UNLOCK(sc); 3697 return; 3698 } 3699 3700 sc_if0 = sc->msk_if[MSK_PORT_A]; 3701 sc_if1 = sc->msk_if[MSK_PORT_B]; 3702 ifp0 = ifp1 = NULL; 3703 if (sc_if0 != NULL) 3704 ifp0 = sc_if0->msk_ifp; 3705 if (sc_if1 != NULL) 3706 ifp1 = sc_if1->msk_ifp; 3707 3708 if ((status & Y2_IS_IRQ_PHY1) != 0 && sc_if0 != NULL) 3709 msk_intr_phy(sc_if0); 3710 if ((status & Y2_IS_IRQ_PHY2) != 0 && sc_if1 != NULL) 3711 msk_intr_phy(sc_if1); 3712 if ((status & Y2_IS_IRQ_MAC1) != 0 && sc_if0 != NULL) 3713 msk_intr_gmac(sc_if0); 3714 if ((status & Y2_IS_IRQ_MAC2) != 0 && sc_if1 != NULL) 3715 msk_intr_gmac(sc_if1); 3716 if ((status & (Y2_IS_CHK_RX1 | Y2_IS_CHK_RX2)) != 0) { 3717 device_printf(sc->msk_dev, "Rx descriptor error\n"); 3718 sc->msk_intrmask &= ~(Y2_IS_CHK_RX1 | Y2_IS_CHK_RX2); 3719 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask); 3720 CSR_READ_4(sc, B0_IMSK); 3721 } 3722 if ((status & (Y2_IS_CHK_TXA1 | Y2_IS_CHK_TXA2)) != 0) { 3723 device_printf(sc->msk_dev, "Tx descriptor error\n"); 3724 sc->msk_intrmask &= ~(Y2_IS_CHK_TXA1 | Y2_IS_CHK_TXA2); 3725 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask); 3726 CSR_READ_4(sc, B0_IMSK); 3727 } 3728 if ((status & Y2_IS_HW_ERR) != 0) 3729 msk_intr_hwerr(sc); 3730 3731 domore = msk_handle_events(sc); 3732 if ((status & Y2_IS_STAT_BMU) != 0 && domore == 0) 3733 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_CLR_IRQ); 3734 3735 /* Reenable interrupts. */ 3736 CSR_WRITE_4(sc, B0_Y2_SP_ICR, 2); 3737 3738 if (ifp0 != NULL && (if_getdrvflags(ifp0) & IFF_DRV_RUNNING) != 0 && 3739 !if_sendq_empty(ifp0)) 3740 msk_start_locked(ifp0); 3741 if (ifp1 != NULL && (if_getdrvflags(ifp1) & IFF_DRV_RUNNING) != 0 && 3742 !if_sendq_empty(ifp1)) 3743 msk_start_locked(ifp1); 3744 3745 MSK_UNLOCK(sc); 3746 } 3747 3748 static void 3749 msk_set_tx_stfwd(struct msk_if_softc *sc_if) 3750 { 3751 struct msk_softc *sc; 3752 if_t ifp; 3753 3754 ifp = sc_if->msk_ifp; 3755 sc = sc_if->msk_softc; 3756 if ((sc->msk_hw_id == CHIP_ID_YUKON_EX && 3757 sc->msk_hw_rev != CHIP_REV_YU_EX_A0) || 3758 sc->msk_hw_id >= CHIP_ID_YUKON_SUPR) { 3759 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 3760 TX_STFW_ENA); 3761 } else { 3762 if (if_getmtu(ifp) > ETHERMTU) { 3763 /* Set Tx GMAC FIFO Almost Empty Threshold. */ 3764 CSR_WRITE_4(sc, 3765 MR_ADDR(sc_if->msk_port, TX_GMF_AE_THR), 3766 MSK_ECU_JUMBO_WM << 16 | MSK_ECU_AE_THR); 3767 /* Disable Store & Forward mode for Tx. */ 3768 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 3769 TX_STFW_DIS); 3770 } else { 3771 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 3772 TX_STFW_ENA); 3773 } 3774 } 3775 } 3776 3777 static void 3778 msk_init(void *xsc) 3779 { 3780 struct msk_if_softc *sc_if = xsc; 3781 3782 MSK_IF_LOCK(sc_if); 3783 msk_init_locked(sc_if); 3784 MSK_IF_UNLOCK(sc_if); 3785 } 3786 3787 static void 3788 msk_init_locked(struct msk_if_softc *sc_if) 3789 { 3790 struct msk_softc *sc; 3791 if_t ifp; 3792 struct mii_data *mii; 3793 uint8_t *eaddr; 3794 uint16_t gmac; 3795 uint32_t reg; 3796 int error; 3797 3798 MSK_IF_LOCK_ASSERT(sc_if); 3799 3800 ifp = sc_if->msk_ifp; 3801 sc = sc_if->msk_softc; 3802 mii = device_get_softc(sc_if->msk_miibus); 3803 3804 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 3805 return; 3806 3807 error = 0; 3808 /* Cancel pending I/O and free all Rx/Tx buffers. */ 3809 msk_stop(sc_if); 3810 3811 if (if_getmtu(ifp) < ETHERMTU) 3812 sc_if->msk_framesize = ETHERMTU; 3813 else 3814 sc_if->msk_framesize = if_getmtu(ifp); 3815 sc_if->msk_framesize += ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 3816 if (if_getmtu(ifp) > ETHERMTU && 3817 (sc_if->msk_flags & MSK_FLAG_JUMBO_NOCSUM) != 0) { 3818 if_sethwassistbits(ifp, 0, (MSK_CSUM_FEATURES | CSUM_TSO)); 3819 if_setcapenablebit(ifp, 0, (IFCAP_TSO4 | IFCAP_TXCSUM)); 3820 } 3821 3822 /* GMAC Control reset. */ 3823 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_RST_SET); 3824 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_RST_CLR); 3825 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_F_LOOPB_OFF); 3826 if (sc->msk_hw_id == CHIP_ID_YUKON_EX || 3827 sc->msk_hw_id == CHIP_ID_YUKON_SUPR) 3828 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), 3829 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON | 3830 GMC_BYP_RETR_ON); 3831 3832 /* 3833 * Initialize GMAC first such that speed/duplex/flow-control 3834 * parameters are renegotiated when interface is brought up. 3835 */ 3836 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, 0); 3837 3838 /* Dummy read the Interrupt Source Register. */ 3839 CSR_READ_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_SRC)); 3840 3841 /* Clear MIB stats. */ 3842 msk_stats_clear(sc_if); 3843 3844 /* Disable FCS. */ 3845 GMAC_WRITE_2(sc, sc_if->msk_port, GM_RX_CTRL, GM_RXCR_CRC_DIS); 3846 3847 /* Setup Transmit Control Register. */ 3848 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF)); 3849 3850 /* Setup Transmit Flow Control Register. */ 3851 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_FLOW_CTRL, 0xffff); 3852 3853 /* Setup Transmit Parameter Register. */ 3854 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_PARAM, 3855 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) | TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) | 3856 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) | TX_BACK_OFF_LIM(TX_BOF_LIM_DEF)); 3857 3858 gmac = DATA_BLIND_VAL(DATA_BLIND_DEF) | 3859 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF); 3860 3861 if (if_getmtu(ifp) > ETHERMTU) 3862 gmac |= GM_SMOD_JUMBO_ENA; 3863 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SERIAL_MODE, gmac); 3864 3865 /* Set station address. */ 3866 eaddr = if_getlladdr(ifp); 3867 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_1L, 3868 eaddr[0] | (eaddr[1] << 8)); 3869 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_1M, 3870 eaddr[2] | (eaddr[3] << 8)); 3871 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_1H, 3872 eaddr[4] | (eaddr[5] << 8)); 3873 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_2L, 3874 eaddr[0] | (eaddr[1] << 8)); 3875 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_2M, 3876 eaddr[2] | (eaddr[3] << 8)); 3877 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_2H, 3878 eaddr[4] | (eaddr[5] << 8)); 3879 3880 /* Disable interrupts for counter overflows. */ 3881 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_IRQ_MSK, 0); 3882 GMAC_WRITE_2(sc, sc_if->msk_port, GM_RX_IRQ_MSK, 0); 3883 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TR_IRQ_MSK, 0); 3884 3885 /* Configure Rx MAC FIFO. */ 3886 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), GMF_RST_SET); 3887 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), GMF_RST_CLR); 3888 reg = GMF_OPER_ON | GMF_RX_F_FL_ON; 3889 if (sc->msk_hw_id == CHIP_ID_YUKON_FE_P || 3890 sc->msk_hw_id == CHIP_ID_YUKON_EX) 3891 reg |= GMF_RX_OVER_ON; 3892 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), reg); 3893 3894 /* Set receive filter. */ 3895 msk_rxfilter(sc_if); 3896 3897 if (sc->msk_hw_id == CHIP_ID_YUKON_XL) { 3898 /* Clear flush mask - HW bug. */ 3899 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_FL_MSK), 0); 3900 } else { 3901 /* Flush Rx MAC FIFO on any flow control or error. */ 3902 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_FL_MSK), 3903 GMR_FS_ANY_ERR); 3904 } 3905 3906 /* 3907 * Set Rx FIFO flush threshold to 64 bytes + 1 FIFO word 3908 * due to hardware hang on receipt of pause frames. 3909 */ 3910 reg = RX_GMF_FL_THR_DEF + 1; 3911 /* Another magic for Yukon FE+ - From Linux. */ 3912 if (sc->msk_hw_id == CHIP_ID_YUKON_FE_P && 3913 sc->msk_hw_rev == CHIP_REV_YU_FE_P_A0) 3914 reg = 0x178; 3915 CSR_WRITE_2(sc, MR_ADDR(sc_if->msk_port, RX_GMF_FL_THR), reg); 3916 3917 /* Configure Tx MAC FIFO. */ 3918 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_RST_SET); 3919 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_RST_CLR); 3920 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_OPER_ON); 3921 3922 /* Configure hardware VLAN tag insertion/stripping. */ 3923 msk_setvlan(sc_if, ifp); 3924 3925 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) == 0) { 3926 /* Set Rx Pause threshold. */ 3927 CSR_WRITE_2(sc, MR_ADDR(sc_if->msk_port, RX_GMF_LP_THR), 3928 MSK_ECU_LLPP); 3929 CSR_WRITE_2(sc, MR_ADDR(sc_if->msk_port, RX_GMF_UP_THR), 3930 MSK_ECU_ULPP); 3931 /* Configure store-and-forward for Tx. */ 3932 msk_set_tx_stfwd(sc_if); 3933 } 3934 3935 if (sc->msk_hw_id == CHIP_ID_YUKON_FE_P && 3936 sc->msk_hw_rev == CHIP_REV_YU_FE_P_A0) { 3937 /* Disable dynamic watermark - from Linux. */ 3938 reg = CSR_READ_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_EA)); 3939 reg &= ~0x03; 3940 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_EA), reg); 3941 } 3942 3943 /* 3944 * Disable Force Sync bit and Alloc bit in Tx RAM interface 3945 * arbiter as we don't use Sync Tx queue. 3946 */ 3947 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, TXA_CTRL), 3948 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC); 3949 /* Enable the RAM Interface Arbiter. */ 3950 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, TXA_CTRL), TXA_ENA_ARB); 3951 3952 /* Setup RAM buffer. */ 3953 msk_set_rambuffer(sc_if); 3954 3955 /* Disable Tx sync Queue. */ 3956 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txsq, RB_CTRL), RB_RST_SET); 3957 3958 /* Setup Tx Queue Bus Memory Interface. */ 3959 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_CLR_RESET); 3960 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_OPER_INIT); 3961 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_FIFO_OP_ON); 3962 CSR_WRITE_2(sc, Q_ADDR(sc_if->msk_txq, Q_WM), MSK_BMU_TX_WM); 3963 switch (sc->msk_hw_id) { 3964 case CHIP_ID_YUKON_EC_U: 3965 if (sc->msk_hw_rev == CHIP_REV_YU_EC_U_A0) { 3966 /* Fix for Yukon-EC Ultra: set BMU FIFO level */ 3967 CSR_WRITE_2(sc, Q_ADDR(sc_if->msk_txq, Q_AL), 3968 MSK_ECU_TXFF_LEV); 3969 } 3970 break; 3971 case CHIP_ID_YUKON_EX: 3972 /* 3973 * Yukon Extreme seems to have silicon bug for 3974 * automatic Tx checksum calculation capability. 3975 */ 3976 if (sc->msk_hw_rev == CHIP_REV_YU_EX_B0) 3977 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_F), 3978 F_TX_CHK_AUTO_OFF); 3979 break; 3980 } 3981 3982 /* Setup Rx Queue Bus Memory Interface. */ 3983 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_CLR_RESET); 3984 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_OPER_INIT); 3985 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_FIFO_OP_ON); 3986 CSR_WRITE_2(sc, Q_ADDR(sc_if->msk_rxq, Q_WM), MSK_BMU_RX_WM); 3987 if (sc->msk_hw_id == CHIP_ID_YUKON_EC_U && 3988 sc->msk_hw_rev >= CHIP_REV_YU_EC_U_A1) { 3989 /* MAC Rx RAM Read is controlled by hardware. */ 3990 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_F), F_M_RX_RAM_DIS); 3991 } 3992 3993 msk_set_prefetch(sc, sc_if->msk_txq, 3994 sc_if->msk_rdata.msk_tx_ring_paddr, MSK_TX_RING_CNT - 1); 3995 msk_init_tx_ring(sc_if); 3996 3997 /* Disable Rx checksum offload and RSS hash. */ 3998 reg = BMU_DIS_RX_RSS_HASH; 3999 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0 && 4000 (if_getcapenable(ifp) & IFCAP_RXCSUM) != 0) 4001 reg |= BMU_ENA_RX_CHKSUM; 4002 else 4003 reg |= BMU_DIS_RX_CHKSUM; 4004 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), reg); 4005 if (sc_if->msk_framesize > (MCLBYTES - MSK_RX_BUF_ALIGN)) { 4006 msk_set_prefetch(sc, sc_if->msk_rxq, 4007 sc_if->msk_rdata.msk_jumbo_rx_ring_paddr, 4008 MSK_JUMBO_RX_RING_CNT - 1); 4009 error = msk_init_jumbo_rx_ring(sc_if); 4010 } else { 4011 msk_set_prefetch(sc, sc_if->msk_rxq, 4012 sc_if->msk_rdata.msk_rx_ring_paddr, 4013 MSK_RX_RING_CNT - 1); 4014 error = msk_init_rx_ring(sc_if); 4015 } 4016 if (error != 0) { 4017 device_printf(sc_if->msk_if_dev, 4018 "initialization failed: no memory for Rx buffers\n"); 4019 msk_stop(sc_if); 4020 return; 4021 } 4022 if (sc->msk_hw_id == CHIP_ID_YUKON_EX || 4023 sc->msk_hw_id == CHIP_ID_YUKON_SUPR) { 4024 /* Disable flushing of non-ASF packets. */ 4025 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), 4026 GMF_RX_MACSEC_FLUSH_OFF); 4027 } 4028 4029 /* Configure interrupt handling. */ 4030 if (sc_if->msk_port == MSK_PORT_A) { 4031 sc->msk_intrmask |= Y2_IS_PORT_A; 4032 sc->msk_intrhwemask |= Y2_HWE_L1_MASK; 4033 } else { 4034 sc->msk_intrmask |= Y2_IS_PORT_B; 4035 sc->msk_intrhwemask |= Y2_HWE_L2_MASK; 4036 } 4037 /* Configure IRQ moderation mask. */ 4038 CSR_WRITE_4(sc, B2_IRQM_MSK, sc->msk_intrmask); 4039 if (sc->msk_int_holdoff > 0) { 4040 /* Configure initial IRQ moderation timer value. */ 4041 CSR_WRITE_4(sc, B2_IRQM_INI, 4042 MSK_USECS(sc, sc->msk_int_holdoff)); 4043 CSR_WRITE_4(sc, B2_IRQM_VAL, 4044 MSK_USECS(sc, sc->msk_int_holdoff)); 4045 /* Start IRQ moderation. */ 4046 CSR_WRITE_1(sc, B2_IRQM_CTRL, TIM_START); 4047 } 4048 CSR_WRITE_4(sc, B0_HWE_IMSK, sc->msk_intrhwemask); 4049 CSR_READ_4(sc, B0_HWE_IMSK); 4050 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask); 4051 CSR_READ_4(sc, B0_IMSK); 4052 4053 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0); 4054 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 4055 4056 sc_if->msk_flags &= ~MSK_FLAG_LINK; 4057 mii_mediachg(mii); 4058 4059 callout_reset(&sc_if->msk_tick_ch, hz, msk_tick, sc_if); 4060 } 4061 4062 static void 4063 msk_set_rambuffer(struct msk_if_softc *sc_if) 4064 { 4065 struct msk_softc *sc; 4066 int ltpp, utpp; 4067 4068 sc = sc_if->msk_softc; 4069 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) == 0) 4070 return; 4071 4072 /* Setup Rx Queue. */ 4073 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_RST_CLR); 4074 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_START), 4075 sc->msk_rxqstart[sc_if->msk_port] / 8); 4076 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_END), 4077 sc->msk_rxqend[sc_if->msk_port] / 8); 4078 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_WP), 4079 sc->msk_rxqstart[sc_if->msk_port] / 8); 4080 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_RP), 4081 sc->msk_rxqstart[sc_if->msk_port] / 8); 4082 4083 utpp = (sc->msk_rxqend[sc_if->msk_port] + 1 - 4084 sc->msk_rxqstart[sc_if->msk_port] - MSK_RB_ULPP) / 8; 4085 ltpp = (sc->msk_rxqend[sc_if->msk_port] + 1 - 4086 sc->msk_rxqstart[sc_if->msk_port] - MSK_RB_LLPP_B) / 8; 4087 if (sc->msk_rxqsize < MSK_MIN_RXQ_SIZE) 4088 ltpp += (MSK_RB_LLPP_B - MSK_RB_LLPP_S) / 8; 4089 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_RX_UTPP), utpp); 4090 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_RX_LTPP), ltpp); 4091 /* Set Rx priority(RB_RX_UTHP/RB_RX_LTHP) thresholds? */ 4092 4093 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_ENA_OP_MD); 4094 CSR_READ_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL)); 4095 4096 /* Setup Tx Queue. */ 4097 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_RST_CLR); 4098 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_START), 4099 sc->msk_txqstart[sc_if->msk_port] / 8); 4100 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_END), 4101 sc->msk_txqend[sc_if->msk_port] / 8); 4102 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_WP), 4103 sc->msk_txqstart[sc_if->msk_port] / 8); 4104 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_RP), 4105 sc->msk_txqstart[sc_if->msk_port] / 8); 4106 /* Enable Store & Forward for Tx side. */ 4107 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_ENA_STFWD); 4108 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_ENA_OP_MD); 4109 CSR_READ_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL)); 4110 } 4111 4112 static void 4113 msk_set_prefetch(struct msk_softc *sc, int qaddr, bus_addr_t addr, 4114 uint32_t count) 4115 { 4116 4117 /* Reset the prefetch unit. */ 4118 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG), 4119 PREF_UNIT_RST_SET); 4120 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG), 4121 PREF_UNIT_RST_CLR); 4122 /* Set LE base address. */ 4123 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_ADDR_LOW_REG), 4124 MSK_ADDR_LO(addr)); 4125 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_ADDR_HI_REG), 4126 MSK_ADDR_HI(addr)); 4127 /* Set the list last index. */ 4128 CSR_WRITE_2(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_LAST_IDX_REG), 4129 count); 4130 /* Turn on prefetch unit. */ 4131 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG), 4132 PREF_UNIT_OP_ON); 4133 /* Dummy read to ensure write. */ 4134 CSR_READ_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG)); 4135 } 4136 4137 static void 4138 msk_stop(struct msk_if_softc *sc_if) 4139 { 4140 struct msk_softc *sc; 4141 struct msk_txdesc *txd; 4142 struct msk_rxdesc *rxd; 4143 struct msk_rxdesc *jrxd; 4144 if_t ifp; 4145 uint32_t val; 4146 int i; 4147 4148 MSK_IF_LOCK_ASSERT(sc_if); 4149 sc = sc_if->msk_softc; 4150 ifp = sc_if->msk_ifp; 4151 4152 callout_stop(&sc_if->msk_tick_ch); 4153 sc_if->msk_watchdog_timer = 0; 4154 4155 /* Disable interrupts. */ 4156 if (sc_if->msk_port == MSK_PORT_A) { 4157 sc->msk_intrmask &= ~Y2_IS_PORT_A; 4158 sc->msk_intrhwemask &= ~Y2_HWE_L1_MASK; 4159 } else { 4160 sc->msk_intrmask &= ~Y2_IS_PORT_B; 4161 sc->msk_intrhwemask &= ~Y2_HWE_L2_MASK; 4162 } 4163 CSR_WRITE_4(sc, B0_HWE_IMSK, sc->msk_intrhwemask); 4164 CSR_READ_4(sc, B0_HWE_IMSK); 4165 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask); 4166 CSR_READ_4(sc, B0_IMSK); 4167 4168 /* Disable Tx/Rx MAC. */ 4169 val = GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL); 4170 val &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA); 4171 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, val); 4172 /* Read again to ensure writing. */ 4173 GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL); 4174 /* Update stats and clear counters. */ 4175 msk_stats_update(sc_if); 4176 4177 /* Stop Tx BMU. */ 4178 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_STOP); 4179 val = CSR_READ_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR)); 4180 for (i = 0; i < MSK_TIMEOUT; i++) { 4181 if ((val & (BMU_STOP | BMU_IDLE)) == 0) { 4182 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), 4183 BMU_STOP); 4184 val = CSR_READ_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR)); 4185 } else 4186 break; 4187 DELAY(1); 4188 } 4189 if (i == MSK_TIMEOUT) 4190 device_printf(sc_if->msk_if_dev, "Tx BMU stop failed\n"); 4191 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), 4192 RB_RST_SET | RB_DIS_OP_MD); 4193 4194 /* Disable all GMAC interrupt. */ 4195 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_MSK), 0); 4196 /* Disable PHY interrupt. */ 4197 msk_phy_writereg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_MASK, 0); 4198 4199 /* Disable the RAM Interface Arbiter. */ 4200 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, TXA_CTRL), TXA_DIS_ARB); 4201 4202 /* Reset the PCI FIFO of the async Tx queue */ 4203 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), 4204 BMU_RST_SET | BMU_FIFO_RST); 4205 4206 /* Reset the Tx prefetch units. */ 4207 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(sc_if->msk_txq, PREF_UNIT_CTRL_REG), 4208 PREF_UNIT_RST_SET); 4209 4210 /* Reset the RAM Buffer async Tx queue. */ 4211 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_RST_SET); 4212 4213 /* Reset Tx MAC FIFO. */ 4214 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_RST_SET); 4215 /* Set Pause Off. */ 4216 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_PAUSE_OFF); 4217 4218 /* 4219 * The Rx Stop command will not work for Yukon-2 if the BMU does not 4220 * reach the end of packet and since we can't make sure that we have 4221 * incoming data, we must reset the BMU while it is not during a DMA 4222 * transfer. Since it is possible that the Rx path is still active, 4223 * the Rx RAM buffer will be stopped first, so any possible incoming 4224 * data will not trigger a DMA. After the RAM buffer is stopped, the 4225 * BMU is polled until any DMA in progress is ended and only then it 4226 * will be reset. 4227 */ 4228 4229 /* Disable the RAM Buffer receive queue. */ 4230 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_DIS_OP_MD); 4231 for (i = 0; i < MSK_TIMEOUT; i++) { 4232 if (CSR_READ_1(sc, RB_ADDR(sc_if->msk_rxq, Q_RSL)) == 4233 CSR_READ_1(sc, RB_ADDR(sc_if->msk_rxq, Q_RL))) 4234 break; 4235 DELAY(1); 4236 } 4237 if (i == MSK_TIMEOUT) 4238 device_printf(sc_if->msk_if_dev, "Rx BMU stop failed\n"); 4239 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), 4240 BMU_RST_SET | BMU_FIFO_RST); 4241 /* Reset the Rx prefetch unit. */ 4242 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_CTRL_REG), 4243 PREF_UNIT_RST_SET); 4244 /* Reset the RAM Buffer receive queue. */ 4245 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_RST_SET); 4246 /* Reset Rx MAC FIFO. */ 4247 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), GMF_RST_SET); 4248 4249 /* Free Rx and Tx mbufs still in the queues. */ 4250 for (i = 0; i < MSK_RX_RING_CNT; i++) { 4251 rxd = &sc_if->msk_cdata.msk_rxdesc[i]; 4252 if (rxd->rx_m != NULL) { 4253 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_tag, 4254 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 4255 bus_dmamap_unload(sc_if->msk_cdata.msk_rx_tag, 4256 rxd->rx_dmamap); 4257 m_freem(rxd->rx_m); 4258 rxd->rx_m = NULL; 4259 } 4260 } 4261 for (i = 0; i < MSK_JUMBO_RX_RING_CNT; i++) { 4262 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[i]; 4263 if (jrxd->rx_m != NULL) { 4264 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_tag, 4265 jrxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 4266 bus_dmamap_unload(sc_if->msk_cdata.msk_jumbo_rx_tag, 4267 jrxd->rx_dmamap); 4268 m_freem(jrxd->rx_m); 4269 jrxd->rx_m = NULL; 4270 } 4271 } 4272 for (i = 0; i < MSK_TX_RING_CNT; i++) { 4273 txd = &sc_if->msk_cdata.msk_txdesc[i]; 4274 if (txd->tx_m != NULL) { 4275 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_tag, 4276 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 4277 bus_dmamap_unload(sc_if->msk_cdata.msk_tx_tag, 4278 txd->tx_dmamap); 4279 m_freem(txd->tx_m); 4280 txd->tx_m = NULL; 4281 } 4282 } 4283 4284 /* 4285 * Mark the interface down. 4286 */ 4287 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)); 4288 sc_if->msk_flags &= ~MSK_FLAG_LINK; 4289 } 4290 4291 /* 4292 * When GM_PAR_MIB_CLR bit of GM_PHY_ADDR is set, reading lower 4293 * counter clears high 16 bits of the counter such that accessing 4294 * lower 16 bits should be the last operation. 4295 */ 4296 #define MSK_READ_MIB32(x, y) \ 4297 ((((uint32_t)GMAC_READ_2(sc, x, (y) + 4)) << 16) + \ 4298 (uint32_t)GMAC_READ_2(sc, x, y)) 4299 #define MSK_READ_MIB64(x, y) \ 4300 ((((uint64_t)MSK_READ_MIB32(x, (y) + 8)) << 32) + \ 4301 (uint64_t)MSK_READ_MIB32(x, y)) 4302 4303 static void 4304 msk_stats_clear(struct msk_if_softc *sc_if) 4305 { 4306 struct msk_softc *sc; 4307 uint16_t gmac; 4308 int i; 4309 4310 MSK_IF_LOCK_ASSERT(sc_if); 4311 4312 sc = sc_if->msk_softc; 4313 /* Set MIB Clear Counter Mode. */ 4314 gmac = GMAC_READ_2(sc, sc_if->msk_port, GM_PHY_ADDR); 4315 GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac | GM_PAR_MIB_CLR); 4316 /* Read all MIB Counters with Clear Mode set. */ 4317 for (i = GM_RXF_UC_OK; i <= GM_TXE_FIFO_UR; i += sizeof(uint32_t)) 4318 (void)MSK_READ_MIB32(sc_if->msk_port, i); 4319 /* Clear MIB Clear Counter Mode. */ 4320 gmac &= ~GM_PAR_MIB_CLR; 4321 GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac); 4322 } 4323 4324 static void 4325 msk_stats_update(struct msk_if_softc *sc_if) 4326 { 4327 struct msk_softc *sc; 4328 if_t ifp; 4329 struct msk_hw_stats *stats; 4330 uint16_t gmac; 4331 4332 MSK_IF_LOCK_ASSERT(sc_if); 4333 4334 ifp = sc_if->msk_ifp; 4335 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) 4336 return; 4337 sc = sc_if->msk_softc; 4338 stats = &sc_if->msk_stats; 4339 /* Set MIB Clear Counter Mode. */ 4340 gmac = GMAC_READ_2(sc, sc_if->msk_port, GM_PHY_ADDR); 4341 GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac | GM_PAR_MIB_CLR); 4342 4343 /* Rx stats. */ 4344 stats->rx_ucast_frames += 4345 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_UC_OK); 4346 stats->rx_bcast_frames += 4347 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_BC_OK); 4348 stats->rx_pause_frames += 4349 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_MPAUSE); 4350 stats->rx_mcast_frames += 4351 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_MC_OK); 4352 stats->rx_crc_errs += 4353 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_FCS_ERR); 4354 stats->rx_good_octets += 4355 MSK_READ_MIB64(sc_if->msk_port, GM_RXO_OK_LO); 4356 stats->rx_bad_octets += 4357 MSK_READ_MIB64(sc_if->msk_port, GM_RXO_ERR_LO); 4358 stats->rx_runts += 4359 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_SHT); 4360 stats->rx_runt_errs += 4361 MSK_READ_MIB32(sc_if->msk_port, GM_RXE_FRAG); 4362 stats->rx_pkts_64 += 4363 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_64B); 4364 stats->rx_pkts_65_127 += 4365 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_127B); 4366 stats->rx_pkts_128_255 += 4367 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_255B); 4368 stats->rx_pkts_256_511 += 4369 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_511B); 4370 stats->rx_pkts_512_1023 += 4371 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_1023B); 4372 stats->rx_pkts_1024_1518 += 4373 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_1518B); 4374 stats->rx_pkts_1519_max += 4375 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_MAX_SZ); 4376 stats->rx_pkts_too_long += 4377 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_LNG_ERR); 4378 stats->rx_pkts_jabbers += 4379 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_JAB_PKT); 4380 stats->rx_fifo_oflows += 4381 MSK_READ_MIB32(sc_if->msk_port, GM_RXE_FIFO_OV); 4382 4383 /* Tx stats. */ 4384 stats->tx_ucast_frames += 4385 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_UC_OK); 4386 stats->tx_bcast_frames += 4387 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_BC_OK); 4388 stats->tx_pause_frames += 4389 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_MPAUSE); 4390 stats->tx_mcast_frames += 4391 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_MC_OK); 4392 stats->tx_octets += 4393 MSK_READ_MIB64(sc_if->msk_port, GM_TXO_OK_LO); 4394 stats->tx_pkts_64 += 4395 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_64B); 4396 stats->tx_pkts_65_127 += 4397 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_127B); 4398 stats->tx_pkts_128_255 += 4399 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_255B); 4400 stats->tx_pkts_256_511 += 4401 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_511B); 4402 stats->tx_pkts_512_1023 += 4403 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_1023B); 4404 stats->tx_pkts_1024_1518 += 4405 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_1518B); 4406 stats->tx_pkts_1519_max += 4407 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_MAX_SZ); 4408 stats->tx_colls += 4409 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_COL); 4410 stats->tx_late_colls += 4411 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_LAT_COL); 4412 stats->tx_excess_colls += 4413 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_ABO_COL); 4414 stats->tx_multi_colls += 4415 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_MUL_COL); 4416 stats->tx_single_colls += 4417 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_SNG_COL); 4418 stats->tx_underflows += 4419 MSK_READ_MIB32(sc_if->msk_port, GM_TXE_FIFO_UR); 4420 /* Clear MIB Clear Counter Mode. */ 4421 gmac &= ~GM_PAR_MIB_CLR; 4422 GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac); 4423 } 4424 4425 static int 4426 msk_sysctl_stat32(SYSCTL_HANDLER_ARGS) 4427 { 4428 struct msk_softc *sc; 4429 struct msk_if_softc *sc_if; 4430 uint32_t result, *stat; 4431 int off; 4432 4433 sc_if = (struct msk_if_softc *)arg1; 4434 sc = sc_if->msk_softc; 4435 off = arg2; 4436 stat = (uint32_t *)((uint8_t *)&sc_if->msk_stats + off); 4437 4438 MSK_IF_LOCK(sc_if); 4439 result = MSK_READ_MIB32(sc_if->msk_port, GM_MIB_CNT_BASE + off * 2); 4440 result += *stat; 4441 MSK_IF_UNLOCK(sc_if); 4442 4443 return (sysctl_handle_int(oidp, &result, 0, req)); 4444 } 4445 4446 static int 4447 msk_sysctl_stat64(SYSCTL_HANDLER_ARGS) 4448 { 4449 struct msk_softc *sc; 4450 struct msk_if_softc *sc_if; 4451 uint64_t result, *stat; 4452 int off; 4453 4454 sc_if = (struct msk_if_softc *)arg1; 4455 sc = sc_if->msk_softc; 4456 off = arg2; 4457 stat = (uint64_t *)((uint8_t *)&sc_if->msk_stats + off); 4458 4459 MSK_IF_LOCK(sc_if); 4460 result = MSK_READ_MIB64(sc_if->msk_port, GM_MIB_CNT_BASE + off * 2); 4461 result += *stat; 4462 MSK_IF_UNLOCK(sc_if); 4463 4464 return (sysctl_handle_64(oidp, &result, 0, req)); 4465 } 4466 4467 #undef MSK_READ_MIB32 4468 #undef MSK_READ_MIB64 4469 4470 #define MSK_SYSCTL_STAT32(sc, c, o, p, n, d) \ 4471 SYSCTL_ADD_PROC(c, p, OID_AUTO, o, \ 4472 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, \ 4473 sc, offsetof(struct msk_hw_stats, n), msk_sysctl_stat32, \ 4474 "IU", d) 4475 #define MSK_SYSCTL_STAT64(sc, c, o, p, n, d) \ 4476 SYSCTL_ADD_PROC(c, p, OID_AUTO, o, \ 4477 CTLTYPE_U64 | CTLFLAG_RD | CTLFLAG_NEEDGIANT, \ 4478 sc, offsetof(struct msk_hw_stats, n), msk_sysctl_stat64, \ 4479 "QU", d) 4480 4481 static void 4482 msk_sysctl_node(struct msk_if_softc *sc_if) 4483 { 4484 struct sysctl_ctx_list *ctx; 4485 struct sysctl_oid_list *child, *schild; 4486 struct sysctl_oid *tree; 4487 4488 ctx = device_get_sysctl_ctx(sc_if->msk_if_dev); 4489 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc_if->msk_if_dev)); 4490 4491 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", 4492 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "MSK Statistics"); 4493 schild = SYSCTL_CHILDREN(tree); 4494 tree = SYSCTL_ADD_NODE(ctx, schild, OID_AUTO, "rx", 4495 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "MSK RX Statistics"); 4496 child = SYSCTL_CHILDREN(tree); 4497 MSK_SYSCTL_STAT32(sc_if, ctx, "ucast_frames", 4498 child, rx_ucast_frames, "Good unicast frames"); 4499 MSK_SYSCTL_STAT32(sc_if, ctx, "bcast_frames", 4500 child, rx_bcast_frames, "Good broadcast frames"); 4501 MSK_SYSCTL_STAT32(sc_if, ctx, "pause_frames", 4502 child, rx_pause_frames, "Pause frames"); 4503 MSK_SYSCTL_STAT32(sc_if, ctx, "mcast_frames", 4504 child, rx_mcast_frames, "Multicast frames"); 4505 MSK_SYSCTL_STAT32(sc_if, ctx, "crc_errs", 4506 child, rx_crc_errs, "CRC errors"); 4507 MSK_SYSCTL_STAT64(sc_if, ctx, "good_octets", 4508 child, rx_good_octets, "Good octets"); 4509 MSK_SYSCTL_STAT64(sc_if, ctx, "bad_octets", 4510 child, rx_bad_octets, "Bad octets"); 4511 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_64", 4512 child, rx_pkts_64, "64 bytes frames"); 4513 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_65_127", 4514 child, rx_pkts_65_127, "65 to 127 bytes frames"); 4515 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_128_255", 4516 child, rx_pkts_128_255, "128 to 255 bytes frames"); 4517 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_256_511", 4518 child, rx_pkts_256_511, "256 to 511 bytes frames"); 4519 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_512_1023", 4520 child, rx_pkts_512_1023, "512 to 1023 bytes frames"); 4521 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_1024_1518", 4522 child, rx_pkts_1024_1518, "1024 to 1518 bytes frames"); 4523 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_1519_max", 4524 child, rx_pkts_1519_max, "1519 to max frames"); 4525 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_too_long", 4526 child, rx_pkts_too_long, "frames too long"); 4527 MSK_SYSCTL_STAT32(sc_if, ctx, "jabbers", 4528 child, rx_pkts_jabbers, "Jabber errors"); 4529 MSK_SYSCTL_STAT32(sc_if, ctx, "overflows", 4530 child, rx_fifo_oflows, "FIFO overflows"); 4531 4532 tree = SYSCTL_ADD_NODE(ctx, schild, OID_AUTO, "tx", 4533 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "MSK TX Statistics"); 4534 child = SYSCTL_CHILDREN(tree); 4535 MSK_SYSCTL_STAT32(sc_if, ctx, "ucast_frames", 4536 child, tx_ucast_frames, "Unicast frames"); 4537 MSK_SYSCTL_STAT32(sc_if, ctx, "bcast_frames", 4538 child, tx_bcast_frames, "Broadcast frames"); 4539 MSK_SYSCTL_STAT32(sc_if, ctx, "pause_frames", 4540 child, tx_pause_frames, "Pause frames"); 4541 MSK_SYSCTL_STAT32(sc_if, ctx, "mcast_frames", 4542 child, tx_mcast_frames, "Multicast frames"); 4543 MSK_SYSCTL_STAT64(sc_if, ctx, "octets", 4544 child, tx_octets, "Octets"); 4545 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_64", 4546 child, tx_pkts_64, "64 bytes frames"); 4547 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_65_127", 4548 child, tx_pkts_65_127, "65 to 127 bytes frames"); 4549 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_128_255", 4550 child, tx_pkts_128_255, "128 to 255 bytes frames"); 4551 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_256_511", 4552 child, tx_pkts_256_511, "256 to 511 bytes frames"); 4553 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_512_1023", 4554 child, tx_pkts_512_1023, "512 to 1023 bytes frames"); 4555 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_1024_1518", 4556 child, tx_pkts_1024_1518, "1024 to 1518 bytes frames"); 4557 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_1519_max", 4558 child, tx_pkts_1519_max, "1519 to max frames"); 4559 MSK_SYSCTL_STAT32(sc_if, ctx, "colls", 4560 child, tx_colls, "Collisions"); 4561 MSK_SYSCTL_STAT32(sc_if, ctx, "late_colls", 4562 child, tx_late_colls, "Late collisions"); 4563 MSK_SYSCTL_STAT32(sc_if, ctx, "excess_colls", 4564 child, tx_excess_colls, "Excessive collisions"); 4565 MSK_SYSCTL_STAT32(sc_if, ctx, "multi_colls", 4566 child, tx_multi_colls, "Multiple collisions"); 4567 MSK_SYSCTL_STAT32(sc_if, ctx, "single_colls", 4568 child, tx_single_colls, "Single collisions"); 4569 MSK_SYSCTL_STAT32(sc_if, ctx, "underflows", 4570 child, tx_underflows, "FIFO underflows"); 4571 } 4572 4573 #undef MSK_SYSCTL_STAT32 4574 #undef MSK_SYSCTL_STAT64 4575 4576 static int 4577 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 4578 { 4579 int error, value; 4580 4581 if (!arg1) 4582 return (EINVAL); 4583 value = *(int *)arg1; 4584 error = sysctl_handle_int(oidp, &value, 0, req); 4585 if (error || !req->newptr) 4586 return (error); 4587 if (value < low || value > high) 4588 return (EINVAL); 4589 *(int *)arg1 = value; 4590 4591 return (0); 4592 } 4593 4594 static int 4595 sysctl_hw_msk_proc_limit(SYSCTL_HANDLER_ARGS) 4596 { 4597 4598 return (sysctl_int_range(oidp, arg1, arg2, req, MSK_PROC_MIN, 4599 MSK_PROC_MAX)); 4600 } 4601