1 /****************************************************************************** 2 * 3 * Name : sky2.c 4 * Project: Gigabit Ethernet Driver for FreeBSD 5.x/6.x 5 * Version: $Revision: 1.23 $ 6 * Date : $Date: 2005/12/22 09:04:11 $ 7 * Purpose: Main driver source file 8 * 9 *****************************************************************************/ 10 11 /****************************************************************************** 12 * 13 * LICENSE: 14 * Copyright (C) Marvell International Ltd. and/or its affiliates 15 * 16 * The computer program files contained in this folder ("Files") 17 * are provided to you under the BSD-type license terms provided 18 * below, and any use of such Files and any derivative works 19 * thereof created by you shall be governed by the following terms 20 * and conditions: 21 * 22 * - Redistributions of source code must retain the above copyright 23 * notice, this list of conditions and the following disclaimer. 24 * - Redistributions in binary form must reproduce the above 25 * copyright notice, this list of conditions and the following 26 * disclaimer in the documentation and/or other materials provided 27 * with the distribution. 28 * - Neither the name of Marvell nor the names of its contributors 29 * may be used to endorse or promote products derived from this 30 * software without specific prior written permission. 31 * 32 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 33 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 34 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 35 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 36 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 37 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 38 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 39 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 40 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 41 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 42 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED 43 * OF THE POSSIBILITY OF SUCH DAMAGE. 44 * /LICENSE 45 * 46 *****************************************************************************/ 47 48 /*- 49 * Copyright (c) 1997, 1998, 1999, 2000 50 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 51 * 52 * Redistribution and use in source and binary forms, with or without 53 * modification, are permitted provided that the following conditions 54 * are met: 55 * 1. Redistributions of source code must retain the above copyright 56 * notice, this list of conditions and the following disclaimer. 57 * 2. Redistributions in binary form must reproduce the above copyright 58 * notice, this list of conditions and the following disclaimer in the 59 * documentation and/or other materials provided with the distribution. 60 * 3. All advertising materials mentioning features or use of this software 61 * must display the following acknowledgement: 62 * This product includes software developed by Bill Paul. 63 * 4. Neither the name of the author nor the names of any co-contributors 64 * may be used to endorse or promote products derived from this software 65 * without specific prior written permission. 66 * 67 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 68 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 69 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 70 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 71 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 72 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 73 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 74 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 75 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 76 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 77 * THE POSSIBILITY OF SUCH DAMAGE. 78 */ 79 /*- 80 * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu> 81 * 82 * Permission to use, copy, modify, and distribute this software for any 83 * purpose with or without fee is hereby granted, provided that the above 84 * copyright notice and this permission notice appear in all copies. 85 * 86 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 87 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 88 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 89 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 90 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 91 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 92 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 93 */ 94 95 /* 96 * Device driver for the Marvell Yukon II Ethernet controller. 97 * Due to lack of documentation, this driver is based on the code from 98 * sk(4) and Marvell's myk(4) driver for FreeBSD 5.x. 99 */ 100 101 #include <sys/cdefs.h> 102 __FBSDID("$FreeBSD$"); 103 104 #include <sys/param.h> 105 #include <sys/systm.h> 106 #include <sys/bus.h> 107 #include <sys/endian.h> 108 #include <sys/mbuf.h> 109 #include <sys/malloc.h> 110 #include <sys/kernel.h> 111 #include <sys/module.h> 112 #include <sys/socket.h> 113 #include <sys/sockio.h> 114 #include <sys/queue.h> 115 #include <sys/sysctl.h> 116 #include <sys/taskqueue.h> 117 118 #include <net/bpf.h> 119 #include <net/ethernet.h> 120 #include <net/if.h> 121 #include <net/if_arp.h> 122 #include <net/if_dl.h> 123 #include <net/if_media.h> 124 #include <net/if_types.h> 125 #include <net/if_vlan_var.h> 126 127 #include <netinet/in.h> 128 #include <netinet/in_systm.h> 129 #include <netinet/ip.h> 130 #include <netinet/tcp.h> 131 #include <netinet/udp.h> 132 133 #include <machine/bus.h> 134 #include <machine/in_cksum.h> 135 #include <machine/resource.h> 136 #include <sys/rman.h> 137 138 #include <dev/mii/mii.h> 139 #include <dev/mii/miivar.h> 140 #include <dev/mii/brgphyreg.h> 141 142 #include <dev/pci/pcireg.h> 143 #include <dev/pci/pcivar.h> 144 145 #include <dev/msk/if_mskreg.h> 146 147 MODULE_DEPEND(msk, pci, 1, 1, 1); 148 MODULE_DEPEND(msk, ether, 1, 1, 1); 149 MODULE_DEPEND(msk, miibus, 1, 1, 1); 150 151 /* "device miibus" required. See GENERIC if you get errors here. */ 152 #include "miibus_if.h" 153 154 /* Tunables. */ 155 static int msi_disable = 0; 156 TUNABLE_INT("hw.msk.msi_disable", &msi_disable); 157 static int legacy_intr = 0; 158 TUNABLE_INT("hw.msk.legacy_intr", &legacy_intr); 159 160 #define MSK_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 161 162 /* 163 * Devices supported by this driver. 164 */ 165 static struct msk_product { 166 uint16_t msk_vendorid; 167 uint16_t msk_deviceid; 168 const char *msk_name; 169 } msk_products[] = { 170 { VENDORID_SK, DEVICEID_SK_YUKON2, 171 "SK-9Sxx Gigabit Ethernet" }, 172 { VENDORID_SK, DEVICEID_SK_YUKON2_EXPR, 173 "SK-9Exx Gigabit Ethernet"}, 174 { VENDORID_MARVELL, DEVICEID_MRVL_8021CU, 175 "Marvell Yukon 88E8021CU Gigabit Ethernet" }, 176 { VENDORID_MARVELL, DEVICEID_MRVL_8021X, 177 "Marvell Yukon 88E8021 SX/LX Gigabit Ethernet" }, 178 { VENDORID_MARVELL, DEVICEID_MRVL_8022CU, 179 "Marvell Yukon 88E8022CU Gigabit Ethernet" }, 180 { VENDORID_MARVELL, DEVICEID_MRVL_8022X, 181 "Marvell Yukon 88E8022 SX/LX Gigabit Ethernet" }, 182 { VENDORID_MARVELL, DEVICEID_MRVL_8061CU, 183 "Marvell Yukon 88E8061CU Gigabit Ethernet" }, 184 { VENDORID_MARVELL, DEVICEID_MRVL_8061X, 185 "Marvell Yukon 88E8061 SX/LX Gigabit Ethernet" }, 186 { VENDORID_MARVELL, DEVICEID_MRVL_8062CU, 187 "Marvell Yukon 88E8062CU Gigabit Ethernet" }, 188 { VENDORID_MARVELL, DEVICEID_MRVL_8062X, 189 "Marvell Yukon 88E8062 SX/LX Gigabit Ethernet" }, 190 { VENDORID_MARVELL, DEVICEID_MRVL_8035, 191 "Marvell Yukon 88E8035 Gigabit Ethernet" }, 192 { VENDORID_MARVELL, DEVICEID_MRVL_8036, 193 "Marvell Yukon 88E8036 Gigabit Ethernet" }, 194 { VENDORID_MARVELL, DEVICEID_MRVL_8038, 195 "Marvell Yukon 88E8038 Gigabit Ethernet" }, 196 { VENDORID_MARVELL, DEVICEID_MRVL_8039, 197 "Marvell Yukon 88E8039 Gigabit Ethernet" }, 198 { VENDORID_MARVELL, DEVICEID_MRVL_4361, 199 "Marvell Yukon 88E8050 Gigabit Ethernet" }, 200 { VENDORID_MARVELL, DEVICEID_MRVL_4360, 201 "Marvell Yukon 88E8052 Gigabit Ethernet" }, 202 { VENDORID_MARVELL, DEVICEID_MRVL_4362, 203 "Marvell Yukon 88E8053 Gigabit Ethernet" }, 204 { VENDORID_MARVELL, DEVICEID_MRVL_4363, 205 "Marvell Yukon 88E8055 Gigabit Ethernet" }, 206 { VENDORID_MARVELL, DEVICEID_MRVL_4364, 207 "Marvell Yukon 88E8056 Gigabit Ethernet" }, 208 { VENDORID_MARVELL, DEVICEID_MRVL_436A, 209 "Marvell Yukon 88E8058 Gigabit Ethernet" }, 210 { VENDORID_DLINK, DEVICEID_DLINK_DGE550SX, 211 "D-Link 550SX Gigabit Ethernet" }, 212 { VENDORID_DLINK, DEVICEID_DLINK_DGE560T, 213 "D-Link 560T Gigabit Ethernet" } 214 }; 215 216 static const char *model_name[] = { 217 "Yukon XL", 218 "Yukon EC Ultra", 219 "Yukon Unknown", 220 "Yukon EC", 221 "Yukon FE" 222 }; 223 224 static int mskc_probe(device_t); 225 static int mskc_attach(device_t); 226 static int mskc_detach(device_t); 227 static int mskc_shutdown(device_t); 228 static int mskc_setup_rambuffer(struct msk_softc *); 229 static int mskc_suspend(device_t); 230 static int mskc_resume(device_t); 231 static void mskc_reset(struct msk_softc *); 232 233 static int msk_probe(device_t); 234 static int msk_attach(device_t); 235 static int msk_detach(device_t); 236 237 static void msk_tick(void *); 238 static void msk_legacy_intr(void *); 239 static int msk_intr(void *); 240 static void msk_int_task(void *, int); 241 static void msk_intr_phy(struct msk_if_softc *); 242 static void msk_intr_gmac(struct msk_if_softc *); 243 static __inline void msk_rxput(struct msk_if_softc *); 244 static int msk_handle_events(struct msk_softc *); 245 static void msk_handle_hwerr(struct msk_if_softc *, uint32_t); 246 static void msk_intr_hwerr(struct msk_softc *); 247 static void msk_rxeof(struct msk_if_softc *, uint32_t, int); 248 static void msk_jumbo_rxeof(struct msk_if_softc *, uint32_t, int); 249 static void msk_txeof(struct msk_if_softc *, int); 250 static int msk_encap(struct msk_if_softc *, struct mbuf **); 251 static void msk_tx_task(void *, int); 252 static void msk_start(struct ifnet *); 253 static int msk_ioctl(struct ifnet *, u_long, caddr_t); 254 static void msk_set_prefetch(struct msk_softc *, int, bus_addr_t, uint32_t); 255 static void msk_set_rambuffer(struct msk_if_softc *); 256 static void msk_init(void *); 257 static void msk_init_locked(struct msk_if_softc *); 258 static void msk_stop(struct msk_if_softc *); 259 static void msk_watchdog(struct msk_if_softc *); 260 static int msk_mediachange(struct ifnet *); 261 static void msk_mediastatus(struct ifnet *, struct ifmediareq *); 262 static void msk_phy_power(struct msk_softc *, int); 263 static void msk_dmamap_cb(void *, bus_dma_segment_t *, int, int); 264 static int msk_status_dma_alloc(struct msk_softc *); 265 static void msk_status_dma_free(struct msk_softc *); 266 static int msk_txrx_dma_alloc(struct msk_if_softc *); 267 static void msk_txrx_dma_free(struct msk_if_softc *); 268 static void *msk_jalloc(struct msk_if_softc *); 269 static void msk_jfree(void *, void *); 270 static int msk_init_rx_ring(struct msk_if_softc *); 271 static int msk_init_jumbo_rx_ring(struct msk_if_softc *); 272 static void msk_init_tx_ring(struct msk_if_softc *); 273 static __inline void msk_discard_rxbuf(struct msk_if_softc *, int); 274 static __inline void msk_discard_jumbo_rxbuf(struct msk_if_softc *, int); 275 static int msk_newbuf(struct msk_if_softc *, int); 276 static int msk_jumbo_newbuf(struct msk_if_softc *, int); 277 278 static int msk_phy_readreg(struct msk_if_softc *, int, int); 279 static int msk_phy_writereg(struct msk_if_softc *, int, int, int); 280 static int msk_miibus_readreg(device_t, int, int); 281 static int msk_miibus_writereg(device_t, int, int, int); 282 static void msk_miibus_statchg(device_t); 283 static void msk_link_task(void *, int); 284 285 static void msk_setmulti(struct msk_if_softc *); 286 static void msk_setvlan(struct msk_if_softc *, struct ifnet *); 287 static void msk_setpromisc(struct msk_if_softc *); 288 289 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int); 290 static int sysctl_hw_msk_proc_limit(SYSCTL_HANDLER_ARGS); 291 292 static device_method_t mskc_methods[] = { 293 /* Device interface */ 294 DEVMETHOD(device_probe, mskc_probe), 295 DEVMETHOD(device_attach, mskc_attach), 296 DEVMETHOD(device_detach, mskc_detach), 297 DEVMETHOD(device_suspend, mskc_suspend), 298 DEVMETHOD(device_resume, mskc_resume), 299 DEVMETHOD(device_shutdown, mskc_shutdown), 300 301 /* bus interface */ 302 DEVMETHOD(bus_print_child, bus_generic_print_child), 303 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 304 305 { NULL, NULL } 306 }; 307 308 static driver_t mskc_driver = { 309 "mskc", 310 mskc_methods, 311 sizeof(struct msk_softc) 312 }; 313 314 static devclass_t mskc_devclass; 315 316 static device_method_t msk_methods[] = { 317 /* Device interface */ 318 DEVMETHOD(device_probe, msk_probe), 319 DEVMETHOD(device_attach, msk_attach), 320 DEVMETHOD(device_detach, msk_detach), 321 DEVMETHOD(device_shutdown, bus_generic_shutdown), 322 323 /* bus interface */ 324 DEVMETHOD(bus_print_child, bus_generic_print_child), 325 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 326 327 /* MII interface */ 328 DEVMETHOD(miibus_readreg, msk_miibus_readreg), 329 DEVMETHOD(miibus_writereg, msk_miibus_writereg), 330 DEVMETHOD(miibus_statchg, msk_miibus_statchg), 331 332 { NULL, NULL } 333 }; 334 335 static driver_t msk_driver = { 336 "msk", 337 msk_methods, 338 sizeof(struct msk_if_softc) 339 }; 340 341 static devclass_t msk_devclass; 342 343 DRIVER_MODULE(mskc, pci, mskc_driver, mskc_devclass, 0, 0); 344 DRIVER_MODULE(msk, mskc, msk_driver, msk_devclass, 0, 0); 345 DRIVER_MODULE(miibus, msk, miibus_driver, miibus_devclass, 0, 0); 346 347 static struct resource_spec msk_res_spec_io[] = { 348 { SYS_RES_IOPORT, PCIR_BAR(1), RF_ACTIVE }, 349 { -1, 0, 0 } 350 }; 351 352 static struct resource_spec msk_res_spec_mem[] = { 353 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 354 { -1, 0, 0 } 355 }; 356 357 static struct resource_spec msk_irq_spec_legacy[] = { 358 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 359 { -1, 0, 0 } 360 }; 361 362 static struct resource_spec msk_irq_spec_msi[] = { 363 { SYS_RES_IRQ, 1, RF_ACTIVE }, 364 { -1, 0, 0 } 365 }; 366 367 static struct resource_spec msk_irq_spec_msi2[] = { 368 { SYS_RES_IRQ, 1, RF_ACTIVE }, 369 { SYS_RES_IRQ, 2, RF_ACTIVE }, 370 { -1, 0, 0 } 371 }; 372 373 static int 374 msk_miibus_readreg(device_t dev, int phy, int reg) 375 { 376 struct msk_if_softc *sc_if; 377 378 if (phy != PHY_ADDR_MARV) 379 return (0); 380 381 sc_if = device_get_softc(dev); 382 383 return (msk_phy_readreg(sc_if, phy, reg)); 384 } 385 386 static int 387 msk_phy_readreg(struct msk_if_softc *sc_if, int phy, int reg) 388 { 389 struct msk_softc *sc; 390 int i, val; 391 392 sc = sc_if->msk_softc; 393 394 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SMI_CTRL, 395 GM_SMI_CT_PHY_AD(phy) | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD); 396 397 for (i = 0; i < MSK_TIMEOUT; i++) { 398 DELAY(1); 399 val = GMAC_READ_2(sc, sc_if->msk_port, GM_SMI_CTRL); 400 if ((val & GM_SMI_CT_RD_VAL) != 0) { 401 val = GMAC_READ_2(sc, sc_if->msk_port, GM_SMI_DATA); 402 break; 403 } 404 } 405 406 if (i == MSK_TIMEOUT) { 407 if_printf(sc_if->msk_ifp, "phy failed to come ready\n"); 408 val = 0; 409 } 410 411 return (val); 412 } 413 414 static int 415 msk_miibus_writereg(device_t dev, int phy, int reg, int val) 416 { 417 struct msk_if_softc *sc_if; 418 419 if (phy != PHY_ADDR_MARV) 420 return (0); 421 422 sc_if = device_get_softc(dev); 423 424 return (msk_phy_writereg(sc_if, phy, reg, val)); 425 } 426 427 static int 428 msk_phy_writereg(struct msk_if_softc *sc_if, int phy, int reg, int val) 429 { 430 struct msk_softc *sc; 431 int i; 432 433 sc = sc_if->msk_softc; 434 435 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SMI_DATA, val); 436 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SMI_CTRL, 437 GM_SMI_CT_PHY_AD(phy) | GM_SMI_CT_REG_AD(reg)); 438 for (i = 0; i < MSK_TIMEOUT; i++) { 439 DELAY(1); 440 if ((GMAC_READ_2(sc, sc_if->msk_port, GM_SMI_CTRL) & 441 GM_SMI_CT_BUSY) == 0) 442 break; 443 } 444 if (i == MSK_TIMEOUT) 445 if_printf(sc_if->msk_ifp, "phy write timeout\n"); 446 447 return (0); 448 } 449 450 static void 451 msk_miibus_statchg(device_t dev) 452 { 453 struct msk_if_softc *sc_if; 454 455 sc_if = device_get_softc(dev); 456 taskqueue_enqueue(taskqueue_swi, &sc_if->msk_link_task); 457 } 458 459 static void 460 msk_link_task(void *arg, int pending) 461 { 462 struct msk_softc *sc; 463 struct msk_if_softc *sc_if; 464 struct mii_data *mii; 465 struct ifnet *ifp; 466 uint32_t gmac; 467 468 sc_if = (struct msk_if_softc *)arg; 469 sc = sc_if->msk_softc; 470 471 MSK_IF_LOCK(sc_if); 472 473 mii = device_get_softc(sc_if->msk_miibus); 474 ifp = sc_if->msk_ifp; 475 if (mii == NULL || ifp == NULL) { 476 MSK_IF_UNLOCK(sc_if); 477 return; 478 } 479 480 if (mii->mii_media_status & IFM_ACTIVE) { 481 if (IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 482 sc_if->msk_link = 1; 483 } else 484 sc_if->msk_link = 0; 485 486 if (sc_if->msk_link != 0) { 487 /* Enable Tx FIFO Underrun. */ 488 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_MSK), 489 GM_IS_TX_FF_UR | GM_IS_RX_FF_OR); 490 /* 491 * Because mii(4) notify msk(4) that it detected link status 492 * change, there is no need to enable automatic 493 * speed/flow-control/duplex updates. 494 */ 495 gmac = GM_GPCR_AU_ALL_DIS; 496 switch (IFM_SUBTYPE(mii->mii_media_active)) { 497 case IFM_1000_SX: 498 case IFM_1000_T: 499 gmac |= GM_GPCR_SPEED_1000; 500 break; 501 case IFM_100_TX: 502 gmac |= GM_GPCR_SPEED_100; 503 break; 504 case IFM_10_T: 505 break; 506 } 507 508 if (((mii->mii_media_active & IFM_GMASK) & IFM_FDX) != 0) 509 gmac |= GM_GPCR_DUP_FULL; 510 /* Disable Rx flow control. */ 511 if (((mii->mii_media_active & IFM_GMASK) & IFM_FLAG0) == 0) 512 gmac |= GM_GPCR_FC_RX_DIS; 513 /* Disable Tx flow control. */ 514 if (((mii->mii_media_active & IFM_GMASK) & IFM_FLAG1) == 0) 515 gmac |= GM_GPCR_FC_TX_DIS; 516 gmac |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA; 517 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, gmac); 518 /* Read again to ensure writing. */ 519 GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL); 520 521 gmac = GMC_PAUSE_ON; 522 if (((mii->mii_media_active & IFM_GMASK) & 523 (IFM_FLAG0 | IFM_FLAG1)) == 0) 524 gmac = GMC_PAUSE_OFF; 525 /* Diable pause for 10/100 Mbps in half-duplex mode. */ 526 if ((((mii->mii_media_active & IFM_GMASK) & IFM_FDX) == 0) && 527 (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX || 528 IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T)) 529 gmac = GMC_PAUSE_OFF; 530 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), gmac); 531 532 /* Enable PHY interrupt for FIFO underrun/overflow. */ 533 msk_phy_writereg(sc_if, PHY_ADDR_MARV, 534 PHY_MARV_INT_MASK, PHY_M_IS_FIFO_ERROR); 535 } else { 536 /* 537 * Link state changed to down. 538 * Disable PHY interrupts. 539 */ 540 msk_phy_writereg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_MASK, 0); 541 /* Disable Rx/Tx MAC. */ 542 gmac = GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL); 543 gmac &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA); 544 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, gmac); 545 /* Read again to ensure writing. */ 546 GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL); 547 } 548 549 MSK_IF_UNLOCK(sc_if); 550 } 551 552 static void 553 msk_setmulti(struct msk_if_softc *sc_if) 554 { 555 struct msk_softc *sc; 556 struct ifnet *ifp; 557 struct ifmultiaddr *ifma; 558 uint32_t mchash[2]; 559 uint32_t crc; 560 uint16_t mode; 561 562 sc = sc_if->msk_softc; 563 564 MSK_IF_LOCK_ASSERT(sc_if); 565 566 ifp = sc_if->msk_ifp; 567 568 bzero(mchash, sizeof(mchash)); 569 mode = GMAC_READ_2(sc, sc_if->msk_port, GM_RX_CTRL); 570 mode |= GM_RXCR_UCF_ENA; 571 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 572 if ((ifp->if_flags & IFF_PROMISC) != 0) 573 mode &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA); 574 else if ((ifp->if_flags & IFF_ALLMULTI) != 0) { 575 mchash[0] = 0xffff; 576 mchash[1] = 0xffff; 577 } 578 } else { 579 IF_ADDR_LOCK(ifp); 580 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 581 if (ifma->ifma_addr->sa_family != AF_LINK) 582 continue; 583 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *) 584 ifma->ifma_addr), ETHER_ADDR_LEN); 585 /* Just want the 6 least significant bits. */ 586 crc &= 0x3f; 587 /* Set the corresponding bit in the hash table. */ 588 mchash[crc >> 5] |= 1 << (crc & 0x1f); 589 } 590 IF_ADDR_UNLOCK(ifp); 591 mode |= GM_RXCR_MCF_ENA; 592 } 593 594 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H1, 595 mchash[0] & 0xffff); 596 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H2, 597 (mchash[0] >> 16) & 0xffff); 598 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H3, 599 mchash[1] & 0xffff); 600 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H4, 601 (mchash[1] >> 16) & 0xffff); 602 GMAC_WRITE_2(sc, sc_if->msk_port, GM_RX_CTRL, mode); 603 } 604 605 static void 606 msk_setvlan(struct msk_if_softc *sc_if, struct ifnet *ifp) 607 { 608 struct msk_softc *sc; 609 610 sc = sc_if->msk_softc; 611 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) { 612 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), 613 RX_VLAN_STRIP_ON); 614 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 615 TX_VLAN_TAG_ON); 616 } else { 617 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), 618 RX_VLAN_STRIP_OFF); 619 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 620 TX_VLAN_TAG_OFF); 621 } 622 } 623 624 static void 625 msk_setpromisc(struct msk_if_softc *sc_if) 626 { 627 struct msk_softc *sc; 628 struct ifnet *ifp; 629 uint16_t mode; 630 631 MSK_IF_LOCK_ASSERT(sc_if); 632 633 sc = sc_if->msk_softc; 634 ifp = sc_if->msk_ifp; 635 636 mode = GMAC_READ_2(sc, sc_if->msk_port, GM_RX_CTRL); 637 if (ifp->if_flags & IFF_PROMISC) 638 mode &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA); 639 else 640 mode |= (GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA); 641 GMAC_WRITE_2(sc, sc_if->msk_port, GM_RX_CTRL, mode); 642 } 643 644 static int 645 msk_init_rx_ring(struct msk_if_softc *sc_if) 646 { 647 struct msk_ring_data *rd; 648 struct msk_rxdesc *rxd; 649 int i, prod; 650 651 MSK_IF_LOCK_ASSERT(sc_if); 652 653 sc_if->msk_cdata.msk_rx_cons = 0; 654 sc_if->msk_cdata.msk_rx_prod = 0; 655 sc_if->msk_cdata.msk_rx_putwm = MSK_PUT_WM; 656 657 rd = &sc_if->msk_rdata; 658 bzero(rd->msk_rx_ring, sizeof(struct msk_rx_desc) * MSK_RX_RING_CNT); 659 prod = sc_if->msk_cdata.msk_rx_prod; 660 for (i = 0; i < MSK_RX_RING_CNT; i++) { 661 rxd = &sc_if->msk_cdata.msk_rxdesc[prod]; 662 rxd->rx_m = NULL; 663 rxd->rx_le = &rd->msk_rx_ring[prod]; 664 if (msk_newbuf(sc_if, prod) != 0) 665 return (ENOBUFS); 666 MSK_INC(prod, MSK_RX_RING_CNT); 667 } 668 669 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_ring_tag, 670 sc_if->msk_cdata.msk_rx_ring_map, 671 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 672 673 /* Update prefetch unit. */ 674 sc_if->msk_cdata.msk_rx_prod = MSK_RX_RING_CNT - 1; 675 CSR_WRITE_2(sc_if->msk_softc, 676 Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_PUT_IDX_REG), 677 sc_if->msk_cdata.msk_rx_prod); 678 679 return (0); 680 } 681 682 static int 683 msk_init_jumbo_rx_ring(struct msk_if_softc *sc_if) 684 { 685 struct msk_ring_data *rd; 686 struct msk_rxdesc *rxd; 687 int i, prod; 688 689 MSK_IF_LOCK_ASSERT(sc_if); 690 691 sc_if->msk_cdata.msk_rx_cons = 0; 692 sc_if->msk_cdata.msk_rx_prod = 0; 693 sc_if->msk_cdata.msk_rx_putwm = MSK_PUT_WM; 694 695 rd = &sc_if->msk_rdata; 696 bzero(rd->msk_jumbo_rx_ring, 697 sizeof(struct msk_rx_desc) * MSK_JUMBO_RX_RING_CNT); 698 prod = sc_if->msk_cdata.msk_rx_prod; 699 for (i = 0; i < MSK_JUMBO_RX_RING_CNT; i++) { 700 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[prod]; 701 rxd->rx_m = NULL; 702 rxd->rx_le = &rd->msk_jumbo_rx_ring[prod]; 703 if (msk_jumbo_newbuf(sc_if, prod) != 0) 704 return (ENOBUFS); 705 MSK_INC(prod, MSK_JUMBO_RX_RING_CNT); 706 } 707 708 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 709 sc_if->msk_cdata.msk_jumbo_rx_ring_map, 710 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 711 712 sc_if->msk_cdata.msk_rx_prod = MSK_JUMBO_RX_RING_CNT - 1; 713 CSR_WRITE_2(sc_if->msk_softc, 714 Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_PUT_IDX_REG), 715 sc_if->msk_cdata.msk_rx_prod); 716 717 return (0); 718 } 719 720 static void 721 msk_init_tx_ring(struct msk_if_softc *sc_if) 722 { 723 struct msk_ring_data *rd; 724 struct msk_txdesc *txd; 725 int i; 726 727 sc_if->msk_cdata.msk_tso_mtu = 0; 728 sc_if->msk_cdata.msk_tx_prod = 0; 729 sc_if->msk_cdata.msk_tx_cons = 0; 730 sc_if->msk_cdata.msk_tx_cnt = 0; 731 732 rd = &sc_if->msk_rdata; 733 bzero(rd->msk_tx_ring, sizeof(struct msk_tx_desc) * MSK_TX_RING_CNT); 734 for (i = 0; i < MSK_TX_RING_CNT; i++) { 735 txd = &sc_if->msk_cdata.msk_txdesc[i]; 736 txd->tx_m = NULL; 737 txd->tx_le = &rd->msk_tx_ring[i]; 738 } 739 740 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_ring_tag, 741 sc_if->msk_cdata.msk_tx_ring_map, 742 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 743 } 744 745 static __inline void 746 msk_discard_rxbuf(struct msk_if_softc *sc_if, int idx) 747 { 748 struct msk_rx_desc *rx_le; 749 struct msk_rxdesc *rxd; 750 struct mbuf *m; 751 752 rxd = &sc_if->msk_cdata.msk_rxdesc[idx]; 753 m = rxd->rx_m; 754 rx_le = rxd->rx_le; 755 rx_le->msk_control = htole32(m->m_len | OP_PACKET | HW_OWNER); 756 } 757 758 static __inline void 759 msk_discard_jumbo_rxbuf(struct msk_if_softc *sc_if, int idx) 760 { 761 struct msk_rx_desc *rx_le; 762 struct msk_rxdesc *rxd; 763 struct mbuf *m; 764 765 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[idx]; 766 m = rxd->rx_m; 767 rx_le = rxd->rx_le; 768 rx_le->msk_control = htole32(m->m_len | OP_PACKET | HW_OWNER); 769 } 770 771 static int 772 msk_newbuf(struct msk_if_softc *sc_if, int idx) 773 { 774 struct msk_rx_desc *rx_le; 775 struct msk_rxdesc *rxd; 776 struct mbuf *m; 777 bus_dma_segment_t segs[1]; 778 bus_dmamap_t map; 779 int nsegs; 780 781 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 782 if (m == NULL) 783 return (ENOBUFS); 784 785 m->m_len = m->m_pkthdr.len = MCLBYTES; 786 m_adj(m, ETHER_ALIGN); 787 788 if (bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_rx_tag, 789 sc_if->msk_cdata.msk_rx_sparemap, m, segs, &nsegs, 790 BUS_DMA_NOWAIT) != 0) { 791 m_freem(m); 792 return (ENOBUFS); 793 } 794 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 795 796 rxd = &sc_if->msk_cdata.msk_rxdesc[idx]; 797 if (rxd->rx_m != NULL) { 798 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_tag, rxd->rx_dmamap, 799 BUS_DMASYNC_POSTREAD); 800 bus_dmamap_unload(sc_if->msk_cdata.msk_rx_tag, rxd->rx_dmamap); 801 } 802 map = rxd->rx_dmamap; 803 rxd->rx_dmamap = sc_if->msk_cdata.msk_rx_sparemap; 804 sc_if->msk_cdata.msk_rx_sparemap = map; 805 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_tag, rxd->rx_dmamap, 806 BUS_DMASYNC_PREREAD); 807 rxd->rx_m = m; 808 rx_le = rxd->rx_le; 809 rx_le->msk_addr = htole32(MSK_ADDR_LO(segs[0].ds_addr)); 810 rx_le->msk_control = 811 htole32(segs[0].ds_len | OP_PACKET | HW_OWNER); 812 813 return (0); 814 } 815 816 static int 817 msk_jumbo_newbuf(struct msk_if_softc *sc_if, int idx) 818 { 819 struct msk_rx_desc *rx_le; 820 struct msk_rxdesc *rxd; 821 struct mbuf *m; 822 bus_dma_segment_t segs[1]; 823 bus_dmamap_t map; 824 int nsegs; 825 void *buf; 826 827 MGETHDR(m, M_DONTWAIT, MT_DATA); 828 if (m == NULL) 829 return (ENOBUFS); 830 buf = msk_jalloc(sc_if); 831 if (buf == NULL) { 832 m_freem(m); 833 return (ENOBUFS); 834 } 835 /* Attach the buffer to the mbuf. */ 836 MEXTADD(m, buf, MSK_JLEN, msk_jfree, buf, 837 (struct msk_if_softc *)sc_if, 0, EXT_NET_DRV); 838 if ((m->m_flags & M_EXT) == 0) { 839 m_freem(m); 840 return (ENOBUFS); 841 } 842 m->m_pkthdr.len = m->m_len = MSK_JLEN; 843 m_adj(m, ETHER_ALIGN); 844 845 if (bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_jumbo_rx_tag, 846 sc_if->msk_cdata.msk_jumbo_rx_sparemap, m, segs, &nsegs, 847 BUS_DMA_NOWAIT) != 0) { 848 m_freem(m); 849 return (ENOBUFS); 850 } 851 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 852 853 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[idx]; 854 if (rxd->rx_m != NULL) { 855 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_tag, 856 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 857 bus_dmamap_unload(sc_if->msk_cdata.msk_jumbo_rx_tag, 858 rxd->rx_dmamap); 859 } 860 map = rxd->rx_dmamap; 861 rxd->rx_dmamap = sc_if->msk_cdata.msk_jumbo_rx_sparemap; 862 sc_if->msk_cdata.msk_jumbo_rx_sparemap = map; 863 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_tag, rxd->rx_dmamap, 864 BUS_DMASYNC_PREREAD); 865 rxd->rx_m = m; 866 rx_le = rxd->rx_le; 867 rx_le->msk_addr = htole32(MSK_ADDR_LO(segs[0].ds_addr)); 868 rx_le->msk_control = 869 htole32(segs[0].ds_len | OP_PACKET | HW_OWNER); 870 871 return (0); 872 } 873 874 /* 875 * Set media options. 876 */ 877 static int 878 msk_mediachange(struct ifnet *ifp) 879 { 880 struct msk_if_softc *sc_if; 881 struct mii_data *mii; 882 883 sc_if = ifp->if_softc; 884 885 MSK_IF_LOCK(sc_if); 886 mii = device_get_softc(sc_if->msk_miibus); 887 mii_mediachg(mii); 888 MSK_IF_UNLOCK(sc_if); 889 890 return (0); 891 } 892 893 /* 894 * Report current media status. 895 */ 896 static void 897 msk_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 898 { 899 struct msk_if_softc *sc_if; 900 struct mii_data *mii; 901 902 sc_if = ifp->if_softc; 903 MSK_IF_LOCK(sc_if); 904 mii = device_get_softc(sc_if->msk_miibus); 905 906 mii_pollstat(mii); 907 MSK_IF_UNLOCK(sc_if); 908 ifmr->ifm_active = mii->mii_media_active; 909 ifmr->ifm_status = mii->mii_media_status; 910 } 911 912 static int 913 msk_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 914 { 915 struct msk_if_softc *sc_if; 916 struct ifreq *ifr; 917 struct mii_data *mii; 918 int error, mask; 919 920 sc_if = ifp->if_softc; 921 ifr = (struct ifreq *)data; 922 error = 0; 923 924 switch(command) { 925 case SIOCSIFMTU: 926 if (ifr->ifr_mtu > MSK_JUMBO_MTU || ifr->ifr_mtu < ETHERMIN) { 927 error = EINVAL; 928 break; 929 } 930 if (sc_if->msk_softc->msk_hw_id == CHIP_ID_YUKON_FE && 931 ifr->ifr_mtu > MSK_MAX_FRAMELEN) { 932 error = EINVAL; 933 break; 934 } 935 MSK_IF_LOCK(sc_if); 936 ifp->if_mtu = ifr->ifr_mtu; 937 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 938 msk_init_locked(sc_if); 939 MSK_IF_UNLOCK(sc_if); 940 break; 941 case SIOCSIFFLAGS: 942 MSK_IF_LOCK(sc_if); 943 if ((ifp->if_flags & IFF_UP) != 0) { 944 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 945 if (((ifp->if_flags ^ sc_if->msk_if_flags) 946 & IFF_PROMISC) != 0) { 947 msk_setpromisc(sc_if); 948 msk_setmulti(sc_if); 949 } 950 } else { 951 if (sc_if->msk_detach == 0) 952 msk_init_locked(sc_if); 953 } 954 } else { 955 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 956 msk_stop(sc_if); 957 } 958 sc_if->msk_if_flags = ifp->if_flags; 959 MSK_IF_UNLOCK(sc_if); 960 break; 961 case SIOCADDMULTI: 962 case SIOCDELMULTI: 963 MSK_IF_LOCK(sc_if); 964 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 965 msk_setmulti(sc_if); 966 MSK_IF_UNLOCK(sc_if); 967 break; 968 case SIOCGIFMEDIA: 969 case SIOCSIFMEDIA: 970 mii = device_get_softc(sc_if->msk_miibus); 971 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 972 break; 973 case SIOCSIFCAP: 974 MSK_IF_LOCK(sc_if); 975 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 976 if ((mask & IFCAP_TXCSUM) != 0) { 977 ifp->if_capenable ^= IFCAP_TXCSUM; 978 if ((IFCAP_TXCSUM & ifp->if_capenable) != 0 && 979 (IFCAP_TXCSUM & ifp->if_capabilities) != 0) 980 ifp->if_hwassist |= MSK_CSUM_FEATURES; 981 else 982 ifp->if_hwassist &= ~MSK_CSUM_FEATURES; 983 } 984 if ((mask & IFCAP_VLAN_HWTAGGING) != 0) { 985 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 986 msk_setvlan(sc_if, ifp); 987 } 988 989 if ((mask & IFCAP_TSO4) != 0) { 990 ifp->if_capenable ^= IFCAP_TSO4; 991 if ((IFCAP_TSO4 & ifp->if_capenable) != 0 && 992 (IFCAP_TSO4 & ifp->if_capabilities) != 0) 993 ifp->if_hwassist |= CSUM_TSO; 994 else 995 ifp->if_hwassist &= ~CSUM_TSO; 996 } 997 if (sc_if->msk_framesize > MSK_MAX_FRAMELEN && 998 sc_if->msk_softc->msk_hw_id == CHIP_ID_YUKON_EC_U) { 999 /* 1000 * In Yukon EC Ultra, TSO & checksum offload is not 1001 * supported for jumbo frame. 1002 */ 1003 ifp->if_hwassist &= ~(MSK_CSUM_FEATURES | CSUM_TSO); 1004 ifp->if_capenable &= ~(IFCAP_TSO4 | IFCAP_TXCSUM); 1005 } 1006 1007 VLAN_CAPABILITIES(ifp); 1008 MSK_IF_UNLOCK(sc_if); 1009 break; 1010 default: 1011 error = ether_ioctl(ifp, command, data); 1012 break; 1013 } 1014 1015 return (error); 1016 } 1017 1018 static int 1019 mskc_probe(device_t dev) 1020 { 1021 struct msk_product *mp; 1022 uint16_t vendor, devid; 1023 int i; 1024 1025 vendor = pci_get_vendor(dev); 1026 devid = pci_get_device(dev); 1027 mp = msk_products; 1028 for (i = 0; i < sizeof(msk_products)/sizeof(msk_products[0]); 1029 i++, mp++) { 1030 if (vendor == mp->msk_vendorid && devid == mp->msk_deviceid) { 1031 device_set_desc(dev, mp->msk_name); 1032 return (BUS_PROBE_DEFAULT); 1033 } 1034 } 1035 1036 return (ENXIO); 1037 } 1038 1039 static int 1040 mskc_setup_rambuffer(struct msk_softc *sc) 1041 { 1042 int next; 1043 int i; 1044 uint8_t val; 1045 1046 /* Get adapter SRAM size. */ 1047 val = CSR_READ_1(sc, B2_E_0); 1048 sc->msk_ramsize = (val == 0) ? 128 : val * 4; 1049 if (bootverbose) 1050 device_printf(sc->msk_dev, 1051 "RAM buffer size : %dKB\n", sc->msk_ramsize); 1052 /* 1053 * Give receiver 2/3 of memory and round down to the multiple 1054 * of 1024. Tx/Rx RAM buffer size of Yukon II shoud be multiple 1055 * of 1024. 1056 */ 1057 sc->msk_rxqsize = rounddown((sc->msk_ramsize * 1024 * 2) / 3, 1024); 1058 sc->msk_txqsize = (sc->msk_ramsize * 1024) - sc->msk_rxqsize; 1059 for (i = 0, next = 0; i < sc->msk_num_port; i++) { 1060 sc->msk_rxqstart[i] = next; 1061 sc->msk_rxqend[i] = next + sc->msk_rxqsize - 1; 1062 next = sc->msk_rxqend[i] + 1; 1063 sc->msk_txqstart[i] = next; 1064 sc->msk_txqend[i] = next + sc->msk_txqsize - 1; 1065 next = sc->msk_txqend[i] + 1; 1066 if (bootverbose) { 1067 device_printf(sc->msk_dev, 1068 "Port %d : Rx Queue %dKB(0x%08x:0x%08x)\n", i, 1069 sc->msk_rxqsize / 1024, sc->msk_rxqstart[i], 1070 sc->msk_rxqend[i]); 1071 device_printf(sc->msk_dev, 1072 "Port %d : Tx Queue %dKB(0x%08x:0x%08x)\n", i, 1073 sc->msk_txqsize / 1024, sc->msk_txqstart[i], 1074 sc->msk_txqend[i]); 1075 } 1076 } 1077 1078 return (0); 1079 } 1080 1081 static void 1082 msk_phy_power(struct msk_softc *sc, int mode) 1083 { 1084 uint32_t val; 1085 int i; 1086 1087 switch (mode) { 1088 case MSK_PHY_POWERUP: 1089 /* Switch power to VCC (WA for VAUX problem). */ 1090 CSR_WRITE_1(sc, B0_POWER_CTRL, 1091 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON); 1092 /* Disable Core Clock Division, set Clock Select to 0. */ 1093 CSR_WRITE_4(sc, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS); 1094 1095 val = 0; 1096 if (sc->msk_hw_id == CHIP_ID_YUKON_XL && 1097 sc->msk_hw_rev > CHIP_REV_YU_XL_A1) { 1098 /* Enable bits are inverted. */ 1099 val = Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS | 1100 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS | 1101 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS; 1102 } 1103 /* 1104 * Enable PCI & Core Clock, enable clock gating for both Links. 1105 */ 1106 CSR_WRITE_1(sc, B2_Y2_CLK_GATE, val); 1107 1108 val = pci_read_config(sc->msk_dev, PCI_OUR_REG_1, 4); 1109 val &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD); 1110 if (sc->msk_hw_id == CHIP_ID_YUKON_XL && 1111 sc->msk_hw_rev > CHIP_REV_YU_XL_A1) { 1112 /* Deassert Low Power for 1st PHY. */ 1113 val |= PCI_Y2_PHY1_COMA; 1114 if (sc->msk_num_port > 1) 1115 val |= PCI_Y2_PHY2_COMA; 1116 } else if (sc->msk_hw_id == CHIP_ID_YUKON_EC_U) { 1117 uint32_t our; 1118 1119 CSR_WRITE_2(sc, B0_CTST, Y2_HW_WOL_ON); 1120 1121 /* Enable all clocks. */ 1122 pci_write_config(sc->msk_dev, PCI_OUR_REG_3, 0, 4); 1123 our = pci_read_config(sc->msk_dev, PCI_OUR_REG_4, 4); 1124 our &= (PCI_FORCE_ASPM_REQUEST|PCI_ASPM_GPHY_LINK_DOWN| 1125 PCI_ASPM_INT_FIFO_EMPTY|PCI_ASPM_CLKRUN_REQUEST); 1126 /* Set all bits to 0 except bits 15..12. */ 1127 pci_write_config(sc->msk_dev, PCI_OUR_REG_4, our, 4); 1128 /* Set to default value. */ 1129 pci_write_config(sc->msk_dev, PCI_OUR_REG_5, 0, 4); 1130 } 1131 /* Release PHY from PowerDown/COMA mode. */ 1132 pci_write_config(sc->msk_dev, PCI_OUR_REG_1, val, 4); 1133 for (i = 0; i < sc->msk_num_port; i++) { 1134 CSR_WRITE_2(sc, MR_ADDR(i, GMAC_LINK_CTRL), 1135 GMLC_RST_SET); 1136 CSR_WRITE_2(sc, MR_ADDR(i, GMAC_LINK_CTRL), 1137 GMLC_RST_CLR); 1138 } 1139 break; 1140 case MSK_PHY_POWERDOWN: 1141 val = pci_read_config(sc->msk_dev, PCI_OUR_REG_1, 4); 1142 val |= PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD; 1143 if (sc->msk_hw_id == CHIP_ID_YUKON_XL && 1144 sc->msk_hw_rev > CHIP_REV_YU_XL_A1) { 1145 val &= ~PCI_Y2_PHY1_COMA; 1146 if (sc->msk_num_port > 1) 1147 val &= ~PCI_Y2_PHY2_COMA; 1148 } 1149 pci_write_config(sc->msk_dev, PCI_OUR_REG_1, val, 4); 1150 1151 val = Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS | 1152 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS | 1153 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS; 1154 if (sc->msk_hw_id == CHIP_ID_YUKON_XL && 1155 sc->msk_hw_rev > CHIP_REV_YU_XL_A1) { 1156 /* Enable bits are inverted. */ 1157 val = 0; 1158 } 1159 /* 1160 * Disable PCI & Core Clock, disable clock gating for 1161 * both Links. 1162 */ 1163 CSR_WRITE_1(sc, B2_Y2_CLK_GATE, val); 1164 CSR_WRITE_1(sc, B0_POWER_CTRL, 1165 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_ON | PC_VCC_OFF); 1166 break; 1167 default: 1168 break; 1169 } 1170 } 1171 1172 static void 1173 mskc_reset(struct msk_softc *sc) 1174 { 1175 bus_addr_t addr; 1176 uint16_t status; 1177 uint32_t val; 1178 int i; 1179 1180 CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR); 1181 1182 /* Disable ASF. */ 1183 if (sc->msk_hw_id < CHIP_ID_YUKON_XL) { 1184 CSR_WRITE_4(sc, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET); 1185 CSR_WRITE_2(sc, B0_CTST, Y2_ASF_DISABLE); 1186 } 1187 /* 1188 * Since we disabled ASF, S/W reset is required for Power Management. 1189 */ 1190 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); 1191 CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR); 1192 1193 /* Clear all error bits in the PCI status register. */ 1194 status = pci_read_config(sc->msk_dev, PCIR_STATUS, 2); 1195 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON); 1196 1197 pci_write_config(sc->msk_dev, PCIR_STATUS, status | 1198 PCIM_STATUS_PERR | PCIM_STATUS_SERR | PCIM_STATUS_RMABORT | 1199 PCIM_STATUS_RTABORT | PCIM_STATUS_PERRREPORT, 2); 1200 CSR_WRITE_2(sc, B0_CTST, CS_MRST_CLR); 1201 1202 switch (sc->msk_bustype) { 1203 case MSK_PEX_BUS: 1204 /* Clear all PEX errors. */ 1205 CSR_PCI_WRITE_4(sc, PEX_UNC_ERR_STAT, 0xffffffff); 1206 val = CSR_PCI_READ_4(sc, PEX_UNC_ERR_STAT); 1207 if ((val & PEX_RX_OV) != 0) { 1208 sc->msk_intrmask &= ~Y2_IS_HW_ERR; 1209 sc->msk_intrhwemask &= ~Y2_IS_PCI_EXP; 1210 } 1211 break; 1212 case MSK_PCI_BUS: 1213 case MSK_PCIX_BUS: 1214 /* Set Cache Line Size to 2(8bytes) if configured to 0. */ 1215 val = pci_read_config(sc->msk_dev, PCIR_CACHELNSZ, 1); 1216 if (val == 0) 1217 pci_write_config(sc->msk_dev, PCIR_CACHELNSZ, 2, 1); 1218 if (sc->msk_bustype == MSK_PCIX_BUS) { 1219 /* Set Cache Line Size opt. */ 1220 val = pci_read_config(sc->msk_dev, PCI_OUR_REG_1, 4); 1221 val |= PCI_CLS_OPT; 1222 pci_write_config(sc->msk_dev, PCI_OUR_REG_1, val, 4); 1223 } 1224 break; 1225 } 1226 /* Set PHY power state. */ 1227 msk_phy_power(sc, MSK_PHY_POWERUP); 1228 1229 /* Reset GPHY/GMAC Control */ 1230 for (i = 0; i < sc->msk_num_port; i++) { 1231 /* GPHY Control reset. */ 1232 CSR_WRITE_4(sc, MR_ADDR(i, GPHY_CTRL), GPC_RST_SET); 1233 CSR_WRITE_4(sc, MR_ADDR(i, GPHY_CTRL), GPC_RST_CLR); 1234 /* GMAC Control reset. */ 1235 CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), GMC_RST_SET); 1236 CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), GMC_RST_CLR); 1237 CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), GMC_F_LOOPB_OFF); 1238 } 1239 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 1240 1241 /* LED On. */ 1242 CSR_WRITE_2(sc, B0_CTST, Y2_LED_STAT_ON); 1243 1244 /* Clear TWSI IRQ. */ 1245 CSR_WRITE_4(sc, B2_I2C_IRQ, I2C_CLR_IRQ); 1246 1247 /* Turn off hardware timer. */ 1248 CSR_WRITE_1(sc, B2_TI_CTRL, TIM_STOP); 1249 CSR_WRITE_1(sc, B2_TI_CTRL, TIM_CLR_IRQ); 1250 1251 /* Turn off descriptor polling. */ 1252 CSR_WRITE_1(sc, B28_DPT_CTRL, DPT_STOP); 1253 1254 /* Turn off time stamps. */ 1255 CSR_WRITE_1(sc, GMAC_TI_ST_CTRL, GMT_ST_STOP); 1256 CSR_WRITE_1(sc, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ); 1257 1258 /* Configure timeout values. */ 1259 for (i = 0; i < sc->msk_num_port; i++) { 1260 CSR_WRITE_2(sc, SELECT_RAM_BUFFER(i, B3_RI_CTRL), RI_RST_SET); 1261 CSR_WRITE_2(sc, SELECT_RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR); 1262 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_R1), 1263 MSK_RI_TO_53); 1264 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XA1), 1265 MSK_RI_TO_53); 1266 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XS1), 1267 MSK_RI_TO_53); 1268 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_R1), 1269 MSK_RI_TO_53); 1270 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XA1), 1271 MSK_RI_TO_53); 1272 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XS1), 1273 MSK_RI_TO_53); 1274 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_R2), 1275 MSK_RI_TO_53); 1276 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XA2), 1277 MSK_RI_TO_53); 1278 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XS2), 1279 MSK_RI_TO_53); 1280 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_R2), 1281 MSK_RI_TO_53); 1282 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XA2), 1283 MSK_RI_TO_53); 1284 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XS2), 1285 MSK_RI_TO_53); 1286 } 1287 1288 /* Disable all interrupts. */ 1289 CSR_WRITE_4(sc, B0_HWE_IMSK, 0); 1290 CSR_READ_4(sc, B0_HWE_IMSK); 1291 CSR_WRITE_4(sc, B0_IMSK, 0); 1292 CSR_READ_4(sc, B0_IMSK); 1293 1294 /* 1295 * On dual port PCI-X card, there is an problem where status 1296 * can be received out of order due to split transactions. 1297 */ 1298 if (sc->msk_bustype == MSK_PCIX_BUS && sc->msk_num_port > 1) { 1299 int pcix; 1300 uint16_t pcix_cmd; 1301 1302 if (pci_find_extcap(sc->msk_dev, PCIY_PCIX, &pcix) == 0) { 1303 pcix_cmd = pci_read_config(sc->msk_dev, pcix + 2, 2); 1304 /* Clear Max Outstanding Split Transactions. */ 1305 pcix_cmd &= ~0x70; 1306 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON); 1307 pci_write_config(sc->msk_dev, pcix + 2, pcix_cmd, 2); 1308 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 1309 } 1310 } 1311 if (sc->msk_bustype == MSK_PEX_BUS) { 1312 uint16_t v, width; 1313 1314 v = pci_read_config(sc->msk_dev, PEX_DEV_CTRL, 2); 1315 /* Change Max. Read Request Size to 4096 bytes. */ 1316 v &= ~PEX_DC_MAX_RRS_MSK; 1317 v |= PEX_DC_MAX_RD_RQ_SIZE(5); 1318 pci_write_config(sc->msk_dev, PEX_DEV_CTRL, v, 2); 1319 width = pci_read_config(sc->msk_dev, PEX_LNK_STAT, 2); 1320 width = (width & PEX_LS_LINK_WI_MSK) >> 4; 1321 v = pci_read_config(sc->msk_dev, PEX_LNK_CAP, 2); 1322 v = (v & PEX_LS_LINK_WI_MSK) >> 4; 1323 if (v != width) 1324 device_printf(sc->msk_dev, 1325 "negotiated width of link(x%d) != " 1326 "max. width of link(x%d)\n", width, v); 1327 } 1328 1329 /* Clear status list. */ 1330 bzero(sc->msk_stat_ring, 1331 sizeof(struct msk_stat_desc) * MSK_STAT_RING_CNT); 1332 sc->msk_stat_cons = 0; 1333 bus_dmamap_sync(sc->msk_stat_tag, sc->msk_stat_map, 1334 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1335 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_RST_SET); 1336 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_RST_CLR); 1337 /* Set the status list base address. */ 1338 addr = sc->msk_stat_ring_paddr; 1339 CSR_WRITE_4(sc, STAT_LIST_ADDR_LO, MSK_ADDR_LO(addr)); 1340 CSR_WRITE_4(sc, STAT_LIST_ADDR_HI, MSK_ADDR_HI(addr)); 1341 /* Set the status list last index. */ 1342 CSR_WRITE_2(sc, STAT_LAST_IDX, MSK_STAT_RING_CNT - 1); 1343 if (sc->msk_hw_id == CHIP_ID_YUKON_EC && 1344 sc->msk_hw_rev == CHIP_REV_YU_EC_A1) { 1345 /* WA for dev. #4.3 */ 1346 CSR_WRITE_2(sc, STAT_TX_IDX_TH, ST_TXTH_IDX_MASK); 1347 /* WA for dev. #4.18 */ 1348 CSR_WRITE_1(sc, STAT_FIFO_WM, 0x21); 1349 CSR_WRITE_1(sc, STAT_FIFO_ISR_WM, 0x07); 1350 } else { 1351 CSR_WRITE_2(sc, STAT_TX_IDX_TH, 0x0a); 1352 CSR_WRITE_1(sc, STAT_FIFO_WM, 0x10); 1353 if (sc->msk_hw_id == CHIP_ID_YUKON_XL && 1354 sc->msk_hw_rev == CHIP_REV_YU_XL_A0) 1355 CSR_WRITE_1(sc, STAT_FIFO_ISR_WM, 0x04); 1356 else 1357 CSR_WRITE_1(sc, STAT_FIFO_ISR_WM, 0x10); 1358 CSR_WRITE_4(sc, STAT_ISR_TIMER_INI, 0x0190); 1359 } 1360 /* 1361 * Use default value for STAT_ISR_TIMER_INI, STAT_LEV_TIMER_INI. 1362 */ 1363 CSR_WRITE_4(sc, STAT_TX_TIMER_INI, MSK_USECS(sc, 1000)); 1364 1365 /* Enable status unit. */ 1366 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_OP_ON); 1367 1368 CSR_WRITE_1(sc, STAT_TX_TIMER_CTRL, TIM_START); 1369 CSR_WRITE_1(sc, STAT_LEV_TIMER_CTRL, TIM_START); 1370 CSR_WRITE_1(sc, STAT_ISR_TIMER_CTRL, TIM_START); 1371 } 1372 1373 static int 1374 msk_probe(device_t dev) 1375 { 1376 struct msk_softc *sc; 1377 char desc[100]; 1378 1379 sc = device_get_softc(device_get_parent(dev)); 1380 /* 1381 * Not much to do here. We always know there will be 1382 * at least one GMAC present, and if there are two, 1383 * mskc_attach() will create a second device instance 1384 * for us. 1385 */ 1386 snprintf(desc, sizeof(desc), 1387 "Marvell Technology Group Ltd. %s Id 0x%02x Rev 0x%02x", 1388 model_name[sc->msk_hw_id - CHIP_ID_YUKON_XL], sc->msk_hw_id, 1389 sc->msk_hw_rev); 1390 device_set_desc_copy(dev, desc); 1391 1392 return (BUS_PROBE_DEFAULT); 1393 } 1394 1395 static int 1396 msk_attach(device_t dev) 1397 { 1398 struct msk_softc *sc; 1399 struct msk_if_softc *sc_if; 1400 struct ifnet *ifp; 1401 int i, port, error; 1402 uint8_t eaddr[6]; 1403 1404 if (dev == NULL) 1405 return (EINVAL); 1406 1407 error = 0; 1408 sc_if = device_get_softc(dev); 1409 sc = device_get_softc(device_get_parent(dev)); 1410 port = *(int *)device_get_ivars(dev); 1411 1412 sc_if->msk_if_dev = dev; 1413 sc_if->msk_port = port; 1414 sc_if->msk_softc = sc; 1415 sc->msk_if[port] = sc_if; 1416 /* Setup Tx/Rx queue register offsets. */ 1417 if (port == MSK_PORT_A) { 1418 sc_if->msk_txq = Q_XA1; 1419 sc_if->msk_txsq = Q_XS1; 1420 sc_if->msk_rxq = Q_R1; 1421 } else { 1422 sc_if->msk_txq = Q_XA2; 1423 sc_if->msk_txsq = Q_XS2; 1424 sc_if->msk_rxq = Q_R2; 1425 } 1426 1427 callout_init_mtx(&sc_if->msk_tick_ch, &sc_if->msk_softc->msk_mtx, 0); 1428 TASK_INIT(&sc_if->msk_link_task, 0, msk_link_task, sc_if); 1429 1430 if ((error = msk_txrx_dma_alloc(sc_if) != 0)) 1431 goto fail; 1432 1433 ifp = sc_if->msk_ifp = if_alloc(IFT_ETHER); 1434 if (ifp == NULL) { 1435 device_printf(sc_if->msk_if_dev, "can not if_alloc()\n"); 1436 error = ENOSPC; 1437 goto fail; 1438 } 1439 ifp->if_softc = sc_if; 1440 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1441 ifp->if_mtu = ETHERMTU; 1442 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1443 /* 1444 * IFCAP_RXCSUM capability is intentionally disabled as the hardware 1445 * has serious bug in Rx checksum offload for all Yukon II family 1446 * hardware. It seems there is a workaround to make it work somtimes. 1447 * However, the workaround also have to check OP code sequences to 1448 * verify whether the OP code is correct. Sometimes it should compute 1449 * IP/TCP/UDP checksum in driver in order to verify correctness of 1450 * checksum computed by hardware. If you have to compute checksum 1451 * with software to verify the hardware's checksum why have hardware 1452 * compute the checksum? I think there is no reason to spend time to 1453 * make Rx checksum offload work on Yukon II hardware. 1454 */ 1455 ifp->if_capabilities = IFCAP_TXCSUM | IFCAP_TSO4; 1456 ifp->if_hwassist = MSK_CSUM_FEATURES | CSUM_TSO; 1457 ifp->if_capenable = ifp->if_capabilities; 1458 ifp->if_ioctl = msk_ioctl; 1459 ifp->if_start = msk_start; 1460 ifp->if_timer = 0; 1461 ifp->if_watchdog = NULL; 1462 ifp->if_init = msk_init; 1463 IFQ_SET_MAXLEN(&ifp->if_snd, MSK_TX_RING_CNT - 1); 1464 ifp->if_snd.ifq_drv_maxlen = MSK_TX_RING_CNT - 1; 1465 IFQ_SET_READY(&ifp->if_snd); 1466 1467 TASK_INIT(&sc_if->msk_tx_task, 1, msk_tx_task, ifp); 1468 1469 /* 1470 * Get station address for this interface. Note that 1471 * dual port cards actually come with three station 1472 * addresses: one for each port, plus an extra. The 1473 * extra one is used by the SysKonnect driver software 1474 * as a 'virtual' station address for when both ports 1475 * are operating in failover mode. Currently we don't 1476 * use this extra address. 1477 */ 1478 MSK_IF_LOCK(sc_if); 1479 for (i = 0; i < ETHER_ADDR_LEN; i++) 1480 eaddr[i] = CSR_READ_1(sc, B2_MAC_1 + (port * 8) + i); 1481 1482 /* 1483 * Call MI attach routine. Can't hold locks when calling into ether_*. 1484 */ 1485 MSK_IF_UNLOCK(sc_if); 1486 ether_ifattach(ifp, eaddr); 1487 MSK_IF_LOCK(sc_if); 1488 1489 /* 1490 * VLAN capability setup 1491 * Due to Tx checksum offload hardware bugs, msk(4) manually 1492 * computes checksum for short frames. For VLAN tagged frames 1493 * this workaround does not work so disable checksum offload 1494 * for VLAN interface. 1495 */ 1496 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING; 1497 ifp->if_capenable = ifp->if_capabilities; 1498 1499 /* 1500 * Tell the upper layer(s) we support long frames. 1501 * Must appear after the call to ether_ifattach() because 1502 * ether_ifattach() sets ifi_hdrlen to the default value. 1503 */ 1504 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1505 1506 sc_if->msk_framesize = ifp->if_mtu + ETHER_HDR_LEN + 1507 ETHER_VLAN_ENCAP_LEN; 1508 1509 /* 1510 * Do miibus setup. 1511 */ 1512 MSK_IF_UNLOCK(sc_if); 1513 error = mii_phy_probe(dev, &sc_if->msk_miibus, msk_mediachange, 1514 msk_mediastatus); 1515 if (error != 0) { 1516 device_printf(sc_if->msk_if_dev, "no PHY found!\n"); 1517 ether_ifdetach(ifp); 1518 error = ENXIO; 1519 goto fail; 1520 } 1521 1522 fail: 1523 if (error != 0) { 1524 /* Access should be ok even though lock has been dropped */ 1525 sc->msk_if[port] = NULL; 1526 msk_detach(dev); 1527 } 1528 1529 return (error); 1530 } 1531 1532 /* 1533 * Attach the interface. Allocate softc structures, do ifmedia 1534 * setup and ethernet/BPF attach. 1535 */ 1536 static int 1537 mskc_attach(device_t dev) 1538 { 1539 struct msk_softc *sc; 1540 int error, msic, msir, *port, reg; 1541 1542 sc = device_get_softc(dev); 1543 sc->msk_dev = dev; 1544 mtx_init(&sc->msk_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1545 MTX_DEF); 1546 1547 /* 1548 * Map control/status registers. 1549 */ 1550 pci_enable_busmaster(dev); 1551 1552 /* Allocate I/O resource */ 1553 #ifdef MSK_USEIOSPACE 1554 sc->msk_res_spec = msk_res_spec_io; 1555 #else 1556 sc->msk_res_spec = msk_res_spec_mem; 1557 #endif 1558 sc->msk_irq_spec = msk_irq_spec_legacy; 1559 error = bus_alloc_resources(dev, sc->msk_res_spec, sc->msk_res); 1560 if (error) { 1561 if (sc->msk_res_spec == msk_res_spec_mem) 1562 sc->msk_res_spec = msk_res_spec_io; 1563 else 1564 sc->msk_res_spec = msk_res_spec_mem; 1565 error = bus_alloc_resources(dev, sc->msk_res_spec, sc->msk_res); 1566 if (error) { 1567 device_printf(dev, "couldn't allocate %s resources\n", 1568 sc->msk_res_spec == msk_res_spec_mem ? "memory" : 1569 "I/O"); 1570 mtx_destroy(&sc->msk_mtx); 1571 return (ENXIO); 1572 } 1573 } 1574 1575 CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR); 1576 sc->msk_hw_id = CSR_READ_1(sc, B2_CHIP_ID); 1577 sc->msk_hw_rev = (CSR_READ_1(sc, B2_MAC_CFG) >> 4) & 0x0f; 1578 /* Bail out if chip is not recognized. */ 1579 if (sc->msk_hw_id < CHIP_ID_YUKON_XL || 1580 sc->msk_hw_id > CHIP_ID_YUKON_FE) { 1581 device_printf(dev, "unknown device: id=0x%02x, rev=0x%02x\n", 1582 sc->msk_hw_id, sc->msk_hw_rev); 1583 mtx_destroy(&sc->msk_mtx); 1584 return (ENXIO); 1585 } 1586 1587 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 1588 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 1589 OID_AUTO, "process_limit", CTLTYPE_INT | CTLFLAG_RW, 1590 &sc->msk_process_limit, 0, sysctl_hw_msk_proc_limit, "I", 1591 "max number of Rx events to process"); 1592 1593 sc->msk_process_limit = MSK_PROC_DEFAULT; 1594 error = resource_int_value(device_get_name(dev), device_get_unit(dev), 1595 "process_limit", &sc->msk_process_limit); 1596 if (error == 0) { 1597 if (sc->msk_process_limit < MSK_PROC_MIN || 1598 sc->msk_process_limit > MSK_PROC_MAX) { 1599 device_printf(dev, "process_limit value out of range; " 1600 "using default: %d\n", MSK_PROC_DEFAULT); 1601 sc->msk_process_limit = MSK_PROC_DEFAULT; 1602 } 1603 } 1604 1605 /* Soft reset. */ 1606 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); 1607 CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR); 1608 sc->msk_pmd = CSR_READ_1(sc, B2_PMD_TYP); 1609 if (sc->msk_pmd == 'L' || sc->msk_pmd == 'S') 1610 sc->msk_coppertype = 0; 1611 else 1612 sc->msk_coppertype = 1; 1613 /* Check number of MACs. */ 1614 sc->msk_num_port = 1; 1615 if ((CSR_READ_1(sc, B2_Y2_HW_RES) & CFG_DUAL_MAC_MSK) == 1616 CFG_DUAL_MAC_MSK) { 1617 if (!(CSR_READ_1(sc, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC)) 1618 sc->msk_num_port++; 1619 } 1620 1621 /* Check bus type. */ 1622 if (pci_find_extcap(sc->msk_dev, PCIY_EXPRESS, ®) == 0) 1623 sc->msk_bustype = MSK_PEX_BUS; 1624 else if (pci_find_extcap(sc->msk_dev, PCIY_PCIX, ®) == 0) 1625 sc->msk_bustype = MSK_PCIX_BUS; 1626 else 1627 sc->msk_bustype = MSK_PCI_BUS; 1628 1629 switch (sc->msk_hw_id) { 1630 case CHIP_ID_YUKON_EC: 1631 case CHIP_ID_YUKON_EC_U: 1632 sc->msk_clock = 125; /* 125 Mhz */ 1633 break; 1634 case CHIP_ID_YUKON_FE: 1635 sc->msk_clock = 100; /* 100 Mhz */ 1636 break; 1637 case CHIP_ID_YUKON_XL: 1638 sc->msk_clock = 156; /* 156 Mhz */ 1639 break; 1640 default: 1641 sc->msk_clock = 156; /* 156 Mhz */ 1642 break; 1643 } 1644 1645 /* Allocate IRQ resources. */ 1646 msic = pci_msi_count(dev); 1647 if (bootverbose) 1648 device_printf(dev, "MSI count : %d\n", msic); 1649 /* 1650 * The Yukon II reports it can handle two messages, one for each 1651 * possible port. We go ahead and allocate two messages and only 1652 * setup a handler for both if we have a dual port card. 1653 * 1654 * XXX: I haven't untangled the interrupt handler to handle dual 1655 * port cards with separate MSI messages, so for now I disable MSI 1656 * on dual port cards. 1657 */ 1658 if (legacy_intr != 0) 1659 msi_disable = 1; 1660 if (msi_disable == 0) { 1661 switch (msic) { 1662 case 2: 1663 case 1: /* 88E8058 reports 1 MSI message */ 1664 msir = msic; 1665 if (sc->msk_num_port == 1 && 1666 pci_alloc_msi(dev, &msir) == 0) { 1667 if (msic == msir) { 1668 sc->msk_msi = 1; 1669 sc->msk_irq_spec = msic == 2 ? 1670 msk_irq_spec_msi2 : 1671 msk_irq_spec_msi; 1672 } else 1673 pci_release_msi(dev); 1674 } 1675 break; 1676 default: 1677 device_printf(dev, 1678 "Unexpected number of MSI messages : %d\n", msic); 1679 break; 1680 } 1681 } 1682 1683 error = bus_alloc_resources(dev, sc->msk_irq_spec, sc->msk_irq); 1684 if (error) { 1685 device_printf(dev, "couldn't allocate IRQ resources\n"); 1686 goto fail; 1687 } 1688 1689 if ((error = msk_status_dma_alloc(sc)) != 0) 1690 goto fail; 1691 1692 /* Set base interrupt mask. */ 1693 sc->msk_intrmask = Y2_IS_HW_ERR | Y2_IS_STAT_BMU; 1694 sc->msk_intrhwemask = Y2_IS_TIST_OV | Y2_IS_MST_ERR | 1695 Y2_IS_IRQ_STAT | Y2_IS_PCI_EXP | Y2_IS_PCI_NEXP; 1696 1697 /* Reset the adapter. */ 1698 mskc_reset(sc); 1699 1700 if ((error = mskc_setup_rambuffer(sc)) != 0) 1701 goto fail; 1702 1703 sc->msk_devs[MSK_PORT_A] = device_add_child(dev, "msk", -1); 1704 if (sc->msk_devs[MSK_PORT_A] == NULL) { 1705 device_printf(dev, "failed to add child for PORT_A\n"); 1706 error = ENXIO; 1707 goto fail; 1708 } 1709 port = malloc(sizeof(int), M_DEVBUF, M_WAITOK); 1710 if (port == NULL) { 1711 device_printf(dev, "failed to allocate memory for " 1712 "ivars of PORT_A\n"); 1713 error = ENXIO; 1714 goto fail; 1715 } 1716 *port = MSK_PORT_A; 1717 device_set_ivars(sc->msk_devs[MSK_PORT_A], port); 1718 1719 if (sc->msk_num_port > 1) { 1720 sc->msk_devs[MSK_PORT_B] = device_add_child(dev, "msk", -1); 1721 if (sc->msk_devs[MSK_PORT_B] == NULL) { 1722 device_printf(dev, "failed to add child for PORT_B\n"); 1723 error = ENXIO; 1724 goto fail; 1725 } 1726 port = malloc(sizeof(int), M_DEVBUF, M_WAITOK); 1727 if (port == NULL) { 1728 device_printf(dev, "failed to allocate memory for " 1729 "ivars of PORT_B\n"); 1730 error = ENXIO; 1731 goto fail; 1732 } 1733 *port = MSK_PORT_B; 1734 device_set_ivars(sc->msk_devs[MSK_PORT_B], port); 1735 } 1736 1737 error = bus_generic_attach(dev); 1738 if (error) { 1739 device_printf(dev, "failed to attach port(s)\n"); 1740 goto fail; 1741 } 1742 1743 /* Hook interrupt last to avoid having to lock softc. */ 1744 if (legacy_intr) 1745 error = bus_setup_intr(dev, sc->msk_irq[0], INTR_TYPE_NET | 1746 INTR_MPSAFE, NULL, msk_legacy_intr, sc, 1747 &sc->msk_intrhand[0]); 1748 else { 1749 TASK_INIT(&sc->msk_int_task, 0, msk_int_task, sc); 1750 sc->msk_tq = taskqueue_create_fast("msk_taskq", M_WAITOK, 1751 taskqueue_thread_enqueue, &sc->msk_tq); 1752 taskqueue_start_threads(&sc->msk_tq, 1, PI_NET, "%s taskq", 1753 device_get_nameunit(sc->msk_dev)); 1754 error = bus_setup_intr(dev, sc->msk_irq[0], INTR_TYPE_NET | 1755 INTR_MPSAFE, msk_intr, NULL, sc, &sc->msk_intrhand[0]); 1756 } 1757 1758 if (error != 0) { 1759 device_printf(dev, "couldn't set up interrupt handler\n"); 1760 if (legacy_intr == 0) 1761 taskqueue_free(sc->msk_tq); 1762 sc->msk_tq = NULL; 1763 goto fail; 1764 } 1765 fail: 1766 if (error != 0) 1767 mskc_detach(dev); 1768 1769 return (error); 1770 } 1771 1772 /* 1773 * Shutdown hardware and free up resources. This can be called any 1774 * time after the mutex has been initialized. It is called in both 1775 * the error case in attach and the normal detach case so it needs 1776 * to be careful about only freeing resources that have actually been 1777 * allocated. 1778 */ 1779 static int 1780 msk_detach(device_t dev) 1781 { 1782 struct msk_softc *sc; 1783 struct msk_if_softc *sc_if; 1784 struct ifnet *ifp; 1785 1786 sc_if = device_get_softc(dev); 1787 KASSERT(mtx_initialized(&sc_if->msk_softc->msk_mtx), 1788 ("msk mutex not initialized in msk_detach")); 1789 MSK_IF_LOCK(sc_if); 1790 1791 ifp = sc_if->msk_ifp; 1792 if (device_is_attached(dev)) { 1793 /* XXX */ 1794 sc_if->msk_detach = 1; 1795 msk_stop(sc_if); 1796 /* Can't hold locks while calling detach. */ 1797 MSK_IF_UNLOCK(sc_if); 1798 callout_drain(&sc_if->msk_tick_ch); 1799 taskqueue_drain(taskqueue_fast, &sc_if->msk_tx_task); 1800 taskqueue_drain(taskqueue_swi, &sc_if->msk_link_task); 1801 ether_ifdetach(ifp); 1802 MSK_IF_LOCK(sc_if); 1803 } 1804 1805 /* 1806 * We're generally called from mskc_detach() which is using 1807 * device_delete_child() to get to here. It's already trashed 1808 * miibus for us, so don't do it here or we'll panic. 1809 * 1810 * if (sc_if->msk_miibus != NULL) { 1811 * device_delete_child(dev, sc_if->msk_miibus); 1812 * sc_if->msk_miibus = NULL; 1813 * } 1814 */ 1815 1816 msk_txrx_dma_free(sc_if); 1817 bus_generic_detach(dev); 1818 1819 if (ifp) 1820 if_free(ifp); 1821 sc = sc_if->msk_softc; 1822 sc->msk_if[sc_if->msk_port] = NULL; 1823 MSK_IF_UNLOCK(sc_if); 1824 1825 return (0); 1826 } 1827 1828 static int 1829 mskc_detach(device_t dev) 1830 { 1831 struct msk_softc *sc; 1832 1833 sc = device_get_softc(dev); 1834 KASSERT(mtx_initialized(&sc->msk_mtx), ("msk mutex not initialized")); 1835 1836 if (device_is_alive(dev)) { 1837 if (sc->msk_devs[MSK_PORT_A] != NULL) { 1838 free(device_get_ivars(sc->msk_devs[MSK_PORT_A]), 1839 M_DEVBUF); 1840 device_delete_child(dev, sc->msk_devs[MSK_PORT_A]); 1841 } 1842 if (sc->msk_devs[MSK_PORT_B] != NULL) { 1843 free(device_get_ivars(sc->msk_devs[MSK_PORT_B]), 1844 M_DEVBUF); 1845 device_delete_child(dev, sc->msk_devs[MSK_PORT_B]); 1846 } 1847 bus_generic_detach(dev); 1848 } 1849 1850 /* Disable all interrupts. */ 1851 CSR_WRITE_4(sc, B0_IMSK, 0); 1852 CSR_READ_4(sc, B0_IMSK); 1853 CSR_WRITE_4(sc, B0_HWE_IMSK, 0); 1854 CSR_READ_4(sc, B0_HWE_IMSK); 1855 1856 /* LED Off. */ 1857 CSR_WRITE_2(sc, B0_CTST, Y2_LED_STAT_OFF); 1858 1859 /* Put hardware reset. */ 1860 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); 1861 1862 msk_status_dma_free(sc); 1863 1864 if (legacy_intr == 0 && sc->msk_tq != NULL) { 1865 taskqueue_drain(sc->msk_tq, &sc->msk_int_task); 1866 taskqueue_free(sc->msk_tq); 1867 sc->msk_tq = NULL; 1868 } 1869 if (sc->msk_intrhand[0]) { 1870 bus_teardown_intr(dev, sc->msk_irq[0], sc->msk_intrhand[0]); 1871 sc->msk_intrhand[0] = NULL; 1872 } 1873 if (sc->msk_intrhand[1]) { 1874 bus_teardown_intr(dev, sc->msk_irq[0], sc->msk_intrhand[0]); 1875 sc->msk_intrhand[1] = NULL; 1876 } 1877 bus_release_resources(dev, sc->msk_irq_spec, sc->msk_irq); 1878 if (sc->msk_msi) 1879 pci_release_msi(dev); 1880 bus_release_resources(dev, sc->msk_res_spec, sc->msk_res); 1881 mtx_destroy(&sc->msk_mtx); 1882 1883 return (0); 1884 } 1885 1886 struct msk_dmamap_arg { 1887 bus_addr_t msk_busaddr; 1888 }; 1889 1890 static void 1891 msk_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1892 { 1893 struct msk_dmamap_arg *ctx; 1894 1895 if (error != 0) 1896 return; 1897 ctx = arg; 1898 ctx->msk_busaddr = segs[0].ds_addr; 1899 } 1900 1901 /* Create status DMA region. */ 1902 static int 1903 msk_status_dma_alloc(struct msk_softc *sc) 1904 { 1905 struct msk_dmamap_arg ctx; 1906 int error; 1907 1908 error = bus_dma_tag_create( 1909 bus_get_dma_tag(sc->msk_dev), /* parent */ 1910 MSK_STAT_ALIGN, 0, /* alignment, boundary */ 1911 BUS_SPACE_MAXADDR, /* lowaddr */ 1912 BUS_SPACE_MAXADDR, /* highaddr */ 1913 NULL, NULL, /* filter, filterarg */ 1914 MSK_STAT_RING_SZ, /* maxsize */ 1915 1, /* nsegments */ 1916 MSK_STAT_RING_SZ, /* maxsegsize */ 1917 0, /* flags */ 1918 NULL, NULL, /* lockfunc, lockarg */ 1919 &sc->msk_stat_tag); 1920 if (error != 0) { 1921 device_printf(sc->msk_dev, 1922 "failed to create status DMA tag\n"); 1923 return (error); 1924 } 1925 1926 /* Allocate DMA'able memory and load the DMA map for status ring. */ 1927 error = bus_dmamem_alloc(sc->msk_stat_tag, 1928 (void **)&sc->msk_stat_ring, BUS_DMA_WAITOK | BUS_DMA_COHERENT | 1929 BUS_DMA_ZERO, &sc->msk_stat_map); 1930 if (error != 0) { 1931 device_printf(sc->msk_dev, 1932 "failed to allocate DMA'able memory for status ring\n"); 1933 return (error); 1934 } 1935 1936 ctx.msk_busaddr = 0; 1937 error = bus_dmamap_load(sc->msk_stat_tag, 1938 sc->msk_stat_map, sc->msk_stat_ring, MSK_STAT_RING_SZ, 1939 msk_dmamap_cb, &ctx, 0); 1940 if (error != 0) { 1941 device_printf(sc->msk_dev, 1942 "failed to load DMA'able memory for status ring\n"); 1943 return (error); 1944 } 1945 sc->msk_stat_ring_paddr = ctx.msk_busaddr; 1946 1947 return (0); 1948 } 1949 1950 static void 1951 msk_status_dma_free(struct msk_softc *sc) 1952 { 1953 1954 /* Destroy status block. */ 1955 if (sc->msk_stat_tag) { 1956 if (sc->msk_stat_map) { 1957 bus_dmamap_unload(sc->msk_stat_tag, sc->msk_stat_map); 1958 if (sc->msk_stat_ring) { 1959 bus_dmamem_free(sc->msk_stat_tag, 1960 sc->msk_stat_ring, sc->msk_stat_map); 1961 sc->msk_stat_ring = NULL; 1962 } 1963 sc->msk_stat_map = NULL; 1964 } 1965 bus_dma_tag_destroy(sc->msk_stat_tag); 1966 sc->msk_stat_tag = NULL; 1967 } 1968 } 1969 1970 static int 1971 msk_txrx_dma_alloc(struct msk_if_softc *sc_if) 1972 { 1973 struct msk_dmamap_arg ctx; 1974 struct msk_txdesc *txd; 1975 struct msk_rxdesc *rxd; 1976 struct msk_rxdesc *jrxd; 1977 struct msk_jpool_entry *entry; 1978 uint8_t *ptr; 1979 int error, i; 1980 1981 mtx_init(&sc_if->msk_jlist_mtx, "msk_jlist_mtx", NULL, MTX_DEF); 1982 SLIST_INIT(&sc_if->msk_jfree_listhead); 1983 SLIST_INIT(&sc_if->msk_jinuse_listhead); 1984 1985 /* Create parent DMA tag. */ 1986 /* 1987 * XXX 1988 * It seems that Yukon II supports full 64bits DMA operations. But 1989 * it needs two descriptors(list elements) for 64bits DMA operations. 1990 * Since we don't know what DMA address mappings(32bits or 64bits) 1991 * would be used in advance for each mbufs, we limits its DMA space 1992 * to be in range of 32bits address space. Otherwise, we should check 1993 * what DMA address is used and chain another descriptor for the 1994 * 64bits DMA operation. This also means descriptor ring size is 1995 * variable. Limiting DMA address to be in 32bit address space greatly 1996 * simplyfies descriptor handling and possibly would increase 1997 * performance a bit due to efficient handling of descriptors. 1998 * Apart from harassing checksum offloading mechanisms, it seems 1999 * it's really bad idea to use a seperate descriptor for 64bit 2000 * DMA operation to save small descriptor memory. Anyway, I've 2001 * never seen these exotic scheme on ethernet interface hardware. 2002 */ 2003 error = bus_dma_tag_create( 2004 bus_get_dma_tag(sc_if->msk_if_dev), /* parent */ 2005 1, 0, /* alignment, boundary */ 2006 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 2007 BUS_SPACE_MAXADDR, /* highaddr */ 2008 NULL, NULL, /* filter, filterarg */ 2009 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 2010 0, /* nsegments */ 2011 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 2012 0, /* flags */ 2013 NULL, NULL, /* lockfunc, lockarg */ 2014 &sc_if->msk_cdata.msk_parent_tag); 2015 if (error != 0) { 2016 device_printf(sc_if->msk_if_dev, 2017 "failed to create parent DMA tag\n"); 2018 goto fail; 2019 } 2020 /* Create tag for Tx ring. */ 2021 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2022 MSK_RING_ALIGN, 0, /* alignment, boundary */ 2023 BUS_SPACE_MAXADDR, /* lowaddr */ 2024 BUS_SPACE_MAXADDR, /* highaddr */ 2025 NULL, NULL, /* filter, filterarg */ 2026 MSK_TX_RING_SZ, /* maxsize */ 2027 1, /* nsegments */ 2028 MSK_TX_RING_SZ, /* maxsegsize */ 2029 0, /* flags */ 2030 NULL, NULL, /* lockfunc, lockarg */ 2031 &sc_if->msk_cdata.msk_tx_ring_tag); 2032 if (error != 0) { 2033 device_printf(sc_if->msk_if_dev, 2034 "failed to create Tx ring DMA tag\n"); 2035 goto fail; 2036 } 2037 2038 /* Create tag for Rx ring. */ 2039 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2040 MSK_RING_ALIGN, 0, /* alignment, boundary */ 2041 BUS_SPACE_MAXADDR, /* lowaddr */ 2042 BUS_SPACE_MAXADDR, /* highaddr */ 2043 NULL, NULL, /* filter, filterarg */ 2044 MSK_RX_RING_SZ, /* maxsize */ 2045 1, /* nsegments */ 2046 MSK_RX_RING_SZ, /* maxsegsize */ 2047 0, /* flags */ 2048 NULL, NULL, /* lockfunc, lockarg */ 2049 &sc_if->msk_cdata.msk_rx_ring_tag); 2050 if (error != 0) { 2051 device_printf(sc_if->msk_if_dev, 2052 "failed to create Rx ring DMA tag\n"); 2053 goto fail; 2054 } 2055 2056 /* Create tag for jumbo Rx ring. */ 2057 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2058 MSK_RING_ALIGN, 0, /* alignment, boundary */ 2059 BUS_SPACE_MAXADDR, /* lowaddr */ 2060 BUS_SPACE_MAXADDR, /* highaddr */ 2061 NULL, NULL, /* filter, filterarg */ 2062 MSK_JUMBO_RX_RING_SZ, /* maxsize */ 2063 1, /* nsegments */ 2064 MSK_JUMBO_RX_RING_SZ, /* maxsegsize */ 2065 0, /* flags */ 2066 NULL, NULL, /* lockfunc, lockarg */ 2067 &sc_if->msk_cdata.msk_jumbo_rx_ring_tag); 2068 if (error != 0) { 2069 device_printf(sc_if->msk_if_dev, 2070 "failed to create jumbo Rx ring DMA tag\n"); 2071 goto fail; 2072 } 2073 2074 /* Create tag for jumbo buffer blocks. */ 2075 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2076 PAGE_SIZE, 0, /* alignment, boundary */ 2077 BUS_SPACE_MAXADDR, /* lowaddr */ 2078 BUS_SPACE_MAXADDR, /* highaddr */ 2079 NULL, NULL, /* filter, filterarg */ 2080 MSK_JMEM, /* maxsize */ 2081 1, /* nsegments */ 2082 MSK_JMEM, /* maxsegsize */ 2083 0, /* flags */ 2084 NULL, NULL, /* lockfunc, lockarg */ 2085 &sc_if->msk_cdata.msk_jumbo_tag); 2086 if (error != 0) { 2087 device_printf(sc_if->msk_if_dev, 2088 "failed to create jumbo Rx buffer block DMA tag\n"); 2089 goto fail; 2090 } 2091 2092 /* Create tag for Tx buffers. */ 2093 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2094 1, 0, /* alignment, boundary */ 2095 BUS_SPACE_MAXADDR, /* lowaddr */ 2096 BUS_SPACE_MAXADDR, /* highaddr */ 2097 NULL, NULL, /* filter, filterarg */ 2098 MSK_TSO_MAXSIZE, /* maxsize */ 2099 MSK_MAXTXSEGS, /* nsegments */ 2100 MSK_TSO_MAXSGSIZE, /* maxsegsize */ 2101 0, /* flags */ 2102 NULL, NULL, /* lockfunc, lockarg */ 2103 &sc_if->msk_cdata.msk_tx_tag); 2104 if (error != 0) { 2105 device_printf(sc_if->msk_if_dev, 2106 "failed to create Tx DMA tag\n"); 2107 goto fail; 2108 } 2109 2110 /* Create tag for Rx buffers. */ 2111 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2112 1, 0, /* alignment, boundary */ 2113 BUS_SPACE_MAXADDR, /* lowaddr */ 2114 BUS_SPACE_MAXADDR, /* highaddr */ 2115 NULL, NULL, /* filter, filterarg */ 2116 MCLBYTES, /* maxsize */ 2117 1, /* nsegments */ 2118 MCLBYTES, /* maxsegsize */ 2119 0, /* flags */ 2120 NULL, NULL, /* lockfunc, lockarg */ 2121 &sc_if->msk_cdata.msk_rx_tag); 2122 if (error != 0) { 2123 device_printf(sc_if->msk_if_dev, 2124 "failed to create Rx DMA tag\n"); 2125 goto fail; 2126 } 2127 2128 /* Create tag for jumbo Rx buffers. */ 2129 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2130 PAGE_SIZE, 0, /* alignment, boundary */ 2131 BUS_SPACE_MAXADDR, /* lowaddr */ 2132 BUS_SPACE_MAXADDR, /* highaddr */ 2133 NULL, NULL, /* filter, filterarg */ 2134 MCLBYTES * MSK_MAXRXSEGS, /* maxsize */ 2135 MSK_MAXRXSEGS, /* nsegments */ 2136 MSK_JLEN, /* maxsegsize */ 2137 0, /* flags */ 2138 NULL, NULL, /* lockfunc, lockarg */ 2139 &sc_if->msk_cdata.msk_jumbo_rx_tag); 2140 if (error != 0) { 2141 device_printf(sc_if->msk_if_dev, 2142 "failed to create jumbo Rx DMA tag\n"); 2143 goto fail; 2144 } 2145 2146 /* Allocate DMA'able memory and load the DMA map for Tx ring. */ 2147 error = bus_dmamem_alloc(sc_if->msk_cdata.msk_tx_ring_tag, 2148 (void **)&sc_if->msk_rdata.msk_tx_ring, BUS_DMA_WAITOK | 2149 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc_if->msk_cdata.msk_tx_ring_map); 2150 if (error != 0) { 2151 device_printf(sc_if->msk_if_dev, 2152 "failed to allocate DMA'able memory for Tx ring\n"); 2153 goto fail; 2154 } 2155 2156 ctx.msk_busaddr = 0; 2157 error = bus_dmamap_load(sc_if->msk_cdata.msk_tx_ring_tag, 2158 sc_if->msk_cdata.msk_tx_ring_map, sc_if->msk_rdata.msk_tx_ring, 2159 MSK_TX_RING_SZ, msk_dmamap_cb, &ctx, 0); 2160 if (error != 0) { 2161 device_printf(sc_if->msk_if_dev, 2162 "failed to load DMA'able memory for Tx ring\n"); 2163 goto fail; 2164 } 2165 sc_if->msk_rdata.msk_tx_ring_paddr = ctx.msk_busaddr; 2166 2167 /* Allocate DMA'able memory and load the DMA map for Rx ring. */ 2168 error = bus_dmamem_alloc(sc_if->msk_cdata.msk_rx_ring_tag, 2169 (void **)&sc_if->msk_rdata.msk_rx_ring, BUS_DMA_WAITOK | 2170 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc_if->msk_cdata.msk_rx_ring_map); 2171 if (error != 0) { 2172 device_printf(sc_if->msk_if_dev, 2173 "failed to allocate DMA'able memory for Rx ring\n"); 2174 goto fail; 2175 } 2176 2177 ctx.msk_busaddr = 0; 2178 error = bus_dmamap_load(sc_if->msk_cdata.msk_rx_ring_tag, 2179 sc_if->msk_cdata.msk_rx_ring_map, sc_if->msk_rdata.msk_rx_ring, 2180 MSK_RX_RING_SZ, msk_dmamap_cb, &ctx, 0); 2181 if (error != 0) { 2182 device_printf(sc_if->msk_if_dev, 2183 "failed to load DMA'able memory for Rx ring\n"); 2184 goto fail; 2185 } 2186 sc_if->msk_rdata.msk_rx_ring_paddr = ctx.msk_busaddr; 2187 2188 /* Allocate DMA'able memory and load the DMA map for jumbo Rx ring. */ 2189 error = bus_dmamem_alloc(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 2190 (void **)&sc_if->msk_rdata.msk_jumbo_rx_ring, 2191 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 2192 &sc_if->msk_cdata.msk_jumbo_rx_ring_map); 2193 if (error != 0) { 2194 device_printf(sc_if->msk_if_dev, 2195 "failed to allocate DMA'able memory for jumbo Rx ring\n"); 2196 goto fail; 2197 } 2198 2199 ctx.msk_busaddr = 0; 2200 error = bus_dmamap_load(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 2201 sc_if->msk_cdata.msk_jumbo_rx_ring_map, 2202 sc_if->msk_rdata.msk_jumbo_rx_ring, MSK_JUMBO_RX_RING_SZ, 2203 msk_dmamap_cb, &ctx, 0); 2204 if (error != 0) { 2205 device_printf(sc_if->msk_if_dev, 2206 "failed to load DMA'able memory for jumbo Rx ring\n"); 2207 goto fail; 2208 } 2209 sc_if->msk_rdata.msk_jumbo_rx_ring_paddr = ctx.msk_busaddr; 2210 2211 /* Create DMA maps for Tx buffers. */ 2212 for (i = 0; i < MSK_TX_RING_CNT; i++) { 2213 txd = &sc_if->msk_cdata.msk_txdesc[i]; 2214 txd->tx_m = NULL; 2215 txd->tx_dmamap = NULL; 2216 error = bus_dmamap_create(sc_if->msk_cdata.msk_tx_tag, 0, 2217 &txd->tx_dmamap); 2218 if (error != 0) { 2219 device_printf(sc_if->msk_if_dev, 2220 "failed to create Tx dmamap\n"); 2221 goto fail; 2222 } 2223 } 2224 /* Create DMA maps for Rx buffers. */ 2225 if ((error = bus_dmamap_create(sc_if->msk_cdata.msk_rx_tag, 0, 2226 &sc_if->msk_cdata.msk_rx_sparemap)) != 0) { 2227 device_printf(sc_if->msk_if_dev, 2228 "failed to create spare Rx dmamap\n"); 2229 goto fail; 2230 } 2231 for (i = 0; i < MSK_RX_RING_CNT; i++) { 2232 rxd = &sc_if->msk_cdata.msk_rxdesc[i]; 2233 rxd->rx_m = NULL; 2234 rxd->rx_dmamap = NULL; 2235 error = bus_dmamap_create(sc_if->msk_cdata.msk_rx_tag, 0, 2236 &rxd->rx_dmamap); 2237 if (error != 0) { 2238 device_printf(sc_if->msk_if_dev, 2239 "failed to create Rx dmamap\n"); 2240 goto fail; 2241 } 2242 } 2243 /* Create DMA maps for jumbo Rx buffers. */ 2244 if ((error = bus_dmamap_create(sc_if->msk_cdata.msk_jumbo_rx_tag, 0, 2245 &sc_if->msk_cdata.msk_jumbo_rx_sparemap)) != 0) { 2246 device_printf(sc_if->msk_if_dev, 2247 "failed to create spare jumbo Rx dmamap\n"); 2248 goto fail; 2249 } 2250 for (i = 0; i < MSK_JUMBO_RX_RING_CNT; i++) { 2251 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[i]; 2252 jrxd->rx_m = NULL; 2253 jrxd->rx_dmamap = NULL; 2254 error = bus_dmamap_create(sc_if->msk_cdata.msk_jumbo_rx_tag, 0, 2255 &jrxd->rx_dmamap); 2256 if (error != 0) { 2257 device_printf(sc_if->msk_if_dev, 2258 "failed to create jumbo Rx dmamap\n"); 2259 goto fail; 2260 } 2261 } 2262 2263 /* Allocate DMA'able memory and load the DMA map for jumbo buf. */ 2264 error = bus_dmamem_alloc(sc_if->msk_cdata.msk_jumbo_tag, 2265 (void **)&sc_if->msk_rdata.msk_jumbo_buf, 2266 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 2267 &sc_if->msk_cdata.msk_jumbo_map); 2268 if (error != 0) { 2269 device_printf(sc_if->msk_if_dev, 2270 "failed to allocate DMA'able memory for jumbo buf\n"); 2271 goto fail; 2272 } 2273 2274 ctx.msk_busaddr = 0; 2275 error = bus_dmamap_load(sc_if->msk_cdata.msk_jumbo_tag, 2276 sc_if->msk_cdata.msk_jumbo_map, sc_if->msk_rdata.msk_jumbo_buf, 2277 MSK_JMEM, msk_dmamap_cb, &ctx, 0); 2278 if (error != 0) { 2279 device_printf(sc_if->msk_if_dev, 2280 "failed to load DMA'able memory for jumbobuf\n"); 2281 goto fail; 2282 } 2283 sc_if->msk_rdata.msk_jumbo_buf_paddr = ctx.msk_busaddr; 2284 2285 /* 2286 * Now divide it up into 9K pieces and save the addresses 2287 * in an array. 2288 */ 2289 ptr = sc_if->msk_rdata.msk_jumbo_buf; 2290 for (i = 0; i < MSK_JSLOTS; i++) { 2291 sc_if->msk_cdata.msk_jslots[i] = ptr; 2292 ptr += MSK_JLEN; 2293 entry = malloc(sizeof(struct msk_jpool_entry), 2294 M_DEVBUF, M_WAITOK); 2295 if (entry == NULL) { 2296 device_printf(sc_if->msk_if_dev, 2297 "no memory for jumbo buffers!\n"); 2298 error = ENOMEM; 2299 goto fail; 2300 } 2301 entry->slot = i; 2302 SLIST_INSERT_HEAD(&sc_if->msk_jfree_listhead, entry, 2303 jpool_entries); 2304 } 2305 2306 fail: 2307 return (error); 2308 } 2309 2310 static void 2311 msk_txrx_dma_free(struct msk_if_softc *sc_if) 2312 { 2313 struct msk_txdesc *txd; 2314 struct msk_rxdesc *rxd; 2315 struct msk_rxdesc *jrxd; 2316 struct msk_jpool_entry *entry; 2317 int i; 2318 2319 MSK_JLIST_LOCK(sc_if); 2320 while ((entry = SLIST_FIRST(&sc_if->msk_jinuse_listhead))) { 2321 device_printf(sc_if->msk_if_dev, 2322 "asked to free buffer that is in use!\n"); 2323 SLIST_REMOVE_HEAD(&sc_if->msk_jinuse_listhead, jpool_entries); 2324 SLIST_INSERT_HEAD(&sc_if->msk_jfree_listhead, entry, 2325 jpool_entries); 2326 } 2327 2328 while (!SLIST_EMPTY(&sc_if->msk_jfree_listhead)) { 2329 entry = SLIST_FIRST(&sc_if->msk_jfree_listhead); 2330 SLIST_REMOVE_HEAD(&sc_if->msk_jfree_listhead, jpool_entries); 2331 free(entry, M_DEVBUF); 2332 } 2333 MSK_JLIST_UNLOCK(sc_if); 2334 2335 /* Destroy jumbo buffer block. */ 2336 if (sc_if->msk_cdata.msk_jumbo_map) 2337 bus_dmamap_unload(sc_if->msk_cdata.msk_jumbo_tag, 2338 sc_if->msk_cdata.msk_jumbo_map); 2339 2340 if (sc_if->msk_rdata.msk_jumbo_buf) { 2341 bus_dmamem_free(sc_if->msk_cdata.msk_jumbo_tag, 2342 sc_if->msk_rdata.msk_jumbo_buf, 2343 sc_if->msk_cdata.msk_jumbo_map); 2344 sc_if->msk_rdata.msk_jumbo_buf = NULL; 2345 sc_if->msk_cdata.msk_jumbo_map = NULL; 2346 } 2347 2348 /* Tx ring. */ 2349 if (sc_if->msk_cdata.msk_tx_ring_tag) { 2350 if (sc_if->msk_cdata.msk_tx_ring_map) 2351 bus_dmamap_unload(sc_if->msk_cdata.msk_tx_ring_tag, 2352 sc_if->msk_cdata.msk_tx_ring_map); 2353 if (sc_if->msk_cdata.msk_tx_ring_map && 2354 sc_if->msk_rdata.msk_tx_ring) 2355 bus_dmamem_free(sc_if->msk_cdata.msk_tx_ring_tag, 2356 sc_if->msk_rdata.msk_tx_ring, 2357 sc_if->msk_cdata.msk_tx_ring_map); 2358 sc_if->msk_rdata.msk_tx_ring = NULL; 2359 sc_if->msk_cdata.msk_tx_ring_map = NULL; 2360 bus_dma_tag_destroy(sc_if->msk_cdata.msk_tx_ring_tag); 2361 sc_if->msk_cdata.msk_tx_ring_tag = NULL; 2362 } 2363 /* Rx ring. */ 2364 if (sc_if->msk_cdata.msk_rx_ring_tag) { 2365 if (sc_if->msk_cdata.msk_rx_ring_map) 2366 bus_dmamap_unload(sc_if->msk_cdata.msk_rx_ring_tag, 2367 sc_if->msk_cdata.msk_rx_ring_map); 2368 if (sc_if->msk_cdata.msk_rx_ring_map && 2369 sc_if->msk_rdata.msk_rx_ring) 2370 bus_dmamem_free(sc_if->msk_cdata.msk_rx_ring_tag, 2371 sc_if->msk_rdata.msk_rx_ring, 2372 sc_if->msk_cdata.msk_rx_ring_map); 2373 sc_if->msk_rdata.msk_rx_ring = NULL; 2374 sc_if->msk_cdata.msk_rx_ring_map = NULL; 2375 bus_dma_tag_destroy(sc_if->msk_cdata.msk_rx_ring_tag); 2376 sc_if->msk_cdata.msk_rx_ring_tag = NULL; 2377 } 2378 /* Jumbo Rx ring. */ 2379 if (sc_if->msk_cdata.msk_jumbo_rx_ring_tag) { 2380 if (sc_if->msk_cdata.msk_jumbo_rx_ring_map) 2381 bus_dmamap_unload(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 2382 sc_if->msk_cdata.msk_jumbo_rx_ring_map); 2383 if (sc_if->msk_cdata.msk_jumbo_rx_ring_map && 2384 sc_if->msk_rdata.msk_jumbo_rx_ring) 2385 bus_dmamem_free(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 2386 sc_if->msk_rdata.msk_jumbo_rx_ring, 2387 sc_if->msk_cdata.msk_jumbo_rx_ring_map); 2388 sc_if->msk_rdata.msk_jumbo_rx_ring = NULL; 2389 sc_if->msk_cdata.msk_jumbo_rx_ring_map = NULL; 2390 bus_dma_tag_destroy(sc_if->msk_cdata.msk_jumbo_rx_ring_tag); 2391 sc_if->msk_cdata.msk_jumbo_rx_ring_tag = NULL; 2392 } 2393 /* Tx buffers. */ 2394 if (sc_if->msk_cdata.msk_tx_tag) { 2395 for (i = 0; i < MSK_TX_RING_CNT; i++) { 2396 txd = &sc_if->msk_cdata.msk_txdesc[i]; 2397 if (txd->tx_dmamap) { 2398 bus_dmamap_destroy(sc_if->msk_cdata.msk_tx_tag, 2399 txd->tx_dmamap); 2400 txd->tx_dmamap = NULL; 2401 } 2402 } 2403 bus_dma_tag_destroy(sc_if->msk_cdata.msk_tx_tag); 2404 sc_if->msk_cdata.msk_tx_tag = NULL; 2405 } 2406 /* Rx buffers. */ 2407 if (sc_if->msk_cdata.msk_rx_tag) { 2408 for (i = 0; i < MSK_RX_RING_CNT; i++) { 2409 rxd = &sc_if->msk_cdata.msk_rxdesc[i]; 2410 if (rxd->rx_dmamap) { 2411 bus_dmamap_destroy(sc_if->msk_cdata.msk_rx_tag, 2412 rxd->rx_dmamap); 2413 rxd->rx_dmamap = NULL; 2414 } 2415 } 2416 if (sc_if->msk_cdata.msk_rx_sparemap) { 2417 bus_dmamap_destroy(sc_if->msk_cdata.msk_rx_tag, 2418 sc_if->msk_cdata.msk_rx_sparemap); 2419 sc_if->msk_cdata.msk_rx_sparemap = 0; 2420 } 2421 bus_dma_tag_destroy(sc_if->msk_cdata.msk_rx_tag); 2422 sc_if->msk_cdata.msk_rx_tag = NULL; 2423 } 2424 /* Jumbo Rx buffers. */ 2425 if (sc_if->msk_cdata.msk_jumbo_rx_tag) { 2426 for (i = 0; i < MSK_JUMBO_RX_RING_CNT; i++) { 2427 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[i]; 2428 if (jrxd->rx_dmamap) { 2429 bus_dmamap_destroy( 2430 sc_if->msk_cdata.msk_jumbo_rx_tag, 2431 jrxd->rx_dmamap); 2432 jrxd->rx_dmamap = NULL; 2433 } 2434 } 2435 if (sc_if->msk_cdata.msk_jumbo_rx_sparemap) { 2436 bus_dmamap_destroy(sc_if->msk_cdata.msk_jumbo_rx_tag, 2437 sc_if->msk_cdata.msk_jumbo_rx_sparemap); 2438 sc_if->msk_cdata.msk_jumbo_rx_sparemap = 0; 2439 } 2440 bus_dma_tag_destroy(sc_if->msk_cdata.msk_jumbo_rx_tag); 2441 sc_if->msk_cdata.msk_jumbo_rx_tag = NULL; 2442 } 2443 2444 if (sc_if->msk_cdata.msk_parent_tag) { 2445 bus_dma_tag_destroy(sc_if->msk_cdata.msk_parent_tag); 2446 sc_if->msk_cdata.msk_parent_tag = NULL; 2447 } 2448 mtx_destroy(&sc_if->msk_jlist_mtx); 2449 } 2450 2451 /* 2452 * Allocate a jumbo buffer. 2453 */ 2454 static void * 2455 msk_jalloc(struct msk_if_softc *sc_if) 2456 { 2457 struct msk_jpool_entry *entry; 2458 2459 MSK_JLIST_LOCK(sc_if); 2460 2461 entry = SLIST_FIRST(&sc_if->msk_jfree_listhead); 2462 2463 if (entry == NULL) { 2464 MSK_JLIST_UNLOCK(sc_if); 2465 return (NULL); 2466 } 2467 2468 SLIST_REMOVE_HEAD(&sc_if->msk_jfree_listhead, jpool_entries); 2469 SLIST_INSERT_HEAD(&sc_if->msk_jinuse_listhead, entry, jpool_entries); 2470 2471 MSK_JLIST_UNLOCK(sc_if); 2472 2473 return (sc_if->msk_cdata.msk_jslots[entry->slot]); 2474 } 2475 2476 /* 2477 * Release a jumbo buffer. 2478 */ 2479 static void 2480 msk_jfree(void *buf, void *args) 2481 { 2482 struct msk_if_softc *sc_if; 2483 struct msk_jpool_entry *entry; 2484 int i; 2485 2486 /* Extract the softc struct pointer. */ 2487 sc_if = (struct msk_if_softc *)args; 2488 KASSERT(sc_if != NULL, ("%s: can't find softc pointer!", __func__)); 2489 2490 MSK_JLIST_LOCK(sc_if); 2491 /* Calculate the slot this buffer belongs to. */ 2492 i = ((vm_offset_t)buf 2493 - (vm_offset_t)sc_if->msk_rdata.msk_jumbo_buf) / MSK_JLEN; 2494 KASSERT(i >= 0 && i < MSK_JSLOTS, 2495 ("%s: asked to free buffer that we don't manage!", __func__)); 2496 2497 entry = SLIST_FIRST(&sc_if->msk_jinuse_listhead); 2498 KASSERT(entry != NULL, ("%s: buffer not in use!", __func__)); 2499 entry->slot = i; 2500 SLIST_REMOVE_HEAD(&sc_if->msk_jinuse_listhead, jpool_entries); 2501 SLIST_INSERT_HEAD(&sc_if->msk_jfree_listhead, entry, jpool_entries); 2502 if (SLIST_EMPTY(&sc_if->msk_jinuse_listhead)) 2503 wakeup(sc_if); 2504 2505 MSK_JLIST_UNLOCK(sc_if); 2506 } 2507 2508 static int 2509 msk_encap(struct msk_if_softc *sc_if, struct mbuf **m_head) 2510 { 2511 struct msk_txdesc *txd, *txd_last; 2512 struct msk_tx_desc *tx_le; 2513 struct mbuf *m; 2514 bus_dmamap_t map; 2515 bus_dma_segment_t txsegs[MSK_MAXTXSEGS]; 2516 uint32_t control, prod, si; 2517 uint16_t offset, tcp_offset, tso_mtu; 2518 int error, i, nseg, tso; 2519 2520 MSK_IF_LOCK_ASSERT(sc_if); 2521 2522 tcp_offset = offset = 0; 2523 m = *m_head; 2524 if ((m->m_pkthdr.csum_flags & (MSK_CSUM_FEATURES | CSUM_TSO)) != 0) { 2525 /* 2526 * Since mbuf has no protocol specific structure information 2527 * in it we have to inspect protocol information here to 2528 * setup TSO and checksum offload. I don't know why Marvell 2529 * made a such decision in chip design because other GigE 2530 * hardwares normally takes care of all these chores in 2531 * hardware. However, TSO performance of Yukon II is very 2532 * good such that it's worth to implement it. 2533 */ 2534 struct ether_header *eh; 2535 struct ip *ip; 2536 struct tcphdr *tcp; 2537 2538 /* TODO check for M_WRITABLE(m) */ 2539 2540 offset = sizeof(struct ether_header); 2541 m = m_pullup(m, offset); 2542 if (m == NULL) { 2543 *m_head = NULL; 2544 return (ENOBUFS); 2545 } 2546 eh = mtod(m, struct ether_header *); 2547 /* Check if hardware VLAN insertion is off. */ 2548 if (eh->ether_type == htons(ETHERTYPE_VLAN)) { 2549 offset = sizeof(struct ether_vlan_header); 2550 m = m_pullup(m, offset); 2551 if (m == NULL) { 2552 *m_head = NULL; 2553 return (ENOBUFS); 2554 } 2555 } 2556 m = m_pullup(m, offset + sizeof(struct ip)); 2557 if (m == NULL) { 2558 *m_head = NULL; 2559 return (ENOBUFS); 2560 } 2561 ip = (struct ip *)(mtod(m, char *) + offset); 2562 offset += (ip->ip_hl << 2); 2563 tcp_offset = offset; 2564 /* 2565 * It seems that Yukon II has Tx checksum offload bug for 2566 * small TCP packets that's less than 60 bytes in size 2567 * (e.g. TCP window probe packet, pure ACK packet). 2568 * Common work around like padding with zeros to make the 2569 * frame minimum ethernet frame size didn't work at all. 2570 * Instead of disabling checksum offload completely we 2571 * resort to S/W checksum routine when we encounter short 2572 * TCP frames. 2573 * Short UDP packets appear to be handled correctly by 2574 * Yukon II. 2575 */ 2576 if (m->m_pkthdr.len < MSK_MIN_FRAMELEN && 2577 (m->m_pkthdr.csum_flags & CSUM_TCP) != 0) { 2578 uint16_t csum; 2579 2580 csum = in_cksum_skip(m, ntohs(ip->ip_len) + offset - 2581 (ip->ip_hl << 2), offset); 2582 *(uint16_t *)(m->m_data + offset + 2583 m->m_pkthdr.csum_data) = csum; 2584 m->m_pkthdr.csum_flags &= ~CSUM_TCP; 2585 } 2586 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 2587 m = m_pullup(m, offset + sizeof(struct tcphdr)); 2588 if (m == NULL) { 2589 *m_head = NULL; 2590 return (ENOBUFS); 2591 } 2592 tcp = (struct tcphdr *)(mtod(m, char *) + offset); 2593 offset += (tcp->th_off << 2); 2594 } 2595 *m_head = m; 2596 } 2597 2598 prod = sc_if->msk_cdata.msk_tx_prod; 2599 txd = &sc_if->msk_cdata.msk_txdesc[prod]; 2600 txd_last = txd; 2601 map = txd->tx_dmamap; 2602 error = bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_tx_tag, map, 2603 *m_head, txsegs, &nseg, BUS_DMA_NOWAIT); 2604 if (error == EFBIG) { 2605 m = m_collapse(*m_head, M_DONTWAIT, MSK_MAXTXSEGS); 2606 if (m == NULL) { 2607 m_freem(*m_head); 2608 *m_head = NULL; 2609 return (ENOBUFS); 2610 } 2611 *m_head = m; 2612 error = bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_tx_tag, 2613 map, *m_head, txsegs, &nseg, BUS_DMA_NOWAIT); 2614 if (error != 0) { 2615 m_freem(*m_head); 2616 *m_head = NULL; 2617 return (error); 2618 } 2619 } else if (error != 0) 2620 return (error); 2621 if (nseg == 0) { 2622 m_freem(*m_head); 2623 *m_head = NULL; 2624 return (EIO); 2625 } 2626 2627 /* Check number of available descriptors. */ 2628 if (sc_if->msk_cdata.msk_tx_cnt + nseg >= 2629 (MSK_TX_RING_CNT - MSK_RESERVED_TX_DESC_CNT)) { 2630 bus_dmamap_unload(sc_if->msk_cdata.msk_tx_tag, map); 2631 return (ENOBUFS); 2632 } 2633 2634 control = 0; 2635 tso = 0; 2636 tx_le = NULL; 2637 2638 /* Check TSO support. */ 2639 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 2640 tso_mtu = offset + m->m_pkthdr.tso_segsz; 2641 if (tso_mtu != sc_if->msk_cdata.msk_tso_mtu) { 2642 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2643 tx_le->msk_addr = htole32(tso_mtu); 2644 tx_le->msk_control = htole32(OP_LRGLEN | HW_OWNER); 2645 sc_if->msk_cdata.msk_tx_cnt++; 2646 MSK_INC(prod, MSK_TX_RING_CNT); 2647 sc_if->msk_cdata.msk_tso_mtu = tso_mtu; 2648 } 2649 tso++; 2650 } 2651 /* Check if we have a VLAN tag to insert. */ 2652 if ((m->m_flags & M_VLANTAG) != 0) { 2653 if (tso == 0) { 2654 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2655 tx_le->msk_addr = htole32(0); 2656 tx_le->msk_control = htole32(OP_VLAN | HW_OWNER | 2657 htons(m->m_pkthdr.ether_vtag)); 2658 sc_if->msk_cdata.msk_tx_cnt++; 2659 MSK_INC(prod, MSK_TX_RING_CNT); 2660 } else { 2661 tx_le->msk_control |= htole32(OP_VLAN | 2662 htons(m->m_pkthdr.ether_vtag)); 2663 } 2664 control |= INS_VLAN; 2665 } 2666 /* Check if we have to handle checksum offload. */ 2667 if (tso == 0 && (m->m_pkthdr.csum_flags & MSK_CSUM_FEATURES) != 0) { 2668 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2669 tx_le->msk_addr = htole32(((tcp_offset + m->m_pkthdr.csum_data) 2670 & 0xffff) | ((uint32_t)tcp_offset << 16)); 2671 tx_le->msk_control = htole32(1 << 16 | (OP_TCPLISW | HW_OWNER)); 2672 control = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM; 2673 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0) 2674 control |= UDPTCP; 2675 sc_if->msk_cdata.msk_tx_cnt++; 2676 MSK_INC(prod, MSK_TX_RING_CNT); 2677 } 2678 2679 si = prod; 2680 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2681 tx_le->msk_addr = htole32(MSK_ADDR_LO(txsegs[0].ds_addr)); 2682 if (tso == 0) 2683 tx_le->msk_control = htole32(txsegs[0].ds_len | control | 2684 OP_PACKET); 2685 else 2686 tx_le->msk_control = htole32(txsegs[0].ds_len | control | 2687 OP_LARGESEND); 2688 sc_if->msk_cdata.msk_tx_cnt++; 2689 MSK_INC(prod, MSK_TX_RING_CNT); 2690 2691 for (i = 1; i < nseg; i++) { 2692 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2693 tx_le->msk_addr = htole32(MSK_ADDR_LO(txsegs[i].ds_addr)); 2694 tx_le->msk_control = htole32(txsegs[i].ds_len | control | 2695 OP_BUFFER | HW_OWNER); 2696 sc_if->msk_cdata.msk_tx_cnt++; 2697 MSK_INC(prod, MSK_TX_RING_CNT); 2698 } 2699 /* Update producer index. */ 2700 sc_if->msk_cdata.msk_tx_prod = prod; 2701 2702 /* Set EOP on the last desciptor. */ 2703 prod = (prod + MSK_TX_RING_CNT - 1) % MSK_TX_RING_CNT; 2704 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2705 tx_le->msk_control |= htole32(EOP); 2706 2707 /* Turn the first descriptor ownership to hardware. */ 2708 tx_le = &sc_if->msk_rdata.msk_tx_ring[si]; 2709 tx_le->msk_control |= htole32(HW_OWNER); 2710 2711 txd = &sc_if->msk_cdata.msk_txdesc[prod]; 2712 map = txd_last->tx_dmamap; 2713 txd_last->tx_dmamap = txd->tx_dmamap; 2714 txd->tx_dmamap = map; 2715 txd->tx_m = m; 2716 2717 /* Sync descriptors. */ 2718 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_tag, map, BUS_DMASYNC_PREWRITE); 2719 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_ring_tag, 2720 sc_if->msk_cdata.msk_tx_ring_map, 2721 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2722 2723 return (0); 2724 } 2725 2726 static void 2727 msk_tx_task(void *arg, int pending) 2728 { 2729 struct ifnet *ifp; 2730 2731 ifp = arg; 2732 msk_start(ifp); 2733 } 2734 2735 static void 2736 msk_start(struct ifnet *ifp) 2737 { 2738 struct msk_if_softc *sc_if; 2739 struct mbuf *m_head; 2740 int enq; 2741 2742 sc_if = ifp->if_softc; 2743 2744 MSK_IF_LOCK(sc_if); 2745 2746 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2747 IFF_DRV_RUNNING || sc_if->msk_link == 0) { 2748 MSK_IF_UNLOCK(sc_if); 2749 return; 2750 } 2751 2752 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 2753 sc_if->msk_cdata.msk_tx_cnt < 2754 (MSK_TX_RING_CNT - MSK_RESERVED_TX_DESC_CNT); ) { 2755 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2756 if (m_head == NULL) 2757 break; 2758 /* 2759 * Pack the data into the transmit ring. If we 2760 * don't have room, set the OACTIVE flag and wait 2761 * for the NIC to drain the ring. 2762 */ 2763 if (msk_encap(sc_if, &m_head) != 0) { 2764 if (m_head == NULL) 2765 break; 2766 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2767 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2768 break; 2769 } 2770 2771 enq++; 2772 /* 2773 * If there's a BPF listener, bounce a copy of this frame 2774 * to him. 2775 */ 2776 ETHER_BPF_MTAP(ifp, m_head); 2777 } 2778 2779 if (enq > 0) { 2780 /* Transmit */ 2781 CSR_WRITE_2(sc_if->msk_softc, 2782 Y2_PREF_Q_ADDR(sc_if->msk_txq, PREF_UNIT_PUT_IDX_REG), 2783 sc_if->msk_cdata.msk_tx_prod); 2784 2785 /* Set a timeout in case the chip goes out to lunch. */ 2786 sc_if->msk_watchdog_timer = MSK_TX_TIMEOUT; 2787 } 2788 2789 MSK_IF_UNLOCK(sc_if); 2790 } 2791 2792 static void 2793 msk_watchdog(struct msk_if_softc *sc_if) 2794 { 2795 struct ifnet *ifp; 2796 uint32_t ridx; 2797 int idx; 2798 2799 MSK_IF_LOCK_ASSERT(sc_if); 2800 2801 if (sc_if->msk_watchdog_timer == 0 || --sc_if->msk_watchdog_timer) 2802 return; 2803 ifp = sc_if->msk_ifp; 2804 if (sc_if->msk_link == 0) { 2805 if (bootverbose) 2806 if_printf(sc_if->msk_ifp, "watchdog timeout " 2807 "(missed link)\n"); 2808 ifp->if_oerrors++; 2809 msk_init_locked(sc_if); 2810 return; 2811 } 2812 2813 /* 2814 * Reclaim first as there is a possibility of losing Tx completion 2815 * interrupts. 2816 */ 2817 ridx = sc_if->msk_port == MSK_PORT_A ? STAT_TXA1_RIDX : STAT_TXA2_RIDX; 2818 idx = CSR_READ_2(sc_if->msk_softc, ridx); 2819 if (sc_if->msk_cdata.msk_tx_cons != idx) { 2820 msk_txeof(sc_if, idx); 2821 if (sc_if->msk_cdata.msk_tx_cnt == 0) { 2822 if_printf(ifp, "watchdog timeout (missed Tx interrupts) " 2823 "-- recovering\n"); 2824 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2825 taskqueue_enqueue(taskqueue_fast, 2826 &sc_if->msk_tx_task); 2827 return; 2828 } 2829 } 2830 2831 if_printf(ifp, "watchdog timeout\n"); 2832 ifp->if_oerrors++; 2833 msk_init_locked(sc_if); 2834 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2835 taskqueue_enqueue(taskqueue_fast, &sc_if->msk_tx_task); 2836 } 2837 2838 static int 2839 mskc_shutdown(device_t dev) 2840 { 2841 struct msk_softc *sc; 2842 int i; 2843 2844 sc = device_get_softc(dev); 2845 MSK_LOCK(sc); 2846 for (i = 0; i < sc->msk_num_port; i++) { 2847 if (sc->msk_if[i] != NULL) 2848 msk_stop(sc->msk_if[i]); 2849 } 2850 2851 /* Disable all interrupts. */ 2852 CSR_WRITE_4(sc, B0_IMSK, 0); 2853 CSR_READ_4(sc, B0_IMSK); 2854 CSR_WRITE_4(sc, B0_HWE_IMSK, 0); 2855 CSR_READ_4(sc, B0_HWE_IMSK); 2856 2857 /* Put hardware reset. */ 2858 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); 2859 2860 MSK_UNLOCK(sc); 2861 return (0); 2862 } 2863 2864 static int 2865 mskc_suspend(device_t dev) 2866 { 2867 struct msk_softc *sc; 2868 int i; 2869 2870 sc = device_get_softc(dev); 2871 2872 MSK_LOCK(sc); 2873 2874 for (i = 0; i < sc->msk_num_port; i++) { 2875 if (sc->msk_if[i] != NULL && sc->msk_if[i]->msk_ifp != NULL && 2876 ((sc->msk_if[i]->msk_ifp->if_drv_flags & 2877 IFF_DRV_RUNNING) != 0)) 2878 msk_stop(sc->msk_if[i]); 2879 } 2880 2881 /* Disable all interrupts. */ 2882 CSR_WRITE_4(sc, B0_IMSK, 0); 2883 CSR_READ_4(sc, B0_IMSK); 2884 CSR_WRITE_4(sc, B0_HWE_IMSK, 0); 2885 CSR_READ_4(sc, B0_HWE_IMSK); 2886 2887 msk_phy_power(sc, MSK_PHY_POWERDOWN); 2888 2889 /* Put hardware reset. */ 2890 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); 2891 sc->msk_suspended = 1; 2892 2893 MSK_UNLOCK(sc); 2894 2895 return (0); 2896 } 2897 2898 static int 2899 mskc_resume(device_t dev) 2900 { 2901 struct msk_softc *sc; 2902 int i; 2903 2904 sc = device_get_softc(dev); 2905 2906 MSK_LOCK(sc); 2907 2908 mskc_reset(sc); 2909 for (i = 0; i < sc->msk_num_port; i++) { 2910 if (sc->msk_if[i] != NULL && sc->msk_if[i]->msk_ifp != NULL && 2911 ((sc->msk_if[i]->msk_ifp->if_flags & IFF_UP) != 0)) 2912 msk_init_locked(sc->msk_if[i]); 2913 } 2914 sc->msk_suspended = 0; 2915 2916 MSK_UNLOCK(sc); 2917 2918 return (0); 2919 } 2920 2921 static void 2922 msk_rxeof(struct msk_if_softc *sc_if, uint32_t status, int len) 2923 { 2924 struct mbuf *m; 2925 struct ifnet *ifp; 2926 struct msk_rxdesc *rxd; 2927 int cons, rxlen; 2928 2929 ifp = sc_if->msk_ifp; 2930 2931 MSK_IF_LOCK_ASSERT(sc_if); 2932 2933 cons = sc_if->msk_cdata.msk_rx_cons; 2934 do { 2935 rxlen = status >> 16; 2936 if ((status & GMR_FS_VLAN) != 0 && 2937 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 2938 rxlen -= ETHER_VLAN_ENCAP_LEN; 2939 if (len > sc_if->msk_framesize || 2940 ((status & GMR_FS_ANY_ERR) != 0) || 2941 ((status & GMR_FS_RX_OK) == 0) || (rxlen != len)) { 2942 /* Don't count flow-control packet as errors. */ 2943 if ((status & GMR_FS_GOOD_FC) == 0) 2944 ifp->if_ierrors++; 2945 msk_discard_rxbuf(sc_if, cons); 2946 break; 2947 } 2948 rxd = &sc_if->msk_cdata.msk_rxdesc[cons]; 2949 m = rxd->rx_m; 2950 if (msk_newbuf(sc_if, cons) != 0) { 2951 ifp->if_iqdrops++; 2952 /* Reuse old buffer. */ 2953 msk_discard_rxbuf(sc_if, cons); 2954 break; 2955 } 2956 m->m_pkthdr.rcvif = ifp; 2957 m->m_pkthdr.len = m->m_len = len; 2958 ifp->if_ipackets++; 2959 /* Check for VLAN tagged packets. */ 2960 if ((status & GMR_FS_VLAN) != 0 && 2961 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) { 2962 m->m_pkthdr.ether_vtag = sc_if->msk_vtag; 2963 m->m_flags |= M_VLANTAG; 2964 } 2965 MSK_IF_UNLOCK(sc_if); 2966 (*ifp->if_input)(ifp, m); 2967 MSK_IF_LOCK(sc_if); 2968 } while (0); 2969 2970 MSK_INC(sc_if->msk_cdata.msk_rx_cons, MSK_RX_RING_CNT); 2971 MSK_INC(sc_if->msk_cdata.msk_rx_prod, MSK_RX_RING_CNT); 2972 } 2973 2974 static void 2975 msk_jumbo_rxeof(struct msk_if_softc *sc_if, uint32_t status, int len) 2976 { 2977 struct mbuf *m; 2978 struct ifnet *ifp; 2979 struct msk_rxdesc *jrxd; 2980 int cons, rxlen; 2981 2982 ifp = sc_if->msk_ifp; 2983 2984 MSK_IF_LOCK_ASSERT(sc_if); 2985 2986 cons = sc_if->msk_cdata.msk_rx_cons; 2987 do { 2988 rxlen = status >> 16; 2989 if ((status & GMR_FS_VLAN) != 0 && 2990 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 2991 rxlen -= ETHER_VLAN_ENCAP_LEN; 2992 if (len > sc_if->msk_framesize || 2993 ((status & GMR_FS_ANY_ERR) != 0) || 2994 ((status & GMR_FS_RX_OK) == 0) || (rxlen != len)) { 2995 /* Don't count flow-control packet as errors. */ 2996 if ((status & GMR_FS_GOOD_FC) == 0) 2997 ifp->if_ierrors++; 2998 msk_discard_jumbo_rxbuf(sc_if, cons); 2999 break; 3000 } 3001 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[cons]; 3002 m = jrxd->rx_m; 3003 if (msk_jumbo_newbuf(sc_if, cons) != 0) { 3004 ifp->if_iqdrops++; 3005 /* Reuse old buffer. */ 3006 msk_discard_jumbo_rxbuf(sc_if, cons); 3007 break; 3008 } 3009 m->m_pkthdr.rcvif = ifp; 3010 m->m_pkthdr.len = m->m_len = len; 3011 ifp->if_ipackets++; 3012 /* Check for VLAN tagged packets. */ 3013 if ((status & GMR_FS_VLAN) != 0 && 3014 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) { 3015 m->m_pkthdr.ether_vtag = sc_if->msk_vtag; 3016 m->m_flags |= M_VLANTAG; 3017 } 3018 MSK_IF_UNLOCK(sc_if); 3019 (*ifp->if_input)(ifp, m); 3020 MSK_IF_LOCK(sc_if); 3021 } while (0); 3022 3023 MSK_INC(sc_if->msk_cdata.msk_rx_cons, MSK_JUMBO_RX_RING_CNT); 3024 MSK_INC(sc_if->msk_cdata.msk_rx_prod, MSK_JUMBO_RX_RING_CNT); 3025 } 3026 3027 static void 3028 msk_txeof(struct msk_if_softc *sc_if, int idx) 3029 { 3030 struct msk_txdesc *txd; 3031 struct msk_tx_desc *cur_tx; 3032 struct ifnet *ifp; 3033 uint32_t control; 3034 int cons, prog; 3035 3036 MSK_IF_LOCK_ASSERT(sc_if); 3037 3038 ifp = sc_if->msk_ifp; 3039 3040 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_ring_tag, 3041 sc_if->msk_cdata.msk_tx_ring_map, 3042 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3043 /* 3044 * Go through our tx ring and free mbufs for those 3045 * frames that have been sent. 3046 */ 3047 cons = sc_if->msk_cdata.msk_tx_cons; 3048 prog = 0; 3049 for (; cons != idx; MSK_INC(cons, MSK_TX_RING_CNT)) { 3050 if (sc_if->msk_cdata.msk_tx_cnt <= 0) 3051 break; 3052 prog++; 3053 cur_tx = &sc_if->msk_rdata.msk_tx_ring[cons]; 3054 control = le32toh(cur_tx->msk_control); 3055 sc_if->msk_cdata.msk_tx_cnt--; 3056 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3057 if ((control & EOP) == 0) 3058 continue; 3059 txd = &sc_if->msk_cdata.msk_txdesc[cons]; 3060 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_tag, txd->tx_dmamap, 3061 BUS_DMASYNC_POSTWRITE); 3062 bus_dmamap_unload(sc_if->msk_cdata.msk_tx_tag, txd->tx_dmamap); 3063 3064 ifp->if_opackets++; 3065 KASSERT(txd->tx_m != NULL, ("%s: freeing NULL mbuf!", 3066 __func__)); 3067 m_freem(txd->tx_m); 3068 txd->tx_m = NULL; 3069 } 3070 3071 if (prog > 0) { 3072 sc_if->msk_cdata.msk_tx_cons = cons; 3073 if (sc_if->msk_cdata.msk_tx_cnt == 0) 3074 sc_if->msk_watchdog_timer = 0; 3075 /* No need to sync LEs as we didn't update LEs. */ 3076 } 3077 } 3078 3079 static void 3080 msk_tick(void *xsc_if) 3081 { 3082 struct msk_if_softc *sc_if; 3083 struct mii_data *mii; 3084 3085 sc_if = xsc_if; 3086 3087 MSK_IF_LOCK_ASSERT(sc_if); 3088 3089 mii = device_get_softc(sc_if->msk_miibus); 3090 3091 mii_tick(mii); 3092 msk_watchdog(sc_if); 3093 callout_reset(&sc_if->msk_tick_ch, hz, msk_tick, sc_if); 3094 } 3095 3096 static void 3097 msk_intr_phy(struct msk_if_softc *sc_if) 3098 { 3099 uint16_t status; 3100 3101 msk_phy_readreg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_STAT); 3102 status = msk_phy_readreg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_STAT); 3103 /* Handle FIFO Underrun/Overflow? */ 3104 if ((status & PHY_M_IS_FIFO_ERROR)) 3105 device_printf(sc_if->msk_if_dev, 3106 "PHY FIFO underrun/overflow.\n"); 3107 } 3108 3109 static void 3110 msk_intr_gmac(struct msk_if_softc *sc_if) 3111 { 3112 struct msk_softc *sc; 3113 uint8_t status; 3114 3115 sc = sc_if->msk_softc; 3116 status = CSR_READ_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_SRC)); 3117 3118 /* GMAC Rx FIFO overrun. */ 3119 if ((status & GM_IS_RX_FF_OR) != 0) { 3120 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), 3121 GMF_CLI_RX_FO); 3122 device_printf(sc_if->msk_if_dev, "Rx FIFO overrun!\n"); 3123 } 3124 /* GMAC Tx FIFO underrun. */ 3125 if ((status & GM_IS_TX_FF_UR) != 0) { 3126 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 3127 GMF_CLI_TX_FU); 3128 device_printf(sc_if->msk_if_dev, "Tx FIFO underrun!\n"); 3129 /* 3130 * XXX 3131 * In case of Tx underrun, we may need to flush/reset 3132 * Tx MAC but that would also require resynchronization 3133 * with status LEs. Reintializing status LEs would 3134 * affect other port in dual MAC configuration so it 3135 * should be avoided as possible as we can. 3136 * Due to lack of documentation it's all vague guess but 3137 * it needs more investigation. 3138 */ 3139 } 3140 } 3141 3142 static void 3143 msk_handle_hwerr(struct msk_if_softc *sc_if, uint32_t status) 3144 { 3145 struct msk_softc *sc; 3146 3147 sc = sc_if->msk_softc; 3148 if ((status & Y2_IS_PAR_RD1) != 0) { 3149 device_printf(sc_if->msk_if_dev, 3150 "RAM buffer read parity error\n"); 3151 /* Clear IRQ. */ 3152 CSR_WRITE_2(sc, SELECT_RAM_BUFFER(sc_if->msk_port, B3_RI_CTRL), 3153 RI_CLR_RD_PERR); 3154 } 3155 if ((status & Y2_IS_PAR_WR1) != 0) { 3156 device_printf(sc_if->msk_if_dev, 3157 "RAM buffer write parity error\n"); 3158 /* Clear IRQ. */ 3159 CSR_WRITE_2(sc, SELECT_RAM_BUFFER(sc_if->msk_port, B3_RI_CTRL), 3160 RI_CLR_WR_PERR); 3161 } 3162 if ((status & Y2_IS_PAR_MAC1) != 0) { 3163 device_printf(sc_if->msk_if_dev, "Tx MAC parity error\n"); 3164 /* Clear IRQ. */ 3165 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 3166 GMF_CLI_TX_PE); 3167 } 3168 if ((status & Y2_IS_PAR_RX1) != 0) { 3169 device_printf(sc_if->msk_if_dev, "Rx parity error\n"); 3170 /* Clear IRQ. */ 3171 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_CLR_IRQ_PAR); 3172 } 3173 if ((status & (Y2_IS_TCP_TXS1 | Y2_IS_TCP_TXA1)) != 0) { 3174 device_printf(sc_if->msk_if_dev, "TCP segmentation error\n"); 3175 /* Clear IRQ. */ 3176 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_CLR_IRQ_TCP); 3177 } 3178 } 3179 3180 static void 3181 msk_intr_hwerr(struct msk_softc *sc) 3182 { 3183 uint32_t status; 3184 uint32_t tlphead[4]; 3185 3186 status = CSR_READ_4(sc, B0_HWE_ISRC); 3187 /* Time Stamp timer overflow. */ 3188 if ((status & Y2_IS_TIST_OV) != 0) 3189 CSR_WRITE_1(sc, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ); 3190 if ((status & Y2_IS_PCI_NEXP) != 0) { 3191 /* 3192 * PCI Express Error occured which is not described in PEX 3193 * spec. 3194 * This error is also mapped either to Master Abort( 3195 * Y2_IS_MST_ERR) or Target Abort (Y2_IS_IRQ_STAT) bit and 3196 * can only be cleared there. 3197 */ 3198 device_printf(sc->msk_dev, 3199 "PCI Express protocol violation error\n"); 3200 } 3201 3202 if ((status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) != 0) { 3203 uint16_t v16; 3204 3205 if ((status & Y2_IS_MST_ERR) != 0) 3206 device_printf(sc->msk_dev, 3207 "unexpected IRQ Status error\n"); 3208 else 3209 device_printf(sc->msk_dev, 3210 "unexpected IRQ Master error\n"); 3211 /* Reset all bits in the PCI status register. */ 3212 v16 = pci_read_config(sc->msk_dev, PCIR_STATUS, 2); 3213 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON); 3214 pci_write_config(sc->msk_dev, PCIR_STATUS, v16 | 3215 PCIM_STATUS_PERR | PCIM_STATUS_SERR | PCIM_STATUS_RMABORT | 3216 PCIM_STATUS_RTABORT | PCIM_STATUS_PERRREPORT, 2); 3217 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 3218 } 3219 3220 /* Check for PCI Express Uncorrectable Error. */ 3221 if ((status & Y2_IS_PCI_EXP) != 0) { 3222 uint32_t v32; 3223 3224 /* 3225 * On PCI Express bus bridges are called root complexes (RC). 3226 * PCI Express errors are recognized by the root complex too, 3227 * which requests the system to handle the problem. After 3228 * error occurence it may be that no access to the adapter 3229 * may be performed any longer. 3230 */ 3231 3232 v32 = CSR_PCI_READ_4(sc, PEX_UNC_ERR_STAT); 3233 if ((v32 & PEX_UNSUP_REQ) != 0) { 3234 /* Ignore unsupported request error. */ 3235 device_printf(sc->msk_dev, 3236 "Uncorrectable PCI Express error\n"); 3237 } 3238 if ((v32 & (PEX_FATAL_ERRORS | PEX_POIS_TLP)) != 0) { 3239 int i; 3240 3241 /* Get TLP header form Log Registers. */ 3242 for (i = 0; i < 4; i++) 3243 tlphead[i] = CSR_PCI_READ_4(sc, 3244 PEX_HEADER_LOG + i * 4); 3245 /* Check for vendor defined broadcast message. */ 3246 if (!(tlphead[0] == 0x73004001 && tlphead[1] == 0x7f)) { 3247 sc->msk_intrhwemask &= ~Y2_IS_PCI_EXP; 3248 CSR_WRITE_4(sc, B0_HWE_IMSK, 3249 sc->msk_intrhwemask); 3250 CSR_READ_4(sc, B0_HWE_IMSK); 3251 } 3252 } 3253 /* Clear the interrupt. */ 3254 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON); 3255 CSR_PCI_WRITE_4(sc, PEX_UNC_ERR_STAT, 0xffffffff); 3256 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 3257 } 3258 3259 if ((status & Y2_HWE_L1_MASK) != 0 && sc->msk_if[MSK_PORT_A] != NULL) 3260 msk_handle_hwerr(sc->msk_if[MSK_PORT_A], status); 3261 if ((status & Y2_HWE_L2_MASK) != 0 && sc->msk_if[MSK_PORT_B] != NULL) 3262 msk_handle_hwerr(sc->msk_if[MSK_PORT_B], status >> 8); 3263 } 3264 3265 static __inline void 3266 msk_rxput(struct msk_if_softc *sc_if) 3267 { 3268 struct msk_softc *sc; 3269 3270 sc = sc_if->msk_softc; 3271 if (sc_if->msk_framesize >(MCLBYTES - ETHER_HDR_LEN)) 3272 bus_dmamap_sync( 3273 sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 3274 sc_if->msk_cdata.msk_jumbo_rx_ring_map, 3275 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3276 else 3277 bus_dmamap_sync( 3278 sc_if->msk_cdata.msk_rx_ring_tag, 3279 sc_if->msk_cdata.msk_rx_ring_map, 3280 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3281 CSR_WRITE_2(sc, Y2_PREF_Q_ADDR(sc_if->msk_rxq, 3282 PREF_UNIT_PUT_IDX_REG), sc_if->msk_cdata.msk_rx_prod); 3283 } 3284 3285 static int 3286 msk_handle_events(struct msk_softc *sc) 3287 { 3288 struct msk_if_softc *sc_if; 3289 int rxput[2]; 3290 struct msk_stat_desc *sd; 3291 uint32_t control, status; 3292 int cons, idx, len, port, rxprog; 3293 3294 idx = CSR_READ_2(sc, STAT_PUT_IDX); 3295 if (idx == sc->msk_stat_cons) 3296 return (0); 3297 3298 /* Sync status LEs. */ 3299 bus_dmamap_sync(sc->msk_stat_tag, sc->msk_stat_map, 3300 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3301 /* XXX Sync Rx LEs here. */ 3302 3303 rxput[MSK_PORT_A] = rxput[MSK_PORT_B] = 0; 3304 3305 rxprog = 0; 3306 for (cons = sc->msk_stat_cons; cons != idx;) { 3307 sd = &sc->msk_stat_ring[cons]; 3308 control = le32toh(sd->msk_control); 3309 if ((control & HW_OWNER) == 0) 3310 break; 3311 /* 3312 * Marvell's FreeBSD driver updates status LE after clearing 3313 * HW_OWNER. However we don't have a way to sync single LE 3314 * with bus_dma(9) API. bus_dma(9) provides a way to sync 3315 * an entire DMA map. So don't sync LE until we have a better 3316 * way to sync LEs. 3317 */ 3318 control &= ~HW_OWNER; 3319 sd->msk_control = htole32(control); 3320 status = le32toh(sd->msk_status); 3321 len = control & STLE_LEN_MASK; 3322 port = (control >> 16) & 0x01; 3323 sc_if = sc->msk_if[port]; 3324 if (sc_if == NULL) { 3325 device_printf(sc->msk_dev, "invalid port opcode " 3326 "0x%08x\n", control & STLE_OP_MASK); 3327 continue; 3328 } 3329 3330 switch (control & STLE_OP_MASK) { 3331 case OP_RXVLAN: 3332 sc_if->msk_vtag = ntohs(len); 3333 break; 3334 case OP_RXCHKSVLAN: 3335 sc_if->msk_vtag = ntohs(len); 3336 break; 3337 case OP_RXSTAT: 3338 if (sc_if->msk_framesize > (MCLBYTES - ETHER_HDR_LEN)) 3339 msk_jumbo_rxeof(sc_if, status, len); 3340 else 3341 msk_rxeof(sc_if, status, len); 3342 rxprog++; 3343 /* 3344 * Because there is no way to sync single Rx LE 3345 * put the DMA sync operation off until the end of 3346 * event processing. 3347 */ 3348 rxput[port]++; 3349 /* Update prefetch unit if we've passed water mark. */ 3350 if (rxput[port] >= sc_if->msk_cdata.msk_rx_putwm) { 3351 msk_rxput(sc_if); 3352 rxput[port] = 0; 3353 } 3354 break; 3355 case OP_TXINDEXLE: 3356 if (sc->msk_if[MSK_PORT_A] != NULL) 3357 msk_txeof(sc->msk_if[MSK_PORT_A], 3358 status & STLE_TXA1_MSKL); 3359 if (sc->msk_if[MSK_PORT_B] != NULL) 3360 msk_txeof(sc->msk_if[MSK_PORT_B], 3361 ((status & STLE_TXA2_MSKL) >> 3362 STLE_TXA2_SHIFTL) | 3363 ((len & STLE_TXA2_MSKH) << 3364 STLE_TXA2_SHIFTH)); 3365 break; 3366 default: 3367 device_printf(sc->msk_dev, "unhandled opcode 0x%08x\n", 3368 control & STLE_OP_MASK); 3369 break; 3370 } 3371 MSK_INC(cons, MSK_STAT_RING_CNT); 3372 if (rxprog > sc->msk_process_limit) 3373 break; 3374 } 3375 3376 sc->msk_stat_cons = cons; 3377 /* XXX We should sync status LEs here. See above notes. */ 3378 3379 if (rxput[MSK_PORT_A] > 0) 3380 msk_rxput(sc->msk_if[MSK_PORT_A]); 3381 if (rxput[MSK_PORT_B] > 0) 3382 msk_rxput(sc->msk_if[MSK_PORT_B]); 3383 3384 return (sc->msk_stat_cons != CSR_READ_2(sc, STAT_PUT_IDX)); 3385 } 3386 3387 /* Legacy interrupt handler for shared interrupt. */ 3388 static void 3389 msk_legacy_intr(void *xsc) 3390 { 3391 struct msk_softc *sc; 3392 struct msk_if_softc *sc_if0, *sc_if1; 3393 struct ifnet *ifp0, *ifp1; 3394 uint32_t status; 3395 3396 sc = xsc; 3397 MSK_LOCK(sc); 3398 3399 /* Reading B0_Y2_SP_ISRC2 masks further interrupts. */ 3400 status = CSR_READ_4(sc, B0_Y2_SP_ISRC2); 3401 if (status == 0 || status == 0xffffffff || sc->msk_suspended != 0 || 3402 (status & sc->msk_intrmask) == 0) { 3403 CSR_WRITE_4(sc, B0_Y2_SP_ICR, 2); 3404 return; 3405 } 3406 3407 sc_if0 = sc->msk_if[MSK_PORT_A]; 3408 sc_if1 = sc->msk_if[MSK_PORT_B]; 3409 ifp0 = ifp1 = NULL; 3410 if (sc_if0 != NULL) 3411 ifp0 = sc_if0->msk_ifp; 3412 if (sc_if1 != NULL) 3413 ifp1 = sc_if1->msk_ifp; 3414 3415 if ((status & Y2_IS_IRQ_PHY1) != 0 && sc_if0 != NULL) 3416 msk_intr_phy(sc_if0); 3417 if ((status & Y2_IS_IRQ_PHY2) != 0 && sc_if1 != NULL) 3418 msk_intr_phy(sc_if1); 3419 if ((status & Y2_IS_IRQ_MAC1) != 0 && sc_if0 != NULL) 3420 msk_intr_gmac(sc_if0); 3421 if ((status & Y2_IS_IRQ_MAC2) != 0 && sc_if1 != NULL) 3422 msk_intr_gmac(sc_if1); 3423 if ((status & (Y2_IS_CHK_RX1 | Y2_IS_CHK_RX2)) != 0) { 3424 device_printf(sc->msk_dev, "Rx descriptor error\n"); 3425 sc->msk_intrmask &= ~(Y2_IS_CHK_RX1 | Y2_IS_CHK_RX2); 3426 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask); 3427 CSR_READ_4(sc, B0_IMSK); 3428 } 3429 if ((status & (Y2_IS_CHK_TXA1 | Y2_IS_CHK_TXA2)) != 0) { 3430 device_printf(sc->msk_dev, "Tx descriptor error\n"); 3431 sc->msk_intrmask &= ~(Y2_IS_CHK_TXA1 | Y2_IS_CHK_TXA2); 3432 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask); 3433 CSR_READ_4(sc, B0_IMSK); 3434 } 3435 if ((status & Y2_IS_HW_ERR) != 0) 3436 msk_intr_hwerr(sc); 3437 3438 while (msk_handle_events(sc) != 0) 3439 ; 3440 if ((status & Y2_IS_STAT_BMU) != 0) 3441 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_CLR_IRQ); 3442 3443 /* Reenable interrupts. */ 3444 CSR_WRITE_4(sc, B0_Y2_SP_ICR, 2); 3445 3446 if (ifp0 != NULL && (ifp0->if_drv_flags & IFF_DRV_RUNNING) != 0 && 3447 !IFQ_DRV_IS_EMPTY(&ifp0->if_snd)) 3448 taskqueue_enqueue(taskqueue_fast, &sc_if0->msk_tx_task); 3449 if (ifp1 != NULL && (ifp1->if_drv_flags & IFF_DRV_RUNNING) != 0 && 3450 !IFQ_DRV_IS_EMPTY(&ifp1->if_snd)) 3451 taskqueue_enqueue(taskqueue_fast, &sc_if1->msk_tx_task); 3452 3453 MSK_UNLOCK(sc); 3454 } 3455 3456 static int 3457 msk_intr(void *xsc) 3458 { 3459 struct msk_softc *sc; 3460 uint32_t status; 3461 3462 sc = xsc; 3463 status = CSR_READ_4(sc, B0_Y2_SP_ISRC2); 3464 /* Reading B0_Y2_SP_ISRC2 masks further interrupts. */ 3465 if (status == 0 || status == 0xffffffff) { 3466 CSR_WRITE_4(sc, B0_Y2_SP_ICR, 2); 3467 return (FILTER_STRAY); 3468 } 3469 3470 taskqueue_enqueue(sc->msk_tq, &sc->msk_int_task); 3471 return (FILTER_HANDLED); 3472 } 3473 3474 static void 3475 msk_int_task(void *arg, int pending) 3476 { 3477 struct msk_softc *sc; 3478 struct msk_if_softc *sc_if0, *sc_if1; 3479 struct ifnet *ifp0, *ifp1; 3480 uint32_t status; 3481 int domore; 3482 3483 sc = arg; 3484 MSK_LOCK(sc); 3485 3486 /* Get interrupt source. */ 3487 status = CSR_READ_4(sc, B0_ISRC); 3488 if (status == 0 || status == 0xffffffff || sc->msk_suspended != 0 || 3489 (status & sc->msk_intrmask) == 0) 3490 goto done; 3491 3492 sc_if0 = sc->msk_if[MSK_PORT_A]; 3493 sc_if1 = sc->msk_if[MSK_PORT_B]; 3494 ifp0 = ifp1 = NULL; 3495 if (sc_if0 != NULL) 3496 ifp0 = sc_if0->msk_ifp; 3497 if (sc_if1 != NULL) 3498 ifp1 = sc_if1->msk_ifp; 3499 3500 if ((status & Y2_IS_IRQ_PHY1) != 0 && sc_if0 != NULL) 3501 msk_intr_phy(sc_if0); 3502 if ((status & Y2_IS_IRQ_PHY2) != 0 && sc_if1 != NULL) 3503 msk_intr_phy(sc_if1); 3504 if ((status & Y2_IS_IRQ_MAC1) != 0 && sc_if0 != NULL) 3505 msk_intr_gmac(sc_if0); 3506 if ((status & Y2_IS_IRQ_MAC2) != 0 && sc_if1 != NULL) 3507 msk_intr_gmac(sc_if1); 3508 if ((status & (Y2_IS_CHK_RX1 | Y2_IS_CHK_RX2)) != 0) { 3509 device_printf(sc->msk_dev, "Rx descriptor error\n"); 3510 sc->msk_intrmask &= ~(Y2_IS_CHK_RX1 | Y2_IS_CHK_RX2); 3511 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask); 3512 CSR_READ_4(sc, B0_IMSK); 3513 } 3514 if ((status & (Y2_IS_CHK_TXA1 | Y2_IS_CHK_TXA2)) != 0) { 3515 device_printf(sc->msk_dev, "Tx descriptor error\n"); 3516 sc->msk_intrmask &= ~(Y2_IS_CHK_TXA1 | Y2_IS_CHK_TXA2); 3517 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask); 3518 CSR_READ_4(sc, B0_IMSK); 3519 } 3520 if ((status & Y2_IS_HW_ERR) != 0) 3521 msk_intr_hwerr(sc); 3522 3523 domore = msk_handle_events(sc); 3524 if ((status & Y2_IS_STAT_BMU) != 0) 3525 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_CLR_IRQ); 3526 3527 if (ifp0 != NULL && (ifp0->if_drv_flags & IFF_DRV_RUNNING) != 0 && 3528 !IFQ_DRV_IS_EMPTY(&ifp0->if_snd)) 3529 taskqueue_enqueue(taskqueue_fast, &sc_if0->msk_tx_task); 3530 if (ifp1 != NULL && (ifp1->if_drv_flags & IFF_DRV_RUNNING) != 0 && 3531 !IFQ_DRV_IS_EMPTY(&ifp1->if_snd)) 3532 taskqueue_enqueue(taskqueue_fast, &sc_if1->msk_tx_task); 3533 3534 if (domore > 0) { 3535 taskqueue_enqueue(sc->msk_tq, &sc->msk_int_task); 3536 MSK_UNLOCK(sc); 3537 return; 3538 } 3539 done: 3540 MSK_UNLOCK(sc); 3541 3542 /* Reenable interrupts. */ 3543 CSR_WRITE_4(sc, B0_Y2_SP_ICR, 2); 3544 } 3545 3546 static void 3547 msk_init(void *xsc) 3548 { 3549 struct msk_if_softc *sc_if = xsc; 3550 3551 MSK_IF_LOCK(sc_if); 3552 msk_init_locked(sc_if); 3553 MSK_IF_UNLOCK(sc_if); 3554 } 3555 3556 static void 3557 msk_init_locked(struct msk_if_softc *sc_if) 3558 { 3559 struct msk_softc *sc; 3560 struct ifnet *ifp; 3561 struct mii_data *mii; 3562 uint16_t eaddr[ETHER_ADDR_LEN / 2]; 3563 uint16_t gmac; 3564 int error, i; 3565 3566 MSK_IF_LOCK_ASSERT(sc_if); 3567 3568 ifp = sc_if->msk_ifp; 3569 sc = sc_if->msk_softc; 3570 mii = device_get_softc(sc_if->msk_miibus); 3571 3572 error = 0; 3573 /* Cancel pending I/O and free all Rx/Tx buffers. */ 3574 msk_stop(sc_if); 3575 3576 sc_if->msk_framesize = ifp->if_mtu + ETHER_HDR_LEN + 3577 ETHER_VLAN_ENCAP_LEN; 3578 if (sc_if->msk_framesize > MSK_MAX_FRAMELEN && 3579 sc_if->msk_softc->msk_hw_id == CHIP_ID_YUKON_EC_U) { 3580 /* 3581 * In Yukon EC Ultra, TSO & checksum offload is not 3582 * supported for jumbo frame. 3583 */ 3584 ifp->if_hwassist &= ~(MSK_CSUM_FEATURES | CSUM_TSO); 3585 ifp->if_capenable &= ~(IFCAP_TSO4 | IFCAP_TXCSUM); 3586 } 3587 3588 /* 3589 * Initialize GMAC first. 3590 * Without this initialization, Rx MAC did not work as expected 3591 * and Rx MAC garbled status LEs and it resulted in out-of-order 3592 * or duplicated frame delivery which in turn showed very poor 3593 * Rx performance.(I had to write a packet analysis code that 3594 * could be embeded in driver to diagnose this issue.) 3595 * I've spent almost 2 months to fix this issue. If I have had 3596 * datasheet for Yukon II I wouldn't have encountered this. :-( 3597 */ 3598 gmac = GM_GPCR_SPEED_100 | GM_GPCR_SPEED_1000 | GM_GPCR_DUP_FULL; 3599 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, gmac); 3600 3601 /* Dummy read the Interrupt Source Register. */ 3602 CSR_READ_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_SRC)); 3603 3604 /* Set MIB Clear Counter Mode. */ 3605 gmac = GMAC_READ_2(sc, sc_if->msk_port, GM_PHY_ADDR); 3606 GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac | GM_PAR_MIB_CLR); 3607 /* Read all MIB Counters with Clear Mode set. */ 3608 for (i = 0; i < GM_MIB_CNT_SIZE; i++) 3609 GMAC_READ_2(sc, sc_if->msk_port, GM_MIB_CNT_BASE + 8 * i); 3610 /* Clear MIB Clear Counter Mode. */ 3611 gmac &= ~GM_PAR_MIB_CLR; 3612 GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac); 3613 3614 /* Disable FCS. */ 3615 GMAC_WRITE_2(sc, sc_if->msk_port, GM_RX_CTRL, GM_RXCR_CRC_DIS); 3616 3617 /* Setup Transmit Control Register. */ 3618 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF)); 3619 3620 /* Setup Transmit Flow Control Register. */ 3621 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_FLOW_CTRL, 0xffff); 3622 3623 /* Setup Transmit Parameter Register. */ 3624 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_PARAM, 3625 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) | TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) | 3626 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) | TX_BACK_OFF_LIM(TX_BOF_LIM_DEF)); 3627 3628 gmac = DATA_BLIND_VAL(DATA_BLIND_DEF) | 3629 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF); 3630 3631 if (sc_if->msk_framesize > MSK_MAX_FRAMELEN) 3632 gmac |= GM_SMOD_JUMBO_ENA; 3633 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SERIAL_MODE, gmac); 3634 3635 /* Set station address. */ 3636 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN); 3637 for (i = 0; i < ETHER_ADDR_LEN /2; i++) 3638 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_1L + i * 4, 3639 eaddr[i]); 3640 for (i = 0; i < ETHER_ADDR_LEN /2; i++) 3641 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_2L + i * 4, 3642 eaddr[i]); 3643 3644 /* Disable interrupts for counter overflows. */ 3645 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_IRQ_MSK, 0); 3646 GMAC_WRITE_2(sc, sc_if->msk_port, GM_RX_IRQ_MSK, 0); 3647 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TR_IRQ_MSK, 0); 3648 3649 /* Configure Rx MAC FIFO. */ 3650 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), GMF_RST_SET); 3651 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), GMF_RST_CLR); 3652 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), 3653 GMF_OPER_ON | GMF_RX_F_FL_ON); 3654 3655 /* Set promiscuous mode. */ 3656 msk_setpromisc(sc_if); 3657 3658 /* Set multicast filter. */ 3659 msk_setmulti(sc_if); 3660 3661 /* Flush Rx MAC FIFO on any flow control or error. */ 3662 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_FL_MSK), 3663 GMR_FS_ANY_ERR); 3664 3665 /* 3666 * Set Rx FIFO flush threshold to 64 bytes + 1 FIFO word 3667 * due to hardware hang on receipt of pause frames. 3668 */ 3669 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_FL_THR), 3670 RX_GMF_FL_THR_DEF + 1); 3671 3672 /* Configure Tx MAC FIFO. */ 3673 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_RST_SET); 3674 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_RST_CLR); 3675 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_OPER_ON); 3676 3677 /* Configure hardware VLAN tag insertion/stripping. */ 3678 msk_setvlan(sc_if, ifp); 3679 3680 if (sc->msk_hw_id == CHIP_ID_YUKON_EC_U) { 3681 /* Set Rx Pause threshould. */ 3682 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, RX_GMF_LP_THR), 3683 MSK_ECU_LLPP); 3684 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, RX_GMF_UP_THR), 3685 MSK_ECU_ULPP); 3686 if (sc_if->msk_framesize > MSK_MAX_FRAMELEN) { 3687 /* 3688 * Set Tx GMAC FIFO Almost Empty Threshold. 3689 */ 3690 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_AE_THR), 3691 MSK_ECU_JUMBO_WM << 16 | MSK_ECU_AE_THR); 3692 /* Disable Store & Forward mode for Tx. */ 3693 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 3694 TX_JUMBO_ENA | TX_STFW_DIS); 3695 } else { 3696 /* Enable Store & Forward mode for Tx. */ 3697 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 3698 TX_JUMBO_DIS | TX_STFW_ENA); 3699 } 3700 } 3701 3702 /* 3703 * Disable Force Sync bit and Alloc bit in Tx RAM interface 3704 * arbiter as we don't use Sync Tx queue. 3705 */ 3706 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, TXA_CTRL), 3707 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC); 3708 /* Enable the RAM Interface Arbiter. */ 3709 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, TXA_CTRL), TXA_ENA_ARB); 3710 3711 /* Setup RAM buffer. */ 3712 msk_set_rambuffer(sc_if); 3713 3714 /* Disable Tx sync Queue. */ 3715 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txsq, RB_CTRL), RB_RST_SET); 3716 3717 /* Setup Tx Queue Bus Memory Interface. */ 3718 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_CLR_RESET); 3719 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_OPER_INIT); 3720 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_FIFO_OP_ON); 3721 CSR_WRITE_2(sc, Q_ADDR(sc_if->msk_txq, Q_WM), MSK_BMU_TX_WM); 3722 if (sc->msk_hw_id == CHIP_ID_YUKON_EC_U && 3723 sc->msk_hw_rev == CHIP_REV_YU_EC_U_A0) { 3724 /* Fix for Yukon-EC Ultra: set BMU FIFO level */ 3725 CSR_WRITE_2(sc, Q_ADDR(sc_if->msk_txq, Q_AL), MSK_ECU_TXFF_LEV); 3726 } 3727 3728 /* Setup Rx Queue Bus Memory Interface. */ 3729 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_CLR_RESET); 3730 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_OPER_INIT); 3731 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_FIFO_OP_ON); 3732 CSR_WRITE_2(sc, Q_ADDR(sc_if->msk_rxq, Q_WM), MSK_BMU_RX_WM); 3733 if (sc->msk_hw_id == CHIP_ID_YUKON_EC_U && 3734 sc->msk_hw_rev >= CHIP_REV_YU_EC_U_A1) { 3735 /* MAC Rx RAM Read is controlled by hardware. */ 3736 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_F), F_M_RX_RAM_DIS); 3737 } 3738 3739 msk_set_prefetch(sc, sc_if->msk_txq, 3740 sc_if->msk_rdata.msk_tx_ring_paddr, MSK_TX_RING_CNT - 1); 3741 msk_init_tx_ring(sc_if); 3742 3743 /* Disable Rx checksum offload and RSS hash. */ 3744 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), 3745 BMU_DIS_RX_CHKSUM | BMU_DIS_RX_RSS_HASH); 3746 if (sc_if->msk_framesize > (MCLBYTES - ETHER_HDR_LEN)) { 3747 msk_set_prefetch(sc, sc_if->msk_rxq, 3748 sc_if->msk_rdata.msk_jumbo_rx_ring_paddr, 3749 MSK_JUMBO_RX_RING_CNT - 1); 3750 error = msk_init_jumbo_rx_ring(sc_if); 3751 } else { 3752 msk_set_prefetch(sc, sc_if->msk_rxq, 3753 sc_if->msk_rdata.msk_rx_ring_paddr, 3754 MSK_RX_RING_CNT - 1); 3755 error = msk_init_rx_ring(sc_if); 3756 } 3757 if (error != 0) { 3758 device_printf(sc_if->msk_if_dev, 3759 "initialization failed: no memory for Rx buffers\n"); 3760 msk_stop(sc_if); 3761 return; 3762 } 3763 3764 /* Configure interrupt handling. */ 3765 if (sc_if->msk_port == MSK_PORT_A) { 3766 sc->msk_intrmask |= Y2_IS_PORT_A; 3767 sc->msk_intrhwemask |= Y2_HWE_L1_MASK; 3768 } else { 3769 sc->msk_intrmask |= Y2_IS_PORT_B; 3770 sc->msk_intrhwemask |= Y2_HWE_L2_MASK; 3771 } 3772 CSR_WRITE_4(sc, B0_HWE_IMSK, sc->msk_intrhwemask); 3773 CSR_READ_4(sc, B0_HWE_IMSK); 3774 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask); 3775 CSR_READ_4(sc, B0_IMSK); 3776 3777 sc_if->msk_link = 0; 3778 mii_mediachg(mii); 3779 3780 ifp->if_drv_flags |= IFF_DRV_RUNNING; 3781 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3782 3783 callout_reset(&sc_if->msk_tick_ch, hz, msk_tick, sc_if); 3784 } 3785 3786 static void 3787 msk_set_rambuffer(struct msk_if_softc *sc_if) 3788 { 3789 struct msk_softc *sc; 3790 int ltpp, utpp; 3791 3792 sc = sc_if->msk_softc; 3793 3794 /* Setup Rx Queue. */ 3795 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_RST_CLR); 3796 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_START), 3797 sc->msk_rxqstart[sc_if->msk_port] / 8); 3798 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_END), 3799 sc->msk_rxqend[sc_if->msk_port] / 8); 3800 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_WP), 3801 sc->msk_rxqstart[sc_if->msk_port] / 8); 3802 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_RP), 3803 sc->msk_rxqstart[sc_if->msk_port] / 8); 3804 3805 utpp = (sc->msk_rxqend[sc_if->msk_port] + 1 - 3806 sc->msk_rxqstart[sc_if->msk_port] - MSK_RB_ULPP) / 8; 3807 ltpp = (sc->msk_rxqend[sc_if->msk_port] + 1 - 3808 sc->msk_rxqstart[sc_if->msk_port] - MSK_RB_LLPP_B) / 8; 3809 if (sc->msk_rxqsize < MSK_MIN_RXQ_SIZE) 3810 ltpp += (MSK_RB_LLPP_B - MSK_RB_LLPP_S) / 8; 3811 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_RX_UTPP), utpp); 3812 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_RX_LTPP), ltpp); 3813 /* Set Rx priority(RB_RX_UTHP/RB_RX_LTHP) thresholds? */ 3814 3815 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_ENA_OP_MD); 3816 CSR_READ_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL)); 3817 3818 /* Setup Tx Queue. */ 3819 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_RST_CLR); 3820 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_START), 3821 sc->msk_txqstart[sc_if->msk_port] / 8); 3822 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_END), 3823 sc->msk_txqend[sc_if->msk_port] / 8); 3824 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_WP), 3825 sc->msk_txqstart[sc_if->msk_port] / 8); 3826 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_RP), 3827 sc->msk_txqstart[sc_if->msk_port] / 8); 3828 /* Enable Store & Forward for Tx side. */ 3829 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_ENA_STFWD); 3830 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_ENA_OP_MD); 3831 CSR_READ_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL)); 3832 } 3833 3834 static void 3835 msk_set_prefetch(struct msk_softc *sc, int qaddr, bus_addr_t addr, 3836 uint32_t count) 3837 { 3838 3839 /* Reset the prefetch unit. */ 3840 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG), 3841 PREF_UNIT_RST_SET); 3842 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG), 3843 PREF_UNIT_RST_CLR); 3844 /* Set LE base address. */ 3845 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_ADDR_LOW_REG), 3846 MSK_ADDR_LO(addr)); 3847 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_ADDR_HI_REG), 3848 MSK_ADDR_HI(addr)); 3849 /* Set the list last index. */ 3850 CSR_WRITE_2(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_LAST_IDX_REG), 3851 count); 3852 /* Turn on prefetch unit. */ 3853 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG), 3854 PREF_UNIT_OP_ON); 3855 /* Dummy read to ensure write. */ 3856 CSR_READ_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG)); 3857 } 3858 3859 static void 3860 msk_stop(struct msk_if_softc *sc_if) 3861 { 3862 struct msk_softc *sc; 3863 struct msk_txdesc *txd; 3864 struct msk_rxdesc *rxd; 3865 struct msk_rxdesc *jrxd; 3866 struct ifnet *ifp; 3867 uint32_t val; 3868 int i; 3869 3870 MSK_IF_LOCK_ASSERT(sc_if); 3871 sc = sc_if->msk_softc; 3872 ifp = sc_if->msk_ifp; 3873 3874 callout_stop(&sc_if->msk_tick_ch); 3875 sc_if->msk_watchdog_timer = 0; 3876 3877 /* Disable interrupts. */ 3878 if (sc_if->msk_port == MSK_PORT_A) { 3879 sc->msk_intrmask &= ~Y2_IS_PORT_A; 3880 sc->msk_intrhwemask &= ~Y2_HWE_L1_MASK; 3881 } else { 3882 sc->msk_intrmask &= ~Y2_IS_PORT_B; 3883 sc->msk_intrhwemask &= ~Y2_HWE_L2_MASK; 3884 } 3885 CSR_WRITE_4(sc, B0_HWE_IMSK, sc->msk_intrhwemask); 3886 CSR_READ_4(sc, B0_HWE_IMSK); 3887 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask); 3888 CSR_READ_4(sc, B0_IMSK); 3889 3890 /* Disable Tx/Rx MAC. */ 3891 val = GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL); 3892 val &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA); 3893 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, val); 3894 /* Read again to ensure writing. */ 3895 GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL); 3896 3897 /* Stop Tx BMU. */ 3898 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_STOP); 3899 val = CSR_READ_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR)); 3900 for (i = 0; i < MSK_TIMEOUT; i++) { 3901 if ((val & (BMU_STOP | BMU_IDLE)) == 0) { 3902 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), 3903 BMU_STOP); 3904 CSR_READ_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR)); 3905 } else 3906 break; 3907 DELAY(1); 3908 } 3909 if (i == MSK_TIMEOUT) 3910 device_printf(sc_if->msk_if_dev, "Tx BMU stop failed\n"); 3911 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), 3912 RB_RST_SET | RB_DIS_OP_MD); 3913 3914 /* Disable all GMAC interrupt. */ 3915 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_MSK), 0); 3916 /* Disable PHY interrupt. */ 3917 msk_phy_writereg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_MASK, 0); 3918 3919 /* Disable the RAM Interface Arbiter. */ 3920 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, TXA_CTRL), TXA_DIS_ARB); 3921 3922 /* Reset the PCI FIFO of the async Tx queue */ 3923 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), 3924 BMU_RST_SET | BMU_FIFO_RST); 3925 3926 /* Reset the Tx prefetch units. */ 3927 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(sc_if->msk_txq, PREF_UNIT_CTRL_REG), 3928 PREF_UNIT_RST_SET); 3929 3930 /* Reset the RAM Buffer async Tx queue. */ 3931 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_RST_SET); 3932 3933 /* Reset Tx MAC FIFO. */ 3934 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_RST_SET); 3935 /* Set Pause Off. */ 3936 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_PAUSE_OFF); 3937 3938 /* 3939 * The Rx Stop command will not work for Yukon-2 if the BMU does not 3940 * reach the end of packet and since we can't make sure that we have 3941 * incoming data, we must reset the BMU while it is not during a DMA 3942 * transfer. Since it is possible that the Rx path is still active, 3943 * the Rx RAM buffer will be stopped first, so any possible incoming 3944 * data will not trigger a DMA. After the RAM buffer is stopped, the 3945 * BMU is polled until any DMA in progress is ended and only then it 3946 * will be reset. 3947 */ 3948 3949 /* Disable the RAM Buffer receive queue. */ 3950 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_DIS_OP_MD); 3951 for (i = 0; i < MSK_TIMEOUT; i++) { 3952 if (CSR_READ_1(sc, RB_ADDR(sc_if->msk_rxq, Q_RSL)) == 3953 CSR_READ_1(sc, RB_ADDR(sc_if->msk_rxq, Q_RL))) 3954 break; 3955 DELAY(1); 3956 } 3957 if (i == MSK_TIMEOUT) 3958 device_printf(sc_if->msk_if_dev, "Rx BMU stop failed\n"); 3959 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), 3960 BMU_RST_SET | BMU_FIFO_RST); 3961 /* Reset the Rx prefetch unit. */ 3962 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_CTRL_REG), 3963 PREF_UNIT_RST_SET); 3964 /* Reset the RAM Buffer receive queue. */ 3965 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_RST_SET); 3966 /* Reset Rx MAC FIFO. */ 3967 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), GMF_RST_SET); 3968 3969 /* Free Rx and Tx mbufs still in the queues. */ 3970 for (i = 0; i < MSK_RX_RING_CNT; i++) { 3971 rxd = &sc_if->msk_cdata.msk_rxdesc[i]; 3972 if (rxd->rx_m != NULL) { 3973 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_tag, 3974 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 3975 bus_dmamap_unload(sc_if->msk_cdata.msk_rx_tag, 3976 rxd->rx_dmamap); 3977 m_freem(rxd->rx_m); 3978 rxd->rx_m = NULL; 3979 } 3980 } 3981 for (i = 0; i < MSK_JUMBO_RX_RING_CNT; i++) { 3982 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[i]; 3983 if (jrxd->rx_m != NULL) { 3984 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_tag, 3985 jrxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 3986 bus_dmamap_unload(sc_if->msk_cdata.msk_jumbo_rx_tag, 3987 jrxd->rx_dmamap); 3988 m_freem(jrxd->rx_m); 3989 jrxd->rx_m = NULL; 3990 } 3991 } 3992 for (i = 0; i < MSK_TX_RING_CNT; i++) { 3993 txd = &sc_if->msk_cdata.msk_txdesc[i]; 3994 if (txd->tx_m != NULL) { 3995 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_tag, 3996 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 3997 bus_dmamap_unload(sc_if->msk_cdata.msk_tx_tag, 3998 txd->tx_dmamap); 3999 m_freem(txd->tx_m); 4000 txd->tx_m = NULL; 4001 } 4002 } 4003 4004 /* 4005 * Mark the interface down. 4006 */ 4007 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 4008 sc_if->msk_link = 0; 4009 } 4010 4011 static int 4012 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 4013 { 4014 int error, value; 4015 4016 if (!arg1) 4017 return (EINVAL); 4018 value = *(int *)arg1; 4019 error = sysctl_handle_int(oidp, &value, 0, req); 4020 if (error || !req->newptr) 4021 return (error); 4022 if (value < low || value > high) 4023 return (EINVAL); 4024 *(int *)arg1 = value; 4025 4026 return (0); 4027 } 4028 4029 static int 4030 sysctl_hw_msk_proc_limit(SYSCTL_HANDLER_ARGS) 4031 { 4032 4033 return (sysctl_int_range(oidp, arg1, arg2, req, MSK_PROC_MIN, 4034 MSK_PROC_MAX)); 4035 } 4036