1 /****************************************************************************** 2 * 3 * Name : sky2.c 4 * Project: Gigabit Ethernet Driver for FreeBSD 5.x/6.x 5 * Version: $Revision: 1.23 $ 6 * Date : $Date: 2005/12/22 09:04:11 $ 7 * Purpose: Main driver source file 8 * 9 *****************************************************************************/ 10 11 /****************************************************************************** 12 * 13 * LICENSE: 14 * Copyright (C) Marvell International Ltd. and/or its affiliates 15 * 16 * The computer program files contained in this folder ("Files") 17 * are provided to you under the BSD-type license terms provided 18 * below, and any use of such Files and any derivative works 19 * thereof created by you shall be governed by the following terms 20 * and conditions: 21 * 22 * - Redistributions of source code must retain the above copyright 23 * notice, this list of conditions and the following disclaimer. 24 * - Redistributions in binary form must reproduce the above 25 * copyright notice, this list of conditions and the following 26 * disclaimer in the documentation and/or other materials provided 27 * with the distribution. 28 * - Neither the name of Marvell nor the names of its contributors 29 * may be used to endorse or promote products derived from this 30 * software without specific prior written permission. 31 * 32 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 33 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 34 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 35 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 36 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 37 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 38 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 39 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 40 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 41 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 42 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED 43 * OF THE POSSIBILITY OF SUCH DAMAGE. 44 * /LICENSE 45 * 46 *****************************************************************************/ 47 48 /*- 49 * Copyright (c) 1997, 1998, 1999, 2000 50 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 51 * 52 * Redistribution and use in source and binary forms, with or without 53 * modification, are permitted provided that the following conditions 54 * are met: 55 * 1. Redistributions of source code must retain the above copyright 56 * notice, this list of conditions and the following disclaimer. 57 * 2. Redistributions in binary form must reproduce the above copyright 58 * notice, this list of conditions and the following disclaimer in the 59 * documentation and/or other materials provided with the distribution. 60 * 3. All advertising materials mentioning features or use of this software 61 * must display the following acknowledgement: 62 * This product includes software developed by Bill Paul. 63 * 4. Neither the name of the author nor the names of any co-contributors 64 * may be used to endorse or promote products derived from this software 65 * without specific prior written permission. 66 * 67 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 68 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 69 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 70 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 71 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 72 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 73 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 74 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 75 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 76 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 77 * THE POSSIBILITY OF SUCH DAMAGE. 78 */ 79 /*- 80 * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu> 81 * 82 * Permission to use, copy, modify, and distribute this software for any 83 * purpose with or without fee is hereby granted, provided that the above 84 * copyright notice and this permission notice appear in all copies. 85 * 86 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 87 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 88 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 89 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 90 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 91 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 92 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 93 */ 94 95 /* 96 * Device driver for the Marvell Yukon II Ethernet controller. 97 * Due to lack of documentation, this driver is based on the code from 98 * sk(4) and Marvell's myk(4) driver for FreeBSD 5.x. 99 */ 100 101 #include <sys/cdefs.h> 102 __FBSDID("$FreeBSD$"); 103 104 #include <sys/param.h> 105 #include <sys/systm.h> 106 #include <sys/bus.h> 107 #include <sys/endian.h> 108 #include <sys/mbuf.h> 109 #include <sys/malloc.h> 110 #include <sys/kernel.h> 111 #include <sys/module.h> 112 #include <sys/socket.h> 113 #include <sys/sockio.h> 114 #include <sys/queue.h> 115 #include <sys/sysctl.h> 116 117 #include <net/bpf.h> 118 #include <net/ethernet.h> 119 #include <net/if.h> 120 #include <net/if_arp.h> 121 #include <net/if_dl.h> 122 #include <net/if_media.h> 123 #include <net/if_types.h> 124 #include <net/if_vlan_var.h> 125 126 #include <netinet/in.h> 127 #include <netinet/in_systm.h> 128 #include <netinet/ip.h> 129 #include <netinet/tcp.h> 130 #include <netinet/udp.h> 131 132 #include <machine/bus.h> 133 #include <machine/in_cksum.h> 134 #include <machine/resource.h> 135 #include <sys/rman.h> 136 137 #include <dev/mii/mii.h> 138 #include <dev/mii/miivar.h> 139 140 #include <dev/pci/pcireg.h> 141 #include <dev/pci/pcivar.h> 142 143 #include <dev/msk/if_mskreg.h> 144 145 MODULE_DEPEND(msk, pci, 1, 1, 1); 146 MODULE_DEPEND(msk, ether, 1, 1, 1); 147 MODULE_DEPEND(msk, miibus, 1, 1, 1); 148 149 /* "device miibus" required. See GENERIC if you get errors here. */ 150 #include "miibus_if.h" 151 152 /* Tunables. */ 153 static int msi_disable = 0; 154 TUNABLE_INT("hw.msk.msi_disable", &msi_disable); 155 static int legacy_intr = 0; 156 TUNABLE_INT("hw.msk.legacy_intr", &legacy_intr); 157 static int jumbo_disable = 0; 158 TUNABLE_INT("hw.msk.jumbo_disable", &jumbo_disable); 159 160 #define MSK_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 161 162 /* 163 * Devices supported by this driver. 164 */ 165 static struct msk_product { 166 uint16_t msk_vendorid; 167 uint16_t msk_deviceid; 168 const char *msk_name; 169 } msk_products[] = { 170 { VENDORID_SK, DEVICEID_SK_YUKON2, 171 "SK-9Sxx Gigabit Ethernet" }, 172 { VENDORID_SK, DEVICEID_SK_YUKON2_EXPR, 173 "SK-9Exx Gigabit Ethernet"}, 174 { VENDORID_MARVELL, DEVICEID_MRVL_8021CU, 175 "Marvell Yukon 88E8021CU Gigabit Ethernet" }, 176 { VENDORID_MARVELL, DEVICEID_MRVL_8021X, 177 "Marvell Yukon 88E8021 SX/LX Gigabit Ethernet" }, 178 { VENDORID_MARVELL, DEVICEID_MRVL_8022CU, 179 "Marvell Yukon 88E8022CU Gigabit Ethernet" }, 180 { VENDORID_MARVELL, DEVICEID_MRVL_8022X, 181 "Marvell Yukon 88E8022 SX/LX Gigabit Ethernet" }, 182 { VENDORID_MARVELL, DEVICEID_MRVL_8061CU, 183 "Marvell Yukon 88E8061CU Gigabit Ethernet" }, 184 { VENDORID_MARVELL, DEVICEID_MRVL_8061X, 185 "Marvell Yukon 88E8061 SX/LX Gigabit Ethernet" }, 186 { VENDORID_MARVELL, DEVICEID_MRVL_8062CU, 187 "Marvell Yukon 88E8062CU Gigabit Ethernet" }, 188 { VENDORID_MARVELL, DEVICEID_MRVL_8062X, 189 "Marvell Yukon 88E8062 SX/LX Gigabit Ethernet" }, 190 { VENDORID_MARVELL, DEVICEID_MRVL_8035, 191 "Marvell Yukon 88E8035 Fast Ethernet" }, 192 { VENDORID_MARVELL, DEVICEID_MRVL_8036, 193 "Marvell Yukon 88E8036 Fast Ethernet" }, 194 { VENDORID_MARVELL, DEVICEID_MRVL_8038, 195 "Marvell Yukon 88E8038 Fast Ethernet" }, 196 { VENDORID_MARVELL, DEVICEID_MRVL_8039, 197 "Marvell Yukon 88E8039 Fast Ethernet" }, 198 { VENDORID_MARVELL, DEVICEID_MRVL_8040, 199 "Marvell Yukon 88E8040 Fast Ethernet" }, 200 { VENDORID_MARVELL, DEVICEID_MRVL_8040T, 201 "Marvell Yukon 88E8040T Fast Ethernet" }, 202 { VENDORID_MARVELL, DEVICEID_MRVL_8042, 203 "Marvell Yukon 88E8042 Fast Ethernet" }, 204 { VENDORID_MARVELL, DEVICEID_MRVL_8048, 205 "Marvell Yukon 88E8048 Fast Ethernet" }, 206 { VENDORID_MARVELL, DEVICEID_MRVL_4361, 207 "Marvell Yukon 88E8050 Gigabit Ethernet" }, 208 { VENDORID_MARVELL, DEVICEID_MRVL_4360, 209 "Marvell Yukon 88E8052 Gigabit Ethernet" }, 210 { VENDORID_MARVELL, DEVICEID_MRVL_4362, 211 "Marvell Yukon 88E8053 Gigabit Ethernet" }, 212 { VENDORID_MARVELL, DEVICEID_MRVL_4363, 213 "Marvell Yukon 88E8055 Gigabit Ethernet" }, 214 { VENDORID_MARVELL, DEVICEID_MRVL_4364, 215 "Marvell Yukon 88E8056 Gigabit Ethernet" }, 216 { VENDORID_MARVELL, DEVICEID_MRVL_4365, 217 "Marvell Yukon 88E8070 Gigabit Ethernet" }, 218 { VENDORID_MARVELL, DEVICEID_MRVL_436A, 219 "Marvell Yukon 88E8058 Gigabit Ethernet" }, 220 { VENDORID_MARVELL, DEVICEID_MRVL_436B, 221 "Marvell Yukon 88E8071 Gigabit Ethernet" }, 222 { VENDORID_MARVELL, DEVICEID_MRVL_436C, 223 "Marvell Yukon 88E8072 Gigabit Ethernet" }, 224 { VENDORID_MARVELL, DEVICEID_MRVL_4380, 225 "Marvell Yukon 88E8057 Gigabit Ethernet" }, 226 { VENDORID_DLINK, DEVICEID_DLINK_DGE550SX, 227 "D-Link 550SX Gigabit Ethernet" }, 228 { VENDORID_DLINK, DEVICEID_DLINK_DGE560SX, 229 "D-Link 560SX Gigabit Ethernet" }, 230 { VENDORID_DLINK, DEVICEID_DLINK_DGE560T, 231 "D-Link 560T Gigabit Ethernet" } 232 }; 233 234 static const char *model_name[] = { 235 "Yukon XL", 236 "Yukon EC Ultra", 237 "Yukon EX", 238 "Yukon EC", 239 "Yukon FE", 240 "Yukon FE+", 241 "Yukon Supreme", 242 "Yukon Ultra 2" 243 }; 244 245 static int mskc_probe(device_t); 246 static int mskc_attach(device_t); 247 static int mskc_detach(device_t); 248 static int mskc_shutdown(device_t); 249 static int mskc_setup_rambuffer(struct msk_softc *); 250 static int mskc_suspend(device_t); 251 static int mskc_resume(device_t); 252 static void mskc_reset(struct msk_softc *); 253 254 static int msk_probe(device_t); 255 static int msk_attach(device_t); 256 static int msk_detach(device_t); 257 258 static void msk_tick(void *); 259 static void msk_intr(void *); 260 static void msk_intr_phy(struct msk_if_softc *); 261 static void msk_intr_gmac(struct msk_if_softc *); 262 static __inline void msk_rxput(struct msk_if_softc *); 263 static int msk_handle_events(struct msk_softc *); 264 static void msk_handle_hwerr(struct msk_if_softc *, uint32_t); 265 static void msk_intr_hwerr(struct msk_softc *); 266 #ifndef __NO_STRICT_ALIGNMENT 267 static __inline void msk_fixup_rx(struct mbuf *); 268 #endif 269 static void msk_rxeof(struct msk_if_softc *, uint32_t, uint32_t, int); 270 static void msk_jumbo_rxeof(struct msk_if_softc *, uint32_t, uint32_t, int); 271 static void msk_txeof(struct msk_if_softc *, int); 272 static int msk_encap(struct msk_if_softc *, struct mbuf **); 273 static void msk_start(struct ifnet *); 274 static void msk_start_locked(struct ifnet *); 275 static int msk_ioctl(struct ifnet *, u_long, caddr_t); 276 static void msk_set_prefetch(struct msk_softc *, int, bus_addr_t, uint32_t); 277 static void msk_set_rambuffer(struct msk_if_softc *); 278 static void msk_set_tx_stfwd(struct msk_if_softc *); 279 static void msk_init(void *); 280 static void msk_init_locked(struct msk_if_softc *); 281 static void msk_stop(struct msk_if_softc *); 282 static void msk_watchdog(struct msk_if_softc *); 283 static int msk_mediachange(struct ifnet *); 284 static void msk_mediastatus(struct ifnet *, struct ifmediareq *); 285 static void msk_phy_power(struct msk_softc *, int); 286 static void msk_dmamap_cb(void *, bus_dma_segment_t *, int, int); 287 static int msk_status_dma_alloc(struct msk_softc *); 288 static void msk_status_dma_free(struct msk_softc *); 289 static int msk_txrx_dma_alloc(struct msk_if_softc *); 290 static int msk_rx_dma_jalloc(struct msk_if_softc *); 291 static void msk_txrx_dma_free(struct msk_if_softc *); 292 static void msk_rx_dma_jfree(struct msk_if_softc *); 293 static int msk_init_rx_ring(struct msk_if_softc *); 294 static int msk_init_jumbo_rx_ring(struct msk_if_softc *); 295 static void msk_init_tx_ring(struct msk_if_softc *); 296 static __inline void msk_discard_rxbuf(struct msk_if_softc *, int); 297 static __inline void msk_discard_jumbo_rxbuf(struct msk_if_softc *, int); 298 static int msk_newbuf(struct msk_if_softc *, int); 299 static int msk_jumbo_newbuf(struct msk_if_softc *, int); 300 301 static int msk_phy_readreg(struct msk_if_softc *, int, int); 302 static int msk_phy_writereg(struct msk_if_softc *, int, int, int); 303 static int msk_miibus_readreg(device_t, int, int); 304 static int msk_miibus_writereg(device_t, int, int, int); 305 static void msk_miibus_statchg(device_t); 306 307 static void msk_rxfilter(struct msk_if_softc *); 308 static void msk_setvlan(struct msk_if_softc *, struct ifnet *); 309 310 static void msk_stats_clear(struct msk_if_softc *); 311 static void msk_stats_update(struct msk_if_softc *); 312 static int msk_sysctl_stat32(SYSCTL_HANDLER_ARGS); 313 static int msk_sysctl_stat64(SYSCTL_HANDLER_ARGS); 314 static void msk_sysctl_node(struct msk_if_softc *); 315 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int); 316 static int sysctl_hw_msk_proc_limit(SYSCTL_HANDLER_ARGS); 317 318 static device_method_t mskc_methods[] = { 319 /* Device interface */ 320 DEVMETHOD(device_probe, mskc_probe), 321 DEVMETHOD(device_attach, mskc_attach), 322 DEVMETHOD(device_detach, mskc_detach), 323 DEVMETHOD(device_suspend, mskc_suspend), 324 DEVMETHOD(device_resume, mskc_resume), 325 DEVMETHOD(device_shutdown, mskc_shutdown), 326 327 /* bus interface */ 328 DEVMETHOD(bus_print_child, bus_generic_print_child), 329 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 330 331 { NULL, NULL } 332 }; 333 334 static driver_t mskc_driver = { 335 "mskc", 336 mskc_methods, 337 sizeof(struct msk_softc) 338 }; 339 340 static devclass_t mskc_devclass; 341 342 static device_method_t msk_methods[] = { 343 /* Device interface */ 344 DEVMETHOD(device_probe, msk_probe), 345 DEVMETHOD(device_attach, msk_attach), 346 DEVMETHOD(device_detach, msk_detach), 347 DEVMETHOD(device_shutdown, bus_generic_shutdown), 348 349 /* bus interface */ 350 DEVMETHOD(bus_print_child, bus_generic_print_child), 351 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 352 353 /* MII interface */ 354 DEVMETHOD(miibus_readreg, msk_miibus_readreg), 355 DEVMETHOD(miibus_writereg, msk_miibus_writereg), 356 DEVMETHOD(miibus_statchg, msk_miibus_statchg), 357 358 { NULL, NULL } 359 }; 360 361 static driver_t msk_driver = { 362 "msk", 363 msk_methods, 364 sizeof(struct msk_if_softc) 365 }; 366 367 static devclass_t msk_devclass; 368 369 DRIVER_MODULE(mskc, pci, mskc_driver, mskc_devclass, 0, 0); 370 DRIVER_MODULE(msk, mskc, msk_driver, msk_devclass, 0, 0); 371 DRIVER_MODULE(miibus, msk, miibus_driver, miibus_devclass, 0, 0); 372 373 static struct resource_spec msk_res_spec_io[] = { 374 { SYS_RES_IOPORT, PCIR_BAR(1), RF_ACTIVE }, 375 { -1, 0, 0 } 376 }; 377 378 static struct resource_spec msk_res_spec_mem[] = { 379 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 380 { -1, 0, 0 } 381 }; 382 383 static struct resource_spec msk_irq_spec_legacy[] = { 384 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 385 { -1, 0, 0 } 386 }; 387 388 static struct resource_spec msk_irq_spec_msi[] = { 389 { SYS_RES_IRQ, 1, RF_ACTIVE }, 390 { -1, 0, 0 } 391 }; 392 393 static int 394 msk_miibus_readreg(device_t dev, int phy, int reg) 395 { 396 struct msk_if_softc *sc_if; 397 398 if (phy != PHY_ADDR_MARV) 399 return (0); 400 401 sc_if = device_get_softc(dev); 402 403 return (msk_phy_readreg(sc_if, phy, reg)); 404 } 405 406 static int 407 msk_phy_readreg(struct msk_if_softc *sc_if, int phy, int reg) 408 { 409 struct msk_softc *sc; 410 int i, val; 411 412 sc = sc_if->msk_softc; 413 414 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SMI_CTRL, 415 GM_SMI_CT_PHY_AD(phy) | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD); 416 417 for (i = 0; i < MSK_TIMEOUT; i++) { 418 DELAY(1); 419 val = GMAC_READ_2(sc, sc_if->msk_port, GM_SMI_CTRL); 420 if ((val & GM_SMI_CT_RD_VAL) != 0) { 421 val = GMAC_READ_2(sc, sc_if->msk_port, GM_SMI_DATA); 422 break; 423 } 424 } 425 426 if (i == MSK_TIMEOUT) { 427 if_printf(sc_if->msk_ifp, "phy failed to come ready\n"); 428 val = 0; 429 } 430 431 return (val); 432 } 433 434 static int 435 msk_miibus_writereg(device_t dev, int phy, int reg, int val) 436 { 437 struct msk_if_softc *sc_if; 438 439 if (phy != PHY_ADDR_MARV) 440 return (0); 441 442 sc_if = device_get_softc(dev); 443 444 return (msk_phy_writereg(sc_if, phy, reg, val)); 445 } 446 447 static int 448 msk_phy_writereg(struct msk_if_softc *sc_if, int phy, int reg, int val) 449 { 450 struct msk_softc *sc; 451 int i; 452 453 sc = sc_if->msk_softc; 454 455 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SMI_DATA, val); 456 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SMI_CTRL, 457 GM_SMI_CT_PHY_AD(phy) | GM_SMI_CT_REG_AD(reg)); 458 for (i = 0; i < MSK_TIMEOUT; i++) { 459 DELAY(1); 460 if ((GMAC_READ_2(sc, sc_if->msk_port, GM_SMI_CTRL) & 461 GM_SMI_CT_BUSY) == 0) 462 break; 463 } 464 if (i == MSK_TIMEOUT) 465 if_printf(sc_if->msk_ifp, "phy write timeout\n"); 466 467 return (0); 468 } 469 470 static void 471 msk_miibus_statchg(device_t dev) 472 { 473 struct msk_softc *sc; 474 struct msk_if_softc *sc_if; 475 struct mii_data *mii; 476 struct ifnet *ifp; 477 uint32_t gmac; 478 479 sc_if = device_get_softc(dev); 480 sc = sc_if->msk_softc; 481 482 MSK_IF_LOCK_ASSERT(sc_if); 483 484 mii = device_get_softc(sc_if->msk_miibus); 485 ifp = sc_if->msk_ifp; 486 if (mii == NULL || ifp == NULL || 487 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 488 return; 489 490 sc_if->msk_flags &= ~MSK_FLAG_LINK; 491 if ((mii->mii_media_status & (IFM_AVALID | IFM_ACTIVE)) == 492 (IFM_AVALID | IFM_ACTIVE)) { 493 switch (IFM_SUBTYPE(mii->mii_media_active)) { 494 case IFM_10_T: 495 case IFM_100_TX: 496 sc_if->msk_flags |= MSK_FLAG_LINK; 497 break; 498 case IFM_1000_T: 499 case IFM_1000_SX: 500 case IFM_1000_LX: 501 case IFM_1000_CX: 502 if ((sc_if->msk_flags & MSK_FLAG_FASTETHER) == 0) 503 sc_if->msk_flags |= MSK_FLAG_LINK; 504 break; 505 default: 506 break; 507 } 508 } 509 510 if ((sc_if->msk_flags & MSK_FLAG_LINK) != 0) { 511 /* Enable Tx FIFO Underrun. */ 512 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_MSK), 513 GM_IS_TX_FF_UR | GM_IS_RX_FF_OR); 514 /* 515 * Because mii(4) notify msk(4) that it detected link status 516 * change, there is no need to enable automatic 517 * speed/flow-control/duplex updates. 518 */ 519 gmac = GM_GPCR_AU_ALL_DIS; 520 switch (IFM_SUBTYPE(mii->mii_media_active)) { 521 case IFM_1000_SX: 522 case IFM_1000_T: 523 gmac |= GM_GPCR_SPEED_1000; 524 break; 525 case IFM_100_TX: 526 gmac |= GM_GPCR_SPEED_100; 527 break; 528 case IFM_10_T: 529 break; 530 } 531 532 /* Disable Rx flow control. */ 533 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FLAG0) == 0) 534 gmac |= GM_GPCR_FC_RX_DIS; 535 /* Disable Tx flow control. */ 536 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FLAG1) == 0) 537 gmac |= GM_GPCR_FC_TX_DIS; 538 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) 539 gmac |= GM_GPCR_DUP_FULL; 540 else 541 gmac |= GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS; 542 gmac |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA; 543 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, gmac); 544 /* Read again to ensure writing. */ 545 GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL); 546 gmac = GMC_PAUSE_OFF; 547 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 548 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FLAG0) != 0) 549 gmac = GMC_PAUSE_ON; 550 } 551 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), gmac); 552 553 /* Enable PHY interrupt for FIFO underrun/overflow. */ 554 msk_phy_writereg(sc_if, PHY_ADDR_MARV, 555 PHY_MARV_INT_MASK, PHY_M_IS_FIFO_ERROR); 556 } else { 557 /* 558 * Link state changed to down. 559 * Disable PHY interrupts. 560 */ 561 msk_phy_writereg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_MASK, 0); 562 /* Disable Rx/Tx MAC. */ 563 gmac = GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL); 564 if ((GM_GPCR_RX_ENA | GM_GPCR_TX_ENA) != 0) { 565 gmac &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA); 566 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, gmac); 567 /* Read again to ensure writing. */ 568 GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL); 569 } 570 } 571 } 572 573 static void 574 msk_rxfilter(struct msk_if_softc *sc_if) 575 { 576 struct msk_softc *sc; 577 struct ifnet *ifp; 578 struct ifmultiaddr *ifma; 579 uint32_t mchash[2]; 580 uint32_t crc; 581 uint16_t mode; 582 583 sc = sc_if->msk_softc; 584 585 MSK_IF_LOCK_ASSERT(sc_if); 586 587 ifp = sc_if->msk_ifp; 588 589 bzero(mchash, sizeof(mchash)); 590 mode = GMAC_READ_2(sc, sc_if->msk_port, GM_RX_CTRL); 591 if ((ifp->if_flags & IFF_PROMISC) != 0) 592 mode &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA); 593 else if ((ifp->if_flags & IFF_ALLMULTI) != 0) { 594 mode |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA; 595 mchash[0] = 0xffff; 596 mchash[1] = 0xffff; 597 } else { 598 mode |= GM_RXCR_UCF_ENA; 599 if_maddr_rlock(ifp); 600 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 601 if (ifma->ifma_addr->sa_family != AF_LINK) 602 continue; 603 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *) 604 ifma->ifma_addr), ETHER_ADDR_LEN); 605 /* Just want the 6 least significant bits. */ 606 crc &= 0x3f; 607 /* Set the corresponding bit in the hash table. */ 608 mchash[crc >> 5] |= 1 << (crc & 0x1f); 609 } 610 if_maddr_runlock(ifp); 611 if (mchash[0] != 0 || mchash[1] != 0) 612 mode |= GM_RXCR_MCF_ENA; 613 } 614 615 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H1, 616 mchash[0] & 0xffff); 617 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H2, 618 (mchash[0] >> 16) & 0xffff); 619 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H3, 620 mchash[1] & 0xffff); 621 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H4, 622 (mchash[1] >> 16) & 0xffff); 623 GMAC_WRITE_2(sc, sc_if->msk_port, GM_RX_CTRL, mode); 624 } 625 626 static void 627 msk_setvlan(struct msk_if_softc *sc_if, struct ifnet *ifp) 628 { 629 struct msk_softc *sc; 630 631 sc = sc_if->msk_softc; 632 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) { 633 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), 634 RX_VLAN_STRIP_ON); 635 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 636 TX_VLAN_TAG_ON); 637 } else { 638 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), 639 RX_VLAN_STRIP_OFF); 640 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 641 TX_VLAN_TAG_OFF); 642 } 643 } 644 645 static int 646 msk_init_rx_ring(struct msk_if_softc *sc_if) 647 { 648 struct msk_ring_data *rd; 649 struct msk_rxdesc *rxd; 650 int i, prod; 651 652 MSK_IF_LOCK_ASSERT(sc_if); 653 654 sc_if->msk_cdata.msk_rx_cons = 0; 655 sc_if->msk_cdata.msk_rx_prod = 0; 656 sc_if->msk_cdata.msk_rx_putwm = MSK_PUT_WM; 657 658 rd = &sc_if->msk_rdata; 659 bzero(rd->msk_rx_ring, sizeof(struct msk_rx_desc) * MSK_RX_RING_CNT); 660 prod = sc_if->msk_cdata.msk_rx_prod; 661 for (i = 0; i < MSK_RX_RING_CNT; i++) { 662 rxd = &sc_if->msk_cdata.msk_rxdesc[prod]; 663 rxd->rx_m = NULL; 664 rxd->rx_le = &rd->msk_rx_ring[prod]; 665 if (msk_newbuf(sc_if, prod) != 0) 666 return (ENOBUFS); 667 MSK_INC(prod, MSK_RX_RING_CNT); 668 } 669 670 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_ring_tag, 671 sc_if->msk_cdata.msk_rx_ring_map, 672 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 673 674 /* Update prefetch unit. */ 675 sc_if->msk_cdata.msk_rx_prod = MSK_RX_RING_CNT - 1; 676 CSR_WRITE_2(sc_if->msk_softc, 677 Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_PUT_IDX_REG), 678 sc_if->msk_cdata.msk_rx_prod); 679 680 return (0); 681 } 682 683 static int 684 msk_init_jumbo_rx_ring(struct msk_if_softc *sc_if) 685 { 686 struct msk_ring_data *rd; 687 struct msk_rxdesc *rxd; 688 int i, prod; 689 690 MSK_IF_LOCK_ASSERT(sc_if); 691 692 sc_if->msk_cdata.msk_rx_cons = 0; 693 sc_if->msk_cdata.msk_rx_prod = 0; 694 sc_if->msk_cdata.msk_rx_putwm = MSK_PUT_WM; 695 696 rd = &sc_if->msk_rdata; 697 bzero(rd->msk_jumbo_rx_ring, 698 sizeof(struct msk_rx_desc) * MSK_JUMBO_RX_RING_CNT); 699 prod = sc_if->msk_cdata.msk_rx_prod; 700 for (i = 0; i < MSK_JUMBO_RX_RING_CNT; i++) { 701 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[prod]; 702 rxd->rx_m = NULL; 703 rxd->rx_le = &rd->msk_jumbo_rx_ring[prod]; 704 if (msk_jumbo_newbuf(sc_if, prod) != 0) 705 return (ENOBUFS); 706 MSK_INC(prod, MSK_JUMBO_RX_RING_CNT); 707 } 708 709 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 710 sc_if->msk_cdata.msk_jumbo_rx_ring_map, 711 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 712 713 sc_if->msk_cdata.msk_rx_prod = MSK_JUMBO_RX_RING_CNT - 1; 714 CSR_WRITE_2(sc_if->msk_softc, 715 Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_PUT_IDX_REG), 716 sc_if->msk_cdata.msk_rx_prod); 717 718 return (0); 719 } 720 721 static void 722 msk_init_tx_ring(struct msk_if_softc *sc_if) 723 { 724 struct msk_ring_data *rd; 725 struct msk_txdesc *txd; 726 int i; 727 728 sc_if->msk_cdata.msk_tso_mtu = 0; 729 sc_if->msk_cdata.msk_last_csum = 0; 730 sc_if->msk_cdata.msk_tx_prod = 0; 731 sc_if->msk_cdata.msk_tx_cons = 0; 732 sc_if->msk_cdata.msk_tx_cnt = 0; 733 734 rd = &sc_if->msk_rdata; 735 bzero(rd->msk_tx_ring, sizeof(struct msk_tx_desc) * MSK_TX_RING_CNT); 736 for (i = 0; i < MSK_TX_RING_CNT; i++) { 737 txd = &sc_if->msk_cdata.msk_txdesc[i]; 738 txd->tx_m = NULL; 739 txd->tx_le = &rd->msk_tx_ring[i]; 740 } 741 742 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_ring_tag, 743 sc_if->msk_cdata.msk_tx_ring_map, 744 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 745 } 746 747 static __inline void 748 msk_discard_rxbuf(struct msk_if_softc *sc_if, int idx) 749 { 750 struct msk_rx_desc *rx_le; 751 struct msk_rxdesc *rxd; 752 struct mbuf *m; 753 754 rxd = &sc_if->msk_cdata.msk_rxdesc[idx]; 755 m = rxd->rx_m; 756 rx_le = rxd->rx_le; 757 rx_le->msk_control = htole32(m->m_len | OP_PACKET | HW_OWNER); 758 } 759 760 static __inline void 761 msk_discard_jumbo_rxbuf(struct msk_if_softc *sc_if, int idx) 762 { 763 struct msk_rx_desc *rx_le; 764 struct msk_rxdesc *rxd; 765 struct mbuf *m; 766 767 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[idx]; 768 m = rxd->rx_m; 769 rx_le = rxd->rx_le; 770 rx_le->msk_control = htole32(m->m_len | OP_PACKET | HW_OWNER); 771 } 772 773 static int 774 msk_newbuf(struct msk_if_softc *sc_if, int idx) 775 { 776 struct msk_rx_desc *rx_le; 777 struct msk_rxdesc *rxd; 778 struct mbuf *m; 779 bus_dma_segment_t segs[1]; 780 bus_dmamap_t map; 781 int nsegs; 782 783 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 784 if (m == NULL) 785 return (ENOBUFS); 786 787 m->m_len = m->m_pkthdr.len = MCLBYTES; 788 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) == 0) 789 m_adj(m, ETHER_ALIGN); 790 #ifndef __NO_STRICT_ALIGNMENT 791 else 792 m_adj(m, MSK_RX_BUF_ALIGN); 793 #endif 794 795 if (bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_rx_tag, 796 sc_if->msk_cdata.msk_rx_sparemap, m, segs, &nsegs, 797 BUS_DMA_NOWAIT) != 0) { 798 m_freem(m); 799 return (ENOBUFS); 800 } 801 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 802 803 rxd = &sc_if->msk_cdata.msk_rxdesc[idx]; 804 if (rxd->rx_m != NULL) { 805 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_tag, rxd->rx_dmamap, 806 BUS_DMASYNC_POSTREAD); 807 bus_dmamap_unload(sc_if->msk_cdata.msk_rx_tag, rxd->rx_dmamap); 808 } 809 map = rxd->rx_dmamap; 810 rxd->rx_dmamap = sc_if->msk_cdata.msk_rx_sparemap; 811 sc_if->msk_cdata.msk_rx_sparemap = map; 812 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_tag, rxd->rx_dmamap, 813 BUS_DMASYNC_PREREAD); 814 rxd->rx_m = m; 815 rx_le = rxd->rx_le; 816 rx_le->msk_addr = htole32(MSK_ADDR_LO(segs[0].ds_addr)); 817 rx_le->msk_control = 818 htole32(segs[0].ds_len | OP_PACKET | HW_OWNER); 819 820 return (0); 821 } 822 823 static int 824 msk_jumbo_newbuf(struct msk_if_softc *sc_if, int idx) 825 { 826 struct msk_rx_desc *rx_le; 827 struct msk_rxdesc *rxd; 828 struct mbuf *m; 829 bus_dma_segment_t segs[1]; 830 bus_dmamap_t map; 831 int nsegs; 832 833 m = m_getjcl(M_DONTWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES); 834 if (m == NULL) 835 return (ENOBUFS); 836 if ((m->m_flags & M_EXT) == 0) { 837 m_freem(m); 838 return (ENOBUFS); 839 } 840 m->m_len = m->m_pkthdr.len = MJUM9BYTES; 841 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) == 0) 842 m_adj(m, ETHER_ALIGN); 843 #ifndef __NO_STRICT_ALIGNMENT 844 else 845 m_adj(m, MSK_RX_BUF_ALIGN); 846 #endif 847 848 if (bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_jumbo_rx_tag, 849 sc_if->msk_cdata.msk_jumbo_rx_sparemap, m, segs, &nsegs, 850 BUS_DMA_NOWAIT) != 0) { 851 m_freem(m); 852 return (ENOBUFS); 853 } 854 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 855 856 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[idx]; 857 if (rxd->rx_m != NULL) { 858 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_tag, 859 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 860 bus_dmamap_unload(sc_if->msk_cdata.msk_jumbo_rx_tag, 861 rxd->rx_dmamap); 862 } 863 map = rxd->rx_dmamap; 864 rxd->rx_dmamap = sc_if->msk_cdata.msk_jumbo_rx_sparemap; 865 sc_if->msk_cdata.msk_jumbo_rx_sparemap = map; 866 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_tag, rxd->rx_dmamap, 867 BUS_DMASYNC_PREREAD); 868 rxd->rx_m = m; 869 rx_le = rxd->rx_le; 870 rx_le->msk_addr = htole32(MSK_ADDR_LO(segs[0].ds_addr)); 871 rx_le->msk_control = 872 htole32(segs[0].ds_len | OP_PACKET | HW_OWNER); 873 874 return (0); 875 } 876 877 /* 878 * Set media options. 879 */ 880 static int 881 msk_mediachange(struct ifnet *ifp) 882 { 883 struct msk_if_softc *sc_if; 884 struct mii_data *mii; 885 int error; 886 887 sc_if = ifp->if_softc; 888 889 MSK_IF_LOCK(sc_if); 890 mii = device_get_softc(sc_if->msk_miibus); 891 error = mii_mediachg(mii); 892 MSK_IF_UNLOCK(sc_if); 893 894 return (error); 895 } 896 897 /* 898 * Report current media status. 899 */ 900 static void 901 msk_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 902 { 903 struct msk_if_softc *sc_if; 904 struct mii_data *mii; 905 906 sc_if = ifp->if_softc; 907 MSK_IF_LOCK(sc_if); 908 if ((ifp->if_flags & IFF_UP) == 0) { 909 MSK_IF_UNLOCK(sc_if); 910 return; 911 } 912 mii = device_get_softc(sc_if->msk_miibus); 913 914 mii_pollstat(mii); 915 MSK_IF_UNLOCK(sc_if); 916 ifmr->ifm_active = mii->mii_media_active; 917 ifmr->ifm_status = mii->mii_media_status; 918 } 919 920 static int 921 msk_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 922 { 923 struct msk_if_softc *sc_if; 924 struct ifreq *ifr; 925 struct mii_data *mii; 926 int error, mask; 927 928 sc_if = ifp->if_softc; 929 ifr = (struct ifreq *)data; 930 error = 0; 931 932 switch(command) { 933 case SIOCSIFMTU: 934 MSK_IF_LOCK(sc_if); 935 if (ifr->ifr_mtu > MSK_JUMBO_MTU || ifr->ifr_mtu < ETHERMIN) 936 error = EINVAL; 937 else if (ifp->if_mtu != ifr->ifr_mtu) { 938 if (ifr->ifr_mtu > ETHERMTU) { 939 if ((sc_if->msk_flags & MSK_FLAG_JUMBO) == 0) { 940 error = EINVAL; 941 MSK_IF_UNLOCK(sc_if); 942 break; 943 } 944 if ((sc_if->msk_flags & 945 MSK_FLAG_JUMBO_NOCSUM) != 0) { 946 ifp->if_hwassist &= 947 ~(MSK_CSUM_FEATURES | CSUM_TSO); 948 ifp->if_capenable &= 949 ~(IFCAP_TSO4 | IFCAP_TXCSUM); 950 VLAN_CAPABILITIES(ifp); 951 } 952 } 953 ifp->if_mtu = ifr->ifr_mtu; 954 msk_init_locked(sc_if); 955 } 956 MSK_IF_UNLOCK(sc_if); 957 break; 958 case SIOCSIFFLAGS: 959 MSK_IF_LOCK(sc_if); 960 if ((ifp->if_flags & IFF_UP) != 0) { 961 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 && 962 ((ifp->if_flags ^ sc_if->msk_if_flags) & 963 (IFF_PROMISC | IFF_ALLMULTI)) != 0) 964 msk_rxfilter(sc_if); 965 else if ((sc_if->msk_flags & MSK_FLAG_DETACH) == 0) 966 msk_init_locked(sc_if); 967 } else if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 968 msk_stop(sc_if); 969 sc_if->msk_if_flags = ifp->if_flags; 970 MSK_IF_UNLOCK(sc_if); 971 break; 972 case SIOCADDMULTI: 973 case SIOCDELMULTI: 974 MSK_IF_LOCK(sc_if); 975 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 976 msk_rxfilter(sc_if); 977 MSK_IF_UNLOCK(sc_if); 978 break; 979 case SIOCGIFMEDIA: 980 case SIOCSIFMEDIA: 981 mii = device_get_softc(sc_if->msk_miibus); 982 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 983 break; 984 case SIOCSIFCAP: 985 MSK_IF_LOCK(sc_if); 986 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 987 if ((mask & IFCAP_TXCSUM) != 0 && 988 (IFCAP_TXCSUM & ifp->if_capabilities) != 0) { 989 ifp->if_capenable ^= IFCAP_TXCSUM; 990 if ((IFCAP_TXCSUM & ifp->if_capenable) != 0) 991 ifp->if_hwassist |= MSK_CSUM_FEATURES; 992 else 993 ifp->if_hwassist &= ~MSK_CSUM_FEATURES; 994 } 995 if ((mask & IFCAP_RXCSUM) != 0 && 996 (IFCAP_RXCSUM & ifp->if_capabilities) != 0) 997 ifp->if_capenable ^= IFCAP_RXCSUM; 998 if ((mask & IFCAP_VLAN_HWCSUM) != 0 && 999 (IFCAP_VLAN_HWCSUM & ifp->if_capabilities) != 0) 1000 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; 1001 if ((mask & IFCAP_TSO4) != 0 && 1002 (IFCAP_TSO4 & ifp->if_capabilities) != 0) { 1003 ifp->if_capenable ^= IFCAP_TSO4; 1004 if ((IFCAP_TSO4 & ifp->if_capenable) != 0) 1005 ifp->if_hwassist |= CSUM_TSO; 1006 else 1007 ifp->if_hwassist &= ~CSUM_TSO; 1008 } 1009 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 1010 (IFCAP_VLAN_HWTSO & ifp->if_capabilities) != 0) 1011 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 1012 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 1013 (IFCAP_VLAN_HWTAGGING & ifp->if_capabilities) != 0) { 1014 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 1015 if ((IFCAP_VLAN_HWTAGGING & ifp->if_capenable) == 0) 1016 ifp->if_capenable &= ~IFCAP_VLAN_HWTSO; 1017 msk_setvlan(sc_if, ifp); 1018 } 1019 if (ifp->if_mtu > ETHERMTU && 1020 (sc_if->msk_flags & MSK_FLAG_JUMBO_NOCSUM) != 0) { 1021 ifp->if_hwassist &= ~(MSK_CSUM_FEATURES | CSUM_TSO); 1022 ifp->if_capenable &= ~(IFCAP_TSO4 | IFCAP_TXCSUM); 1023 } 1024 1025 VLAN_CAPABILITIES(ifp); 1026 MSK_IF_UNLOCK(sc_if); 1027 break; 1028 default: 1029 error = ether_ioctl(ifp, command, data); 1030 break; 1031 } 1032 1033 return (error); 1034 } 1035 1036 static int 1037 mskc_probe(device_t dev) 1038 { 1039 struct msk_product *mp; 1040 uint16_t vendor, devid; 1041 int i; 1042 1043 vendor = pci_get_vendor(dev); 1044 devid = pci_get_device(dev); 1045 mp = msk_products; 1046 for (i = 0; i < sizeof(msk_products)/sizeof(msk_products[0]); 1047 i++, mp++) { 1048 if (vendor == mp->msk_vendorid && devid == mp->msk_deviceid) { 1049 device_set_desc(dev, mp->msk_name); 1050 return (BUS_PROBE_DEFAULT); 1051 } 1052 } 1053 1054 return (ENXIO); 1055 } 1056 1057 static int 1058 mskc_setup_rambuffer(struct msk_softc *sc) 1059 { 1060 int next; 1061 int i; 1062 1063 /* Get adapter SRAM size. */ 1064 sc->msk_ramsize = CSR_READ_1(sc, B2_E_0) * 4; 1065 if (bootverbose) 1066 device_printf(sc->msk_dev, 1067 "RAM buffer size : %dKB\n", sc->msk_ramsize); 1068 if (sc->msk_ramsize == 0) 1069 return (0); 1070 1071 sc->msk_pflags |= MSK_FLAG_RAMBUF; 1072 /* 1073 * Give receiver 2/3 of memory and round down to the multiple 1074 * of 1024. Tx/Rx RAM buffer size of Yukon II shoud be multiple 1075 * of 1024. 1076 */ 1077 sc->msk_rxqsize = rounddown((sc->msk_ramsize * 1024 * 2) / 3, 1024); 1078 sc->msk_txqsize = (sc->msk_ramsize * 1024) - sc->msk_rxqsize; 1079 for (i = 0, next = 0; i < sc->msk_num_port; i++) { 1080 sc->msk_rxqstart[i] = next; 1081 sc->msk_rxqend[i] = next + sc->msk_rxqsize - 1; 1082 next = sc->msk_rxqend[i] + 1; 1083 sc->msk_txqstart[i] = next; 1084 sc->msk_txqend[i] = next + sc->msk_txqsize - 1; 1085 next = sc->msk_txqend[i] + 1; 1086 if (bootverbose) { 1087 device_printf(sc->msk_dev, 1088 "Port %d : Rx Queue %dKB(0x%08x:0x%08x)\n", i, 1089 sc->msk_rxqsize / 1024, sc->msk_rxqstart[i], 1090 sc->msk_rxqend[i]); 1091 device_printf(sc->msk_dev, 1092 "Port %d : Tx Queue %dKB(0x%08x:0x%08x)\n", i, 1093 sc->msk_txqsize / 1024, sc->msk_txqstart[i], 1094 sc->msk_txqend[i]); 1095 } 1096 } 1097 1098 return (0); 1099 } 1100 1101 static void 1102 msk_phy_power(struct msk_softc *sc, int mode) 1103 { 1104 uint32_t our, val; 1105 int i; 1106 1107 switch (mode) { 1108 case MSK_PHY_POWERUP: 1109 /* Switch power to VCC (WA for VAUX problem). */ 1110 CSR_WRITE_1(sc, B0_POWER_CTRL, 1111 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON); 1112 /* Disable Core Clock Division, set Clock Select to 0. */ 1113 CSR_WRITE_4(sc, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS); 1114 1115 val = 0; 1116 if (sc->msk_hw_id == CHIP_ID_YUKON_XL && 1117 sc->msk_hw_rev > CHIP_REV_YU_XL_A1) { 1118 /* Enable bits are inverted. */ 1119 val = Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS | 1120 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS | 1121 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS; 1122 } 1123 /* 1124 * Enable PCI & Core Clock, enable clock gating for both Links. 1125 */ 1126 CSR_WRITE_1(sc, B2_Y2_CLK_GATE, val); 1127 1128 val = pci_read_config(sc->msk_dev, PCI_OUR_REG_1, 4); 1129 val &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD); 1130 if (sc->msk_hw_id == CHIP_ID_YUKON_XL) { 1131 if (sc->msk_hw_rev > CHIP_REV_YU_XL_A1) { 1132 /* Deassert Low Power for 1st PHY. */ 1133 val |= PCI_Y2_PHY1_COMA; 1134 if (sc->msk_num_port > 1) 1135 val |= PCI_Y2_PHY2_COMA; 1136 } 1137 } 1138 /* Release PHY from PowerDown/COMA mode. */ 1139 pci_write_config(sc->msk_dev, PCI_OUR_REG_1, val, 4); 1140 switch (sc->msk_hw_id) { 1141 case CHIP_ID_YUKON_EC_U: 1142 case CHIP_ID_YUKON_EX: 1143 case CHIP_ID_YUKON_FE_P: 1144 case CHIP_ID_YUKON_UL_2: 1145 CSR_WRITE_2(sc, B0_CTST, Y2_HW_WOL_OFF); 1146 1147 /* Enable all clocks. */ 1148 pci_write_config(sc->msk_dev, PCI_OUR_REG_3, 0, 4); 1149 our = pci_read_config(sc->msk_dev, PCI_OUR_REG_4, 4); 1150 our &= (PCI_FORCE_ASPM_REQUEST|PCI_ASPM_GPHY_LINK_DOWN| 1151 PCI_ASPM_INT_FIFO_EMPTY|PCI_ASPM_CLKRUN_REQUEST); 1152 /* Set all bits to 0 except bits 15..12. */ 1153 pci_write_config(sc->msk_dev, PCI_OUR_REG_4, our, 4); 1154 our = pci_read_config(sc->msk_dev, PCI_OUR_REG_5, 4); 1155 our &= PCI_CTL_TIM_VMAIN_AV_MSK; 1156 pci_write_config(sc->msk_dev, PCI_OUR_REG_5, our, 4); 1157 pci_write_config(sc->msk_dev, PCI_CFG_REG_1, 0, 4); 1158 /* 1159 * Disable status race, workaround for 1160 * Yukon EC Ultra & Yukon EX. 1161 */ 1162 val = CSR_READ_4(sc, B2_GP_IO); 1163 val |= GLB_GPIO_STAT_RACE_DIS; 1164 CSR_WRITE_4(sc, B2_GP_IO, val); 1165 CSR_READ_4(sc, B2_GP_IO); 1166 break; 1167 default: 1168 break; 1169 } 1170 for (i = 0; i < sc->msk_num_port; i++) { 1171 CSR_WRITE_2(sc, MR_ADDR(i, GMAC_LINK_CTRL), 1172 GMLC_RST_SET); 1173 CSR_WRITE_2(sc, MR_ADDR(i, GMAC_LINK_CTRL), 1174 GMLC_RST_CLR); 1175 } 1176 break; 1177 case MSK_PHY_POWERDOWN: 1178 val = pci_read_config(sc->msk_dev, PCI_OUR_REG_1, 4); 1179 val |= PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD; 1180 if (sc->msk_hw_id == CHIP_ID_YUKON_XL && 1181 sc->msk_hw_rev > CHIP_REV_YU_XL_A1) { 1182 val &= ~PCI_Y2_PHY1_COMA; 1183 if (sc->msk_num_port > 1) 1184 val &= ~PCI_Y2_PHY2_COMA; 1185 } 1186 pci_write_config(sc->msk_dev, PCI_OUR_REG_1, val, 4); 1187 1188 val = Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS | 1189 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS | 1190 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS; 1191 if (sc->msk_hw_id == CHIP_ID_YUKON_XL && 1192 sc->msk_hw_rev > CHIP_REV_YU_XL_A1) { 1193 /* Enable bits are inverted. */ 1194 val = 0; 1195 } 1196 /* 1197 * Disable PCI & Core Clock, disable clock gating for 1198 * both Links. 1199 */ 1200 CSR_WRITE_1(sc, B2_Y2_CLK_GATE, val); 1201 CSR_WRITE_1(sc, B0_POWER_CTRL, 1202 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_ON | PC_VCC_OFF); 1203 break; 1204 default: 1205 break; 1206 } 1207 } 1208 1209 static void 1210 mskc_reset(struct msk_softc *sc) 1211 { 1212 bus_addr_t addr; 1213 uint16_t status; 1214 uint32_t val; 1215 int i; 1216 1217 CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR); 1218 1219 /* Disable ASF. */ 1220 if (sc->msk_hw_id == CHIP_ID_YUKON_EX) { 1221 status = CSR_READ_2(sc, B28_Y2_ASF_HCU_CCSR); 1222 /* Clear AHB bridge & microcontroller reset. */ 1223 status &= ~(Y2_ASF_HCU_CCSR_AHB_RST | 1224 Y2_ASF_HCU_CCSR_CPU_RST_MODE); 1225 /* Clear ASF microcontroller state. */ 1226 status &= ~ Y2_ASF_HCU_CCSR_UC_STATE_MSK; 1227 CSR_WRITE_2(sc, B28_Y2_ASF_HCU_CCSR, status); 1228 } else 1229 CSR_WRITE_1(sc, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET); 1230 CSR_WRITE_2(sc, B0_CTST, Y2_ASF_DISABLE); 1231 1232 /* 1233 * Since we disabled ASF, S/W reset is required for Power Management. 1234 */ 1235 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); 1236 CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR); 1237 1238 /* Clear all error bits in the PCI status register. */ 1239 status = pci_read_config(sc->msk_dev, PCIR_STATUS, 2); 1240 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON); 1241 1242 pci_write_config(sc->msk_dev, PCIR_STATUS, status | 1243 PCIM_STATUS_PERR | PCIM_STATUS_SERR | PCIM_STATUS_RMABORT | 1244 PCIM_STATUS_RTABORT | PCIM_STATUS_PERRREPORT, 2); 1245 CSR_WRITE_2(sc, B0_CTST, CS_MRST_CLR); 1246 1247 switch (sc->msk_bustype) { 1248 case MSK_PEX_BUS: 1249 /* Clear all PEX errors. */ 1250 CSR_PCI_WRITE_4(sc, PEX_UNC_ERR_STAT, 0xffffffff); 1251 val = CSR_PCI_READ_4(sc, PEX_UNC_ERR_STAT); 1252 if ((val & PEX_RX_OV) != 0) { 1253 sc->msk_intrmask &= ~Y2_IS_HW_ERR; 1254 sc->msk_intrhwemask &= ~Y2_IS_PCI_EXP; 1255 } 1256 break; 1257 case MSK_PCI_BUS: 1258 case MSK_PCIX_BUS: 1259 /* Set Cache Line Size to 2(8bytes) if configured to 0. */ 1260 val = pci_read_config(sc->msk_dev, PCIR_CACHELNSZ, 1); 1261 if (val == 0) 1262 pci_write_config(sc->msk_dev, PCIR_CACHELNSZ, 2, 1); 1263 if (sc->msk_bustype == MSK_PCIX_BUS) { 1264 /* Set Cache Line Size opt. */ 1265 val = pci_read_config(sc->msk_dev, PCI_OUR_REG_1, 4); 1266 val |= PCI_CLS_OPT; 1267 pci_write_config(sc->msk_dev, PCI_OUR_REG_1, val, 4); 1268 } 1269 break; 1270 } 1271 /* Set PHY power state. */ 1272 msk_phy_power(sc, MSK_PHY_POWERUP); 1273 1274 /* Reset GPHY/GMAC Control */ 1275 for (i = 0; i < sc->msk_num_port; i++) { 1276 /* GPHY Control reset. */ 1277 CSR_WRITE_4(sc, MR_ADDR(i, GPHY_CTRL), GPC_RST_SET); 1278 CSR_WRITE_4(sc, MR_ADDR(i, GPHY_CTRL), GPC_RST_CLR); 1279 /* GMAC Control reset. */ 1280 CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), GMC_RST_SET); 1281 CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), GMC_RST_CLR); 1282 CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), GMC_F_LOOPB_OFF); 1283 if (sc->msk_hw_id == CHIP_ID_YUKON_EX) 1284 CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), 1285 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON | 1286 GMC_BYP_RETR_ON); 1287 } 1288 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 1289 1290 /* LED On. */ 1291 CSR_WRITE_2(sc, B0_CTST, Y2_LED_STAT_ON); 1292 1293 /* Clear TWSI IRQ. */ 1294 CSR_WRITE_4(sc, B2_I2C_IRQ, I2C_CLR_IRQ); 1295 1296 /* Turn off hardware timer. */ 1297 CSR_WRITE_1(sc, B2_TI_CTRL, TIM_STOP); 1298 CSR_WRITE_1(sc, B2_TI_CTRL, TIM_CLR_IRQ); 1299 1300 /* Turn off descriptor polling. */ 1301 CSR_WRITE_1(sc, B28_DPT_CTRL, DPT_STOP); 1302 1303 /* Turn off time stamps. */ 1304 CSR_WRITE_1(sc, GMAC_TI_ST_CTRL, GMT_ST_STOP); 1305 CSR_WRITE_1(sc, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ); 1306 1307 /* Configure timeout values. */ 1308 for (i = 0; i < sc->msk_num_port; i++) { 1309 CSR_WRITE_2(sc, SELECT_RAM_BUFFER(i, B3_RI_CTRL), RI_RST_SET); 1310 CSR_WRITE_2(sc, SELECT_RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR); 1311 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_R1), 1312 MSK_RI_TO_53); 1313 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XA1), 1314 MSK_RI_TO_53); 1315 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XS1), 1316 MSK_RI_TO_53); 1317 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_R1), 1318 MSK_RI_TO_53); 1319 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XA1), 1320 MSK_RI_TO_53); 1321 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XS1), 1322 MSK_RI_TO_53); 1323 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_R2), 1324 MSK_RI_TO_53); 1325 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XA2), 1326 MSK_RI_TO_53); 1327 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XS2), 1328 MSK_RI_TO_53); 1329 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_R2), 1330 MSK_RI_TO_53); 1331 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XA2), 1332 MSK_RI_TO_53); 1333 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XS2), 1334 MSK_RI_TO_53); 1335 } 1336 1337 /* Disable all interrupts. */ 1338 CSR_WRITE_4(sc, B0_HWE_IMSK, 0); 1339 CSR_READ_4(sc, B0_HWE_IMSK); 1340 CSR_WRITE_4(sc, B0_IMSK, 0); 1341 CSR_READ_4(sc, B0_IMSK); 1342 1343 /* 1344 * On dual port PCI-X card, there is an problem where status 1345 * can be received out of order due to split transactions. 1346 */ 1347 if (sc->msk_pcixcap != 0 && sc->msk_num_port > 1) { 1348 uint16_t pcix_cmd; 1349 1350 pcix_cmd = pci_read_config(sc->msk_dev, 1351 sc->msk_pcixcap + PCIXR_COMMAND, 2); 1352 /* Clear Max Outstanding Split Transactions. */ 1353 pcix_cmd &= ~PCIXM_COMMAND_MAX_SPLITS; 1354 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON); 1355 pci_write_config(sc->msk_dev, 1356 sc->msk_pcixcap + PCIXR_COMMAND, pcix_cmd, 2); 1357 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 1358 } 1359 if (sc->msk_expcap != 0) { 1360 /* Change Max. Read Request Size to 2048 bytes. */ 1361 if (pci_get_max_read_req(sc->msk_dev) == 512) 1362 pci_set_max_read_req(sc->msk_dev, 2048); 1363 } 1364 1365 /* Clear status list. */ 1366 bzero(sc->msk_stat_ring, 1367 sizeof(struct msk_stat_desc) * MSK_STAT_RING_CNT); 1368 sc->msk_stat_cons = 0; 1369 bus_dmamap_sync(sc->msk_stat_tag, sc->msk_stat_map, 1370 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1371 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_RST_SET); 1372 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_RST_CLR); 1373 /* Set the status list base address. */ 1374 addr = sc->msk_stat_ring_paddr; 1375 CSR_WRITE_4(sc, STAT_LIST_ADDR_LO, MSK_ADDR_LO(addr)); 1376 CSR_WRITE_4(sc, STAT_LIST_ADDR_HI, MSK_ADDR_HI(addr)); 1377 /* Set the status list last index. */ 1378 CSR_WRITE_2(sc, STAT_LAST_IDX, MSK_STAT_RING_CNT - 1); 1379 if (sc->msk_hw_id == CHIP_ID_YUKON_EC && 1380 sc->msk_hw_rev == CHIP_REV_YU_EC_A1) { 1381 /* WA for dev. #4.3 */ 1382 CSR_WRITE_2(sc, STAT_TX_IDX_TH, ST_TXTH_IDX_MASK); 1383 /* WA for dev. #4.18 */ 1384 CSR_WRITE_1(sc, STAT_FIFO_WM, 0x21); 1385 CSR_WRITE_1(sc, STAT_FIFO_ISR_WM, 0x07); 1386 } else { 1387 CSR_WRITE_2(sc, STAT_TX_IDX_TH, 0x0a); 1388 CSR_WRITE_1(sc, STAT_FIFO_WM, 0x10); 1389 if (sc->msk_hw_id == CHIP_ID_YUKON_XL && 1390 sc->msk_hw_rev == CHIP_REV_YU_XL_A0) 1391 CSR_WRITE_1(sc, STAT_FIFO_ISR_WM, 0x04); 1392 else 1393 CSR_WRITE_1(sc, STAT_FIFO_ISR_WM, 0x10); 1394 CSR_WRITE_4(sc, STAT_ISR_TIMER_INI, 0x0190); 1395 } 1396 /* 1397 * Use default value for STAT_ISR_TIMER_INI, STAT_LEV_TIMER_INI. 1398 */ 1399 CSR_WRITE_4(sc, STAT_TX_TIMER_INI, MSK_USECS(sc, 1000)); 1400 1401 /* Enable status unit. */ 1402 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_OP_ON); 1403 1404 CSR_WRITE_1(sc, STAT_TX_TIMER_CTRL, TIM_START); 1405 CSR_WRITE_1(sc, STAT_LEV_TIMER_CTRL, TIM_START); 1406 CSR_WRITE_1(sc, STAT_ISR_TIMER_CTRL, TIM_START); 1407 } 1408 1409 static int 1410 msk_probe(device_t dev) 1411 { 1412 struct msk_softc *sc; 1413 char desc[100]; 1414 1415 sc = device_get_softc(device_get_parent(dev)); 1416 /* 1417 * Not much to do here. We always know there will be 1418 * at least one GMAC present, and if there are two, 1419 * mskc_attach() will create a second device instance 1420 * for us. 1421 */ 1422 snprintf(desc, sizeof(desc), 1423 "Marvell Technology Group Ltd. %s Id 0x%02x Rev 0x%02x", 1424 model_name[sc->msk_hw_id - CHIP_ID_YUKON_XL], sc->msk_hw_id, 1425 sc->msk_hw_rev); 1426 device_set_desc_copy(dev, desc); 1427 1428 return (BUS_PROBE_DEFAULT); 1429 } 1430 1431 static int 1432 msk_attach(device_t dev) 1433 { 1434 struct msk_softc *sc; 1435 struct msk_if_softc *sc_if; 1436 struct ifnet *ifp; 1437 struct msk_mii_data *mmd; 1438 int i, port, error; 1439 uint8_t eaddr[6]; 1440 1441 if (dev == NULL) 1442 return (EINVAL); 1443 1444 error = 0; 1445 sc_if = device_get_softc(dev); 1446 sc = device_get_softc(device_get_parent(dev)); 1447 mmd = device_get_ivars(dev); 1448 port = mmd->port; 1449 1450 sc_if->msk_if_dev = dev; 1451 sc_if->msk_port = port; 1452 sc_if->msk_softc = sc; 1453 sc_if->msk_flags = sc->msk_pflags; 1454 sc->msk_if[port] = sc_if; 1455 /* Setup Tx/Rx queue register offsets. */ 1456 if (port == MSK_PORT_A) { 1457 sc_if->msk_txq = Q_XA1; 1458 sc_if->msk_txsq = Q_XS1; 1459 sc_if->msk_rxq = Q_R1; 1460 } else { 1461 sc_if->msk_txq = Q_XA2; 1462 sc_if->msk_txsq = Q_XS2; 1463 sc_if->msk_rxq = Q_R2; 1464 } 1465 1466 callout_init_mtx(&sc_if->msk_tick_ch, &sc_if->msk_softc->msk_mtx, 0); 1467 msk_sysctl_node(sc_if); 1468 1469 if ((error = msk_txrx_dma_alloc(sc_if) != 0)) 1470 goto fail; 1471 msk_rx_dma_jalloc(sc_if); 1472 1473 ifp = sc_if->msk_ifp = if_alloc(IFT_ETHER); 1474 if (ifp == NULL) { 1475 device_printf(sc_if->msk_if_dev, "can not if_alloc()\n"); 1476 error = ENOSPC; 1477 goto fail; 1478 } 1479 ifp->if_softc = sc_if; 1480 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1481 ifp->if_mtu = ETHERMTU; 1482 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1483 /* 1484 * IFCAP_RXCSUM capability is intentionally disabled as the hardware 1485 * has serious bug in Rx checksum offload for all Yukon II family 1486 * hardware. It seems there is a workaround to make it work somtimes. 1487 * However, the workaround also have to check OP code sequences to 1488 * verify whether the OP code is correct. Sometimes it should compute 1489 * IP/TCP/UDP checksum in driver in order to verify correctness of 1490 * checksum computed by hardware. If you have to compute checksum 1491 * with software to verify the hardware's checksum why have hardware 1492 * compute the checksum? I think there is no reason to spend time to 1493 * make Rx checksum offload work on Yukon II hardware. 1494 */ 1495 ifp->if_capabilities = IFCAP_TXCSUM | IFCAP_TSO4; 1496 /* 1497 * Enable Rx checksum offloading if controller support new 1498 * descriptor format. 1499 */ 1500 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) != 0 && 1501 (sc_if->msk_flags & MSK_FLAG_NORX_CSUM) == 0) 1502 ifp->if_capabilities |= IFCAP_RXCSUM; 1503 ifp->if_hwassist = MSK_CSUM_FEATURES | CSUM_TSO; 1504 ifp->if_capenable = ifp->if_capabilities; 1505 ifp->if_ioctl = msk_ioctl; 1506 ifp->if_start = msk_start; 1507 ifp->if_init = msk_init; 1508 IFQ_SET_MAXLEN(&ifp->if_snd, MSK_TX_RING_CNT - 1); 1509 ifp->if_snd.ifq_drv_maxlen = MSK_TX_RING_CNT - 1; 1510 IFQ_SET_READY(&ifp->if_snd); 1511 /* 1512 * Get station address for this interface. Note that 1513 * dual port cards actually come with three station 1514 * addresses: one for each port, plus an extra. The 1515 * extra one is used by the SysKonnect driver software 1516 * as a 'virtual' station address for when both ports 1517 * are operating in failover mode. Currently we don't 1518 * use this extra address. 1519 */ 1520 MSK_IF_LOCK(sc_if); 1521 for (i = 0; i < ETHER_ADDR_LEN; i++) 1522 eaddr[i] = CSR_READ_1(sc, B2_MAC_1 + (port * 8) + i); 1523 1524 /* 1525 * Call MI attach routine. Can't hold locks when calling into ether_*. 1526 */ 1527 MSK_IF_UNLOCK(sc_if); 1528 ether_ifattach(ifp, eaddr); 1529 MSK_IF_LOCK(sc_if); 1530 1531 /* VLAN capability setup */ 1532 ifp->if_capabilities |= IFCAP_VLAN_MTU; 1533 if ((sc_if->msk_flags & MSK_FLAG_NOHWVLAN) == 0) { 1534 /* 1535 * Due to Tx checksum offload hardware bugs, msk(4) manually 1536 * computes checksum for short frames. For VLAN tagged frames 1537 * this workaround does not work so disable checksum offload 1538 * for VLAN interface. 1539 */ 1540 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWTSO; 1541 /* 1542 * Enable Rx checksum offloading for VLAN taggedd frames 1543 * if controller support new descriptor format. 1544 */ 1545 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) != 0 && 1546 (sc_if->msk_flags & MSK_FLAG_NORX_CSUM) == 0) 1547 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM; 1548 } 1549 ifp->if_capenable = ifp->if_capabilities; 1550 1551 /* 1552 * Tell the upper layer(s) we support long frames. 1553 * Must appear after the call to ether_ifattach() because 1554 * ether_ifattach() sets ifi_hdrlen to the default value. 1555 */ 1556 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1557 1558 /* 1559 * Do miibus setup. 1560 */ 1561 MSK_IF_UNLOCK(sc_if); 1562 error = mii_phy_probe(dev, &sc_if->msk_miibus, msk_mediachange, 1563 msk_mediastatus); 1564 if (error != 0) { 1565 device_printf(sc_if->msk_if_dev, "no PHY found!\n"); 1566 ether_ifdetach(ifp); 1567 error = ENXIO; 1568 goto fail; 1569 } 1570 1571 fail: 1572 if (error != 0) { 1573 /* Access should be ok even though lock has been dropped */ 1574 sc->msk_if[port] = NULL; 1575 msk_detach(dev); 1576 } 1577 1578 return (error); 1579 } 1580 1581 /* 1582 * Attach the interface. Allocate softc structures, do ifmedia 1583 * setup and ethernet/BPF attach. 1584 */ 1585 static int 1586 mskc_attach(device_t dev) 1587 { 1588 struct msk_softc *sc; 1589 struct msk_mii_data *mmd; 1590 int error, msic, msir, reg; 1591 1592 sc = device_get_softc(dev); 1593 sc->msk_dev = dev; 1594 mtx_init(&sc->msk_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1595 MTX_DEF); 1596 1597 /* 1598 * Map control/status registers. 1599 */ 1600 pci_enable_busmaster(dev); 1601 1602 /* Allocate I/O resource */ 1603 #ifdef MSK_USEIOSPACE 1604 sc->msk_res_spec = msk_res_spec_io; 1605 #else 1606 sc->msk_res_spec = msk_res_spec_mem; 1607 #endif 1608 sc->msk_irq_spec = msk_irq_spec_legacy; 1609 error = bus_alloc_resources(dev, sc->msk_res_spec, sc->msk_res); 1610 if (error) { 1611 if (sc->msk_res_spec == msk_res_spec_mem) 1612 sc->msk_res_spec = msk_res_spec_io; 1613 else 1614 sc->msk_res_spec = msk_res_spec_mem; 1615 error = bus_alloc_resources(dev, sc->msk_res_spec, sc->msk_res); 1616 if (error) { 1617 device_printf(dev, "couldn't allocate %s resources\n", 1618 sc->msk_res_spec == msk_res_spec_mem ? "memory" : 1619 "I/O"); 1620 mtx_destroy(&sc->msk_mtx); 1621 return (ENXIO); 1622 } 1623 } 1624 1625 CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR); 1626 sc->msk_hw_id = CSR_READ_1(sc, B2_CHIP_ID); 1627 sc->msk_hw_rev = (CSR_READ_1(sc, B2_MAC_CFG) >> 4) & 0x0f; 1628 /* Bail out if chip is not recognized. */ 1629 if (sc->msk_hw_id < CHIP_ID_YUKON_XL || 1630 sc->msk_hw_id > CHIP_ID_YUKON_UL_2 || 1631 sc->msk_hw_id == CHIP_ID_YUKON_SUPR) { 1632 device_printf(dev, "unknown device: id=0x%02x, rev=0x%02x\n", 1633 sc->msk_hw_id, sc->msk_hw_rev); 1634 mtx_destroy(&sc->msk_mtx); 1635 return (ENXIO); 1636 } 1637 1638 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 1639 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 1640 OID_AUTO, "process_limit", CTLTYPE_INT | CTLFLAG_RW, 1641 &sc->msk_process_limit, 0, sysctl_hw_msk_proc_limit, "I", 1642 "max number of Rx events to process"); 1643 1644 sc->msk_process_limit = MSK_PROC_DEFAULT; 1645 error = resource_int_value(device_get_name(dev), device_get_unit(dev), 1646 "process_limit", &sc->msk_process_limit); 1647 if (error == 0) { 1648 if (sc->msk_process_limit < MSK_PROC_MIN || 1649 sc->msk_process_limit > MSK_PROC_MAX) { 1650 device_printf(dev, "process_limit value out of range; " 1651 "using default: %d\n", MSK_PROC_DEFAULT); 1652 sc->msk_process_limit = MSK_PROC_DEFAULT; 1653 } 1654 } 1655 1656 sc->msk_int_holdoff = MSK_INT_HOLDOFF_DEFAULT; 1657 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 1658 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 1659 "int_holdoff", CTLFLAG_RW, &sc->msk_int_holdoff, 0, 1660 "Maximum number of time to delay interrupts"); 1661 resource_int_value(device_get_name(dev), device_get_unit(dev), 1662 "int_holdoff", &sc->msk_int_holdoff); 1663 1664 /* Soft reset. */ 1665 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); 1666 CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR); 1667 sc->msk_pmd = CSR_READ_1(sc, B2_PMD_TYP); 1668 /* Check number of MACs. */ 1669 sc->msk_num_port = 1; 1670 if ((CSR_READ_1(sc, B2_Y2_HW_RES) & CFG_DUAL_MAC_MSK) == 1671 CFG_DUAL_MAC_MSK) { 1672 if (!(CSR_READ_1(sc, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC)) 1673 sc->msk_num_port++; 1674 } 1675 1676 /* Check bus type. */ 1677 if (pci_find_extcap(sc->msk_dev, PCIY_EXPRESS, ®) == 0) { 1678 sc->msk_bustype = MSK_PEX_BUS; 1679 sc->msk_expcap = reg; 1680 } else if (pci_find_extcap(sc->msk_dev, PCIY_PCIX, ®) == 0) { 1681 sc->msk_bustype = MSK_PCIX_BUS; 1682 sc->msk_pcixcap = reg; 1683 } else 1684 sc->msk_bustype = MSK_PCI_BUS; 1685 1686 switch (sc->msk_hw_id) { 1687 case CHIP_ID_YUKON_EC: 1688 sc->msk_clock = 125; /* 125 MHz */ 1689 sc->msk_pflags |= MSK_FLAG_JUMBO; 1690 break; 1691 case CHIP_ID_YUKON_EC_U: 1692 sc->msk_clock = 125; /* 125 MHz */ 1693 sc->msk_pflags |= MSK_FLAG_JUMBO | MSK_FLAG_JUMBO_NOCSUM; 1694 break; 1695 case CHIP_ID_YUKON_EX: 1696 sc->msk_clock = 125; /* 125 MHz */ 1697 sc->msk_pflags |= MSK_FLAG_JUMBO | MSK_FLAG_DESCV2 | 1698 MSK_FLAG_AUTOTX_CSUM; 1699 /* 1700 * Yukon Extreme seems to have silicon bug for 1701 * automatic Tx checksum calculation capability. 1702 */ 1703 if (sc->msk_hw_rev == CHIP_REV_YU_EX_B0) 1704 sc->msk_pflags &= ~MSK_FLAG_AUTOTX_CSUM; 1705 /* 1706 * Yukon Extreme A0 could not use store-and-forward 1707 * for jumbo frames, so disable Tx checksum 1708 * offloading for jumbo frames. 1709 */ 1710 if (sc->msk_hw_rev == CHIP_REV_YU_EX_A0) 1711 sc->msk_pflags |= MSK_FLAG_JUMBO_NOCSUM; 1712 break; 1713 case CHIP_ID_YUKON_FE: 1714 sc->msk_clock = 100; /* 100 MHz */ 1715 sc->msk_pflags |= MSK_FLAG_FASTETHER; 1716 break; 1717 case CHIP_ID_YUKON_FE_P: 1718 sc->msk_clock = 50; /* 50 MHz */ 1719 sc->msk_pflags |= MSK_FLAG_FASTETHER | MSK_FLAG_DESCV2 | 1720 MSK_FLAG_AUTOTX_CSUM; 1721 if (sc->msk_hw_rev == CHIP_REV_YU_FE_P_A0) { 1722 /* 1723 * XXX 1724 * FE+ A0 has status LE writeback bug so msk(4) 1725 * does not rely on status word of received frame 1726 * in msk_rxeof() which in turn disables all 1727 * hardware assistance bits reported by the status 1728 * word as well as validity of the recevied frame. 1729 * Just pass received frames to upper stack with 1730 * minimal test and let upper stack handle them. 1731 */ 1732 sc->msk_pflags |= MSK_FLAG_NOHWVLAN | 1733 MSK_FLAG_NORXCHK | MSK_FLAG_NORX_CSUM; 1734 } 1735 break; 1736 case CHIP_ID_YUKON_XL: 1737 sc->msk_clock = 156; /* 156 MHz */ 1738 sc->msk_pflags |= MSK_FLAG_JUMBO; 1739 break; 1740 case CHIP_ID_YUKON_UL_2: 1741 sc->msk_clock = 125; /* 125 MHz */ 1742 sc->msk_pflags |= MSK_FLAG_JUMBO; 1743 break; 1744 default: 1745 sc->msk_clock = 156; /* 156 MHz */ 1746 break; 1747 } 1748 1749 /* Allocate IRQ resources. */ 1750 msic = pci_msi_count(dev); 1751 if (bootverbose) 1752 device_printf(dev, "MSI count : %d\n", msic); 1753 if (legacy_intr != 0) 1754 msi_disable = 1; 1755 if (msi_disable == 0 && msic > 0) { 1756 msir = 1; 1757 if (pci_alloc_msi(dev, &msir) == 0) { 1758 if (msir == 1) { 1759 sc->msk_pflags |= MSK_FLAG_MSI; 1760 sc->msk_irq_spec = msk_irq_spec_msi; 1761 } else 1762 pci_release_msi(dev); 1763 } 1764 } 1765 1766 error = bus_alloc_resources(dev, sc->msk_irq_spec, sc->msk_irq); 1767 if (error) { 1768 device_printf(dev, "couldn't allocate IRQ resources\n"); 1769 goto fail; 1770 } 1771 1772 if ((error = msk_status_dma_alloc(sc)) != 0) 1773 goto fail; 1774 1775 /* Set base interrupt mask. */ 1776 sc->msk_intrmask = Y2_IS_HW_ERR | Y2_IS_STAT_BMU; 1777 sc->msk_intrhwemask = Y2_IS_TIST_OV | Y2_IS_MST_ERR | 1778 Y2_IS_IRQ_STAT | Y2_IS_PCI_EXP | Y2_IS_PCI_NEXP; 1779 1780 /* Reset the adapter. */ 1781 mskc_reset(sc); 1782 1783 if ((error = mskc_setup_rambuffer(sc)) != 0) 1784 goto fail; 1785 1786 sc->msk_devs[MSK_PORT_A] = device_add_child(dev, "msk", -1); 1787 if (sc->msk_devs[MSK_PORT_A] == NULL) { 1788 device_printf(dev, "failed to add child for PORT_A\n"); 1789 error = ENXIO; 1790 goto fail; 1791 } 1792 mmd = malloc(sizeof(struct msk_mii_data), M_DEVBUF, M_WAITOK | M_ZERO); 1793 if (mmd == NULL) { 1794 device_printf(dev, "failed to allocate memory for " 1795 "ivars of PORT_A\n"); 1796 error = ENXIO; 1797 goto fail; 1798 } 1799 mmd->port = MSK_PORT_A; 1800 mmd->pmd = sc->msk_pmd; 1801 if (sc->msk_pmd == 'L' || sc->msk_pmd == 'S' || sc->msk_pmd == 'P') 1802 mmd->mii_flags |= MIIF_HAVEFIBER; 1803 device_set_ivars(sc->msk_devs[MSK_PORT_A], mmd); 1804 1805 if (sc->msk_num_port > 1) { 1806 sc->msk_devs[MSK_PORT_B] = device_add_child(dev, "msk", -1); 1807 if (sc->msk_devs[MSK_PORT_B] == NULL) { 1808 device_printf(dev, "failed to add child for PORT_B\n"); 1809 error = ENXIO; 1810 goto fail; 1811 } 1812 mmd = malloc(sizeof(struct msk_mii_data), M_DEVBUF, M_WAITOK | M_ZERO); 1813 if (mmd == NULL) { 1814 device_printf(dev, "failed to allocate memory for " 1815 "ivars of PORT_B\n"); 1816 error = ENXIO; 1817 goto fail; 1818 } 1819 mmd->port = MSK_PORT_B; 1820 mmd->pmd = sc->msk_pmd; 1821 if (sc->msk_pmd == 'L' || sc->msk_pmd == 'S' || sc->msk_pmd == 'P') 1822 mmd->mii_flags |= MIIF_HAVEFIBER; 1823 device_set_ivars(sc->msk_devs[MSK_PORT_B], mmd); 1824 } 1825 1826 error = bus_generic_attach(dev); 1827 if (error) { 1828 device_printf(dev, "failed to attach port(s)\n"); 1829 goto fail; 1830 } 1831 1832 /* Hook interrupt last to avoid having to lock softc. */ 1833 error = bus_setup_intr(dev, sc->msk_irq[0], INTR_TYPE_NET | 1834 INTR_MPSAFE, NULL, msk_intr, sc, &sc->msk_intrhand); 1835 if (error != 0) { 1836 device_printf(dev, "couldn't set up interrupt handler\n"); 1837 goto fail; 1838 } 1839 fail: 1840 if (error != 0) 1841 mskc_detach(dev); 1842 1843 return (error); 1844 } 1845 1846 /* 1847 * Shutdown hardware and free up resources. This can be called any 1848 * time after the mutex has been initialized. It is called in both 1849 * the error case in attach and the normal detach case so it needs 1850 * to be careful about only freeing resources that have actually been 1851 * allocated. 1852 */ 1853 static int 1854 msk_detach(device_t dev) 1855 { 1856 struct msk_softc *sc; 1857 struct msk_if_softc *sc_if; 1858 struct ifnet *ifp; 1859 1860 sc_if = device_get_softc(dev); 1861 KASSERT(mtx_initialized(&sc_if->msk_softc->msk_mtx), 1862 ("msk mutex not initialized in msk_detach")); 1863 MSK_IF_LOCK(sc_if); 1864 1865 ifp = sc_if->msk_ifp; 1866 if (device_is_attached(dev)) { 1867 /* XXX */ 1868 sc_if->msk_flags |= MSK_FLAG_DETACH; 1869 msk_stop(sc_if); 1870 /* Can't hold locks while calling detach. */ 1871 MSK_IF_UNLOCK(sc_if); 1872 callout_drain(&sc_if->msk_tick_ch); 1873 ether_ifdetach(ifp); 1874 MSK_IF_LOCK(sc_if); 1875 } 1876 1877 /* 1878 * We're generally called from mskc_detach() which is using 1879 * device_delete_child() to get to here. It's already trashed 1880 * miibus for us, so don't do it here or we'll panic. 1881 * 1882 * if (sc_if->msk_miibus != NULL) { 1883 * device_delete_child(dev, sc_if->msk_miibus); 1884 * sc_if->msk_miibus = NULL; 1885 * } 1886 */ 1887 1888 msk_rx_dma_jfree(sc_if); 1889 msk_txrx_dma_free(sc_if); 1890 bus_generic_detach(dev); 1891 1892 if (ifp) 1893 if_free(ifp); 1894 sc = sc_if->msk_softc; 1895 sc->msk_if[sc_if->msk_port] = NULL; 1896 MSK_IF_UNLOCK(sc_if); 1897 1898 return (0); 1899 } 1900 1901 static int 1902 mskc_detach(device_t dev) 1903 { 1904 struct msk_softc *sc; 1905 1906 sc = device_get_softc(dev); 1907 KASSERT(mtx_initialized(&sc->msk_mtx), ("msk mutex not initialized")); 1908 1909 if (device_is_alive(dev)) { 1910 if (sc->msk_devs[MSK_PORT_A] != NULL) { 1911 free(device_get_ivars(sc->msk_devs[MSK_PORT_A]), 1912 M_DEVBUF); 1913 device_delete_child(dev, sc->msk_devs[MSK_PORT_A]); 1914 } 1915 if (sc->msk_devs[MSK_PORT_B] != NULL) { 1916 free(device_get_ivars(sc->msk_devs[MSK_PORT_B]), 1917 M_DEVBUF); 1918 device_delete_child(dev, sc->msk_devs[MSK_PORT_B]); 1919 } 1920 bus_generic_detach(dev); 1921 } 1922 1923 /* Disable all interrupts. */ 1924 CSR_WRITE_4(sc, B0_IMSK, 0); 1925 CSR_READ_4(sc, B0_IMSK); 1926 CSR_WRITE_4(sc, B0_HWE_IMSK, 0); 1927 CSR_READ_4(sc, B0_HWE_IMSK); 1928 1929 /* LED Off. */ 1930 CSR_WRITE_2(sc, B0_CTST, Y2_LED_STAT_OFF); 1931 1932 /* Put hardware reset. */ 1933 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); 1934 1935 msk_status_dma_free(sc); 1936 1937 if (sc->msk_intrhand) { 1938 bus_teardown_intr(dev, sc->msk_irq[0], sc->msk_intrhand); 1939 sc->msk_intrhand = NULL; 1940 } 1941 bus_release_resources(dev, sc->msk_irq_spec, sc->msk_irq); 1942 if ((sc->msk_pflags & MSK_FLAG_MSI) != 0) 1943 pci_release_msi(dev); 1944 bus_release_resources(dev, sc->msk_res_spec, sc->msk_res); 1945 mtx_destroy(&sc->msk_mtx); 1946 1947 return (0); 1948 } 1949 1950 struct msk_dmamap_arg { 1951 bus_addr_t msk_busaddr; 1952 }; 1953 1954 static void 1955 msk_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1956 { 1957 struct msk_dmamap_arg *ctx; 1958 1959 if (error != 0) 1960 return; 1961 ctx = arg; 1962 ctx->msk_busaddr = segs[0].ds_addr; 1963 } 1964 1965 /* Create status DMA region. */ 1966 static int 1967 msk_status_dma_alloc(struct msk_softc *sc) 1968 { 1969 struct msk_dmamap_arg ctx; 1970 int error; 1971 1972 error = bus_dma_tag_create( 1973 bus_get_dma_tag(sc->msk_dev), /* parent */ 1974 MSK_STAT_ALIGN, 0, /* alignment, boundary */ 1975 BUS_SPACE_MAXADDR, /* lowaddr */ 1976 BUS_SPACE_MAXADDR, /* highaddr */ 1977 NULL, NULL, /* filter, filterarg */ 1978 MSK_STAT_RING_SZ, /* maxsize */ 1979 1, /* nsegments */ 1980 MSK_STAT_RING_SZ, /* maxsegsize */ 1981 0, /* flags */ 1982 NULL, NULL, /* lockfunc, lockarg */ 1983 &sc->msk_stat_tag); 1984 if (error != 0) { 1985 device_printf(sc->msk_dev, 1986 "failed to create status DMA tag\n"); 1987 return (error); 1988 } 1989 1990 /* Allocate DMA'able memory and load the DMA map for status ring. */ 1991 error = bus_dmamem_alloc(sc->msk_stat_tag, 1992 (void **)&sc->msk_stat_ring, BUS_DMA_WAITOK | BUS_DMA_COHERENT | 1993 BUS_DMA_ZERO, &sc->msk_stat_map); 1994 if (error != 0) { 1995 device_printf(sc->msk_dev, 1996 "failed to allocate DMA'able memory for status ring\n"); 1997 return (error); 1998 } 1999 2000 ctx.msk_busaddr = 0; 2001 error = bus_dmamap_load(sc->msk_stat_tag, 2002 sc->msk_stat_map, sc->msk_stat_ring, MSK_STAT_RING_SZ, 2003 msk_dmamap_cb, &ctx, 0); 2004 if (error != 0) { 2005 device_printf(sc->msk_dev, 2006 "failed to load DMA'able memory for status ring\n"); 2007 return (error); 2008 } 2009 sc->msk_stat_ring_paddr = ctx.msk_busaddr; 2010 2011 return (0); 2012 } 2013 2014 static void 2015 msk_status_dma_free(struct msk_softc *sc) 2016 { 2017 2018 /* Destroy status block. */ 2019 if (sc->msk_stat_tag) { 2020 if (sc->msk_stat_map) { 2021 bus_dmamap_unload(sc->msk_stat_tag, sc->msk_stat_map); 2022 if (sc->msk_stat_ring) { 2023 bus_dmamem_free(sc->msk_stat_tag, 2024 sc->msk_stat_ring, sc->msk_stat_map); 2025 sc->msk_stat_ring = NULL; 2026 } 2027 sc->msk_stat_map = NULL; 2028 } 2029 bus_dma_tag_destroy(sc->msk_stat_tag); 2030 sc->msk_stat_tag = NULL; 2031 } 2032 } 2033 2034 static int 2035 msk_txrx_dma_alloc(struct msk_if_softc *sc_if) 2036 { 2037 struct msk_dmamap_arg ctx; 2038 struct msk_txdesc *txd; 2039 struct msk_rxdesc *rxd; 2040 bus_size_t rxalign; 2041 int error, i; 2042 2043 /* Create parent DMA tag. */ 2044 /* 2045 * XXX 2046 * It seems that Yukon II supports full 64bits DMA operations. But 2047 * it needs two descriptors(list elements) for 64bits DMA operations. 2048 * Since we don't know what DMA address mappings(32bits or 64bits) 2049 * would be used in advance for each mbufs, we limits its DMA space 2050 * to be in range of 32bits address space. Otherwise, we should check 2051 * what DMA address is used and chain another descriptor for the 2052 * 64bits DMA operation. This also means descriptor ring size is 2053 * variable. Limiting DMA address to be in 32bit address space greatly 2054 * simplyfies descriptor handling and possibly would increase 2055 * performance a bit due to efficient handling of descriptors. 2056 * Apart from harassing checksum offloading mechanisms, it seems 2057 * it's really bad idea to use a seperate descriptor for 64bit 2058 * DMA operation to save small descriptor memory. Anyway, I've 2059 * never seen these exotic scheme on ethernet interface hardware. 2060 */ 2061 error = bus_dma_tag_create( 2062 bus_get_dma_tag(sc_if->msk_if_dev), /* parent */ 2063 1, 0, /* alignment, boundary */ 2064 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 2065 BUS_SPACE_MAXADDR, /* highaddr */ 2066 NULL, NULL, /* filter, filterarg */ 2067 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 2068 0, /* nsegments */ 2069 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 2070 0, /* flags */ 2071 NULL, NULL, /* lockfunc, lockarg */ 2072 &sc_if->msk_cdata.msk_parent_tag); 2073 if (error != 0) { 2074 device_printf(sc_if->msk_if_dev, 2075 "failed to create parent DMA tag\n"); 2076 goto fail; 2077 } 2078 /* Create tag for Tx ring. */ 2079 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2080 MSK_RING_ALIGN, 0, /* alignment, boundary */ 2081 BUS_SPACE_MAXADDR, /* lowaddr */ 2082 BUS_SPACE_MAXADDR, /* highaddr */ 2083 NULL, NULL, /* filter, filterarg */ 2084 MSK_TX_RING_SZ, /* maxsize */ 2085 1, /* nsegments */ 2086 MSK_TX_RING_SZ, /* maxsegsize */ 2087 0, /* flags */ 2088 NULL, NULL, /* lockfunc, lockarg */ 2089 &sc_if->msk_cdata.msk_tx_ring_tag); 2090 if (error != 0) { 2091 device_printf(sc_if->msk_if_dev, 2092 "failed to create Tx ring DMA tag\n"); 2093 goto fail; 2094 } 2095 2096 /* Create tag for Rx ring. */ 2097 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2098 MSK_RING_ALIGN, 0, /* alignment, boundary */ 2099 BUS_SPACE_MAXADDR, /* lowaddr */ 2100 BUS_SPACE_MAXADDR, /* highaddr */ 2101 NULL, NULL, /* filter, filterarg */ 2102 MSK_RX_RING_SZ, /* maxsize */ 2103 1, /* nsegments */ 2104 MSK_RX_RING_SZ, /* maxsegsize */ 2105 0, /* flags */ 2106 NULL, NULL, /* lockfunc, lockarg */ 2107 &sc_if->msk_cdata.msk_rx_ring_tag); 2108 if (error != 0) { 2109 device_printf(sc_if->msk_if_dev, 2110 "failed to create Rx ring DMA tag\n"); 2111 goto fail; 2112 } 2113 2114 /* Create tag for Tx buffers. */ 2115 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2116 1, 0, /* alignment, boundary */ 2117 BUS_SPACE_MAXADDR, /* lowaddr */ 2118 BUS_SPACE_MAXADDR, /* highaddr */ 2119 NULL, NULL, /* filter, filterarg */ 2120 MSK_TSO_MAXSIZE, /* maxsize */ 2121 MSK_MAXTXSEGS, /* nsegments */ 2122 MSK_TSO_MAXSGSIZE, /* maxsegsize */ 2123 0, /* flags */ 2124 NULL, NULL, /* lockfunc, lockarg */ 2125 &sc_if->msk_cdata.msk_tx_tag); 2126 if (error != 0) { 2127 device_printf(sc_if->msk_if_dev, 2128 "failed to create Tx DMA tag\n"); 2129 goto fail; 2130 } 2131 2132 rxalign = 1; 2133 /* 2134 * Workaround hardware hang which seems to happen when Rx buffer 2135 * is not aligned on multiple of FIFO word(8 bytes). 2136 */ 2137 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) != 0) 2138 rxalign = MSK_RX_BUF_ALIGN; 2139 /* Create tag for Rx buffers. */ 2140 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2141 rxalign, 0, /* alignment, boundary */ 2142 BUS_SPACE_MAXADDR, /* lowaddr */ 2143 BUS_SPACE_MAXADDR, /* highaddr */ 2144 NULL, NULL, /* filter, filterarg */ 2145 MCLBYTES, /* maxsize */ 2146 1, /* nsegments */ 2147 MCLBYTES, /* maxsegsize */ 2148 0, /* flags */ 2149 NULL, NULL, /* lockfunc, lockarg */ 2150 &sc_if->msk_cdata.msk_rx_tag); 2151 if (error != 0) { 2152 device_printf(sc_if->msk_if_dev, 2153 "failed to create Rx DMA tag\n"); 2154 goto fail; 2155 } 2156 2157 /* Allocate DMA'able memory and load the DMA map for Tx ring. */ 2158 error = bus_dmamem_alloc(sc_if->msk_cdata.msk_tx_ring_tag, 2159 (void **)&sc_if->msk_rdata.msk_tx_ring, BUS_DMA_WAITOK | 2160 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc_if->msk_cdata.msk_tx_ring_map); 2161 if (error != 0) { 2162 device_printf(sc_if->msk_if_dev, 2163 "failed to allocate DMA'able memory for Tx ring\n"); 2164 goto fail; 2165 } 2166 2167 ctx.msk_busaddr = 0; 2168 error = bus_dmamap_load(sc_if->msk_cdata.msk_tx_ring_tag, 2169 sc_if->msk_cdata.msk_tx_ring_map, sc_if->msk_rdata.msk_tx_ring, 2170 MSK_TX_RING_SZ, msk_dmamap_cb, &ctx, 0); 2171 if (error != 0) { 2172 device_printf(sc_if->msk_if_dev, 2173 "failed to load DMA'able memory for Tx ring\n"); 2174 goto fail; 2175 } 2176 sc_if->msk_rdata.msk_tx_ring_paddr = ctx.msk_busaddr; 2177 2178 /* Allocate DMA'able memory and load the DMA map for Rx ring. */ 2179 error = bus_dmamem_alloc(sc_if->msk_cdata.msk_rx_ring_tag, 2180 (void **)&sc_if->msk_rdata.msk_rx_ring, BUS_DMA_WAITOK | 2181 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc_if->msk_cdata.msk_rx_ring_map); 2182 if (error != 0) { 2183 device_printf(sc_if->msk_if_dev, 2184 "failed to allocate DMA'able memory for Rx ring\n"); 2185 goto fail; 2186 } 2187 2188 ctx.msk_busaddr = 0; 2189 error = bus_dmamap_load(sc_if->msk_cdata.msk_rx_ring_tag, 2190 sc_if->msk_cdata.msk_rx_ring_map, sc_if->msk_rdata.msk_rx_ring, 2191 MSK_RX_RING_SZ, msk_dmamap_cb, &ctx, 0); 2192 if (error != 0) { 2193 device_printf(sc_if->msk_if_dev, 2194 "failed to load DMA'able memory for Rx ring\n"); 2195 goto fail; 2196 } 2197 sc_if->msk_rdata.msk_rx_ring_paddr = ctx.msk_busaddr; 2198 2199 /* Create DMA maps for Tx buffers. */ 2200 for (i = 0; i < MSK_TX_RING_CNT; i++) { 2201 txd = &sc_if->msk_cdata.msk_txdesc[i]; 2202 txd->tx_m = NULL; 2203 txd->tx_dmamap = NULL; 2204 error = bus_dmamap_create(sc_if->msk_cdata.msk_tx_tag, 0, 2205 &txd->tx_dmamap); 2206 if (error != 0) { 2207 device_printf(sc_if->msk_if_dev, 2208 "failed to create Tx dmamap\n"); 2209 goto fail; 2210 } 2211 } 2212 /* Create DMA maps for Rx buffers. */ 2213 if ((error = bus_dmamap_create(sc_if->msk_cdata.msk_rx_tag, 0, 2214 &sc_if->msk_cdata.msk_rx_sparemap)) != 0) { 2215 device_printf(sc_if->msk_if_dev, 2216 "failed to create spare Rx dmamap\n"); 2217 goto fail; 2218 } 2219 for (i = 0; i < MSK_RX_RING_CNT; i++) { 2220 rxd = &sc_if->msk_cdata.msk_rxdesc[i]; 2221 rxd->rx_m = NULL; 2222 rxd->rx_dmamap = NULL; 2223 error = bus_dmamap_create(sc_if->msk_cdata.msk_rx_tag, 0, 2224 &rxd->rx_dmamap); 2225 if (error != 0) { 2226 device_printf(sc_if->msk_if_dev, 2227 "failed to create Rx dmamap\n"); 2228 goto fail; 2229 } 2230 } 2231 2232 fail: 2233 return (error); 2234 } 2235 2236 static int 2237 msk_rx_dma_jalloc(struct msk_if_softc *sc_if) 2238 { 2239 struct msk_dmamap_arg ctx; 2240 struct msk_rxdesc *jrxd; 2241 bus_size_t rxalign; 2242 int error, i; 2243 2244 if (jumbo_disable != 0 || (sc_if->msk_flags & MSK_FLAG_JUMBO) == 0) { 2245 sc_if->msk_flags &= ~MSK_FLAG_JUMBO; 2246 device_printf(sc_if->msk_if_dev, 2247 "disabling jumbo frame support\n"); 2248 return (0); 2249 } 2250 /* Create tag for jumbo Rx ring. */ 2251 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2252 MSK_RING_ALIGN, 0, /* alignment, boundary */ 2253 BUS_SPACE_MAXADDR, /* lowaddr */ 2254 BUS_SPACE_MAXADDR, /* highaddr */ 2255 NULL, NULL, /* filter, filterarg */ 2256 MSK_JUMBO_RX_RING_SZ, /* maxsize */ 2257 1, /* nsegments */ 2258 MSK_JUMBO_RX_RING_SZ, /* maxsegsize */ 2259 0, /* flags */ 2260 NULL, NULL, /* lockfunc, lockarg */ 2261 &sc_if->msk_cdata.msk_jumbo_rx_ring_tag); 2262 if (error != 0) { 2263 device_printf(sc_if->msk_if_dev, 2264 "failed to create jumbo Rx ring DMA tag\n"); 2265 goto jumbo_fail; 2266 } 2267 2268 rxalign = 1; 2269 /* 2270 * Workaround hardware hang which seems to happen when Rx buffer 2271 * is not aligned on multiple of FIFO word(8 bytes). 2272 */ 2273 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) != 0) 2274 rxalign = MSK_RX_BUF_ALIGN; 2275 /* Create tag for jumbo Rx buffers. */ 2276 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2277 rxalign, 0, /* alignment, boundary */ 2278 BUS_SPACE_MAXADDR, /* lowaddr */ 2279 BUS_SPACE_MAXADDR, /* highaddr */ 2280 NULL, NULL, /* filter, filterarg */ 2281 MJUM9BYTES, /* maxsize */ 2282 1, /* nsegments */ 2283 MJUM9BYTES, /* maxsegsize */ 2284 0, /* flags */ 2285 NULL, NULL, /* lockfunc, lockarg */ 2286 &sc_if->msk_cdata.msk_jumbo_rx_tag); 2287 if (error != 0) { 2288 device_printf(sc_if->msk_if_dev, 2289 "failed to create jumbo Rx DMA tag\n"); 2290 goto jumbo_fail; 2291 } 2292 2293 /* Allocate DMA'able memory and load the DMA map for jumbo Rx ring. */ 2294 error = bus_dmamem_alloc(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 2295 (void **)&sc_if->msk_rdata.msk_jumbo_rx_ring, 2296 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 2297 &sc_if->msk_cdata.msk_jumbo_rx_ring_map); 2298 if (error != 0) { 2299 device_printf(sc_if->msk_if_dev, 2300 "failed to allocate DMA'able memory for jumbo Rx ring\n"); 2301 goto jumbo_fail; 2302 } 2303 2304 ctx.msk_busaddr = 0; 2305 error = bus_dmamap_load(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 2306 sc_if->msk_cdata.msk_jumbo_rx_ring_map, 2307 sc_if->msk_rdata.msk_jumbo_rx_ring, MSK_JUMBO_RX_RING_SZ, 2308 msk_dmamap_cb, &ctx, 0); 2309 if (error != 0) { 2310 device_printf(sc_if->msk_if_dev, 2311 "failed to load DMA'able memory for jumbo Rx ring\n"); 2312 goto jumbo_fail; 2313 } 2314 sc_if->msk_rdata.msk_jumbo_rx_ring_paddr = ctx.msk_busaddr; 2315 2316 /* Create DMA maps for jumbo Rx buffers. */ 2317 if ((error = bus_dmamap_create(sc_if->msk_cdata.msk_jumbo_rx_tag, 0, 2318 &sc_if->msk_cdata.msk_jumbo_rx_sparemap)) != 0) { 2319 device_printf(sc_if->msk_if_dev, 2320 "failed to create spare jumbo Rx dmamap\n"); 2321 goto jumbo_fail; 2322 } 2323 for (i = 0; i < MSK_JUMBO_RX_RING_CNT; i++) { 2324 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[i]; 2325 jrxd->rx_m = NULL; 2326 jrxd->rx_dmamap = NULL; 2327 error = bus_dmamap_create(sc_if->msk_cdata.msk_jumbo_rx_tag, 0, 2328 &jrxd->rx_dmamap); 2329 if (error != 0) { 2330 device_printf(sc_if->msk_if_dev, 2331 "failed to create jumbo Rx dmamap\n"); 2332 goto jumbo_fail; 2333 } 2334 } 2335 2336 return (0); 2337 2338 jumbo_fail: 2339 msk_rx_dma_jfree(sc_if); 2340 device_printf(sc_if->msk_if_dev, "disabling jumbo frame support " 2341 "due to resource shortage\n"); 2342 sc_if->msk_flags &= ~MSK_FLAG_JUMBO; 2343 return (error); 2344 } 2345 2346 static void 2347 msk_txrx_dma_free(struct msk_if_softc *sc_if) 2348 { 2349 struct msk_txdesc *txd; 2350 struct msk_rxdesc *rxd; 2351 int i; 2352 2353 /* Tx ring. */ 2354 if (sc_if->msk_cdata.msk_tx_ring_tag) { 2355 if (sc_if->msk_cdata.msk_tx_ring_map) 2356 bus_dmamap_unload(sc_if->msk_cdata.msk_tx_ring_tag, 2357 sc_if->msk_cdata.msk_tx_ring_map); 2358 if (sc_if->msk_cdata.msk_tx_ring_map && 2359 sc_if->msk_rdata.msk_tx_ring) 2360 bus_dmamem_free(sc_if->msk_cdata.msk_tx_ring_tag, 2361 sc_if->msk_rdata.msk_tx_ring, 2362 sc_if->msk_cdata.msk_tx_ring_map); 2363 sc_if->msk_rdata.msk_tx_ring = NULL; 2364 sc_if->msk_cdata.msk_tx_ring_map = NULL; 2365 bus_dma_tag_destroy(sc_if->msk_cdata.msk_tx_ring_tag); 2366 sc_if->msk_cdata.msk_tx_ring_tag = NULL; 2367 } 2368 /* Rx ring. */ 2369 if (sc_if->msk_cdata.msk_rx_ring_tag) { 2370 if (sc_if->msk_cdata.msk_rx_ring_map) 2371 bus_dmamap_unload(sc_if->msk_cdata.msk_rx_ring_tag, 2372 sc_if->msk_cdata.msk_rx_ring_map); 2373 if (sc_if->msk_cdata.msk_rx_ring_map && 2374 sc_if->msk_rdata.msk_rx_ring) 2375 bus_dmamem_free(sc_if->msk_cdata.msk_rx_ring_tag, 2376 sc_if->msk_rdata.msk_rx_ring, 2377 sc_if->msk_cdata.msk_rx_ring_map); 2378 sc_if->msk_rdata.msk_rx_ring = NULL; 2379 sc_if->msk_cdata.msk_rx_ring_map = NULL; 2380 bus_dma_tag_destroy(sc_if->msk_cdata.msk_rx_ring_tag); 2381 sc_if->msk_cdata.msk_rx_ring_tag = NULL; 2382 } 2383 /* Tx buffers. */ 2384 if (sc_if->msk_cdata.msk_tx_tag) { 2385 for (i = 0; i < MSK_TX_RING_CNT; i++) { 2386 txd = &sc_if->msk_cdata.msk_txdesc[i]; 2387 if (txd->tx_dmamap) { 2388 bus_dmamap_destroy(sc_if->msk_cdata.msk_tx_tag, 2389 txd->tx_dmamap); 2390 txd->tx_dmamap = NULL; 2391 } 2392 } 2393 bus_dma_tag_destroy(sc_if->msk_cdata.msk_tx_tag); 2394 sc_if->msk_cdata.msk_tx_tag = NULL; 2395 } 2396 /* Rx buffers. */ 2397 if (sc_if->msk_cdata.msk_rx_tag) { 2398 for (i = 0; i < MSK_RX_RING_CNT; i++) { 2399 rxd = &sc_if->msk_cdata.msk_rxdesc[i]; 2400 if (rxd->rx_dmamap) { 2401 bus_dmamap_destroy(sc_if->msk_cdata.msk_rx_tag, 2402 rxd->rx_dmamap); 2403 rxd->rx_dmamap = NULL; 2404 } 2405 } 2406 if (sc_if->msk_cdata.msk_rx_sparemap) { 2407 bus_dmamap_destroy(sc_if->msk_cdata.msk_rx_tag, 2408 sc_if->msk_cdata.msk_rx_sparemap); 2409 sc_if->msk_cdata.msk_rx_sparemap = 0; 2410 } 2411 bus_dma_tag_destroy(sc_if->msk_cdata.msk_rx_tag); 2412 sc_if->msk_cdata.msk_rx_tag = NULL; 2413 } 2414 if (sc_if->msk_cdata.msk_parent_tag) { 2415 bus_dma_tag_destroy(sc_if->msk_cdata.msk_parent_tag); 2416 sc_if->msk_cdata.msk_parent_tag = NULL; 2417 } 2418 } 2419 2420 static void 2421 msk_rx_dma_jfree(struct msk_if_softc *sc_if) 2422 { 2423 struct msk_rxdesc *jrxd; 2424 int i; 2425 2426 /* Jumbo Rx ring. */ 2427 if (sc_if->msk_cdata.msk_jumbo_rx_ring_tag) { 2428 if (sc_if->msk_cdata.msk_jumbo_rx_ring_map) 2429 bus_dmamap_unload(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 2430 sc_if->msk_cdata.msk_jumbo_rx_ring_map); 2431 if (sc_if->msk_cdata.msk_jumbo_rx_ring_map && 2432 sc_if->msk_rdata.msk_jumbo_rx_ring) 2433 bus_dmamem_free(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 2434 sc_if->msk_rdata.msk_jumbo_rx_ring, 2435 sc_if->msk_cdata.msk_jumbo_rx_ring_map); 2436 sc_if->msk_rdata.msk_jumbo_rx_ring = NULL; 2437 sc_if->msk_cdata.msk_jumbo_rx_ring_map = NULL; 2438 bus_dma_tag_destroy(sc_if->msk_cdata.msk_jumbo_rx_ring_tag); 2439 sc_if->msk_cdata.msk_jumbo_rx_ring_tag = NULL; 2440 } 2441 /* Jumbo Rx buffers. */ 2442 if (sc_if->msk_cdata.msk_jumbo_rx_tag) { 2443 for (i = 0; i < MSK_JUMBO_RX_RING_CNT; i++) { 2444 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[i]; 2445 if (jrxd->rx_dmamap) { 2446 bus_dmamap_destroy( 2447 sc_if->msk_cdata.msk_jumbo_rx_tag, 2448 jrxd->rx_dmamap); 2449 jrxd->rx_dmamap = NULL; 2450 } 2451 } 2452 if (sc_if->msk_cdata.msk_jumbo_rx_sparemap) { 2453 bus_dmamap_destroy(sc_if->msk_cdata.msk_jumbo_rx_tag, 2454 sc_if->msk_cdata.msk_jumbo_rx_sparemap); 2455 sc_if->msk_cdata.msk_jumbo_rx_sparemap = 0; 2456 } 2457 bus_dma_tag_destroy(sc_if->msk_cdata.msk_jumbo_rx_tag); 2458 sc_if->msk_cdata.msk_jumbo_rx_tag = NULL; 2459 } 2460 } 2461 2462 static int 2463 msk_encap(struct msk_if_softc *sc_if, struct mbuf **m_head) 2464 { 2465 struct msk_txdesc *txd, *txd_last; 2466 struct msk_tx_desc *tx_le; 2467 struct mbuf *m; 2468 bus_dmamap_t map; 2469 bus_dma_segment_t txsegs[MSK_MAXTXSEGS]; 2470 uint32_t control, csum, prod, si; 2471 uint16_t offset, tcp_offset, tso_mtu; 2472 int error, i, nseg, tso; 2473 2474 MSK_IF_LOCK_ASSERT(sc_if); 2475 2476 tcp_offset = offset = 0; 2477 m = *m_head; 2478 if (((sc_if->msk_flags & MSK_FLAG_AUTOTX_CSUM) == 0 && 2479 (m->m_pkthdr.csum_flags & MSK_CSUM_FEATURES) != 0) || 2480 ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0 && 2481 (m->m_pkthdr.csum_flags & CSUM_TSO) != 0)) { 2482 /* 2483 * Since mbuf has no protocol specific structure information 2484 * in it we have to inspect protocol information here to 2485 * setup TSO and checksum offload. I don't know why Marvell 2486 * made a such decision in chip design because other GigE 2487 * hardwares normally takes care of all these chores in 2488 * hardware. However, TSO performance of Yukon II is very 2489 * good such that it's worth to implement it. 2490 */ 2491 struct ether_header *eh; 2492 struct ip *ip; 2493 struct tcphdr *tcp; 2494 2495 if (M_WRITABLE(m) == 0) { 2496 /* Get a writable copy. */ 2497 m = m_dup(*m_head, M_DONTWAIT); 2498 m_freem(*m_head); 2499 if (m == NULL) { 2500 *m_head = NULL; 2501 return (ENOBUFS); 2502 } 2503 *m_head = m; 2504 } 2505 2506 offset = sizeof(struct ether_header); 2507 m = m_pullup(m, offset); 2508 if (m == NULL) { 2509 *m_head = NULL; 2510 return (ENOBUFS); 2511 } 2512 eh = mtod(m, struct ether_header *); 2513 /* Check if hardware VLAN insertion is off. */ 2514 if (eh->ether_type == htons(ETHERTYPE_VLAN)) { 2515 offset = sizeof(struct ether_vlan_header); 2516 m = m_pullup(m, offset); 2517 if (m == NULL) { 2518 *m_head = NULL; 2519 return (ENOBUFS); 2520 } 2521 } 2522 m = m_pullup(m, offset + sizeof(struct ip)); 2523 if (m == NULL) { 2524 *m_head = NULL; 2525 return (ENOBUFS); 2526 } 2527 ip = (struct ip *)(mtod(m, char *) + offset); 2528 offset += (ip->ip_hl << 2); 2529 tcp_offset = offset; 2530 /* 2531 * It seems that Yukon II has Tx checksum offload bug for 2532 * small TCP packets that's less than 60 bytes in size 2533 * (e.g. TCP window probe packet, pure ACK packet). 2534 * Common work around like padding with zeros to make the 2535 * frame minimum ethernet frame size didn't work at all. 2536 * Instead of disabling checksum offload completely we 2537 * resort to S/W checksum routine when we encounter short 2538 * TCP frames. 2539 * Short UDP packets appear to be handled correctly by 2540 * Yukon II. Also I assume this bug does not happen on 2541 * controllers that use newer descriptor format or 2542 * automatic Tx checksum calaulcation. 2543 */ 2544 if ((sc_if->msk_flags & MSK_FLAG_AUTOTX_CSUM) == 0 && 2545 (m->m_pkthdr.len < MSK_MIN_FRAMELEN) && 2546 (m->m_pkthdr.csum_flags & CSUM_TCP) != 0) { 2547 m = m_pullup(m, offset + sizeof(struct tcphdr)); 2548 if (m == NULL) { 2549 *m_head = NULL; 2550 return (ENOBUFS); 2551 } 2552 *(uint16_t *)(m->m_data + offset + 2553 m->m_pkthdr.csum_data) = in_cksum_skip(m, 2554 m->m_pkthdr.len, offset); 2555 m->m_pkthdr.csum_flags &= ~CSUM_TCP; 2556 } 2557 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 2558 m = m_pullup(m, offset + sizeof(struct tcphdr)); 2559 if (m == NULL) { 2560 *m_head = NULL; 2561 return (ENOBUFS); 2562 } 2563 tcp = (struct tcphdr *)(mtod(m, char *) + offset); 2564 offset += (tcp->th_off << 2); 2565 } 2566 *m_head = m; 2567 } 2568 2569 prod = sc_if->msk_cdata.msk_tx_prod; 2570 txd = &sc_if->msk_cdata.msk_txdesc[prod]; 2571 txd_last = txd; 2572 map = txd->tx_dmamap; 2573 error = bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_tx_tag, map, 2574 *m_head, txsegs, &nseg, BUS_DMA_NOWAIT); 2575 if (error == EFBIG) { 2576 m = m_collapse(*m_head, M_DONTWAIT, MSK_MAXTXSEGS); 2577 if (m == NULL) { 2578 m_freem(*m_head); 2579 *m_head = NULL; 2580 return (ENOBUFS); 2581 } 2582 *m_head = m; 2583 error = bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_tx_tag, 2584 map, *m_head, txsegs, &nseg, BUS_DMA_NOWAIT); 2585 if (error != 0) { 2586 m_freem(*m_head); 2587 *m_head = NULL; 2588 return (error); 2589 } 2590 } else if (error != 0) 2591 return (error); 2592 if (nseg == 0) { 2593 m_freem(*m_head); 2594 *m_head = NULL; 2595 return (EIO); 2596 } 2597 2598 /* Check number of available descriptors. */ 2599 if (sc_if->msk_cdata.msk_tx_cnt + nseg >= 2600 (MSK_TX_RING_CNT - MSK_RESERVED_TX_DESC_CNT)) { 2601 bus_dmamap_unload(sc_if->msk_cdata.msk_tx_tag, map); 2602 return (ENOBUFS); 2603 } 2604 2605 control = 0; 2606 tso = 0; 2607 tx_le = NULL; 2608 2609 /* Check TSO support. */ 2610 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 2611 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) != 0) 2612 tso_mtu = m->m_pkthdr.tso_segsz; 2613 else 2614 tso_mtu = offset + m->m_pkthdr.tso_segsz; 2615 if (tso_mtu != sc_if->msk_cdata.msk_tso_mtu) { 2616 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2617 tx_le->msk_addr = htole32(tso_mtu); 2618 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) != 0) 2619 tx_le->msk_control = htole32(OP_MSS | HW_OWNER); 2620 else 2621 tx_le->msk_control = 2622 htole32(OP_LRGLEN | HW_OWNER); 2623 sc_if->msk_cdata.msk_tx_cnt++; 2624 MSK_INC(prod, MSK_TX_RING_CNT); 2625 sc_if->msk_cdata.msk_tso_mtu = tso_mtu; 2626 } 2627 tso++; 2628 } 2629 /* Check if we have a VLAN tag to insert. */ 2630 if ((m->m_flags & M_VLANTAG) != 0) { 2631 if (tx_le == NULL) { 2632 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2633 tx_le->msk_addr = htole32(0); 2634 tx_le->msk_control = htole32(OP_VLAN | HW_OWNER | 2635 htons(m->m_pkthdr.ether_vtag)); 2636 sc_if->msk_cdata.msk_tx_cnt++; 2637 MSK_INC(prod, MSK_TX_RING_CNT); 2638 } else { 2639 tx_le->msk_control |= htole32(OP_VLAN | 2640 htons(m->m_pkthdr.ether_vtag)); 2641 } 2642 control |= INS_VLAN; 2643 } 2644 /* Check if we have to handle checksum offload. */ 2645 if (tso == 0 && (m->m_pkthdr.csum_flags & MSK_CSUM_FEATURES) != 0) { 2646 if ((sc_if->msk_flags & MSK_FLAG_AUTOTX_CSUM) != 0) 2647 control |= CALSUM; 2648 else { 2649 control |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM; 2650 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0) 2651 control |= UDPTCP; 2652 /* Checksum write position. */ 2653 csum = (tcp_offset + m->m_pkthdr.csum_data) & 0xffff; 2654 /* Checksum start position. */ 2655 csum |= (uint32_t)tcp_offset << 16; 2656 if (csum != sc_if->msk_cdata.msk_last_csum) { 2657 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2658 tx_le->msk_addr = htole32(csum); 2659 tx_le->msk_control = htole32(1 << 16 | 2660 (OP_TCPLISW | HW_OWNER)); 2661 sc_if->msk_cdata.msk_tx_cnt++; 2662 MSK_INC(prod, MSK_TX_RING_CNT); 2663 sc_if->msk_cdata.msk_last_csum = csum; 2664 } 2665 } 2666 } 2667 2668 si = prod; 2669 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2670 tx_le->msk_addr = htole32(MSK_ADDR_LO(txsegs[0].ds_addr)); 2671 if (tso == 0) 2672 tx_le->msk_control = htole32(txsegs[0].ds_len | control | 2673 OP_PACKET); 2674 else 2675 tx_le->msk_control = htole32(txsegs[0].ds_len | control | 2676 OP_LARGESEND); 2677 sc_if->msk_cdata.msk_tx_cnt++; 2678 MSK_INC(prod, MSK_TX_RING_CNT); 2679 2680 for (i = 1; i < nseg; i++) { 2681 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2682 tx_le->msk_addr = htole32(MSK_ADDR_LO(txsegs[i].ds_addr)); 2683 tx_le->msk_control = htole32(txsegs[i].ds_len | control | 2684 OP_BUFFER | HW_OWNER); 2685 sc_if->msk_cdata.msk_tx_cnt++; 2686 MSK_INC(prod, MSK_TX_RING_CNT); 2687 } 2688 /* Update producer index. */ 2689 sc_if->msk_cdata.msk_tx_prod = prod; 2690 2691 /* Set EOP on the last desciptor. */ 2692 prod = (prod + MSK_TX_RING_CNT - 1) % MSK_TX_RING_CNT; 2693 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2694 tx_le->msk_control |= htole32(EOP); 2695 2696 /* Turn the first descriptor ownership to hardware. */ 2697 tx_le = &sc_if->msk_rdata.msk_tx_ring[si]; 2698 tx_le->msk_control |= htole32(HW_OWNER); 2699 2700 txd = &sc_if->msk_cdata.msk_txdesc[prod]; 2701 map = txd_last->tx_dmamap; 2702 txd_last->tx_dmamap = txd->tx_dmamap; 2703 txd->tx_dmamap = map; 2704 txd->tx_m = m; 2705 2706 /* Sync descriptors. */ 2707 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_tag, map, BUS_DMASYNC_PREWRITE); 2708 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_ring_tag, 2709 sc_if->msk_cdata.msk_tx_ring_map, 2710 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2711 2712 return (0); 2713 } 2714 2715 static void 2716 msk_start(struct ifnet *ifp) 2717 { 2718 struct msk_if_softc *sc_if; 2719 2720 sc_if = ifp->if_softc; 2721 MSK_IF_LOCK(sc_if); 2722 msk_start_locked(ifp); 2723 MSK_IF_UNLOCK(sc_if); 2724 } 2725 2726 static void 2727 msk_start_locked(struct ifnet *ifp) 2728 { 2729 struct msk_if_softc *sc_if; 2730 struct mbuf *m_head; 2731 int enq; 2732 2733 sc_if = ifp->if_softc; 2734 MSK_IF_LOCK_ASSERT(sc_if); 2735 2736 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2737 IFF_DRV_RUNNING || (sc_if->msk_flags & MSK_FLAG_LINK) == 0) 2738 return; 2739 2740 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 2741 sc_if->msk_cdata.msk_tx_cnt < 2742 (MSK_TX_RING_CNT - MSK_RESERVED_TX_DESC_CNT); ) { 2743 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2744 if (m_head == NULL) 2745 break; 2746 /* 2747 * Pack the data into the transmit ring. If we 2748 * don't have room, set the OACTIVE flag and wait 2749 * for the NIC to drain the ring. 2750 */ 2751 if (msk_encap(sc_if, &m_head) != 0) { 2752 if (m_head == NULL) 2753 break; 2754 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2755 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2756 break; 2757 } 2758 2759 enq++; 2760 /* 2761 * If there's a BPF listener, bounce a copy of this frame 2762 * to him. 2763 */ 2764 ETHER_BPF_MTAP(ifp, m_head); 2765 } 2766 2767 if (enq > 0) { 2768 /* Transmit */ 2769 CSR_WRITE_2(sc_if->msk_softc, 2770 Y2_PREF_Q_ADDR(sc_if->msk_txq, PREF_UNIT_PUT_IDX_REG), 2771 sc_if->msk_cdata.msk_tx_prod); 2772 2773 /* Set a timeout in case the chip goes out to lunch. */ 2774 sc_if->msk_watchdog_timer = MSK_TX_TIMEOUT; 2775 } 2776 } 2777 2778 static void 2779 msk_watchdog(struct msk_if_softc *sc_if) 2780 { 2781 struct ifnet *ifp; 2782 2783 MSK_IF_LOCK_ASSERT(sc_if); 2784 2785 if (sc_if->msk_watchdog_timer == 0 || --sc_if->msk_watchdog_timer) 2786 return; 2787 ifp = sc_if->msk_ifp; 2788 if ((sc_if->msk_flags & MSK_FLAG_LINK) == 0) { 2789 if (bootverbose) 2790 if_printf(sc_if->msk_ifp, "watchdog timeout " 2791 "(missed link)\n"); 2792 ifp->if_oerrors++; 2793 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2794 msk_init_locked(sc_if); 2795 return; 2796 } 2797 2798 if_printf(ifp, "watchdog timeout\n"); 2799 ifp->if_oerrors++; 2800 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2801 msk_init_locked(sc_if); 2802 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2803 msk_start_locked(ifp); 2804 } 2805 2806 static int 2807 mskc_shutdown(device_t dev) 2808 { 2809 struct msk_softc *sc; 2810 int i; 2811 2812 sc = device_get_softc(dev); 2813 MSK_LOCK(sc); 2814 for (i = 0; i < sc->msk_num_port; i++) { 2815 if (sc->msk_if[i] != NULL) 2816 msk_stop(sc->msk_if[i]); 2817 } 2818 2819 /* Disable all interrupts. */ 2820 CSR_WRITE_4(sc, B0_IMSK, 0); 2821 CSR_READ_4(sc, B0_IMSK); 2822 CSR_WRITE_4(sc, B0_HWE_IMSK, 0); 2823 CSR_READ_4(sc, B0_HWE_IMSK); 2824 2825 /* Put hardware reset. */ 2826 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); 2827 2828 MSK_UNLOCK(sc); 2829 return (0); 2830 } 2831 2832 static int 2833 mskc_suspend(device_t dev) 2834 { 2835 struct msk_softc *sc; 2836 int i; 2837 2838 sc = device_get_softc(dev); 2839 2840 MSK_LOCK(sc); 2841 2842 for (i = 0; i < sc->msk_num_port; i++) { 2843 if (sc->msk_if[i] != NULL && sc->msk_if[i]->msk_ifp != NULL && 2844 ((sc->msk_if[i]->msk_ifp->if_drv_flags & 2845 IFF_DRV_RUNNING) != 0)) 2846 msk_stop(sc->msk_if[i]); 2847 } 2848 2849 /* Disable all interrupts. */ 2850 CSR_WRITE_4(sc, B0_IMSK, 0); 2851 CSR_READ_4(sc, B0_IMSK); 2852 CSR_WRITE_4(sc, B0_HWE_IMSK, 0); 2853 CSR_READ_4(sc, B0_HWE_IMSK); 2854 2855 msk_phy_power(sc, MSK_PHY_POWERDOWN); 2856 2857 /* Put hardware reset. */ 2858 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); 2859 sc->msk_pflags |= MSK_FLAG_SUSPEND; 2860 2861 MSK_UNLOCK(sc); 2862 2863 return (0); 2864 } 2865 2866 static int 2867 mskc_resume(device_t dev) 2868 { 2869 struct msk_softc *sc; 2870 int i; 2871 2872 sc = device_get_softc(dev); 2873 2874 MSK_LOCK(sc); 2875 2876 mskc_reset(sc); 2877 for (i = 0; i < sc->msk_num_port; i++) { 2878 if (sc->msk_if[i] != NULL && sc->msk_if[i]->msk_ifp != NULL && 2879 ((sc->msk_if[i]->msk_ifp->if_flags & IFF_UP) != 0)) { 2880 sc->msk_if[i]->msk_ifp->if_drv_flags &= 2881 ~IFF_DRV_RUNNING; 2882 msk_init_locked(sc->msk_if[i]); 2883 } 2884 } 2885 sc->msk_pflags &= ~MSK_FLAG_SUSPEND; 2886 2887 MSK_UNLOCK(sc); 2888 2889 return (0); 2890 } 2891 2892 #ifndef __NO_STRICT_ALIGNMENT 2893 static __inline void 2894 msk_fixup_rx(struct mbuf *m) 2895 { 2896 int i; 2897 uint16_t *src, *dst; 2898 2899 src = mtod(m, uint16_t *); 2900 dst = src - 3; 2901 2902 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 2903 *dst++ = *src++; 2904 2905 m->m_data -= (MSK_RX_BUF_ALIGN - ETHER_ALIGN); 2906 } 2907 #endif 2908 2909 static void 2910 msk_rxeof(struct msk_if_softc *sc_if, uint32_t status, uint32_t control, 2911 int len) 2912 { 2913 struct mbuf *m; 2914 struct ifnet *ifp; 2915 struct msk_rxdesc *rxd; 2916 int cons, rxlen; 2917 2918 ifp = sc_if->msk_ifp; 2919 2920 MSK_IF_LOCK_ASSERT(sc_if); 2921 2922 cons = sc_if->msk_cdata.msk_rx_cons; 2923 do { 2924 rxlen = status >> 16; 2925 if ((status & GMR_FS_VLAN) != 0 && 2926 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 2927 rxlen -= ETHER_VLAN_ENCAP_LEN; 2928 if ((sc_if->msk_flags & MSK_FLAG_NORXCHK) != 0) { 2929 /* 2930 * For controllers that returns bogus status code 2931 * just do minimal check and let upper stack 2932 * handle this frame. 2933 */ 2934 if (len > MSK_MAX_FRAMELEN || len < ETHER_HDR_LEN) { 2935 ifp->if_ierrors++; 2936 msk_discard_rxbuf(sc_if, cons); 2937 break; 2938 } 2939 } else if (len > sc_if->msk_framesize || 2940 ((status & GMR_FS_ANY_ERR) != 0) || 2941 ((status & GMR_FS_RX_OK) == 0) || (rxlen != len)) { 2942 /* Don't count flow-control packet as errors. */ 2943 if ((status & GMR_FS_GOOD_FC) == 0) 2944 ifp->if_ierrors++; 2945 msk_discard_rxbuf(sc_if, cons); 2946 break; 2947 } 2948 rxd = &sc_if->msk_cdata.msk_rxdesc[cons]; 2949 m = rxd->rx_m; 2950 if (msk_newbuf(sc_if, cons) != 0) { 2951 ifp->if_iqdrops++; 2952 /* Reuse old buffer. */ 2953 msk_discard_rxbuf(sc_if, cons); 2954 break; 2955 } 2956 m->m_pkthdr.rcvif = ifp; 2957 m->m_pkthdr.len = m->m_len = len; 2958 #ifndef __NO_STRICT_ALIGNMENT 2959 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) != 0) 2960 msk_fixup_rx(m); 2961 #endif 2962 ifp->if_ipackets++; 2963 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0 && 2964 (control & (CSS_IPV4 | CSS_IPFRAG)) == CSS_IPV4) { 2965 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 2966 if ((control & CSS_IPV4_CSUM_OK) != 0) 2967 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2968 if ((control & (CSS_TCP | CSS_UDP)) != 0 && 2969 (control & (CSS_TCPUDP_CSUM_OK)) != 0) { 2970 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID | 2971 CSUM_PSEUDO_HDR; 2972 m->m_pkthdr.csum_data = 0xffff; 2973 } 2974 } 2975 /* Check for VLAN tagged packets. */ 2976 if ((status & GMR_FS_VLAN) != 0 && 2977 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) { 2978 m->m_pkthdr.ether_vtag = sc_if->msk_vtag; 2979 m->m_flags |= M_VLANTAG; 2980 } 2981 MSK_IF_UNLOCK(sc_if); 2982 (*ifp->if_input)(ifp, m); 2983 MSK_IF_LOCK(sc_if); 2984 } while (0); 2985 2986 MSK_INC(sc_if->msk_cdata.msk_rx_cons, MSK_RX_RING_CNT); 2987 MSK_INC(sc_if->msk_cdata.msk_rx_prod, MSK_RX_RING_CNT); 2988 } 2989 2990 static void 2991 msk_jumbo_rxeof(struct msk_if_softc *sc_if, uint32_t status, uint32_t control, 2992 int len) 2993 { 2994 struct mbuf *m; 2995 struct ifnet *ifp; 2996 struct msk_rxdesc *jrxd; 2997 int cons, rxlen; 2998 2999 ifp = sc_if->msk_ifp; 3000 3001 MSK_IF_LOCK_ASSERT(sc_if); 3002 3003 cons = sc_if->msk_cdata.msk_rx_cons; 3004 do { 3005 rxlen = status >> 16; 3006 if ((status & GMR_FS_VLAN) != 0 && 3007 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 3008 rxlen -= ETHER_VLAN_ENCAP_LEN; 3009 if (len > sc_if->msk_framesize || 3010 ((status & GMR_FS_ANY_ERR) != 0) || 3011 ((status & GMR_FS_RX_OK) == 0) || (rxlen != len)) { 3012 /* Don't count flow-control packet as errors. */ 3013 if ((status & GMR_FS_GOOD_FC) == 0) 3014 ifp->if_ierrors++; 3015 msk_discard_jumbo_rxbuf(sc_if, cons); 3016 break; 3017 } 3018 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[cons]; 3019 m = jrxd->rx_m; 3020 if (msk_jumbo_newbuf(sc_if, cons) != 0) { 3021 ifp->if_iqdrops++; 3022 /* Reuse old buffer. */ 3023 msk_discard_jumbo_rxbuf(sc_if, cons); 3024 break; 3025 } 3026 m->m_pkthdr.rcvif = ifp; 3027 m->m_pkthdr.len = m->m_len = len; 3028 #ifndef __NO_STRICT_ALIGNMENT 3029 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) != 0) 3030 msk_fixup_rx(m); 3031 #endif 3032 ifp->if_ipackets++; 3033 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0 && 3034 (control & (CSS_IPV4 | CSS_IPFRAG)) == CSS_IPV4) { 3035 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 3036 if ((control & CSS_IPV4_CSUM_OK) != 0) 3037 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 3038 if ((control & (CSS_TCP | CSS_UDP)) != 0 && 3039 (control & (CSS_TCPUDP_CSUM_OK)) != 0) { 3040 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID | 3041 CSUM_PSEUDO_HDR; 3042 m->m_pkthdr.csum_data = 0xffff; 3043 } 3044 } 3045 /* Check for VLAN tagged packets. */ 3046 if ((status & GMR_FS_VLAN) != 0 && 3047 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) { 3048 m->m_pkthdr.ether_vtag = sc_if->msk_vtag; 3049 m->m_flags |= M_VLANTAG; 3050 } 3051 MSK_IF_UNLOCK(sc_if); 3052 (*ifp->if_input)(ifp, m); 3053 MSK_IF_LOCK(sc_if); 3054 } while (0); 3055 3056 MSK_INC(sc_if->msk_cdata.msk_rx_cons, MSK_JUMBO_RX_RING_CNT); 3057 MSK_INC(sc_if->msk_cdata.msk_rx_prod, MSK_JUMBO_RX_RING_CNT); 3058 } 3059 3060 static void 3061 msk_txeof(struct msk_if_softc *sc_if, int idx) 3062 { 3063 struct msk_txdesc *txd; 3064 struct msk_tx_desc *cur_tx; 3065 struct ifnet *ifp; 3066 uint32_t control; 3067 int cons, prog; 3068 3069 MSK_IF_LOCK_ASSERT(sc_if); 3070 3071 ifp = sc_if->msk_ifp; 3072 3073 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_ring_tag, 3074 sc_if->msk_cdata.msk_tx_ring_map, 3075 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3076 /* 3077 * Go through our tx ring and free mbufs for those 3078 * frames that have been sent. 3079 */ 3080 cons = sc_if->msk_cdata.msk_tx_cons; 3081 prog = 0; 3082 for (; cons != idx; MSK_INC(cons, MSK_TX_RING_CNT)) { 3083 if (sc_if->msk_cdata.msk_tx_cnt <= 0) 3084 break; 3085 prog++; 3086 cur_tx = &sc_if->msk_rdata.msk_tx_ring[cons]; 3087 control = le32toh(cur_tx->msk_control); 3088 sc_if->msk_cdata.msk_tx_cnt--; 3089 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3090 if ((control & EOP) == 0) 3091 continue; 3092 txd = &sc_if->msk_cdata.msk_txdesc[cons]; 3093 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_tag, txd->tx_dmamap, 3094 BUS_DMASYNC_POSTWRITE); 3095 bus_dmamap_unload(sc_if->msk_cdata.msk_tx_tag, txd->tx_dmamap); 3096 3097 ifp->if_opackets++; 3098 KASSERT(txd->tx_m != NULL, ("%s: freeing NULL mbuf!", 3099 __func__)); 3100 m_freem(txd->tx_m); 3101 txd->tx_m = NULL; 3102 } 3103 3104 if (prog > 0) { 3105 sc_if->msk_cdata.msk_tx_cons = cons; 3106 if (sc_if->msk_cdata.msk_tx_cnt == 0) 3107 sc_if->msk_watchdog_timer = 0; 3108 /* No need to sync LEs as we didn't update LEs. */ 3109 } 3110 } 3111 3112 static void 3113 msk_tick(void *xsc_if) 3114 { 3115 struct msk_if_softc *sc_if; 3116 struct mii_data *mii; 3117 3118 sc_if = xsc_if; 3119 3120 MSK_IF_LOCK_ASSERT(sc_if); 3121 3122 mii = device_get_softc(sc_if->msk_miibus); 3123 3124 mii_tick(mii); 3125 if ((sc_if->msk_flags & MSK_FLAG_LINK) == 0) 3126 msk_miibus_statchg(sc_if->msk_if_dev); 3127 msk_handle_events(sc_if->msk_softc); 3128 msk_watchdog(sc_if); 3129 callout_reset(&sc_if->msk_tick_ch, hz, msk_tick, sc_if); 3130 } 3131 3132 static void 3133 msk_intr_phy(struct msk_if_softc *sc_if) 3134 { 3135 uint16_t status; 3136 3137 msk_phy_readreg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_STAT); 3138 status = msk_phy_readreg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_STAT); 3139 /* Handle FIFO Underrun/Overflow? */ 3140 if ((status & PHY_M_IS_FIFO_ERROR)) 3141 device_printf(sc_if->msk_if_dev, 3142 "PHY FIFO underrun/overflow.\n"); 3143 } 3144 3145 static void 3146 msk_intr_gmac(struct msk_if_softc *sc_if) 3147 { 3148 struct msk_softc *sc; 3149 uint8_t status; 3150 3151 sc = sc_if->msk_softc; 3152 status = CSR_READ_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_SRC)); 3153 3154 /* GMAC Rx FIFO overrun. */ 3155 if ((status & GM_IS_RX_FF_OR) != 0) 3156 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), 3157 GMF_CLI_RX_FO); 3158 /* GMAC Tx FIFO underrun. */ 3159 if ((status & GM_IS_TX_FF_UR) != 0) { 3160 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 3161 GMF_CLI_TX_FU); 3162 device_printf(sc_if->msk_if_dev, "Tx FIFO underrun!\n"); 3163 /* 3164 * XXX 3165 * In case of Tx underrun, we may need to flush/reset 3166 * Tx MAC but that would also require resynchronization 3167 * with status LEs. Reintializing status LEs would 3168 * affect other port in dual MAC configuration so it 3169 * should be avoided as possible as we can. 3170 * Due to lack of documentation it's all vague guess but 3171 * it needs more investigation. 3172 */ 3173 } 3174 } 3175 3176 static void 3177 msk_handle_hwerr(struct msk_if_softc *sc_if, uint32_t status) 3178 { 3179 struct msk_softc *sc; 3180 3181 sc = sc_if->msk_softc; 3182 if ((status & Y2_IS_PAR_RD1) != 0) { 3183 device_printf(sc_if->msk_if_dev, 3184 "RAM buffer read parity error\n"); 3185 /* Clear IRQ. */ 3186 CSR_WRITE_2(sc, SELECT_RAM_BUFFER(sc_if->msk_port, B3_RI_CTRL), 3187 RI_CLR_RD_PERR); 3188 } 3189 if ((status & Y2_IS_PAR_WR1) != 0) { 3190 device_printf(sc_if->msk_if_dev, 3191 "RAM buffer write parity error\n"); 3192 /* Clear IRQ. */ 3193 CSR_WRITE_2(sc, SELECT_RAM_BUFFER(sc_if->msk_port, B3_RI_CTRL), 3194 RI_CLR_WR_PERR); 3195 } 3196 if ((status & Y2_IS_PAR_MAC1) != 0) { 3197 device_printf(sc_if->msk_if_dev, "Tx MAC parity error\n"); 3198 /* Clear IRQ. */ 3199 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 3200 GMF_CLI_TX_PE); 3201 } 3202 if ((status & Y2_IS_PAR_RX1) != 0) { 3203 device_printf(sc_if->msk_if_dev, "Rx parity error\n"); 3204 /* Clear IRQ. */ 3205 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_CLR_IRQ_PAR); 3206 } 3207 if ((status & (Y2_IS_TCP_TXS1 | Y2_IS_TCP_TXA1)) != 0) { 3208 device_printf(sc_if->msk_if_dev, "TCP segmentation error\n"); 3209 /* Clear IRQ. */ 3210 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_CLR_IRQ_TCP); 3211 } 3212 } 3213 3214 static void 3215 msk_intr_hwerr(struct msk_softc *sc) 3216 { 3217 uint32_t status; 3218 uint32_t tlphead[4]; 3219 3220 status = CSR_READ_4(sc, B0_HWE_ISRC); 3221 /* Time Stamp timer overflow. */ 3222 if ((status & Y2_IS_TIST_OV) != 0) 3223 CSR_WRITE_1(sc, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ); 3224 if ((status & Y2_IS_PCI_NEXP) != 0) { 3225 /* 3226 * PCI Express Error occured which is not described in PEX 3227 * spec. 3228 * This error is also mapped either to Master Abort( 3229 * Y2_IS_MST_ERR) or Target Abort (Y2_IS_IRQ_STAT) bit and 3230 * can only be cleared there. 3231 */ 3232 device_printf(sc->msk_dev, 3233 "PCI Express protocol violation error\n"); 3234 } 3235 3236 if ((status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) != 0) { 3237 uint16_t v16; 3238 3239 if ((status & Y2_IS_MST_ERR) != 0) 3240 device_printf(sc->msk_dev, 3241 "unexpected IRQ Status error\n"); 3242 else 3243 device_printf(sc->msk_dev, 3244 "unexpected IRQ Master error\n"); 3245 /* Reset all bits in the PCI status register. */ 3246 v16 = pci_read_config(sc->msk_dev, PCIR_STATUS, 2); 3247 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON); 3248 pci_write_config(sc->msk_dev, PCIR_STATUS, v16 | 3249 PCIM_STATUS_PERR | PCIM_STATUS_SERR | PCIM_STATUS_RMABORT | 3250 PCIM_STATUS_RTABORT | PCIM_STATUS_PERRREPORT, 2); 3251 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 3252 } 3253 3254 /* Check for PCI Express Uncorrectable Error. */ 3255 if ((status & Y2_IS_PCI_EXP) != 0) { 3256 uint32_t v32; 3257 3258 /* 3259 * On PCI Express bus bridges are called root complexes (RC). 3260 * PCI Express errors are recognized by the root complex too, 3261 * which requests the system to handle the problem. After 3262 * error occurence it may be that no access to the adapter 3263 * may be performed any longer. 3264 */ 3265 3266 v32 = CSR_PCI_READ_4(sc, PEX_UNC_ERR_STAT); 3267 if ((v32 & PEX_UNSUP_REQ) != 0) { 3268 /* Ignore unsupported request error. */ 3269 device_printf(sc->msk_dev, 3270 "Uncorrectable PCI Express error\n"); 3271 } 3272 if ((v32 & (PEX_FATAL_ERRORS | PEX_POIS_TLP)) != 0) { 3273 int i; 3274 3275 /* Get TLP header form Log Registers. */ 3276 for (i = 0; i < 4; i++) 3277 tlphead[i] = CSR_PCI_READ_4(sc, 3278 PEX_HEADER_LOG + i * 4); 3279 /* Check for vendor defined broadcast message. */ 3280 if (!(tlphead[0] == 0x73004001 && tlphead[1] == 0x7f)) { 3281 sc->msk_intrhwemask &= ~Y2_IS_PCI_EXP; 3282 CSR_WRITE_4(sc, B0_HWE_IMSK, 3283 sc->msk_intrhwemask); 3284 CSR_READ_4(sc, B0_HWE_IMSK); 3285 } 3286 } 3287 /* Clear the interrupt. */ 3288 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON); 3289 CSR_PCI_WRITE_4(sc, PEX_UNC_ERR_STAT, 0xffffffff); 3290 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 3291 } 3292 3293 if ((status & Y2_HWE_L1_MASK) != 0 && sc->msk_if[MSK_PORT_A] != NULL) 3294 msk_handle_hwerr(sc->msk_if[MSK_PORT_A], status); 3295 if ((status & Y2_HWE_L2_MASK) != 0 && sc->msk_if[MSK_PORT_B] != NULL) 3296 msk_handle_hwerr(sc->msk_if[MSK_PORT_B], status >> 8); 3297 } 3298 3299 static __inline void 3300 msk_rxput(struct msk_if_softc *sc_if) 3301 { 3302 struct msk_softc *sc; 3303 3304 sc = sc_if->msk_softc; 3305 if (sc_if->msk_framesize > (MCLBYTES - MSK_RX_BUF_ALIGN)) 3306 bus_dmamap_sync( 3307 sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 3308 sc_if->msk_cdata.msk_jumbo_rx_ring_map, 3309 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3310 else 3311 bus_dmamap_sync( 3312 sc_if->msk_cdata.msk_rx_ring_tag, 3313 sc_if->msk_cdata.msk_rx_ring_map, 3314 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3315 CSR_WRITE_2(sc, Y2_PREF_Q_ADDR(sc_if->msk_rxq, 3316 PREF_UNIT_PUT_IDX_REG), sc_if->msk_cdata.msk_rx_prod); 3317 } 3318 3319 static int 3320 msk_handle_events(struct msk_softc *sc) 3321 { 3322 struct msk_if_softc *sc_if; 3323 int rxput[2]; 3324 struct msk_stat_desc *sd; 3325 uint32_t control, status; 3326 int cons, len, port, rxprog; 3327 3328 /* Sync status LEs. */ 3329 bus_dmamap_sync(sc->msk_stat_tag, sc->msk_stat_map, 3330 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3331 3332 rxput[MSK_PORT_A] = rxput[MSK_PORT_B] = 0; 3333 rxprog = 0; 3334 cons = sc->msk_stat_cons; 3335 for (;;) { 3336 sd = &sc->msk_stat_ring[cons]; 3337 control = le32toh(sd->msk_control); 3338 if ((control & HW_OWNER) == 0) 3339 break; 3340 control &= ~HW_OWNER; 3341 sd->msk_control = htole32(control); 3342 status = le32toh(sd->msk_status); 3343 len = control & STLE_LEN_MASK; 3344 port = (control >> 16) & 0x01; 3345 sc_if = sc->msk_if[port]; 3346 if (sc_if == NULL) { 3347 device_printf(sc->msk_dev, "invalid port opcode " 3348 "0x%08x\n", control & STLE_OP_MASK); 3349 continue; 3350 } 3351 3352 switch (control & STLE_OP_MASK) { 3353 case OP_RXVLAN: 3354 sc_if->msk_vtag = ntohs(len); 3355 break; 3356 case OP_RXCHKSVLAN: 3357 sc_if->msk_vtag = ntohs(len); 3358 break; 3359 case OP_RXSTAT: 3360 if (sc_if->msk_framesize > 3361 (MCLBYTES - MSK_RX_BUF_ALIGN)) 3362 msk_jumbo_rxeof(sc_if, status, control, len); 3363 else 3364 msk_rxeof(sc_if, status, control, len); 3365 rxprog++; 3366 /* 3367 * Because there is no way to sync single Rx LE 3368 * put the DMA sync operation off until the end of 3369 * event processing. 3370 */ 3371 rxput[port]++; 3372 /* Update prefetch unit if we've passed water mark. */ 3373 if (rxput[port] >= sc_if->msk_cdata.msk_rx_putwm) { 3374 msk_rxput(sc_if); 3375 rxput[port] = 0; 3376 } 3377 break; 3378 case OP_TXINDEXLE: 3379 if (sc->msk_if[MSK_PORT_A] != NULL) 3380 msk_txeof(sc->msk_if[MSK_PORT_A], 3381 status & STLE_TXA1_MSKL); 3382 if (sc->msk_if[MSK_PORT_B] != NULL) 3383 msk_txeof(sc->msk_if[MSK_PORT_B], 3384 ((status & STLE_TXA2_MSKL) >> 3385 STLE_TXA2_SHIFTL) | 3386 ((len & STLE_TXA2_MSKH) << 3387 STLE_TXA2_SHIFTH)); 3388 break; 3389 default: 3390 device_printf(sc->msk_dev, "unhandled opcode 0x%08x\n", 3391 control & STLE_OP_MASK); 3392 break; 3393 } 3394 MSK_INC(cons, MSK_STAT_RING_CNT); 3395 if (rxprog > sc->msk_process_limit) 3396 break; 3397 } 3398 3399 sc->msk_stat_cons = cons; 3400 bus_dmamap_sync(sc->msk_stat_tag, sc->msk_stat_map, 3401 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3402 3403 if (rxput[MSK_PORT_A] > 0) 3404 msk_rxput(sc->msk_if[MSK_PORT_A]); 3405 if (rxput[MSK_PORT_B] > 0) 3406 msk_rxput(sc->msk_if[MSK_PORT_B]); 3407 3408 return (rxprog > sc->msk_process_limit ? EAGAIN : 0); 3409 } 3410 3411 static void 3412 msk_intr(void *xsc) 3413 { 3414 struct msk_softc *sc; 3415 struct msk_if_softc *sc_if0, *sc_if1; 3416 struct ifnet *ifp0, *ifp1; 3417 uint32_t status; 3418 int domore; 3419 3420 sc = xsc; 3421 MSK_LOCK(sc); 3422 3423 /* Reading B0_Y2_SP_ISRC2 masks further interrupts. */ 3424 status = CSR_READ_4(sc, B0_Y2_SP_ISRC2); 3425 if (status == 0 || status == 0xffffffff || 3426 (sc->msk_pflags & MSK_FLAG_SUSPEND) != 0 || 3427 (status & sc->msk_intrmask) == 0) { 3428 CSR_WRITE_4(sc, B0_Y2_SP_ICR, 2); 3429 return; 3430 } 3431 3432 sc_if0 = sc->msk_if[MSK_PORT_A]; 3433 sc_if1 = sc->msk_if[MSK_PORT_B]; 3434 ifp0 = ifp1 = NULL; 3435 if (sc_if0 != NULL) 3436 ifp0 = sc_if0->msk_ifp; 3437 if (sc_if1 != NULL) 3438 ifp1 = sc_if1->msk_ifp; 3439 3440 if ((status & Y2_IS_IRQ_PHY1) != 0 && sc_if0 != NULL) 3441 msk_intr_phy(sc_if0); 3442 if ((status & Y2_IS_IRQ_PHY2) != 0 && sc_if1 != NULL) 3443 msk_intr_phy(sc_if1); 3444 if ((status & Y2_IS_IRQ_MAC1) != 0 && sc_if0 != NULL) 3445 msk_intr_gmac(sc_if0); 3446 if ((status & Y2_IS_IRQ_MAC2) != 0 && sc_if1 != NULL) 3447 msk_intr_gmac(sc_if1); 3448 if ((status & (Y2_IS_CHK_RX1 | Y2_IS_CHK_RX2)) != 0) { 3449 device_printf(sc->msk_dev, "Rx descriptor error\n"); 3450 sc->msk_intrmask &= ~(Y2_IS_CHK_RX1 | Y2_IS_CHK_RX2); 3451 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask); 3452 CSR_READ_4(sc, B0_IMSK); 3453 } 3454 if ((status & (Y2_IS_CHK_TXA1 | Y2_IS_CHK_TXA2)) != 0) { 3455 device_printf(sc->msk_dev, "Tx descriptor error\n"); 3456 sc->msk_intrmask &= ~(Y2_IS_CHK_TXA1 | Y2_IS_CHK_TXA2); 3457 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask); 3458 CSR_READ_4(sc, B0_IMSK); 3459 } 3460 if ((status & Y2_IS_HW_ERR) != 0) 3461 msk_intr_hwerr(sc); 3462 3463 domore = msk_handle_events(sc); 3464 if ((status & Y2_IS_STAT_BMU) != 0 && domore == 0) 3465 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_CLR_IRQ); 3466 3467 /* Reenable interrupts. */ 3468 CSR_WRITE_4(sc, B0_Y2_SP_ICR, 2); 3469 3470 if (ifp0 != NULL && (ifp0->if_drv_flags & IFF_DRV_RUNNING) != 0 && 3471 !IFQ_DRV_IS_EMPTY(&ifp0->if_snd)) 3472 msk_start_locked(ifp0); 3473 if (ifp1 != NULL && (ifp1->if_drv_flags & IFF_DRV_RUNNING) != 0 && 3474 !IFQ_DRV_IS_EMPTY(&ifp1->if_snd)) 3475 msk_start_locked(ifp1); 3476 3477 MSK_UNLOCK(sc); 3478 } 3479 3480 static void 3481 msk_set_tx_stfwd(struct msk_if_softc *sc_if) 3482 { 3483 struct msk_softc *sc; 3484 struct ifnet *ifp; 3485 3486 ifp = sc_if->msk_ifp; 3487 sc = sc_if->msk_softc; 3488 switch (sc->msk_hw_id) { 3489 case CHIP_ID_YUKON_EX: 3490 if (sc->msk_hw_rev == CHIP_REV_YU_EX_A0) 3491 goto yukon_ex_workaround; 3492 if (ifp->if_mtu > ETHERMTU) 3493 CSR_WRITE_4(sc, 3494 MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 3495 TX_JUMBO_ENA | TX_STFW_ENA); 3496 else 3497 CSR_WRITE_4(sc, 3498 MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 3499 TX_JUMBO_DIS | TX_STFW_ENA); 3500 break; 3501 default: 3502 yukon_ex_workaround: 3503 if (ifp->if_mtu > ETHERMTU) { 3504 /* Set Tx GMAC FIFO Almost Empty Threshold. */ 3505 CSR_WRITE_4(sc, 3506 MR_ADDR(sc_if->msk_port, TX_GMF_AE_THR), 3507 MSK_ECU_JUMBO_WM << 16 | MSK_ECU_AE_THR); 3508 /* Disable Store & Forward mode for Tx. */ 3509 CSR_WRITE_4(sc, 3510 MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 3511 TX_JUMBO_ENA | TX_STFW_DIS); 3512 } else { 3513 /* Enable Store & Forward mode for Tx. */ 3514 CSR_WRITE_4(sc, 3515 MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 3516 TX_JUMBO_DIS | TX_STFW_ENA); 3517 } 3518 break; 3519 } 3520 } 3521 3522 static void 3523 msk_init(void *xsc) 3524 { 3525 struct msk_if_softc *sc_if = xsc; 3526 3527 MSK_IF_LOCK(sc_if); 3528 msk_init_locked(sc_if); 3529 MSK_IF_UNLOCK(sc_if); 3530 } 3531 3532 static void 3533 msk_init_locked(struct msk_if_softc *sc_if) 3534 { 3535 struct msk_softc *sc; 3536 struct ifnet *ifp; 3537 struct mii_data *mii; 3538 uint8_t *eaddr; 3539 uint16_t gmac; 3540 uint32_t reg; 3541 int error; 3542 3543 MSK_IF_LOCK_ASSERT(sc_if); 3544 3545 ifp = sc_if->msk_ifp; 3546 sc = sc_if->msk_softc; 3547 mii = device_get_softc(sc_if->msk_miibus); 3548 3549 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 3550 return; 3551 3552 error = 0; 3553 /* Cancel pending I/O and free all Rx/Tx buffers. */ 3554 msk_stop(sc_if); 3555 3556 if (ifp->if_mtu < ETHERMTU) 3557 sc_if->msk_framesize = ETHERMTU; 3558 else 3559 sc_if->msk_framesize = ifp->if_mtu; 3560 sc_if->msk_framesize += ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 3561 if (ifp->if_mtu > ETHERMTU && 3562 (sc_if->msk_flags & MSK_FLAG_JUMBO_NOCSUM) != 0) { 3563 ifp->if_hwassist &= ~(MSK_CSUM_FEATURES | CSUM_TSO); 3564 ifp->if_capenable &= ~(IFCAP_TSO4 | IFCAP_TXCSUM); 3565 } 3566 3567 /* GMAC Control reset. */ 3568 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_RST_SET); 3569 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_RST_CLR); 3570 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_F_LOOPB_OFF); 3571 if (sc->msk_hw_id == CHIP_ID_YUKON_EX) 3572 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), 3573 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON | 3574 GMC_BYP_RETR_ON); 3575 3576 /* 3577 * Initialize GMAC first such that speed/duplex/flow-control 3578 * parameters are renegotiated when interface is brought up. 3579 */ 3580 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, 0); 3581 3582 /* Dummy read the Interrupt Source Register. */ 3583 CSR_READ_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_SRC)); 3584 3585 /* Clear MIB stats. */ 3586 msk_stats_clear(sc_if); 3587 3588 /* Disable FCS. */ 3589 GMAC_WRITE_2(sc, sc_if->msk_port, GM_RX_CTRL, GM_RXCR_CRC_DIS); 3590 3591 /* Setup Transmit Control Register. */ 3592 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF)); 3593 3594 /* Setup Transmit Flow Control Register. */ 3595 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_FLOW_CTRL, 0xffff); 3596 3597 /* Setup Transmit Parameter Register. */ 3598 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_PARAM, 3599 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) | TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) | 3600 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) | TX_BACK_OFF_LIM(TX_BOF_LIM_DEF)); 3601 3602 gmac = DATA_BLIND_VAL(DATA_BLIND_DEF) | 3603 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF); 3604 3605 if (ifp->if_mtu > ETHERMTU) 3606 gmac |= GM_SMOD_JUMBO_ENA; 3607 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SERIAL_MODE, gmac); 3608 3609 /* Set station address. */ 3610 eaddr = IF_LLADDR(ifp); 3611 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_1L, 3612 eaddr[0] | (eaddr[1] << 8)); 3613 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_1M, 3614 eaddr[2] | (eaddr[3] << 8)); 3615 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_1H, 3616 eaddr[4] | (eaddr[5] << 8)); 3617 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_2L, 3618 eaddr[0] | (eaddr[1] << 8)); 3619 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_2M, 3620 eaddr[2] | (eaddr[3] << 8)); 3621 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_2H, 3622 eaddr[4] | (eaddr[5] << 8)); 3623 3624 /* Disable interrupts for counter overflows. */ 3625 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_IRQ_MSK, 0); 3626 GMAC_WRITE_2(sc, sc_if->msk_port, GM_RX_IRQ_MSK, 0); 3627 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TR_IRQ_MSK, 0); 3628 3629 /* Configure Rx MAC FIFO. */ 3630 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), GMF_RST_SET); 3631 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), GMF_RST_CLR); 3632 reg = GMF_OPER_ON | GMF_RX_F_FL_ON; 3633 if (sc->msk_hw_id == CHIP_ID_YUKON_FE_P || 3634 sc->msk_hw_id == CHIP_ID_YUKON_EX) 3635 reg |= GMF_RX_OVER_ON; 3636 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), reg); 3637 3638 /* Set receive filter. */ 3639 msk_rxfilter(sc_if); 3640 3641 if (sc->msk_hw_id == CHIP_ID_YUKON_XL) { 3642 /* Clear flush mask - HW bug. */ 3643 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_FL_MSK), 0); 3644 } else { 3645 /* Flush Rx MAC FIFO on any flow control or error. */ 3646 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_FL_MSK), 3647 GMR_FS_ANY_ERR); 3648 } 3649 3650 /* 3651 * Set Rx FIFO flush threshold to 64 bytes + 1 FIFO word 3652 * due to hardware hang on receipt of pause frames. 3653 */ 3654 reg = RX_GMF_FL_THR_DEF + 1; 3655 /* Another magic for Yukon FE+ - From Linux. */ 3656 if (sc->msk_hw_id == CHIP_ID_YUKON_FE_P && 3657 sc->msk_hw_rev == CHIP_REV_YU_FE_P_A0) 3658 reg = 0x178; 3659 CSR_WRITE_2(sc, MR_ADDR(sc_if->msk_port, RX_GMF_FL_THR), reg); 3660 3661 /* Configure Tx MAC FIFO. */ 3662 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_RST_SET); 3663 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_RST_CLR); 3664 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_OPER_ON); 3665 3666 /* Configure hardware VLAN tag insertion/stripping. */ 3667 msk_setvlan(sc_if, ifp); 3668 3669 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) == 0) { 3670 /* Set Rx Pause threshould. */ 3671 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, RX_GMF_LP_THR), 3672 MSK_ECU_LLPP); 3673 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, RX_GMF_UP_THR), 3674 MSK_ECU_ULPP); 3675 /* Configure store-and-forward for Tx. */ 3676 msk_set_tx_stfwd(sc_if); 3677 } 3678 3679 if (sc->msk_hw_id == CHIP_ID_YUKON_FE_P && 3680 sc->msk_hw_rev == CHIP_REV_YU_FE_P_A0) { 3681 /* Disable dynamic watermark - from Linux. */ 3682 reg = CSR_READ_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_EA)); 3683 reg &= ~0x03; 3684 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_EA), reg); 3685 } 3686 3687 /* 3688 * Disable Force Sync bit and Alloc bit in Tx RAM interface 3689 * arbiter as we don't use Sync Tx queue. 3690 */ 3691 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, TXA_CTRL), 3692 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC); 3693 /* Enable the RAM Interface Arbiter. */ 3694 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, TXA_CTRL), TXA_ENA_ARB); 3695 3696 /* Setup RAM buffer. */ 3697 msk_set_rambuffer(sc_if); 3698 3699 /* Disable Tx sync Queue. */ 3700 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txsq, RB_CTRL), RB_RST_SET); 3701 3702 /* Setup Tx Queue Bus Memory Interface. */ 3703 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_CLR_RESET); 3704 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_OPER_INIT); 3705 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_FIFO_OP_ON); 3706 CSR_WRITE_2(sc, Q_ADDR(sc_if->msk_txq, Q_WM), MSK_BMU_TX_WM); 3707 switch (sc->msk_hw_id) { 3708 case CHIP_ID_YUKON_EC_U: 3709 if (sc->msk_hw_rev == CHIP_REV_YU_EC_U_A0) { 3710 /* Fix for Yukon-EC Ultra: set BMU FIFO level */ 3711 CSR_WRITE_2(sc, Q_ADDR(sc_if->msk_txq, Q_AL), 3712 MSK_ECU_TXFF_LEV); 3713 } 3714 break; 3715 case CHIP_ID_YUKON_EX: 3716 /* 3717 * Yukon Extreme seems to have silicon bug for 3718 * automatic Tx checksum calculation capability. 3719 */ 3720 if (sc->msk_hw_rev == CHIP_REV_YU_EX_B0) 3721 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_F), 3722 F_TX_CHK_AUTO_OFF); 3723 break; 3724 } 3725 3726 /* Setup Rx Queue Bus Memory Interface. */ 3727 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_CLR_RESET); 3728 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_OPER_INIT); 3729 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_FIFO_OP_ON); 3730 CSR_WRITE_2(sc, Q_ADDR(sc_if->msk_rxq, Q_WM), MSK_BMU_RX_WM); 3731 if (sc->msk_hw_id == CHIP_ID_YUKON_EC_U && 3732 sc->msk_hw_rev >= CHIP_REV_YU_EC_U_A1) { 3733 /* MAC Rx RAM Read is controlled by hardware. */ 3734 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_F), F_M_RX_RAM_DIS); 3735 } 3736 3737 msk_set_prefetch(sc, sc_if->msk_txq, 3738 sc_if->msk_rdata.msk_tx_ring_paddr, MSK_TX_RING_CNT - 1); 3739 msk_init_tx_ring(sc_if); 3740 3741 /* Disable Rx checksum offload and RSS hash. */ 3742 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), 3743 BMU_DIS_RX_CHKSUM | BMU_DIS_RX_RSS_HASH); 3744 if (sc_if->msk_framesize > (MCLBYTES - MSK_RX_BUF_ALIGN)) { 3745 msk_set_prefetch(sc, sc_if->msk_rxq, 3746 sc_if->msk_rdata.msk_jumbo_rx_ring_paddr, 3747 MSK_JUMBO_RX_RING_CNT - 1); 3748 error = msk_init_jumbo_rx_ring(sc_if); 3749 } else { 3750 msk_set_prefetch(sc, sc_if->msk_rxq, 3751 sc_if->msk_rdata.msk_rx_ring_paddr, 3752 MSK_RX_RING_CNT - 1); 3753 error = msk_init_rx_ring(sc_if); 3754 } 3755 if (error != 0) { 3756 device_printf(sc_if->msk_if_dev, 3757 "initialization failed: no memory for Rx buffers\n"); 3758 msk_stop(sc_if); 3759 return; 3760 } 3761 3762 /* Configure interrupt handling. */ 3763 if (sc_if->msk_port == MSK_PORT_A) { 3764 sc->msk_intrmask |= Y2_IS_PORT_A; 3765 sc->msk_intrhwemask |= Y2_HWE_L1_MASK; 3766 } else { 3767 sc->msk_intrmask |= Y2_IS_PORT_B; 3768 sc->msk_intrhwemask |= Y2_HWE_L2_MASK; 3769 } 3770 /* Configure IRQ moderation mask. */ 3771 CSR_WRITE_4(sc, B2_IRQM_MSK, sc->msk_intrmask); 3772 if (sc->msk_int_holdoff > 0) { 3773 /* Configure initial IRQ moderation timer value. */ 3774 CSR_WRITE_4(sc, B2_IRQM_INI, 3775 MSK_USECS(sc, sc->msk_int_holdoff)); 3776 CSR_WRITE_4(sc, B2_IRQM_VAL, 3777 MSK_USECS(sc, sc->msk_int_holdoff)); 3778 /* Start IRQ moderation. */ 3779 CSR_WRITE_1(sc, B2_IRQM_CTRL, TIM_START); 3780 } 3781 CSR_WRITE_4(sc, B0_HWE_IMSK, sc->msk_intrhwemask); 3782 CSR_READ_4(sc, B0_HWE_IMSK); 3783 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask); 3784 CSR_READ_4(sc, B0_IMSK); 3785 3786 sc_if->msk_flags &= ~MSK_FLAG_LINK; 3787 mii_mediachg(mii); 3788 3789 ifp->if_drv_flags |= IFF_DRV_RUNNING; 3790 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3791 3792 callout_reset(&sc_if->msk_tick_ch, hz, msk_tick, sc_if); 3793 } 3794 3795 static void 3796 msk_set_rambuffer(struct msk_if_softc *sc_if) 3797 { 3798 struct msk_softc *sc; 3799 int ltpp, utpp; 3800 3801 sc = sc_if->msk_softc; 3802 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) == 0) 3803 return; 3804 3805 /* Setup Rx Queue. */ 3806 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_RST_CLR); 3807 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_START), 3808 sc->msk_rxqstart[sc_if->msk_port] / 8); 3809 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_END), 3810 sc->msk_rxqend[sc_if->msk_port] / 8); 3811 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_WP), 3812 sc->msk_rxqstart[sc_if->msk_port] / 8); 3813 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_RP), 3814 sc->msk_rxqstart[sc_if->msk_port] / 8); 3815 3816 utpp = (sc->msk_rxqend[sc_if->msk_port] + 1 - 3817 sc->msk_rxqstart[sc_if->msk_port] - MSK_RB_ULPP) / 8; 3818 ltpp = (sc->msk_rxqend[sc_if->msk_port] + 1 - 3819 sc->msk_rxqstart[sc_if->msk_port] - MSK_RB_LLPP_B) / 8; 3820 if (sc->msk_rxqsize < MSK_MIN_RXQ_SIZE) 3821 ltpp += (MSK_RB_LLPP_B - MSK_RB_LLPP_S) / 8; 3822 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_RX_UTPP), utpp); 3823 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_RX_LTPP), ltpp); 3824 /* Set Rx priority(RB_RX_UTHP/RB_RX_LTHP) thresholds? */ 3825 3826 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_ENA_OP_MD); 3827 CSR_READ_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL)); 3828 3829 /* Setup Tx Queue. */ 3830 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_RST_CLR); 3831 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_START), 3832 sc->msk_txqstart[sc_if->msk_port] / 8); 3833 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_END), 3834 sc->msk_txqend[sc_if->msk_port] / 8); 3835 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_WP), 3836 sc->msk_txqstart[sc_if->msk_port] / 8); 3837 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_RP), 3838 sc->msk_txqstart[sc_if->msk_port] / 8); 3839 /* Enable Store & Forward for Tx side. */ 3840 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_ENA_STFWD); 3841 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_ENA_OP_MD); 3842 CSR_READ_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL)); 3843 } 3844 3845 static void 3846 msk_set_prefetch(struct msk_softc *sc, int qaddr, bus_addr_t addr, 3847 uint32_t count) 3848 { 3849 3850 /* Reset the prefetch unit. */ 3851 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG), 3852 PREF_UNIT_RST_SET); 3853 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG), 3854 PREF_UNIT_RST_CLR); 3855 /* Set LE base address. */ 3856 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_ADDR_LOW_REG), 3857 MSK_ADDR_LO(addr)); 3858 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_ADDR_HI_REG), 3859 MSK_ADDR_HI(addr)); 3860 /* Set the list last index. */ 3861 CSR_WRITE_2(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_LAST_IDX_REG), 3862 count); 3863 /* Turn on prefetch unit. */ 3864 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG), 3865 PREF_UNIT_OP_ON); 3866 /* Dummy read to ensure write. */ 3867 CSR_READ_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG)); 3868 } 3869 3870 static void 3871 msk_stop(struct msk_if_softc *sc_if) 3872 { 3873 struct msk_softc *sc; 3874 struct msk_txdesc *txd; 3875 struct msk_rxdesc *rxd; 3876 struct msk_rxdesc *jrxd; 3877 struct ifnet *ifp; 3878 uint32_t val; 3879 int i; 3880 3881 MSK_IF_LOCK_ASSERT(sc_if); 3882 sc = sc_if->msk_softc; 3883 ifp = sc_if->msk_ifp; 3884 3885 callout_stop(&sc_if->msk_tick_ch); 3886 sc_if->msk_watchdog_timer = 0; 3887 3888 /* Disable interrupts. */ 3889 if (sc_if->msk_port == MSK_PORT_A) { 3890 sc->msk_intrmask &= ~Y2_IS_PORT_A; 3891 sc->msk_intrhwemask &= ~Y2_HWE_L1_MASK; 3892 } else { 3893 sc->msk_intrmask &= ~Y2_IS_PORT_B; 3894 sc->msk_intrhwemask &= ~Y2_HWE_L2_MASK; 3895 } 3896 CSR_WRITE_4(sc, B0_HWE_IMSK, sc->msk_intrhwemask); 3897 CSR_READ_4(sc, B0_HWE_IMSK); 3898 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask); 3899 CSR_READ_4(sc, B0_IMSK); 3900 3901 /* Disable Tx/Rx MAC. */ 3902 val = GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL); 3903 val &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA); 3904 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, val); 3905 /* Read again to ensure writing. */ 3906 GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL); 3907 /* Update stats and clear counters. */ 3908 msk_stats_update(sc_if); 3909 3910 /* Stop Tx BMU. */ 3911 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_STOP); 3912 val = CSR_READ_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR)); 3913 for (i = 0; i < MSK_TIMEOUT; i++) { 3914 if ((val & (BMU_STOP | BMU_IDLE)) == 0) { 3915 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), 3916 BMU_STOP); 3917 val = CSR_READ_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR)); 3918 } else 3919 break; 3920 DELAY(1); 3921 } 3922 if (i == MSK_TIMEOUT) 3923 device_printf(sc_if->msk_if_dev, "Tx BMU stop failed\n"); 3924 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), 3925 RB_RST_SET | RB_DIS_OP_MD); 3926 3927 /* Disable all GMAC interrupt. */ 3928 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_MSK), 0); 3929 /* Disable PHY interrupt. */ 3930 msk_phy_writereg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_MASK, 0); 3931 3932 /* Disable the RAM Interface Arbiter. */ 3933 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, TXA_CTRL), TXA_DIS_ARB); 3934 3935 /* Reset the PCI FIFO of the async Tx queue */ 3936 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), 3937 BMU_RST_SET | BMU_FIFO_RST); 3938 3939 /* Reset the Tx prefetch units. */ 3940 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(sc_if->msk_txq, PREF_UNIT_CTRL_REG), 3941 PREF_UNIT_RST_SET); 3942 3943 /* Reset the RAM Buffer async Tx queue. */ 3944 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_RST_SET); 3945 3946 /* Reset Tx MAC FIFO. */ 3947 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_RST_SET); 3948 /* Set Pause Off. */ 3949 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_PAUSE_OFF); 3950 3951 /* 3952 * The Rx Stop command will not work for Yukon-2 if the BMU does not 3953 * reach the end of packet and since we can't make sure that we have 3954 * incoming data, we must reset the BMU while it is not during a DMA 3955 * transfer. Since it is possible that the Rx path is still active, 3956 * the Rx RAM buffer will be stopped first, so any possible incoming 3957 * data will not trigger a DMA. After the RAM buffer is stopped, the 3958 * BMU is polled until any DMA in progress is ended and only then it 3959 * will be reset. 3960 */ 3961 3962 /* Disable the RAM Buffer receive queue. */ 3963 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_DIS_OP_MD); 3964 for (i = 0; i < MSK_TIMEOUT; i++) { 3965 if (CSR_READ_1(sc, RB_ADDR(sc_if->msk_rxq, Q_RSL)) == 3966 CSR_READ_1(sc, RB_ADDR(sc_if->msk_rxq, Q_RL))) 3967 break; 3968 DELAY(1); 3969 } 3970 if (i == MSK_TIMEOUT) 3971 device_printf(sc_if->msk_if_dev, "Rx BMU stop failed\n"); 3972 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), 3973 BMU_RST_SET | BMU_FIFO_RST); 3974 /* Reset the Rx prefetch unit. */ 3975 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_CTRL_REG), 3976 PREF_UNIT_RST_SET); 3977 /* Reset the RAM Buffer receive queue. */ 3978 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_RST_SET); 3979 /* Reset Rx MAC FIFO. */ 3980 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), GMF_RST_SET); 3981 3982 /* Free Rx and Tx mbufs still in the queues. */ 3983 for (i = 0; i < MSK_RX_RING_CNT; i++) { 3984 rxd = &sc_if->msk_cdata.msk_rxdesc[i]; 3985 if (rxd->rx_m != NULL) { 3986 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_tag, 3987 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 3988 bus_dmamap_unload(sc_if->msk_cdata.msk_rx_tag, 3989 rxd->rx_dmamap); 3990 m_freem(rxd->rx_m); 3991 rxd->rx_m = NULL; 3992 } 3993 } 3994 for (i = 0; i < MSK_JUMBO_RX_RING_CNT; i++) { 3995 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[i]; 3996 if (jrxd->rx_m != NULL) { 3997 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_tag, 3998 jrxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 3999 bus_dmamap_unload(sc_if->msk_cdata.msk_jumbo_rx_tag, 4000 jrxd->rx_dmamap); 4001 m_freem(jrxd->rx_m); 4002 jrxd->rx_m = NULL; 4003 } 4004 } 4005 for (i = 0; i < MSK_TX_RING_CNT; i++) { 4006 txd = &sc_if->msk_cdata.msk_txdesc[i]; 4007 if (txd->tx_m != NULL) { 4008 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_tag, 4009 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 4010 bus_dmamap_unload(sc_if->msk_cdata.msk_tx_tag, 4011 txd->tx_dmamap); 4012 m_freem(txd->tx_m); 4013 txd->tx_m = NULL; 4014 } 4015 } 4016 4017 /* 4018 * Mark the interface down. 4019 */ 4020 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 4021 sc_if->msk_flags &= ~MSK_FLAG_LINK; 4022 } 4023 4024 /* 4025 * When GM_PAR_MIB_CLR bit of GM_PHY_ADDR is set, reading lower 4026 * counter clears high 16 bits of the counter such that accessing 4027 * lower 16 bits should be the last operation. 4028 */ 4029 #define MSK_READ_MIB32(x, y) \ 4030 (((uint32_t)GMAC_READ_2(sc, x, (y) + 4)) << 16) + \ 4031 (uint32_t)GMAC_READ_2(sc, x, y) 4032 #define MSK_READ_MIB64(x, y) \ 4033 (((uint64_t)MSK_READ_MIB32(x, (y) + 8)) << 32) + \ 4034 (uint64_t)MSK_READ_MIB32(x, y) 4035 4036 static void 4037 msk_stats_clear(struct msk_if_softc *sc_if) 4038 { 4039 struct msk_softc *sc; 4040 uint32_t reg; 4041 uint16_t gmac; 4042 int i; 4043 4044 MSK_IF_LOCK_ASSERT(sc_if); 4045 4046 sc = sc_if->msk_softc; 4047 /* Set MIB Clear Counter Mode. */ 4048 gmac = GMAC_READ_2(sc, sc_if->msk_port, GM_PHY_ADDR); 4049 GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac | GM_PAR_MIB_CLR); 4050 /* Read all MIB Counters with Clear Mode set. */ 4051 for (i = GM_RXF_UC_OK; i <= GM_TXE_FIFO_UR; i += sizeof(uint32_t)) 4052 reg = MSK_READ_MIB32(sc_if->msk_port, i); 4053 /* Clear MIB Clear Counter Mode. */ 4054 gmac &= ~GM_PAR_MIB_CLR; 4055 GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac); 4056 } 4057 4058 static void 4059 msk_stats_update(struct msk_if_softc *sc_if) 4060 { 4061 struct msk_softc *sc; 4062 struct ifnet *ifp; 4063 struct msk_hw_stats *stats; 4064 uint16_t gmac; 4065 uint32_t reg; 4066 4067 MSK_IF_LOCK_ASSERT(sc_if); 4068 4069 ifp = sc_if->msk_ifp; 4070 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 4071 return; 4072 sc = sc_if->msk_softc; 4073 stats = &sc_if->msk_stats; 4074 /* Set MIB Clear Counter Mode. */ 4075 gmac = GMAC_READ_2(sc, sc_if->msk_port, GM_PHY_ADDR); 4076 GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac | GM_PAR_MIB_CLR); 4077 4078 /* Rx stats. */ 4079 stats->rx_ucast_frames += 4080 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_UC_OK); 4081 stats->rx_bcast_frames += 4082 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_BC_OK); 4083 stats->rx_pause_frames += 4084 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_MPAUSE); 4085 stats->rx_mcast_frames += 4086 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_MC_OK); 4087 stats->rx_crc_errs += 4088 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_FCS_ERR); 4089 reg = MSK_READ_MIB32(sc_if->msk_port, GM_RXF_SPARE1); 4090 stats->rx_good_octets += 4091 MSK_READ_MIB64(sc_if->msk_port, GM_RXO_OK_LO); 4092 stats->rx_bad_octets += 4093 MSK_READ_MIB64(sc_if->msk_port, GM_RXO_ERR_LO); 4094 stats->rx_runts += 4095 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_SHT); 4096 stats->rx_runt_errs += 4097 MSK_READ_MIB32(sc_if->msk_port, GM_RXE_FRAG); 4098 stats->rx_pkts_64 += 4099 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_64B); 4100 stats->rx_pkts_65_127 += 4101 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_127B); 4102 stats->rx_pkts_128_255 += 4103 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_255B); 4104 stats->rx_pkts_256_511 += 4105 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_511B); 4106 stats->rx_pkts_512_1023 += 4107 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_1023B); 4108 stats->rx_pkts_1024_1518 += 4109 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_1518B); 4110 stats->rx_pkts_1519_max += 4111 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_MAX_SZ); 4112 stats->rx_pkts_too_long += 4113 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_LNG_ERR); 4114 stats->rx_pkts_jabbers += 4115 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_JAB_PKT); 4116 reg = MSK_READ_MIB32(sc_if->msk_port, GM_RXF_SPARE2); 4117 stats->rx_fifo_oflows += 4118 MSK_READ_MIB32(sc_if->msk_port, GM_RXE_FIFO_OV); 4119 reg = MSK_READ_MIB32(sc_if->msk_port, GM_RXF_SPARE3); 4120 4121 /* Tx stats. */ 4122 stats->tx_ucast_frames += 4123 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_UC_OK); 4124 stats->tx_bcast_frames += 4125 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_BC_OK); 4126 stats->tx_pause_frames += 4127 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_MPAUSE); 4128 stats->tx_mcast_frames += 4129 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_MC_OK); 4130 stats->tx_octets += 4131 MSK_READ_MIB64(sc_if->msk_port, GM_TXO_OK_LO); 4132 stats->tx_pkts_64 += 4133 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_64B); 4134 stats->tx_pkts_65_127 += 4135 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_127B); 4136 stats->tx_pkts_128_255 += 4137 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_255B); 4138 stats->tx_pkts_256_511 += 4139 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_511B); 4140 stats->tx_pkts_512_1023 += 4141 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_1023B); 4142 stats->tx_pkts_1024_1518 += 4143 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_1518B); 4144 stats->tx_pkts_1519_max += 4145 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_MAX_SZ); 4146 reg = MSK_READ_MIB32(sc_if->msk_port, GM_TXF_SPARE1); 4147 stats->tx_colls += 4148 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_COL); 4149 stats->tx_late_colls += 4150 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_LAT_COL); 4151 stats->tx_excess_colls += 4152 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_ABO_COL); 4153 stats->tx_multi_colls += 4154 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_MUL_COL); 4155 stats->tx_single_colls += 4156 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_SNG_COL); 4157 stats->tx_underflows += 4158 MSK_READ_MIB32(sc_if->msk_port, GM_TXE_FIFO_UR); 4159 /* Clear MIB Clear Counter Mode. */ 4160 gmac &= ~GM_PAR_MIB_CLR; 4161 GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac); 4162 } 4163 4164 static int 4165 msk_sysctl_stat32(SYSCTL_HANDLER_ARGS) 4166 { 4167 struct msk_softc *sc; 4168 struct msk_if_softc *sc_if; 4169 uint32_t result, *stat; 4170 int off; 4171 4172 sc_if = (struct msk_if_softc *)arg1; 4173 sc = sc_if->msk_softc; 4174 off = arg2; 4175 stat = (uint32_t *)((uint8_t *)&sc_if->msk_stats + off); 4176 4177 MSK_IF_LOCK(sc_if); 4178 result = MSK_READ_MIB32(sc_if->msk_port, GM_MIB_CNT_BASE + off * 2); 4179 result += *stat; 4180 MSK_IF_UNLOCK(sc_if); 4181 4182 return (sysctl_handle_int(oidp, &result, 0, req)); 4183 } 4184 4185 static int 4186 msk_sysctl_stat64(SYSCTL_HANDLER_ARGS) 4187 { 4188 struct msk_softc *sc; 4189 struct msk_if_softc *sc_if; 4190 uint64_t result, *stat; 4191 int off; 4192 4193 sc_if = (struct msk_if_softc *)arg1; 4194 sc = sc_if->msk_softc; 4195 off = arg2; 4196 stat = (uint64_t *)((uint8_t *)&sc_if->msk_stats + off); 4197 4198 MSK_IF_LOCK(sc_if); 4199 result = MSK_READ_MIB64(sc_if->msk_port, GM_MIB_CNT_BASE + off * 2); 4200 result += *stat; 4201 MSK_IF_UNLOCK(sc_if); 4202 4203 return (sysctl_handle_quad(oidp, &result, 0, req)); 4204 } 4205 4206 #undef MSK_READ_MIB32 4207 #undef MSK_READ_MIB64 4208 4209 #define MSK_SYSCTL_STAT32(sc, c, o, p, n, d) \ 4210 SYSCTL_ADD_PROC(c, p, OID_AUTO, o, CTLTYPE_UINT | CTLFLAG_RD, \ 4211 sc, offsetof(struct msk_hw_stats, n), msk_sysctl_stat32, \ 4212 "IU", d) 4213 #define MSK_SYSCTL_STAT64(sc, c, o, p, n, d) \ 4214 SYSCTL_ADD_PROC(c, p, OID_AUTO, o, CTLTYPE_UINT | CTLFLAG_RD, \ 4215 sc, offsetof(struct msk_hw_stats, n), msk_sysctl_stat64, \ 4216 "Q", d) 4217 4218 static void 4219 msk_sysctl_node(struct msk_if_softc *sc_if) 4220 { 4221 struct sysctl_ctx_list *ctx; 4222 struct sysctl_oid_list *child, *schild; 4223 struct sysctl_oid *tree; 4224 4225 ctx = device_get_sysctl_ctx(sc_if->msk_if_dev); 4226 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc_if->msk_if_dev)); 4227 4228 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD, 4229 NULL, "MSK Statistics"); 4230 schild = child = SYSCTL_CHILDREN(tree); 4231 tree = SYSCTL_ADD_NODE(ctx, schild, OID_AUTO, "rx", CTLFLAG_RD, 4232 NULL, "MSK RX Statistics"); 4233 child = SYSCTL_CHILDREN(tree); 4234 MSK_SYSCTL_STAT32(sc_if, ctx, "ucast_frames", 4235 child, rx_ucast_frames, "Good unicast frames"); 4236 MSK_SYSCTL_STAT32(sc_if, ctx, "bcast_frames", 4237 child, rx_bcast_frames, "Good broadcast frames"); 4238 MSK_SYSCTL_STAT32(sc_if, ctx, "pause_frames", 4239 child, rx_pause_frames, "Pause frames"); 4240 MSK_SYSCTL_STAT32(sc_if, ctx, "mcast_frames", 4241 child, rx_mcast_frames, "Multicast frames"); 4242 MSK_SYSCTL_STAT32(sc_if, ctx, "crc_errs", 4243 child, rx_crc_errs, "CRC errors"); 4244 MSK_SYSCTL_STAT64(sc_if, ctx, "good_octets", 4245 child, rx_good_octets, "Good octets"); 4246 MSK_SYSCTL_STAT64(sc_if, ctx, "bad_octets", 4247 child, rx_bad_octets, "Bad octets"); 4248 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_64", 4249 child, rx_pkts_64, "64 bytes frames"); 4250 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_65_127", 4251 child, rx_pkts_65_127, "65 to 127 bytes frames"); 4252 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_128_255", 4253 child, rx_pkts_128_255, "128 to 255 bytes frames"); 4254 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_256_511", 4255 child, rx_pkts_256_511, "256 to 511 bytes frames"); 4256 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_512_1023", 4257 child, rx_pkts_512_1023, "512 to 1023 bytes frames"); 4258 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_1024_1518", 4259 child, rx_pkts_1024_1518, "1024 to 1518 bytes frames"); 4260 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_1519_max", 4261 child, rx_pkts_1519_max, "1519 to max frames"); 4262 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_too_long", 4263 child, rx_pkts_too_long, "frames too long"); 4264 MSK_SYSCTL_STAT32(sc_if, ctx, "jabbers", 4265 child, rx_pkts_jabbers, "Jabber errors"); 4266 MSK_SYSCTL_STAT32(sc_if, ctx, "overflows", 4267 child, rx_fifo_oflows, "FIFO overflows"); 4268 4269 tree = SYSCTL_ADD_NODE(ctx, schild, OID_AUTO, "tx", CTLFLAG_RD, 4270 NULL, "MSK TX Statistics"); 4271 child = SYSCTL_CHILDREN(tree); 4272 MSK_SYSCTL_STAT32(sc_if, ctx, "ucast_frames", 4273 child, tx_ucast_frames, "Unicast frames"); 4274 MSK_SYSCTL_STAT32(sc_if, ctx, "bcast_frames", 4275 child, tx_bcast_frames, "Broadcast frames"); 4276 MSK_SYSCTL_STAT32(sc_if, ctx, "pause_frames", 4277 child, tx_pause_frames, "Pause frames"); 4278 MSK_SYSCTL_STAT32(sc_if, ctx, "mcast_frames", 4279 child, tx_mcast_frames, "Multicast frames"); 4280 MSK_SYSCTL_STAT64(sc_if, ctx, "octets", 4281 child, tx_octets, "Octets"); 4282 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_64", 4283 child, tx_pkts_64, "64 bytes frames"); 4284 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_65_127", 4285 child, tx_pkts_65_127, "65 to 127 bytes frames"); 4286 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_128_255", 4287 child, tx_pkts_128_255, "128 to 255 bytes frames"); 4288 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_256_511", 4289 child, tx_pkts_256_511, "256 to 511 bytes frames"); 4290 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_512_1023", 4291 child, tx_pkts_512_1023, "512 to 1023 bytes frames"); 4292 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_1024_1518", 4293 child, tx_pkts_1024_1518, "1024 to 1518 bytes frames"); 4294 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_1519_max", 4295 child, tx_pkts_1519_max, "1519 to max frames"); 4296 MSK_SYSCTL_STAT32(sc_if, ctx, "colls", 4297 child, tx_colls, "Collisions"); 4298 MSK_SYSCTL_STAT32(sc_if, ctx, "late_colls", 4299 child, tx_late_colls, "Late collisions"); 4300 MSK_SYSCTL_STAT32(sc_if, ctx, "excess_colls", 4301 child, tx_excess_colls, "Excessive collisions"); 4302 MSK_SYSCTL_STAT32(sc_if, ctx, "multi_colls", 4303 child, tx_multi_colls, "Multiple collisions"); 4304 MSK_SYSCTL_STAT32(sc_if, ctx, "single_colls", 4305 child, tx_single_colls, "Single collisions"); 4306 MSK_SYSCTL_STAT32(sc_if, ctx, "underflows", 4307 child, tx_underflows, "FIFO underflows"); 4308 } 4309 4310 #undef MSK_SYSCTL_STAT32 4311 #undef MSK_SYSCTL_STAT64 4312 4313 static int 4314 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 4315 { 4316 int error, value; 4317 4318 if (!arg1) 4319 return (EINVAL); 4320 value = *(int *)arg1; 4321 error = sysctl_handle_int(oidp, &value, 0, req); 4322 if (error || !req->newptr) 4323 return (error); 4324 if (value < low || value > high) 4325 return (EINVAL); 4326 *(int *)arg1 = value; 4327 4328 return (0); 4329 } 4330 4331 static int 4332 sysctl_hw_msk_proc_limit(SYSCTL_HANDLER_ARGS) 4333 { 4334 4335 return (sysctl_int_range(oidp, arg1, arg2, req, MSK_PROC_MIN, 4336 MSK_PROC_MAX)); 4337 } 4338