1 /****************************************************************************** 2 * 3 * Name : sky2.c 4 * Project: Gigabit Ethernet Driver for FreeBSD 5.x/6.x 5 * Version: $Revision: 1.23 $ 6 * Date : $Date: 2005/12/22 09:04:11 $ 7 * Purpose: Main driver source file 8 * 9 *****************************************************************************/ 10 11 /****************************************************************************** 12 * 13 * LICENSE: 14 * Copyright (C) Marvell International Ltd. and/or its affiliates 15 * 16 * The computer program files contained in this folder ("Files") 17 * are provided to you under the BSD-type license terms provided 18 * below, and any use of such Files and any derivative works 19 * thereof created by you shall be governed by the following terms 20 * and conditions: 21 * 22 * - Redistributions of source code must retain the above copyright 23 * notice, this list of conditions and the following disclaimer. 24 * - Redistributions in binary form must reproduce the above 25 * copyright notice, this list of conditions and the following 26 * disclaimer in the documentation and/or other materials provided 27 * with the distribution. 28 * - Neither the name of Marvell nor the names of its contributors 29 * may be used to endorse or promote products derived from this 30 * software without specific prior written permission. 31 * 32 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 33 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 34 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 35 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 36 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 37 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 38 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 39 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 40 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 41 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 42 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED 43 * OF THE POSSIBILITY OF SUCH DAMAGE. 44 * /LICENSE 45 * 46 *****************************************************************************/ 47 48 /*- 49 * Copyright (c) 1997, 1998, 1999, 2000 50 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 51 * 52 * Redistribution and use in source and binary forms, with or without 53 * modification, are permitted provided that the following conditions 54 * are met: 55 * 1. Redistributions of source code must retain the above copyright 56 * notice, this list of conditions and the following disclaimer. 57 * 2. Redistributions in binary form must reproduce the above copyright 58 * notice, this list of conditions and the following disclaimer in the 59 * documentation and/or other materials provided with the distribution. 60 * 3. All advertising materials mentioning features or use of this software 61 * must display the following acknowledgement: 62 * This product includes software developed by Bill Paul. 63 * 4. Neither the name of the author nor the names of any co-contributors 64 * may be used to endorse or promote products derived from this software 65 * without specific prior written permission. 66 * 67 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 68 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 69 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 70 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 71 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 72 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 73 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 74 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 75 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 76 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 77 * THE POSSIBILITY OF SUCH DAMAGE. 78 */ 79 /*- 80 * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu> 81 * 82 * Permission to use, copy, modify, and distribute this software for any 83 * purpose with or without fee is hereby granted, provided that the above 84 * copyright notice and this permission notice appear in all copies. 85 * 86 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 87 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 88 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 89 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 90 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 91 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 92 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 93 */ 94 95 /* 96 * Device driver for the Marvell Yukon II Ethernet controller. 97 * Due to lack of documentation, this driver is based on the code from 98 * sk(4) and Marvell's myk(4) driver for FreeBSD 5.x. 99 */ 100 101 #include <sys/cdefs.h> 102 __FBSDID("$FreeBSD$"); 103 104 #include <sys/param.h> 105 #include <sys/systm.h> 106 #include <sys/bus.h> 107 #include <sys/endian.h> 108 #include <sys/mbuf.h> 109 #include <sys/malloc.h> 110 #include <sys/kernel.h> 111 #include <sys/module.h> 112 #include <sys/socket.h> 113 #include <sys/sockio.h> 114 #include <sys/queue.h> 115 #include <sys/sysctl.h> 116 #include <sys/taskqueue.h> 117 118 #include <net/bpf.h> 119 #include <net/ethernet.h> 120 #include <net/if.h> 121 #include <net/if_arp.h> 122 #include <net/if_dl.h> 123 #include <net/if_media.h> 124 #include <net/if_types.h> 125 #include <net/if_vlan_var.h> 126 127 #include <netinet/in.h> 128 #include <netinet/in_systm.h> 129 #include <netinet/ip.h> 130 #include <netinet/tcp.h> 131 #include <netinet/udp.h> 132 133 #include <machine/bus.h> 134 #include <machine/in_cksum.h> 135 #include <machine/resource.h> 136 #include <sys/rman.h> 137 138 #include <dev/mii/mii.h> 139 #include <dev/mii/miivar.h> 140 #include <dev/mii/brgphyreg.h> 141 142 #include <dev/pci/pcireg.h> 143 #include <dev/pci/pcivar.h> 144 145 #include <dev/msk/if_mskreg.h> 146 147 MODULE_DEPEND(msk, pci, 1, 1, 1); 148 MODULE_DEPEND(msk, ether, 1, 1, 1); 149 MODULE_DEPEND(msk, miibus, 1, 1, 1); 150 151 /* "device miibus" required. See GENERIC if you get errors here. */ 152 #include "miibus_if.h" 153 154 /* Tunables. */ 155 static int msi_disable = 0; 156 TUNABLE_INT("hw.msk.msi_disable", &msi_disable); 157 static int legacy_intr = 0; 158 TUNABLE_INT("hw.msk.legacy_intr", &legacy_intr); 159 static int jumbo_disable = 0; 160 TUNABLE_INT("hw.msk.jumbo_disable", &jumbo_disable); 161 162 #define MSK_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 163 164 /* 165 * Devices supported by this driver. 166 */ 167 static struct msk_product { 168 uint16_t msk_vendorid; 169 uint16_t msk_deviceid; 170 const char *msk_name; 171 } msk_products[] = { 172 { VENDORID_SK, DEVICEID_SK_YUKON2, 173 "SK-9Sxx Gigabit Ethernet" }, 174 { VENDORID_SK, DEVICEID_SK_YUKON2_EXPR, 175 "SK-9Exx Gigabit Ethernet"}, 176 { VENDORID_MARVELL, DEVICEID_MRVL_8021CU, 177 "Marvell Yukon 88E8021CU Gigabit Ethernet" }, 178 { VENDORID_MARVELL, DEVICEID_MRVL_8021X, 179 "Marvell Yukon 88E8021 SX/LX Gigabit Ethernet" }, 180 { VENDORID_MARVELL, DEVICEID_MRVL_8022CU, 181 "Marvell Yukon 88E8022CU Gigabit Ethernet" }, 182 { VENDORID_MARVELL, DEVICEID_MRVL_8022X, 183 "Marvell Yukon 88E8022 SX/LX Gigabit Ethernet" }, 184 { VENDORID_MARVELL, DEVICEID_MRVL_8061CU, 185 "Marvell Yukon 88E8061CU Gigabit Ethernet" }, 186 { VENDORID_MARVELL, DEVICEID_MRVL_8061X, 187 "Marvell Yukon 88E8061 SX/LX Gigabit Ethernet" }, 188 { VENDORID_MARVELL, DEVICEID_MRVL_8062CU, 189 "Marvell Yukon 88E8062CU Gigabit Ethernet" }, 190 { VENDORID_MARVELL, DEVICEID_MRVL_8062X, 191 "Marvell Yukon 88E8062 SX/LX Gigabit Ethernet" }, 192 { VENDORID_MARVELL, DEVICEID_MRVL_8035, 193 "Marvell Yukon 88E8035 Fast Ethernet" }, 194 { VENDORID_MARVELL, DEVICEID_MRVL_8036, 195 "Marvell Yukon 88E8036 Fast Ethernet" }, 196 { VENDORID_MARVELL, DEVICEID_MRVL_8038, 197 "Marvell Yukon 88E8038 Fast Ethernet" }, 198 { VENDORID_MARVELL, DEVICEID_MRVL_8039, 199 "Marvell Yukon 88E8039 Fast Ethernet" }, 200 { VENDORID_MARVELL, DEVICEID_MRVL_8040, 201 "Marvell Yukon 88E8040 Fast Ethernet" }, 202 { VENDORID_MARVELL, DEVICEID_MRVL_8040T, 203 "Marvell Yukon 88E8040T Fast Ethernet" }, 204 { VENDORID_MARVELL, DEVICEID_MRVL_8048, 205 "Marvell Yukon 88E8048 Fast Ethernet" }, 206 { VENDORID_MARVELL, DEVICEID_MRVL_8070, 207 "Marvell Yukon 88E8070 Fast Ethernet" }, 208 { VENDORID_MARVELL, DEVICEID_MRVL_4361, 209 "Marvell Yukon 88E8050 Gigabit Ethernet" }, 210 { VENDORID_MARVELL, DEVICEID_MRVL_4360, 211 "Marvell Yukon 88E8052 Gigabit Ethernet" }, 212 { VENDORID_MARVELL, DEVICEID_MRVL_4362, 213 "Marvell Yukon 88E8053 Gigabit Ethernet" }, 214 { VENDORID_MARVELL, DEVICEID_MRVL_4363, 215 "Marvell Yukon 88E8055 Gigabit Ethernet" }, 216 { VENDORID_MARVELL, DEVICEID_MRVL_4364, 217 "Marvell Yukon 88E8056 Gigabit Ethernet" }, 218 { VENDORID_MARVELL, DEVICEID_MRVL_436A, 219 "Marvell Yukon 88E8058 Gigabit Ethernet" }, 220 { VENDORID_DLINK, DEVICEID_DLINK_DGE550SX, 221 "D-Link 550SX Gigabit Ethernet" }, 222 { VENDORID_DLINK, DEVICEID_DLINK_DGE560T, 223 "D-Link 560T Gigabit Ethernet" } 224 }; 225 226 static const char *model_name[] = { 227 "Yukon XL", 228 "Yukon EC Ultra", 229 "Yukon Unknown", 230 "Yukon EC", 231 "Yukon FE", 232 "Yukon FE+" 233 }; 234 235 static int mskc_probe(device_t); 236 static int mskc_attach(device_t); 237 static int mskc_detach(device_t); 238 static int mskc_shutdown(device_t); 239 static int mskc_setup_rambuffer(struct msk_softc *); 240 static int mskc_suspend(device_t); 241 static int mskc_resume(device_t); 242 static void mskc_reset(struct msk_softc *); 243 244 static int msk_probe(device_t); 245 static int msk_attach(device_t); 246 static int msk_detach(device_t); 247 248 static void msk_tick(void *); 249 static void msk_legacy_intr(void *); 250 static int msk_intr(void *); 251 static void msk_int_task(void *, int); 252 static void msk_intr_phy(struct msk_if_softc *); 253 static void msk_intr_gmac(struct msk_if_softc *); 254 static __inline void msk_rxput(struct msk_if_softc *); 255 static int msk_handle_events(struct msk_softc *); 256 static void msk_handle_hwerr(struct msk_if_softc *, uint32_t); 257 static void msk_intr_hwerr(struct msk_softc *); 258 #ifndef __NO_STRICT_ALIGNMENT 259 static __inline void msk_fixup_rx(struct mbuf *); 260 #endif 261 static void msk_rxeof(struct msk_if_softc *, uint32_t, int); 262 static void msk_jumbo_rxeof(struct msk_if_softc *, uint32_t, int); 263 static void msk_txeof(struct msk_if_softc *, int); 264 static int msk_encap(struct msk_if_softc *, struct mbuf **); 265 static void msk_tx_task(void *, int); 266 static void msk_start(struct ifnet *); 267 static int msk_ioctl(struct ifnet *, u_long, caddr_t); 268 static void msk_set_prefetch(struct msk_softc *, int, bus_addr_t, uint32_t); 269 static void msk_set_rambuffer(struct msk_if_softc *); 270 static void msk_init(void *); 271 static void msk_init_locked(struct msk_if_softc *); 272 static void msk_stop(struct msk_if_softc *); 273 static void msk_watchdog(struct msk_if_softc *); 274 static int msk_mediachange(struct ifnet *); 275 static void msk_mediastatus(struct ifnet *, struct ifmediareq *); 276 static void msk_phy_power(struct msk_softc *, int); 277 static void msk_dmamap_cb(void *, bus_dma_segment_t *, int, int); 278 static int msk_status_dma_alloc(struct msk_softc *); 279 static void msk_status_dma_free(struct msk_softc *); 280 static int msk_txrx_dma_alloc(struct msk_if_softc *); 281 static int msk_rx_dma_jalloc(struct msk_if_softc *); 282 static void msk_txrx_dma_free(struct msk_if_softc *); 283 static void msk_rx_dma_jfree(struct msk_if_softc *); 284 static int msk_init_rx_ring(struct msk_if_softc *); 285 static int msk_init_jumbo_rx_ring(struct msk_if_softc *); 286 static void msk_init_tx_ring(struct msk_if_softc *); 287 static __inline void msk_discard_rxbuf(struct msk_if_softc *, int); 288 static __inline void msk_discard_jumbo_rxbuf(struct msk_if_softc *, int); 289 static int msk_newbuf(struct msk_if_softc *, int); 290 static int msk_jumbo_newbuf(struct msk_if_softc *, int); 291 292 static int msk_phy_readreg(struct msk_if_softc *, int, int); 293 static int msk_phy_writereg(struct msk_if_softc *, int, int, int); 294 static int msk_miibus_readreg(device_t, int, int); 295 static int msk_miibus_writereg(device_t, int, int, int); 296 static void msk_miibus_statchg(device_t); 297 298 static void msk_rxfilter(struct msk_if_softc *); 299 static void msk_setvlan(struct msk_if_softc *, struct ifnet *); 300 301 static void msk_stats_clear(struct msk_if_softc *); 302 static void msk_stats_update(struct msk_if_softc *); 303 static int msk_sysctl_stat32(SYSCTL_HANDLER_ARGS); 304 static int msk_sysctl_stat64(SYSCTL_HANDLER_ARGS); 305 static void msk_sysctl_node(struct msk_if_softc *); 306 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int); 307 static int sysctl_hw_msk_proc_limit(SYSCTL_HANDLER_ARGS); 308 309 static device_method_t mskc_methods[] = { 310 /* Device interface */ 311 DEVMETHOD(device_probe, mskc_probe), 312 DEVMETHOD(device_attach, mskc_attach), 313 DEVMETHOD(device_detach, mskc_detach), 314 DEVMETHOD(device_suspend, mskc_suspend), 315 DEVMETHOD(device_resume, mskc_resume), 316 DEVMETHOD(device_shutdown, mskc_shutdown), 317 318 /* bus interface */ 319 DEVMETHOD(bus_print_child, bus_generic_print_child), 320 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 321 322 { NULL, NULL } 323 }; 324 325 static driver_t mskc_driver = { 326 "mskc", 327 mskc_methods, 328 sizeof(struct msk_softc) 329 }; 330 331 static devclass_t mskc_devclass; 332 333 static device_method_t msk_methods[] = { 334 /* Device interface */ 335 DEVMETHOD(device_probe, msk_probe), 336 DEVMETHOD(device_attach, msk_attach), 337 DEVMETHOD(device_detach, msk_detach), 338 DEVMETHOD(device_shutdown, bus_generic_shutdown), 339 340 /* bus interface */ 341 DEVMETHOD(bus_print_child, bus_generic_print_child), 342 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 343 344 /* MII interface */ 345 DEVMETHOD(miibus_readreg, msk_miibus_readreg), 346 DEVMETHOD(miibus_writereg, msk_miibus_writereg), 347 DEVMETHOD(miibus_statchg, msk_miibus_statchg), 348 349 { NULL, NULL } 350 }; 351 352 static driver_t msk_driver = { 353 "msk", 354 msk_methods, 355 sizeof(struct msk_if_softc) 356 }; 357 358 static devclass_t msk_devclass; 359 360 DRIVER_MODULE(mskc, pci, mskc_driver, mskc_devclass, 0, 0); 361 DRIVER_MODULE(msk, mskc, msk_driver, msk_devclass, 0, 0); 362 DRIVER_MODULE(miibus, msk, miibus_driver, miibus_devclass, 0, 0); 363 364 static struct resource_spec msk_res_spec_io[] = { 365 { SYS_RES_IOPORT, PCIR_BAR(1), RF_ACTIVE }, 366 { -1, 0, 0 } 367 }; 368 369 static struct resource_spec msk_res_spec_mem[] = { 370 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 371 { -1, 0, 0 } 372 }; 373 374 static struct resource_spec msk_irq_spec_legacy[] = { 375 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 376 { -1, 0, 0 } 377 }; 378 379 static struct resource_spec msk_irq_spec_msi[] = { 380 { SYS_RES_IRQ, 1, RF_ACTIVE }, 381 { -1, 0, 0 } 382 }; 383 384 static struct resource_spec msk_irq_spec_msi2[] = { 385 { SYS_RES_IRQ, 1, RF_ACTIVE }, 386 { SYS_RES_IRQ, 2, RF_ACTIVE }, 387 { -1, 0, 0 } 388 }; 389 390 static int 391 msk_miibus_readreg(device_t dev, int phy, int reg) 392 { 393 struct msk_if_softc *sc_if; 394 395 if (phy != PHY_ADDR_MARV) 396 return (0); 397 398 sc_if = device_get_softc(dev); 399 400 return (msk_phy_readreg(sc_if, phy, reg)); 401 } 402 403 static int 404 msk_phy_readreg(struct msk_if_softc *sc_if, int phy, int reg) 405 { 406 struct msk_softc *sc; 407 int i, val; 408 409 sc = sc_if->msk_softc; 410 411 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SMI_CTRL, 412 GM_SMI_CT_PHY_AD(phy) | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD); 413 414 for (i = 0; i < MSK_TIMEOUT; i++) { 415 DELAY(1); 416 val = GMAC_READ_2(sc, sc_if->msk_port, GM_SMI_CTRL); 417 if ((val & GM_SMI_CT_RD_VAL) != 0) { 418 val = GMAC_READ_2(sc, sc_if->msk_port, GM_SMI_DATA); 419 break; 420 } 421 } 422 423 if (i == MSK_TIMEOUT) { 424 if_printf(sc_if->msk_ifp, "phy failed to come ready\n"); 425 val = 0; 426 } 427 428 return (val); 429 } 430 431 static int 432 msk_miibus_writereg(device_t dev, int phy, int reg, int val) 433 { 434 struct msk_if_softc *sc_if; 435 436 if (phy != PHY_ADDR_MARV) 437 return (0); 438 439 sc_if = device_get_softc(dev); 440 441 return (msk_phy_writereg(sc_if, phy, reg, val)); 442 } 443 444 static int 445 msk_phy_writereg(struct msk_if_softc *sc_if, int phy, int reg, int val) 446 { 447 struct msk_softc *sc; 448 int i; 449 450 sc = sc_if->msk_softc; 451 452 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SMI_DATA, val); 453 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SMI_CTRL, 454 GM_SMI_CT_PHY_AD(phy) | GM_SMI_CT_REG_AD(reg)); 455 for (i = 0; i < MSK_TIMEOUT; i++) { 456 DELAY(1); 457 if ((GMAC_READ_2(sc, sc_if->msk_port, GM_SMI_CTRL) & 458 GM_SMI_CT_BUSY) == 0) 459 break; 460 } 461 if (i == MSK_TIMEOUT) 462 if_printf(sc_if->msk_ifp, "phy write timeout\n"); 463 464 return (0); 465 } 466 467 static void 468 msk_miibus_statchg(device_t dev) 469 { 470 struct msk_softc *sc; 471 struct msk_if_softc *sc_if; 472 struct mii_data *mii; 473 struct ifnet *ifp; 474 uint32_t gmac; 475 476 sc_if = device_get_softc(dev); 477 sc = sc_if->msk_softc; 478 479 MSK_IF_LOCK_ASSERT(sc_if); 480 481 mii = device_get_softc(sc_if->msk_miibus); 482 ifp = sc_if->msk_ifp; 483 if (mii == NULL || ifp == NULL || 484 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 485 return; 486 487 sc_if->msk_flags &= ~MSK_FLAG_LINK; 488 if ((mii->mii_media_status & (IFM_AVALID | IFM_ACTIVE)) == 489 (IFM_AVALID | IFM_ACTIVE)) { 490 switch (IFM_SUBTYPE(mii->mii_media_active)) { 491 case IFM_10_T: 492 case IFM_100_TX: 493 sc_if->msk_flags |= MSK_FLAG_LINK; 494 break; 495 case IFM_1000_T: 496 case IFM_1000_SX: 497 case IFM_1000_LX: 498 case IFM_1000_CX: 499 if ((sc_if->msk_flags & MSK_FLAG_FASTETHER) == 0) 500 sc_if->msk_flags |= MSK_FLAG_LINK; 501 break; 502 default: 503 break; 504 } 505 } 506 507 if ((sc_if->msk_flags & MSK_FLAG_LINK) != 0) { 508 /* Enable Tx FIFO Underrun. */ 509 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_MSK), 510 GM_IS_TX_FF_UR | GM_IS_RX_FF_OR); 511 /* 512 * Because mii(4) notify msk(4) that it detected link status 513 * change, there is no need to enable automatic 514 * speed/flow-control/duplex updates. 515 */ 516 gmac = GM_GPCR_AU_ALL_DIS; 517 switch (IFM_SUBTYPE(mii->mii_media_active)) { 518 case IFM_1000_SX: 519 case IFM_1000_T: 520 gmac |= GM_GPCR_SPEED_1000; 521 break; 522 case IFM_100_TX: 523 gmac |= GM_GPCR_SPEED_100; 524 break; 525 case IFM_10_T: 526 break; 527 } 528 529 if (((mii->mii_media_active & IFM_GMASK) & IFM_FDX) != 0) 530 gmac |= GM_GPCR_DUP_FULL; 531 /* Disable Rx flow control. */ 532 if (((mii->mii_media_active & IFM_GMASK) & IFM_FLAG0) == 0) 533 gmac |= GM_GPCR_FC_RX_DIS; 534 /* Disable Tx flow control. */ 535 if (((mii->mii_media_active & IFM_GMASK) & IFM_FLAG1) == 0) 536 gmac |= GM_GPCR_FC_TX_DIS; 537 gmac |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA; 538 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, gmac); 539 /* Read again to ensure writing. */ 540 GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL); 541 542 gmac = GMC_PAUSE_ON; 543 if (((mii->mii_media_active & IFM_GMASK) & 544 (IFM_FLAG0 | IFM_FLAG1)) == 0) 545 gmac = GMC_PAUSE_OFF; 546 /* Diable pause for 10/100 Mbps in half-duplex mode. */ 547 if ((((mii->mii_media_active & IFM_GMASK) & IFM_FDX) == 0) && 548 (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX || 549 IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T)) 550 gmac = GMC_PAUSE_OFF; 551 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), gmac); 552 553 /* Enable PHY interrupt for FIFO underrun/overflow. */ 554 msk_phy_writereg(sc_if, PHY_ADDR_MARV, 555 PHY_MARV_INT_MASK, PHY_M_IS_FIFO_ERROR); 556 } else { 557 /* 558 * Link state changed to down. 559 * Disable PHY interrupts. 560 */ 561 msk_phy_writereg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_MASK, 0); 562 /* Disable Rx/Tx MAC. */ 563 gmac = GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL); 564 if ((GM_GPCR_RX_ENA | GM_GPCR_TX_ENA) != 0) { 565 gmac &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA); 566 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, gmac); 567 /* Read again to ensure writing. */ 568 GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL); 569 } 570 } 571 } 572 573 static void 574 msk_rxfilter(struct msk_if_softc *sc_if) 575 { 576 struct msk_softc *sc; 577 struct ifnet *ifp; 578 struct ifmultiaddr *ifma; 579 uint32_t mchash[2]; 580 uint32_t crc; 581 uint16_t mode; 582 583 sc = sc_if->msk_softc; 584 585 MSK_IF_LOCK_ASSERT(sc_if); 586 587 ifp = sc_if->msk_ifp; 588 589 bzero(mchash, sizeof(mchash)); 590 mode = GMAC_READ_2(sc, sc_if->msk_port, GM_RX_CTRL); 591 if ((ifp->if_flags & IFF_PROMISC) != 0) 592 mode &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA); 593 else if ((ifp->if_flags & IFF_ALLMULTI) != 0) { 594 mode |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA; 595 mchash[0] = 0xffff; 596 mchash[1] = 0xffff; 597 } else { 598 mode |= GM_RXCR_UCF_ENA; 599 IF_ADDR_LOCK(ifp); 600 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 601 if (ifma->ifma_addr->sa_family != AF_LINK) 602 continue; 603 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *) 604 ifma->ifma_addr), ETHER_ADDR_LEN); 605 /* Just want the 6 least significant bits. */ 606 crc &= 0x3f; 607 /* Set the corresponding bit in the hash table. */ 608 mchash[crc >> 5] |= 1 << (crc & 0x1f); 609 } 610 IF_ADDR_UNLOCK(ifp); 611 if (mchash[0] != 0 || mchash[1] != 0) 612 mode |= GM_RXCR_MCF_ENA; 613 } 614 615 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H1, 616 mchash[0] & 0xffff); 617 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H2, 618 (mchash[0] >> 16) & 0xffff); 619 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H3, 620 mchash[1] & 0xffff); 621 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H4, 622 (mchash[1] >> 16) & 0xffff); 623 GMAC_WRITE_2(sc, sc_if->msk_port, GM_RX_CTRL, mode); 624 } 625 626 static void 627 msk_setvlan(struct msk_if_softc *sc_if, struct ifnet *ifp) 628 { 629 struct msk_softc *sc; 630 631 sc = sc_if->msk_softc; 632 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) { 633 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), 634 RX_VLAN_STRIP_ON); 635 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 636 TX_VLAN_TAG_ON); 637 } else { 638 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), 639 RX_VLAN_STRIP_OFF); 640 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 641 TX_VLAN_TAG_OFF); 642 } 643 } 644 645 static int 646 msk_init_rx_ring(struct msk_if_softc *sc_if) 647 { 648 struct msk_ring_data *rd; 649 struct msk_rxdesc *rxd; 650 int i, prod; 651 652 MSK_IF_LOCK_ASSERT(sc_if); 653 654 sc_if->msk_cdata.msk_rx_cons = 0; 655 sc_if->msk_cdata.msk_rx_prod = 0; 656 sc_if->msk_cdata.msk_rx_putwm = MSK_PUT_WM; 657 658 rd = &sc_if->msk_rdata; 659 bzero(rd->msk_rx_ring, sizeof(struct msk_rx_desc) * MSK_RX_RING_CNT); 660 prod = sc_if->msk_cdata.msk_rx_prod; 661 for (i = 0; i < MSK_RX_RING_CNT; i++) { 662 rxd = &sc_if->msk_cdata.msk_rxdesc[prod]; 663 rxd->rx_m = NULL; 664 rxd->rx_le = &rd->msk_rx_ring[prod]; 665 if (msk_newbuf(sc_if, prod) != 0) 666 return (ENOBUFS); 667 MSK_INC(prod, MSK_RX_RING_CNT); 668 } 669 670 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_ring_tag, 671 sc_if->msk_cdata.msk_rx_ring_map, 672 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 673 674 /* Update prefetch unit. */ 675 sc_if->msk_cdata.msk_rx_prod = MSK_RX_RING_CNT - 1; 676 CSR_WRITE_2(sc_if->msk_softc, 677 Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_PUT_IDX_REG), 678 sc_if->msk_cdata.msk_rx_prod); 679 680 return (0); 681 } 682 683 static int 684 msk_init_jumbo_rx_ring(struct msk_if_softc *sc_if) 685 { 686 struct msk_ring_data *rd; 687 struct msk_rxdesc *rxd; 688 int i, prod; 689 690 MSK_IF_LOCK_ASSERT(sc_if); 691 692 sc_if->msk_cdata.msk_rx_cons = 0; 693 sc_if->msk_cdata.msk_rx_prod = 0; 694 sc_if->msk_cdata.msk_rx_putwm = MSK_PUT_WM; 695 696 rd = &sc_if->msk_rdata; 697 bzero(rd->msk_jumbo_rx_ring, 698 sizeof(struct msk_rx_desc) * MSK_JUMBO_RX_RING_CNT); 699 prod = sc_if->msk_cdata.msk_rx_prod; 700 for (i = 0; i < MSK_JUMBO_RX_RING_CNT; i++) { 701 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[prod]; 702 rxd->rx_m = NULL; 703 rxd->rx_le = &rd->msk_jumbo_rx_ring[prod]; 704 if (msk_jumbo_newbuf(sc_if, prod) != 0) 705 return (ENOBUFS); 706 MSK_INC(prod, MSK_JUMBO_RX_RING_CNT); 707 } 708 709 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 710 sc_if->msk_cdata.msk_jumbo_rx_ring_map, 711 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 712 713 sc_if->msk_cdata.msk_rx_prod = MSK_JUMBO_RX_RING_CNT - 1; 714 CSR_WRITE_2(sc_if->msk_softc, 715 Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_PUT_IDX_REG), 716 sc_if->msk_cdata.msk_rx_prod); 717 718 return (0); 719 } 720 721 static void 722 msk_init_tx_ring(struct msk_if_softc *sc_if) 723 { 724 struct msk_ring_data *rd; 725 struct msk_txdesc *txd; 726 int i; 727 728 sc_if->msk_cdata.msk_tso_mtu = 0; 729 sc_if->msk_cdata.msk_tx_prod = 0; 730 sc_if->msk_cdata.msk_tx_cons = 0; 731 sc_if->msk_cdata.msk_tx_cnt = 0; 732 733 rd = &sc_if->msk_rdata; 734 bzero(rd->msk_tx_ring, sizeof(struct msk_tx_desc) * MSK_TX_RING_CNT); 735 for (i = 0; i < MSK_TX_RING_CNT; i++) { 736 txd = &sc_if->msk_cdata.msk_txdesc[i]; 737 txd->tx_m = NULL; 738 txd->tx_le = &rd->msk_tx_ring[i]; 739 } 740 741 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_ring_tag, 742 sc_if->msk_cdata.msk_tx_ring_map, 743 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 744 } 745 746 static __inline void 747 msk_discard_rxbuf(struct msk_if_softc *sc_if, int idx) 748 { 749 struct msk_rx_desc *rx_le; 750 struct msk_rxdesc *rxd; 751 struct mbuf *m; 752 753 rxd = &sc_if->msk_cdata.msk_rxdesc[idx]; 754 m = rxd->rx_m; 755 rx_le = rxd->rx_le; 756 rx_le->msk_control = htole32(m->m_len | OP_PACKET | HW_OWNER); 757 } 758 759 static __inline void 760 msk_discard_jumbo_rxbuf(struct msk_if_softc *sc_if, int idx) 761 { 762 struct msk_rx_desc *rx_le; 763 struct msk_rxdesc *rxd; 764 struct mbuf *m; 765 766 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[idx]; 767 m = rxd->rx_m; 768 rx_le = rxd->rx_le; 769 rx_le->msk_control = htole32(m->m_len | OP_PACKET | HW_OWNER); 770 } 771 772 static int 773 msk_newbuf(struct msk_if_softc *sc_if, int idx) 774 { 775 struct msk_rx_desc *rx_le; 776 struct msk_rxdesc *rxd; 777 struct mbuf *m; 778 bus_dma_segment_t segs[1]; 779 bus_dmamap_t map; 780 int nsegs; 781 782 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 783 if (m == NULL) 784 return (ENOBUFS); 785 786 m->m_len = m->m_pkthdr.len = MCLBYTES; 787 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) == 0) 788 m_adj(m, ETHER_ALIGN); 789 #ifndef __NO_STRICT_ALIGNMENT 790 else 791 m_adj(m, MSK_RX_BUF_ALIGN); 792 #endif 793 794 if (bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_rx_tag, 795 sc_if->msk_cdata.msk_rx_sparemap, m, segs, &nsegs, 796 BUS_DMA_NOWAIT) != 0) { 797 m_freem(m); 798 return (ENOBUFS); 799 } 800 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 801 802 rxd = &sc_if->msk_cdata.msk_rxdesc[idx]; 803 if (rxd->rx_m != NULL) { 804 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_tag, rxd->rx_dmamap, 805 BUS_DMASYNC_POSTREAD); 806 bus_dmamap_unload(sc_if->msk_cdata.msk_rx_tag, rxd->rx_dmamap); 807 } 808 map = rxd->rx_dmamap; 809 rxd->rx_dmamap = sc_if->msk_cdata.msk_rx_sparemap; 810 sc_if->msk_cdata.msk_rx_sparemap = map; 811 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_tag, rxd->rx_dmamap, 812 BUS_DMASYNC_PREREAD); 813 rxd->rx_m = m; 814 rx_le = rxd->rx_le; 815 rx_le->msk_addr = htole32(MSK_ADDR_LO(segs[0].ds_addr)); 816 rx_le->msk_control = 817 htole32(segs[0].ds_len | OP_PACKET | HW_OWNER); 818 819 return (0); 820 } 821 822 static int 823 msk_jumbo_newbuf(struct msk_if_softc *sc_if, int idx) 824 { 825 struct msk_rx_desc *rx_le; 826 struct msk_rxdesc *rxd; 827 struct mbuf *m; 828 bus_dma_segment_t segs[1]; 829 bus_dmamap_t map; 830 int nsegs; 831 832 m = m_getjcl(M_DONTWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES); 833 if (m == NULL) 834 return (ENOBUFS); 835 if ((m->m_flags & M_EXT) == 0) { 836 m_freem(m); 837 return (ENOBUFS); 838 } 839 m->m_len = m->m_pkthdr.len = MJUM9BYTES; 840 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) == 0) 841 m_adj(m, ETHER_ALIGN); 842 #ifndef __NO_STRICT_ALIGNMENT 843 else 844 m_adj(m, MSK_RX_BUF_ALIGN); 845 #endif 846 847 if (bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_jumbo_rx_tag, 848 sc_if->msk_cdata.msk_jumbo_rx_sparemap, m, segs, &nsegs, 849 BUS_DMA_NOWAIT) != 0) { 850 m_freem(m); 851 return (ENOBUFS); 852 } 853 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 854 855 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[idx]; 856 if (rxd->rx_m != NULL) { 857 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_tag, 858 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 859 bus_dmamap_unload(sc_if->msk_cdata.msk_jumbo_rx_tag, 860 rxd->rx_dmamap); 861 } 862 map = rxd->rx_dmamap; 863 rxd->rx_dmamap = sc_if->msk_cdata.msk_jumbo_rx_sparemap; 864 sc_if->msk_cdata.msk_jumbo_rx_sparemap = map; 865 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_tag, rxd->rx_dmamap, 866 BUS_DMASYNC_PREREAD); 867 rxd->rx_m = m; 868 rx_le = rxd->rx_le; 869 rx_le->msk_addr = htole32(MSK_ADDR_LO(segs[0].ds_addr)); 870 rx_le->msk_control = 871 htole32(segs[0].ds_len | OP_PACKET | HW_OWNER); 872 873 return (0); 874 } 875 876 /* 877 * Set media options. 878 */ 879 static int 880 msk_mediachange(struct ifnet *ifp) 881 { 882 struct msk_if_softc *sc_if; 883 struct mii_data *mii; 884 int error; 885 886 sc_if = ifp->if_softc; 887 888 MSK_IF_LOCK(sc_if); 889 mii = device_get_softc(sc_if->msk_miibus); 890 error = mii_mediachg(mii); 891 MSK_IF_UNLOCK(sc_if); 892 893 return (error); 894 } 895 896 /* 897 * Report current media status. 898 */ 899 static void 900 msk_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 901 { 902 struct msk_if_softc *sc_if; 903 struct mii_data *mii; 904 905 sc_if = ifp->if_softc; 906 MSK_IF_LOCK(sc_if); 907 if ((ifp->if_flags & IFF_UP) == 0) { 908 MSK_IF_UNLOCK(sc_if); 909 return; 910 } 911 mii = device_get_softc(sc_if->msk_miibus); 912 913 mii_pollstat(mii); 914 MSK_IF_UNLOCK(sc_if); 915 ifmr->ifm_active = mii->mii_media_active; 916 ifmr->ifm_status = mii->mii_media_status; 917 } 918 919 static int 920 msk_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 921 { 922 struct msk_if_softc *sc_if; 923 struct ifreq *ifr; 924 struct mii_data *mii; 925 int error, mask; 926 927 sc_if = ifp->if_softc; 928 ifr = (struct ifreq *)data; 929 error = 0; 930 931 switch(command) { 932 case SIOCSIFMTU: 933 MSK_IF_LOCK(sc_if); 934 if (ifr->ifr_mtu > MSK_JUMBO_MTU || ifr->ifr_mtu < ETHERMIN) 935 error = EINVAL; 936 else if (ifp->if_mtu != ifr->ifr_mtu) { 937 if (ifr->ifr_mtu > ETHERMTU) { 938 if ((sc_if->msk_flags & MSK_FLAG_JUMBO) == 0) { 939 error = EINVAL; 940 MSK_IF_UNLOCK(sc_if); 941 break; 942 } 943 if ((sc_if->msk_flags & 944 MSK_FLAG_JUMBO_NOCSUM) != 0) { 945 ifp->if_hwassist &= 946 ~(MSK_CSUM_FEATURES | CSUM_TSO); 947 ifp->if_capenable &= 948 ~(IFCAP_TSO4 | IFCAP_TXCSUM); 949 VLAN_CAPABILITIES(ifp); 950 } 951 } 952 ifp->if_mtu = ifr->ifr_mtu; 953 msk_init_locked(sc_if); 954 } 955 MSK_IF_UNLOCK(sc_if); 956 break; 957 case SIOCSIFFLAGS: 958 MSK_IF_LOCK(sc_if); 959 if ((ifp->if_flags & IFF_UP) != 0) { 960 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 && 961 ((ifp->if_flags ^ sc_if->msk_if_flags) & 962 (IFF_PROMISC | IFF_ALLMULTI)) != 0) 963 msk_rxfilter(sc_if); 964 else if ((sc_if->msk_flags & MSK_FLAG_DETACH) == 0) 965 msk_init_locked(sc_if); 966 } else if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 967 msk_stop(sc_if); 968 sc_if->msk_if_flags = ifp->if_flags; 969 MSK_IF_UNLOCK(sc_if); 970 break; 971 case SIOCADDMULTI: 972 case SIOCDELMULTI: 973 MSK_IF_LOCK(sc_if); 974 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 975 msk_rxfilter(sc_if); 976 MSK_IF_UNLOCK(sc_if); 977 break; 978 case SIOCGIFMEDIA: 979 case SIOCSIFMEDIA: 980 mii = device_get_softc(sc_if->msk_miibus); 981 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 982 break; 983 case SIOCSIFCAP: 984 MSK_IF_LOCK(sc_if); 985 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 986 if ((mask & IFCAP_TXCSUM) != 0 && 987 (IFCAP_TXCSUM & ifp->if_capabilities) != 0) { 988 ifp->if_capenable ^= IFCAP_TXCSUM; 989 if ((IFCAP_TXCSUM & ifp->if_capenable) != 0) 990 ifp->if_hwassist |= MSK_CSUM_FEATURES; 991 else 992 ifp->if_hwassist &= ~MSK_CSUM_FEATURES; 993 } 994 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 995 (IFCAP_VLAN_HWTAGGING & ifp->if_capabilities) != 0) { 996 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 997 msk_setvlan(sc_if, ifp); 998 } 999 1000 if ((mask & IFCAP_TSO4) != 0 && 1001 (IFCAP_TSO4 & ifp->if_capabilities) != 0) { 1002 ifp->if_capenable ^= IFCAP_TSO4; 1003 if ((IFCAP_TSO4 & ifp->if_capenable) != 0) 1004 ifp->if_hwassist |= CSUM_TSO; 1005 else 1006 ifp->if_hwassist &= ~CSUM_TSO; 1007 } 1008 if (ifp->if_mtu > ETHERMTU && 1009 (sc_if->msk_flags & MSK_FLAG_JUMBO_NOCSUM) != 0) { 1010 ifp->if_hwassist &= ~(MSK_CSUM_FEATURES | CSUM_TSO); 1011 ifp->if_capenable &= ~(IFCAP_TSO4 | IFCAP_TXCSUM); 1012 } 1013 1014 VLAN_CAPABILITIES(ifp); 1015 MSK_IF_UNLOCK(sc_if); 1016 break; 1017 default: 1018 error = ether_ioctl(ifp, command, data); 1019 break; 1020 } 1021 1022 return (error); 1023 } 1024 1025 static int 1026 mskc_probe(device_t dev) 1027 { 1028 struct msk_product *mp; 1029 uint16_t vendor, devid; 1030 int i; 1031 1032 vendor = pci_get_vendor(dev); 1033 devid = pci_get_device(dev); 1034 mp = msk_products; 1035 for (i = 0; i < sizeof(msk_products)/sizeof(msk_products[0]); 1036 i++, mp++) { 1037 if (vendor == mp->msk_vendorid && devid == mp->msk_deviceid) { 1038 device_set_desc(dev, mp->msk_name); 1039 return (BUS_PROBE_DEFAULT); 1040 } 1041 } 1042 1043 return (ENXIO); 1044 } 1045 1046 static int 1047 mskc_setup_rambuffer(struct msk_softc *sc) 1048 { 1049 int next; 1050 int i; 1051 1052 /* Get adapter SRAM size. */ 1053 sc->msk_ramsize = CSR_READ_1(sc, B2_E_0) * 4; 1054 if (bootverbose) 1055 device_printf(sc->msk_dev, 1056 "RAM buffer size : %dKB\n", sc->msk_ramsize); 1057 if (sc->msk_ramsize == 0) 1058 return (0); 1059 1060 sc->msk_pflags |= MSK_FLAG_RAMBUF; 1061 /* 1062 * Give receiver 2/3 of memory and round down to the multiple 1063 * of 1024. Tx/Rx RAM buffer size of Yukon II shoud be multiple 1064 * of 1024. 1065 */ 1066 sc->msk_rxqsize = rounddown((sc->msk_ramsize * 1024 * 2) / 3, 1024); 1067 sc->msk_txqsize = (sc->msk_ramsize * 1024) - sc->msk_rxqsize; 1068 for (i = 0, next = 0; i < sc->msk_num_port; i++) { 1069 sc->msk_rxqstart[i] = next; 1070 sc->msk_rxqend[i] = next + sc->msk_rxqsize - 1; 1071 next = sc->msk_rxqend[i] + 1; 1072 sc->msk_txqstart[i] = next; 1073 sc->msk_txqend[i] = next + sc->msk_txqsize - 1; 1074 next = sc->msk_txqend[i] + 1; 1075 if (bootverbose) { 1076 device_printf(sc->msk_dev, 1077 "Port %d : Rx Queue %dKB(0x%08x:0x%08x)\n", i, 1078 sc->msk_rxqsize / 1024, sc->msk_rxqstart[i], 1079 sc->msk_rxqend[i]); 1080 device_printf(sc->msk_dev, 1081 "Port %d : Tx Queue %dKB(0x%08x:0x%08x)\n", i, 1082 sc->msk_txqsize / 1024, sc->msk_txqstart[i], 1083 sc->msk_txqend[i]); 1084 } 1085 } 1086 1087 return (0); 1088 } 1089 1090 static void 1091 msk_phy_power(struct msk_softc *sc, int mode) 1092 { 1093 uint32_t our, val; 1094 int i; 1095 1096 switch (mode) { 1097 case MSK_PHY_POWERUP: 1098 /* Switch power to VCC (WA for VAUX problem). */ 1099 CSR_WRITE_1(sc, B0_POWER_CTRL, 1100 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON); 1101 /* Disable Core Clock Division, set Clock Select to 0. */ 1102 CSR_WRITE_4(sc, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS); 1103 1104 val = 0; 1105 if (sc->msk_hw_id == CHIP_ID_YUKON_XL && 1106 sc->msk_hw_rev > CHIP_REV_YU_XL_A1) { 1107 /* Enable bits are inverted. */ 1108 val = Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS | 1109 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS | 1110 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS; 1111 } 1112 /* 1113 * Enable PCI & Core Clock, enable clock gating for both Links. 1114 */ 1115 CSR_WRITE_1(sc, B2_Y2_CLK_GATE, val); 1116 1117 val = pci_read_config(sc->msk_dev, PCI_OUR_REG_1, 4); 1118 val &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD); 1119 switch (sc->msk_hw_id) { 1120 case CHIP_ID_YUKON_XL: 1121 if (sc->msk_hw_rev > CHIP_REV_YU_XL_A1) { 1122 /* Deassert Low Power for 1st PHY. */ 1123 val |= PCI_Y2_PHY1_COMA; 1124 if (sc->msk_num_port > 1) 1125 val |= PCI_Y2_PHY2_COMA; 1126 } 1127 break; 1128 case CHIP_ID_YUKON_EC_U: 1129 case CHIP_ID_YUKON_FE_P: 1130 CSR_WRITE_2(sc, B0_CTST, Y2_HW_WOL_OFF); 1131 1132 /* Enable all clocks. */ 1133 pci_write_config(sc->msk_dev, PCI_OUR_REG_3, 0, 4); 1134 our = pci_read_config(sc->msk_dev, PCI_OUR_REG_4, 4); 1135 our &= (PCI_FORCE_ASPM_REQUEST|PCI_ASPM_GPHY_LINK_DOWN| 1136 PCI_ASPM_INT_FIFO_EMPTY|PCI_ASPM_CLKRUN_REQUEST); 1137 /* Set all bits to 0 except bits 15..12. */ 1138 pci_write_config(sc->msk_dev, PCI_OUR_REG_4, our, 4); 1139 /* Set to default value. */ 1140 pci_write_config(sc->msk_dev, PCI_OUR_REG_5, 0, 4); 1141 break; 1142 default: 1143 break; 1144 } 1145 /* Release PHY from PowerDown/COMA mode. */ 1146 pci_write_config(sc->msk_dev, PCI_OUR_REG_1, val, 4); 1147 for (i = 0; i < sc->msk_num_port; i++) { 1148 CSR_WRITE_2(sc, MR_ADDR(i, GMAC_LINK_CTRL), 1149 GMLC_RST_SET); 1150 CSR_WRITE_2(sc, MR_ADDR(i, GMAC_LINK_CTRL), 1151 GMLC_RST_CLR); 1152 } 1153 break; 1154 case MSK_PHY_POWERDOWN: 1155 val = pci_read_config(sc->msk_dev, PCI_OUR_REG_1, 4); 1156 val |= PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD; 1157 if (sc->msk_hw_id == CHIP_ID_YUKON_XL && 1158 sc->msk_hw_rev > CHIP_REV_YU_XL_A1) { 1159 val &= ~PCI_Y2_PHY1_COMA; 1160 if (sc->msk_num_port > 1) 1161 val &= ~PCI_Y2_PHY2_COMA; 1162 } 1163 pci_write_config(sc->msk_dev, PCI_OUR_REG_1, val, 4); 1164 1165 val = Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS | 1166 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS | 1167 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS; 1168 if (sc->msk_hw_id == CHIP_ID_YUKON_XL && 1169 sc->msk_hw_rev > CHIP_REV_YU_XL_A1) { 1170 /* Enable bits are inverted. */ 1171 val = 0; 1172 } 1173 /* 1174 * Disable PCI & Core Clock, disable clock gating for 1175 * both Links. 1176 */ 1177 CSR_WRITE_1(sc, B2_Y2_CLK_GATE, val); 1178 CSR_WRITE_1(sc, B0_POWER_CTRL, 1179 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_ON | PC_VCC_OFF); 1180 break; 1181 default: 1182 break; 1183 } 1184 } 1185 1186 static void 1187 mskc_reset(struct msk_softc *sc) 1188 { 1189 bus_addr_t addr; 1190 uint16_t status; 1191 uint32_t val; 1192 int i; 1193 1194 CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR); 1195 1196 /* Disable ASF. */ 1197 if (sc->msk_hw_id < CHIP_ID_YUKON_XL) { 1198 CSR_WRITE_4(sc, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET); 1199 CSR_WRITE_2(sc, B0_CTST, Y2_ASF_DISABLE); 1200 } 1201 /* 1202 * Since we disabled ASF, S/W reset is required for Power Management. 1203 */ 1204 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); 1205 CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR); 1206 1207 /* Clear all error bits in the PCI status register. */ 1208 status = pci_read_config(sc->msk_dev, PCIR_STATUS, 2); 1209 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON); 1210 1211 pci_write_config(sc->msk_dev, PCIR_STATUS, status | 1212 PCIM_STATUS_PERR | PCIM_STATUS_SERR | PCIM_STATUS_RMABORT | 1213 PCIM_STATUS_RTABORT | PCIM_STATUS_PERRREPORT, 2); 1214 CSR_WRITE_2(sc, B0_CTST, CS_MRST_CLR); 1215 1216 switch (sc->msk_bustype) { 1217 case MSK_PEX_BUS: 1218 /* Clear all PEX errors. */ 1219 CSR_PCI_WRITE_4(sc, PEX_UNC_ERR_STAT, 0xffffffff); 1220 val = CSR_PCI_READ_4(sc, PEX_UNC_ERR_STAT); 1221 if ((val & PEX_RX_OV) != 0) { 1222 sc->msk_intrmask &= ~Y2_IS_HW_ERR; 1223 sc->msk_intrhwemask &= ~Y2_IS_PCI_EXP; 1224 } 1225 break; 1226 case MSK_PCI_BUS: 1227 case MSK_PCIX_BUS: 1228 /* Set Cache Line Size to 2(8bytes) if configured to 0. */ 1229 val = pci_read_config(sc->msk_dev, PCIR_CACHELNSZ, 1); 1230 if (val == 0) 1231 pci_write_config(sc->msk_dev, PCIR_CACHELNSZ, 2, 1); 1232 if (sc->msk_bustype == MSK_PCIX_BUS) { 1233 /* Set Cache Line Size opt. */ 1234 val = pci_read_config(sc->msk_dev, PCI_OUR_REG_1, 4); 1235 val |= PCI_CLS_OPT; 1236 pci_write_config(sc->msk_dev, PCI_OUR_REG_1, val, 4); 1237 } 1238 break; 1239 } 1240 /* Set PHY power state. */ 1241 msk_phy_power(sc, MSK_PHY_POWERUP); 1242 1243 /* Reset GPHY/GMAC Control */ 1244 for (i = 0; i < sc->msk_num_port; i++) { 1245 /* GPHY Control reset. */ 1246 CSR_WRITE_4(sc, MR_ADDR(i, GPHY_CTRL), GPC_RST_SET); 1247 CSR_WRITE_4(sc, MR_ADDR(i, GPHY_CTRL), GPC_RST_CLR); 1248 /* GMAC Control reset. */ 1249 CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), GMC_RST_SET); 1250 CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), GMC_RST_CLR); 1251 CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), GMC_F_LOOPB_OFF); 1252 } 1253 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 1254 1255 /* LED On. */ 1256 CSR_WRITE_2(sc, B0_CTST, Y2_LED_STAT_ON); 1257 1258 /* Clear TWSI IRQ. */ 1259 CSR_WRITE_4(sc, B2_I2C_IRQ, I2C_CLR_IRQ); 1260 1261 /* Turn off hardware timer. */ 1262 CSR_WRITE_1(sc, B2_TI_CTRL, TIM_STOP); 1263 CSR_WRITE_1(sc, B2_TI_CTRL, TIM_CLR_IRQ); 1264 1265 /* Turn off descriptor polling. */ 1266 CSR_WRITE_1(sc, B28_DPT_CTRL, DPT_STOP); 1267 1268 /* Turn off time stamps. */ 1269 CSR_WRITE_1(sc, GMAC_TI_ST_CTRL, GMT_ST_STOP); 1270 CSR_WRITE_1(sc, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ); 1271 1272 /* Configure timeout values. */ 1273 for (i = 0; i < sc->msk_num_port; i++) { 1274 CSR_WRITE_2(sc, SELECT_RAM_BUFFER(i, B3_RI_CTRL), RI_RST_SET); 1275 CSR_WRITE_2(sc, SELECT_RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR); 1276 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_R1), 1277 MSK_RI_TO_53); 1278 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XA1), 1279 MSK_RI_TO_53); 1280 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XS1), 1281 MSK_RI_TO_53); 1282 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_R1), 1283 MSK_RI_TO_53); 1284 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XA1), 1285 MSK_RI_TO_53); 1286 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XS1), 1287 MSK_RI_TO_53); 1288 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_R2), 1289 MSK_RI_TO_53); 1290 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XA2), 1291 MSK_RI_TO_53); 1292 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XS2), 1293 MSK_RI_TO_53); 1294 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_R2), 1295 MSK_RI_TO_53); 1296 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XA2), 1297 MSK_RI_TO_53); 1298 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XS2), 1299 MSK_RI_TO_53); 1300 } 1301 1302 /* Disable all interrupts. */ 1303 CSR_WRITE_4(sc, B0_HWE_IMSK, 0); 1304 CSR_READ_4(sc, B0_HWE_IMSK); 1305 CSR_WRITE_4(sc, B0_IMSK, 0); 1306 CSR_READ_4(sc, B0_IMSK); 1307 1308 /* 1309 * On dual port PCI-X card, there is an problem where status 1310 * can be received out of order due to split transactions. 1311 */ 1312 if (sc->msk_bustype == MSK_PCIX_BUS && sc->msk_num_port > 1) { 1313 int pcix; 1314 uint16_t pcix_cmd; 1315 1316 if (pci_find_extcap(sc->msk_dev, PCIY_PCIX, &pcix) == 0) { 1317 pcix_cmd = pci_read_config(sc->msk_dev, pcix + 2, 2); 1318 /* Clear Max Outstanding Split Transactions. */ 1319 pcix_cmd &= ~0x70; 1320 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON); 1321 pci_write_config(sc->msk_dev, pcix + 2, pcix_cmd, 2); 1322 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 1323 } 1324 } 1325 if (sc->msk_bustype == MSK_PEX_BUS) { 1326 uint16_t v, width; 1327 1328 v = pci_read_config(sc->msk_dev, PEX_DEV_CTRL, 2); 1329 /* Change Max. Read Request Size to 4096 bytes. */ 1330 v &= ~PEX_DC_MAX_RRS_MSK; 1331 v |= PEX_DC_MAX_RD_RQ_SIZE(5); 1332 pci_write_config(sc->msk_dev, PEX_DEV_CTRL, v, 2); 1333 width = pci_read_config(sc->msk_dev, PEX_LNK_STAT, 2); 1334 width = (width & PEX_LS_LINK_WI_MSK) >> 4; 1335 v = pci_read_config(sc->msk_dev, PEX_LNK_CAP, 2); 1336 v = (v & PEX_LS_LINK_WI_MSK) >> 4; 1337 if (v != width) 1338 device_printf(sc->msk_dev, 1339 "negotiated width of link(x%d) != " 1340 "max. width of link(x%d)\n", width, v); 1341 } 1342 1343 /* Clear status list. */ 1344 bzero(sc->msk_stat_ring, 1345 sizeof(struct msk_stat_desc) * MSK_STAT_RING_CNT); 1346 sc->msk_stat_cons = 0; 1347 bus_dmamap_sync(sc->msk_stat_tag, sc->msk_stat_map, 1348 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1349 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_RST_SET); 1350 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_RST_CLR); 1351 /* Set the status list base address. */ 1352 addr = sc->msk_stat_ring_paddr; 1353 CSR_WRITE_4(sc, STAT_LIST_ADDR_LO, MSK_ADDR_LO(addr)); 1354 CSR_WRITE_4(sc, STAT_LIST_ADDR_HI, MSK_ADDR_HI(addr)); 1355 /* Set the status list last index. */ 1356 CSR_WRITE_2(sc, STAT_LAST_IDX, MSK_STAT_RING_CNT - 1); 1357 if (sc->msk_hw_id == CHIP_ID_YUKON_EC && 1358 sc->msk_hw_rev == CHIP_REV_YU_EC_A1) { 1359 /* WA for dev. #4.3 */ 1360 CSR_WRITE_2(sc, STAT_TX_IDX_TH, ST_TXTH_IDX_MASK); 1361 /* WA for dev. #4.18 */ 1362 CSR_WRITE_1(sc, STAT_FIFO_WM, 0x21); 1363 CSR_WRITE_1(sc, STAT_FIFO_ISR_WM, 0x07); 1364 } else { 1365 CSR_WRITE_2(sc, STAT_TX_IDX_TH, 0x0a); 1366 CSR_WRITE_1(sc, STAT_FIFO_WM, 0x10); 1367 if (sc->msk_hw_id == CHIP_ID_YUKON_XL && 1368 sc->msk_hw_rev == CHIP_REV_YU_XL_A0) 1369 CSR_WRITE_1(sc, STAT_FIFO_ISR_WM, 0x04); 1370 else 1371 CSR_WRITE_1(sc, STAT_FIFO_ISR_WM, 0x10); 1372 CSR_WRITE_4(sc, STAT_ISR_TIMER_INI, 0x0190); 1373 } 1374 /* 1375 * Use default value for STAT_ISR_TIMER_INI, STAT_LEV_TIMER_INI. 1376 */ 1377 CSR_WRITE_4(sc, STAT_TX_TIMER_INI, MSK_USECS(sc, 1000)); 1378 1379 /* Enable status unit. */ 1380 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_OP_ON); 1381 1382 CSR_WRITE_1(sc, STAT_TX_TIMER_CTRL, TIM_START); 1383 CSR_WRITE_1(sc, STAT_LEV_TIMER_CTRL, TIM_START); 1384 CSR_WRITE_1(sc, STAT_ISR_TIMER_CTRL, TIM_START); 1385 } 1386 1387 static int 1388 msk_probe(device_t dev) 1389 { 1390 struct msk_softc *sc; 1391 char desc[100]; 1392 1393 sc = device_get_softc(device_get_parent(dev)); 1394 /* 1395 * Not much to do here. We always know there will be 1396 * at least one GMAC present, and if there are two, 1397 * mskc_attach() will create a second device instance 1398 * for us. 1399 */ 1400 snprintf(desc, sizeof(desc), 1401 "Marvell Technology Group Ltd. %s Id 0x%02x Rev 0x%02x", 1402 model_name[sc->msk_hw_id - CHIP_ID_YUKON_XL], sc->msk_hw_id, 1403 sc->msk_hw_rev); 1404 device_set_desc_copy(dev, desc); 1405 1406 return (BUS_PROBE_DEFAULT); 1407 } 1408 1409 static int 1410 msk_attach(device_t dev) 1411 { 1412 struct msk_softc *sc; 1413 struct msk_if_softc *sc_if; 1414 struct ifnet *ifp; 1415 int i, port, error; 1416 uint8_t eaddr[6]; 1417 1418 if (dev == NULL) 1419 return (EINVAL); 1420 1421 error = 0; 1422 sc_if = device_get_softc(dev); 1423 sc = device_get_softc(device_get_parent(dev)); 1424 port = *(int *)device_get_ivars(dev); 1425 1426 sc_if->msk_if_dev = dev; 1427 sc_if->msk_port = port; 1428 sc_if->msk_softc = sc; 1429 sc_if->msk_flags = sc->msk_pflags; 1430 sc->msk_if[port] = sc_if; 1431 /* Setup Tx/Rx queue register offsets. */ 1432 if (port == MSK_PORT_A) { 1433 sc_if->msk_txq = Q_XA1; 1434 sc_if->msk_txsq = Q_XS1; 1435 sc_if->msk_rxq = Q_R1; 1436 } else { 1437 sc_if->msk_txq = Q_XA2; 1438 sc_if->msk_txsq = Q_XS2; 1439 sc_if->msk_rxq = Q_R2; 1440 } 1441 1442 callout_init_mtx(&sc_if->msk_tick_ch, &sc_if->msk_softc->msk_mtx, 0); 1443 msk_sysctl_node(sc_if); 1444 1445 if ((error = msk_txrx_dma_alloc(sc_if) != 0)) 1446 goto fail; 1447 msk_rx_dma_jalloc(sc_if); 1448 1449 ifp = sc_if->msk_ifp = if_alloc(IFT_ETHER); 1450 if (ifp == NULL) { 1451 device_printf(sc_if->msk_if_dev, "can not if_alloc()\n"); 1452 error = ENOSPC; 1453 goto fail; 1454 } 1455 ifp->if_softc = sc_if; 1456 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1457 ifp->if_mtu = ETHERMTU; 1458 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1459 /* 1460 * IFCAP_RXCSUM capability is intentionally disabled as the hardware 1461 * has serious bug in Rx checksum offload for all Yukon II family 1462 * hardware. It seems there is a workaround to make it work somtimes. 1463 * However, the workaround also have to check OP code sequences to 1464 * verify whether the OP code is correct. Sometimes it should compute 1465 * IP/TCP/UDP checksum in driver in order to verify correctness of 1466 * checksum computed by hardware. If you have to compute checksum 1467 * with software to verify the hardware's checksum why have hardware 1468 * compute the checksum? I think there is no reason to spend time to 1469 * make Rx checksum offload work on Yukon II hardware. 1470 */ 1471 ifp->if_capabilities = IFCAP_TXCSUM | IFCAP_TSO4; 1472 ifp->if_hwassist = MSK_CSUM_FEATURES | CSUM_TSO; 1473 ifp->if_capenable = ifp->if_capabilities; 1474 ifp->if_ioctl = msk_ioctl; 1475 ifp->if_start = msk_start; 1476 ifp->if_timer = 0; 1477 ifp->if_watchdog = NULL; 1478 ifp->if_init = msk_init; 1479 IFQ_SET_MAXLEN(&ifp->if_snd, MSK_TX_RING_CNT - 1); 1480 ifp->if_snd.ifq_drv_maxlen = MSK_TX_RING_CNT - 1; 1481 IFQ_SET_READY(&ifp->if_snd); 1482 1483 TASK_INIT(&sc_if->msk_tx_task, 1, msk_tx_task, ifp); 1484 1485 /* 1486 * Get station address for this interface. Note that 1487 * dual port cards actually come with three station 1488 * addresses: one for each port, plus an extra. The 1489 * extra one is used by the SysKonnect driver software 1490 * as a 'virtual' station address for when both ports 1491 * are operating in failover mode. Currently we don't 1492 * use this extra address. 1493 */ 1494 MSK_IF_LOCK(sc_if); 1495 for (i = 0; i < ETHER_ADDR_LEN; i++) 1496 eaddr[i] = CSR_READ_1(sc, B2_MAC_1 + (port * 8) + i); 1497 1498 /* 1499 * Call MI attach routine. Can't hold locks when calling into ether_*. 1500 */ 1501 MSK_IF_UNLOCK(sc_if); 1502 ether_ifattach(ifp, eaddr); 1503 MSK_IF_LOCK(sc_if); 1504 1505 /* VLAN capability setup */ 1506 ifp->if_capabilities |= IFCAP_VLAN_MTU; 1507 if ((sc_if->msk_flags & MSK_FLAG_NOHWVLAN) == 0) { 1508 /* 1509 * Due to Tx checksum offload hardware bugs, msk(4) manually 1510 * computes checksum for short frames. For VLAN tagged frames 1511 * this workaround does not work so disable checksum offload 1512 * for VLAN interface. 1513 */ 1514 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING; 1515 } 1516 ifp->if_capenable = ifp->if_capabilities; 1517 1518 /* 1519 * Tell the upper layer(s) we support long frames. 1520 * Must appear after the call to ether_ifattach() because 1521 * ether_ifattach() sets ifi_hdrlen to the default value. 1522 */ 1523 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1524 1525 /* 1526 * Do miibus setup. 1527 */ 1528 MSK_IF_UNLOCK(sc_if); 1529 error = mii_phy_probe(dev, &sc_if->msk_miibus, msk_mediachange, 1530 msk_mediastatus); 1531 if (error != 0) { 1532 device_printf(sc_if->msk_if_dev, "no PHY found!\n"); 1533 ether_ifdetach(ifp); 1534 error = ENXIO; 1535 goto fail; 1536 } 1537 1538 fail: 1539 if (error != 0) { 1540 /* Access should be ok even though lock has been dropped */ 1541 sc->msk_if[port] = NULL; 1542 msk_detach(dev); 1543 } 1544 1545 return (error); 1546 } 1547 1548 /* 1549 * Attach the interface. Allocate softc structures, do ifmedia 1550 * setup and ethernet/BPF attach. 1551 */ 1552 static int 1553 mskc_attach(device_t dev) 1554 { 1555 struct msk_softc *sc; 1556 int error, msic, msir, *port, reg; 1557 1558 sc = device_get_softc(dev); 1559 sc->msk_dev = dev; 1560 mtx_init(&sc->msk_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1561 MTX_DEF); 1562 1563 /* 1564 * Map control/status registers. 1565 */ 1566 pci_enable_busmaster(dev); 1567 1568 /* Allocate I/O resource */ 1569 #ifdef MSK_USEIOSPACE 1570 sc->msk_res_spec = msk_res_spec_io; 1571 #else 1572 sc->msk_res_spec = msk_res_spec_mem; 1573 #endif 1574 sc->msk_irq_spec = msk_irq_spec_legacy; 1575 error = bus_alloc_resources(dev, sc->msk_res_spec, sc->msk_res); 1576 if (error) { 1577 if (sc->msk_res_spec == msk_res_spec_mem) 1578 sc->msk_res_spec = msk_res_spec_io; 1579 else 1580 sc->msk_res_spec = msk_res_spec_mem; 1581 error = bus_alloc_resources(dev, sc->msk_res_spec, sc->msk_res); 1582 if (error) { 1583 device_printf(dev, "couldn't allocate %s resources\n", 1584 sc->msk_res_spec == msk_res_spec_mem ? "memory" : 1585 "I/O"); 1586 mtx_destroy(&sc->msk_mtx); 1587 return (ENXIO); 1588 } 1589 } 1590 1591 CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR); 1592 sc->msk_hw_id = CSR_READ_1(sc, B2_CHIP_ID); 1593 sc->msk_hw_rev = (CSR_READ_1(sc, B2_MAC_CFG) >> 4) & 0x0f; 1594 /* Bail out if chip is not recognized. */ 1595 if (sc->msk_hw_id < CHIP_ID_YUKON_XL || 1596 sc->msk_hw_id > CHIP_ID_YUKON_FE_P) { 1597 device_printf(dev, "unknown device: id=0x%02x, rev=0x%02x\n", 1598 sc->msk_hw_id, sc->msk_hw_rev); 1599 mtx_destroy(&sc->msk_mtx); 1600 return (ENXIO); 1601 } 1602 1603 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 1604 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 1605 OID_AUTO, "process_limit", CTLTYPE_INT | CTLFLAG_RW, 1606 &sc->msk_process_limit, 0, sysctl_hw_msk_proc_limit, "I", 1607 "max number of Rx events to process"); 1608 1609 sc->msk_process_limit = MSK_PROC_DEFAULT; 1610 error = resource_int_value(device_get_name(dev), device_get_unit(dev), 1611 "process_limit", &sc->msk_process_limit); 1612 if (error == 0) { 1613 if (sc->msk_process_limit < MSK_PROC_MIN || 1614 sc->msk_process_limit > MSK_PROC_MAX) { 1615 device_printf(dev, "process_limit value out of range; " 1616 "using default: %d\n", MSK_PROC_DEFAULT); 1617 sc->msk_process_limit = MSK_PROC_DEFAULT; 1618 } 1619 } 1620 1621 /* Soft reset. */ 1622 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); 1623 CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR); 1624 sc->msk_pmd = CSR_READ_1(sc, B2_PMD_TYP); 1625 if (sc->msk_pmd == 'L' || sc->msk_pmd == 'S') 1626 sc->msk_coppertype = 0; 1627 else 1628 sc->msk_coppertype = 1; 1629 /* Check number of MACs. */ 1630 sc->msk_num_port = 1; 1631 if ((CSR_READ_1(sc, B2_Y2_HW_RES) & CFG_DUAL_MAC_MSK) == 1632 CFG_DUAL_MAC_MSK) { 1633 if (!(CSR_READ_1(sc, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC)) 1634 sc->msk_num_port++; 1635 } 1636 1637 /* Check bus type. */ 1638 if (pci_find_extcap(sc->msk_dev, PCIY_EXPRESS, ®) == 0) 1639 sc->msk_bustype = MSK_PEX_BUS; 1640 else if (pci_find_extcap(sc->msk_dev, PCIY_PCIX, ®) == 0) 1641 sc->msk_bustype = MSK_PCIX_BUS; 1642 else 1643 sc->msk_bustype = MSK_PCI_BUS; 1644 1645 switch (sc->msk_hw_id) { 1646 case CHIP_ID_YUKON_EC: 1647 sc->msk_clock = 125; /* 125 Mhz */ 1648 sc->msk_pflags |= MSK_FLAG_JUMBO; 1649 break; 1650 case CHIP_ID_YUKON_EC_U: 1651 sc->msk_clock = 125; /* 125 Mhz */ 1652 sc->msk_pflags |= MSK_FLAG_JUMBO | MSK_FLAG_JUMBO_NOCSUM; 1653 break; 1654 case CHIP_ID_YUKON_FE: 1655 sc->msk_clock = 100; /* 100 Mhz */ 1656 sc->msk_pflags |= MSK_FLAG_FASTETHER; 1657 break; 1658 case CHIP_ID_YUKON_FE_P: 1659 sc->msk_clock = 50; /* 50 Mhz */ 1660 sc->msk_pflags |= MSK_FLAG_FASTETHER | MSK_FLAG_DESCV2; 1661 if (sc->msk_hw_rev == CHIP_REV_YU_FE_P_A0) { 1662 /* 1663 * XXX 1664 * FE+ A0 has status LE writeback bug so msk(4) 1665 * does not rely on status word of received frame 1666 * in msk_rxeof() which in turn disables all 1667 * hardware assistance bits reported by the status 1668 * word as well as validity of the recevied frame. 1669 * Just pass received frames to upper stack with 1670 * minimal test and let upper stack handle them. 1671 */ 1672 sc->msk_pflags |= MSK_FLAG_NOHWVLAN | MSK_FLAG_NORXCHK; 1673 } 1674 break; 1675 case CHIP_ID_YUKON_XL: 1676 sc->msk_clock = 156; /* 156 Mhz */ 1677 sc->msk_pflags |= MSK_FLAG_JUMBO; 1678 break; 1679 default: 1680 sc->msk_clock = 156; /* 156 Mhz */ 1681 break; 1682 } 1683 1684 /* Allocate IRQ resources. */ 1685 msic = pci_msi_count(dev); 1686 if (bootverbose) 1687 device_printf(dev, "MSI count : %d\n", msic); 1688 /* 1689 * The Yukon II reports it can handle two messages, one for each 1690 * possible port. We go ahead and allocate two messages and only 1691 * setup a handler for both if we have a dual port card. 1692 * 1693 * XXX: I haven't untangled the interrupt handler to handle dual 1694 * port cards with separate MSI messages, so for now I disable MSI 1695 * on dual port cards. 1696 */ 1697 if (legacy_intr != 0) 1698 msi_disable = 1; 1699 if (msi_disable == 0) { 1700 switch (msic) { 1701 case 2: 1702 case 1: /* 88E8058 reports 1 MSI message */ 1703 msir = msic; 1704 if (sc->msk_num_port == 1 && 1705 pci_alloc_msi(dev, &msir) == 0) { 1706 if (msic == msir) { 1707 sc->msk_pflags |= MSK_FLAG_MSI; 1708 sc->msk_irq_spec = msic == 2 ? 1709 msk_irq_spec_msi2 : 1710 msk_irq_spec_msi; 1711 } else 1712 pci_release_msi(dev); 1713 } 1714 break; 1715 default: 1716 device_printf(dev, 1717 "Unexpected number of MSI messages : %d\n", msic); 1718 break; 1719 } 1720 } 1721 1722 error = bus_alloc_resources(dev, sc->msk_irq_spec, sc->msk_irq); 1723 if (error) { 1724 device_printf(dev, "couldn't allocate IRQ resources\n"); 1725 goto fail; 1726 } 1727 1728 if ((error = msk_status_dma_alloc(sc)) != 0) 1729 goto fail; 1730 1731 /* Set base interrupt mask. */ 1732 sc->msk_intrmask = Y2_IS_HW_ERR | Y2_IS_STAT_BMU; 1733 sc->msk_intrhwemask = Y2_IS_TIST_OV | Y2_IS_MST_ERR | 1734 Y2_IS_IRQ_STAT | Y2_IS_PCI_EXP | Y2_IS_PCI_NEXP; 1735 1736 /* Reset the adapter. */ 1737 mskc_reset(sc); 1738 1739 if ((error = mskc_setup_rambuffer(sc)) != 0) 1740 goto fail; 1741 1742 sc->msk_devs[MSK_PORT_A] = device_add_child(dev, "msk", -1); 1743 if (sc->msk_devs[MSK_PORT_A] == NULL) { 1744 device_printf(dev, "failed to add child for PORT_A\n"); 1745 error = ENXIO; 1746 goto fail; 1747 } 1748 port = malloc(sizeof(int), M_DEVBUF, M_WAITOK); 1749 if (port == NULL) { 1750 device_printf(dev, "failed to allocate memory for " 1751 "ivars of PORT_A\n"); 1752 error = ENXIO; 1753 goto fail; 1754 } 1755 *port = MSK_PORT_A; 1756 device_set_ivars(sc->msk_devs[MSK_PORT_A], port); 1757 1758 if (sc->msk_num_port > 1) { 1759 sc->msk_devs[MSK_PORT_B] = device_add_child(dev, "msk", -1); 1760 if (sc->msk_devs[MSK_PORT_B] == NULL) { 1761 device_printf(dev, "failed to add child for PORT_B\n"); 1762 error = ENXIO; 1763 goto fail; 1764 } 1765 port = malloc(sizeof(int), M_DEVBUF, M_WAITOK); 1766 if (port == NULL) { 1767 device_printf(dev, "failed to allocate memory for " 1768 "ivars of PORT_B\n"); 1769 error = ENXIO; 1770 goto fail; 1771 } 1772 *port = MSK_PORT_B; 1773 device_set_ivars(sc->msk_devs[MSK_PORT_B], port); 1774 } 1775 1776 error = bus_generic_attach(dev); 1777 if (error) { 1778 device_printf(dev, "failed to attach port(s)\n"); 1779 goto fail; 1780 } 1781 1782 /* Hook interrupt last to avoid having to lock softc. */ 1783 if (legacy_intr) 1784 error = bus_setup_intr(dev, sc->msk_irq[0], INTR_TYPE_NET | 1785 INTR_MPSAFE, NULL, msk_legacy_intr, sc, 1786 &sc->msk_intrhand[0]); 1787 else { 1788 TASK_INIT(&sc->msk_int_task, 0, msk_int_task, sc); 1789 sc->msk_tq = taskqueue_create_fast("msk_taskq", M_WAITOK, 1790 taskqueue_thread_enqueue, &sc->msk_tq); 1791 taskqueue_start_threads(&sc->msk_tq, 1, PI_NET, "%s taskq", 1792 device_get_nameunit(sc->msk_dev)); 1793 error = bus_setup_intr(dev, sc->msk_irq[0], INTR_TYPE_NET | 1794 INTR_MPSAFE, msk_intr, NULL, sc, &sc->msk_intrhand[0]); 1795 } 1796 1797 if (error != 0) { 1798 device_printf(dev, "couldn't set up interrupt handler\n"); 1799 if (legacy_intr == 0) 1800 taskqueue_free(sc->msk_tq); 1801 sc->msk_tq = NULL; 1802 goto fail; 1803 } 1804 fail: 1805 if (error != 0) 1806 mskc_detach(dev); 1807 1808 return (error); 1809 } 1810 1811 /* 1812 * Shutdown hardware and free up resources. This can be called any 1813 * time after the mutex has been initialized. It is called in both 1814 * the error case in attach and the normal detach case so it needs 1815 * to be careful about only freeing resources that have actually been 1816 * allocated. 1817 */ 1818 static int 1819 msk_detach(device_t dev) 1820 { 1821 struct msk_softc *sc; 1822 struct msk_if_softc *sc_if; 1823 struct ifnet *ifp; 1824 1825 sc_if = device_get_softc(dev); 1826 KASSERT(mtx_initialized(&sc_if->msk_softc->msk_mtx), 1827 ("msk mutex not initialized in msk_detach")); 1828 MSK_IF_LOCK(sc_if); 1829 1830 ifp = sc_if->msk_ifp; 1831 if (device_is_attached(dev)) { 1832 /* XXX */ 1833 sc_if->msk_flags |= MSK_FLAG_DETACH; 1834 msk_stop(sc_if); 1835 /* Can't hold locks while calling detach. */ 1836 MSK_IF_UNLOCK(sc_if); 1837 callout_drain(&sc_if->msk_tick_ch); 1838 taskqueue_drain(taskqueue_fast, &sc_if->msk_tx_task); 1839 ether_ifdetach(ifp); 1840 MSK_IF_LOCK(sc_if); 1841 } 1842 1843 /* 1844 * We're generally called from mskc_detach() which is using 1845 * device_delete_child() to get to here. It's already trashed 1846 * miibus for us, so don't do it here or we'll panic. 1847 * 1848 * if (sc_if->msk_miibus != NULL) { 1849 * device_delete_child(dev, sc_if->msk_miibus); 1850 * sc_if->msk_miibus = NULL; 1851 * } 1852 */ 1853 1854 msk_rx_dma_jfree(sc_if); 1855 msk_txrx_dma_free(sc_if); 1856 bus_generic_detach(dev); 1857 1858 if (ifp) 1859 if_free(ifp); 1860 sc = sc_if->msk_softc; 1861 sc->msk_if[sc_if->msk_port] = NULL; 1862 MSK_IF_UNLOCK(sc_if); 1863 1864 return (0); 1865 } 1866 1867 static int 1868 mskc_detach(device_t dev) 1869 { 1870 struct msk_softc *sc; 1871 1872 sc = device_get_softc(dev); 1873 KASSERT(mtx_initialized(&sc->msk_mtx), ("msk mutex not initialized")); 1874 1875 if (device_is_alive(dev)) { 1876 if (sc->msk_devs[MSK_PORT_A] != NULL) { 1877 free(device_get_ivars(sc->msk_devs[MSK_PORT_A]), 1878 M_DEVBUF); 1879 device_delete_child(dev, sc->msk_devs[MSK_PORT_A]); 1880 } 1881 if (sc->msk_devs[MSK_PORT_B] != NULL) { 1882 free(device_get_ivars(sc->msk_devs[MSK_PORT_B]), 1883 M_DEVBUF); 1884 device_delete_child(dev, sc->msk_devs[MSK_PORT_B]); 1885 } 1886 bus_generic_detach(dev); 1887 } 1888 1889 /* Disable all interrupts. */ 1890 CSR_WRITE_4(sc, B0_IMSK, 0); 1891 CSR_READ_4(sc, B0_IMSK); 1892 CSR_WRITE_4(sc, B0_HWE_IMSK, 0); 1893 CSR_READ_4(sc, B0_HWE_IMSK); 1894 1895 /* LED Off. */ 1896 CSR_WRITE_2(sc, B0_CTST, Y2_LED_STAT_OFF); 1897 1898 /* Put hardware reset. */ 1899 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); 1900 1901 msk_status_dma_free(sc); 1902 1903 if (legacy_intr == 0 && sc->msk_tq != NULL) { 1904 taskqueue_drain(sc->msk_tq, &sc->msk_int_task); 1905 taskqueue_free(sc->msk_tq); 1906 sc->msk_tq = NULL; 1907 } 1908 if (sc->msk_intrhand[0]) { 1909 bus_teardown_intr(dev, sc->msk_irq[0], sc->msk_intrhand[0]); 1910 sc->msk_intrhand[0] = NULL; 1911 } 1912 if (sc->msk_intrhand[1]) { 1913 bus_teardown_intr(dev, sc->msk_irq[0], sc->msk_intrhand[0]); 1914 sc->msk_intrhand[1] = NULL; 1915 } 1916 bus_release_resources(dev, sc->msk_irq_spec, sc->msk_irq); 1917 if ((sc->msk_pflags & MSK_FLAG_MSI) != 0) 1918 pci_release_msi(dev); 1919 bus_release_resources(dev, sc->msk_res_spec, sc->msk_res); 1920 mtx_destroy(&sc->msk_mtx); 1921 1922 return (0); 1923 } 1924 1925 struct msk_dmamap_arg { 1926 bus_addr_t msk_busaddr; 1927 }; 1928 1929 static void 1930 msk_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1931 { 1932 struct msk_dmamap_arg *ctx; 1933 1934 if (error != 0) 1935 return; 1936 ctx = arg; 1937 ctx->msk_busaddr = segs[0].ds_addr; 1938 } 1939 1940 /* Create status DMA region. */ 1941 static int 1942 msk_status_dma_alloc(struct msk_softc *sc) 1943 { 1944 struct msk_dmamap_arg ctx; 1945 int error; 1946 1947 error = bus_dma_tag_create( 1948 bus_get_dma_tag(sc->msk_dev), /* parent */ 1949 MSK_STAT_ALIGN, 0, /* alignment, boundary */ 1950 BUS_SPACE_MAXADDR, /* lowaddr */ 1951 BUS_SPACE_MAXADDR, /* highaddr */ 1952 NULL, NULL, /* filter, filterarg */ 1953 MSK_STAT_RING_SZ, /* maxsize */ 1954 1, /* nsegments */ 1955 MSK_STAT_RING_SZ, /* maxsegsize */ 1956 0, /* flags */ 1957 NULL, NULL, /* lockfunc, lockarg */ 1958 &sc->msk_stat_tag); 1959 if (error != 0) { 1960 device_printf(sc->msk_dev, 1961 "failed to create status DMA tag\n"); 1962 return (error); 1963 } 1964 1965 /* Allocate DMA'able memory and load the DMA map for status ring. */ 1966 error = bus_dmamem_alloc(sc->msk_stat_tag, 1967 (void **)&sc->msk_stat_ring, BUS_DMA_WAITOK | BUS_DMA_COHERENT | 1968 BUS_DMA_ZERO, &sc->msk_stat_map); 1969 if (error != 0) { 1970 device_printf(sc->msk_dev, 1971 "failed to allocate DMA'able memory for status ring\n"); 1972 return (error); 1973 } 1974 1975 ctx.msk_busaddr = 0; 1976 error = bus_dmamap_load(sc->msk_stat_tag, 1977 sc->msk_stat_map, sc->msk_stat_ring, MSK_STAT_RING_SZ, 1978 msk_dmamap_cb, &ctx, 0); 1979 if (error != 0) { 1980 device_printf(sc->msk_dev, 1981 "failed to load DMA'able memory for status ring\n"); 1982 return (error); 1983 } 1984 sc->msk_stat_ring_paddr = ctx.msk_busaddr; 1985 1986 return (0); 1987 } 1988 1989 static void 1990 msk_status_dma_free(struct msk_softc *sc) 1991 { 1992 1993 /* Destroy status block. */ 1994 if (sc->msk_stat_tag) { 1995 if (sc->msk_stat_map) { 1996 bus_dmamap_unload(sc->msk_stat_tag, sc->msk_stat_map); 1997 if (sc->msk_stat_ring) { 1998 bus_dmamem_free(sc->msk_stat_tag, 1999 sc->msk_stat_ring, sc->msk_stat_map); 2000 sc->msk_stat_ring = NULL; 2001 } 2002 sc->msk_stat_map = NULL; 2003 } 2004 bus_dma_tag_destroy(sc->msk_stat_tag); 2005 sc->msk_stat_tag = NULL; 2006 } 2007 } 2008 2009 static int 2010 msk_txrx_dma_alloc(struct msk_if_softc *sc_if) 2011 { 2012 struct msk_dmamap_arg ctx; 2013 struct msk_txdesc *txd; 2014 struct msk_rxdesc *rxd; 2015 bus_size_t rxalign; 2016 int error, i; 2017 2018 /* Create parent DMA tag. */ 2019 /* 2020 * XXX 2021 * It seems that Yukon II supports full 64bits DMA operations. But 2022 * it needs two descriptors(list elements) for 64bits DMA operations. 2023 * Since we don't know what DMA address mappings(32bits or 64bits) 2024 * would be used in advance for each mbufs, we limits its DMA space 2025 * to be in range of 32bits address space. Otherwise, we should check 2026 * what DMA address is used and chain another descriptor for the 2027 * 64bits DMA operation. This also means descriptor ring size is 2028 * variable. Limiting DMA address to be in 32bit address space greatly 2029 * simplyfies descriptor handling and possibly would increase 2030 * performance a bit due to efficient handling of descriptors. 2031 * Apart from harassing checksum offloading mechanisms, it seems 2032 * it's really bad idea to use a seperate descriptor for 64bit 2033 * DMA operation to save small descriptor memory. Anyway, I've 2034 * never seen these exotic scheme on ethernet interface hardware. 2035 */ 2036 error = bus_dma_tag_create( 2037 bus_get_dma_tag(sc_if->msk_if_dev), /* parent */ 2038 1, 0, /* alignment, boundary */ 2039 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 2040 BUS_SPACE_MAXADDR, /* highaddr */ 2041 NULL, NULL, /* filter, filterarg */ 2042 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 2043 0, /* nsegments */ 2044 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 2045 0, /* flags */ 2046 NULL, NULL, /* lockfunc, lockarg */ 2047 &sc_if->msk_cdata.msk_parent_tag); 2048 if (error != 0) { 2049 device_printf(sc_if->msk_if_dev, 2050 "failed to create parent DMA tag\n"); 2051 goto fail; 2052 } 2053 /* Create tag for Tx ring. */ 2054 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2055 MSK_RING_ALIGN, 0, /* alignment, boundary */ 2056 BUS_SPACE_MAXADDR, /* lowaddr */ 2057 BUS_SPACE_MAXADDR, /* highaddr */ 2058 NULL, NULL, /* filter, filterarg */ 2059 MSK_TX_RING_SZ, /* maxsize */ 2060 1, /* nsegments */ 2061 MSK_TX_RING_SZ, /* maxsegsize */ 2062 0, /* flags */ 2063 NULL, NULL, /* lockfunc, lockarg */ 2064 &sc_if->msk_cdata.msk_tx_ring_tag); 2065 if (error != 0) { 2066 device_printf(sc_if->msk_if_dev, 2067 "failed to create Tx ring DMA tag\n"); 2068 goto fail; 2069 } 2070 2071 /* Create tag for Rx ring. */ 2072 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2073 MSK_RING_ALIGN, 0, /* alignment, boundary */ 2074 BUS_SPACE_MAXADDR, /* lowaddr */ 2075 BUS_SPACE_MAXADDR, /* highaddr */ 2076 NULL, NULL, /* filter, filterarg */ 2077 MSK_RX_RING_SZ, /* maxsize */ 2078 1, /* nsegments */ 2079 MSK_RX_RING_SZ, /* maxsegsize */ 2080 0, /* flags */ 2081 NULL, NULL, /* lockfunc, lockarg */ 2082 &sc_if->msk_cdata.msk_rx_ring_tag); 2083 if (error != 0) { 2084 device_printf(sc_if->msk_if_dev, 2085 "failed to create Rx ring DMA tag\n"); 2086 goto fail; 2087 } 2088 2089 /* Create tag for Tx buffers. */ 2090 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2091 1, 0, /* alignment, boundary */ 2092 BUS_SPACE_MAXADDR, /* lowaddr */ 2093 BUS_SPACE_MAXADDR, /* highaddr */ 2094 NULL, NULL, /* filter, filterarg */ 2095 MSK_TSO_MAXSIZE, /* maxsize */ 2096 MSK_MAXTXSEGS, /* nsegments */ 2097 MSK_TSO_MAXSGSIZE, /* maxsegsize */ 2098 0, /* flags */ 2099 NULL, NULL, /* lockfunc, lockarg */ 2100 &sc_if->msk_cdata.msk_tx_tag); 2101 if (error != 0) { 2102 device_printf(sc_if->msk_if_dev, 2103 "failed to create Tx DMA tag\n"); 2104 goto fail; 2105 } 2106 2107 rxalign = 1; 2108 /* 2109 * Workaround hardware hang which seems to happen when Rx buffer 2110 * is not aligned on multiple of FIFO word(8 bytes). 2111 */ 2112 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) != 0) 2113 rxalign = MSK_RX_BUF_ALIGN; 2114 /* Create tag for Rx buffers. */ 2115 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2116 rxalign, 0, /* alignment, boundary */ 2117 BUS_SPACE_MAXADDR, /* lowaddr */ 2118 BUS_SPACE_MAXADDR, /* highaddr */ 2119 NULL, NULL, /* filter, filterarg */ 2120 MCLBYTES, /* maxsize */ 2121 1, /* nsegments */ 2122 MCLBYTES, /* maxsegsize */ 2123 0, /* flags */ 2124 NULL, NULL, /* lockfunc, lockarg */ 2125 &sc_if->msk_cdata.msk_rx_tag); 2126 if (error != 0) { 2127 device_printf(sc_if->msk_if_dev, 2128 "failed to create Rx DMA tag\n"); 2129 goto fail; 2130 } 2131 2132 /* Allocate DMA'able memory and load the DMA map for Tx ring. */ 2133 error = bus_dmamem_alloc(sc_if->msk_cdata.msk_tx_ring_tag, 2134 (void **)&sc_if->msk_rdata.msk_tx_ring, BUS_DMA_WAITOK | 2135 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc_if->msk_cdata.msk_tx_ring_map); 2136 if (error != 0) { 2137 device_printf(sc_if->msk_if_dev, 2138 "failed to allocate DMA'able memory for Tx ring\n"); 2139 goto fail; 2140 } 2141 2142 ctx.msk_busaddr = 0; 2143 error = bus_dmamap_load(sc_if->msk_cdata.msk_tx_ring_tag, 2144 sc_if->msk_cdata.msk_tx_ring_map, sc_if->msk_rdata.msk_tx_ring, 2145 MSK_TX_RING_SZ, msk_dmamap_cb, &ctx, 0); 2146 if (error != 0) { 2147 device_printf(sc_if->msk_if_dev, 2148 "failed to load DMA'able memory for Tx ring\n"); 2149 goto fail; 2150 } 2151 sc_if->msk_rdata.msk_tx_ring_paddr = ctx.msk_busaddr; 2152 2153 /* Allocate DMA'able memory and load the DMA map for Rx ring. */ 2154 error = bus_dmamem_alloc(sc_if->msk_cdata.msk_rx_ring_tag, 2155 (void **)&sc_if->msk_rdata.msk_rx_ring, BUS_DMA_WAITOK | 2156 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc_if->msk_cdata.msk_rx_ring_map); 2157 if (error != 0) { 2158 device_printf(sc_if->msk_if_dev, 2159 "failed to allocate DMA'able memory for Rx ring\n"); 2160 goto fail; 2161 } 2162 2163 ctx.msk_busaddr = 0; 2164 error = bus_dmamap_load(sc_if->msk_cdata.msk_rx_ring_tag, 2165 sc_if->msk_cdata.msk_rx_ring_map, sc_if->msk_rdata.msk_rx_ring, 2166 MSK_RX_RING_SZ, msk_dmamap_cb, &ctx, 0); 2167 if (error != 0) { 2168 device_printf(sc_if->msk_if_dev, 2169 "failed to load DMA'able memory for Rx ring\n"); 2170 goto fail; 2171 } 2172 sc_if->msk_rdata.msk_rx_ring_paddr = ctx.msk_busaddr; 2173 2174 /* Create DMA maps for Tx buffers. */ 2175 for (i = 0; i < MSK_TX_RING_CNT; i++) { 2176 txd = &sc_if->msk_cdata.msk_txdesc[i]; 2177 txd->tx_m = NULL; 2178 txd->tx_dmamap = NULL; 2179 error = bus_dmamap_create(sc_if->msk_cdata.msk_tx_tag, 0, 2180 &txd->tx_dmamap); 2181 if (error != 0) { 2182 device_printf(sc_if->msk_if_dev, 2183 "failed to create Tx dmamap\n"); 2184 goto fail; 2185 } 2186 } 2187 /* Create DMA maps for Rx buffers. */ 2188 if ((error = bus_dmamap_create(sc_if->msk_cdata.msk_rx_tag, 0, 2189 &sc_if->msk_cdata.msk_rx_sparemap)) != 0) { 2190 device_printf(sc_if->msk_if_dev, 2191 "failed to create spare Rx dmamap\n"); 2192 goto fail; 2193 } 2194 for (i = 0; i < MSK_RX_RING_CNT; i++) { 2195 rxd = &sc_if->msk_cdata.msk_rxdesc[i]; 2196 rxd->rx_m = NULL; 2197 rxd->rx_dmamap = NULL; 2198 error = bus_dmamap_create(sc_if->msk_cdata.msk_rx_tag, 0, 2199 &rxd->rx_dmamap); 2200 if (error != 0) { 2201 device_printf(sc_if->msk_if_dev, 2202 "failed to create Rx dmamap\n"); 2203 goto fail; 2204 } 2205 } 2206 2207 fail: 2208 return (error); 2209 } 2210 2211 static int 2212 msk_rx_dma_jalloc(struct msk_if_softc *sc_if) 2213 { 2214 struct msk_dmamap_arg ctx; 2215 struct msk_rxdesc *jrxd; 2216 bus_size_t rxalign; 2217 int error, i; 2218 2219 if (jumbo_disable != 0 || (sc_if->msk_flags & MSK_FLAG_JUMBO) == 0) { 2220 sc_if->msk_flags &= ~MSK_FLAG_JUMBO; 2221 device_printf(sc_if->msk_if_dev, 2222 "disabling jumbo frame support\n"); 2223 return (0); 2224 } 2225 /* Create tag for jumbo Rx ring. */ 2226 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2227 MSK_RING_ALIGN, 0, /* alignment, boundary */ 2228 BUS_SPACE_MAXADDR, /* lowaddr */ 2229 BUS_SPACE_MAXADDR, /* highaddr */ 2230 NULL, NULL, /* filter, filterarg */ 2231 MSK_JUMBO_RX_RING_SZ, /* maxsize */ 2232 1, /* nsegments */ 2233 MSK_JUMBO_RX_RING_SZ, /* maxsegsize */ 2234 0, /* flags */ 2235 NULL, NULL, /* lockfunc, lockarg */ 2236 &sc_if->msk_cdata.msk_jumbo_rx_ring_tag); 2237 if (error != 0) { 2238 device_printf(sc_if->msk_if_dev, 2239 "failed to create jumbo Rx ring DMA tag\n"); 2240 goto jumbo_fail; 2241 } 2242 2243 rxalign = 1; 2244 /* 2245 * Workaround hardware hang which seems to happen when Rx buffer 2246 * is not aligned on multiple of FIFO word(8 bytes). 2247 */ 2248 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) != 0) 2249 rxalign = MSK_RX_BUF_ALIGN; 2250 /* Create tag for jumbo Rx buffers. */ 2251 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2252 rxalign, 0, /* alignment, boundary */ 2253 BUS_SPACE_MAXADDR, /* lowaddr */ 2254 BUS_SPACE_MAXADDR, /* highaddr */ 2255 NULL, NULL, /* filter, filterarg */ 2256 MJUM9BYTES, /* maxsize */ 2257 1, /* nsegments */ 2258 MJUM9BYTES, /* maxsegsize */ 2259 0, /* flags */ 2260 NULL, NULL, /* lockfunc, lockarg */ 2261 &sc_if->msk_cdata.msk_jumbo_rx_tag); 2262 if (error != 0) { 2263 device_printf(sc_if->msk_if_dev, 2264 "failed to create jumbo Rx DMA tag\n"); 2265 goto jumbo_fail; 2266 } 2267 2268 /* Allocate DMA'able memory and load the DMA map for jumbo Rx ring. */ 2269 error = bus_dmamem_alloc(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 2270 (void **)&sc_if->msk_rdata.msk_jumbo_rx_ring, 2271 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 2272 &sc_if->msk_cdata.msk_jumbo_rx_ring_map); 2273 if (error != 0) { 2274 device_printf(sc_if->msk_if_dev, 2275 "failed to allocate DMA'able memory for jumbo Rx ring\n"); 2276 goto jumbo_fail; 2277 } 2278 2279 ctx.msk_busaddr = 0; 2280 error = bus_dmamap_load(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 2281 sc_if->msk_cdata.msk_jumbo_rx_ring_map, 2282 sc_if->msk_rdata.msk_jumbo_rx_ring, MSK_JUMBO_RX_RING_SZ, 2283 msk_dmamap_cb, &ctx, 0); 2284 if (error != 0) { 2285 device_printf(sc_if->msk_if_dev, 2286 "failed to load DMA'able memory for jumbo Rx ring\n"); 2287 goto jumbo_fail; 2288 } 2289 sc_if->msk_rdata.msk_jumbo_rx_ring_paddr = ctx.msk_busaddr; 2290 2291 /* Create DMA maps for jumbo Rx buffers. */ 2292 if ((error = bus_dmamap_create(sc_if->msk_cdata.msk_jumbo_rx_tag, 0, 2293 &sc_if->msk_cdata.msk_jumbo_rx_sparemap)) != 0) { 2294 device_printf(sc_if->msk_if_dev, 2295 "failed to create spare jumbo Rx dmamap\n"); 2296 goto jumbo_fail; 2297 } 2298 for (i = 0; i < MSK_JUMBO_RX_RING_CNT; i++) { 2299 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[i]; 2300 jrxd->rx_m = NULL; 2301 jrxd->rx_dmamap = NULL; 2302 error = bus_dmamap_create(sc_if->msk_cdata.msk_jumbo_rx_tag, 0, 2303 &jrxd->rx_dmamap); 2304 if (error != 0) { 2305 device_printf(sc_if->msk_if_dev, 2306 "failed to create jumbo Rx dmamap\n"); 2307 goto jumbo_fail; 2308 } 2309 } 2310 2311 return (0); 2312 2313 jumbo_fail: 2314 msk_rx_dma_jfree(sc_if); 2315 device_printf(sc_if->msk_if_dev, "disabling jumbo frame support " 2316 "due to resource shortage\n"); 2317 sc_if->msk_flags &= ~MSK_FLAG_JUMBO; 2318 return (error); 2319 } 2320 2321 static void 2322 msk_txrx_dma_free(struct msk_if_softc *sc_if) 2323 { 2324 struct msk_txdesc *txd; 2325 struct msk_rxdesc *rxd; 2326 int i; 2327 2328 /* Tx ring. */ 2329 if (sc_if->msk_cdata.msk_tx_ring_tag) { 2330 if (sc_if->msk_cdata.msk_tx_ring_map) 2331 bus_dmamap_unload(sc_if->msk_cdata.msk_tx_ring_tag, 2332 sc_if->msk_cdata.msk_tx_ring_map); 2333 if (sc_if->msk_cdata.msk_tx_ring_map && 2334 sc_if->msk_rdata.msk_tx_ring) 2335 bus_dmamem_free(sc_if->msk_cdata.msk_tx_ring_tag, 2336 sc_if->msk_rdata.msk_tx_ring, 2337 sc_if->msk_cdata.msk_tx_ring_map); 2338 sc_if->msk_rdata.msk_tx_ring = NULL; 2339 sc_if->msk_cdata.msk_tx_ring_map = NULL; 2340 bus_dma_tag_destroy(sc_if->msk_cdata.msk_tx_ring_tag); 2341 sc_if->msk_cdata.msk_tx_ring_tag = NULL; 2342 } 2343 /* Rx ring. */ 2344 if (sc_if->msk_cdata.msk_rx_ring_tag) { 2345 if (sc_if->msk_cdata.msk_rx_ring_map) 2346 bus_dmamap_unload(sc_if->msk_cdata.msk_rx_ring_tag, 2347 sc_if->msk_cdata.msk_rx_ring_map); 2348 if (sc_if->msk_cdata.msk_rx_ring_map && 2349 sc_if->msk_rdata.msk_rx_ring) 2350 bus_dmamem_free(sc_if->msk_cdata.msk_rx_ring_tag, 2351 sc_if->msk_rdata.msk_rx_ring, 2352 sc_if->msk_cdata.msk_rx_ring_map); 2353 sc_if->msk_rdata.msk_rx_ring = NULL; 2354 sc_if->msk_cdata.msk_rx_ring_map = NULL; 2355 bus_dma_tag_destroy(sc_if->msk_cdata.msk_rx_ring_tag); 2356 sc_if->msk_cdata.msk_rx_ring_tag = NULL; 2357 } 2358 /* Tx buffers. */ 2359 if (sc_if->msk_cdata.msk_tx_tag) { 2360 for (i = 0; i < MSK_TX_RING_CNT; i++) { 2361 txd = &sc_if->msk_cdata.msk_txdesc[i]; 2362 if (txd->tx_dmamap) { 2363 bus_dmamap_destroy(sc_if->msk_cdata.msk_tx_tag, 2364 txd->tx_dmamap); 2365 txd->tx_dmamap = NULL; 2366 } 2367 } 2368 bus_dma_tag_destroy(sc_if->msk_cdata.msk_tx_tag); 2369 sc_if->msk_cdata.msk_tx_tag = NULL; 2370 } 2371 /* Rx buffers. */ 2372 if (sc_if->msk_cdata.msk_rx_tag) { 2373 for (i = 0; i < MSK_RX_RING_CNT; i++) { 2374 rxd = &sc_if->msk_cdata.msk_rxdesc[i]; 2375 if (rxd->rx_dmamap) { 2376 bus_dmamap_destroy(sc_if->msk_cdata.msk_rx_tag, 2377 rxd->rx_dmamap); 2378 rxd->rx_dmamap = NULL; 2379 } 2380 } 2381 if (sc_if->msk_cdata.msk_rx_sparemap) { 2382 bus_dmamap_destroy(sc_if->msk_cdata.msk_rx_tag, 2383 sc_if->msk_cdata.msk_rx_sparemap); 2384 sc_if->msk_cdata.msk_rx_sparemap = 0; 2385 } 2386 bus_dma_tag_destroy(sc_if->msk_cdata.msk_rx_tag); 2387 sc_if->msk_cdata.msk_rx_tag = NULL; 2388 } 2389 if (sc_if->msk_cdata.msk_parent_tag) { 2390 bus_dma_tag_destroy(sc_if->msk_cdata.msk_parent_tag); 2391 sc_if->msk_cdata.msk_parent_tag = NULL; 2392 } 2393 } 2394 2395 static void 2396 msk_rx_dma_jfree(struct msk_if_softc *sc_if) 2397 { 2398 struct msk_rxdesc *jrxd; 2399 int i; 2400 2401 /* Jumbo Rx ring. */ 2402 if (sc_if->msk_cdata.msk_jumbo_rx_ring_tag) { 2403 if (sc_if->msk_cdata.msk_jumbo_rx_ring_map) 2404 bus_dmamap_unload(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 2405 sc_if->msk_cdata.msk_jumbo_rx_ring_map); 2406 if (sc_if->msk_cdata.msk_jumbo_rx_ring_map && 2407 sc_if->msk_rdata.msk_jumbo_rx_ring) 2408 bus_dmamem_free(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 2409 sc_if->msk_rdata.msk_jumbo_rx_ring, 2410 sc_if->msk_cdata.msk_jumbo_rx_ring_map); 2411 sc_if->msk_rdata.msk_jumbo_rx_ring = NULL; 2412 sc_if->msk_cdata.msk_jumbo_rx_ring_map = NULL; 2413 bus_dma_tag_destroy(sc_if->msk_cdata.msk_jumbo_rx_ring_tag); 2414 sc_if->msk_cdata.msk_jumbo_rx_ring_tag = NULL; 2415 } 2416 /* Jumbo Rx buffers. */ 2417 if (sc_if->msk_cdata.msk_jumbo_rx_tag) { 2418 for (i = 0; i < MSK_JUMBO_RX_RING_CNT; i++) { 2419 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[i]; 2420 if (jrxd->rx_dmamap) { 2421 bus_dmamap_destroy( 2422 sc_if->msk_cdata.msk_jumbo_rx_tag, 2423 jrxd->rx_dmamap); 2424 jrxd->rx_dmamap = NULL; 2425 } 2426 } 2427 if (sc_if->msk_cdata.msk_jumbo_rx_sparemap) { 2428 bus_dmamap_destroy(sc_if->msk_cdata.msk_jumbo_rx_tag, 2429 sc_if->msk_cdata.msk_jumbo_rx_sparemap); 2430 sc_if->msk_cdata.msk_jumbo_rx_sparemap = 0; 2431 } 2432 bus_dma_tag_destroy(sc_if->msk_cdata.msk_jumbo_rx_tag); 2433 sc_if->msk_cdata.msk_jumbo_rx_tag = NULL; 2434 } 2435 } 2436 2437 static int 2438 msk_encap(struct msk_if_softc *sc_if, struct mbuf **m_head) 2439 { 2440 struct msk_txdesc *txd, *txd_last; 2441 struct msk_tx_desc *tx_le; 2442 struct mbuf *m; 2443 bus_dmamap_t map; 2444 bus_dma_segment_t txsegs[MSK_MAXTXSEGS]; 2445 uint32_t control, prod, si; 2446 uint16_t offset, tcp_offset, tso_mtu; 2447 int error, i, nseg, tso; 2448 2449 MSK_IF_LOCK_ASSERT(sc_if); 2450 2451 tcp_offset = offset = 0; 2452 m = *m_head; 2453 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0 && 2454 (m->m_pkthdr.csum_flags & (MSK_CSUM_FEATURES | CSUM_TSO)) != 0) { 2455 /* 2456 * Since mbuf has no protocol specific structure information 2457 * in it we have to inspect protocol information here to 2458 * setup TSO and checksum offload. I don't know why Marvell 2459 * made a such decision in chip design because other GigE 2460 * hardwares normally takes care of all these chores in 2461 * hardware. However, TSO performance of Yukon II is very 2462 * good such that it's worth to implement it. 2463 */ 2464 struct ether_header *eh; 2465 struct ip *ip; 2466 struct tcphdr *tcp; 2467 2468 if (M_WRITABLE(m) == 0) { 2469 /* Get a writable copy. */ 2470 m = m_dup(*m_head, M_DONTWAIT); 2471 m_freem(*m_head); 2472 if (m == NULL) { 2473 *m_head = NULL; 2474 return (ENOBUFS); 2475 } 2476 *m_head = m; 2477 } 2478 2479 offset = sizeof(struct ether_header); 2480 m = m_pullup(m, offset); 2481 if (m == NULL) { 2482 *m_head = NULL; 2483 return (ENOBUFS); 2484 } 2485 eh = mtod(m, struct ether_header *); 2486 /* Check if hardware VLAN insertion is off. */ 2487 if (eh->ether_type == htons(ETHERTYPE_VLAN)) { 2488 offset = sizeof(struct ether_vlan_header); 2489 m = m_pullup(m, offset); 2490 if (m == NULL) { 2491 *m_head = NULL; 2492 return (ENOBUFS); 2493 } 2494 } 2495 m = m_pullup(m, offset + sizeof(struct ip)); 2496 if (m == NULL) { 2497 *m_head = NULL; 2498 return (ENOBUFS); 2499 } 2500 ip = (struct ip *)(mtod(m, char *) + offset); 2501 offset += (ip->ip_hl << 2); 2502 tcp_offset = offset; 2503 /* 2504 * It seems that Yukon II has Tx checksum offload bug for 2505 * small TCP packets that's less than 60 bytes in size 2506 * (e.g. TCP window probe packet, pure ACK packet). 2507 * Common work around like padding with zeros to make the 2508 * frame minimum ethernet frame size didn't work at all. 2509 * Instead of disabling checksum offload completely we 2510 * resort to S/W checksum routine when we encounter short 2511 * TCP frames. 2512 * Short UDP packets appear to be handled correctly by 2513 * Yukon II. 2514 */ 2515 if (m->m_pkthdr.len < MSK_MIN_FRAMELEN && 2516 (m->m_pkthdr.csum_flags & CSUM_TCP) != 0) { 2517 m = m_pullup(m, offset + sizeof(struct tcphdr)); 2518 if (m == NULL) { 2519 *m_head = NULL; 2520 return (ENOBUFS); 2521 } 2522 *(uint16_t *)(m->m_data + offset + 2523 m->m_pkthdr.csum_data) = in_cksum_skip(m, 2524 m->m_pkthdr.len, offset); 2525 m->m_pkthdr.csum_flags &= ~CSUM_TCP; 2526 } 2527 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 2528 m = m_pullup(m, offset + sizeof(struct tcphdr)); 2529 if (m == NULL) { 2530 *m_head = NULL; 2531 return (ENOBUFS); 2532 } 2533 tcp = (struct tcphdr *)(mtod(m, char *) + offset); 2534 offset += (tcp->th_off << 2); 2535 } 2536 *m_head = m; 2537 } 2538 2539 prod = sc_if->msk_cdata.msk_tx_prod; 2540 txd = &sc_if->msk_cdata.msk_txdesc[prod]; 2541 txd_last = txd; 2542 map = txd->tx_dmamap; 2543 error = bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_tx_tag, map, 2544 *m_head, txsegs, &nseg, BUS_DMA_NOWAIT); 2545 if (error == EFBIG) { 2546 m = m_collapse(*m_head, M_DONTWAIT, MSK_MAXTXSEGS); 2547 if (m == NULL) { 2548 m_freem(*m_head); 2549 *m_head = NULL; 2550 return (ENOBUFS); 2551 } 2552 *m_head = m; 2553 error = bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_tx_tag, 2554 map, *m_head, txsegs, &nseg, BUS_DMA_NOWAIT); 2555 if (error != 0) { 2556 m_freem(*m_head); 2557 *m_head = NULL; 2558 return (error); 2559 } 2560 } else if (error != 0) 2561 return (error); 2562 if (nseg == 0) { 2563 m_freem(*m_head); 2564 *m_head = NULL; 2565 return (EIO); 2566 } 2567 2568 /* Check number of available descriptors. */ 2569 if (sc_if->msk_cdata.msk_tx_cnt + nseg >= 2570 (MSK_TX_RING_CNT - MSK_RESERVED_TX_DESC_CNT)) { 2571 bus_dmamap_unload(sc_if->msk_cdata.msk_tx_tag, map); 2572 return (ENOBUFS); 2573 } 2574 2575 control = 0; 2576 tso = 0; 2577 tx_le = NULL; 2578 2579 /* Check TSO support. */ 2580 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 2581 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) != 0) 2582 tso_mtu = m->m_pkthdr.tso_segsz; 2583 else 2584 tso_mtu = offset + m->m_pkthdr.tso_segsz; 2585 if (tso_mtu != sc_if->msk_cdata.msk_tso_mtu) { 2586 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2587 tx_le->msk_addr = htole32(tso_mtu); 2588 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) != 0) 2589 tx_le->msk_control = htole32(OP_MSS | HW_OWNER); 2590 else 2591 tx_le->msk_control = 2592 htole32(OP_LRGLEN | HW_OWNER); 2593 sc_if->msk_cdata.msk_tx_cnt++; 2594 MSK_INC(prod, MSK_TX_RING_CNT); 2595 sc_if->msk_cdata.msk_tso_mtu = tso_mtu; 2596 } 2597 tso++; 2598 } 2599 /* Check if we have a VLAN tag to insert. */ 2600 if ((m->m_flags & M_VLANTAG) != 0) { 2601 if (tso == 0) { 2602 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2603 tx_le->msk_addr = htole32(0); 2604 tx_le->msk_control = htole32(OP_VLAN | HW_OWNER | 2605 htons(m->m_pkthdr.ether_vtag)); 2606 sc_if->msk_cdata.msk_tx_cnt++; 2607 MSK_INC(prod, MSK_TX_RING_CNT); 2608 } else { 2609 tx_le->msk_control |= htole32(OP_VLAN | 2610 htons(m->m_pkthdr.ether_vtag)); 2611 } 2612 control |= INS_VLAN; 2613 } 2614 /* Check if we have to handle checksum offload. */ 2615 if (tso == 0 && (m->m_pkthdr.csum_flags & MSK_CSUM_FEATURES) != 0) { 2616 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) != 0) 2617 control |= CALSUM; 2618 else { 2619 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2620 tx_le->msk_addr = htole32(((tcp_offset + 2621 m->m_pkthdr.csum_data) & 0xffff) | 2622 ((uint32_t)tcp_offset << 16)); 2623 tx_le->msk_control = htole32(1 << 16 | 2624 (OP_TCPLISW | HW_OWNER)); 2625 control = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM; 2626 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0) 2627 control |= UDPTCP; 2628 sc_if->msk_cdata.msk_tx_cnt++; 2629 MSK_INC(prod, MSK_TX_RING_CNT); 2630 } 2631 } 2632 2633 si = prod; 2634 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2635 tx_le->msk_addr = htole32(MSK_ADDR_LO(txsegs[0].ds_addr)); 2636 if (tso == 0) 2637 tx_le->msk_control = htole32(txsegs[0].ds_len | control | 2638 OP_PACKET); 2639 else 2640 tx_le->msk_control = htole32(txsegs[0].ds_len | control | 2641 OP_LARGESEND); 2642 sc_if->msk_cdata.msk_tx_cnt++; 2643 MSK_INC(prod, MSK_TX_RING_CNT); 2644 2645 for (i = 1; i < nseg; i++) { 2646 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2647 tx_le->msk_addr = htole32(MSK_ADDR_LO(txsegs[i].ds_addr)); 2648 tx_le->msk_control = htole32(txsegs[i].ds_len | control | 2649 OP_BUFFER | HW_OWNER); 2650 sc_if->msk_cdata.msk_tx_cnt++; 2651 MSK_INC(prod, MSK_TX_RING_CNT); 2652 } 2653 /* Update producer index. */ 2654 sc_if->msk_cdata.msk_tx_prod = prod; 2655 2656 /* Set EOP on the last desciptor. */ 2657 prod = (prod + MSK_TX_RING_CNT - 1) % MSK_TX_RING_CNT; 2658 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2659 tx_le->msk_control |= htole32(EOP); 2660 2661 /* Turn the first descriptor ownership to hardware. */ 2662 tx_le = &sc_if->msk_rdata.msk_tx_ring[si]; 2663 tx_le->msk_control |= htole32(HW_OWNER); 2664 2665 txd = &sc_if->msk_cdata.msk_txdesc[prod]; 2666 map = txd_last->tx_dmamap; 2667 txd_last->tx_dmamap = txd->tx_dmamap; 2668 txd->tx_dmamap = map; 2669 txd->tx_m = m; 2670 2671 /* Sync descriptors. */ 2672 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_tag, map, BUS_DMASYNC_PREWRITE); 2673 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_ring_tag, 2674 sc_if->msk_cdata.msk_tx_ring_map, 2675 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2676 2677 return (0); 2678 } 2679 2680 static void 2681 msk_tx_task(void *arg, int pending) 2682 { 2683 struct ifnet *ifp; 2684 2685 ifp = arg; 2686 msk_start(ifp); 2687 } 2688 2689 static void 2690 msk_start(struct ifnet *ifp) 2691 { 2692 struct msk_if_softc *sc_if; 2693 struct mbuf *m_head; 2694 int enq; 2695 2696 sc_if = ifp->if_softc; 2697 2698 MSK_IF_LOCK(sc_if); 2699 2700 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2701 IFF_DRV_RUNNING || (sc_if->msk_flags & MSK_FLAG_LINK) == 0) { 2702 MSK_IF_UNLOCK(sc_if); 2703 return; 2704 } 2705 2706 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 2707 sc_if->msk_cdata.msk_tx_cnt < 2708 (MSK_TX_RING_CNT - MSK_RESERVED_TX_DESC_CNT); ) { 2709 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2710 if (m_head == NULL) 2711 break; 2712 /* 2713 * Pack the data into the transmit ring. If we 2714 * don't have room, set the OACTIVE flag and wait 2715 * for the NIC to drain the ring. 2716 */ 2717 if (msk_encap(sc_if, &m_head) != 0) { 2718 if (m_head == NULL) 2719 break; 2720 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2721 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2722 break; 2723 } 2724 2725 enq++; 2726 /* 2727 * If there's a BPF listener, bounce a copy of this frame 2728 * to him. 2729 */ 2730 ETHER_BPF_MTAP(ifp, m_head); 2731 } 2732 2733 if (enq > 0) { 2734 /* Transmit */ 2735 CSR_WRITE_2(sc_if->msk_softc, 2736 Y2_PREF_Q_ADDR(sc_if->msk_txq, PREF_UNIT_PUT_IDX_REG), 2737 sc_if->msk_cdata.msk_tx_prod); 2738 2739 /* Set a timeout in case the chip goes out to lunch. */ 2740 sc_if->msk_watchdog_timer = MSK_TX_TIMEOUT; 2741 } 2742 2743 MSK_IF_UNLOCK(sc_if); 2744 } 2745 2746 static void 2747 msk_watchdog(struct msk_if_softc *sc_if) 2748 { 2749 struct ifnet *ifp; 2750 uint32_t ridx; 2751 int idx; 2752 2753 MSK_IF_LOCK_ASSERT(sc_if); 2754 2755 if (sc_if->msk_watchdog_timer == 0 || --sc_if->msk_watchdog_timer) 2756 return; 2757 ifp = sc_if->msk_ifp; 2758 if ((sc_if->msk_flags & MSK_FLAG_LINK) == 0) { 2759 if (bootverbose) 2760 if_printf(sc_if->msk_ifp, "watchdog timeout " 2761 "(missed link)\n"); 2762 ifp->if_oerrors++; 2763 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2764 msk_init_locked(sc_if); 2765 return; 2766 } 2767 2768 /* 2769 * Reclaim first as there is a possibility of losing Tx completion 2770 * interrupts. 2771 */ 2772 ridx = sc_if->msk_port == MSK_PORT_A ? STAT_TXA1_RIDX : STAT_TXA2_RIDX; 2773 idx = CSR_READ_2(sc_if->msk_softc, ridx); 2774 if (sc_if->msk_cdata.msk_tx_cons != idx) { 2775 msk_txeof(sc_if, idx); 2776 if (sc_if->msk_cdata.msk_tx_cnt == 0) { 2777 if_printf(ifp, "watchdog timeout (missed Tx interrupts) " 2778 "-- recovering\n"); 2779 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2780 taskqueue_enqueue(taskqueue_fast, 2781 &sc_if->msk_tx_task); 2782 return; 2783 } 2784 } 2785 2786 if_printf(ifp, "watchdog timeout\n"); 2787 ifp->if_oerrors++; 2788 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2789 msk_init_locked(sc_if); 2790 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2791 taskqueue_enqueue(taskqueue_fast, &sc_if->msk_tx_task); 2792 } 2793 2794 static int 2795 mskc_shutdown(device_t dev) 2796 { 2797 struct msk_softc *sc; 2798 int i; 2799 2800 sc = device_get_softc(dev); 2801 MSK_LOCK(sc); 2802 for (i = 0; i < sc->msk_num_port; i++) { 2803 if (sc->msk_if[i] != NULL) 2804 msk_stop(sc->msk_if[i]); 2805 } 2806 2807 /* Disable all interrupts. */ 2808 CSR_WRITE_4(sc, B0_IMSK, 0); 2809 CSR_READ_4(sc, B0_IMSK); 2810 CSR_WRITE_4(sc, B0_HWE_IMSK, 0); 2811 CSR_READ_4(sc, B0_HWE_IMSK); 2812 2813 /* Put hardware reset. */ 2814 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); 2815 2816 MSK_UNLOCK(sc); 2817 return (0); 2818 } 2819 2820 static int 2821 mskc_suspend(device_t dev) 2822 { 2823 struct msk_softc *sc; 2824 int i; 2825 2826 sc = device_get_softc(dev); 2827 2828 MSK_LOCK(sc); 2829 2830 for (i = 0; i < sc->msk_num_port; i++) { 2831 if (sc->msk_if[i] != NULL && sc->msk_if[i]->msk_ifp != NULL && 2832 ((sc->msk_if[i]->msk_ifp->if_drv_flags & 2833 IFF_DRV_RUNNING) != 0)) 2834 msk_stop(sc->msk_if[i]); 2835 } 2836 2837 /* Disable all interrupts. */ 2838 CSR_WRITE_4(sc, B0_IMSK, 0); 2839 CSR_READ_4(sc, B0_IMSK); 2840 CSR_WRITE_4(sc, B0_HWE_IMSK, 0); 2841 CSR_READ_4(sc, B0_HWE_IMSK); 2842 2843 msk_phy_power(sc, MSK_PHY_POWERDOWN); 2844 2845 /* Put hardware reset. */ 2846 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); 2847 sc->msk_pflags |= MSK_FLAG_SUSPEND; 2848 2849 MSK_UNLOCK(sc); 2850 2851 return (0); 2852 } 2853 2854 static int 2855 mskc_resume(device_t dev) 2856 { 2857 struct msk_softc *sc; 2858 int i; 2859 2860 sc = device_get_softc(dev); 2861 2862 MSK_LOCK(sc); 2863 2864 mskc_reset(sc); 2865 for (i = 0; i < sc->msk_num_port; i++) { 2866 if (sc->msk_if[i] != NULL && sc->msk_if[i]->msk_ifp != NULL && 2867 ((sc->msk_if[i]->msk_ifp->if_flags & IFF_UP) != 0)) { 2868 sc->msk_if[i]->msk_ifp->if_drv_flags &= 2869 ~IFF_DRV_RUNNING; 2870 msk_init_locked(sc->msk_if[i]); 2871 } 2872 } 2873 sc->msk_pflags &= ~MSK_FLAG_SUSPEND; 2874 2875 MSK_UNLOCK(sc); 2876 2877 return (0); 2878 } 2879 2880 #ifndef __NO_STRICT_ALIGNMENT 2881 static __inline void 2882 msk_fixup_rx(struct mbuf *m) 2883 { 2884 int i; 2885 uint16_t *src, *dst; 2886 2887 src = mtod(m, uint16_t *); 2888 dst = src - 3; 2889 2890 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 2891 *dst++ = *src++; 2892 2893 m->m_data -= (MSK_RX_BUF_ALIGN - ETHER_ALIGN); 2894 } 2895 #endif 2896 2897 static void 2898 msk_rxeof(struct msk_if_softc *sc_if, uint32_t status, int len) 2899 { 2900 struct mbuf *m; 2901 struct ifnet *ifp; 2902 struct msk_rxdesc *rxd; 2903 int cons, rxlen; 2904 2905 ifp = sc_if->msk_ifp; 2906 2907 MSK_IF_LOCK_ASSERT(sc_if); 2908 2909 cons = sc_if->msk_cdata.msk_rx_cons; 2910 do { 2911 rxlen = status >> 16; 2912 if ((status & GMR_FS_VLAN) != 0 && 2913 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 2914 rxlen -= ETHER_VLAN_ENCAP_LEN; 2915 if ((sc_if->msk_flags & MSK_FLAG_NORXCHK) != 0) { 2916 /* 2917 * For controllers that returns bogus status code 2918 * just do minimal check and let upper stack 2919 * handle this frame. 2920 */ 2921 if (len > MSK_MAX_FRAMELEN || len < ETHER_HDR_LEN) { 2922 ifp->if_ierrors++; 2923 msk_discard_rxbuf(sc_if, cons); 2924 break; 2925 } 2926 } else if (len > sc_if->msk_framesize || 2927 ((status & GMR_FS_ANY_ERR) != 0) || 2928 ((status & GMR_FS_RX_OK) == 0) || (rxlen != len)) { 2929 /* Don't count flow-control packet as errors. */ 2930 if ((status & GMR_FS_GOOD_FC) == 0) 2931 ifp->if_ierrors++; 2932 msk_discard_rxbuf(sc_if, cons); 2933 break; 2934 } 2935 rxd = &sc_if->msk_cdata.msk_rxdesc[cons]; 2936 m = rxd->rx_m; 2937 if (msk_newbuf(sc_if, cons) != 0) { 2938 ifp->if_iqdrops++; 2939 /* Reuse old buffer. */ 2940 msk_discard_rxbuf(sc_if, cons); 2941 break; 2942 } 2943 m->m_pkthdr.rcvif = ifp; 2944 m->m_pkthdr.len = m->m_len = len; 2945 #ifndef __NO_STRICT_ALIGNMENT 2946 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) != 0) 2947 msk_fixup_rx(m); 2948 #endif 2949 ifp->if_ipackets++; 2950 /* Check for VLAN tagged packets. */ 2951 if ((status & GMR_FS_VLAN) != 0 && 2952 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) { 2953 m->m_pkthdr.ether_vtag = sc_if->msk_vtag; 2954 m->m_flags |= M_VLANTAG; 2955 } 2956 MSK_IF_UNLOCK(sc_if); 2957 (*ifp->if_input)(ifp, m); 2958 MSK_IF_LOCK(sc_if); 2959 } while (0); 2960 2961 MSK_INC(sc_if->msk_cdata.msk_rx_cons, MSK_RX_RING_CNT); 2962 MSK_INC(sc_if->msk_cdata.msk_rx_prod, MSK_RX_RING_CNT); 2963 } 2964 2965 static void 2966 msk_jumbo_rxeof(struct msk_if_softc *sc_if, uint32_t status, int len) 2967 { 2968 struct mbuf *m; 2969 struct ifnet *ifp; 2970 struct msk_rxdesc *jrxd; 2971 int cons, rxlen; 2972 2973 ifp = sc_if->msk_ifp; 2974 2975 MSK_IF_LOCK_ASSERT(sc_if); 2976 2977 cons = sc_if->msk_cdata.msk_rx_cons; 2978 do { 2979 rxlen = status >> 16; 2980 if ((status & GMR_FS_VLAN) != 0 && 2981 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 2982 rxlen -= ETHER_VLAN_ENCAP_LEN; 2983 if (len > sc_if->msk_framesize || 2984 ((status & GMR_FS_ANY_ERR) != 0) || 2985 ((status & GMR_FS_RX_OK) == 0) || (rxlen != len)) { 2986 /* Don't count flow-control packet as errors. */ 2987 if ((status & GMR_FS_GOOD_FC) == 0) 2988 ifp->if_ierrors++; 2989 msk_discard_jumbo_rxbuf(sc_if, cons); 2990 break; 2991 } 2992 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[cons]; 2993 m = jrxd->rx_m; 2994 if (msk_jumbo_newbuf(sc_if, cons) != 0) { 2995 ifp->if_iqdrops++; 2996 /* Reuse old buffer. */ 2997 msk_discard_jumbo_rxbuf(sc_if, cons); 2998 break; 2999 } 3000 m->m_pkthdr.rcvif = ifp; 3001 m->m_pkthdr.len = m->m_len = len; 3002 #ifndef __NO_STRICT_ALIGNMENT 3003 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) != 0) 3004 msk_fixup_rx(m); 3005 #endif 3006 ifp->if_ipackets++; 3007 /* Check for VLAN tagged packets. */ 3008 if ((status & GMR_FS_VLAN) != 0 && 3009 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) { 3010 m->m_pkthdr.ether_vtag = sc_if->msk_vtag; 3011 m->m_flags |= M_VLANTAG; 3012 } 3013 MSK_IF_UNLOCK(sc_if); 3014 (*ifp->if_input)(ifp, m); 3015 MSK_IF_LOCK(sc_if); 3016 } while (0); 3017 3018 MSK_INC(sc_if->msk_cdata.msk_rx_cons, MSK_JUMBO_RX_RING_CNT); 3019 MSK_INC(sc_if->msk_cdata.msk_rx_prod, MSK_JUMBO_RX_RING_CNT); 3020 } 3021 3022 static void 3023 msk_txeof(struct msk_if_softc *sc_if, int idx) 3024 { 3025 struct msk_txdesc *txd; 3026 struct msk_tx_desc *cur_tx; 3027 struct ifnet *ifp; 3028 uint32_t control; 3029 int cons, prog; 3030 3031 MSK_IF_LOCK_ASSERT(sc_if); 3032 3033 ifp = sc_if->msk_ifp; 3034 3035 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_ring_tag, 3036 sc_if->msk_cdata.msk_tx_ring_map, 3037 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3038 /* 3039 * Go through our tx ring and free mbufs for those 3040 * frames that have been sent. 3041 */ 3042 cons = sc_if->msk_cdata.msk_tx_cons; 3043 prog = 0; 3044 for (; cons != idx; MSK_INC(cons, MSK_TX_RING_CNT)) { 3045 if (sc_if->msk_cdata.msk_tx_cnt <= 0) 3046 break; 3047 prog++; 3048 cur_tx = &sc_if->msk_rdata.msk_tx_ring[cons]; 3049 control = le32toh(cur_tx->msk_control); 3050 sc_if->msk_cdata.msk_tx_cnt--; 3051 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3052 if ((control & EOP) == 0) 3053 continue; 3054 txd = &sc_if->msk_cdata.msk_txdesc[cons]; 3055 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_tag, txd->tx_dmamap, 3056 BUS_DMASYNC_POSTWRITE); 3057 bus_dmamap_unload(sc_if->msk_cdata.msk_tx_tag, txd->tx_dmamap); 3058 3059 ifp->if_opackets++; 3060 KASSERT(txd->tx_m != NULL, ("%s: freeing NULL mbuf!", 3061 __func__)); 3062 m_freem(txd->tx_m); 3063 txd->tx_m = NULL; 3064 } 3065 3066 if (prog > 0) { 3067 sc_if->msk_cdata.msk_tx_cons = cons; 3068 if (sc_if->msk_cdata.msk_tx_cnt == 0) 3069 sc_if->msk_watchdog_timer = 0; 3070 /* No need to sync LEs as we didn't update LEs. */ 3071 } 3072 } 3073 3074 static void 3075 msk_tick(void *xsc_if) 3076 { 3077 struct msk_if_softc *sc_if; 3078 struct mii_data *mii; 3079 3080 sc_if = xsc_if; 3081 3082 MSK_IF_LOCK_ASSERT(sc_if); 3083 3084 mii = device_get_softc(sc_if->msk_miibus); 3085 3086 mii_tick(mii); 3087 msk_watchdog(sc_if); 3088 callout_reset(&sc_if->msk_tick_ch, hz, msk_tick, sc_if); 3089 } 3090 3091 static void 3092 msk_intr_phy(struct msk_if_softc *sc_if) 3093 { 3094 uint16_t status; 3095 3096 msk_phy_readreg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_STAT); 3097 status = msk_phy_readreg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_STAT); 3098 /* Handle FIFO Underrun/Overflow? */ 3099 if ((status & PHY_M_IS_FIFO_ERROR)) 3100 device_printf(sc_if->msk_if_dev, 3101 "PHY FIFO underrun/overflow.\n"); 3102 } 3103 3104 static void 3105 msk_intr_gmac(struct msk_if_softc *sc_if) 3106 { 3107 struct msk_softc *sc; 3108 uint8_t status; 3109 3110 sc = sc_if->msk_softc; 3111 status = CSR_READ_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_SRC)); 3112 3113 /* GMAC Rx FIFO overrun. */ 3114 if ((status & GM_IS_RX_FF_OR) != 0) { 3115 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), 3116 GMF_CLI_RX_FO); 3117 device_printf(sc_if->msk_if_dev, "Rx FIFO overrun!\n"); 3118 } 3119 /* GMAC Tx FIFO underrun. */ 3120 if ((status & GM_IS_TX_FF_UR) != 0) { 3121 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 3122 GMF_CLI_TX_FU); 3123 device_printf(sc_if->msk_if_dev, "Tx FIFO underrun!\n"); 3124 /* 3125 * XXX 3126 * In case of Tx underrun, we may need to flush/reset 3127 * Tx MAC but that would also require resynchronization 3128 * with status LEs. Reintializing status LEs would 3129 * affect other port in dual MAC configuration so it 3130 * should be avoided as possible as we can. 3131 * Due to lack of documentation it's all vague guess but 3132 * it needs more investigation. 3133 */ 3134 } 3135 } 3136 3137 static void 3138 msk_handle_hwerr(struct msk_if_softc *sc_if, uint32_t status) 3139 { 3140 struct msk_softc *sc; 3141 3142 sc = sc_if->msk_softc; 3143 if ((status & Y2_IS_PAR_RD1) != 0) { 3144 device_printf(sc_if->msk_if_dev, 3145 "RAM buffer read parity error\n"); 3146 /* Clear IRQ. */ 3147 CSR_WRITE_2(sc, SELECT_RAM_BUFFER(sc_if->msk_port, B3_RI_CTRL), 3148 RI_CLR_RD_PERR); 3149 } 3150 if ((status & Y2_IS_PAR_WR1) != 0) { 3151 device_printf(sc_if->msk_if_dev, 3152 "RAM buffer write parity error\n"); 3153 /* Clear IRQ. */ 3154 CSR_WRITE_2(sc, SELECT_RAM_BUFFER(sc_if->msk_port, B3_RI_CTRL), 3155 RI_CLR_WR_PERR); 3156 } 3157 if ((status & Y2_IS_PAR_MAC1) != 0) { 3158 device_printf(sc_if->msk_if_dev, "Tx MAC parity error\n"); 3159 /* Clear IRQ. */ 3160 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 3161 GMF_CLI_TX_PE); 3162 } 3163 if ((status & Y2_IS_PAR_RX1) != 0) { 3164 device_printf(sc_if->msk_if_dev, "Rx parity error\n"); 3165 /* Clear IRQ. */ 3166 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_CLR_IRQ_PAR); 3167 } 3168 if ((status & (Y2_IS_TCP_TXS1 | Y2_IS_TCP_TXA1)) != 0) { 3169 device_printf(sc_if->msk_if_dev, "TCP segmentation error\n"); 3170 /* Clear IRQ. */ 3171 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_CLR_IRQ_TCP); 3172 } 3173 } 3174 3175 static void 3176 msk_intr_hwerr(struct msk_softc *sc) 3177 { 3178 uint32_t status; 3179 uint32_t tlphead[4]; 3180 3181 status = CSR_READ_4(sc, B0_HWE_ISRC); 3182 /* Time Stamp timer overflow. */ 3183 if ((status & Y2_IS_TIST_OV) != 0) 3184 CSR_WRITE_1(sc, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ); 3185 if ((status & Y2_IS_PCI_NEXP) != 0) { 3186 /* 3187 * PCI Express Error occured which is not described in PEX 3188 * spec. 3189 * This error is also mapped either to Master Abort( 3190 * Y2_IS_MST_ERR) or Target Abort (Y2_IS_IRQ_STAT) bit and 3191 * can only be cleared there. 3192 */ 3193 device_printf(sc->msk_dev, 3194 "PCI Express protocol violation error\n"); 3195 } 3196 3197 if ((status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) != 0) { 3198 uint16_t v16; 3199 3200 if ((status & Y2_IS_MST_ERR) != 0) 3201 device_printf(sc->msk_dev, 3202 "unexpected IRQ Status error\n"); 3203 else 3204 device_printf(sc->msk_dev, 3205 "unexpected IRQ Master error\n"); 3206 /* Reset all bits in the PCI status register. */ 3207 v16 = pci_read_config(sc->msk_dev, PCIR_STATUS, 2); 3208 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON); 3209 pci_write_config(sc->msk_dev, PCIR_STATUS, v16 | 3210 PCIM_STATUS_PERR | PCIM_STATUS_SERR | PCIM_STATUS_RMABORT | 3211 PCIM_STATUS_RTABORT | PCIM_STATUS_PERRREPORT, 2); 3212 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 3213 } 3214 3215 /* Check for PCI Express Uncorrectable Error. */ 3216 if ((status & Y2_IS_PCI_EXP) != 0) { 3217 uint32_t v32; 3218 3219 /* 3220 * On PCI Express bus bridges are called root complexes (RC). 3221 * PCI Express errors are recognized by the root complex too, 3222 * which requests the system to handle the problem. After 3223 * error occurence it may be that no access to the adapter 3224 * may be performed any longer. 3225 */ 3226 3227 v32 = CSR_PCI_READ_4(sc, PEX_UNC_ERR_STAT); 3228 if ((v32 & PEX_UNSUP_REQ) != 0) { 3229 /* Ignore unsupported request error. */ 3230 device_printf(sc->msk_dev, 3231 "Uncorrectable PCI Express error\n"); 3232 } 3233 if ((v32 & (PEX_FATAL_ERRORS | PEX_POIS_TLP)) != 0) { 3234 int i; 3235 3236 /* Get TLP header form Log Registers. */ 3237 for (i = 0; i < 4; i++) 3238 tlphead[i] = CSR_PCI_READ_4(sc, 3239 PEX_HEADER_LOG + i * 4); 3240 /* Check for vendor defined broadcast message. */ 3241 if (!(tlphead[0] == 0x73004001 && tlphead[1] == 0x7f)) { 3242 sc->msk_intrhwemask &= ~Y2_IS_PCI_EXP; 3243 CSR_WRITE_4(sc, B0_HWE_IMSK, 3244 sc->msk_intrhwemask); 3245 CSR_READ_4(sc, B0_HWE_IMSK); 3246 } 3247 } 3248 /* Clear the interrupt. */ 3249 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON); 3250 CSR_PCI_WRITE_4(sc, PEX_UNC_ERR_STAT, 0xffffffff); 3251 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 3252 } 3253 3254 if ((status & Y2_HWE_L1_MASK) != 0 && sc->msk_if[MSK_PORT_A] != NULL) 3255 msk_handle_hwerr(sc->msk_if[MSK_PORT_A], status); 3256 if ((status & Y2_HWE_L2_MASK) != 0 && sc->msk_if[MSK_PORT_B] != NULL) 3257 msk_handle_hwerr(sc->msk_if[MSK_PORT_B], status >> 8); 3258 } 3259 3260 static __inline void 3261 msk_rxput(struct msk_if_softc *sc_if) 3262 { 3263 struct msk_softc *sc; 3264 3265 sc = sc_if->msk_softc; 3266 if (sc_if->msk_framesize > (MCLBYTES - MSK_RX_BUF_ALIGN)) 3267 bus_dmamap_sync( 3268 sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 3269 sc_if->msk_cdata.msk_jumbo_rx_ring_map, 3270 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3271 else 3272 bus_dmamap_sync( 3273 sc_if->msk_cdata.msk_rx_ring_tag, 3274 sc_if->msk_cdata.msk_rx_ring_map, 3275 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3276 CSR_WRITE_2(sc, Y2_PREF_Q_ADDR(sc_if->msk_rxq, 3277 PREF_UNIT_PUT_IDX_REG), sc_if->msk_cdata.msk_rx_prod); 3278 } 3279 3280 static int 3281 msk_handle_events(struct msk_softc *sc) 3282 { 3283 struct msk_if_softc *sc_if; 3284 int rxput[2]; 3285 struct msk_stat_desc *sd; 3286 uint32_t control, status; 3287 int cons, idx, len, port, rxprog; 3288 3289 idx = CSR_READ_2(sc, STAT_PUT_IDX); 3290 if (idx == sc->msk_stat_cons) 3291 return (0); 3292 3293 /* Sync status LEs. */ 3294 bus_dmamap_sync(sc->msk_stat_tag, sc->msk_stat_map, 3295 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3296 /* XXX Sync Rx LEs here. */ 3297 3298 rxput[MSK_PORT_A] = rxput[MSK_PORT_B] = 0; 3299 3300 rxprog = 0; 3301 for (cons = sc->msk_stat_cons; cons != idx;) { 3302 sd = &sc->msk_stat_ring[cons]; 3303 control = le32toh(sd->msk_control); 3304 if ((control & HW_OWNER) == 0) 3305 break; 3306 /* 3307 * Marvell's FreeBSD driver updates status LE after clearing 3308 * HW_OWNER. However we don't have a way to sync single LE 3309 * with bus_dma(9) API. bus_dma(9) provides a way to sync 3310 * an entire DMA map. So don't sync LE until we have a better 3311 * way to sync LEs. 3312 */ 3313 control &= ~HW_OWNER; 3314 sd->msk_control = htole32(control); 3315 status = le32toh(sd->msk_status); 3316 len = control & STLE_LEN_MASK; 3317 port = (control >> 16) & 0x01; 3318 sc_if = sc->msk_if[port]; 3319 if (sc_if == NULL) { 3320 device_printf(sc->msk_dev, "invalid port opcode " 3321 "0x%08x\n", control & STLE_OP_MASK); 3322 continue; 3323 } 3324 3325 switch (control & STLE_OP_MASK) { 3326 case OP_RXVLAN: 3327 sc_if->msk_vtag = ntohs(len); 3328 break; 3329 case OP_RXCHKSVLAN: 3330 sc_if->msk_vtag = ntohs(len); 3331 break; 3332 case OP_RXSTAT: 3333 if (sc_if->msk_framesize > 3334 (MCLBYTES - MSK_RX_BUF_ALIGN)) 3335 msk_jumbo_rxeof(sc_if, status, len); 3336 else 3337 msk_rxeof(sc_if, status, len); 3338 rxprog++; 3339 /* 3340 * Because there is no way to sync single Rx LE 3341 * put the DMA sync operation off until the end of 3342 * event processing. 3343 */ 3344 rxput[port]++; 3345 /* Update prefetch unit if we've passed water mark. */ 3346 if (rxput[port] >= sc_if->msk_cdata.msk_rx_putwm) { 3347 msk_rxput(sc_if); 3348 rxput[port] = 0; 3349 } 3350 break; 3351 case OP_TXINDEXLE: 3352 if (sc->msk_if[MSK_PORT_A] != NULL) 3353 msk_txeof(sc->msk_if[MSK_PORT_A], 3354 status & STLE_TXA1_MSKL); 3355 if (sc->msk_if[MSK_PORT_B] != NULL) 3356 msk_txeof(sc->msk_if[MSK_PORT_B], 3357 ((status & STLE_TXA2_MSKL) >> 3358 STLE_TXA2_SHIFTL) | 3359 ((len & STLE_TXA2_MSKH) << 3360 STLE_TXA2_SHIFTH)); 3361 break; 3362 default: 3363 device_printf(sc->msk_dev, "unhandled opcode 0x%08x\n", 3364 control & STLE_OP_MASK); 3365 break; 3366 } 3367 MSK_INC(cons, MSK_STAT_RING_CNT); 3368 if (rxprog > sc->msk_process_limit) 3369 break; 3370 } 3371 3372 sc->msk_stat_cons = cons; 3373 /* XXX We should sync status LEs here. See above notes. */ 3374 3375 if (rxput[MSK_PORT_A] > 0) 3376 msk_rxput(sc->msk_if[MSK_PORT_A]); 3377 if (rxput[MSK_PORT_B] > 0) 3378 msk_rxput(sc->msk_if[MSK_PORT_B]); 3379 3380 return (sc->msk_stat_cons != CSR_READ_2(sc, STAT_PUT_IDX)); 3381 } 3382 3383 /* Legacy interrupt handler for shared interrupt. */ 3384 static void 3385 msk_legacy_intr(void *xsc) 3386 { 3387 struct msk_softc *sc; 3388 struct msk_if_softc *sc_if0, *sc_if1; 3389 struct ifnet *ifp0, *ifp1; 3390 uint32_t status; 3391 3392 sc = xsc; 3393 MSK_LOCK(sc); 3394 3395 /* Reading B0_Y2_SP_ISRC2 masks further interrupts. */ 3396 status = CSR_READ_4(sc, B0_Y2_SP_ISRC2); 3397 if (status == 0 || status == 0xffffffff || 3398 (sc->msk_pflags & MSK_FLAG_SUSPEND) != 0 || 3399 (status & sc->msk_intrmask) == 0) { 3400 CSR_WRITE_4(sc, B0_Y2_SP_ICR, 2); 3401 return; 3402 } 3403 3404 sc_if0 = sc->msk_if[MSK_PORT_A]; 3405 sc_if1 = sc->msk_if[MSK_PORT_B]; 3406 ifp0 = ifp1 = NULL; 3407 if (sc_if0 != NULL) 3408 ifp0 = sc_if0->msk_ifp; 3409 if (sc_if1 != NULL) 3410 ifp1 = sc_if1->msk_ifp; 3411 3412 if ((status & Y2_IS_IRQ_PHY1) != 0 && sc_if0 != NULL) 3413 msk_intr_phy(sc_if0); 3414 if ((status & Y2_IS_IRQ_PHY2) != 0 && sc_if1 != NULL) 3415 msk_intr_phy(sc_if1); 3416 if ((status & Y2_IS_IRQ_MAC1) != 0 && sc_if0 != NULL) 3417 msk_intr_gmac(sc_if0); 3418 if ((status & Y2_IS_IRQ_MAC2) != 0 && sc_if1 != NULL) 3419 msk_intr_gmac(sc_if1); 3420 if ((status & (Y2_IS_CHK_RX1 | Y2_IS_CHK_RX2)) != 0) { 3421 device_printf(sc->msk_dev, "Rx descriptor error\n"); 3422 sc->msk_intrmask &= ~(Y2_IS_CHK_RX1 | Y2_IS_CHK_RX2); 3423 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask); 3424 CSR_READ_4(sc, B0_IMSK); 3425 } 3426 if ((status & (Y2_IS_CHK_TXA1 | Y2_IS_CHK_TXA2)) != 0) { 3427 device_printf(sc->msk_dev, "Tx descriptor error\n"); 3428 sc->msk_intrmask &= ~(Y2_IS_CHK_TXA1 | Y2_IS_CHK_TXA2); 3429 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask); 3430 CSR_READ_4(sc, B0_IMSK); 3431 } 3432 if ((status & Y2_IS_HW_ERR) != 0) 3433 msk_intr_hwerr(sc); 3434 3435 while (msk_handle_events(sc) != 0) 3436 ; 3437 if ((status & Y2_IS_STAT_BMU) != 0) 3438 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_CLR_IRQ); 3439 3440 /* Reenable interrupts. */ 3441 CSR_WRITE_4(sc, B0_Y2_SP_ICR, 2); 3442 3443 if (ifp0 != NULL && (ifp0->if_drv_flags & IFF_DRV_RUNNING) != 0 && 3444 !IFQ_DRV_IS_EMPTY(&ifp0->if_snd)) 3445 taskqueue_enqueue(taskqueue_fast, &sc_if0->msk_tx_task); 3446 if (ifp1 != NULL && (ifp1->if_drv_flags & IFF_DRV_RUNNING) != 0 && 3447 !IFQ_DRV_IS_EMPTY(&ifp1->if_snd)) 3448 taskqueue_enqueue(taskqueue_fast, &sc_if1->msk_tx_task); 3449 3450 MSK_UNLOCK(sc); 3451 } 3452 3453 static int 3454 msk_intr(void *xsc) 3455 { 3456 struct msk_softc *sc; 3457 uint32_t status; 3458 3459 sc = xsc; 3460 status = CSR_READ_4(sc, B0_Y2_SP_ISRC2); 3461 /* Reading B0_Y2_SP_ISRC2 masks further interrupts. */ 3462 if (status == 0 || status == 0xffffffff) { 3463 CSR_WRITE_4(sc, B0_Y2_SP_ICR, 2); 3464 return (FILTER_STRAY); 3465 } 3466 3467 taskqueue_enqueue(sc->msk_tq, &sc->msk_int_task); 3468 return (FILTER_HANDLED); 3469 } 3470 3471 static void 3472 msk_int_task(void *arg, int pending) 3473 { 3474 struct msk_softc *sc; 3475 struct msk_if_softc *sc_if0, *sc_if1; 3476 struct ifnet *ifp0, *ifp1; 3477 uint32_t status; 3478 int domore; 3479 3480 sc = arg; 3481 MSK_LOCK(sc); 3482 3483 /* Get interrupt source. */ 3484 status = CSR_READ_4(sc, B0_ISRC); 3485 if (status == 0 || status == 0xffffffff || 3486 (sc->msk_pflags & MSK_FLAG_SUSPEND) != 0 || 3487 (status & sc->msk_intrmask) == 0) 3488 goto done; 3489 3490 sc_if0 = sc->msk_if[MSK_PORT_A]; 3491 sc_if1 = sc->msk_if[MSK_PORT_B]; 3492 ifp0 = ifp1 = NULL; 3493 if (sc_if0 != NULL) 3494 ifp0 = sc_if0->msk_ifp; 3495 if (sc_if1 != NULL) 3496 ifp1 = sc_if1->msk_ifp; 3497 3498 if ((status & Y2_IS_IRQ_PHY1) != 0 && sc_if0 != NULL) 3499 msk_intr_phy(sc_if0); 3500 if ((status & Y2_IS_IRQ_PHY2) != 0 && sc_if1 != NULL) 3501 msk_intr_phy(sc_if1); 3502 if ((status & Y2_IS_IRQ_MAC1) != 0 && sc_if0 != NULL) 3503 msk_intr_gmac(sc_if0); 3504 if ((status & Y2_IS_IRQ_MAC2) != 0 && sc_if1 != NULL) 3505 msk_intr_gmac(sc_if1); 3506 if ((status & (Y2_IS_CHK_RX1 | Y2_IS_CHK_RX2)) != 0) { 3507 device_printf(sc->msk_dev, "Rx descriptor error\n"); 3508 sc->msk_intrmask &= ~(Y2_IS_CHK_RX1 | Y2_IS_CHK_RX2); 3509 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask); 3510 CSR_READ_4(sc, B0_IMSK); 3511 } 3512 if ((status & (Y2_IS_CHK_TXA1 | Y2_IS_CHK_TXA2)) != 0) { 3513 device_printf(sc->msk_dev, "Tx descriptor error\n"); 3514 sc->msk_intrmask &= ~(Y2_IS_CHK_TXA1 | Y2_IS_CHK_TXA2); 3515 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask); 3516 CSR_READ_4(sc, B0_IMSK); 3517 } 3518 if ((status & Y2_IS_HW_ERR) != 0) 3519 msk_intr_hwerr(sc); 3520 3521 domore = msk_handle_events(sc); 3522 if ((status & Y2_IS_STAT_BMU) != 0) 3523 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_CLR_IRQ); 3524 3525 if (ifp0 != NULL && (ifp0->if_drv_flags & IFF_DRV_RUNNING) != 0 && 3526 !IFQ_DRV_IS_EMPTY(&ifp0->if_snd)) 3527 taskqueue_enqueue(taskqueue_fast, &sc_if0->msk_tx_task); 3528 if (ifp1 != NULL && (ifp1->if_drv_flags & IFF_DRV_RUNNING) != 0 && 3529 !IFQ_DRV_IS_EMPTY(&ifp1->if_snd)) 3530 taskqueue_enqueue(taskqueue_fast, &sc_if1->msk_tx_task); 3531 3532 if (domore > 0) { 3533 taskqueue_enqueue(sc->msk_tq, &sc->msk_int_task); 3534 MSK_UNLOCK(sc); 3535 return; 3536 } 3537 done: 3538 MSK_UNLOCK(sc); 3539 3540 /* Reenable interrupts. */ 3541 CSR_WRITE_4(sc, B0_Y2_SP_ICR, 2); 3542 } 3543 3544 static void 3545 msk_init(void *xsc) 3546 { 3547 struct msk_if_softc *sc_if = xsc; 3548 3549 MSK_IF_LOCK(sc_if); 3550 msk_init_locked(sc_if); 3551 MSK_IF_UNLOCK(sc_if); 3552 } 3553 3554 static void 3555 msk_init_locked(struct msk_if_softc *sc_if) 3556 { 3557 struct msk_softc *sc; 3558 struct ifnet *ifp; 3559 struct mii_data *mii; 3560 uint16_t eaddr[ETHER_ADDR_LEN / 2]; 3561 uint16_t gmac; 3562 uint32_t reg; 3563 int error, i; 3564 3565 MSK_IF_LOCK_ASSERT(sc_if); 3566 3567 ifp = sc_if->msk_ifp; 3568 sc = sc_if->msk_softc; 3569 mii = device_get_softc(sc_if->msk_miibus); 3570 3571 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 3572 return; 3573 3574 error = 0; 3575 /* Cancel pending I/O and free all Rx/Tx buffers. */ 3576 msk_stop(sc_if); 3577 3578 if (ifp->if_mtu < ETHERMTU) 3579 sc_if->msk_framesize = ETHERMTU; 3580 else 3581 sc_if->msk_framesize = ifp->if_mtu; 3582 sc_if->msk_framesize += ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 3583 if (ifp->if_mtu > ETHERMTU && 3584 (sc_if->msk_flags & MSK_FLAG_JUMBO_NOCSUM) != 0) { 3585 ifp->if_hwassist &= ~(MSK_CSUM_FEATURES | CSUM_TSO); 3586 ifp->if_capenable &= ~(IFCAP_TSO4 | IFCAP_TXCSUM); 3587 } 3588 3589 /* GMAC Control reset. */ 3590 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_RST_SET); 3591 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_RST_CLR); 3592 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_F_LOOPB_OFF); 3593 3594 /* 3595 * Initialize GMAC first such that speed/duplex/flow-control 3596 * parameters are renegotiated when interface is brought up. 3597 */ 3598 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, 0); 3599 3600 /* Dummy read the Interrupt Source Register. */ 3601 CSR_READ_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_SRC)); 3602 3603 /* Clear MIB stats. */ 3604 msk_stats_clear(sc_if); 3605 3606 /* Disable FCS. */ 3607 GMAC_WRITE_2(sc, sc_if->msk_port, GM_RX_CTRL, GM_RXCR_CRC_DIS); 3608 3609 /* Setup Transmit Control Register. */ 3610 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF)); 3611 3612 /* Setup Transmit Flow Control Register. */ 3613 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_FLOW_CTRL, 0xffff); 3614 3615 /* Setup Transmit Parameter Register. */ 3616 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_PARAM, 3617 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) | TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) | 3618 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) | TX_BACK_OFF_LIM(TX_BOF_LIM_DEF)); 3619 3620 gmac = DATA_BLIND_VAL(DATA_BLIND_DEF) | 3621 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF); 3622 3623 if (ifp->if_mtu > ETHERMTU) 3624 gmac |= GM_SMOD_JUMBO_ENA; 3625 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SERIAL_MODE, gmac); 3626 3627 /* Set station address. */ 3628 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN); 3629 for (i = 0; i < ETHER_ADDR_LEN /2; i++) 3630 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_1L + i * 4, 3631 eaddr[i]); 3632 for (i = 0; i < ETHER_ADDR_LEN /2; i++) 3633 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_2L + i * 4, 3634 eaddr[i]); 3635 3636 /* Disable interrupts for counter overflows. */ 3637 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_IRQ_MSK, 0); 3638 GMAC_WRITE_2(sc, sc_if->msk_port, GM_RX_IRQ_MSK, 0); 3639 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TR_IRQ_MSK, 0); 3640 3641 /* Configure Rx MAC FIFO. */ 3642 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), GMF_RST_SET); 3643 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), GMF_RST_CLR); 3644 reg = GMF_OPER_ON | GMF_RX_F_FL_ON; 3645 if (sc->msk_hw_id == CHIP_ID_YUKON_FE_P) 3646 reg |= GMF_RX_OVER_ON; 3647 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), reg); 3648 3649 /* Set receive filter. */ 3650 msk_rxfilter(sc_if); 3651 3652 /* Flush Rx MAC FIFO on any flow control or error. */ 3653 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_FL_MSK), 3654 GMR_FS_ANY_ERR); 3655 3656 /* 3657 * Set Rx FIFO flush threshold to 64 bytes + 1 FIFO word 3658 * due to hardware hang on receipt of pause frames. 3659 */ 3660 reg = RX_GMF_FL_THR_DEF + 1; 3661 /* Another magic for Yukon FE+ - From Linux. */ 3662 if (sc->msk_hw_id == CHIP_ID_YUKON_FE_P && 3663 sc->msk_hw_rev == CHIP_REV_YU_FE_P_A0) 3664 reg = 0x178; 3665 CSR_WRITE_2(sc, MR_ADDR(sc_if->msk_port, RX_GMF_FL_THR), reg); 3666 3667 /* Configure Tx MAC FIFO. */ 3668 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_RST_SET); 3669 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_RST_CLR); 3670 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_OPER_ON); 3671 3672 /* Configure hardware VLAN tag insertion/stripping. */ 3673 msk_setvlan(sc_if, ifp); 3674 3675 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) == 0) { 3676 /* Set Rx Pause threshould. */ 3677 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, RX_GMF_LP_THR), 3678 MSK_ECU_LLPP); 3679 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, RX_GMF_UP_THR), 3680 MSK_ECU_ULPP); 3681 if (ifp->if_mtu > ETHERMTU) { 3682 /* 3683 * Set Tx GMAC FIFO Almost Empty Threshold. 3684 */ 3685 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_AE_THR), 3686 MSK_ECU_JUMBO_WM << 16 | MSK_ECU_AE_THR); 3687 /* Disable Store & Forward mode for Tx. */ 3688 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 3689 TX_JUMBO_ENA | TX_STFW_DIS); 3690 } else { 3691 /* Enable Store & Forward mode for Tx. */ 3692 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 3693 TX_JUMBO_DIS | TX_STFW_ENA); 3694 } 3695 } 3696 3697 if (sc->msk_hw_id == CHIP_ID_YUKON_FE_P && 3698 sc->msk_hw_rev == CHIP_REV_YU_FE_P_A0) { 3699 /* Disable dynamic watermark - from Linux. */ 3700 reg = CSR_READ_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_EA)); 3701 reg &= ~0x03; 3702 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_EA), reg); 3703 } 3704 3705 /* 3706 * Disable Force Sync bit and Alloc bit in Tx RAM interface 3707 * arbiter as we don't use Sync Tx queue. 3708 */ 3709 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, TXA_CTRL), 3710 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC); 3711 /* Enable the RAM Interface Arbiter. */ 3712 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, TXA_CTRL), TXA_ENA_ARB); 3713 3714 /* Setup RAM buffer. */ 3715 msk_set_rambuffer(sc_if); 3716 3717 /* Disable Tx sync Queue. */ 3718 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txsq, RB_CTRL), RB_RST_SET); 3719 3720 /* Setup Tx Queue Bus Memory Interface. */ 3721 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_CLR_RESET); 3722 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_OPER_INIT); 3723 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_FIFO_OP_ON); 3724 CSR_WRITE_2(sc, Q_ADDR(sc_if->msk_txq, Q_WM), MSK_BMU_TX_WM); 3725 if (sc->msk_hw_id == CHIP_ID_YUKON_EC_U && 3726 sc->msk_hw_rev == CHIP_REV_YU_EC_U_A0) { 3727 /* Fix for Yukon-EC Ultra: set BMU FIFO level */ 3728 CSR_WRITE_2(sc, Q_ADDR(sc_if->msk_txq, Q_AL), MSK_ECU_TXFF_LEV); 3729 } 3730 3731 /* Setup Rx Queue Bus Memory Interface. */ 3732 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_CLR_RESET); 3733 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_OPER_INIT); 3734 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_FIFO_OP_ON); 3735 CSR_WRITE_2(sc, Q_ADDR(sc_if->msk_rxq, Q_WM), MSK_BMU_RX_WM); 3736 if (sc->msk_hw_id == CHIP_ID_YUKON_EC_U && 3737 sc->msk_hw_rev >= CHIP_REV_YU_EC_U_A1) { 3738 /* MAC Rx RAM Read is controlled by hardware. */ 3739 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_F), F_M_RX_RAM_DIS); 3740 } 3741 3742 msk_set_prefetch(sc, sc_if->msk_txq, 3743 sc_if->msk_rdata.msk_tx_ring_paddr, MSK_TX_RING_CNT - 1); 3744 msk_init_tx_ring(sc_if); 3745 3746 /* Disable Rx checksum offload and RSS hash. */ 3747 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), 3748 BMU_DIS_RX_CHKSUM | BMU_DIS_RX_RSS_HASH); 3749 if (sc_if->msk_framesize > (MCLBYTES - MSK_RX_BUF_ALIGN)) { 3750 msk_set_prefetch(sc, sc_if->msk_rxq, 3751 sc_if->msk_rdata.msk_jumbo_rx_ring_paddr, 3752 MSK_JUMBO_RX_RING_CNT - 1); 3753 error = msk_init_jumbo_rx_ring(sc_if); 3754 } else { 3755 msk_set_prefetch(sc, sc_if->msk_rxq, 3756 sc_if->msk_rdata.msk_rx_ring_paddr, 3757 MSK_RX_RING_CNT - 1); 3758 error = msk_init_rx_ring(sc_if); 3759 } 3760 if (error != 0) { 3761 device_printf(sc_if->msk_if_dev, 3762 "initialization failed: no memory for Rx buffers\n"); 3763 msk_stop(sc_if); 3764 return; 3765 } 3766 3767 /* Configure interrupt handling. */ 3768 if (sc_if->msk_port == MSK_PORT_A) { 3769 sc->msk_intrmask |= Y2_IS_PORT_A; 3770 sc->msk_intrhwemask |= Y2_HWE_L1_MASK; 3771 } else { 3772 sc->msk_intrmask |= Y2_IS_PORT_B; 3773 sc->msk_intrhwemask |= Y2_HWE_L2_MASK; 3774 } 3775 CSR_WRITE_4(sc, B0_HWE_IMSK, sc->msk_intrhwemask); 3776 CSR_READ_4(sc, B0_HWE_IMSK); 3777 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask); 3778 CSR_READ_4(sc, B0_IMSK); 3779 3780 sc_if->msk_flags &= ~MSK_FLAG_LINK; 3781 mii_mediachg(mii); 3782 3783 ifp->if_drv_flags |= IFF_DRV_RUNNING; 3784 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3785 3786 callout_reset(&sc_if->msk_tick_ch, hz, msk_tick, sc_if); 3787 } 3788 3789 static void 3790 msk_set_rambuffer(struct msk_if_softc *sc_if) 3791 { 3792 struct msk_softc *sc; 3793 int ltpp, utpp; 3794 3795 sc = sc_if->msk_softc; 3796 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) == 0) 3797 return; 3798 3799 /* Setup Rx Queue. */ 3800 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_RST_CLR); 3801 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_START), 3802 sc->msk_rxqstart[sc_if->msk_port] / 8); 3803 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_END), 3804 sc->msk_rxqend[sc_if->msk_port] / 8); 3805 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_WP), 3806 sc->msk_rxqstart[sc_if->msk_port] / 8); 3807 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_RP), 3808 sc->msk_rxqstart[sc_if->msk_port] / 8); 3809 3810 utpp = (sc->msk_rxqend[sc_if->msk_port] + 1 - 3811 sc->msk_rxqstart[sc_if->msk_port] - MSK_RB_ULPP) / 8; 3812 ltpp = (sc->msk_rxqend[sc_if->msk_port] + 1 - 3813 sc->msk_rxqstart[sc_if->msk_port] - MSK_RB_LLPP_B) / 8; 3814 if (sc->msk_rxqsize < MSK_MIN_RXQ_SIZE) 3815 ltpp += (MSK_RB_LLPP_B - MSK_RB_LLPP_S) / 8; 3816 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_RX_UTPP), utpp); 3817 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_RX_LTPP), ltpp); 3818 /* Set Rx priority(RB_RX_UTHP/RB_RX_LTHP) thresholds? */ 3819 3820 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_ENA_OP_MD); 3821 CSR_READ_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL)); 3822 3823 /* Setup Tx Queue. */ 3824 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_RST_CLR); 3825 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_START), 3826 sc->msk_txqstart[sc_if->msk_port] / 8); 3827 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_END), 3828 sc->msk_txqend[sc_if->msk_port] / 8); 3829 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_WP), 3830 sc->msk_txqstart[sc_if->msk_port] / 8); 3831 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_RP), 3832 sc->msk_txqstart[sc_if->msk_port] / 8); 3833 /* Enable Store & Forward for Tx side. */ 3834 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_ENA_STFWD); 3835 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_ENA_OP_MD); 3836 CSR_READ_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL)); 3837 } 3838 3839 static void 3840 msk_set_prefetch(struct msk_softc *sc, int qaddr, bus_addr_t addr, 3841 uint32_t count) 3842 { 3843 3844 /* Reset the prefetch unit. */ 3845 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG), 3846 PREF_UNIT_RST_SET); 3847 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG), 3848 PREF_UNIT_RST_CLR); 3849 /* Set LE base address. */ 3850 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_ADDR_LOW_REG), 3851 MSK_ADDR_LO(addr)); 3852 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_ADDR_HI_REG), 3853 MSK_ADDR_HI(addr)); 3854 /* Set the list last index. */ 3855 CSR_WRITE_2(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_LAST_IDX_REG), 3856 count); 3857 /* Turn on prefetch unit. */ 3858 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG), 3859 PREF_UNIT_OP_ON); 3860 /* Dummy read to ensure write. */ 3861 CSR_READ_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG)); 3862 } 3863 3864 static void 3865 msk_stop(struct msk_if_softc *sc_if) 3866 { 3867 struct msk_softc *sc; 3868 struct msk_txdesc *txd; 3869 struct msk_rxdesc *rxd; 3870 struct msk_rxdesc *jrxd; 3871 struct ifnet *ifp; 3872 uint32_t val; 3873 int i; 3874 3875 MSK_IF_LOCK_ASSERT(sc_if); 3876 sc = sc_if->msk_softc; 3877 ifp = sc_if->msk_ifp; 3878 3879 callout_stop(&sc_if->msk_tick_ch); 3880 sc_if->msk_watchdog_timer = 0; 3881 3882 /* Disable interrupts. */ 3883 if (sc_if->msk_port == MSK_PORT_A) { 3884 sc->msk_intrmask &= ~Y2_IS_PORT_A; 3885 sc->msk_intrhwemask &= ~Y2_HWE_L1_MASK; 3886 } else { 3887 sc->msk_intrmask &= ~Y2_IS_PORT_B; 3888 sc->msk_intrhwemask &= ~Y2_HWE_L2_MASK; 3889 } 3890 CSR_WRITE_4(sc, B0_HWE_IMSK, sc->msk_intrhwemask); 3891 CSR_READ_4(sc, B0_HWE_IMSK); 3892 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask); 3893 CSR_READ_4(sc, B0_IMSK); 3894 3895 /* Disable Tx/Rx MAC. */ 3896 val = GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL); 3897 val &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA); 3898 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, val); 3899 /* Read again to ensure writing. */ 3900 GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL); 3901 /* Update stats and clear counters. */ 3902 msk_stats_update(sc_if); 3903 3904 /* Stop Tx BMU. */ 3905 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_STOP); 3906 val = CSR_READ_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR)); 3907 for (i = 0; i < MSK_TIMEOUT; i++) { 3908 if ((val & (BMU_STOP | BMU_IDLE)) == 0) { 3909 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), 3910 BMU_STOP); 3911 val = CSR_READ_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR)); 3912 } else 3913 break; 3914 DELAY(1); 3915 } 3916 if (i == MSK_TIMEOUT) 3917 device_printf(sc_if->msk_if_dev, "Tx BMU stop failed\n"); 3918 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), 3919 RB_RST_SET | RB_DIS_OP_MD); 3920 3921 /* Disable all GMAC interrupt. */ 3922 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_MSK), 0); 3923 /* Disable PHY interrupt. */ 3924 msk_phy_writereg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_MASK, 0); 3925 3926 /* Disable the RAM Interface Arbiter. */ 3927 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, TXA_CTRL), TXA_DIS_ARB); 3928 3929 /* Reset the PCI FIFO of the async Tx queue */ 3930 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), 3931 BMU_RST_SET | BMU_FIFO_RST); 3932 3933 /* Reset the Tx prefetch units. */ 3934 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(sc_if->msk_txq, PREF_UNIT_CTRL_REG), 3935 PREF_UNIT_RST_SET); 3936 3937 /* Reset the RAM Buffer async Tx queue. */ 3938 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_RST_SET); 3939 3940 /* Reset Tx MAC FIFO. */ 3941 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_RST_SET); 3942 /* Set Pause Off. */ 3943 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_PAUSE_OFF); 3944 3945 /* 3946 * The Rx Stop command will not work for Yukon-2 if the BMU does not 3947 * reach the end of packet and since we can't make sure that we have 3948 * incoming data, we must reset the BMU while it is not during a DMA 3949 * transfer. Since it is possible that the Rx path is still active, 3950 * the Rx RAM buffer will be stopped first, so any possible incoming 3951 * data will not trigger a DMA. After the RAM buffer is stopped, the 3952 * BMU is polled until any DMA in progress is ended and only then it 3953 * will be reset. 3954 */ 3955 3956 /* Disable the RAM Buffer receive queue. */ 3957 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_DIS_OP_MD); 3958 for (i = 0; i < MSK_TIMEOUT; i++) { 3959 if (CSR_READ_1(sc, RB_ADDR(sc_if->msk_rxq, Q_RSL)) == 3960 CSR_READ_1(sc, RB_ADDR(sc_if->msk_rxq, Q_RL))) 3961 break; 3962 DELAY(1); 3963 } 3964 if (i == MSK_TIMEOUT) 3965 device_printf(sc_if->msk_if_dev, "Rx BMU stop failed\n"); 3966 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), 3967 BMU_RST_SET | BMU_FIFO_RST); 3968 /* Reset the Rx prefetch unit. */ 3969 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_CTRL_REG), 3970 PREF_UNIT_RST_SET); 3971 /* Reset the RAM Buffer receive queue. */ 3972 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_RST_SET); 3973 /* Reset Rx MAC FIFO. */ 3974 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), GMF_RST_SET); 3975 3976 /* Free Rx and Tx mbufs still in the queues. */ 3977 for (i = 0; i < MSK_RX_RING_CNT; i++) { 3978 rxd = &sc_if->msk_cdata.msk_rxdesc[i]; 3979 if (rxd->rx_m != NULL) { 3980 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_tag, 3981 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 3982 bus_dmamap_unload(sc_if->msk_cdata.msk_rx_tag, 3983 rxd->rx_dmamap); 3984 m_freem(rxd->rx_m); 3985 rxd->rx_m = NULL; 3986 } 3987 } 3988 for (i = 0; i < MSK_JUMBO_RX_RING_CNT; i++) { 3989 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[i]; 3990 if (jrxd->rx_m != NULL) { 3991 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_tag, 3992 jrxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 3993 bus_dmamap_unload(sc_if->msk_cdata.msk_jumbo_rx_tag, 3994 jrxd->rx_dmamap); 3995 m_freem(jrxd->rx_m); 3996 jrxd->rx_m = NULL; 3997 } 3998 } 3999 for (i = 0; i < MSK_TX_RING_CNT; i++) { 4000 txd = &sc_if->msk_cdata.msk_txdesc[i]; 4001 if (txd->tx_m != NULL) { 4002 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_tag, 4003 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 4004 bus_dmamap_unload(sc_if->msk_cdata.msk_tx_tag, 4005 txd->tx_dmamap); 4006 m_freem(txd->tx_m); 4007 txd->tx_m = NULL; 4008 } 4009 } 4010 4011 /* 4012 * Mark the interface down. 4013 */ 4014 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 4015 sc_if->msk_flags &= ~MSK_FLAG_LINK; 4016 } 4017 4018 /* 4019 * When GM_PAR_MIB_CLR bit of GM_PHY_ADDR is set, reading lower 4020 * counter clears high 16 bits of the counter such that accessing 4021 * lower 16 bits should be the last operation. 4022 */ 4023 #define MSK_READ_MIB32(x, y) \ 4024 (((uint32_t)GMAC_READ_2(sc, x, (y) + 4)) << 16) + \ 4025 (uint32_t)GMAC_READ_2(sc, x, y) 4026 #define MSK_READ_MIB64(x, y) \ 4027 (((uint64_t)MSK_READ_MIB32(x, (y) + 8)) << 32) + \ 4028 (uint64_t)MSK_READ_MIB32(x, y) 4029 4030 static void 4031 msk_stats_clear(struct msk_if_softc *sc_if) 4032 { 4033 struct msk_softc *sc; 4034 uint32_t reg; 4035 uint16_t gmac; 4036 int i; 4037 4038 MSK_IF_LOCK_ASSERT(sc_if); 4039 4040 sc = sc_if->msk_softc; 4041 /* Set MIB Clear Counter Mode. */ 4042 gmac = GMAC_READ_2(sc, sc_if->msk_port, GM_PHY_ADDR); 4043 GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac | GM_PAR_MIB_CLR); 4044 /* Read all MIB Counters with Clear Mode set. */ 4045 for (i = GM_RXF_UC_OK; i <= GM_TXE_FIFO_UR; i++) 4046 reg = MSK_READ_MIB32(sc_if->msk_port, i); 4047 /* Clear MIB Clear Counter Mode. */ 4048 gmac &= ~GM_PAR_MIB_CLR; 4049 GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac); 4050 } 4051 4052 static void 4053 msk_stats_update(struct msk_if_softc *sc_if) 4054 { 4055 struct msk_softc *sc; 4056 struct ifnet *ifp; 4057 struct msk_hw_stats *stats; 4058 uint16_t gmac; 4059 uint32_t reg; 4060 4061 MSK_IF_LOCK_ASSERT(sc_if); 4062 4063 ifp = sc_if->msk_ifp; 4064 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 4065 return; 4066 sc = sc_if->msk_softc; 4067 stats = &sc_if->msk_stats; 4068 /* Set MIB Clear Counter Mode. */ 4069 gmac = GMAC_READ_2(sc, sc_if->msk_port, GM_PHY_ADDR); 4070 GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac | GM_PAR_MIB_CLR); 4071 4072 /* Rx stats. */ 4073 stats->rx_ucast_frames += 4074 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_UC_OK); 4075 stats->rx_bcast_frames += 4076 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_BC_OK); 4077 stats->rx_pause_frames += 4078 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_MPAUSE); 4079 stats->rx_mcast_frames += 4080 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_MC_OK); 4081 stats->rx_crc_errs += 4082 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_FCS_ERR); 4083 reg = MSK_READ_MIB32(sc_if->msk_port, GM_RXF_SPARE1); 4084 stats->rx_good_octets += 4085 MSK_READ_MIB64(sc_if->msk_port, GM_RXO_OK_LO); 4086 stats->rx_bad_octets += 4087 MSK_READ_MIB64(sc_if->msk_port, GM_RXO_ERR_LO); 4088 stats->rx_runts += 4089 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_SHT); 4090 stats->rx_runt_errs += 4091 MSK_READ_MIB32(sc_if->msk_port, GM_RXE_FRAG); 4092 stats->rx_pkts_64 += 4093 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_64B); 4094 stats->rx_pkts_65_127 += 4095 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_127B); 4096 stats->rx_pkts_128_255 += 4097 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_255B); 4098 stats->rx_pkts_256_511 += 4099 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_511B); 4100 stats->rx_pkts_512_1023 += 4101 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_1023B); 4102 stats->rx_pkts_1024_1518 += 4103 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_1518B); 4104 stats->rx_pkts_1519_max += 4105 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_MAX_SZ); 4106 stats->rx_pkts_too_long += 4107 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_LNG_ERR); 4108 stats->rx_pkts_jabbers += 4109 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_JAB_PKT); 4110 reg = MSK_READ_MIB32(sc_if->msk_port, GM_RXF_SPARE2); 4111 stats->rx_fifo_oflows += 4112 MSK_READ_MIB32(sc_if->msk_port, GM_RXE_FIFO_OV); 4113 reg = MSK_READ_MIB32(sc_if->msk_port, GM_RXF_SPARE3); 4114 4115 /* Tx stats. */ 4116 stats->tx_ucast_frames += 4117 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_UC_OK); 4118 stats->tx_bcast_frames += 4119 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_BC_OK); 4120 stats->tx_pause_frames += 4121 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_MPAUSE); 4122 stats->tx_mcast_frames += 4123 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_MC_OK); 4124 stats->tx_octets += 4125 MSK_READ_MIB64(sc_if->msk_port, GM_TXO_OK_LO); 4126 stats->tx_pkts_64 += 4127 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_64B); 4128 stats->tx_pkts_65_127 += 4129 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_127B); 4130 stats->tx_pkts_128_255 += 4131 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_255B); 4132 stats->tx_pkts_256_511 += 4133 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_511B); 4134 stats->tx_pkts_512_1023 += 4135 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_1023B); 4136 stats->tx_pkts_1024_1518 += 4137 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_1518B); 4138 stats->tx_pkts_1519_max += 4139 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_MAX_SZ); 4140 reg = MSK_READ_MIB32(sc_if->msk_port, GM_TXF_SPARE1); 4141 stats->tx_colls += 4142 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_COL); 4143 stats->tx_late_colls += 4144 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_LAT_COL); 4145 stats->tx_excess_colls += 4146 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_ABO_COL); 4147 stats->tx_multi_colls += 4148 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_MUL_COL); 4149 stats->tx_single_colls += 4150 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_SNG_COL); 4151 stats->tx_underflows += 4152 MSK_READ_MIB32(sc_if->msk_port, GM_TXE_FIFO_UR); 4153 /* Clear MIB Clear Counter Mode. */ 4154 gmac &= ~GM_PAR_MIB_CLR; 4155 GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac); 4156 } 4157 4158 static int 4159 msk_sysctl_stat32(SYSCTL_HANDLER_ARGS) 4160 { 4161 struct msk_softc *sc; 4162 struct msk_if_softc *sc_if; 4163 uint32_t result, *stat; 4164 int off; 4165 4166 sc_if = (struct msk_if_softc *)arg1; 4167 sc = sc_if->msk_softc; 4168 off = arg2; 4169 stat = (uint32_t *)((uint8_t *)&sc_if->msk_stats + off); 4170 4171 MSK_IF_LOCK(sc_if); 4172 result = MSK_READ_MIB32(sc_if->msk_port, GM_MIB_CNT_BASE + off * 2); 4173 result += *stat; 4174 MSK_IF_UNLOCK(sc_if); 4175 4176 return (sysctl_handle_int(oidp, &result, 0, req)); 4177 } 4178 4179 static int 4180 msk_sysctl_stat64(SYSCTL_HANDLER_ARGS) 4181 { 4182 struct msk_softc *sc; 4183 struct msk_if_softc *sc_if; 4184 uint64_t result, *stat; 4185 int off; 4186 4187 sc_if = (struct msk_if_softc *)arg1; 4188 sc = sc_if->msk_softc; 4189 off = arg2; 4190 stat = (uint64_t *)((uint8_t *)&sc_if->msk_stats + off); 4191 4192 MSK_IF_LOCK(sc_if); 4193 result = MSK_READ_MIB64(sc_if->msk_port, GM_MIB_CNT_BASE + off * 2); 4194 result += *stat; 4195 MSK_IF_UNLOCK(sc_if); 4196 4197 return (sysctl_handle_quad(oidp, &result, 0, req)); 4198 } 4199 4200 #undef MSK_READ_MIB32 4201 #undef MSK_READ_MIB64 4202 4203 #define MSK_SYSCTL_STAT32(sc, c, o, p, n, d) \ 4204 SYSCTL_ADD_PROC(c, p, OID_AUTO, o, CTLTYPE_UINT | CTLFLAG_RD, \ 4205 sc, offsetof(struct msk_hw_stats, n), msk_sysctl_stat32, \ 4206 "IU", d) 4207 #define MSK_SYSCTL_STAT64(sc, c, o, p, n, d) \ 4208 SYSCTL_ADD_PROC(c, p, OID_AUTO, o, CTLTYPE_UINT | CTLFLAG_RD, \ 4209 sc, offsetof(struct msk_hw_stats, n), msk_sysctl_stat64, \ 4210 "Q", d) 4211 4212 static void 4213 msk_sysctl_node(struct msk_if_softc *sc_if) 4214 { 4215 struct sysctl_ctx_list *ctx; 4216 struct sysctl_oid_list *child, *schild; 4217 struct sysctl_oid *tree; 4218 4219 ctx = device_get_sysctl_ctx(sc_if->msk_if_dev); 4220 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc_if->msk_if_dev)); 4221 4222 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD, 4223 NULL, "MSK Statistics"); 4224 schild = child = SYSCTL_CHILDREN(tree); 4225 tree = SYSCTL_ADD_NODE(ctx, schild, OID_AUTO, "rx", CTLFLAG_RD, 4226 NULL, "MSK RX Statistics"); 4227 child = SYSCTL_CHILDREN(tree); 4228 MSK_SYSCTL_STAT32(sc_if, ctx, "ucast_frames", 4229 child, rx_ucast_frames, "Good unicast frames"); 4230 MSK_SYSCTL_STAT32(sc_if, ctx, "bcast_frames", 4231 child, rx_bcast_frames, "Good broadcast frames"); 4232 MSK_SYSCTL_STAT32(sc_if, ctx, "pause_frames", 4233 child, rx_pause_frames, "Pause frames"); 4234 MSK_SYSCTL_STAT32(sc_if, ctx, "mcast_frames", 4235 child, rx_mcast_frames, "Multicast frames"); 4236 MSK_SYSCTL_STAT32(sc_if, ctx, "crc_errs", 4237 child, rx_crc_errs, "CRC errors"); 4238 MSK_SYSCTL_STAT64(sc_if, ctx, "good_octets", 4239 child, rx_good_octets, "Good octets"); 4240 MSK_SYSCTL_STAT64(sc_if, ctx, "bad_octets", 4241 child, rx_bad_octets, "Bad octets"); 4242 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_64", 4243 child, rx_pkts_64, "64 bytes frames"); 4244 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_65_127", 4245 child, rx_pkts_65_127, "65 to 127 bytes frames"); 4246 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_128_255", 4247 child, rx_pkts_128_255, "128 to 255 bytes frames"); 4248 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_256_511", 4249 child, rx_pkts_256_511, "256 to 511 bytes frames"); 4250 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_512_1023", 4251 child, rx_pkts_512_1023, "512 to 1023 bytes frames"); 4252 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_1024_1518", 4253 child, rx_pkts_1024_1518, "1024 to 1518 bytes frames"); 4254 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_1519_max", 4255 child, rx_pkts_1519_max, "1519 to max frames"); 4256 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_too_long", 4257 child, rx_pkts_too_long, "frames too long"); 4258 MSK_SYSCTL_STAT32(sc_if, ctx, "jabbers", 4259 child, rx_pkts_jabbers, "Jabber errors"); 4260 MSK_SYSCTL_STAT32(sc_if, ctx, "overflows", 4261 child, rx_fifo_oflows, "FIFO overflows"); 4262 4263 tree = SYSCTL_ADD_NODE(ctx, schild, OID_AUTO, "tx", CTLFLAG_RD, 4264 NULL, "MSK TX Statistics"); 4265 child = SYSCTL_CHILDREN(tree); 4266 MSK_SYSCTL_STAT32(sc_if, ctx, "ucast_frames", 4267 child, tx_ucast_frames, "Unicast frames"); 4268 MSK_SYSCTL_STAT32(sc_if, ctx, "bcast_frames", 4269 child, tx_bcast_frames, "Broadcast frames"); 4270 MSK_SYSCTL_STAT32(sc_if, ctx, "pause_frames", 4271 child, tx_pause_frames, "Pause frames"); 4272 MSK_SYSCTL_STAT32(sc_if, ctx, "mcast_frames", 4273 child, tx_mcast_frames, "Multicast frames"); 4274 MSK_SYSCTL_STAT64(sc_if, ctx, "octets", 4275 child, tx_octets, "Octets"); 4276 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_64", 4277 child, tx_pkts_64, "64 bytes frames"); 4278 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_65_127", 4279 child, tx_pkts_65_127, "65 to 127 bytes frames"); 4280 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_128_255", 4281 child, tx_pkts_128_255, "128 to 255 bytes frames"); 4282 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_256_511", 4283 child, tx_pkts_256_511, "256 to 511 bytes frames"); 4284 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_512_1023", 4285 child, tx_pkts_512_1023, "512 to 1023 bytes frames"); 4286 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_1024_1518", 4287 child, tx_pkts_1024_1518, "1024 to 1518 bytes frames"); 4288 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_1519_max", 4289 child, tx_pkts_1519_max, "1519 to max frames"); 4290 MSK_SYSCTL_STAT32(sc_if, ctx, "colls", 4291 child, tx_colls, "Collisions"); 4292 MSK_SYSCTL_STAT32(sc_if, ctx, "late_colls", 4293 child, tx_late_colls, "Late collisions"); 4294 MSK_SYSCTL_STAT32(sc_if, ctx, "excess_colls", 4295 child, tx_excess_colls, "Excessive collisions"); 4296 MSK_SYSCTL_STAT32(sc_if, ctx, "multi_colls", 4297 child, tx_multi_colls, "Multiple collisions"); 4298 MSK_SYSCTL_STAT32(sc_if, ctx, "single_colls", 4299 child, tx_single_colls, "Single collisions"); 4300 MSK_SYSCTL_STAT32(sc_if, ctx, "underflows", 4301 child, tx_underflows, "FIFO underflows"); 4302 } 4303 4304 #undef MSK_SYSCTL_STAT32 4305 #undef MSK_SYSCTL_STAT64 4306 4307 static int 4308 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 4309 { 4310 int error, value; 4311 4312 if (!arg1) 4313 return (EINVAL); 4314 value = *(int *)arg1; 4315 error = sysctl_handle_int(oidp, &value, 0, req); 4316 if (error || !req->newptr) 4317 return (error); 4318 if (value < low || value > high) 4319 return (EINVAL); 4320 *(int *)arg1 = value; 4321 4322 return (0); 4323 } 4324 4325 static int 4326 sysctl_hw_msk_proc_limit(SYSCTL_HANDLER_ARGS) 4327 { 4328 4329 return (sysctl_int_range(oidp, arg1, arg2, req, MSK_PROC_MIN, 4330 MSK_PROC_MAX)); 4331 } 4332