1 /****************************************************************************** 2 * 3 * Name : sky2.c 4 * Project: Gigabit Ethernet Driver for FreeBSD 5.x/6.x 5 * Version: $Revision: 1.23 $ 6 * Date : $Date: 2005/12/22 09:04:11 $ 7 * Purpose: Main driver source file 8 * 9 *****************************************************************************/ 10 11 /****************************************************************************** 12 * 13 * LICENSE: 14 * Copyright (C) Marvell International Ltd. and/or its affiliates 15 * 16 * The computer program files contained in this folder ("Files") 17 * are provided to you under the BSD-type license terms provided 18 * below, and any use of such Files and any derivative works 19 * thereof created by you shall be governed by the following terms 20 * and conditions: 21 * 22 * - Redistributions of source code must retain the above copyright 23 * notice, this list of conditions and the following disclaimer. 24 * - Redistributions in binary form must reproduce the above 25 * copyright notice, this list of conditions and the following 26 * disclaimer in the documentation and/or other materials provided 27 * with the distribution. 28 * - Neither the name of Marvell nor the names of its contributors 29 * may be used to endorse or promote products derived from this 30 * software without specific prior written permission. 31 * 32 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 33 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 34 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 35 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 36 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 37 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 38 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 39 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 40 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 41 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 42 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED 43 * OF THE POSSIBILITY OF SUCH DAMAGE. 44 * /LICENSE 45 * 46 *****************************************************************************/ 47 48 /*- 49 * Copyright (c) 1997, 1998, 1999, 2000 50 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 51 * 52 * Redistribution and use in source and binary forms, with or without 53 * modification, are permitted provided that the following conditions 54 * are met: 55 * 1. Redistributions of source code must retain the above copyright 56 * notice, this list of conditions and the following disclaimer. 57 * 2. Redistributions in binary form must reproduce the above copyright 58 * notice, this list of conditions and the following disclaimer in the 59 * documentation and/or other materials provided with the distribution. 60 * 3. All advertising materials mentioning features or use of this software 61 * must display the following acknowledgement: 62 * This product includes software developed by Bill Paul. 63 * 4. Neither the name of the author nor the names of any co-contributors 64 * may be used to endorse or promote products derived from this software 65 * without specific prior written permission. 66 * 67 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 68 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 69 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 70 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 71 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 72 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 73 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 74 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 75 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 76 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 77 * THE POSSIBILITY OF SUCH DAMAGE. 78 */ 79 /*- 80 * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu> 81 * 82 * Permission to use, copy, modify, and distribute this software for any 83 * purpose with or without fee is hereby granted, provided that the above 84 * copyright notice and this permission notice appear in all copies. 85 * 86 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 87 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 88 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 89 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 90 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 91 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 92 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 93 */ 94 95 /* 96 * Device driver for the Marvell Yukon II Ethernet controller. 97 * Due to lack of documentation, this driver is based on the code from 98 * sk(4) and Marvell's myk(4) driver for FreeBSD 5.x. 99 */ 100 101 #include <sys/cdefs.h> 102 __FBSDID("$FreeBSD$"); 103 104 #include <sys/param.h> 105 #include <sys/systm.h> 106 #include <sys/bus.h> 107 #include <sys/endian.h> 108 #include <sys/mbuf.h> 109 #include <sys/malloc.h> 110 #include <sys/kernel.h> 111 #include <sys/module.h> 112 #include <sys/socket.h> 113 #include <sys/sockio.h> 114 #include <sys/queue.h> 115 #include <sys/sysctl.h> 116 #include <sys/taskqueue.h> 117 118 #include <net/bpf.h> 119 #include <net/ethernet.h> 120 #include <net/if.h> 121 #include <net/if_arp.h> 122 #include <net/if_dl.h> 123 #include <net/if_media.h> 124 #include <net/if_types.h> 125 #include <net/if_vlan_var.h> 126 127 #include <netinet/in.h> 128 #include <netinet/in_systm.h> 129 #include <netinet/ip.h> 130 #include <netinet/tcp.h> 131 #include <netinet/udp.h> 132 133 #include <machine/bus.h> 134 #include <machine/in_cksum.h> 135 #include <machine/resource.h> 136 #include <sys/rman.h> 137 138 #include <dev/mii/mii.h> 139 #include <dev/mii/miivar.h> 140 #include <dev/mii/brgphyreg.h> 141 142 #include <dev/pci/pcireg.h> 143 #include <dev/pci/pcivar.h> 144 145 #include <dev/msk/if_mskreg.h> 146 147 MODULE_DEPEND(msk, pci, 1, 1, 1); 148 MODULE_DEPEND(msk, ether, 1, 1, 1); 149 MODULE_DEPEND(msk, miibus, 1, 1, 1); 150 151 /* "device miibus" required. See GENERIC if you get errors here. */ 152 #include "miibus_if.h" 153 154 /* Tunables. */ 155 static int msi_disable = 0; 156 TUNABLE_INT("hw.msk.msi_disable", &msi_disable); 157 static int legacy_intr = 0; 158 TUNABLE_INT("hw.msk.legacy_intr", &legacy_intr); 159 static int jumbo_disable = 0; 160 TUNABLE_INT("hw.msk.jumbo_disable", &jumbo_disable); 161 162 #define MSK_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 163 164 /* 165 * Devices supported by this driver. 166 */ 167 static struct msk_product { 168 uint16_t msk_vendorid; 169 uint16_t msk_deviceid; 170 const char *msk_name; 171 } msk_products[] = { 172 { VENDORID_SK, DEVICEID_SK_YUKON2, 173 "SK-9Sxx Gigabit Ethernet" }, 174 { VENDORID_SK, DEVICEID_SK_YUKON2_EXPR, 175 "SK-9Exx Gigabit Ethernet"}, 176 { VENDORID_MARVELL, DEVICEID_MRVL_8021CU, 177 "Marvell Yukon 88E8021CU Gigabit Ethernet" }, 178 { VENDORID_MARVELL, DEVICEID_MRVL_8021X, 179 "Marvell Yukon 88E8021 SX/LX Gigabit Ethernet" }, 180 { VENDORID_MARVELL, DEVICEID_MRVL_8022CU, 181 "Marvell Yukon 88E8022CU Gigabit Ethernet" }, 182 { VENDORID_MARVELL, DEVICEID_MRVL_8022X, 183 "Marvell Yukon 88E8022 SX/LX Gigabit Ethernet" }, 184 { VENDORID_MARVELL, DEVICEID_MRVL_8061CU, 185 "Marvell Yukon 88E8061CU Gigabit Ethernet" }, 186 { VENDORID_MARVELL, DEVICEID_MRVL_8061X, 187 "Marvell Yukon 88E8061 SX/LX Gigabit Ethernet" }, 188 { VENDORID_MARVELL, DEVICEID_MRVL_8062CU, 189 "Marvell Yukon 88E8062CU Gigabit Ethernet" }, 190 { VENDORID_MARVELL, DEVICEID_MRVL_8062X, 191 "Marvell Yukon 88E8062 SX/LX Gigabit Ethernet" }, 192 { VENDORID_MARVELL, DEVICEID_MRVL_8035, 193 "Marvell Yukon 88E8035 Gigabit Ethernet" }, 194 { VENDORID_MARVELL, DEVICEID_MRVL_8036, 195 "Marvell Yukon 88E8036 Gigabit Ethernet" }, 196 { VENDORID_MARVELL, DEVICEID_MRVL_8038, 197 "Marvell Yukon 88E8038 Gigabit Ethernet" }, 198 { VENDORID_MARVELL, DEVICEID_MRVL_8039, 199 "Marvell Yukon 88E8039 Gigabit Ethernet" }, 200 { VENDORID_MARVELL, DEVICEID_MRVL_4361, 201 "Marvell Yukon 88E8050 Gigabit Ethernet" }, 202 { VENDORID_MARVELL, DEVICEID_MRVL_4360, 203 "Marvell Yukon 88E8052 Gigabit Ethernet" }, 204 { VENDORID_MARVELL, DEVICEID_MRVL_4362, 205 "Marvell Yukon 88E8053 Gigabit Ethernet" }, 206 { VENDORID_MARVELL, DEVICEID_MRVL_4363, 207 "Marvell Yukon 88E8055 Gigabit Ethernet" }, 208 { VENDORID_MARVELL, DEVICEID_MRVL_4364, 209 "Marvell Yukon 88E8056 Gigabit Ethernet" }, 210 { VENDORID_MARVELL, DEVICEID_MRVL_436A, 211 "Marvell Yukon 88E8058 Gigabit Ethernet" }, 212 { VENDORID_DLINK, DEVICEID_DLINK_DGE550SX, 213 "D-Link 550SX Gigabit Ethernet" }, 214 { VENDORID_DLINK, DEVICEID_DLINK_DGE560T, 215 "D-Link 560T Gigabit Ethernet" } 216 }; 217 218 static const char *model_name[] = { 219 "Yukon XL", 220 "Yukon EC Ultra", 221 "Yukon Unknown", 222 "Yukon EC", 223 "Yukon FE" 224 }; 225 226 static int mskc_probe(device_t); 227 static int mskc_attach(device_t); 228 static int mskc_detach(device_t); 229 static int mskc_shutdown(device_t); 230 static int mskc_setup_rambuffer(struct msk_softc *); 231 static int mskc_suspend(device_t); 232 static int mskc_resume(device_t); 233 static void mskc_reset(struct msk_softc *); 234 235 static int msk_probe(device_t); 236 static int msk_attach(device_t); 237 static int msk_detach(device_t); 238 239 static void msk_tick(void *); 240 static void msk_legacy_intr(void *); 241 static int msk_intr(void *); 242 static void msk_int_task(void *, int); 243 static void msk_intr_phy(struct msk_if_softc *); 244 static void msk_intr_gmac(struct msk_if_softc *); 245 static __inline void msk_rxput(struct msk_if_softc *); 246 static int msk_handle_events(struct msk_softc *); 247 static void msk_handle_hwerr(struct msk_if_softc *, uint32_t); 248 static void msk_intr_hwerr(struct msk_softc *); 249 #ifndef __NO_STRICT_ALIGNMENT 250 static __inline void msk_fixup_rx(struct mbuf *); 251 #endif 252 static void msk_rxeof(struct msk_if_softc *, uint32_t, int); 253 static void msk_jumbo_rxeof(struct msk_if_softc *, uint32_t, int); 254 static void msk_txeof(struct msk_if_softc *, int); 255 static int msk_encap(struct msk_if_softc *, struct mbuf **); 256 static void msk_tx_task(void *, int); 257 static void msk_start(struct ifnet *); 258 static int msk_ioctl(struct ifnet *, u_long, caddr_t); 259 static void msk_set_prefetch(struct msk_softc *, int, bus_addr_t, uint32_t); 260 static void msk_set_rambuffer(struct msk_if_softc *); 261 static void msk_init(void *); 262 static void msk_init_locked(struct msk_if_softc *); 263 static void msk_stop(struct msk_if_softc *); 264 static void msk_watchdog(struct msk_if_softc *); 265 static int msk_mediachange(struct ifnet *); 266 static void msk_mediastatus(struct ifnet *, struct ifmediareq *); 267 static void msk_phy_power(struct msk_softc *, int); 268 static void msk_dmamap_cb(void *, bus_dma_segment_t *, int, int); 269 static int msk_status_dma_alloc(struct msk_softc *); 270 static void msk_status_dma_free(struct msk_softc *); 271 static int msk_txrx_dma_alloc(struct msk_if_softc *); 272 static int msk_rx_dma_jalloc(struct msk_if_softc *); 273 static void msk_txrx_dma_free(struct msk_if_softc *); 274 static void msk_rx_dma_jfree(struct msk_if_softc *); 275 static int msk_init_rx_ring(struct msk_if_softc *); 276 static int msk_init_jumbo_rx_ring(struct msk_if_softc *); 277 static void msk_init_tx_ring(struct msk_if_softc *); 278 static __inline void msk_discard_rxbuf(struct msk_if_softc *, int); 279 static __inline void msk_discard_jumbo_rxbuf(struct msk_if_softc *, int); 280 static int msk_newbuf(struct msk_if_softc *, int); 281 static int msk_jumbo_newbuf(struct msk_if_softc *, int); 282 283 static int msk_phy_readreg(struct msk_if_softc *, int, int); 284 static int msk_phy_writereg(struct msk_if_softc *, int, int, int); 285 static int msk_miibus_readreg(device_t, int, int); 286 static int msk_miibus_writereg(device_t, int, int, int); 287 static void msk_miibus_statchg(device_t); 288 static void msk_link_task(void *, int); 289 290 static void msk_rxfilter(struct msk_if_softc *); 291 static void msk_setvlan(struct msk_if_softc *, struct ifnet *); 292 293 static void msk_stats_clear(struct msk_if_softc *); 294 static void msk_stats_update(struct msk_if_softc *); 295 static int msk_sysctl_stat32(SYSCTL_HANDLER_ARGS); 296 static int msk_sysctl_stat64(SYSCTL_HANDLER_ARGS); 297 static void msk_sysctl_node(struct msk_if_softc *); 298 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int); 299 static int sysctl_hw_msk_proc_limit(SYSCTL_HANDLER_ARGS); 300 301 static device_method_t mskc_methods[] = { 302 /* Device interface */ 303 DEVMETHOD(device_probe, mskc_probe), 304 DEVMETHOD(device_attach, mskc_attach), 305 DEVMETHOD(device_detach, mskc_detach), 306 DEVMETHOD(device_suspend, mskc_suspend), 307 DEVMETHOD(device_resume, mskc_resume), 308 DEVMETHOD(device_shutdown, mskc_shutdown), 309 310 /* bus interface */ 311 DEVMETHOD(bus_print_child, bus_generic_print_child), 312 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 313 314 { NULL, NULL } 315 }; 316 317 static driver_t mskc_driver = { 318 "mskc", 319 mskc_methods, 320 sizeof(struct msk_softc) 321 }; 322 323 static devclass_t mskc_devclass; 324 325 static device_method_t msk_methods[] = { 326 /* Device interface */ 327 DEVMETHOD(device_probe, msk_probe), 328 DEVMETHOD(device_attach, msk_attach), 329 DEVMETHOD(device_detach, msk_detach), 330 DEVMETHOD(device_shutdown, bus_generic_shutdown), 331 332 /* bus interface */ 333 DEVMETHOD(bus_print_child, bus_generic_print_child), 334 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 335 336 /* MII interface */ 337 DEVMETHOD(miibus_readreg, msk_miibus_readreg), 338 DEVMETHOD(miibus_writereg, msk_miibus_writereg), 339 DEVMETHOD(miibus_statchg, msk_miibus_statchg), 340 341 { NULL, NULL } 342 }; 343 344 static driver_t msk_driver = { 345 "msk", 346 msk_methods, 347 sizeof(struct msk_if_softc) 348 }; 349 350 static devclass_t msk_devclass; 351 352 DRIVER_MODULE(mskc, pci, mskc_driver, mskc_devclass, 0, 0); 353 DRIVER_MODULE(msk, mskc, msk_driver, msk_devclass, 0, 0); 354 DRIVER_MODULE(miibus, msk, miibus_driver, miibus_devclass, 0, 0); 355 356 static struct resource_spec msk_res_spec_io[] = { 357 { SYS_RES_IOPORT, PCIR_BAR(1), RF_ACTIVE }, 358 { -1, 0, 0 } 359 }; 360 361 static struct resource_spec msk_res_spec_mem[] = { 362 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 363 { -1, 0, 0 } 364 }; 365 366 static struct resource_spec msk_irq_spec_legacy[] = { 367 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 368 { -1, 0, 0 } 369 }; 370 371 static struct resource_spec msk_irq_spec_msi[] = { 372 { SYS_RES_IRQ, 1, RF_ACTIVE }, 373 { -1, 0, 0 } 374 }; 375 376 static struct resource_spec msk_irq_spec_msi2[] = { 377 { SYS_RES_IRQ, 1, RF_ACTIVE }, 378 { SYS_RES_IRQ, 2, RF_ACTIVE }, 379 { -1, 0, 0 } 380 }; 381 382 static int 383 msk_miibus_readreg(device_t dev, int phy, int reg) 384 { 385 struct msk_if_softc *sc_if; 386 387 if (phy != PHY_ADDR_MARV) 388 return (0); 389 390 sc_if = device_get_softc(dev); 391 392 return (msk_phy_readreg(sc_if, phy, reg)); 393 } 394 395 static int 396 msk_phy_readreg(struct msk_if_softc *sc_if, int phy, int reg) 397 { 398 struct msk_softc *sc; 399 int i, val; 400 401 sc = sc_if->msk_softc; 402 403 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SMI_CTRL, 404 GM_SMI_CT_PHY_AD(phy) | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD); 405 406 for (i = 0; i < MSK_TIMEOUT; i++) { 407 DELAY(1); 408 val = GMAC_READ_2(sc, sc_if->msk_port, GM_SMI_CTRL); 409 if ((val & GM_SMI_CT_RD_VAL) != 0) { 410 val = GMAC_READ_2(sc, sc_if->msk_port, GM_SMI_DATA); 411 break; 412 } 413 } 414 415 if (i == MSK_TIMEOUT) { 416 if_printf(sc_if->msk_ifp, "phy failed to come ready\n"); 417 val = 0; 418 } 419 420 return (val); 421 } 422 423 static int 424 msk_miibus_writereg(device_t dev, int phy, int reg, int val) 425 { 426 struct msk_if_softc *sc_if; 427 428 if (phy != PHY_ADDR_MARV) 429 return (0); 430 431 sc_if = device_get_softc(dev); 432 433 return (msk_phy_writereg(sc_if, phy, reg, val)); 434 } 435 436 static int 437 msk_phy_writereg(struct msk_if_softc *sc_if, int phy, int reg, int val) 438 { 439 struct msk_softc *sc; 440 int i; 441 442 sc = sc_if->msk_softc; 443 444 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SMI_DATA, val); 445 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SMI_CTRL, 446 GM_SMI_CT_PHY_AD(phy) | GM_SMI_CT_REG_AD(reg)); 447 for (i = 0; i < MSK_TIMEOUT; i++) { 448 DELAY(1); 449 if ((GMAC_READ_2(sc, sc_if->msk_port, GM_SMI_CTRL) & 450 GM_SMI_CT_BUSY) == 0) 451 break; 452 } 453 if (i == MSK_TIMEOUT) 454 if_printf(sc_if->msk_ifp, "phy write timeout\n"); 455 456 return (0); 457 } 458 459 static void 460 msk_miibus_statchg(device_t dev) 461 { 462 struct msk_if_softc *sc_if; 463 464 sc_if = device_get_softc(dev); 465 taskqueue_enqueue(taskqueue_swi, &sc_if->msk_link_task); 466 } 467 468 static void 469 msk_link_task(void *arg, int pending) 470 { 471 struct msk_softc *sc; 472 struct msk_if_softc *sc_if; 473 struct mii_data *mii; 474 struct ifnet *ifp; 475 uint32_t gmac; 476 477 sc_if = (struct msk_if_softc *)arg; 478 sc = sc_if->msk_softc; 479 480 MSK_IF_LOCK(sc_if); 481 482 mii = device_get_softc(sc_if->msk_miibus); 483 ifp = sc_if->msk_ifp; 484 if (mii == NULL || ifp == NULL) { 485 MSK_IF_UNLOCK(sc_if); 486 return; 487 } 488 489 if (mii->mii_media_status & IFM_ACTIVE) { 490 if (IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 491 sc_if->msk_link = 1; 492 } else 493 sc_if->msk_link = 0; 494 495 if (sc_if->msk_link != 0) { 496 /* Enable Tx FIFO Underrun. */ 497 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_MSK), 498 GM_IS_TX_FF_UR | GM_IS_RX_FF_OR); 499 /* 500 * Because mii(4) notify msk(4) that it detected link status 501 * change, there is no need to enable automatic 502 * speed/flow-control/duplex updates. 503 */ 504 gmac = GM_GPCR_AU_ALL_DIS; 505 switch (IFM_SUBTYPE(mii->mii_media_active)) { 506 case IFM_1000_SX: 507 case IFM_1000_T: 508 gmac |= GM_GPCR_SPEED_1000; 509 break; 510 case IFM_100_TX: 511 gmac |= GM_GPCR_SPEED_100; 512 break; 513 case IFM_10_T: 514 break; 515 } 516 517 if (((mii->mii_media_active & IFM_GMASK) & IFM_FDX) != 0) 518 gmac |= GM_GPCR_DUP_FULL; 519 /* Disable Rx flow control. */ 520 if (((mii->mii_media_active & IFM_GMASK) & IFM_FLAG0) == 0) 521 gmac |= GM_GPCR_FC_RX_DIS; 522 /* Disable Tx flow control. */ 523 if (((mii->mii_media_active & IFM_GMASK) & IFM_FLAG1) == 0) 524 gmac |= GM_GPCR_FC_TX_DIS; 525 gmac |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA; 526 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, gmac); 527 /* Read again to ensure writing. */ 528 GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL); 529 530 gmac = GMC_PAUSE_ON; 531 if (((mii->mii_media_active & IFM_GMASK) & 532 (IFM_FLAG0 | IFM_FLAG1)) == 0) 533 gmac = GMC_PAUSE_OFF; 534 /* Diable pause for 10/100 Mbps in half-duplex mode. */ 535 if ((((mii->mii_media_active & IFM_GMASK) & IFM_FDX) == 0) && 536 (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX || 537 IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T)) 538 gmac = GMC_PAUSE_OFF; 539 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), gmac); 540 541 /* Enable PHY interrupt for FIFO underrun/overflow. */ 542 msk_phy_writereg(sc_if, PHY_ADDR_MARV, 543 PHY_MARV_INT_MASK, PHY_M_IS_FIFO_ERROR); 544 } else { 545 /* 546 * Link state changed to down. 547 * Disable PHY interrupts. 548 */ 549 msk_phy_writereg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_MASK, 0); 550 /* Disable Rx/Tx MAC. */ 551 gmac = GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL); 552 gmac &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA); 553 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, gmac); 554 /* Read again to ensure writing. */ 555 GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL); 556 } 557 558 MSK_IF_UNLOCK(sc_if); 559 } 560 561 static void 562 msk_rxfilter(struct msk_if_softc *sc_if) 563 { 564 struct msk_softc *sc; 565 struct ifnet *ifp; 566 struct ifmultiaddr *ifma; 567 uint32_t mchash[2]; 568 uint32_t crc; 569 uint16_t mode; 570 571 sc = sc_if->msk_softc; 572 573 MSK_IF_LOCK_ASSERT(sc_if); 574 575 ifp = sc_if->msk_ifp; 576 577 bzero(mchash, sizeof(mchash)); 578 mode = GMAC_READ_2(sc, sc_if->msk_port, GM_RX_CTRL); 579 if ((ifp->if_flags & IFF_PROMISC) != 0) 580 mode &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA); 581 else if ((ifp->if_flags & IFF_ALLMULTI) != 0) { 582 mode |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA; 583 mchash[0] = 0xffff; 584 mchash[1] = 0xffff; 585 } else { 586 mode |= GM_RXCR_UCF_ENA; 587 IF_ADDR_LOCK(ifp); 588 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 589 if (ifma->ifma_addr->sa_family != AF_LINK) 590 continue; 591 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *) 592 ifma->ifma_addr), ETHER_ADDR_LEN); 593 /* Just want the 6 least significant bits. */ 594 crc &= 0x3f; 595 /* Set the corresponding bit in the hash table. */ 596 mchash[crc >> 5] |= 1 << (crc & 0x1f); 597 } 598 IF_ADDR_UNLOCK(ifp); 599 if (mchash[0] != 0 || mchash[1] != 0) 600 mode |= GM_RXCR_MCF_ENA; 601 } 602 603 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H1, 604 mchash[0] & 0xffff); 605 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H2, 606 (mchash[0] >> 16) & 0xffff); 607 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H3, 608 mchash[1] & 0xffff); 609 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H4, 610 (mchash[1] >> 16) & 0xffff); 611 GMAC_WRITE_2(sc, sc_if->msk_port, GM_RX_CTRL, mode); 612 } 613 614 static void 615 msk_setvlan(struct msk_if_softc *sc_if, struct ifnet *ifp) 616 { 617 struct msk_softc *sc; 618 619 sc = sc_if->msk_softc; 620 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) { 621 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), 622 RX_VLAN_STRIP_ON); 623 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 624 TX_VLAN_TAG_ON); 625 } else { 626 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), 627 RX_VLAN_STRIP_OFF); 628 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 629 TX_VLAN_TAG_OFF); 630 } 631 } 632 633 static int 634 msk_init_rx_ring(struct msk_if_softc *sc_if) 635 { 636 struct msk_ring_data *rd; 637 struct msk_rxdesc *rxd; 638 int i, prod; 639 640 MSK_IF_LOCK_ASSERT(sc_if); 641 642 sc_if->msk_cdata.msk_rx_cons = 0; 643 sc_if->msk_cdata.msk_rx_prod = 0; 644 sc_if->msk_cdata.msk_rx_putwm = MSK_PUT_WM; 645 646 rd = &sc_if->msk_rdata; 647 bzero(rd->msk_rx_ring, sizeof(struct msk_rx_desc) * MSK_RX_RING_CNT); 648 prod = sc_if->msk_cdata.msk_rx_prod; 649 for (i = 0; i < MSK_RX_RING_CNT; i++) { 650 rxd = &sc_if->msk_cdata.msk_rxdesc[prod]; 651 rxd->rx_m = NULL; 652 rxd->rx_le = &rd->msk_rx_ring[prod]; 653 if (msk_newbuf(sc_if, prod) != 0) 654 return (ENOBUFS); 655 MSK_INC(prod, MSK_RX_RING_CNT); 656 } 657 658 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_ring_tag, 659 sc_if->msk_cdata.msk_rx_ring_map, 660 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 661 662 /* Update prefetch unit. */ 663 sc_if->msk_cdata.msk_rx_prod = MSK_RX_RING_CNT - 1; 664 CSR_WRITE_2(sc_if->msk_softc, 665 Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_PUT_IDX_REG), 666 sc_if->msk_cdata.msk_rx_prod); 667 668 return (0); 669 } 670 671 static int 672 msk_init_jumbo_rx_ring(struct msk_if_softc *sc_if) 673 { 674 struct msk_ring_data *rd; 675 struct msk_rxdesc *rxd; 676 int i, prod; 677 678 MSK_IF_LOCK_ASSERT(sc_if); 679 680 sc_if->msk_cdata.msk_rx_cons = 0; 681 sc_if->msk_cdata.msk_rx_prod = 0; 682 sc_if->msk_cdata.msk_rx_putwm = MSK_PUT_WM; 683 684 rd = &sc_if->msk_rdata; 685 bzero(rd->msk_jumbo_rx_ring, 686 sizeof(struct msk_rx_desc) * MSK_JUMBO_RX_RING_CNT); 687 prod = sc_if->msk_cdata.msk_rx_prod; 688 for (i = 0; i < MSK_JUMBO_RX_RING_CNT; i++) { 689 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[prod]; 690 rxd->rx_m = NULL; 691 rxd->rx_le = &rd->msk_jumbo_rx_ring[prod]; 692 if (msk_jumbo_newbuf(sc_if, prod) != 0) 693 return (ENOBUFS); 694 MSK_INC(prod, MSK_JUMBO_RX_RING_CNT); 695 } 696 697 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 698 sc_if->msk_cdata.msk_jumbo_rx_ring_map, 699 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 700 701 sc_if->msk_cdata.msk_rx_prod = MSK_JUMBO_RX_RING_CNT - 1; 702 CSR_WRITE_2(sc_if->msk_softc, 703 Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_PUT_IDX_REG), 704 sc_if->msk_cdata.msk_rx_prod); 705 706 return (0); 707 } 708 709 static void 710 msk_init_tx_ring(struct msk_if_softc *sc_if) 711 { 712 struct msk_ring_data *rd; 713 struct msk_txdesc *txd; 714 int i; 715 716 sc_if->msk_cdata.msk_tso_mtu = 0; 717 sc_if->msk_cdata.msk_tx_prod = 0; 718 sc_if->msk_cdata.msk_tx_cons = 0; 719 sc_if->msk_cdata.msk_tx_cnt = 0; 720 721 rd = &sc_if->msk_rdata; 722 bzero(rd->msk_tx_ring, sizeof(struct msk_tx_desc) * MSK_TX_RING_CNT); 723 for (i = 0; i < MSK_TX_RING_CNT; i++) { 724 txd = &sc_if->msk_cdata.msk_txdesc[i]; 725 txd->tx_m = NULL; 726 txd->tx_le = &rd->msk_tx_ring[i]; 727 } 728 729 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_ring_tag, 730 sc_if->msk_cdata.msk_tx_ring_map, 731 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 732 } 733 734 static __inline void 735 msk_discard_rxbuf(struct msk_if_softc *sc_if, int idx) 736 { 737 struct msk_rx_desc *rx_le; 738 struct msk_rxdesc *rxd; 739 struct mbuf *m; 740 741 rxd = &sc_if->msk_cdata.msk_rxdesc[idx]; 742 m = rxd->rx_m; 743 rx_le = rxd->rx_le; 744 rx_le->msk_control = htole32(m->m_len | OP_PACKET | HW_OWNER); 745 } 746 747 static __inline void 748 msk_discard_jumbo_rxbuf(struct msk_if_softc *sc_if, int idx) 749 { 750 struct msk_rx_desc *rx_le; 751 struct msk_rxdesc *rxd; 752 struct mbuf *m; 753 754 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[idx]; 755 m = rxd->rx_m; 756 rx_le = rxd->rx_le; 757 rx_le->msk_control = htole32(m->m_len | OP_PACKET | HW_OWNER); 758 } 759 760 static int 761 msk_newbuf(struct msk_if_softc *sc_if, int idx) 762 { 763 struct msk_rx_desc *rx_le; 764 struct msk_rxdesc *rxd; 765 struct mbuf *m; 766 bus_dma_segment_t segs[1]; 767 bus_dmamap_t map; 768 int nsegs; 769 770 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 771 if (m == NULL) 772 return (ENOBUFS); 773 774 m->m_len = m->m_pkthdr.len = MCLBYTES; 775 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) == 0) 776 m_adj(m, ETHER_ALIGN); 777 #ifndef __NO_STRICT_ALIGNMENT 778 else 779 m_adj(m, MSK_RX_BUF_ALIGN); 780 #endif 781 782 if (bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_rx_tag, 783 sc_if->msk_cdata.msk_rx_sparemap, m, segs, &nsegs, 784 BUS_DMA_NOWAIT) != 0) { 785 m_freem(m); 786 return (ENOBUFS); 787 } 788 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 789 790 rxd = &sc_if->msk_cdata.msk_rxdesc[idx]; 791 if (rxd->rx_m != NULL) { 792 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_tag, rxd->rx_dmamap, 793 BUS_DMASYNC_POSTREAD); 794 bus_dmamap_unload(sc_if->msk_cdata.msk_rx_tag, rxd->rx_dmamap); 795 } 796 map = rxd->rx_dmamap; 797 rxd->rx_dmamap = sc_if->msk_cdata.msk_rx_sparemap; 798 sc_if->msk_cdata.msk_rx_sparemap = map; 799 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_tag, rxd->rx_dmamap, 800 BUS_DMASYNC_PREREAD); 801 rxd->rx_m = m; 802 rx_le = rxd->rx_le; 803 rx_le->msk_addr = htole32(MSK_ADDR_LO(segs[0].ds_addr)); 804 rx_le->msk_control = 805 htole32(segs[0].ds_len | OP_PACKET | HW_OWNER); 806 807 return (0); 808 } 809 810 static int 811 msk_jumbo_newbuf(struct msk_if_softc *sc_if, int idx) 812 { 813 struct msk_rx_desc *rx_le; 814 struct msk_rxdesc *rxd; 815 struct mbuf *m; 816 bus_dma_segment_t segs[1]; 817 bus_dmamap_t map; 818 int nsegs; 819 820 m = m_getjcl(M_DONTWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES); 821 if (m == NULL) 822 return (ENOBUFS); 823 if ((m->m_flags & M_EXT) == 0) { 824 m_freem(m); 825 return (ENOBUFS); 826 } 827 m->m_len = m->m_pkthdr.len = MJUM9BYTES; 828 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) == 0) 829 m_adj(m, ETHER_ALIGN); 830 #ifndef __NO_STRICT_ALIGNMENT 831 else 832 m_adj(m, MSK_RX_BUF_ALIGN); 833 #endif 834 835 if (bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_jumbo_rx_tag, 836 sc_if->msk_cdata.msk_jumbo_rx_sparemap, m, segs, &nsegs, 837 BUS_DMA_NOWAIT) != 0) { 838 m_freem(m); 839 return (ENOBUFS); 840 } 841 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 842 843 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[idx]; 844 if (rxd->rx_m != NULL) { 845 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_tag, 846 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 847 bus_dmamap_unload(sc_if->msk_cdata.msk_jumbo_rx_tag, 848 rxd->rx_dmamap); 849 } 850 map = rxd->rx_dmamap; 851 rxd->rx_dmamap = sc_if->msk_cdata.msk_jumbo_rx_sparemap; 852 sc_if->msk_cdata.msk_jumbo_rx_sparemap = map; 853 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_tag, rxd->rx_dmamap, 854 BUS_DMASYNC_PREREAD); 855 rxd->rx_m = m; 856 rx_le = rxd->rx_le; 857 rx_le->msk_addr = htole32(MSK_ADDR_LO(segs[0].ds_addr)); 858 rx_le->msk_control = 859 htole32(segs[0].ds_len | OP_PACKET | HW_OWNER); 860 861 return (0); 862 } 863 864 /* 865 * Set media options. 866 */ 867 static int 868 msk_mediachange(struct ifnet *ifp) 869 { 870 struct msk_if_softc *sc_if; 871 struct mii_data *mii; 872 873 sc_if = ifp->if_softc; 874 875 MSK_IF_LOCK(sc_if); 876 mii = device_get_softc(sc_if->msk_miibus); 877 mii_mediachg(mii); 878 MSK_IF_UNLOCK(sc_if); 879 880 return (0); 881 } 882 883 /* 884 * Report current media status. 885 */ 886 static void 887 msk_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 888 { 889 struct msk_if_softc *sc_if; 890 struct mii_data *mii; 891 892 sc_if = ifp->if_softc; 893 MSK_IF_LOCK(sc_if); 894 mii = device_get_softc(sc_if->msk_miibus); 895 896 mii_pollstat(mii); 897 MSK_IF_UNLOCK(sc_if); 898 ifmr->ifm_active = mii->mii_media_active; 899 ifmr->ifm_status = mii->mii_media_status; 900 } 901 902 static int 903 msk_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 904 { 905 struct msk_if_softc *sc_if; 906 struct ifreq *ifr; 907 struct mii_data *mii; 908 int error, mask; 909 910 sc_if = ifp->if_softc; 911 ifr = (struct ifreq *)data; 912 error = 0; 913 914 switch(command) { 915 case SIOCSIFMTU: 916 if (ifr->ifr_mtu > MSK_JUMBO_MTU || ifr->ifr_mtu < ETHERMIN) 917 error = EINVAL; 918 else if (ifp->if_mtu != ifr->ifr_mtu) { 919 if ((sc_if->msk_flags & MSK_FLAG_NOJUMBO) != 0 && 920 ifr->ifr_mtu > ETHERMTU) 921 error = EINVAL; 922 else { 923 MSK_IF_LOCK(sc_if); 924 ifp->if_mtu = ifr->ifr_mtu; 925 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 926 msk_init_locked(sc_if); 927 MSK_IF_UNLOCK(sc_if); 928 } 929 } 930 break; 931 case SIOCSIFFLAGS: 932 MSK_IF_LOCK(sc_if); 933 if ((ifp->if_flags & IFF_UP) != 0) { 934 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 935 if (((ifp->if_flags ^ sc_if->msk_if_flags) 936 & (IFF_PROMISC | IFF_ALLMULTI)) != 0) 937 msk_rxfilter(sc_if); 938 } else { 939 if (sc_if->msk_detach == 0) 940 msk_init_locked(sc_if); 941 } 942 } else { 943 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 944 msk_stop(sc_if); 945 } 946 sc_if->msk_if_flags = ifp->if_flags; 947 MSK_IF_UNLOCK(sc_if); 948 break; 949 case SIOCADDMULTI: 950 case SIOCDELMULTI: 951 MSK_IF_LOCK(sc_if); 952 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 953 msk_rxfilter(sc_if); 954 MSK_IF_UNLOCK(sc_if); 955 break; 956 case SIOCGIFMEDIA: 957 case SIOCSIFMEDIA: 958 mii = device_get_softc(sc_if->msk_miibus); 959 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 960 break; 961 case SIOCSIFCAP: 962 MSK_IF_LOCK(sc_if); 963 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 964 if ((mask & IFCAP_TXCSUM) != 0) { 965 ifp->if_capenable ^= IFCAP_TXCSUM; 966 if ((IFCAP_TXCSUM & ifp->if_capenable) != 0 && 967 (IFCAP_TXCSUM & ifp->if_capabilities) != 0) 968 ifp->if_hwassist |= MSK_CSUM_FEATURES; 969 else 970 ifp->if_hwassist &= ~MSK_CSUM_FEATURES; 971 } 972 if ((mask & IFCAP_VLAN_HWTAGGING) != 0) { 973 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 974 msk_setvlan(sc_if, ifp); 975 } 976 977 if ((mask & IFCAP_TSO4) != 0) { 978 ifp->if_capenable ^= IFCAP_TSO4; 979 if ((IFCAP_TSO4 & ifp->if_capenable) != 0 && 980 (IFCAP_TSO4 & ifp->if_capabilities) != 0) 981 ifp->if_hwassist |= CSUM_TSO; 982 else 983 ifp->if_hwassist &= ~CSUM_TSO; 984 } 985 if (ifp->if_mtu > ETHERMTU && 986 sc_if->msk_softc->msk_hw_id == CHIP_ID_YUKON_EC_U) { 987 /* 988 * In Yukon EC Ultra, TSO & checksum offload is not 989 * supported for jumbo frame. 990 */ 991 ifp->if_hwassist &= ~(MSK_CSUM_FEATURES | CSUM_TSO); 992 ifp->if_capenable &= ~(IFCAP_TSO4 | IFCAP_TXCSUM); 993 } 994 995 VLAN_CAPABILITIES(ifp); 996 MSK_IF_UNLOCK(sc_if); 997 break; 998 default: 999 error = ether_ioctl(ifp, command, data); 1000 break; 1001 } 1002 1003 return (error); 1004 } 1005 1006 static int 1007 mskc_probe(device_t dev) 1008 { 1009 struct msk_product *mp; 1010 uint16_t vendor, devid; 1011 int i; 1012 1013 vendor = pci_get_vendor(dev); 1014 devid = pci_get_device(dev); 1015 mp = msk_products; 1016 for (i = 0; i < sizeof(msk_products)/sizeof(msk_products[0]); 1017 i++, mp++) { 1018 if (vendor == mp->msk_vendorid && devid == mp->msk_deviceid) { 1019 device_set_desc(dev, mp->msk_name); 1020 return (BUS_PROBE_DEFAULT); 1021 } 1022 } 1023 1024 return (ENXIO); 1025 } 1026 1027 static int 1028 mskc_setup_rambuffer(struct msk_softc *sc) 1029 { 1030 int next; 1031 int i; 1032 1033 /* Get adapter SRAM size. */ 1034 sc->msk_ramsize = CSR_READ_1(sc, B2_E_0) * 4; 1035 if (bootverbose) 1036 device_printf(sc->msk_dev, 1037 "RAM buffer size : %dKB\n", sc->msk_ramsize); 1038 if (sc->msk_ramsize == 0) 1039 return (0); 1040 1041 sc->msk_pflags |= MSK_FLAG_RAMBUF; 1042 /* 1043 * Give receiver 2/3 of memory and round down to the multiple 1044 * of 1024. Tx/Rx RAM buffer size of Yukon II shoud be multiple 1045 * of 1024. 1046 */ 1047 sc->msk_rxqsize = rounddown((sc->msk_ramsize * 1024 * 2) / 3, 1024); 1048 sc->msk_txqsize = (sc->msk_ramsize * 1024) - sc->msk_rxqsize; 1049 for (i = 0, next = 0; i < sc->msk_num_port; i++) { 1050 sc->msk_rxqstart[i] = next; 1051 sc->msk_rxqend[i] = next + sc->msk_rxqsize - 1; 1052 next = sc->msk_rxqend[i] + 1; 1053 sc->msk_txqstart[i] = next; 1054 sc->msk_txqend[i] = next + sc->msk_txqsize - 1; 1055 next = sc->msk_txqend[i] + 1; 1056 if (bootverbose) { 1057 device_printf(sc->msk_dev, 1058 "Port %d : Rx Queue %dKB(0x%08x:0x%08x)\n", i, 1059 sc->msk_rxqsize / 1024, sc->msk_rxqstart[i], 1060 sc->msk_rxqend[i]); 1061 device_printf(sc->msk_dev, 1062 "Port %d : Tx Queue %dKB(0x%08x:0x%08x)\n", i, 1063 sc->msk_txqsize / 1024, sc->msk_txqstart[i], 1064 sc->msk_txqend[i]); 1065 } 1066 } 1067 1068 return (0); 1069 } 1070 1071 static void 1072 msk_phy_power(struct msk_softc *sc, int mode) 1073 { 1074 uint32_t val; 1075 int i; 1076 1077 switch (mode) { 1078 case MSK_PHY_POWERUP: 1079 /* Switch power to VCC (WA for VAUX problem). */ 1080 CSR_WRITE_1(sc, B0_POWER_CTRL, 1081 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON); 1082 /* Disable Core Clock Division, set Clock Select to 0. */ 1083 CSR_WRITE_4(sc, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS); 1084 1085 val = 0; 1086 if (sc->msk_hw_id == CHIP_ID_YUKON_XL && 1087 sc->msk_hw_rev > CHIP_REV_YU_XL_A1) { 1088 /* Enable bits are inverted. */ 1089 val = Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS | 1090 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS | 1091 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS; 1092 } 1093 /* 1094 * Enable PCI & Core Clock, enable clock gating for both Links. 1095 */ 1096 CSR_WRITE_1(sc, B2_Y2_CLK_GATE, val); 1097 1098 val = pci_read_config(sc->msk_dev, PCI_OUR_REG_1, 4); 1099 val &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD); 1100 if (sc->msk_hw_id == CHIP_ID_YUKON_XL && 1101 sc->msk_hw_rev > CHIP_REV_YU_XL_A1) { 1102 /* Deassert Low Power for 1st PHY. */ 1103 val |= PCI_Y2_PHY1_COMA; 1104 if (sc->msk_num_port > 1) 1105 val |= PCI_Y2_PHY2_COMA; 1106 } else if (sc->msk_hw_id == CHIP_ID_YUKON_EC_U) { 1107 uint32_t our; 1108 1109 CSR_WRITE_2(sc, B0_CTST, Y2_HW_WOL_ON); 1110 1111 /* Enable all clocks. */ 1112 pci_write_config(sc->msk_dev, PCI_OUR_REG_3, 0, 4); 1113 our = pci_read_config(sc->msk_dev, PCI_OUR_REG_4, 4); 1114 our &= (PCI_FORCE_ASPM_REQUEST|PCI_ASPM_GPHY_LINK_DOWN| 1115 PCI_ASPM_INT_FIFO_EMPTY|PCI_ASPM_CLKRUN_REQUEST); 1116 /* Set all bits to 0 except bits 15..12. */ 1117 pci_write_config(sc->msk_dev, PCI_OUR_REG_4, our, 4); 1118 /* Set to default value. */ 1119 pci_write_config(sc->msk_dev, PCI_OUR_REG_5, 0, 4); 1120 } 1121 /* Release PHY from PowerDown/COMA mode. */ 1122 pci_write_config(sc->msk_dev, PCI_OUR_REG_1, val, 4); 1123 for (i = 0; i < sc->msk_num_port; i++) { 1124 CSR_WRITE_2(sc, MR_ADDR(i, GMAC_LINK_CTRL), 1125 GMLC_RST_SET); 1126 CSR_WRITE_2(sc, MR_ADDR(i, GMAC_LINK_CTRL), 1127 GMLC_RST_CLR); 1128 } 1129 break; 1130 case MSK_PHY_POWERDOWN: 1131 val = pci_read_config(sc->msk_dev, PCI_OUR_REG_1, 4); 1132 val |= PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD; 1133 if (sc->msk_hw_id == CHIP_ID_YUKON_XL && 1134 sc->msk_hw_rev > CHIP_REV_YU_XL_A1) { 1135 val &= ~PCI_Y2_PHY1_COMA; 1136 if (sc->msk_num_port > 1) 1137 val &= ~PCI_Y2_PHY2_COMA; 1138 } 1139 pci_write_config(sc->msk_dev, PCI_OUR_REG_1, val, 4); 1140 1141 val = Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS | 1142 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS | 1143 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS; 1144 if (sc->msk_hw_id == CHIP_ID_YUKON_XL && 1145 sc->msk_hw_rev > CHIP_REV_YU_XL_A1) { 1146 /* Enable bits are inverted. */ 1147 val = 0; 1148 } 1149 /* 1150 * Disable PCI & Core Clock, disable clock gating for 1151 * both Links. 1152 */ 1153 CSR_WRITE_1(sc, B2_Y2_CLK_GATE, val); 1154 CSR_WRITE_1(sc, B0_POWER_CTRL, 1155 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_ON | PC_VCC_OFF); 1156 break; 1157 default: 1158 break; 1159 } 1160 } 1161 1162 static void 1163 mskc_reset(struct msk_softc *sc) 1164 { 1165 bus_addr_t addr; 1166 uint16_t status; 1167 uint32_t val; 1168 int i; 1169 1170 CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR); 1171 1172 /* Disable ASF. */ 1173 if (sc->msk_hw_id < CHIP_ID_YUKON_XL) { 1174 CSR_WRITE_4(sc, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET); 1175 CSR_WRITE_2(sc, B0_CTST, Y2_ASF_DISABLE); 1176 } 1177 /* 1178 * Since we disabled ASF, S/W reset is required for Power Management. 1179 */ 1180 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); 1181 CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR); 1182 1183 /* Clear all error bits in the PCI status register. */ 1184 status = pci_read_config(sc->msk_dev, PCIR_STATUS, 2); 1185 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON); 1186 1187 pci_write_config(sc->msk_dev, PCIR_STATUS, status | 1188 PCIM_STATUS_PERR | PCIM_STATUS_SERR | PCIM_STATUS_RMABORT | 1189 PCIM_STATUS_RTABORT | PCIM_STATUS_PERRREPORT, 2); 1190 CSR_WRITE_2(sc, B0_CTST, CS_MRST_CLR); 1191 1192 switch (sc->msk_bustype) { 1193 case MSK_PEX_BUS: 1194 /* Clear all PEX errors. */ 1195 CSR_PCI_WRITE_4(sc, PEX_UNC_ERR_STAT, 0xffffffff); 1196 val = CSR_PCI_READ_4(sc, PEX_UNC_ERR_STAT); 1197 if ((val & PEX_RX_OV) != 0) { 1198 sc->msk_intrmask &= ~Y2_IS_HW_ERR; 1199 sc->msk_intrhwemask &= ~Y2_IS_PCI_EXP; 1200 } 1201 break; 1202 case MSK_PCI_BUS: 1203 case MSK_PCIX_BUS: 1204 /* Set Cache Line Size to 2(8bytes) if configured to 0. */ 1205 val = pci_read_config(sc->msk_dev, PCIR_CACHELNSZ, 1); 1206 if (val == 0) 1207 pci_write_config(sc->msk_dev, PCIR_CACHELNSZ, 2, 1); 1208 if (sc->msk_bustype == MSK_PCIX_BUS) { 1209 /* Set Cache Line Size opt. */ 1210 val = pci_read_config(sc->msk_dev, PCI_OUR_REG_1, 4); 1211 val |= PCI_CLS_OPT; 1212 pci_write_config(sc->msk_dev, PCI_OUR_REG_1, val, 4); 1213 } 1214 break; 1215 } 1216 /* Set PHY power state. */ 1217 msk_phy_power(sc, MSK_PHY_POWERUP); 1218 1219 /* Reset GPHY/GMAC Control */ 1220 for (i = 0; i < sc->msk_num_port; i++) { 1221 /* GPHY Control reset. */ 1222 CSR_WRITE_4(sc, MR_ADDR(i, GPHY_CTRL), GPC_RST_SET); 1223 CSR_WRITE_4(sc, MR_ADDR(i, GPHY_CTRL), GPC_RST_CLR); 1224 /* GMAC Control reset. */ 1225 CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), GMC_RST_SET); 1226 CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), GMC_RST_CLR); 1227 CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), GMC_F_LOOPB_OFF); 1228 } 1229 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 1230 1231 /* LED On. */ 1232 CSR_WRITE_2(sc, B0_CTST, Y2_LED_STAT_ON); 1233 1234 /* Clear TWSI IRQ. */ 1235 CSR_WRITE_4(sc, B2_I2C_IRQ, I2C_CLR_IRQ); 1236 1237 /* Turn off hardware timer. */ 1238 CSR_WRITE_1(sc, B2_TI_CTRL, TIM_STOP); 1239 CSR_WRITE_1(sc, B2_TI_CTRL, TIM_CLR_IRQ); 1240 1241 /* Turn off descriptor polling. */ 1242 CSR_WRITE_1(sc, B28_DPT_CTRL, DPT_STOP); 1243 1244 /* Turn off time stamps. */ 1245 CSR_WRITE_1(sc, GMAC_TI_ST_CTRL, GMT_ST_STOP); 1246 CSR_WRITE_1(sc, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ); 1247 1248 /* Configure timeout values. */ 1249 for (i = 0; i < sc->msk_num_port; i++) { 1250 CSR_WRITE_2(sc, SELECT_RAM_BUFFER(i, B3_RI_CTRL), RI_RST_SET); 1251 CSR_WRITE_2(sc, SELECT_RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR); 1252 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_R1), 1253 MSK_RI_TO_53); 1254 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XA1), 1255 MSK_RI_TO_53); 1256 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XS1), 1257 MSK_RI_TO_53); 1258 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_R1), 1259 MSK_RI_TO_53); 1260 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XA1), 1261 MSK_RI_TO_53); 1262 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XS1), 1263 MSK_RI_TO_53); 1264 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_R2), 1265 MSK_RI_TO_53); 1266 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XA2), 1267 MSK_RI_TO_53); 1268 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XS2), 1269 MSK_RI_TO_53); 1270 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_R2), 1271 MSK_RI_TO_53); 1272 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XA2), 1273 MSK_RI_TO_53); 1274 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XS2), 1275 MSK_RI_TO_53); 1276 } 1277 1278 /* Disable all interrupts. */ 1279 CSR_WRITE_4(sc, B0_HWE_IMSK, 0); 1280 CSR_READ_4(sc, B0_HWE_IMSK); 1281 CSR_WRITE_4(sc, B0_IMSK, 0); 1282 CSR_READ_4(sc, B0_IMSK); 1283 1284 /* 1285 * On dual port PCI-X card, there is an problem where status 1286 * can be received out of order due to split transactions. 1287 */ 1288 if (sc->msk_bustype == MSK_PCIX_BUS && sc->msk_num_port > 1) { 1289 int pcix; 1290 uint16_t pcix_cmd; 1291 1292 if (pci_find_extcap(sc->msk_dev, PCIY_PCIX, &pcix) == 0) { 1293 pcix_cmd = pci_read_config(sc->msk_dev, pcix + 2, 2); 1294 /* Clear Max Outstanding Split Transactions. */ 1295 pcix_cmd &= ~0x70; 1296 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON); 1297 pci_write_config(sc->msk_dev, pcix + 2, pcix_cmd, 2); 1298 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 1299 } 1300 } 1301 if (sc->msk_bustype == MSK_PEX_BUS) { 1302 uint16_t v, width; 1303 1304 v = pci_read_config(sc->msk_dev, PEX_DEV_CTRL, 2); 1305 /* Change Max. Read Request Size to 4096 bytes. */ 1306 v &= ~PEX_DC_MAX_RRS_MSK; 1307 v |= PEX_DC_MAX_RD_RQ_SIZE(5); 1308 pci_write_config(sc->msk_dev, PEX_DEV_CTRL, v, 2); 1309 width = pci_read_config(sc->msk_dev, PEX_LNK_STAT, 2); 1310 width = (width & PEX_LS_LINK_WI_MSK) >> 4; 1311 v = pci_read_config(sc->msk_dev, PEX_LNK_CAP, 2); 1312 v = (v & PEX_LS_LINK_WI_MSK) >> 4; 1313 if (v != width) 1314 device_printf(sc->msk_dev, 1315 "negotiated width of link(x%d) != " 1316 "max. width of link(x%d)\n", width, v); 1317 } 1318 1319 /* Clear status list. */ 1320 bzero(sc->msk_stat_ring, 1321 sizeof(struct msk_stat_desc) * MSK_STAT_RING_CNT); 1322 sc->msk_stat_cons = 0; 1323 bus_dmamap_sync(sc->msk_stat_tag, sc->msk_stat_map, 1324 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1325 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_RST_SET); 1326 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_RST_CLR); 1327 /* Set the status list base address. */ 1328 addr = sc->msk_stat_ring_paddr; 1329 CSR_WRITE_4(sc, STAT_LIST_ADDR_LO, MSK_ADDR_LO(addr)); 1330 CSR_WRITE_4(sc, STAT_LIST_ADDR_HI, MSK_ADDR_HI(addr)); 1331 /* Set the status list last index. */ 1332 CSR_WRITE_2(sc, STAT_LAST_IDX, MSK_STAT_RING_CNT - 1); 1333 if (sc->msk_hw_id == CHIP_ID_YUKON_EC && 1334 sc->msk_hw_rev == CHIP_REV_YU_EC_A1) { 1335 /* WA for dev. #4.3 */ 1336 CSR_WRITE_2(sc, STAT_TX_IDX_TH, ST_TXTH_IDX_MASK); 1337 /* WA for dev. #4.18 */ 1338 CSR_WRITE_1(sc, STAT_FIFO_WM, 0x21); 1339 CSR_WRITE_1(sc, STAT_FIFO_ISR_WM, 0x07); 1340 } else { 1341 CSR_WRITE_2(sc, STAT_TX_IDX_TH, 0x0a); 1342 CSR_WRITE_1(sc, STAT_FIFO_WM, 0x10); 1343 if (sc->msk_hw_id == CHIP_ID_YUKON_XL && 1344 sc->msk_hw_rev == CHIP_REV_YU_XL_A0) 1345 CSR_WRITE_1(sc, STAT_FIFO_ISR_WM, 0x04); 1346 else 1347 CSR_WRITE_1(sc, STAT_FIFO_ISR_WM, 0x10); 1348 CSR_WRITE_4(sc, STAT_ISR_TIMER_INI, 0x0190); 1349 } 1350 /* 1351 * Use default value for STAT_ISR_TIMER_INI, STAT_LEV_TIMER_INI. 1352 */ 1353 CSR_WRITE_4(sc, STAT_TX_TIMER_INI, MSK_USECS(sc, 1000)); 1354 1355 /* Enable status unit. */ 1356 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_OP_ON); 1357 1358 CSR_WRITE_1(sc, STAT_TX_TIMER_CTRL, TIM_START); 1359 CSR_WRITE_1(sc, STAT_LEV_TIMER_CTRL, TIM_START); 1360 CSR_WRITE_1(sc, STAT_ISR_TIMER_CTRL, TIM_START); 1361 } 1362 1363 static int 1364 msk_probe(device_t dev) 1365 { 1366 struct msk_softc *sc; 1367 char desc[100]; 1368 1369 sc = device_get_softc(device_get_parent(dev)); 1370 /* 1371 * Not much to do here. We always know there will be 1372 * at least one GMAC present, and if there are two, 1373 * mskc_attach() will create a second device instance 1374 * for us. 1375 */ 1376 snprintf(desc, sizeof(desc), 1377 "Marvell Technology Group Ltd. %s Id 0x%02x Rev 0x%02x", 1378 model_name[sc->msk_hw_id - CHIP_ID_YUKON_XL], sc->msk_hw_id, 1379 sc->msk_hw_rev); 1380 device_set_desc_copy(dev, desc); 1381 1382 return (BUS_PROBE_DEFAULT); 1383 } 1384 1385 static int 1386 msk_attach(device_t dev) 1387 { 1388 struct msk_softc *sc; 1389 struct msk_if_softc *sc_if; 1390 struct ifnet *ifp; 1391 int i, port, error; 1392 uint8_t eaddr[6]; 1393 1394 if (dev == NULL) 1395 return (EINVAL); 1396 1397 error = 0; 1398 sc_if = device_get_softc(dev); 1399 sc = device_get_softc(device_get_parent(dev)); 1400 port = *(int *)device_get_ivars(dev); 1401 1402 sc_if->msk_if_dev = dev; 1403 sc_if->msk_port = port; 1404 sc_if->msk_softc = sc; 1405 sc_if->msk_flags = sc->msk_pflags; 1406 sc->msk_if[port] = sc_if; 1407 /* Setup Tx/Rx queue register offsets. */ 1408 if (port == MSK_PORT_A) { 1409 sc_if->msk_txq = Q_XA1; 1410 sc_if->msk_txsq = Q_XS1; 1411 sc_if->msk_rxq = Q_R1; 1412 } else { 1413 sc_if->msk_txq = Q_XA2; 1414 sc_if->msk_txsq = Q_XS2; 1415 sc_if->msk_rxq = Q_R2; 1416 } 1417 1418 callout_init_mtx(&sc_if->msk_tick_ch, &sc_if->msk_softc->msk_mtx, 0); 1419 TASK_INIT(&sc_if->msk_link_task, 0, msk_link_task, sc_if); 1420 msk_sysctl_node(sc_if); 1421 1422 /* Disable jumbo frame for Yukon FE. */ 1423 if (sc_if->msk_softc->msk_hw_id == CHIP_ID_YUKON_FE) 1424 sc_if->msk_flags |= MSK_FLAG_NOJUMBO; 1425 1426 if ((error = msk_txrx_dma_alloc(sc_if) != 0)) 1427 goto fail; 1428 msk_rx_dma_jalloc(sc_if); 1429 1430 ifp = sc_if->msk_ifp = if_alloc(IFT_ETHER); 1431 if (ifp == NULL) { 1432 device_printf(sc_if->msk_if_dev, "can not if_alloc()\n"); 1433 error = ENOSPC; 1434 goto fail; 1435 } 1436 ifp->if_softc = sc_if; 1437 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1438 ifp->if_mtu = ETHERMTU; 1439 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1440 /* 1441 * IFCAP_RXCSUM capability is intentionally disabled as the hardware 1442 * has serious bug in Rx checksum offload for all Yukon II family 1443 * hardware. It seems there is a workaround to make it work somtimes. 1444 * However, the workaround also have to check OP code sequences to 1445 * verify whether the OP code is correct. Sometimes it should compute 1446 * IP/TCP/UDP checksum in driver in order to verify correctness of 1447 * checksum computed by hardware. If you have to compute checksum 1448 * with software to verify the hardware's checksum why have hardware 1449 * compute the checksum? I think there is no reason to spend time to 1450 * make Rx checksum offload work on Yukon II hardware. 1451 */ 1452 ifp->if_capabilities = IFCAP_TXCSUM | IFCAP_TSO4; 1453 ifp->if_hwassist = MSK_CSUM_FEATURES | CSUM_TSO; 1454 ifp->if_capenable = ifp->if_capabilities; 1455 ifp->if_ioctl = msk_ioctl; 1456 ifp->if_start = msk_start; 1457 ifp->if_timer = 0; 1458 ifp->if_watchdog = NULL; 1459 ifp->if_init = msk_init; 1460 IFQ_SET_MAXLEN(&ifp->if_snd, MSK_TX_RING_CNT - 1); 1461 ifp->if_snd.ifq_drv_maxlen = MSK_TX_RING_CNT - 1; 1462 IFQ_SET_READY(&ifp->if_snd); 1463 1464 TASK_INIT(&sc_if->msk_tx_task, 1, msk_tx_task, ifp); 1465 1466 /* 1467 * Get station address for this interface. Note that 1468 * dual port cards actually come with three station 1469 * addresses: one for each port, plus an extra. The 1470 * extra one is used by the SysKonnect driver software 1471 * as a 'virtual' station address for when both ports 1472 * are operating in failover mode. Currently we don't 1473 * use this extra address. 1474 */ 1475 MSK_IF_LOCK(sc_if); 1476 for (i = 0; i < ETHER_ADDR_LEN; i++) 1477 eaddr[i] = CSR_READ_1(sc, B2_MAC_1 + (port * 8) + i); 1478 1479 /* 1480 * Call MI attach routine. Can't hold locks when calling into ether_*. 1481 */ 1482 MSK_IF_UNLOCK(sc_if); 1483 ether_ifattach(ifp, eaddr); 1484 MSK_IF_LOCK(sc_if); 1485 1486 /* 1487 * VLAN capability setup 1488 * Due to Tx checksum offload hardware bugs, msk(4) manually 1489 * computes checksum for short frames. For VLAN tagged frames 1490 * this workaround does not work so disable checksum offload 1491 * for VLAN interface. 1492 */ 1493 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING; 1494 ifp->if_capenable = ifp->if_capabilities; 1495 1496 /* 1497 * Tell the upper layer(s) we support long frames. 1498 * Must appear after the call to ether_ifattach() because 1499 * ether_ifattach() sets ifi_hdrlen to the default value. 1500 */ 1501 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1502 1503 /* 1504 * Do miibus setup. 1505 */ 1506 MSK_IF_UNLOCK(sc_if); 1507 error = mii_phy_probe(dev, &sc_if->msk_miibus, msk_mediachange, 1508 msk_mediastatus); 1509 if (error != 0) { 1510 device_printf(sc_if->msk_if_dev, "no PHY found!\n"); 1511 ether_ifdetach(ifp); 1512 error = ENXIO; 1513 goto fail; 1514 } 1515 1516 fail: 1517 if (error != 0) { 1518 /* Access should be ok even though lock has been dropped */ 1519 sc->msk_if[port] = NULL; 1520 msk_detach(dev); 1521 } 1522 1523 return (error); 1524 } 1525 1526 /* 1527 * Attach the interface. Allocate softc structures, do ifmedia 1528 * setup and ethernet/BPF attach. 1529 */ 1530 static int 1531 mskc_attach(device_t dev) 1532 { 1533 struct msk_softc *sc; 1534 int error, msic, msir, *port, reg; 1535 1536 sc = device_get_softc(dev); 1537 sc->msk_dev = dev; 1538 mtx_init(&sc->msk_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1539 MTX_DEF); 1540 1541 /* 1542 * Map control/status registers. 1543 */ 1544 pci_enable_busmaster(dev); 1545 1546 /* Allocate I/O resource */ 1547 #ifdef MSK_USEIOSPACE 1548 sc->msk_res_spec = msk_res_spec_io; 1549 #else 1550 sc->msk_res_spec = msk_res_spec_mem; 1551 #endif 1552 sc->msk_irq_spec = msk_irq_spec_legacy; 1553 error = bus_alloc_resources(dev, sc->msk_res_spec, sc->msk_res); 1554 if (error) { 1555 if (sc->msk_res_spec == msk_res_spec_mem) 1556 sc->msk_res_spec = msk_res_spec_io; 1557 else 1558 sc->msk_res_spec = msk_res_spec_mem; 1559 error = bus_alloc_resources(dev, sc->msk_res_spec, sc->msk_res); 1560 if (error) { 1561 device_printf(dev, "couldn't allocate %s resources\n", 1562 sc->msk_res_spec == msk_res_spec_mem ? "memory" : 1563 "I/O"); 1564 mtx_destroy(&sc->msk_mtx); 1565 return (ENXIO); 1566 } 1567 } 1568 1569 CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR); 1570 sc->msk_hw_id = CSR_READ_1(sc, B2_CHIP_ID); 1571 sc->msk_hw_rev = (CSR_READ_1(sc, B2_MAC_CFG) >> 4) & 0x0f; 1572 /* Bail out if chip is not recognized. */ 1573 if (sc->msk_hw_id < CHIP_ID_YUKON_XL || 1574 sc->msk_hw_id > CHIP_ID_YUKON_FE) { 1575 device_printf(dev, "unknown device: id=0x%02x, rev=0x%02x\n", 1576 sc->msk_hw_id, sc->msk_hw_rev); 1577 mtx_destroy(&sc->msk_mtx); 1578 return (ENXIO); 1579 } 1580 1581 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 1582 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 1583 OID_AUTO, "process_limit", CTLTYPE_INT | CTLFLAG_RW, 1584 &sc->msk_process_limit, 0, sysctl_hw_msk_proc_limit, "I", 1585 "max number of Rx events to process"); 1586 1587 sc->msk_process_limit = MSK_PROC_DEFAULT; 1588 error = resource_int_value(device_get_name(dev), device_get_unit(dev), 1589 "process_limit", &sc->msk_process_limit); 1590 if (error == 0) { 1591 if (sc->msk_process_limit < MSK_PROC_MIN || 1592 sc->msk_process_limit > MSK_PROC_MAX) { 1593 device_printf(dev, "process_limit value out of range; " 1594 "using default: %d\n", MSK_PROC_DEFAULT); 1595 sc->msk_process_limit = MSK_PROC_DEFAULT; 1596 } 1597 } 1598 1599 /* Soft reset. */ 1600 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); 1601 CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR); 1602 sc->msk_pmd = CSR_READ_1(sc, B2_PMD_TYP); 1603 if (sc->msk_pmd == 'L' || sc->msk_pmd == 'S') 1604 sc->msk_coppertype = 0; 1605 else 1606 sc->msk_coppertype = 1; 1607 /* Check number of MACs. */ 1608 sc->msk_num_port = 1; 1609 if ((CSR_READ_1(sc, B2_Y2_HW_RES) & CFG_DUAL_MAC_MSK) == 1610 CFG_DUAL_MAC_MSK) { 1611 if (!(CSR_READ_1(sc, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC)) 1612 sc->msk_num_port++; 1613 } 1614 1615 /* Check bus type. */ 1616 if (pci_find_extcap(sc->msk_dev, PCIY_EXPRESS, ®) == 0) 1617 sc->msk_bustype = MSK_PEX_BUS; 1618 else if (pci_find_extcap(sc->msk_dev, PCIY_PCIX, ®) == 0) 1619 sc->msk_bustype = MSK_PCIX_BUS; 1620 else 1621 sc->msk_bustype = MSK_PCI_BUS; 1622 1623 switch (sc->msk_hw_id) { 1624 case CHIP_ID_YUKON_EC: 1625 case CHIP_ID_YUKON_EC_U: 1626 sc->msk_clock = 125; /* 125 Mhz */ 1627 break; 1628 case CHIP_ID_YUKON_FE: 1629 sc->msk_clock = 100; /* 100 Mhz */ 1630 break; 1631 case CHIP_ID_YUKON_XL: 1632 sc->msk_clock = 156; /* 156 Mhz */ 1633 break; 1634 default: 1635 sc->msk_clock = 156; /* 156 Mhz */ 1636 break; 1637 } 1638 1639 /* Allocate IRQ resources. */ 1640 msic = pci_msi_count(dev); 1641 if (bootverbose) 1642 device_printf(dev, "MSI count : %d\n", msic); 1643 /* 1644 * The Yukon II reports it can handle two messages, one for each 1645 * possible port. We go ahead and allocate two messages and only 1646 * setup a handler for both if we have a dual port card. 1647 * 1648 * XXX: I haven't untangled the interrupt handler to handle dual 1649 * port cards with separate MSI messages, so for now I disable MSI 1650 * on dual port cards. 1651 */ 1652 if (legacy_intr != 0) 1653 msi_disable = 1; 1654 if (msi_disable == 0) { 1655 switch (msic) { 1656 case 2: 1657 case 1: /* 88E8058 reports 1 MSI message */ 1658 msir = msic; 1659 if (sc->msk_num_port == 1 && 1660 pci_alloc_msi(dev, &msir) == 0) { 1661 if (msic == msir) { 1662 sc->msk_msi = 1; 1663 sc->msk_irq_spec = msic == 2 ? 1664 msk_irq_spec_msi2 : 1665 msk_irq_spec_msi; 1666 } else 1667 pci_release_msi(dev); 1668 } 1669 break; 1670 default: 1671 device_printf(dev, 1672 "Unexpected number of MSI messages : %d\n", msic); 1673 break; 1674 } 1675 } 1676 1677 error = bus_alloc_resources(dev, sc->msk_irq_spec, sc->msk_irq); 1678 if (error) { 1679 device_printf(dev, "couldn't allocate IRQ resources\n"); 1680 goto fail; 1681 } 1682 1683 if ((error = msk_status_dma_alloc(sc)) != 0) 1684 goto fail; 1685 1686 /* Set base interrupt mask. */ 1687 sc->msk_intrmask = Y2_IS_HW_ERR | Y2_IS_STAT_BMU; 1688 sc->msk_intrhwemask = Y2_IS_TIST_OV | Y2_IS_MST_ERR | 1689 Y2_IS_IRQ_STAT | Y2_IS_PCI_EXP | Y2_IS_PCI_NEXP; 1690 1691 /* Reset the adapter. */ 1692 mskc_reset(sc); 1693 1694 if ((error = mskc_setup_rambuffer(sc)) != 0) 1695 goto fail; 1696 1697 sc->msk_devs[MSK_PORT_A] = device_add_child(dev, "msk", -1); 1698 if (sc->msk_devs[MSK_PORT_A] == NULL) { 1699 device_printf(dev, "failed to add child for PORT_A\n"); 1700 error = ENXIO; 1701 goto fail; 1702 } 1703 port = malloc(sizeof(int), M_DEVBUF, M_WAITOK); 1704 if (port == NULL) { 1705 device_printf(dev, "failed to allocate memory for " 1706 "ivars of PORT_A\n"); 1707 error = ENXIO; 1708 goto fail; 1709 } 1710 *port = MSK_PORT_A; 1711 device_set_ivars(sc->msk_devs[MSK_PORT_A], port); 1712 1713 if (sc->msk_num_port > 1) { 1714 sc->msk_devs[MSK_PORT_B] = device_add_child(dev, "msk", -1); 1715 if (sc->msk_devs[MSK_PORT_B] == NULL) { 1716 device_printf(dev, "failed to add child for PORT_B\n"); 1717 error = ENXIO; 1718 goto fail; 1719 } 1720 port = malloc(sizeof(int), M_DEVBUF, M_WAITOK); 1721 if (port == NULL) { 1722 device_printf(dev, "failed to allocate memory for " 1723 "ivars of PORT_B\n"); 1724 error = ENXIO; 1725 goto fail; 1726 } 1727 *port = MSK_PORT_B; 1728 device_set_ivars(sc->msk_devs[MSK_PORT_B], port); 1729 } 1730 1731 error = bus_generic_attach(dev); 1732 if (error) { 1733 device_printf(dev, "failed to attach port(s)\n"); 1734 goto fail; 1735 } 1736 1737 /* Hook interrupt last to avoid having to lock softc. */ 1738 if (legacy_intr) 1739 error = bus_setup_intr(dev, sc->msk_irq[0], INTR_TYPE_NET | 1740 INTR_MPSAFE, NULL, msk_legacy_intr, sc, 1741 &sc->msk_intrhand[0]); 1742 else { 1743 TASK_INIT(&sc->msk_int_task, 0, msk_int_task, sc); 1744 sc->msk_tq = taskqueue_create_fast("msk_taskq", M_WAITOK, 1745 taskqueue_thread_enqueue, &sc->msk_tq); 1746 taskqueue_start_threads(&sc->msk_tq, 1, PI_NET, "%s taskq", 1747 device_get_nameunit(sc->msk_dev)); 1748 error = bus_setup_intr(dev, sc->msk_irq[0], INTR_TYPE_NET | 1749 INTR_MPSAFE, msk_intr, NULL, sc, &sc->msk_intrhand[0]); 1750 } 1751 1752 if (error != 0) { 1753 device_printf(dev, "couldn't set up interrupt handler\n"); 1754 if (legacy_intr == 0) 1755 taskqueue_free(sc->msk_tq); 1756 sc->msk_tq = NULL; 1757 goto fail; 1758 } 1759 fail: 1760 if (error != 0) 1761 mskc_detach(dev); 1762 1763 return (error); 1764 } 1765 1766 /* 1767 * Shutdown hardware and free up resources. This can be called any 1768 * time after the mutex has been initialized. It is called in both 1769 * the error case in attach and the normal detach case so it needs 1770 * to be careful about only freeing resources that have actually been 1771 * allocated. 1772 */ 1773 static int 1774 msk_detach(device_t dev) 1775 { 1776 struct msk_softc *sc; 1777 struct msk_if_softc *sc_if; 1778 struct ifnet *ifp; 1779 1780 sc_if = device_get_softc(dev); 1781 KASSERT(mtx_initialized(&sc_if->msk_softc->msk_mtx), 1782 ("msk mutex not initialized in msk_detach")); 1783 MSK_IF_LOCK(sc_if); 1784 1785 ifp = sc_if->msk_ifp; 1786 if (device_is_attached(dev)) { 1787 /* XXX */ 1788 sc_if->msk_detach = 1; 1789 msk_stop(sc_if); 1790 /* Can't hold locks while calling detach. */ 1791 MSK_IF_UNLOCK(sc_if); 1792 callout_drain(&sc_if->msk_tick_ch); 1793 taskqueue_drain(taskqueue_fast, &sc_if->msk_tx_task); 1794 taskqueue_drain(taskqueue_swi, &sc_if->msk_link_task); 1795 ether_ifdetach(ifp); 1796 MSK_IF_LOCK(sc_if); 1797 } 1798 1799 /* 1800 * We're generally called from mskc_detach() which is using 1801 * device_delete_child() to get to here. It's already trashed 1802 * miibus for us, so don't do it here or we'll panic. 1803 * 1804 * if (sc_if->msk_miibus != NULL) { 1805 * device_delete_child(dev, sc_if->msk_miibus); 1806 * sc_if->msk_miibus = NULL; 1807 * } 1808 */ 1809 1810 msk_rx_dma_jfree(sc_if); 1811 msk_txrx_dma_free(sc_if); 1812 bus_generic_detach(dev); 1813 1814 if (ifp) 1815 if_free(ifp); 1816 sc = sc_if->msk_softc; 1817 sc->msk_if[sc_if->msk_port] = NULL; 1818 MSK_IF_UNLOCK(sc_if); 1819 1820 return (0); 1821 } 1822 1823 static int 1824 mskc_detach(device_t dev) 1825 { 1826 struct msk_softc *sc; 1827 1828 sc = device_get_softc(dev); 1829 KASSERT(mtx_initialized(&sc->msk_mtx), ("msk mutex not initialized")); 1830 1831 if (device_is_alive(dev)) { 1832 if (sc->msk_devs[MSK_PORT_A] != NULL) { 1833 free(device_get_ivars(sc->msk_devs[MSK_PORT_A]), 1834 M_DEVBUF); 1835 device_delete_child(dev, sc->msk_devs[MSK_PORT_A]); 1836 } 1837 if (sc->msk_devs[MSK_PORT_B] != NULL) { 1838 free(device_get_ivars(sc->msk_devs[MSK_PORT_B]), 1839 M_DEVBUF); 1840 device_delete_child(dev, sc->msk_devs[MSK_PORT_B]); 1841 } 1842 bus_generic_detach(dev); 1843 } 1844 1845 /* Disable all interrupts. */ 1846 CSR_WRITE_4(sc, B0_IMSK, 0); 1847 CSR_READ_4(sc, B0_IMSK); 1848 CSR_WRITE_4(sc, B0_HWE_IMSK, 0); 1849 CSR_READ_4(sc, B0_HWE_IMSK); 1850 1851 /* LED Off. */ 1852 CSR_WRITE_2(sc, B0_CTST, Y2_LED_STAT_OFF); 1853 1854 /* Put hardware reset. */ 1855 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); 1856 1857 msk_status_dma_free(sc); 1858 1859 if (legacy_intr == 0 && sc->msk_tq != NULL) { 1860 taskqueue_drain(sc->msk_tq, &sc->msk_int_task); 1861 taskqueue_free(sc->msk_tq); 1862 sc->msk_tq = NULL; 1863 } 1864 if (sc->msk_intrhand[0]) { 1865 bus_teardown_intr(dev, sc->msk_irq[0], sc->msk_intrhand[0]); 1866 sc->msk_intrhand[0] = NULL; 1867 } 1868 if (sc->msk_intrhand[1]) { 1869 bus_teardown_intr(dev, sc->msk_irq[0], sc->msk_intrhand[0]); 1870 sc->msk_intrhand[1] = NULL; 1871 } 1872 bus_release_resources(dev, sc->msk_irq_spec, sc->msk_irq); 1873 if (sc->msk_msi) 1874 pci_release_msi(dev); 1875 bus_release_resources(dev, sc->msk_res_spec, sc->msk_res); 1876 mtx_destroy(&sc->msk_mtx); 1877 1878 return (0); 1879 } 1880 1881 struct msk_dmamap_arg { 1882 bus_addr_t msk_busaddr; 1883 }; 1884 1885 static void 1886 msk_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1887 { 1888 struct msk_dmamap_arg *ctx; 1889 1890 if (error != 0) 1891 return; 1892 ctx = arg; 1893 ctx->msk_busaddr = segs[0].ds_addr; 1894 } 1895 1896 /* Create status DMA region. */ 1897 static int 1898 msk_status_dma_alloc(struct msk_softc *sc) 1899 { 1900 struct msk_dmamap_arg ctx; 1901 int error; 1902 1903 error = bus_dma_tag_create( 1904 bus_get_dma_tag(sc->msk_dev), /* parent */ 1905 MSK_STAT_ALIGN, 0, /* alignment, boundary */ 1906 BUS_SPACE_MAXADDR, /* lowaddr */ 1907 BUS_SPACE_MAXADDR, /* highaddr */ 1908 NULL, NULL, /* filter, filterarg */ 1909 MSK_STAT_RING_SZ, /* maxsize */ 1910 1, /* nsegments */ 1911 MSK_STAT_RING_SZ, /* maxsegsize */ 1912 0, /* flags */ 1913 NULL, NULL, /* lockfunc, lockarg */ 1914 &sc->msk_stat_tag); 1915 if (error != 0) { 1916 device_printf(sc->msk_dev, 1917 "failed to create status DMA tag\n"); 1918 return (error); 1919 } 1920 1921 /* Allocate DMA'able memory and load the DMA map for status ring. */ 1922 error = bus_dmamem_alloc(sc->msk_stat_tag, 1923 (void **)&sc->msk_stat_ring, BUS_DMA_WAITOK | BUS_DMA_COHERENT | 1924 BUS_DMA_ZERO, &sc->msk_stat_map); 1925 if (error != 0) { 1926 device_printf(sc->msk_dev, 1927 "failed to allocate DMA'able memory for status ring\n"); 1928 return (error); 1929 } 1930 1931 ctx.msk_busaddr = 0; 1932 error = bus_dmamap_load(sc->msk_stat_tag, 1933 sc->msk_stat_map, sc->msk_stat_ring, MSK_STAT_RING_SZ, 1934 msk_dmamap_cb, &ctx, 0); 1935 if (error != 0) { 1936 device_printf(sc->msk_dev, 1937 "failed to load DMA'able memory for status ring\n"); 1938 return (error); 1939 } 1940 sc->msk_stat_ring_paddr = ctx.msk_busaddr; 1941 1942 return (0); 1943 } 1944 1945 static void 1946 msk_status_dma_free(struct msk_softc *sc) 1947 { 1948 1949 /* Destroy status block. */ 1950 if (sc->msk_stat_tag) { 1951 if (sc->msk_stat_map) { 1952 bus_dmamap_unload(sc->msk_stat_tag, sc->msk_stat_map); 1953 if (sc->msk_stat_ring) { 1954 bus_dmamem_free(sc->msk_stat_tag, 1955 sc->msk_stat_ring, sc->msk_stat_map); 1956 sc->msk_stat_ring = NULL; 1957 } 1958 sc->msk_stat_map = NULL; 1959 } 1960 bus_dma_tag_destroy(sc->msk_stat_tag); 1961 sc->msk_stat_tag = NULL; 1962 } 1963 } 1964 1965 static int 1966 msk_txrx_dma_alloc(struct msk_if_softc *sc_if) 1967 { 1968 struct msk_dmamap_arg ctx; 1969 struct msk_txdesc *txd; 1970 struct msk_rxdesc *rxd; 1971 bus_size_t rxalign; 1972 int error, i; 1973 1974 /* Create parent DMA tag. */ 1975 /* 1976 * XXX 1977 * It seems that Yukon II supports full 64bits DMA operations. But 1978 * it needs two descriptors(list elements) for 64bits DMA operations. 1979 * Since we don't know what DMA address mappings(32bits or 64bits) 1980 * would be used in advance for each mbufs, we limits its DMA space 1981 * to be in range of 32bits address space. Otherwise, we should check 1982 * what DMA address is used and chain another descriptor for the 1983 * 64bits DMA operation. This also means descriptor ring size is 1984 * variable. Limiting DMA address to be in 32bit address space greatly 1985 * simplyfies descriptor handling and possibly would increase 1986 * performance a bit due to efficient handling of descriptors. 1987 * Apart from harassing checksum offloading mechanisms, it seems 1988 * it's really bad idea to use a seperate descriptor for 64bit 1989 * DMA operation to save small descriptor memory. Anyway, I've 1990 * never seen these exotic scheme on ethernet interface hardware. 1991 */ 1992 error = bus_dma_tag_create( 1993 bus_get_dma_tag(sc_if->msk_if_dev), /* parent */ 1994 1, 0, /* alignment, boundary */ 1995 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1996 BUS_SPACE_MAXADDR, /* highaddr */ 1997 NULL, NULL, /* filter, filterarg */ 1998 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1999 0, /* nsegments */ 2000 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 2001 0, /* flags */ 2002 NULL, NULL, /* lockfunc, lockarg */ 2003 &sc_if->msk_cdata.msk_parent_tag); 2004 if (error != 0) { 2005 device_printf(sc_if->msk_if_dev, 2006 "failed to create parent DMA tag\n"); 2007 goto fail; 2008 } 2009 /* Create tag for Tx ring. */ 2010 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2011 MSK_RING_ALIGN, 0, /* alignment, boundary */ 2012 BUS_SPACE_MAXADDR, /* lowaddr */ 2013 BUS_SPACE_MAXADDR, /* highaddr */ 2014 NULL, NULL, /* filter, filterarg */ 2015 MSK_TX_RING_SZ, /* maxsize */ 2016 1, /* nsegments */ 2017 MSK_TX_RING_SZ, /* maxsegsize */ 2018 0, /* flags */ 2019 NULL, NULL, /* lockfunc, lockarg */ 2020 &sc_if->msk_cdata.msk_tx_ring_tag); 2021 if (error != 0) { 2022 device_printf(sc_if->msk_if_dev, 2023 "failed to create Tx ring DMA tag\n"); 2024 goto fail; 2025 } 2026 2027 /* Create tag for Rx ring. */ 2028 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2029 MSK_RING_ALIGN, 0, /* alignment, boundary */ 2030 BUS_SPACE_MAXADDR, /* lowaddr */ 2031 BUS_SPACE_MAXADDR, /* highaddr */ 2032 NULL, NULL, /* filter, filterarg */ 2033 MSK_RX_RING_SZ, /* maxsize */ 2034 1, /* nsegments */ 2035 MSK_RX_RING_SZ, /* maxsegsize */ 2036 0, /* flags */ 2037 NULL, NULL, /* lockfunc, lockarg */ 2038 &sc_if->msk_cdata.msk_rx_ring_tag); 2039 if (error != 0) { 2040 device_printf(sc_if->msk_if_dev, 2041 "failed to create Rx ring DMA tag\n"); 2042 goto fail; 2043 } 2044 2045 /* Create tag for Tx buffers. */ 2046 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2047 1, 0, /* alignment, boundary */ 2048 BUS_SPACE_MAXADDR, /* lowaddr */ 2049 BUS_SPACE_MAXADDR, /* highaddr */ 2050 NULL, NULL, /* filter, filterarg */ 2051 MSK_TSO_MAXSIZE, /* maxsize */ 2052 MSK_MAXTXSEGS, /* nsegments */ 2053 MSK_TSO_MAXSGSIZE, /* maxsegsize */ 2054 0, /* flags */ 2055 NULL, NULL, /* lockfunc, lockarg */ 2056 &sc_if->msk_cdata.msk_tx_tag); 2057 if (error != 0) { 2058 device_printf(sc_if->msk_if_dev, 2059 "failed to create Tx DMA tag\n"); 2060 goto fail; 2061 } 2062 2063 rxalign = 1; 2064 /* 2065 * Workaround hardware hang which seems to happen when Rx buffer 2066 * is not aligned on multiple of FIFO word(8 bytes). 2067 */ 2068 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) != 0) 2069 rxalign = MSK_RX_BUF_ALIGN; 2070 /* Create tag for Rx buffers. */ 2071 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2072 rxalign, 0, /* alignment, boundary */ 2073 BUS_SPACE_MAXADDR, /* lowaddr */ 2074 BUS_SPACE_MAXADDR, /* highaddr */ 2075 NULL, NULL, /* filter, filterarg */ 2076 MCLBYTES, /* maxsize */ 2077 1, /* nsegments */ 2078 MCLBYTES, /* maxsegsize */ 2079 0, /* flags */ 2080 NULL, NULL, /* lockfunc, lockarg */ 2081 &sc_if->msk_cdata.msk_rx_tag); 2082 if (error != 0) { 2083 device_printf(sc_if->msk_if_dev, 2084 "failed to create Rx DMA tag\n"); 2085 goto fail; 2086 } 2087 2088 /* Allocate DMA'able memory and load the DMA map for Tx ring. */ 2089 error = bus_dmamem_alloc(sc_if->msk_cdata.msk_tx_ring_tag, 2090 (void **)&sc_if->msk_rdata.msk_tx_ring, BUS_DMA_WAITOK | 2091 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc_if->msk_cdata.msk_tx_ring_map); 2092 if (error != 0) { 2093 device_printf(sc_if->msk_if_dev, 2094 "failed to allocate DMA'able memory for Tx ring\n"); 2095 goto fail; 2096 } 2097 2098 ctx.msk_busaddr = 0; 2099 error = bus_dmamap_load(sc_if->msk_cdata.msk_tx_ring_tag, 2100 sc_if->msk_cdata.msk_tx_ring_map, sc_if->msk_rdata.msk_tx_ring, 2101 MSK_TX_RING_SZ, msk_dmamap_cb, &ctx, 0); 2102 if (error != 0) { 2103 device_printf(sc_if->msk_if_dev, 2104 "failed to load DMA'able memory for Tx ring\n"); 2105 goto fail; 2106 } 2107 sc_if->msk_rdata.msk_tx_ring_paddr = ctx.msk_busaddr; 2108 2109 /* Allocate DMA'able memory and load the DMA map for Rx ring. */ 2110 error = bus_dmamem_alloc(sc_if->msk_cdata.msk_rx_ring_tag, 2111 (void **)&sc_if->msk_rdata.msk_rx_ring, BUS_DMA_WAITOK | 2112 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc_if->msk_cdata.msk_rx_ring_map); 2113 if (error != 0) { 2114 device_printf(sc_if->msk_if_dev, 2115 "failed to allocate DMA'able memory for Rx ring\n"); 2116 goto fail; 2117 } 2118 2119 ctx.msk_busaddr = 0; 2120 error = bus_dmamap_load(sc_if->msk_cdata.msk_rx_ring_tag, 2121 sc_if->msk_cdata.msk_rx_ring_map, sc_if->msk_rdata.msk_rx_ring, 2122 MSK_RX_RING_SZ, msk_dmamap_cb, &ctx, 0); 2123 if (error != 0) { 2124 device_printf(sc_if->msk_if_dev, 2125 "failed to load DMA'able memory for Rx ring\n"); 2126 goto fail; 2127 } 2128 sc_if->msk_rdata.msk_rx_ring_paddr = ctx.msk_busaddr; 2129 2130 /* Create DMA maps for Tx buffers. */ 2131 for (i = 0; i < MSK_TX_RING_CNT; i++) { 2132 txd = &sc_if->msk_cdata.msk_txdesc[i]; 2133 txd->tx_m = NULL; 2134 txd->tx_dmamap = NULL; 2135 error = bus_dmamap_create(sc_if->msk_cdata.msk_tx_tag, 0, 2136 &txd->tx_dmamap); 2137 if (error != 0) { 2138 device_printf(sc_if->msk_if_dev, 2139 "failed to create Tx dmamap\n"); 2140 goto fail; 2141 } 2142 } 2143 /* Create DMA maps for Rx buffers. */ 2144 if ((error = bus_dmamap_create(sc_if->msk_cdata.msk_rx_tag, 0, 2145 &sc_if->msk_cdata.msk_rx_sparemap)) != 0) { 2146 device_printf(sc_if->msk_if_dev, 2147 "failed to create spare Rx dmamap\n"); 2148 goto fail; 2149 } 2150 for (i = 0; i < MSK_RX_RING_CNT; i++) { 2151 rxd = &sc_if->msk_cdata.msk_rxdesc[i]; 2152 rxd->rx_m = NULL; 2153 rxd->rx_dmamap = NULL; 2154 error = bus_dmamap_create(sc_if->msk_cdata.msk_rx_tag, 0, 2155 &rxd->rx_dmamap); 2156 if (error != 0) { 2157 device_printf(sc_if->msk_if_dev, 2158 "failed to create Rx dmamap\n"); 2159 goto fail; 2160 } 2161 } 2162 2163 fail: 2164 return (error); 2165 } 2166 2167 static int 2168 msk_rx_dma_jalloc(struct msk_if_softc *sc_if) 2169 { 2170 struct msk_dmamap_arg ctx; 2171 struct msk_rxdesc *jrxd; 2172 bus_size_t rxalign; 2173 int error, i; 2174 2175 if (jumbo_disable != 0 || (sc_if->msk_flags & MSK_FLAG_NOJUMBO) != 0) { 2176 sc_if->msk_flags |= MSK_FLAG_NOJUMBO; 2177 device_printf(sc_if->msk_if_dev, 2178 "disabling jumbo frame support\n"); 2179 sc_if->msk_flags |= MSK_FLAG_NOJUMBO; 2180 return (0); 2181 } 2182 /* Create tag for jumbo Rx ring. */ 2183 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2184 MSK_RING_ALIGN, 0, /* alignment, boundary */ 2185 BUS_SPACE_MAXADDR, /* lowaddr */ 2186 BUS_SPACE_MAXADDR, /* highaddr */ 2187 NULL, NULL, /* filter, filterarg */ 2188 MSK_JUMBO_RX_RING_SZ, /* maxsize */ 2189 1, /* nsegments */ 2190 MSK_JUMBO_RX_RING_SZ, /* maxsegsize */ 2191 0, /* flags */ 2192 NULL, NULL, /* lockfunc, lockarg */ 2193 &sc_if->msk_cdata.msk_jumbo_rx_ring_tag); 2194 if (error != 0) { 2195 device_printf(sc_if->msk_if_dev, 2196 "failed to create jumbo Rx ring DMA tag\n"); 2197 goto jumbo_fail; 2198 } 2199 2200 rxalign = 1; 2201 /* 2202 * Workaround hardware hang which seems to happen when Rx buffer 2203 * is not aligned on multiple of FIFO word(8 bytes). 2204 */ 2205 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) != 0) 2206 rxalign = MSK_RX_BUF_ALIGN; 2207 /* Create tag for jumbo Rx buffers. */ 2208 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2209 rxalign, 0, /* alignment, boundary */ 2210 BUS_SPACE_MAXADDR, /* lowaddr */ 2211 BUS_SPACE_MAXADDR, /* highaddr */ 2212 NULL, NULL, /* filter, filterarg */ 2213 MJUM9BYTES, /* maxsize */ 2214 1, /* nsegments */ 2215 MJUM9BYTES, /* maxsegsize */ 2216 0, /* flags */ 2217 NULL, NULL, /* lockfunc, lockarg */ 2218 &sc_if->msk_cdata.msk_jumbo_rx_tag); 2219 if (error != 0) { 2220 device_printf(sc_if->msk_if_dev, 2221 "failed to create jumbo Rx DMA tag\n"); 2222 goto jumbo_fail; 2223 } 2224 2225 /* Allocate DMA'able memory and load the DMA map for jumbo Rx ring. */ 2226 error = bus_dmamem_alloc(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 2227 (void **)&sc_if->msk_rdata.msk_jumbo_rx_ring, 2228 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 2229 &sc_if->msk_cdata.msk_jumbo_rx_ring_map); 2230 if (error != 0) { 2231 device_printf(sc_if->msk_if_dev, 2232 "failed to allocate DMA'able memory for jumbo Rx ring\n"); 2233 goto jumbo_fail; 2234 } 2235 2236 ctx.msk_busaddr = 0; 2237 error = bus_dmamap_load(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 2238 sc_if->msk_cdata.msk_jumbo_rx_ring_map, 2239 sc_if->msk_rdata.msk_jumbo_rx_ring, MSK_JUMBO_RX_RING_SZ, 2240 msk_dmamap_cb, &ctx, 0); 2241 if (error != 0) { 2242 device_printf(sc_if->msk_if_dev, 2243 "failed to load DMA'able memory for jumbo Rx ring\n"); 2244 goto jumbo_fail; 2245 } 2246 sc_if->msk_rdata.msk_jumbo_rx_ring_paddr = ctx.msk_busaddr; 2247 2248 /* Create DMA maps for jumbo Rx buffers. */ 2249 if ((error = bus_dmamap_create(sc_if->msk_cdata.msk_jumbo_rx_tag, 0, 2250 &sc_if->msk_cdata.msk_jumbo_rx_sparemap)) != 0) { 2251 device_printf(sc_if->msk_if_dev, 2252 "failed to create spare jumbo Rx dmamap\n"); 2253 goto jumbo_fail; 2254 } 2255 for (i = 0; i < MSK_JUMBO_RX_RING_CNT; i++) { 2256 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[i]; 2257 jrxd->rx_m = NULL; 2258 jrxd->rx_dmamap = NULL; 2259 error = bus_dmamap_create(sc_if->msk_cdata.msk_jumbo_rx_tag, 0, 2260 &jrxd->rx_dmamap); 2261 if (error != 0) { 2262 device_printf(sc_if->msk_if_dev, 2263 "failed to create jumbo Rx dmamap\n"); 2264 goto jumbo_fail; 2265 } 2266 } 2267 2268 return (0); 2269 2270 jumbo_fail: 2271 msk_rx_dma_jfree(sc_if); 2272 device_printf(sc_if->msk_if_dev, "disabling jumbo frame support " 2273 "due to resource shortage\n"); 2274 sc_if->msk_flags |= MSK_FLAG_NOJUMBO; 2275 return (error); 2276 } 2277 2278 static void 2279 msk_txrx_dma_free(struct msk_if_softc *sc_if) 2280 { 2281 struct msk_txdesc *txd; 2282 struct msk_rxdesc *rxd; 2283 int i; 2284 2285 /* Tx ring. */ 2286 if (sc_if->msk_cdata.msk_tx_ring_tag) { 2287 if (sc_if->msk_cdata.msk_tx_ring_map) 2288 bus_dmamap_unload(sc_if->msk_cdata.msk_tx_ring_tag, 2289 sc_if->msk_cdata.msk_tx_ring_map); 2290 if (sc_if->msk_cdata.msk_tx_ring_map && 2291 sc_if->msk_rdata.msk_tx_ring) 2292 bus_dmamem_free(sc_if->msk_cdata.msk_tx_ring_tag, 2293 sc_if->msk_rdata.msk_tx_ring, 2294 sc_if->msk_cdata.msk_tx_ring_map); 2295 sc_if->msk_rdata.msk_tx_ring = NULL; 2296 sc_if->msk_cdata.msk_tx_ring_map = NULL; 2297 bus_dma_tag_destroy(sc_if->msk_cdata.msk_tx_ring_tag); 2298 sc_if->msk_cdata.msk_tx_ring_tag = NULL; 2299 } 2300 /* Rx ring. */ 2301 if (sc_if->msk_cdata.msk_rx_ring_tag) { 2302 if (sc_if->msk_cdata.msk_rx_ring_map) 2303 bus_dmamap_unload(sc_if->msk_cdata.msk_rx_ring_tag, 2304 sc_if->msk_cdata.msk_rx_ring_map); 2305 if (sc_if->msk_cdata.msk_rx_ring_map && 2306 sc_if->msk_rdata.msk_rx_ring) 2307 bus_dmamem_free(sc_if->msk_cdata.msk_rx_ring_tag, 2308 sc_if->msk_rdata.msk_rx_ring, 2309 sc_if->msk_cdata.msk_rx_ring_map); 2310 sc_if->msk_rdata.msk_rx_ring = NULL; 2311 sc_if->msk_cdata.msk_rx_ring_map = NULL; 2312 bus_dma_tag_destroy(sc_if->msk_cdata.msk_rx_ring_tag); 2313 sc_if->msk_cdata.msk_rx_ring_tag = NULL; 2314 } 2315 /* Tx buffers. */ 2316 if (sc_if->msk_cdata.msk_tx_tag) { 2317 for (i = 0; i < MSK_TX_RING_CNT; i++) { 2318 txd = &sc_if->msk_cdata.msk_txdesc[i]; 2319 if (txd->tx_dmamap) { 2320 bus_dmamap_destroy(sc_if->msk_cdata.msk_tx_tag, 2321 txd->tx_dmamap); 2322 txd->tx_dmamap = NULL; 2323 } 2324 } 2325 bus_dma_tag_destroy(sc_if->msk_cdata.msk_tx_tag); 2326 sc_if->msk_cdata.msk_tx_tag = NULL; 2327 } 2328 /* Rx buffers. */ 2329 if (sc_if->msk_cdata.msk_rx_tag) { 2330 for (i = 0; i < MSK_RX_RING_CNT; i++) { 2331 rxd = &sc_if->msk_cdata.msk_rxdesc[i]; 2332 if (rxd->rx_dmamap) { 2333 bus_dmamap_destroy(sc_if->msk_cdata.msk_rx_tag, 2334 rxd->rx_dmamap); 2335 rxd->rx_dmamap = NULL; 2336 } 2337 } 2338 if (sc_if->msk_cdata.msk_rx_sparemap) { 2339 bus_dmamap_destroy(sc_if->msk_cdata.msk_rx_tag, 2340 sc_if->msk_cdata.msk_rx_sparemap); 2341 sc_if->msk_cdata.msk_rx_sparemap = 0; 2342 } 2343 bus_dma_tag_destroy(sc_if->msk_cdata.msk_rx_tag); 2344 sc_if->msk_cdata.msk_rx_tag = NULL; 2345 } 2346 if (sc_if->msk_cdata.msk_parent_tag) { 2347 bus_dma_tag_destroy(sc_if->msk_cdata.msk_parent_tag); 2348 sc_if->msk_cdata.msk_parent_tag = NULL; 2349 } 2350 } 2351 2352 static void 2353 msk_rx_dma_jfree(struct msk_if_softc *sc_if) 2354 { 2355 struct msk_rxdesc *jrxd; 2356 int i; 2357 2358 /* Jumbo Rx ring. */ 2359 if (sc_if->msk_cdata.msk_jumbo_rx_ring_tag) { 2360 if (sc_if->msk_cdata.msk_jumbo_rx_ring_map) 2361 bus_dmamap_unload(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 2362 sc_if->msk_cdata.msk_jumbo_rx_ring_map); 2363 if (sc_if->msk_cdata.msk_jumbo_rx_ring_map && 2364 sc_if->msk_rdata.msk_jumbo_rx_ring) 2365 bus_dmamem_free(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 2366 sc_if->msk_rdata.msk_jumbo_rx_ring, 2367 sc_if->msk_cdata.msk_jumbo_rx_ring_map); 2368 sc_if->msk_rdata.msk_jumbo_rx_ring = NULL; 2369 sc_if->msk_cdata.msk_jumbo_rx_ring_map = NULL; 2370 bus_dma_tag_destroy(sc_if->msk_cdata.msk_jumbo_rx_ring_tag); 2371 sc_if->msk_cdata.msk_jumbo_rx_ring_tag = NULL; 2372 } 2373 /* Jumbo Rx buffers. */ 2374 if (sc_if->msk_cdata.msk_jumbo_rx_tag) { 2375 for (i = 0; i < MSK_JUMBO_RX_RING_CNT; i++) { 2376 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[i]; 2377 if (jrxd->rx_dmamap) { 2378 bus_dmamap_destroy( 2379 sc_if->msk_cdata.msk_jumbo_rx_tag, 2380 jrxd->rx_dmamap); 2381 jrxd->rx_dmamap = NULL; 2382 } 2383 } 2384 if (sc_if->msk_cdata.msk_jumbo_rx_sparemap) { 2385 bus_dmamap_destroy(sc_if->msk_cdata.msk_jumbo_rx_tag, 2386 sc_if->msk_cdata.msk_jumbo_rx_sparemap); 2387 sc_if->msk_cdata.msk_jumbo_rx_sparemap = 0; 2388 } 2389 bus_dma_tag_destroy(sc_if->msk_cdata.msk_jumbo_rx_tag); 2390 sc_if->msk_cdata.msk_jumbo_rx_tag = NULL; 2391 } 2392 } 2393 2394 static int 2395 msk_encap(struct msk_if_softc *sc_if, struct mbuf **m_head) 2396 { 2397 struct msk_txdesc *txd, *txd_last; 2398 struct msk_tx_desc *tx_le; 2399 struct mbuf *m; 2400 bus_dmamap_t map; 2401 bus_dma_segment_t txsegs[MSK_MAXTXSEGS]; 2402 uint32_t control, prod, si; 2403 uint16_t offset, tcp_offset, tso_mtu; 2404 int error, i, nseg, tso; 2405 2406 MSK_IF_LOCK_ASSERT(sc_if); 2407 2408 tcp_offset = offset = 0; 2409 m = *m_head; 2410 if ((m->m_pkthdr.csum_flags & (MSK_CSUM_FEATURES | CSUM_TSO)) != 0) { 2411 /* 2412 * Since mbuf has no protocol specific structure information 2413 * in it we have to inspect protocol information here to 2414 * setup TSO and checksum offload. I don't know why Marvell 2415 * made a such decision in chip design because other GigE 2416 * hardwares normally takes care of all these chores in 2417 * hardware. However, TSO performance of Yukon II is very 2418 * good such that it's worth to implement it. 2419 */ 2420 struct ether_header *eh; 2421 struct ip *ip; 2422 struct tcphdr *tcp; 2423 2424 if (M_WRITABLE(m) == 0) { 2425 /* Get a writable copy. */ 2426 m = m_dup(*m_head, M_DONTWAIT); 2427 m_freem(*m_head); 2428 if (m == NULL) { 2429 *m_head = NULL; 2430 return (ENOBUFS); 2431 } 2432 *m_head = m; 2433 } 2434 2435 offset = sizeof(struct ether_header); 2436 m = m_pullup(m, offset); 2437 if (m == NULL) { 2438 *m_head = NULL; 2439 return (ENOBUFS); 2440 } 2441 eh = mtod(m, struct ether_header *); 2442 /* Check if hardware VLAN insertion is off. */ 2443 if (eh->ether_type == htons(ETHERTYPE_VLAN)) { 2444 offset = sizeof(struct ether_vlan_header); 2445 m = m_pullup(m, offset); 2446 if (m == NULL) { 2447 *m_head = NULL; 2448 return (ENOBUFS); 2449 } 2450 } 2451 m = m_pullup(m, offset + sizeof(struct ip)); 2452 if (m == NULL) { 2453 *m_head = NULL; 2454 return (ENOBUFS); 2455 } 2456 ip = (struct ip *)(mtod(m, char *) + offset); 2457 offset += (ip->ip_hl << 2); 2458 tcp_offset = offset; 2459 /* 2460 * It seems that Yukon II has Tx checksum offload bug for 2461 * small TCP packets that's less than 60 bytes in size 2462 * (e.g. TCP window probe packet, pure ACK packet). 2463 * Common work around like padding with zeros to make the 2464 * frame minimum ethernet frame size didn't work at all. 2465 * Instead of disabling checksum offload completely we 2466 * resort to S/W checksum routine when we encounter short 2467 * TCP frames. 2468 * Short UDP packets appear to be handled correctly by 2469 * Yukon II. 2470 */ 2471 if (m->m_pkthdr.len < MSK_MIN_FRAMELEN && 2472 (m->m_pkthdr.csum_flags & CSUM_TCP) != 0) { 2473 m = m_pullup(m, offset + sizeof(struct tcphdr)); 2474 if (m == NULL) { 2475 *m_head = NULL; 2476 return (ENOBUFS); 2477 } 2478 *(uint16_t *)(m->m_data + offset + 2479 m->m_pkthdr.csum_data) = in_cksum_skip(m, 2480 m->m_pkthdr.len, offset); 2481 m->m_pkthdr.csum_flags &= ~CSUM_TCP; 2482 } 2483 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 2484 m = m_pullup(m, offset + sizeof(struct tcphdr)); 2485 if (m == NULL) { 2486 *m_head = NULL; 2487 return (ENOBUFS); 2488 } 2489 tcp = (struct tcphdr *)(mtod(m, char *) + offset); 2490 offset += (tcp->th_off << 2); 2491 } 2492 *m_head = m; 2493 } 2494 2495 prod = sc_if->msk_cdata.msk_tx_prod; 2496 txd = &sc_if->msk_cdata.msk_txdesc[prod]; 2497 txd_last = txd; 2498 map = txd->tx_dmamap; 2499 error = bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_tx_tag, map, 2500 *m_head, txsegs, &nseg, BUS_DMA_NOWAIT); 2501 if (error == EFBIG) { 2502 m = m_collapse(*m_head, M_DONTWAIT, MSK_MAXTXSEGS); 2503 if (m == NULL) { 2504 m_freem(*m_head); 2505 *m_head = NULL; 2506 return (ENOBUFS); 2507 } 2508 *m_head = m; 2509 error = bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_tx_tag, 2510 map, *m_head, txsegs, &nseg, BUS_DMA_NOWAIT); 2511 if (error != 0) { 2512 m_freem(*m_head); 2513 *m_head = NULL; 2514 return (error); 2515 } 2516 } else if (error != 0) 2517 return (error); 2518 if (nseg == 0) { 2519 m_freem(*m_head); 2520 *m_head = NULL; 2521 return (EIO); 2522 } 2523 2524 /* Check number of available descriptors. */ 2525 if (sc_if->msk_cdata.msk_tx_cnt + nseg >= 2526 (MSK_TX_RING_CNT - MSK_RESERVED_TX_DESC_CNT)) { 2527 bus_dmamap_unload(sc_if->msk_cdata.msk_tx_tag, map); 2528 return (ENOBUFS); 2529 } 2530 2531 control = 0; 2532 tso = 0; 2533 tx_le = NULL; 2534 2535 /* Check TSO support. */ 2536 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 2537 tso_mtu = offset + m->m_pkthdr.tso_segsz; 2538 if (tso_mtu != sc_if->msk_cdata.msk_tso_mtu) { 2539 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2540 tx_le->msk_addr = htole32(tso_mtu); 2541 tx_le->msk_control = htole32(OP_LRGLEN | HW_OWNER); 2542 sc_if->msk_cdata.msk_tx_cnt++; 2543 MSK_INC(prod, MSK_TX_RING_CNT); 2544 sc_if->msk_cdata.msk_tso_mtu = tso_mtu; 2545 } 2546 tso++; 2547 } 2548 /* Check if we have a VLAN tag to insert. */ 2549 if ((m->m_flags & M_VLANTAG) != 0) { 2550 if (tso == 0) { 2551 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2552 tx_le->msk_addr = htole32(0); 2553 tx_le->msk_control = htole32(OP_VLAN | HW_OWNER | 2554 htons(m->m_pkthdr.ether_vtag)); 2555 sc_if->msk_cdata.msk_tx_cnt++; 2556 MSK_INC(prod, MSK_TX_RING_CNT); 2557 } else { 2558 tx_le->msk_control |= htole32(OP_VLAN | 2559 htons(m->m_pkthdr.ether_vtag)); 2560 } 2561 control |= INS_VLAN; 2562 } 2563 /* Check if we have to handle checksum offload. */ 2564 if (tso == 0 && (m->m_pkthdr.csum_flags & MSK_CSUM_FEATURES) != 0) { 2565 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2566 tx_le->msk_addr = htole32(((tcp_offset + m->m_pkthdr.csum_data) 2567 & 0xffff) | ((uint32_t)tcp_offset << 16)); 2568 tx_le->msk_control = htole32(1 << 16 | (OP_TCPLISW | HW_OWNER)); 2569 control = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM; 2570 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0) 2571 control |= UDPTCP; 2572 sc_if->msk_cdata.msk_tx_cnt++; 2573 MSK_INC(prod, MSK_TX_RING_CNT); 2574 } 2575 2576 si = prod; 2577 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2578 tx_le->msk_addr = htole32(MSK_ADDR_LO(txsegs[0].ds_addr)); 2579 if (tso == 0) 2580 tx_le->msk_control = htole32(txsegs[0].ds_len | control | 2581 OP_PACKET); 2582 else 2583 tx_le->msk_control = htole32(txsegs[0].ds_len | control | 2584 OP_LARGESEND); 2585 sc_if->msk_cdata.msk_tx_cnt++; 2586 MSK_INC(prod, MSK_TX_RING_CNT); 2587 2588 for (i = 1; i < nseg; i++) { 2589 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2590 tx_le->msk_addr = htole32(MSK_ADDR_LO(txsegs[i].ds_addr)); 2591 tx_le->msk_control = htole32(txsegs[i].ds_len | control | 2592 OP_BUFFER | HW_OWNER); 2593 sc_if->msk_cdata.msk_tx_cnt++; 2594 MSK_INC(prod, MSK_TX_RING_CNT); 2595 } 2596 /* Update producer index. */ 2597 sc_if->msk_cdata.msk_tx_prod = prod; 2598 2599 /* Set EOP on the last desciptor. */ 2600 prod = (prod + MSK_TX_RING_CNT - 1) % MSK_TX_RING_CNT; 2601 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2602 tx_le->msk_control |= htole32(EOP); 2603 2604 /* Turn the first descriptor ownership to hardware. */ 2605 tx_le = &sc_if->msk_rdata.msk_tx_ring[si]; 2606 tx_le->msk_control |= htole32(HW_OWNER); 2607 2608 txd = &sc_if->msk_cdata.msk_txdesc[prod]; 2609 map = txd_last->tx_dmamap; 2610 txd_last->tx_dmamap = txd->tx_dmamap; 2611 txd->tx_dmamap = map; 2612 txd->tx_m = m; 2613 2614 /* Sync descriptors. */ 2615 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_tag, map, BUS_DMASYNC_PREWRITE); 2616 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_ring_tag, 2617 sc_if->msk_cdata.msk_tx_ring_map, 2618 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2619 2620 return (0); 2621 } 2622 2623 static void 2624 msk_tx_task(void *arg, int pending) 2625 { 2626 struct ifnet *ifp; 2627 2628 ifp = arg; 2629 msk_start(ifp); 2630 } 2631 2632 static void 2633 msk_start(struct ifnet *ifp) 2634 { 2635 struct msk_if_softc *sc_if; 2636 struct mbuf *m_head; 2637 int enq; 2638 2639 sc_if = ifp->if_softc; 2640 2641 MSK_IF_LOCK(sc_if); 2642 2643 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2644 IFF_DRV_RUNNING || sc_if->msk_link == 0) { 2645 MSK_IF_UNLOCK(sc_if); 2646 return; 2647 } 2648 2649 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 2650 sc_if->msk_cdata.msk_tx_cnt < 2651 (MSK_TX_RING_CNT - MSK_RESERVED_TX_DESC_CNT); ) { 2652 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2653 if (m_head == NULL) 2654 break; 2655 /* 2656 * Pack the data into the transmit ring. If we 2657 * don't have room, set the OACTIVE flag and wait 2658 * for the NIC to drain the ring. 2659 */ 2660 if (msk_encap(sc_if, &m_head) != 0) { 2661 if (m_head == NULL) 2662 break; 2663 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2664 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2665 break; 2666 } 2667 2668 enq++; 2669 /* 2670 * If there's a BPF listener, bounce a copy of this frame 2671 * to him. 2672 */ 2673 ETHER_BPF_MTAP(ifp, m_head); 2674 } 2675 2676 if (enq > 0) { 2677 /* Transmit */ 2678 CSR_WRITE_2(sc_if->msk_softc, 2679 Y2_PREF_Q_ADDR(sc_if->msk_txq, PREF_UNIT_PUT_IDX_REG), 2680 sc_if->msk_cdata.msk_tx_prod); 2681 2682 /* Set a timeout in case the chip goes out to lunch. */ 2683 sc_if->msk_watchdog_timer = MSK_TX_TIMEOUT; 2684 } 2685 2686 MSK_IF_UNLOCK(sc_if); 2687 } 2688 2689 static void 2690 msk_watchdog(struct msk_if_softc *sc_if) 2691 { 2692 struct ifnet *ifp; 2693 uint32_t ridx; 2694 int idx; 2695 2696 MSK_IF_LOCK_ASSERT(sc_if); 2697 2698 if (sc_if->msk_watchdog_timer == 0 || --sc_if->msk_watchdog_timer) 2699 return; 2700 ifp = sc_if->msk_ifp; 2701 if (sc_if->msk_link == 0) { 2702 if (bootverbose) 2703 if_printf(sc_if->msk_ifp, "watchdog timeout " 2704 "(missed link)\n"); 2705 ifp->if_oerrors++; 2706 msk_init_locked(sc_if); 2707 return; 2708 } 2709 2710 /* 2711 * Reclaim first as there is a possibility of losing Tx completion 2712 * interrupts. 2713 */ 2714 ridx = sc_if->msk_port == MSK_PORT_A ? STAT_TXA1_RIDX : STAT_TXA2_RIDX; 2715 idx = CSR_READ_2(sc_if->msk_softc, ridx); 2716 if (sc_if->msk_cdata.msk_tx_cons != idx) { 2717 msk_txeof(sc_if, idx); 2718 if (sc_if->msk_cdata.msk_tx_cnt == 0) { 2719 if_printf(ifp, "watchdog timeout (missed Tx interrupts) " 2720 "-- recovering\n"); 2721 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2722 taskqueue_enqueue(taskqueue_fast, 2723 &sc_if->msk_tx_task); 2724 return; 2725 } 2726 } 2727 2728 if_printf(ifp, "watchdog timeout\n"); 2729 ifp->if_oerrors++; 2730 msk_init_locked(sc_if); 2731 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2732 taskqueue_enqueue(taskqueue_fast, &sc_if->msk_tx_task); 2733 } 2734 2735 static int 2736 mskc_shutdown(device_t dev) 2737 { 2738 struct msk_softc *sc; 2739 int i; 2740 2741 sc = device_get_softc(dev); 2742 MSK_LOCK(sc); 2743 for (i = 0; i < sc->msk_num_port; i++) { 2744 if (sc->msk_if[i] != NULL) 2745 msk_stop(sc->msk_if[i]); 2746 } 2747 2748 /* Disable all interrupts. */ 2749 CSR_WRITE_4(sc, B0_IMSK, 0); 2750 CSR_READ_4(sc, B0_IMSK); 2751 CSR_WRITE_4(sc, B0_HWE_IMSK, 0); 2752 CSR_READ_4(sc, B0_HWE_IMSK); 2753 2754 /* Put hardware reset. */ 2755 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); 2756 2757 MSK_UNLOCK(sc); 2758 return (0); 2759 } 2760 2761 static int 2762 mskc_suspend(device_t dev) 2763 { 2764 struct msk_softc *sc; 2765 int i; 2766 2767 sc = device_get_softc(dev); 2768 2769 MSK_LOCK(sc); 2770 2771 for (i = 0; i < sc->msk_num_port; i++) { 2772 if (sc->msk_if[i] != NULL && sc->msk_if[i]->msk_ifp != NULL && 2773 ((sc->msk_if[i]->msk_ifp->if_drv_flags & 2774 IFF_DRV_RUNNING) != 0)) 2775 msk_stop(sc->msk_if[i]); 2776 } 2777 2778 /* Disable all interrupts. */ 2779 CSR_WRITE_4(sc, B0_IMSK, 0); 2780 CSR_READ_4(sc, B0_IMSK); 2781 CSR_WRITE_4(sc, B0_HWE_IMSK, 0); 2782 CSR_READ_4(sc, B0_HWE_IMSK); 2783 2784 msk_phy_power(sc, MSK_PHY_POWERDOWN); 2785 2786 /* Put hardware reset. */ 2787 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); 2788 sc->msk_suspended = 1; 2789 2790 MSK_UNLOCK(sc); 2791 2792 return (0); 2793 } 2794 2795 static int 2796 mskc_resume(device_t dev) 2797 { 2798 struct msk_softc *sc; 2799 int i; 2800 2801 sc = device_get_softc(dev); 2802 2803 MSK_LOCK(sc); 2804 2805 mskc_reset(sc); 2806 for (i = 0; i < sc->msk_num_port; i++) { 2807 if (sc->msk_if[i] != NULL && sc->msk_if[i]->msk_ifp != NULL && 2808 ((sc->msk_if[i]->msk_ifp->if_flags & IFF_UP) != 0)) 2809 msk_init_locked(sc->msk_if[i]); 2810 } 2811 sc->msk_suspended = 0; 2812 2813 MSK_UNLOCK(sc); 2814 2815 return (0); 2816 } 2817 2818 #ifndef __NO_STRICT_ALIGNMENT 2819 static __inline void 2820 msk_fixup_rx(struct mbuf *m) 2821 { 2822 int i; 2823 uint16_t *src, *dst; 2824 2825 src = mtod(m, uint16_t *); 2826 dst = src - 3; 2827 2828 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 2829 *dst++ = *src++; 2830 2831 m->m_data -= (MSK_RX_BUF_ALIGN - ETHER_ALIGN); 2832 } 2833 #endif 2834 2835 static void 2836 msk_rxeof(struct msk_if_softc *sc_if, uint32_t status, int len) 2837 { 2838 struct mbuf *m; 2839 struct ifnet *ifp; 2840 struct msk_rxdesc *rxd; 2841 int cons, rxlen; 2842 2843 ifp = sc_if->msk_ifp; 2844 2845 MSK_IF_LOCK_ASSERT(sc_if); 2846 2847 cons = sc_if->msk_cdata.msk_rx_cons; 2848 do { 2849 rxlen = status >> 16; 2850 if ((status & GMR_FS_VLAN) != 0 && 2851 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 2852 rxlen -= ETHER_VLAN_ENCAP_LEN; 2853 if (len > sc_if->msk_framesize || 2854 ((status & GMR_FS_ANY_ERR) != 0) || 2855 ((status & GMR_FS_RX_OK) == 0) || (rxlen != len)) { 2856 /* Don't count flow-control packet as errors. */ 2857 if ((status & GMR_FS_GOOD_FC) == 0) 2858 ifp->if_ierrors++; 2859 msk_discard_rxbuf(sc_if, cons); 2860 break; 2861 } 2862 rxd = &sc_if->msk_cdata.msk_rxdesc[cons]; 2863 m = rxd->rx_m; 2864 if (msk_newbuf(sc_if, cons) != 0) { 2865 ifp->if_iqdrops++; 2866 /* Reuse old buffer. */ 2867 msk_discard_rxbuf(sc_if, cons); 2868 break; 2869 } 2870 m->m_pkthdr.rcvif = ifp; 2871 m->m_pkthdr.len = m->m_len = len; 2872 #ifndef __NO_STRICT_ALIGNMENT 2873 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) != 0) 2874 msk_fixup_rx(m); 2875 #endif 2876 ifp->if_ipackets++; 2877 /* Check for VLAN tagged packets. */ 2878 if ((status & GMR_FS_VLAN) != 0 && 2879 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) { 2880 m->m_pkthdr.ether_vtag = sc_if->msk_vtag; 2881 m->m_flags |= M_VLANTAG; 2882 } 2883 MSK_IF_UNLOCK(sc_if); 2884 (*ifp->if_input)(ifp, m); 2885 MSK_IF_LOCK(sc_if); 2886 } while (0); 2887 2888 MSK_INC(sc_if->msk_cdata.msk_rx_cons, MSK_RX_RING_CNT); 2889 MSK_INC(sc_if->msk_cdata.msk_rx_prod, MSK_RX_RING_CNT); 2890 } 2891 2892 static void 2893 msk_jumbo_rxeof(struct msk_if_softc *sc_if, uint32_t status, int len) 2894 { 2895 struct mbuf *m; 2896 struct ifnet *ifp; 2897 struct msk_rxdesc *jrxd; 2898 int cons, rxlen; 2899 2900 ifp = sc_if->msk_ifp; 2901 2902 MSK_IF_LOCK_ASSERT(sc_if); 2903 2904 cons = sc_if->msk_cdata.msk_rx_cons; 2905 do { 2906 rxlen = status >> 16; 2907 if ((status & GMR_FS_VLAN) != 0 && 2908 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 2909 rxlen -= ETHER_VLAN_ENCAP_LEN; 2910 if (len > sc_if->msk_framesize || 2911 ((status & GMR_FS_ANY_ERR) != 0) || 2912 ((status & GMR_FS_RX_OK) == 0) || (rxlen != len)) { 2913 /* Don't count flow-control packet as errors. */ 2914 if ((status & GMR_FS_GOOD_FC) == 0) 2915 ifp->if_ierrors++; 2916 msk_discard_jumbo_rxbuf(sc_if, cons); 2917 break; 2918 } 2919 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[cons]; 2920 m = jrxd->rx_m; 2921 if (msk_jumbo_newbuf(sc_if, cons) != 0) { 2922 ifp->if_iqdrops++; 2923 /* Reuse old buffer. */ 2924 msk_discard_jumbo_rxbuf(sc_if, cons); 2925 break; 2926 } 2927 m->m_pkthdr.rcvif = ifp; 2928 m->m_pkthdr.len = m->m_len = len; 2929 #ifndef __NO_STRICT_ALIGNMENT 2930 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) != 0) 2931 msk_fixup_rx(m); 2932 #endif 2933 ifp->if_ipackets++; 2934 /* Check for VLAN tagged packets. */ 2935 if ((status & GMR_FS_VLAN) != 0 && 2936 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) { 2937 m->m_pkthdr.ether_vtag = sc_if->msk_vtag; 2938 m->m_flags |= M_VLANTAG; 2939 } 2940 MSK_IF_UNLOCK(sc_if); 2941 (*ifp->if_input)(ifp, m); 2942 MSK_IF_LOCK(sc_if); 2943 } while (0); 2944 2945 MSK_INC(sc_if->msk_cdata.msk_rx_cons, MSK_JUMBO_RX_RING_CNT); 2946 MSK_INC(sc_if->msk_cdata.msk_rx_prod, MSK_JUMBO_RX_RING_CNT); 2947 } 2948 2949 static void 2950 msk_txeof(struct msk_if_softc *sc_if, int idx) 2951 { 2952 struct msk_txdesc *txd; 2953 struct msk_tx_desc *cur_tx; 2954 struct ifnet *ifp; 2955 uint32_t control; 2956 int cons, prog; 2957 2958 MSK_IF_LOCK_ASSERT(sc_if); 2959 2960 ifp = sc_if->msk_ifp; 2961 2962 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_ring_tag, 2963 sc_if->msk_cdata.msk_tx_ring_map, 2964 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2965 /* 2966 * Go through our tx ring and free mbufs for those 2967 * frames that have been sent. 2968 */ 2969 cons = sc_if->msk_cdata.msk_tx_cons; 2970 prog = 0; 2971 for (; cons != idx; MSK_INC(cons, MSK_TX_RING_CNT)) { 2972 if (sc_if->msk_cdata.msk_tx_cnt <= 0) 2973 break; 2974 prog++; 2975 cur_tx = &sc_if->msk_rdata.msk_tx_ring[cons]; 2976 control = le32toh(cur_tx->msk_control); 2977 sc_if->msk_cdata.msk_tx_cnt--; 2978 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2979 if ((control & EOP) == 0) 2980 continue; 2981 txd = &sc_if->msk_cdata.msk_txdesc[cons]; 2982 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_tag, txd->tx_dmamap, 2983 BUS_DMASYNC_POSTWRITE); 2984 bus_dmamap_unload(sc_if->msk_cdata.msk_tx_tag, txd->tx_dmamap); 2985 2986 ifp->if_opackets++; 2987 KASSERT(txd->tx_m != NULL, ("%s: freeing NULL mbuf!", 2988 __func__)); 2989 m_freem(txd->tx_m); 2990 txd->tx_m = NULL; 2991 } 2992 2993 if (prog > 0) { 2994 sc_if->msk_cdata.msk_tx_cons = cons; 2995 if (sc_if->msk_cdata.msk_tx_cnt == 0) 2996 sc_if->msk_watchdog_timer = 0; 2997 /* No need to sync LEs as we didn't update LEs. */ 2998 } 2999 } 3000 3001 static void 3002 msk_tick(void *xsc_if) 3003 { 3004 struct msk_if_softc *sc_if; 3005 struct mii_data *mii; 3006 3007 sc_if = xsc_if; 3008 3009 MSK_IF_LOCK_ASSERT(sc_if); 3010 3011 mii = device_get_softc(sc_if->msk_miibus); 3012 3013 mii_tick(mii); 3014 msk_watchdog(sc_if); 3015 callout_reset(&sc_if->msk_tick_ch, hz, msk_tick, sc_if); 3016 } 3017 3018 static void 3019 msk_intr_phy(struct msk_if_softc *sc_if) 3020 { 3021 uint16_t status; 3022 3023 msk_phy_readreg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_STAT); 3024 status = msk_phy_readreg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_STAT); 3025 /* Handle FIFO Underrun/Overflow? */ 3026 if ((status & PHY_M_IS_FIFO_ERROR)) 3027 device_printf(sc_if->msk_if_dev, 3028 "PHY FIFO underrun/overflow.\n"); 3029 } 3030 3031 static void 3032 msk_intr_gmac(struct msk_if_softc *sc_if) 3033 { 3034 struct msk_softc *sc; 3035 uint8_t status; 3036 3037 sc = sc_if->msk_softc; 3038 status = CSR_READ_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_SRC)); 3039 3040 /* GMAC Rx FIFO overrun. */ 3041 if ((status & GM_IS_RX_FF_OR) != 0) { 3042 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), 3043 GMF_CLI_RX_FO); 3044 device_printf(sc_if->msk_if_dev, "Rx FIFO overrun!\n"); 3045 } 3046 /* GMAC Tx FIFO underrun. */ 3047 if ((status & GM_IS_TX_FF_UR) != 0) { 3048 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 3049 GMF_CLI_TX_FU); 3050 device_printf(sc_if->msk_if_dev, "Tx FIFO underrun!\n"); 3051 /* 3052 * XXX 3053 * In case of Tx underrun, we may need to flush/reset 3054 * Tx MAC but that would also require resynchronization 3055 * with status LEs. Reintializing status LEs would 3056 * affect other port in dual MAC configuration so it 3057 * should be avoided as possible as we can. 3058 * Due to lack of documentation it's all vague guess but 3059 * it needs more investigation. 3060 */ 3061 } 3062 } 3063 3064 static void 3065 msk_handle_hwerr(struct msk_if_softc *sc_if, uint32_t status) 3066 { 3067 struct msk_softc *sc; 3068 3069 sc = sc_if->msk_softc; 3070 if ((status & Y2_IS_PAR_RD1) != 0) { 3071 device_printf(sc_if->msk_if_dev, 3072 "RAM buffer read parity error\n"); 3073 /* Clear IRQ. */ 3074 CSR_WRITE_2(sc, SELECT_RAM_BUFFER(sc_if->msk_port, B3_RI_CTRL), 3075 RI_CLR_RD_PERR); 3076 } 3077 if ((status & Y2_IS_PAR_WR1) != 0) { 3078 device_printf(sc_if->msk_if_dev, 3079 "RAM buffer write parity error\n"); 3080 /* Clear IRQ. */ 3081 CSR_WRITE_2(sc, SELECT_RAM_BUFFER(sc_if->msk_port, B3_RI_CTRL), 3082 RI_CLR_WR_PERR); 3083 } 3084 if ((status & Y2_IS_PAR_MAC1) != 0) { 3085 device_printf(sc_if->msk_if_dev, "Tx MAC parity error\n"); 3086 /* Clear IRQ. */ 3087 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 3088 GMF_CLI_TX_PE); 3089 } 3090 if ((status & Y2_IS_PAR_RX1) != 0) { 3091 device_printf(sc_if->msk_if_dev, "Rx parity error\n"); 3092 /* Clear IRQ. */ 3093 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_CLR_IRQ_PAR); 3094 } 3095 if ((status & (Y2_IS_TCP_TXS1 | Y2_IS_TCP_TXA1)) != 0) { 3096 device_printf(sc_if->msk_if_dev, "TCP segmentation error\n"); 3097 /* Clear IRQ. */ 3098 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_CLR_IRQ_TCP); 3099 } 3100 } 3101 3102 static void 3103 msk_intr_hwerr(struct msk_softc *sc) 3104 { 3105 uint32_t status; 3106 uint32_t tlphead[4]; 3107 3108 status = CSR_READ_4(sc, B0_HWE_ISRC); 3109 /* Time Stamp timer overflow. */ 3110 if ((status & Y2_IS_TIST_OV) != 0) 3111 CSR_WRITE_1(sc, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ); 3112 if ((status & Y2_IS_PCI_NEXP) != 0) { 3113 /* 3114 * PCI Express Error occured which is not described in PEX 3115 * spec. 3116 * This error is also mapped either to Master Abort( 3117 * Y2_IS_MST_ERR) or Target Abort (Y2_IS_IRQ_STAT) bit and 3118 * can only be cleared there. 3119 */ 3120 device_printf(sc->msk_dev, 3121 "PCI Express protocol violation error\n"); 3122 } 3123 3124 if ((status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) != 0) { 3125 uint16_t v16; 3126 3127 if ((status & Y2_IS_MST_ERR) != 0) 3128 device_printf(sc->msk_dev, 3129 "unexpected IRQ Status error\n"); 3130 else 3131 device_printf(sc->msk_dev, 3132 "unexpected IRQ Master error\n"); 3133 /* Reset all bits in the PCI status register. */ 3134 v16 = pci_read_config(sc->msk_dev, PCIR_STATUS, 2); 3135 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON); 3136 pci_write_config(sc->msk_dev, PCIR_STATUS, v16 | 3137 PCIM_STATUS_PERR | PCIM_STATUS_SERR | PCIM_STATUS_RMABORT | 3138 PCIM_STATUS_RTABORT | PCIM_STATUS_PERRREPORT, 2); 3139 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 3140 } 3141 3142 /* Check for PCI Express Uncorrectable Error. */ 3143 if ((status & Y2_IS_PCI_EXP) != 0) { 3144 uint32_t v32; 3145 3146 /* 3147 * On PCI Express bus bridges are called root complexes (RC). 3148 * PCI Express errors are recognized by the root complex too, 3149 * which requests the system to handle the problem. After 3150 * error occurence it may be that no access to the adapter 3151 * may be performed any longer. 3152 */ 3153 3154 v32 = CSR_PCI_READ_4(sc, PEX_UNC_ERR_STAT); 3155 if ((v32 & PEX_UNSUP_REQ) != 0) { 3156 /* Ignore unsupported request error. */ 3157 device_printf(sc->msk_dev, 3158 "Uncorrectable PCI Express error\n"); 3159 } 3160 if ((v32 & (PEX_FATAL_ERRORS | PEX_POIS_TLP)) != 0) { 3161 int i; 3162 3163 /* Get TLP header form Log Registers. */ 3164 for (i = 0; i < 4; i++) 3165 tlphead[i] = CSR_PCI_READ_4(sc, 3166 PEX_HEADER_LOG + i * 4); 3167 /* Check for vendor defined broadcast message. */ 3168 if (!(tlphead[0] == 0x73004001 && tlphead[1] == 0x7f)) { 3169 sc->msk_intrhwemask &= ~Y2_IS_PCI_EXP; 3170 CSR_WRITE_4(sc, B0_HWE_IMSK, 3171 sc->msk_intrhwemask); 3172 CSR_READ_4(sc, B0_HWE_IMSK); 3173 } 3174 } 3175 /* Clear the interrupt. */ 3176 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON); 3177 CSR_PCI_WRITE_4(sc, PEX_UNC_ERR_STAT, 0xffffffff); 3178 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 3179 } 3180 3181 if ((status & Y2_HWE_L1_MASK) != 0 && sc->msk_if[MSK_PORT_A] != NULL) 3182 msk_handle_hwerr(sc->msk_if[MSK_PORT_A], status); 3183 if ((status & Y2_HWE_L2_MASK) != 0 && sc->msk_if[MSK_PORT_B] != NULL) 3184 msk_handle_hwerr(sc->msk_if[MSK_PORT_B], status >> 8); 3185 } 3186 3187 static __inline void 3188 msk_rxput(struct msk_if_softc *sc_if) 3189 { 3190 struct msk_softc *sc; 3191 3192 sc = sc_if->msk_softc; 3193 if (sc_if->msk_framesize > (MCLBYTES - MSK_RX_BUF_ALIGN)) 3194 bus_dmamap_sync( 3195 sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 3196 sc_if->msk_cdata.msk_jumbo_rx_ring_map, 3197 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3198 else 3199 bus_dmamap_sync( 3200 sc_if->msk_cdata.msk_rx_ring_tag, 3201 sc_if->msk_cdata.msk_rx_ring_map, 3202 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3203 CSR_WRITE_2(sc, Y2_PREF_Q_ADDR(sc_if->msk_rxq, 3204 PREF_UNIT_PUT_IDX_REG), sc_if->msk_cdata.msk_rx_prod); 3205 } 3206 3207 static int 3208 msk_handle_events(struct msk_softc *sc) 3209 { 3210 struct msk_if_softc *sc_if; 3211 int rxput[2]; 3212 struct msk_stat_desc *sd; 3213 uint32_t control, status; 3214 int cons, idx, len, port, rxprog; 3215 3216 idx = CSR_READ_2(sc, STAT_PUT_IDX); 3217 if (idx == sc->msk_stat_cons) 3218 return (0); 3219 3220 /* Sync status LEs. */ 3221 bus_dmamap_sync(sc->msk_stat_tag, sc->msk_stat_map, 3222 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3223 /* XXX Sync Rx LEs here. */ 3224 3225 rxput[MSK_PORT_A] = rxput[MSK_PORT_B] = 0; 3226 3227 rxprog = 0; 3228 for (cons = sc->msk_stat_cons; cons != idx;) { 3229 sd = &sc->msk_stat_ring[cons]; 3230 control = le32toh(sd->msk_control); 3231 if ((control & HW_OWNER) == 0) 3232 break; 3233 /* 3234 * Marvell's FreeBSD driver updates status LE after clearing 3235 * HW_OWNER. However we don't have a way to sync single LE 3236 * with bus_dma(9) API. bus_dma(9) provides a way to sync 3237 * an entire DMA map. So don't sync LE until we have a better 3238 * way to sync LEs. 3239 */ 3240 control &= ~HW_OWNER; 3241 sd->msk_control = htole32(control); 3242 status = le32toh(sd->msk_status); 3243 len = control & STLE_LEN_MASK; 3244 port = (control >> 16) & 0x01; 3245 sc_if = sc->msk_if[port]; 3246 if (sc_if == NULL) { 3247 device_printf(sc->msk_dev, "invalid port opcode " 3248 "0x%08x\n", control & STLE_OP_MASK); 3249 continue; 3250 } 3251 3252 switch (control & STLE_OP_MASK) { 3253 case OP_RXVLAN: 3254 sc_if->msk_vtag = ntohs(len); 3255 break; 3256 case OP_RXCHKSVLAN: 3257 sc_if->msk_vtag = ntohs(len); 3258 break; 3259 case OP_RXSTAT: 3260 if (sc_if->msk_framesize > 3261 (MCLBYTES - MSK_RX_BUF_ALIGN)) 3262 msk_jumbo_rxeof(sc_if, status, len); 3263 else 3264 msk_rxeof(sc_if, status, len); 3265 rxprog++; 3266 /* 3267 * Because there is no way to sync single Rx LE 3268 * put the DMA sync operation off until the end of 3269 * event processing. 3270 */ 3271 rxput[port]++; 3272 /* Update prefetch unit if we've passed water mark. */ 3273 if (rxput[port] >= sc_if->msk_cdata.msk_rx_putwm) { 3274 msk_rxput(sc_if); 3275 rxput[port] = 0; 3276 } 3277 break; 3278 case OP_TXINDEXLE: 3279 if (sc->msk_if[MSK_PORT_A] != NULL) 3280 msk_txeof(sc->msk_if[MSK_PORT_A], 3281 status & STLE_TXA1_MSKL); 3282 if (sc->msk_if[MSK_PORT_B] != NULL) 3283 msk_txeof(sc->msk_if[MSK_PORT_B], 3284 ((status & STLE_TXA2_MSKL) >> 3285 STLE_TXA2_SHIFTL) | 3286 ((len & STLE_TXA2_MSKH) << 3287 STLE_TXA2_SHIFTH)); 3288 break; 3289 default: 3290 device_printf(sc->msk_dev, "unhandled opcode 0x%08x\n", 3291 control & STLE_OP_MASK); 3292 break; 3293 } 3294 MSK_INC(cons, MSK_STAT_RING_CNT); 3295 if (rxprog > sc->msk_process_limit) 3296 break; 3297 } 3298 3299 sc->msk_stat_cons = cons; 3300 /* XXX We should sync status LEs here. See above notes. */ 3301 3302 if (rxput[MSK_PORT_A] > 0) 3303 msk_rxput(sc->msk_if[MSK_PORT_A]); 3304 if (rxput[MSK_PORT_B] > 0) 3305 msk_rxput(sc->msk_if[MSK_PORT_B]); 3306 3307 return (sc->msk_stat_cons != CSR_READ_2(sc, STAT_PUT_IDX)); 3308 } 3309 3310 /* Legacy interrupt handler for shared interrupt. */ 3311 static void 3312 msk_legacy_intr(void *xsc) 3313 { 3314 struct msk_softc *sc; 3315 struct msk_if_softc *sc_if0, *sc_if1; 3316 struct ifnet *ifp0, *ifp1; 3317 uint32_t status; 3318 3319 sc = xsc; 3320 MSK_LOCK(sc); 3321 3322 /* Reading B0_Y2_SP_ISRC2 masks further interrupts. */ 3323 status = CSR_READ_4(sc, B0_Y2_SP_ISRC2); 3324 if (status == 0 || status == 0xffffffff || sc->msk_suspended != 0 || 3325 (status & sc->msk_intrmask) == 0) { 3326 CSR_WRITE_4(sc, B0_Y2_SP_ICR, 2); 3327 return; 3328 } 3329 3330 sc_if0 = sc->msk_if[MSK_PORT_A]; 3331 sc_if1 = sc->msk_if[MSK_PORT_B]; 3332 ifp0 = ifp1 = NULL; 3333 if (sc_if0 != NULL) 3334 ifp0 = sc_if0->msk_ifp; 3335 if (sc_if1 != NULL) 3336 ifp1 = sc_if1->msk_ifp; 3337 3338 if ((status & Y2_IS_IRQ_PHY1) != 0 && sc_if0 != NULL) 3339 msk_intr_phy(sc_if0); 3340 if ((status & Y2_IS_IRQ_PHY2) != 0 && sc_if1 != NULL) 3341 msk_intr_phy(sc_if1); 3342 if ((status & Y2_IS_IRQ_MAC1) != 0 && sc_if0 != NULL) 3343 msk_intr_gmac(sc_if0); 3344 if ((status & Y2_IS_IRQ_MAC2) != 0 && sc_if1 != NULL) 3345 msk_intr_gmac(sc_if1); 3346 if ((status & (Y2_IS_CHK_RX1 | Y2_IS_CHK_RX2)) != 0) { 3347 device_printf(sc->msk_dev, "Rx descriptor error\n"); 3348 sc->msk_intrmask &= ~(Y2_IS_CHK_RX1 | Y2_IS_CHK_RX2); 3349 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask); 3350 CSR_READ_4(sc, B0_IMSK); 3351 } 3352 if ((status & (Y2_IS_CHK_TXA1 | Y2_IS_CHK_TXA2)) != 0) { 3353 device_printf(sc->msk_dev, "Tx descriptor error\n"); 3354 sc->msk_intrmask &= ~(Y2_IS_CHK_TXA1 | Y2_IS_CHK_TXA2); 3355 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask); 3356 CSR_READ_4(sc, B0_IMSK); 3357 } 3358 if ((status & Y2_IS_HW_ERR) != 0) 3359 msk_intr_hwerr(sc); 3360 3361 while (msk_handle_events(sc) != 0) 3362 ; 3363 if ((status & Y2_IS_STAT_BMU) != 0) 3364 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_CLR_IRQ); 3365 3366 /* Reenable interrupts. */ 3367 CSR_WRITE_4(sc, B0_Y2_SP_ICR, 2); 3368 3369 if (ifp0 != NULL && (ifp0->if_drv_flags & IFF_DRV_RUNNING) != 0 && 3370 !IFQ_DRV_IS_EMPTY(&ifp0->if_snd)) 3371 taskqueue_enqueue(taskqueue_fast, &sc_if0->msk_tx_task); 3372 if (ifp1 != NULL && (ifp1->if_drv_flags & IFF_DRV_RUNNING) != 0 && 3373 !IFQ_DRV_IS_EMPTY(&ifp1->if_snd)) 3374 taskqueue_enqueue(taskqueue_fast, &sc_if1->msk_tx_task); 3375 3376 MSK_UNLOCK(sc); 3377 } 3378 3379 static int 3380 msk_intr(void *xsc) 3381 { 3382 struct msk_softc *sc; 3383 uint32_t status; 3384 3385 sc = xsc; 3386 status = CSR_READ_4(sc, B0_Y2_SP_ISRC2); 3387 /* Reading B0_Y2_SP_ISRC2 masks further interrupts. */ 3388 if (status == 0 || status == 0xffffffff) { 3389 CSR_WRITE_4(sc, B0_Y2_SP_ICR, 2); 3390 return (FILTER_STRAY); 3391 } 3392 3393 taskqueue_enqueue(sc->msk_tq, &sc->msk_int_task); 3394 return (FILTER_HANDLED); 3395 } 3396 3397 static void 3398 msk_int_task(void *arg, int pending) 3399 { 3400 struct msk_softc *sc; 3401 struct msk_if_softc *sc_if0, *sc_if1; 3402 struct ifnet *ifp0, *ifp1; 3403 uint32_t status; 3404 int domore; 3405 3406 sc = arg; 3407 MSK_LOCK(sc); 3408 3409 /* Get interrupt source. */ 3410 status = CSR_READ_4(sc, B0_ISRC); 3411 if (status == 0 || status == 0xffffffff || sc->msk_suspended != 0 || 3412 (status & sc->msk_intrmask) == 0) 3413 goto done; 3414 3415 sc_if0 = sc->msk_if[MSK_PORT_A]; 3416 sc_if1 = sc->msk_if[MSK_PORT_B]; 3417 ifp0 = ifp1 = NULL; 3418 if (sc_if0 != NULL) 3419 ifp0 = sc_if0->msk_ifp; 3420 if (sc_if1 != NULL) 3421 ifp1 = sc_if1->msk_ifp; 3422 3423 if ((status & Y2_IS_IRQ_PHY1) != 0 && sc_if0 != NULL) 3424 msk_intr_phy(sc_if0); 3425 if ((status & Y2_IS_IRQ_PHY2) != 0 && sc_if1 != NULL) 3426 msk_intr_phy(sc_if1); 3427 if ((status & Y2_IS_IRQ_MAC1) != 0 && sc_if0 != NULL) 3428 msk_intr_gmac(sc_if0); 3429 if ((status & Y2_IS_IRQ_MAC2) != 0 && sc_if1 != NULL) 3430 msk_intr_gmac(sc_if1); 3431 if ((status & (Y2_IS_CHK_RX1 | Y2_IS_CHK_RX2)) != 0) { 3432 device_printf(sc->msk_dev, "Rx descriptor error\n"); 3433 sc->msk_intrmask &= ~(Y2_IS_CHK_RX1 | Y2_IS_CHK_RX2); 3434 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask); 3435 CSR_READ_4(sc, B0_IMSK); 3436 } 3437 if ((status & (Y2_IS_CHK_TXA1 | Y2_IS_CHK_TXA2)) != 0) { 3438 device_printf(sc->msk_dev, "Tx descriptor error\n"); 3439 sc->msk_intrmask &= ~(Y2_IS_CHK_TXA1 | Y2_IS_CHK_TXA2); 3440 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask); 3441 CSR_READ_4(sc, B0_IMSK); 3442 } 3443 if ((status & Y2_IS_HW_ERR) != 0) 3444 msk_intr_hwerr(sc); 3445 3446 domore = msk_handle_events(sc); 3447 if ((status & Y2_IS_STAT_BMU) != 0) 3448 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_CLR_IRQ); 3449 3450 if (ifp0 != NULL && (ifp0->if_drv_flags & IFF_DRV_RUNNING) != 0 && 3451 !IFQ_DRV_IS_EMPTY(&ifp0->if_snd)) 3452 taskqueue_enqueue(taskqueue_fast, &sc_if0->msk_tx_task); 3453 if (ifp1 != NULL && (ifp1->if_drv_flags & IFF_DRV_RUNNING) != 0 && 3454 !IFQ_DRV_IS_EMPTY(&ifp1->if_snd)) 3455 taskqueue_enqueue(taskqueue_fast, &sc_if1->msk_tx_task); 3456 3457 if (domore > 0) { 3458 taskqueue_enqueue(sc->msk_tq, &sc->msk_int_task); 3459 MSK_UNLOCK(sc); 3460 return; 3461 } 3462 done: 3463 MSK_UNLOCK(sc); 3464 3465 /* Reenable interrupts. */ 3466 CSR_WRITE_4(sc, B0_Y2_SP_ICR, 2); 3467 } 3468 3469 static void 3470 msk_init(void *xsc) 3471 { 3472 struct msk_if_softc *sc_if = xsc; 3473 3474 MSK_IF_LOCK(sc_if); 3475 msk_init_locked(sc_if); 3476 MSK_IF_UNLOCK(sc_if); 3477 } 3478 3479 static void 3480 msk_init_locked(struct msk_if_softc *sc_if) 3481 { 3482 struct msk_softc *sc; 3483 struct ifnet *ifp; 3484 struct mii_data *mii; 3485 uint16_t eaddr[ETHER_ADDR_LEN / 2]; 3486 uint16_t gmac; 3487 int error, i; 3488 3489 MSK_IF_LOCK_ASSERT(sc_if); 3490 3491 ifp = sc_if->msk_ifp; 3492 sc = sc_if->msk_softc; 3493 mii = device_get_softc(sc_if->msk_miibus); 3494 3495 error = 0; 3496 /* Cancel pending I/O and free all Rx/Tx buffers. */ 3497 msk_stop(sc_if); 3498 3499 if (ifp->if_mtu < ETHERMTU) 3500 sc_if->msk_framesize = ETHERMTU; 3501 else 3502 sc_if->msk_framesize = ifp->if_mtu; 3503 sc_if->msk_framesize += ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 3504 if (ifp->if_mtu > ETHERMTU && 3505 sc_if->msk_softc->msk_hw_id == CHIP_ID_YUKON_EC_U) { 3506 /* 3507 * In Yukon EC Ultra, TSO & checksum offload is not 3508 * supported for jumbo frame. 3509 */ 3510 ifp->if_hwassist &= ~(MSK_CSUM_FEATURES | CSUM_TSO); 3511 ifp->if_capenable &= ~(IFCAP_TSO4 | IFCAP_TXCSUM); 3512 } 3513 3514 /* 3515 * Initialize GMAC first. 3516 * Without this initialization, Rx MAC did not work as expected 3517 * and Rx MAC garbled status LEs and it resulted in out-of-order 3518 * or duplicated frame delivery which in turn showed very poor 3519 * Rx performance.(I had to write a packet analysis code that 3520 * could be embeded in driver to diagnose this issue.) 3521 * I've spent almost 2 months to fix this issue. If I have had 3522 * datasheet for Yukon II I wouldn't have encountered this. :-( 3523 */ 3524 gmac = GM_GPCR_SPEED_100 | GM_GPCR_SPEED_1000 | GM_GPCR_DUP_FULL; 3525 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, gmac); 3526 3527 /* Dummy read the Interrupt Source Register. */ 3528 CSR_READ_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_SRC)); 3529 3530 /* Clear MIB stats. */ 3531 msk_stats_clear(sc_if); 3532 3533 /* Disable FCS. */ 3534 GMAC_WRITE_2(sc, sc_if->msk_port, GM_RX_CTRL, GM_RXCR_CRC_DIS); 3535 3536 /* Setup Transmit Control Register. */ 3537 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF)); 3538 3539 /* Setup Transmit Flow Control Register. */ 3540 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_FLOW_CTRL, 0xffff); 3541 3542 /* Setup Transmit Parameter Register. */ 3543 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_PARAM, 3544 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) | TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) | 3545 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) | TX_BACK_OFF_LIM(TX_BOF_LIM_DEF)); 3546 3547 gmac = DATA_BLIND_VAL(DATA_BLIND_DEF) | 3548 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF); 3549 3550 if (ifp->if_mtu > ETHERMTU) 3551 gmac |= GM_SMOD_JUMBO_ENA; 3552 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SERIAL_MODE, gmac); 3553 3554 /* Set station address. */ 3555 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN); 3556 for (i = 0; i < ETHER_ADDR_LEN /2; i++) 3557 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_1L + i * 4, 3558 eaddr[i]); 3559 for (i = 0; i < ETHER_ADDR_LEN /2; i++) 3560 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_2L + i * 4, 3561 eaddr[i]); 3562 3563 /* Disable interrupts for counter overflows. */ 3564 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_IRQ_MSK, 0); 3565 GMAC_WRITE_2(sc, sc_if->msk_port, GM_RX_IRQ_MSK, 0); 3566 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TR_IRQ_MSK, 0); 3567 3568 /* Configure Rx MAC FIFO. */ 3569 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), GMF_RST_SET); 3570 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), GMF_RST_CLR); 3571 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), 3572 GMF_OPER_ON | GMF_RX_F_FL_ON); 3573 3574 /* Set receive filter. */ 3575 msk_rxfilter(sc_if); 3576 3577 /* Flush Rx MAC FIFO on any flow control or error. */ 3578 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_FL_MSK), 3579 GMR_FS_ANY_ERR); 3580 3581 /* 3582 * Set Rx FIFO flush threshold to 64 bytes + 1 FIFO word 3583 * due to hardware hang on receipt of pause frames. 3584 */ 3585 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_FL_THR), 3586 RX_GMF_FL_THR_DEF + 1); 3587 3588 /* Configure Tx MAC FIFO. */ 3589 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_RST_SET); 3590 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_RST_CLR); 3591 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_OPER_ON); 3592 3593 /* Configure hardware VLAN tag insertion/stripping. */ 3594 msk_setvlan(sc_if, ifp); 3595 3596 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) == 0) { 3597 /* Set Rx Pause threshould. */ 3598 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, RX_GMF_LP_THR), 3599 MSK_ECU_LLPP); 3600 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, RX_GMF_UP_THR), 3601 MSK_ECU_ULPP); 3602 if (ifp->if_mtu > ETHERMTU) { 3603 /* 3604 * Set Tx GMAC FIFO Almost Empty Threshold. 3605 */ 3606 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_AE_THR), 3607 MSK_ECU_JUMBO_WM << 16 | MSK_ECU_AE_THR); 3608 /* Disable Store & Forward mode for Tx. */ 3609 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 3610 TX_JUMBO_ENA | TX_STFW_DIS); 3611 } else { 3612 /* Enable Store & Forward mode for Tx. */ 3613 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 3614 TX_JUMBO_DIS | TX_STFW_ENA); 3615 } 3616 } 3617 3618 /* 3619 * Disable Force Sync bit and Alloc bit in Tx RAM interface 3620 * arbiter as we don't use Sync Tx queue. 3621 */ 3622 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, TXA_CTRL), 3623 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC); 3624 /* Enable the RAM Interface Arbiter. */ 3625 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, TXA_CTRL), TXA_ENA_ARB); 3626 3627 /* Setup RAM buffer. */ 3628 msk_set_rambuffer(sc_if); 3629 3630 /* Disable Tx sync Queue. */ 3631 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txsq, RB_CTRL), RB_RST_SET); 3632 3633 /* Setup Tx Queue Bus Memory Interface. */ 3634 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_CLR_RESET); 3635 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_OPER_INIT); 3636 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_FIFO_OP_ON); 3637 CSR_WRITE_2(sc, Q_ADDR(sc_if->msk_txq, Q_WM), MSK_BMU_TX_WM); 3638 if (sc->msk_hw_id == CHIP_ID_YUKON_EC_U && 3639 sc->msk_hw_rev == CHIP_REV_YU_EC_U_A0) { 3640 /* Fix for Yukon-EC Ultra: set BMU FIFO level */ 3641 CSR_WRITE_2(sc, Q_ADDR(sc_if->msk_txq, Q_AL), MSK_ECU_TXFF_LEV); 3642 } 3643 3644 /* Setup Rx Queue Bus Memory Interface. */ 3645 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_CLR_RESET); 3646 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_OPER_INIT); 3647 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_FIFO_OP_ON); 3648 CSR_WRITE_2(sc, Q_ADDR(sc_if->msk_rxq, Q_WM), MSK_BMU_RX_WM); 3649 if (sc->msk_hw_id == CHIP_ID_YUKON_EC_U && 3650 sc->msk_hw_rev >= CHIP_REV_YU_EC_U_A1) { 3651 /* MAC Rx RAM Read is controlled by hardware. */ 3652 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_F), F_M_RX_RAM_DIS); 3653 } 3654 3655 msk_set_prefetch(sc, sc_if->msk_txq, 3656 sc_if->msk_rdata.msk_tx_ring_paddr, MSK_TX_RING_CNT - 1); 3657 msk_init_tx_ring(sc_if); 3658 3659 /* Disable Rx checksum offload and RSS hash. */ 3660 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), 3661 BMU_DIS_RX_CHKSUM | BMU_DIS_RX_RSS_HASH); 3662 if (sc_if->msk_framesize > (MCLBYTES - MSK_RX_BUF_ALIGN)) { 3663 msk_set_prefetch(sc, sc_if->msk_rxq, 3664 sc_if->msk_rdata.msk_jumbo_rx_ring_paddr, 3665 MSK_JUMBO_RX_RING_CNT - 1); 3666 error = msk_init_jumbo_rx_ring(sc_if); 3667 } else { 3668 msk_set_prefetch(sc, sc_if->msk_rxq, 3669 sc_if->msk_rdata.msk_rx_ring_paddr, 3670 MSK_RX_RING_CNT - 1); 3671 error = msk_init_rx_ring(sc_if); 3672 } 3673 if (error != 0) { 3674 device_printf(sc_if->msk_if_dev, 3675 "initialization failed: no memory for Rx buffers\n"); 3676 msk_stop(sc_if); 3677 return; 3678 } 3679 3680 /* Configure interrupt handling. */ 3681 if (sc_if->msk_port == MSK_PORT_A) { 3682 sc->msk_intrmask |= Y2_IS_PORT_A; 3683 sc->msk_intrhwemask |= Y2_HWE_L1_MASK; 3684 } else { 3685 sc->msk_intrmask |= Y2_IS_PORT_B; 3686 sc->msk_intrhwemask |= Y2_HWE_L2_MASK; 3687 } 3688 CSR_WRITE_4(sc, B0_HWE_IMSK, sc->msk_intrhwemask); 3689 CSR_READ_4(sc, B0_HWE_IMSK); 3690 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask); 3691 CSR_READ_4(sc, B0_IMSK); 3692 3693 sc_if->msk_link = 0; 3694 mii_mediachg(mii); 3695 3696 ifp->if_drv_flags |= IFF_DRV_RUNNING; 3697 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3698 3699 callout_reset(&sc_if->msk_tick_ch, hz, msk_tick, sc_if); 3700 } 3701 3702 static void 3703 msk_set_rambuffer(struct msk_if_softc *sc_if) 3704 { 3705 struct msk_softc *sc; 3706 int ltpp, utpp; 3707 3708 sc = sc_if->msk_softc; 3709 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) == 0) 3710 return; 3711 3712 /* Setup Rx Queue. */ 3713 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_RST_CLR); 3714 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_START), 3715 sc->msk_rxqstart[sc_if->msk_port] / 8); 3716 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_END), 3717 sc->msk_rxqend[sc_if->msk_port] / 8); 3718 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_WP), 3719 sc->msk_rxqstart[sc_if->msk_port] / 8); 3720 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_RP), 3721 sc->msk_rxqstart[sc_if->msk_port] / 8); 3722 3723 utpp = (sc->msk_rxqend[sc_if->msk_port] + 1 - 3724 sc->msk_rxqstart[sc_if->msk_port] - MSK_RB_ULPP) / 8; 3725 ltpp = (sc->msk_rxqend[sc_if->msk_port] + 1 - 3726 sc->msk_rxqstart[sc_if->msk_port] - MSK_RB_LLPP_B) / 8; 3727 if (sc->msk_rxqsize < MSK_MIN_RXQ_SIZE) 3728 ltpp += (MSK_RB_LLPP_B - MSK_RB_LLPP_S) / 8; 3729 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_RX_UTPP), utpp); 3730 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_RX_LTPP), ltpp); 3731 /* Set Rx priority(RB_RX_UTHP/RB_RX_LTHP) thresholds? */ 3732 3733 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_ENA_OP_MD); 3734 CSR_READ_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL)); 3735 3736 /* Setup Tx Queue. */ 3737 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_RST_CLR); 3738 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_START), 3739 sc->msk_txqstart[sc_if->msk_port] / 8); 3740 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_END), 3741 sc->msk_txqend[sc_if->msk_port] / 8); 3742 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_WP), 3743 sc->msk_txqstart[sc_if->msk_port] / 8); 3744 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_RP), 3745 sc->msk_txqstart[sc_if->msk_port] / 8); 3746 /* Enable Store & Forward for Tx side. */ 3747 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_ENA_STFWD); 3748 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_ENA_OP_MD); 3749 CSR_READ_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL)); 3750 } 3751 3752 static void 3753 msk_set_prefetch(struct msk_softc *sc, int qaddr, bus_addr_t addr, 3754 uint32_t count) 3755 { 3756 3757 /* Reset the prefetch unit. */ 3758 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG), 3759 PREF_UNIT_RST_SET); 3760 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG), 3761 PREF_UNIT_RST_CLR); 3762 /* Set LE base address. */ 3763 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_ADDR_LOW_REG), 3764 MSK_ADDR_LO(addr)); 3765 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_ADDR_HI_REG), 3766 MSK_ADDR_HI(addr)); 3767 /* Set the list last index. */ 3768 CSR_WRITE_2(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_LAST_IDX_REG), 3769 count); 3770 /* Turn on prefetch unit. */ 3771 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG), 3772 PREF_UNIT_OP_ON); 3773 /* Dummy read to ensure write. */ 3774 CSR_READ_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG)); 3775 } 3776 3777 static void 3778 msk_stop(struct msk_if_softc *sc_if) 3779 { 3780 struct msk_softc *sc; 3781 struct msk_txdesc *txd; 3782 struct msk_rxdesc *rxd; 3783 struct msk_rxdesc *jrxd; 3784 struct ifnet *ifp; 3785 uint32_t val; 3786 int i; 3787 3788 MSK_IF_LOCK_ASSERT(sc_if); 3789 sc = sc_if->msk_softc; 3790 ifp = sc_if->msk_ifp; 3791 3792 callout_stop(&sc_if->msk_tick_ch); 3793 sc_if->msk_watchdog_timer = 0; 3794 3795 /* Disable interrupts. */ 3796 if (sc_if->msk_port == MSK_PORT_A) { 3797 sc->msk_intrmask &= ~Y2_IS_PORT_A; 3798 sc->msk_intrhwemask &= ~Y2_HWE_L1_MASK; 3799 } else { 3800 sc->msk_intrmask &= ~Y2_IS_PORT_B; 3801 sc->msk_intrhwemask &= ~Y2_HWE_L2_MASK; 3802 } 3803 CSR_WRITE_4(sc, B0_HWE_IMSK, sc->msk_intrhwemask); 3804 CSR_READ_4(sc, B0_HWE_IMSK); 3805 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask); 3806 CSR_READ_4(sc, B0_IMSK); 3807 3808 /* Disable Tx/Rx MAC. */ 3809 val = GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL); 3810 val &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA); 3811 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, val); 3812 /* Read again to ensure writing. */ 3813 GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL); 3814 /* Update stats and clear counters. */ 3815 msk_stats_update(sc_if); 3816 3817 /* Stop Tx BMU. */ 3818 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_STOP); 3819 val = CSR_READ_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR)); 3820 for (i = 0; i < MSK_TIMEOUT; i++) { 3821 if ((val & (BMU_STOP | BMU_IDLE)) == 0) { 3822 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), 3823 BMU_STOP); 3824 val = CSR_READ_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR)); 3825 } else 3826 break; 3827 DELAY(1); 3828 } 3829 if (i == MSK_TIMEOUT) 3830 device_printf(sc_if->msk_if_dev, "Tx BMU stop failed\n"); 3831 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), 3832 RB_RST_SET | RB_DIS_OP_MD); 3833 3834 /* Disable all GMAC interrupt. */ 3835 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_MSK), 0); 3836 /* Disable PHY interrupt. */ 3837 msk_phy_writereg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_MASK, 0); 3838 3839 /* Disable the RAM Interface Arbiter. */ 3840 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, TXA_CTRL), TXA_DIS_ARB); 3841 3842 /* Reset the PCI FIFO of the async Tx queue */ 3843 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), 3844 BMU_RST_SET | BMU_FIFO_RST); 3845 3846 /* Reset the Tx prefetch units. */ 3847 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(sc_if->msk_txq, PREF_UNIT_CTRL_REG), 3848 PREF_UNIT_RST_SET); 3849 3850 /* Reset the RAM Buffer async Tx queue. */ 3851 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_RST_SET); 3852 3853 /* Reset Tx MAC FIFO. */ 3854 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_RST_SET); 3855 /* Set Pause Off. */ 3856 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_PAUSE_OFF); 3857 3858 /* 3859 * The Rx Stop command will not work for Yukon-2 if the BMU does not 3860 * reach the end of packet and since we can't make sure that we have 3861 * incoming data, we must reset the BMU while it is not during a DMA 3862 * transfer. Since it is possible that the Rx path is still active, 3863 * the Rx RAM buffer will be stopped first, so any possible incoming 3864 * data will not trigger a DMA. After the RAM buffer is stopped, the 3865 * BMU is polled until any DMA in progress is ended and only then it 3866 * will be reset. 3867 */ 3868 3869 /* Disable the RAM Buffer receive queue. */ 3870 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_DIS_OP_MD); 3871 for (i = 0; i < MSK_TIMEOUT; i++) { 3872 if (CSR_READ_1(sc, RB_ADDR(sc_if->msk_rxq, Q_RSL)) == 3873 CSR_READ_1(sc, RB_ADDR(sc_if->msk_rxq, Q_RL))) 3874 break; 3875 DELAY(1); 3876 } 3877 if (i == MSK_TIMEOUT) 3878 device_printf(sc_if->msk_if_dev, "Rx BMU stop failed\n"); 3879 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), 3880 BMU_RST_SET | BMU_FIFO_RST); 3881 /* Reset the Rx prefetch unit. */ 3882 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_CTRL_REG), 3883 PREF_UNIT_RST_SET); 3884 /* Reset the RAM Buffer receive queue. */ 3885 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_RST_SET); 3886 /* Reset Rx MAC FIFO. */ 3887 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), GMF_RST_SET); 3888 3889 /* Free Rx and Tx mbufs still in the queues. */ 3890 for (i = 0; i < MSK_RX_RING_CNT; i++) { 3891 rxd = &sc_if->msk_cdata.msk_rxdesc[i]; 3892 if (rxd->rx_m != NULL) { 3893 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_tag, 3894 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 3895 bus_dmamap_unload(sc_if->msk_cdata.msk_rx_tag, 3896 rxd->rx_dmamap); 3897 m_freem(rxd->rx_m); 3898 rxd->rx_m = NULL; 3899 } 3900 } 3901 for (i = 0; i < MSK_JUMBO_RX_RING_CNT; i++) { 3902 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[i]; 3903 if (jrxd->rx_m != NULL) { 3904 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_tag, 3905 jrxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 3906 bus_dmamap_unload(sc_if->msk_cdata.msk_jumbo_rx_tag, 3907 jrxd->rx_dmamap); 3908 m_freem(jrxd->rx_m); 3909 jrxd->rx_m = NULL; 3910 } 3911 } 3912 for (i = 0; i < MSK_TX_RING_CNT; i++) { 3913 txd = &sc_if->msk_cdata.msk_txdesc[i]; 3914 if (txd->tx_m != NULL) { 3915 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_tag, 3916 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 3917 bus_dmamap_unload(sc_if->msk_cdata.msk_tx_tag, 3918 txd->tx_dmamap); 3919 m_freem(txd->tx_m); 3920 txd->tx_m = NULL; 3921 } 3922 } 3923 3924 /* 3925 * Mark the interface down. 3926 */ 3927 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 3928 sc_if->msk_link = 0; 3929 } 3930 3931 /* 3932 * When GM_PAR_MIB_CLR bit of GM_PHY_ADDR is set, reading lower 3933 * counter clears high 16 bits of the counter such that accessing 3934 * lower 16 bits should be the last operation. 3935 */ 3936 #define MSK_READ_MIB32(x, y) \ 3937 (((uint32_t)GMAC_READ_2(sc, x, (y) + 4)) << 16) + \ 3938 (uint32_t)GMAC_READ_2(sc, x, y) 3939 #define MSK_READ_MIB64(x, y) \ 3940 (((uint64_t)MSK_READ_MIB32(x, (y) + 8)) << 32) + \ 3941 (uint64_t)MSK_READ_MIB32(x, y) 3942 3943 static void 3944 msk_stats_clear(struct msk_if_softc *sc_if) 3945 { 3946 struct msk_softc *sc; 3947 uint32_t reg; 3948 uint16_t gmac; 3949 int i; 3950 3951 MSK_IF_LOCK_ASSERT(sc_if); 3952 3953 sc = sc_if->msk_softc; 3954 /* Set MIB Clear Counter Mode. */ 3955 gmac = GMAC_READ_2(sc, sc_if->msk_port, GM_PHY_ADDR); 3956 GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac | GM_PAR_MIB_CLR); 3957 /* Read all MIB Counters with Clear Mode set. */ 3958 for (i = GM_RXF_UC_OK; i <= GM_TXE_FIFO_UR; i++) 3959 reg = MSK_READ_MIB32(sc_if->msk_port, i); 3960 /* Clear MIB Clear Counter Mode. */ 3961 gmac &= ~GM_PAR_MIB_CLR; 3962 GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac); 3963 } 3964 3965 static void 3966 msk_stats_update(struct msk_if_softc *sc_if) 3967 { 3968 struct msk_softc *sc; 3969 struct ifnet *ifp; 3970 struct msk_hw_stats *stats; 3971 uint16_t gmac; 3972 uint32_t reg; 3973 3974 MSK_IF_LOCK_ASSERT(sc_if); 3975 3976 ifp = sc_if->msk_ifp; 3977 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 3978 return; 3979 sc = sc_if->msk_softc; 3980 stats = &sc_if->msk_stats; 3981 /* Set MIB Clear Counter Mode. */ 3982 gmac = GMAC_READ_2(sc, sc_if->msk_port, GM_PHY_ADDR); 3983 GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac | GM_PAR_MIB_CLR); 3984 3985 /* Rx stats. */ 3986 stats->rx_ucast_frames += 3987 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_UC_OK); 3988 stats->rx_bcast_frames += 3989 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_BC_OK); 3990 stats->rx_pause_frames += 3991 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_MPAUSE); 3992 stats->rx_mcast_frames += 3993 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_MC_OK); 3994 stats->rx_crc_errs += 3995 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_FCS_ERR); 3996 reg = MSK_READ_MIB32(sc_if->msk_port, GM_RXF_SPARE1); 3997 stats->rx_good_octets += 3998 MSK_READ_MIB64(sc_if->msk_port, GM_RXO_OK_LO); 3999 stats->rx_bad_octets += 4000 MSK_READ_MIB64(sc_if->msk_port, GM_RXO_ERR_LO); 4001 stats->rx_runts += 4002 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_SHT); 4003 stats->rx_runt_errs += 4004 MSK_READ_MIB32(sc_if->msk_port, GM_RXE_FRAG); 4005 stats->rx_pkts_64 += 4006 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_64B); 4007 stats->rx_pkts_65_127 += 4008 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_127B); 4009 stats->rx_pkts_128_255 += 4010 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_255B); 4011 stats->rx_pkts_256_511 += 4012 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_511B); 4013 stats->rx_pkts_512_1023 += 4014 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_1023B); 4015 stats->rx_pkts_1024_1518 += 4016 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_1518B); 4017 stats->rx_pkts_1519_max += 4018 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_MAX_SZ); 4019 stats->rx_pkts_too_long += 4020 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_LNG_ERR); 4021 stats->rx_pkts_jabbers += 4022 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_JAB_PKT); 4023 reg = MSK_READ_MIB32(sc_if->msk_port, GM_RXF_SPARE2); 4024 stats->rx_fifo_oflows += 4025 MSK_READ_MIB32(sc_if->msk_port, GM_RXE_FIFO_OV); 4026 reg = MSK_READ_MIB32(sc_if->msk_port, GM_RXF_SPARE3); 4027 4028 /* Tx stats. */ 4029 stats->tx_ucast_frames += 4030 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_UC_OK); 4031 stats->tx_bcast_frames += 4032 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_BC_OK); 4033 stats->tx_pause_frames += 4034 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_MPAUSE); 4035 stats->tx_mcast_frames += 4036 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_MC_OK); 4037 stats->tx_octets += 4038 MSK_READ_MIB64(sc_if->msk_port, GM_TXO_OK_LO); 4039 stats->tx_pkts_64 += 4040 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_64B); 4041 stats->tx_pkts_65_127 += 4042 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_127B); 4043 stats->tx_pkts_128_255 += 4044 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_255B); 4045 stats->tx_pkts_256_511 += 4046 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_511B); 4047 stats->tx_pkts_512_1023 += 4048 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_1023B); 4049 stats->tx_pkts_1024_1518 += 4050 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_1518B); 4051 stats->tx_pkts_1519_max += 4052 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_MAX_SZ); 4053 reg = MSK_READ_MIB32(sc_if->msk_port, GM_TXF_SPARE1); 4054 stats->tx_colls += 4055 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_COL); 4056 stats->tx_late_colls += 4057 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_LAT_COL); 4058 stats->tx_excess_colls += 4059 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_ABO_COL); 4060 stats->tx_multi_colls += 4061 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_MUL_COL); 4062 stats->tx_single_colls += 4063 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_SNG_COL); 4064 stats->tx_underflows += 4065 MSK_READ_MIB32(sc_if->msk_port, GM_TXE_FIFO_UR); 4066 /* Clear MIB Clear Counter Mode. */ 4067 gmac &= ~GM_PAR_MIB_CLR; 4068 GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac); 4069 } 4070 4071 static int 4072 msk_sysctl_stat32(SYSCTL_HANDLER_ARGS) 4073 { 4074 struct msk_softc *sc; 4075 struct msk_if_softc *sc_if; 4076 uint32_t result, *stat; 4077 int off; 4078 4079 sc_if = (struct msk_if_softc *)arg1; 4080 sc = sc_if->msk_softc; 4081 off = arg2; 4082 stat = (uint32_t *)((uint8_t *)&sc_if->msk_stats + off); 4083 4084 MSK_IF_LOCK(sc_if); 4085 result = MSK_READ_MIB32(sc_if->msk_port, GM_MIB_CNT_BASE + off * 2); 4086 result += *stat; 4087 MSK_IF_UNLOCK(sc_if); 4088 4089 return (sysctl_handle_int(oidp, &result, 0, req)); 4090 } 4091 4092 static int 4093 msk_sysctl_stat64(SYSCTL_HANDLER_ARGS) 4094 { 4095 struct msk_softc *sc; 4096 struct msk_if_softc *sc_if; 4097 uint64_t result, *stat; 4098 int off; 4099 4100 sc_if = (struct msk_if_softc *)arg1; 4101 sc = sc_if->msk_softc; 4102 off = arg2; 4103 stat = (uint64_t *)((uint8_t *)&sc_if->msk_stats + off); 4104 4105 MSK_IF_LOCK(sc_if); 4106 result = MSK_READ_MIB64(sc_if->msk_port, GM_MIB_CNT_BASE + off * 2); 4107 result += *stat; 4108 MSK_IF_UNLOCK(sc_if); 4109 4110 return (sysctl_handle_quad(oidp, &result, 0, req)); 4111 } 4112 4113 #undef MSK_READ_MIB32 4114 #undef MSK_READ_MIB64 4115 4116 #define MSK_SYSCTL_STAT32(sc, c, o, p, n, d) \ 4117 SYSCTL_ADD_PROC(c, p, OID_AUTO, o, CTLTYPE_UINT | CTLFLAG_RD, \ 4118 sc, offsetof(struct msk_hw_stats, n), msk_sysctl_stat32, \ 4119 "IU", d) 4120 #define MSK_SYSCTL_STAT64(sc, c, o, p, n, d) \ 4121 SYSCTL_ADD_PROC(c, p, OID_AUTO, o, CTLTYPE_UINT | CTLFLAG_RD, \ 4122 sc, offsetof(struct msk_hw_stats, n), msk_sysctl_stat64, \ 4123 "Q", d) 4124 4125 static void 4126 msk_sysctl_node(struct msk_if_softc *sc_if) 4127 { 4128 struct sysctl_ctx_list *ctx; 4129 struct sysctl_oid_list *child, *schild; 4130 struct sysctl_oid *tree; 4131 4132 ctx = device_get_sysctl_ctx(sc_if->msk_if_dev); 4133 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc_if->msk_if_dev)); 4134 4135 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD, 4136 NULL, "MSK Statistics"); 4137 schild = child = SYSCTL_CHILDREN(tree); 4138 tree = SYSCTL_ADD_NODE(ctx, schild, OID_AUTO, "rx", CTLFLAG_RD, 4139 NULL, "MSK RX Statistics"); 4140 child = SYSCTL_CHILDREN(tree); 4141 MSK_SYSCTL_STAT32(sc_if, ctx, "ucast_frames", 4142 child, rx_ucast_frames, "Good unicast frames"); 4143 MSK_SYSCTL_STAT32(sc_if, ctx, "bcast_frames", 4144 child, rx_bcast_frames, "Good broadcast frames"); 4145 MSK_SYSCTL_STAT32(sc_if, ctx, "pause_frames", 4146 child, rx_pause_frames, "Pause frames"); 4147 MSK_SYSCTL_STAT32(sc_if, ctx, "mcast_frames", 4148 child, rx_mcast_frames, "Multicast frames"); 4149 MSK_SYSCTL_STAT32(sc_if, ctx, "crc_errs", 4150 child, rx_crc_errs, "CRC errors"); 4151 MSK_SYSCTL_STAT64(sc_if, ctx, "good_octets", 4152 child, rx_good_octets, "Good octets"); 4153 MSK_SYSCTL_STAT64(sc_if, ctx, "bad_octets", 4154 child, rx_bad_octets, "Bad octets"); 4155 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_64", 4156 child, rx_pkts_64, "64 bytes frames"); 4157 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_65_127", 4158 child, rx_pkts_65_127, "65 to 127 bytes frames"); 4159 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_128_255", 4160 child, rx_pkts_128_255, "128 to 255 bytes frames"); 4161 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_256_511", 4162 child, rx_pkts_256_511, "256 to 511 bytes frames"); 4163 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_512_1023", 4164 child, rx_pkts_512_1023, "512 to 1023 bytes frames"); 4165 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_1024_1518", 4166 child, rx_pkts_1024_1518, "1024 to 1518 bytes frames"); 4167 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_1519_max", 4168 child, rx_pkts_1519_max, "1519 to max frames"); 4169 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_too_long", 4170 child, rx_pkts_too_long, "frames too long"); 4171 MSK_SYSCTL_STAT32(sc_if, ctx, "jabbers", 4172 child, rx_pkts_jabbers, "Jabber errors"); 4173 MSK_SYSCTL_STAT32(sc_if, ctx, "overflows", 4174 child, rx_fifo_oflows, "FIFO overflows"); 4175 4176 tree = SYSCTL_ADD_NODE(ctx, schild, OID_AUTO, "tx", CTLFLAG_RD, 4177 NULL, "MSK TX Statistics"); 4178 child = SYSCTL_CHILDREN(tree); 4179 MSK_SYSCTL_STAT32(sc_if, ctx, "ucast_frames", 4180 child, tx_ucast_frames, "Unicast frames"); 4181 MSK_SYSCTL_STAT32(sc_if, ctx, "bcast_frames", 4182 child, tx_bcast_frames, "Broadcast frames"); 4183 MSK_SYSCTL_STAT32(sc_if, ctx, "pause_frames", 4184 child, tx_pause_frames, "Pause frames"); 4185 MSK_SYSCTL_STAT32(sc_if, ctx, "mcast_frames", 4186 child, tx_mcast_frames, "Multicast frames"); 4187 MSK_SYSCTL_STAT64(sc_if, ctx, "octets", 4188 child, tx_octets, "Octets"); 4189 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_64", 4190 child, tx_pkts_64, "64 bytes frames"); 4191 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_65_127", 4192 child, tx_pkts_65_127, "65 to 127 bytes frames"); 4193 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_128_255", 4194 child, tx_pkts_128_255, "128 to 255 bytes frames"); 4195 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_256_511", 4196 child, tx_pkts_256_511, "256 to 511 bytes frames"); 4197 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_512_1023", 4198 child, tx_pkts_512_1023, "512 to 1023 bytes frames"); 4199 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_1024_1518", 4200 child, tx_pkts_1024_1518, "1024 to 1518 bytes frames"); 4201 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_1519_max", 4202 child, tx_pkts_1519_max, "1519 to max frames"); 4203 MSK_SYSCTL_STAT32(sc_if, ctx, "colls", 4204 child, tx_colls, "Collisions"); 4205 MSK_SYSCTL_STAT32(sc_if, ctx, "late_colls", 4206 child, tx_late_colls, "Late collisions"); 4207 MSK_SYSCTL_STAT32(sc_if, ctx, "excess_colls", 4208 child, tx_excess_colls, "Excessive collisions"); 4209 MSK_SYSCTL_STAT32(sc_if, ctx, "multi_colls", 4210 child, tx_multi_colls, "Multiple collisions"); 4211 MSK_SYSCTL_STAT32(sc_if, ctx, "single_colls", 4212 child, tx_single_colls, "Single collisions"); 4213 MSK_SYSCTL_STAT32(sc_if, ctx, "underflows", 4214 child, tx_underflows, "FIFO underflows"); 4215 } 4216 4217 #undef MSK_SYSCTL_STAT32 4218 #undef MSK_SYSCTL_STAT64 4219 4220 static int 4221 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 4222 { 4223 int error, value; 4224 4225 if (!arg1) 4226 return (EINVAL); 4227 value = *(int *)arg1; 4228 error = sysctl_handle_int(oidp, &value, 0, req); 4229 if (error || !req->newptr) 4230 return (error); 4231 if (value < low || value > high) 4232 return (EINVAL); 4233 *(int *)arg1 = value; 4234 4235 return (0); 4236 } 4237 4238 static int 4239 sysctl_hw_msk_proc_limit(SYSCTL_HANDLER_ARGS) 4240 { 4241 4242 return (sysctl_int_range(oidp, arg1, arg2, req, MSK_PROC_MIN, 4243 MSK_PROC_MAX)); 4244 } 4245