1 /****************************************************************************** 2 * 3 * Name : sky2.c 4 * Project: Gigabit Ethernet Driver for FreeBSD 5.x/6.x 5 * Version: $Revision: 1.23 $ 6 * Date : $Date: 2005/12/22 09:04:11 $ 7 * Purpose: Main driver source file 8 * 9 *****************************************************************************/ 10 11 /****************************************************************************** 12 * 13 * LICENSE: 14 * Copyright (C) Marvell International Ltd. and/or its affiliates 15 * 16 * The computer program files contained in this folder ("Files") 17 * are provided to you under the BSD-type license terms provided 18 * below, and any use of such Files and any derivative works 19 * thereof created by you shall be governed by the following terms 20 * and conditions: 21 * 22 * - Redistributions of source code must retain the above copyright 23 * notice, this list of conditions and the following disclaimer. 24 * - Redistributions in binary form must reproduce the above 25 * copyright notice, this list of conditions and the following 26 * disclaimer in the documentation and/or other materials provided 27 * with the distribution. 28 * - Neither the name of Marvell nor the names of its contributors 29 * may be used to endorse or promote products derived from this 30 * software without specific prior written permission. 31 * 32 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 33 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 34 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 35 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 36 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 37 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 38 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 39 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 40 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 41 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 42 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED 43 * OF THE POSSIBILITY OF SUCH DAMAGE. 44 * /LICENSE 45 * 46 *****************************************************************************/ 47 48 /*- 49 * Copyright (c) 1997, 1998, 1999, 2000 50 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 51 * 52 * Redistribution and use in source and binary forms, with or without 53 * modification, are permitted provided that the following conditions 54 * are met: 55 * 1. Redistributions of source code must retain the above copyright 56 * notice, this list of conditions and the following disclaimer. 57 * 2. Redistributions in binary form must reproduce the above copyright 58 * notice, this list of conditions and the following disclaimer in the 59 * documentation and/or other materials provided with the distribution. 60 * 3. All advertising materials mentioning features or use of this software 61 * must display the following acknowledgement: 62 * This product includes software developed by Bill Paul. 63 * 4. Neither the name of the author nor the names of any co-contributors 64 * may be used to endorse or promote products derived from this software 65 * without specific prior written permission. 66 * 67 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 68 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 69 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 70 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 71 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 72 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 73 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 74 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 75 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 76 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 77 * THE POSSIBILITY OF SUCH DAMAGE. 78 */ 79 /*- 80 * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu> 81 * 82 * Permission to use, copy, modify, and distribute this software for any 83 * purpose with or without fee is hereby granted, provided that the above 84 * copyright notice and this permission notice appear in all copies. 85 * 86 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 87 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 88 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 89 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 90 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 91 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 92 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 93 */ 94 95 /* 96 * Device driver for the Marvell Yukon II Ethernet controller. 97 * Due to lack of documentation, this driver is based on the code from 98 * sk(4) and Marvell's myk(4) driver for FreeBSD 5.x. 99 */ 100 101 #include <sys/cdefs.h> 102 __FBSDID("$FreeBSD$"); 103 104 #include <sys/param.h> 105 #include <sys/systm.h> 106 #include <sys/bus.h> 107 #include <sys/endian.h> 108 #include <sys/mbuf.h> 109 #include <sys/malloc.h> 110 #include <sys/kernel.h> 111 #include <sys/module.h> 112 #include <sys/socket.h> 113 #include <sys/sockio.h> 114 #include <sys/queue.h> 115 #include <sys/sysctl.h> 116 117 #include <net/bpf.h> 118 #include <net/ethernet.h> 119 #include <net/if.h> 120 #include <net/if_arp.h> 121 #include <net/if_dl.h> 122 #include <net/if_media.h> 123 #include <net/if_types.h> 124 #include <net/if_vlan_var.h> 125 126 #include <netinet/in.h> 127 #include <netinet/in_systm.h> 128 #include <netinet/ip.h> 129 #include <netinet/tcp.h> 130 #include <netinet/udp.h> 131 132 #include <machine/bus.h> 133 #include <machine/in_cksum.h> 134 #include <machine/resource.h> 135 #include <sys/rman.h> 136 137 #include <dev/mii/mii.h> 138 #include <dev/mii/miivar.h> 139 140 #include <dev/pci/pcireg.h> 141 #include <dev/pci/pcivar.h> 142 143 #include <dev/msk/if_mskreg.h> 144 145 MODULE_DEPEND(msk, pci, 1, 1, 1); 146 MODULE_DEPEND(msk, ether, 1, 1, 1); 147 MODULE_DEPEND(msk, miibus, 1, 1, 1); 148 149 /* "device miibus" required. See GENERIC if you get errors here. */ 150 #include "miibus_if.h" 151 152 /* Tunables. */ 153 static int msi_disable = 0; 154 TUNABLE_INT("hw.msk.msi_disable", &msi_disable); 155 static int legacy_intr = 0; 156 TUNABLE_INT("hw.msk.legacy_intr", &legacy_intr); 157 static int jumbo_disable = 0; 158 TUNABLE_INT("hw.msk.jumbo_disable", &jumbo_disable); 159 160 #define MSK_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 161 162 /* 163 * Devices supported by this driver. 164 */ 165 static struct msk_product { 166 uint16_t msk_vendorid; 167 uint16_t msk_deviceid; 168 const char *msk_name; 169 } msk_products[] = { 170 { VENDORID_SK, DEVICEID_SK_YUKON2, 171 "SK-9Sxx Gigabit Ethernet" }, 172 { VENDORID_SK, DEVICEID_SK_YUKON2_EXPR, 173 "SK-9Exx Gigabit Ethernet"}, 174 { VENDORID_MARVELL, DEVICEID_MRVL_8021CU, 175 "Marvell Yukon 88E8021CU Gigabit Ethernet" }, 176 { VENDORID_MARVELL, DEVICEID_MRVL_8021X, 177 "Marvell Yukon 88E8021 SX/LX Gigabit Ethernet" }, 178 { VENDORID_MARVELL, DEVICEID_MRVL_8022CU, 179 "Marvell Yukon 88E8022CU Gigabit Ethernet" }, 180 { VENDORID_MARVELL, DEVICEID_MRVL_8022X, 181 "Marvell Yukon 88E8022 SX/LX Gigabit Ethernet" }, 182 { VENDORID_MARVELL, DEVICEID_MRVL_8061CU, 183 "Marvell Yukon 88E8061CU Gigabit Ethernet" }, 184 { VENDORID_MARVELL, DEVICEID_MRVL_8061X, 185 "Marvell Yukon 88E8061 SX/LX Gigabit Ethernet" }, 186 { VENDORID_MARVELL, DEVICEID_MRVL_8062CU, 187 "Marvell Yukon 88E8062CU Gigabit Ethernet" }, 188 { VENDORID_MARVELL, DEVICEID_MRVL_8062X, 189 "Marvell Yukon 88E8062 SX/LX Gigabit Ethernet" }, 190 { VENDORID_MARVELL, DEVICEID_MRVL_8035, 191 "Marvell Yukon 88E8035 Fast Ethernet" }, 192 { VENDORID_MARVELL, DEVICEID_MRVL_8036, 193 "Marvell Yukon 88E8036 Fast Ethernet" }, 194 { VENDORID_MARVELL, DEVICEID_MRVL_8038, 195 "Marvell Yukon 88E8038 Fast Ethernet" }, 196 { VENDORID_MARVELL, DEVICEID_MRVL_8039, 197 "Marvell Yukon 88E8039 Fast Ethernet" }, 198 { VENDORID_MARVELL, DEVICEID_MRVL_8040, 199 "Marvell Yukon 88E8040 Fast Ethernet" }, 200 { VENDORID_MARVELL, DEVICEID_MRVL_8040T, 201 "Marvell Yukon 88E8040T Fast Ethernet" }, 202 { VENDORID_MARVELL, DEVICEID_MRVL_8042, 203 "Marvell Yukon 88E8042 Fast Ethernet" }, 204 { VENDORID_MARVELL, DEVICEID_MRVL_8048, 205 "Marvell Yukon 88E8048 Fast Ethernet" }, 206 { VENDORID_MARVELL, DEVICEID_MRVL_4361, 207 "Marvell Yukon 88E8050 Gigabit Ethernet" }, 208 { VENDORID_MARVELL, DEVICEID_MRVL_4360, 209 "Marvell Yukon 88E8052 Gigabit Ethernet" }, 210 { VENDORID_MARVELL, DEVICEID_MRVL_4362, 211 "Marvell Yukon 88E8053 Gigabit Ethernet" }, 212 { VENDORID_MARVELL, DEVICEID_MRVL_4363, 213 "Marvell Yukon 88E8055 Gigabit Ethernet" }, 214 { VENDORID_MARVELL, DEVICEID_MRVL_4364, 215 "Marvell Yukon 88E8056 Gigabit Ethernet" }, 216 { VENDORID_MARVELL, DEVICEID_MRVL_4365, 217 "Marvell Yukon 88E8070 Gigabit Ethernet" }, 218 { VENDORID_MARVELL, DEVICEID_MRVL_436A, 219 "Marvell Yukon 88E8058 Gigabit Ethernet" }, 220 { VENDORID_MARVELL, DEVICEID_MRVL_436B, 221 "Marvell Yukon 88E8071 Gigabit Ethernet" }, 222 { VENDORID_MARVELL, DEVICEID_MRVL_436C, 223 "Marvell Yukon 88E8072 Gigabit Ethernet" }, 224 { VENDORID_MARVELL, DEVICEID_MRVL_4380, 225 "Marvell Yukon 88E8057 Gigabit Ethernet" }, 226 { VENDORID_MARVELL, DEVICEID_MRVL_4381, 227 "Marvell Yukon 88E8059 Gigabit Ethernet" }, 228 { VENDORID_DLINK, DEVICEID_DLINK_DGE550SX, 229 "D-Link 550SX Gigabit Ethernet" }, 230 { VENDORID_DLINK, DEVICEID_DLINK_DGE560SX, 231 "D-Link 560SX Gigabit Ethernet" }, 232 { VENDORID_DLINK, DEVICEID_DLINK_DGE560T, 233 "D-Link 560T Gigabit Ethernet" } 234 }; 235 236 static const char *model_name[] = { 237 "Yukon XL", 238 "Yukon EC Ultra", 239 "Yukon EX", 240 "Yukon EC", 241 "Yukon FE", 242 "Yukon FE+", 243 "Yukon Supreme", 244 "Yukon Ultra 2", 245 "Yukon Unknown", 246 "Yukon Optima", 247 }; 248 249 static int mskc_probe(device_t); 250 static int mskc_attach(device_t); 251 static int mskc_detach(device_t); 252 static int mskc_shutdown(device_t); 253 static int mskc_setup_rambuffer(struct msk_softc *); 254 static int mskc_suspend(device_t); 255 static int mskc_resume(device_t); 256 static void mskc_reset(struct msk_softc *); 257 258 static int msk_probe(device_t); 259 static int msk_attach(device_t); 260 static int msk_detach(device_t); 261 262 static void msk_tick(void *); 263 static void msk_intr(void *); 264 static void msk_intr_phy(struct msk_if_softc *); 265 static void msk_intr_gmac(struct msk_if_softc *); 266 static __inline void msk_rxput(struct msk_if_softc *); 267 static int msk_handle_events(struct msk_softc *); 268 static void msk_handle_hwerr(struct msk_if_softc *, uint32_t); 269 static void msk_intr_hwerr(struct msk_softc *); 270 #ifndef __NO_STRICT_ALIGNMENT 271 static __inline void msk_fixup_rx(struct mbuf *); 272 #endif 273 static __inline void msk_rxcsum(struct msk_if_softc *, uint32_t, struct mbuf *); 274 static void msk_rxeof(struct msk_if_softc *, uint32_t, uint32_t, int); 275 static void msk_jumbo_rxeof(struct msk_if_softc *, uint32_t, uint32_t, int); 276 static void msk_txeof(struct msk_if_softc *, int); 277 static int msk_encap(struct msk_if_softc *, struct mbuf **); 278 static void msk_start(struct ifnet *); 279 static void msk_start_locked(struct ifnet *); 280 static int msk_ioctl(struct ifnet *, u_long, caddr_t); 281 static void msk_set_prefetch(struct msk_softc *, int, bus_addr_t, uint32_t); 282 static void msk_set_rambuffer(struct msk_if_softc *); 283 static void msk_set_tx_stfwd(struct msk_if_softc *); 284 static void msk_init(void *); 285 static void msk_init_locked(struct msk_if_softc *); 286 static void msk_stop(struct msk_if_softc *); 287 static void msk_watchdog(struct msk_if_softc *); 288 static int msk_mediachange(struct ifnet *); 289 static void msk_mediastatus(struct ifnet *, struct ifmediareq *); 290 static void msk_phy_power(struct msk_softc *, int); 291 static void msk_dmamap_cb(void *, bus_dma_segment_t *, int, int); 292 static int msk_status_dma_alloc(struct msk_softc *); 293 static void msk_status_dma_free(struct msk_softc *); 294 static int msk_txrx_dma_alloc(struct msk_if_softc *); 295 static int msk_rx_dma_jalloc(struct msk_if_softc *); 296 static void msk_txrx_dma_free(struct msk_if_softc *); 297 static void msk_rx_dma_jfree(struct msk_if_softc *); 298 static int msk_rx_fill(struct msk_if_softc *, int); 299 static int msk_init_rx_ring(struct msk_if_softc *); 300 static int msk_init_jumbo_rx_ring(struct msk_if_softc *); 301 static void msk_init_tx_ring(struct msk_if_softc *); 302 static __inline void msk_discard_rxbuf(struct msk_if_softc *, int); 303 static __inline void msk_discard_jumbo_rxbuf(struct msk_if_softc *, int); 304 static int msk_newbuf(struct msk_if_softc *, int); 305 static int msk_jumbo_newbuf(struct msk_if_softc *, int); 306 307 static int msk_phy_readreg(struct msk_if_softc *, int, int); 308 static int msk_phy_writereg(struct msk_if_softc *, int, int, int); 309 static int msk_miibus_readreg(device_t, int, int); 310 static int msk_miibus_writereg(device_t, int, int, int); 311 static void msk_miibus_statchg(device_t); 312 313 static void msk_rxfilter(struct msk_if_softc *); 314 static void msk_setvlan(struct msk_if_softc *, struct ifnet *); 315 316 static void msk_stats_clear(struct msk_if_softc *); 317 static void msk_stats_update(struct msk_if_softc *); 318 static int msk_sysctl_stat32(SYSCTL_HANDLER_ARGS); 319 static int msk_sysctl_stat64(SYSCTL_HANDLER_ARGS); 320 static void msk_sysctl_node(struct msk_if_softc *); 321 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int); 322 static int sysctl_hw_msk_proc_limit(SYSCTL_HANDLER_ARGS); 323 324 static device_method_t mskc_methods[] = { 325 /* Device interface */ 326 DEVMETHOD(device_probe, mskc_probe), 327 DEVMETHOD(device_attach, mskc_attach), 328 DEVMETHOD(device_detach, mskc_detach), 329 DEVMETHOD(device_suspend, mskc_suspend), 330 DEVMETHOD(device_resume, mskc_resume), 331 DEVMETHOD(device_shutdown, mskc_shutdown), 332 333 /* bus interface */ 334 DEVMETHOD(bus_print_child, bus_generic_print_child), 335 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 336 337 { NULL, NULL } 338 }; 339 340 static driver_t mskc_driver = { 341 "mskc", 342 mskc_methods, 343 sizeof(struct msk_softc) 344 }; 345 346 static devclass_t mskc_devclass; 347 348 static device_method_t msk_methods[] = { 349 /* Device interface */ 350 DEVMETHOD(device_probe, msk_probe), 351 DEVMETHOD(device_attach, msk_attach), 352 DEVMETHOD(device_detach, msk_detach), 353 DEVMETHOD(device_shutdown, bus_generic_shutdown), 354 355 /* bus interface */ 356 DEVMETHOD(bus_print_child, bus_generic_print_child), 357 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 358 359 /* MII interface */ 360 DEVMETHOD(miibus_readreg, msk_miibus_readreg), 361 DEVMETHOD(miibus_writereg, msk_miibus_writereg), 362 DEVMETHOD(miibus_statchg, msk_miibus_statchg), 363 364 { NULL, NULL } 365 }; 366 367 static driver_t msk_driver = { 368 "msk", 369 msk_methods, 370 sizeof(struct msk_if_softc) 371 }; 372 373 static devclass_t msk_devclass; 374 375 DRIVER_MODULE(mskc, pci, mskc_driver, mskc_devclass, 0, 0); 376 DRIVER_MODULE(msk, mskc, msk_driver, msk_devclass, 0, 0); 377 DRIVER_MODULE(miibus, msk, miibus_driver, miibus_devclass, 0, 0); 378 379 static struct resource_spec msk_res_spec_io[] = { 380 { SYS_RES_IOPORT, PCIR_BAR(1), RF_ACTIVE }, 381 { -1, 0, 0 } 382 }; 383 384 static struct resource_spec msk_res_spec_mem[] = { 385 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 386 { -1, 0, 0 } 387 }; 388 389 static struct resource_spec msk_irq_spec_legacy[] = { 390 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 391 { -1, 0, 0 } 392 }; 393 394 static struct resource_spec msk_irq_spec_msi[] = { 395 { SYS_RES_IRQ, 1, RF_ACTIVE }, 396 { -1, 0, 0 } 397 }; 398 399 static int 400 msk_miibus_readreg(device_t dev, int phy, int reg) 401 { 402 struct msk_if_softc *sc_if; 403 404 if (phy != PHY_ADDR_MARV) 405 return (0); 406 407 sc_if = device_get_softc(dev); 408 409 return (msk_phy_readreg(sc_if, phy, reg)); 410 } 411 412 static int 413 msk_phy_readreg(struct msk_if_softc *sc_if, int phy, int reg) 414 { 415 struct msk_softc *sc; 416 int i, val; 417 418 sc = sc_if->msk_softc; 419 420 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SMI_CTRL, 421 GM_SMI_CT_PHY_AD(phy) | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD); 422 423 for (i = 0; i < MSK_TIMEOUT; i++) { 424 DELAY(1); 425 val = GMAC_READ_2(sc, sc_if->msk_port, GM_SMI_CTRL); 426 if ((val & GM_SMI_CT_RD_VAL) != 0) { 427 val = GMAC_READ_2(sc, sc_if->msk_port, GM_SMI_DATA); 428 break; 429 } 430 } 431 432 if (i == MSK_TIMEOUT) { 433 if_printf(sc_if->msk_ifp, "phy failed to come ready\n"); 434 val = 0; 435 } 436 437 return (val); 438 } 439 440 static int 441 msk_miibus_writereg(device_t dev, int phy, int reg, int val) 442 { 443 struct msk_if_softc *sc_if; 444 445 if (phy != PHY_ADDR_MARV) 446 return (0); 447 448 sc_if = device_get_softc(dev); 449 450 return (msk_phy_writereg(sc_if, phy, reg, val)); 451 } 452 453 static int 454 msk_phy_writereg(struct msk_if_softc *sc_if, int phy, int reg, int val) 455 { 456 struct msk_softc *sc; 457 int i; 458 459 sc = sc_if->msk_softc; 460 461 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SMI_DATA, val); 462 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SMI_CTRL, 463 GM_SMI_CT_PHY_AD(phy) | GM_SMI_CT_REG_AD(reg)); 464 for (i = 0; i < MSK_TIMEOUT; i++) { 465 DELAY(1); 466 if ((GMAC_READ_2(sc, sc_if->msk_port, GM_SMI_CTRL) & 467 GM_SMI_CT_BUSY) == 0) 468 break; 469 } 470 if (i == MSK_TIMEOUT) 471 if_printf(sc_if->msk_ifp, "phy write timeout\n"); 472 473 return (0); 474 } 475 476 static void 477 msk_miibus_statchg(device_t dev) 478 { 479 struct msk_softc *sc; 480 struct msk_if_softc *sc_if; 481 struct mii_data *mii; 482 struct ifnet *ifp; 483 uint32_t gmac; 484 485 sc_if = device_get_softc(dev); 486 sc = sc_if->msk_softc; 487 488 MSK_IF_LOCK_ASSERT(sc_if); 489 490 mii = device_get_softc(sc_if->msk_miibus); 491 ifp = sc_if->msk_ifp; 492 if (mii == NULL || ifp == NULL || 493 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 494 return; 495 496 sc_if->msk_flags &= ~MSK_FLAG_LINK; 497 if ((mii->mii_media_status & (IFM_AVALID | IFM_ACTIVE)) == 498 (IFM_AVALID | IFM_ACTIVE)) { 499 switch (IFM_SUBTYPE(mii->mii_media_active)) { 500 case IFM_10_T: 501 case IFM_100_TX: 502 sc_if->msk_flags |= MSK_FLAG_LINK; 503 break; 504 case IFM_1000_T: 505 case IFM_1000_SX: 506 case IFM_1000_LX: 507 case IFM_1000_CX: 508 if ((sc_if->msk_flags & MSK_FLAG_FASTETHER) == 0) 509 sc_if->msk_flags |= MSK_FLAG_LINK; 510 break; 511 default: 512 break; 513 } 514 } 515 516 if ((sc_if->msk_flags & MSK_FLAG_LINK) != 0) { 517 /* Enable Tx FIFO Underrun. */ 518 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_MSK), 519 GM_IS_TX_FF_UR | GM_IS_RX_FF_OR); 520 /* 521 * Because mii(4) notify msk(4) that it detected link status 522 * change, there is no need to enable automatic 523 * speed/flow-control/duplex updates. 524 */ 525 gmac = GM_GPCR_AU_ALL_DIS; 526 switch (IFM_SUBTYPE(mii->mii_media_active)) { 527 case IFM_1000_SX: 528 case IFM_1000_T: 529 gmac |= GM_GPCR_SPEED_1000; 530 break; 531 case IFM_100_TX: 532 gmac |= GM_GPCR_SPEED_100; 533 break; 534 case IFM_10_T: 535 break; 536 } 537 538 /* Disable Rx flow control. */ 539 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FLAG0) == 0) 540 gmac |= GM_GPCR_FC_RX_DIS; 541 /* Disable Tx flow control. */ 542 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FLAG1) == 0) 543 gmac |= GM_GPCR_FC_TX_DIS; 544 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) 545 gmac |= GM_GPCR_DUP_FULL; 546 else 547 gmac |= GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS; 548 gmac |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA; 549 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, gmac); 550 /* Read again to ensure writing. */ 551 GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL); 552 gmac = GMC_PAUSE_OFF; 553 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 554 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FLAG0) != 0) 555 gmac = GMC_PAUSE_ON; 556 } 557 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), gmac); 558 559 /* Enable PHY interrupt for FIFO underrun/overflow. */ 560 msk_phy_writereg(sc_if, PHY_ADDR_MARV, 561 PHY_MARV_INT_MASK, PHY_M_IS_FIFO_ERROR); 562 } else { 563 /* 564 * Link state changed to down. 565 * Disable PHY interrupts. 566 */ 567 msk_phy_writereg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_MASK, 0); 568 /* Disable Rx/Tx MAC. */ 569 gmac = GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL); 570 if ((GM_GPCR_RX_ENA | GM_GPCR_TX_ENA) != 0) { 571 gmac &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA); 572 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, gmac); 573 /* Read again to ensure writing. */ 574 GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL); 575 } 576 } 577 } 578 579 static void 580 msk_rxfilter(struct msk_if_softc *sc_if) 581 { 582 struct msk_softc *sc; 583 struct ifnet *ifp; 584 struct ifmultiaddr *ifma; 585 uint32_t mchash[2]; 586 uint32_t crc; 587 uint16_t mode; 588 589 sc = sc_if->msk_softc; 590 591 MSK_IF_LOCK_ASSERT(sc_if); 592 593 ifp = sc_if->msk_ifp; 594 595 bzero(mchash, sizeof(mchash)); 596 mode = GMAC_READ_2(sc, sc_if->msk_port, GM_RX_CTRL); 597 if ((ifp->if_flags & IFF_PROMISC) != 0) 598 mode &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA); 599 else if ((ifp->if_flags & IFF_ALLMULTI) != 0) { 600 mode |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA; 601 mchash[0] = 0xffff; 602 mchash[1] = 0xffff; 603 } else { 604 mode |= GM_RXCR_UCF_ENA; 605 if_maddr_rlock(ifp); 606 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 607 if (ifma->ifma_addr->sa_family != AF_LINK) 608 continue; 609 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *) 610 ifma->ifma_addr), ETHER_ADDR_LEN); 611 /* Just want the 6 least significant bits. */ 612 crc &= 0x3f; 613 /* Set the corresponding bit in the hash table. */ 614 mchash[crc >> 5] |= 1 << (crc & 0x1f); 615 } 616 if_maddr_runlock(ifp); 617 if (mchash[0] != 0 || mchash[1] != 0) 618 mode |= GM_RXCR_MCF_ENA; 619 } 620 621 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H1, 622 mchash[0] & 0xffff); 623 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H2, 624 (mchash[0] >> 16) & 0xffff); 625 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H3, 626 mchash[1] & 0xffff); 627 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H4, 628 (mchash[1] >> 16) & 0xffff); 629 GMAC_WRITE_2(sc, sc_if->msk_port, GM_RX_CTRL, mode); 630 } 631 632 static void 633 msk_setvlan(struct msk_if_softc *sc_if, struct ifnet *ifp) 634 { 635 struct msk_softc *sc; 636 637 sc = sc_if->msk_softc; 638 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) { 639 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), 640 RX_VLAN_STRIP_ON); 641 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 642 TX_VLAN_TAG_ON); 643 } else { 644 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), 645 RX_VLAN_STRIP_OFF); 646 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 647 TX_VLAN_TAG_OFF); 648 } 649 } 650 651 static int 652 msk_rx_fill(struct msk_if_softc *sc_if, int jumbo) 653 { 654 uint16_t idx; 655 int i; 656 657 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0 && 658 (sc_if->msk_ifp->if_capenable & IFCAP_RXCSUM) != 0) { 659 /* Wait until controller executes OP_TCPSTART command. */ 660 for (i = 10; i > 0; i--) { 661 DELAY(10); 662 idx = CSR_READ_2(sc_if->msk_softc, 663 Y2_PREF_Q_ADDR(sc_if->msk_rxq, 664 PREF_UNIT_GET_IDX_REG)); 665 if (idx != 0) 666 break; 667 } 668 if (i == 0) { 669 device_printf(sc_if->msk_if_dev, 670 "prefetch unit stuck?\n"); 671 return (ETIMEDOUT); 672 } 673 /* 674 * Fill consumed LE with free buffer. This can be done 675 * in Rx handler but we don't want to add special code 676 * in fast handler. 677 */ 678 if (jumbo > 0) { 679 if (msk_jumbo_newbuf(sc_if, 0) != 0) 680 return (ENOBUFS); 681 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 682 sc_if->msk_cdata.msk_jumbo_rx_ring_map, 683 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 684 } else { 685 if (msk_newbuf(sc_if, 0) != 0) 686 return (ENOBUFS); 687 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_ring_tag, 688 sc_if->msk_cdata.msk_rx_ring_map, 689 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 690 } 691 sc_if->msk_cdata.msk_rx_prod = 0; 692 CSR_WRITE_2(sc_if->msk_softc, 693 Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_PUT_IDX_REG), 694 sc_if->msk_cdata.msk_rx_prod); 695 } 696 return (0); 697 } 698 699 static int 700 msk_init_rx_ring(struct msk_if_softc *sc_if) 701 { 702 struct msk_ring_data *rd; 703 struct msk_rxdesc *rxd; 704 int i, prod; 705 706 MSK_IF_LOCK_ASSERT(sc_if); 707 708 sc_if->msk_cdata.msk_rx_cons = 0; 709 sc_if->msk_cdata.msk_rx_prod = 0; 710 sc_if->msk_cdata.msk_rx_putwm = MSK_PUT_WM; 711 712 rd = &sc_if->msk_rdata; 713 bzero(rd->msk_rx_ring, sizeof(struct msk_rx_desc) * MSK_RX_RING_CNT); 714 prod = sc_if->msk_cdata.msk_rx_prod; 715 i = 0; 716 /* Have controller know how to compute Rx checksum. */ 717 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0 && 718 (sc_if->msk_ifp->if_capenable & IFCAP_RXCSUM) != 0) { 719 rxd = &sc_if->msk_cdata.msk_rxdesc[prod]; 720 rxd->rx_m = NULL; 721 rxd->rx_le = &rd->msk_rx_ring[prod]; 722 rxd->rx_le->msk_addr = htole32(ETHER_HDR_LEN << 16 | 723 ETHER_HDR_LEN); 724 rxd->rx_le->msk_control = htole32(OP_TCPSTART | HW_OWNER); 725 MSK_INC(prod, MSK_RX_RING_CNT); 726 MSK_INC(sc_if->msk_cdata.msk_rx_cons, MSK_RX_RING_CNT); 727 i++; 728 } 729 for (; i < MSK_RX_RING_CNT; i++) { 730 rxd = &sc_if->msk_cdata.msk_rxdesc[prod]; 731 rxd->rx_m = NULL; 732 rxd->rx_le = &rd->msk_rx_ring[prod]; 733 if (msk_newbuf(sc_if, prod) != 0) 734 return (ENOBUFS); 735 MSK_INC(prod, MSK_RX_RING_CNT); 736 } 737 738 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_ring_tag, 739 sc_if->msk_cdata.msk_rx_ring_map, 740 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 741 742 /* Update prefetch unit. */ 743 sc_if->msk_cdata.msk_rx_prod = MSK_RX_RING_CNT - 1; 744 CSR_WRITE_2(sc_if->msk_softc, 745 Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_PUT_IDX_REG), 746 sc_if->msk_cdata.msk_rx_prod); 747 if (msk_rx_fill(sc_if, 0) != 0) 748 return (ENOBUFS); 749 return (0); 750 } 751 752 static int 753 msk_init_jumbo_rx_ring(struct msk_if_softc *sc_if) 754 { 755 struct msk_ring_data *rd; 756 struct msk_rxdesc *rxd; 757 int i, prod; 758 759 MSK_IF_LOCK_ASSERT(sc_if); 760 761 sc_if->msk_cdata.msk_rx_cons = 0; 762 sc_if->msk_cdata.msk_rx_prod = 0; 763 sc_if->msk_cdata.msk_rx_putwm = MSK_PUT_WM; 764 765 rd = &sc_if->msk_rdata; 766 bzero(rd->msk_jumbo_rx_ring, 767 sizeof(struct msk_rx_desc) * MSK_JUMBO_RX_RING_CNT); 768 prod = sc_if->msk_cdata.msk_rx_prod; 769 i = 0; 770 /* Have controller know how to compute Rx checksum. */ 771 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0 && 772 (sc_if->msk_ifp->if_capenable & IFCAP_RXCSUM) != 0) { 773 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[prod]; 774 rxd->rx_m = NULL; 775 rxd->rx_le = &rd->msk_jumbo_rx_ring[prod]; 776 rxd->rx_le->msk_addr = htole32(ETHER_HDR_LEN << 16 | 777 ETHER_HDR_LEN); 778 rxd->rx_le->msk_control = htole32(OP_TCPSTART | HW_OWNER); 779 MSK_INC(prod, MSK_JUMBO_RX_RING_CNT); 780 MSK_INC(sc_if->msk_cdata.msk_rx_cons, MSK_JUMBO_RX_RING_CNT); 781 i++; 782 } 783 for (; i < MSK_JUMBO_RX_RING_CNT; i++) { 784 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[prod]; 785 rxd->rx_m = NULL; 786 rxd->rx_le = &rd->msk_jumbo_rx_ring[prod]; 787 if (msk_jumbo_newbuf(sc_if, prod) != 0) 788 return (ENOBUFS); 789 MSK_INC(prod, MSK_JUMBO_RX_RING_CNT); 790 } 791 792 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 793 sc_if->msk_cdata.msk_jumbo_rx_ring_map, 794 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 795 796 sc_if->msk_cdata.msk_rx_prod = MSK_JUMBO_RX_RING_CNT - 1; 797 CSR_WRITE_2(sc_if->msk_softc, 798 Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_PUT_IDX_REG), 799 sc_if->msk_cdata.msk_rx_prod); 800 if (msk_rx_fill(sc_if, 1) != 0) 801 return (ENOBUFS); 802 return (0); 803 } 804 805 static void 806 msk_init_tx_ring(struct msk_if_softc *sc_if) 807 { 808 struct msk_ring_data *rd; 809 struct msk_txdesc *txd; 810 int i; 811 812 sc_if->msk_cdata.msk_tso_mtu = 0; 813 sc_if->msk_cdata.msk_last_csum = 0; 814 sc_if->msk_cdata.msk_tx_prod = 0; 815 sc_if->msk_cdata.msk_tx_cons = 0; 816 sc_if->msk_cdata.msk_tx_cnt = 0; 817 818 rd = &sc_if->msk_rdata; 819 bzero(rd->msk_tx_ring, sizeof(struct msk_tx_desc) * MSK_TX_RING_CNT); 820 for (i = 0; i < MSK_TX_RING_CNT; i++) { 821 txd = &sc_if->msk_cdata.msk_txdesc[i]; 822 txd->tx_m = NULL; 823 txd->tx_le = &rd->msk_tx_ring[i]; 824 } 825 826 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_ring_tag, 827 sc_if->msk_cdata.msk_tx_ring_map, 828 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 829 } 830 831 static __inline void 832 msk_discard_rxbuf(struct msk_if_softc *sc_if, int idx) 833 { 834 struct msk_rx_desc *rx_le; 835 struct msk_rxdesc *rxd; 836 struct mbuf *m; 837 838 rxd = &sc_if->msk_cdata.msk_rxdesc[idx]; 839 m = rxd->rx_m; 840 rx_le = rxd->rx_le; 841 rx_le->msk_control = htole32(m->m_len | OP_PACKET | HW_OWNER); 842 } 843 844 static __inline void 845 msk_discard_jumbo_rxbuf(struct msk_if_softc *sc_if, int idx) 846 { 847 struct msk_rx_desc *rx_le; 848 struct msk_rxdesc *rxd; 849 struct mbuf *m; 850 851 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[idx]; 852 m = rxd->rx_m; 853 rx_le = rxd->rx_le; 854 rx_le->msk_control = htole32(m->m_len | OP_PACKET | HW_OWNER); 855 } 856 857 static int 858 msk_newbuf(struct msk_if_softc *sc_if, int idx) 859 { 860 struct msk_rx_desc *rx_le; 861 struct msk_rxdesc *rxd; 862 struct mbuf *m; 863 bus_dma_segment_t segs[1]; 864 bus_dmamap_t map; 865 int nsegs; 866 867 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 868 if (m == NULL) 869 return (ENOBUFS); 870 871 m->m_len = m->m_pkthdr.len = MCLBYTES; 872 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) == 0) 873 m_adj(m, ETHER_ALIGN); 874 #ifndef __NO_STRICT_ALIGNMENT 875 else 876 m_adj(m, MSK_RX_BUF_ALIGN); 877 #endif 878 879 if (bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_rx_tag, 880 sc_if->msk_cdata.msk_rx_sparemap, m, segs, &nsegs, 881 BUS_DMA_NOWAIT) != 0) { 882 m_freem(m); 883 return (ENOBUFS); 884 } 885 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 886 887 rxd = &sc_if->msk_cdata.msk_rxdesc[idx]; 888 if (rxd->rx_m != NULL) { 889 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_tag, rxd->rx_dmamap, 890 BUS_DMASYNC_POSTREAD); 891 bus_dmamap_unload(sc_if->msk_cdata.msk_rx_tag, rxd->rx_dmamap); 892 } 893 map = rxd->rx_dmamap; 894 rxd->rx_dmamap = sc_if->msk_cdata.msk_rx_sparemap; 895 sc_if->msk_cdata.msk_rx_sparemap = map; 896 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_tag, rxd->rx_dmamap, 897 BUS_DMASYNC_PREREAD); 898 rxd->rx_m = m; 899 rx_le = rxd->rx_le; 900 rx_le->msk_addr = htole32(MSK_ADDR_LO(segs[0].ds_addr)); 901 rx_le->msk_control = 902 htole32(segs[0].ds_len | OP_PACKET | HW_OWNER); 903 904 return (0); 905 } 906 907 static int 908 msk_jumbo_newbuf(struct msk_if_softc *sc_if, int idx) 909 { 910 struct msk_rx_desc *rx_le; 911 struct msk_rxdesc *rxd; 912 struct mbuf *m; 913 bus_dma_segment_t segs[1]; 914 bus_dmamap_t map; 915 int nsegs; 916 917 m = m_getjcl(M_DONTWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES); 918 if (m == NULL) 919 return (ENOBUFS); 920 if ((m->m_flags & M_EXT) == 0) { 921 m_freem(m); 922 return (ENOBUFS); 923 } 924 m->m_len = m->m_pkthdr.len = MJUM9BYTES; 925 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) == 0) 926 m_adj(m, ETHER_ALIGN); 927 #ifndef __NO_STRICT_ALIGNMENT 928 else 929 m_adj(m, MSK_RX_BUF_ALIGN); 930 #endif 931 932 if (bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_jumbo_rx_tag, 933 sc_if->msk_cdata.msk_jumbo_rx_sparemap, m, segs, &nsegs, 934 BUS_DMA_NOWAIT) != 0) { 935 m_freem(m); 936 return (ENOBUFS); 937 } 938 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 939 940 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[idx]; 941 if (rxd->rx_m != NULL) { 942 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_tag, 943 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 944 bus_dmamap_unload(sc_if->msk_cdata.msk_jumbo_rx_tag, 945 rxd->rx_dmamap); 946 } 947 map = rxd->rx_dmamap; 948 rxd->rx_dmamap = sc_if->msk_cdata.msk_jumbo_rx_sparemap; 949 sc_if->msk_cdata.msk_jumbo_rx_sparemap = map; 950 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_tag, rxd->rx_dmamap, 951 BUS_DMASYNC_PREREAD); 952 rxd->rx_m = m; 953 rx_le = rxd->rx_le; 954 rx_le->msk_addr = htole32(MSK_ADDR_LO(segs[0].ds_addr)); 955 rx_le->msk_control = 956 htole32(segs[0].ds_len | OP_PACKET | HW_OWNER); 957 958 return (0); 959 } 960 961 /* 962 * Set media options. 963 */ 964 static int 965 msk_mediachange(struct ifnet *ifp) 966 { 967 struct msk_if_softc *sc_if; 968 struct mii_data *mii; 969 int error; 970 971 sc_if = ifp->if_softc; 972 973 MSK_IF_LOCK(sc_if); 974 mii = device_get_softc(sc_if->msk_miibus); 975 error = mii_mediachg(mii); 976 MSK_IF_UNLOCK(sc_if); 977 978 return (error); 979 } 980 981 /* 982 * Report current media status. 983 */ 984 static void 985 msk_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 986 { 987 struct msk_if_softc *sc_if; 988 struct mii_data *mii; 989 990 sc_if = ifp->if_softc; 991 MSK_IF_LOCK(sc_if); 992 if ((ifp->if_flags & IFF_UP) == 0) { 993 MSK_IF_UNLOCK(sc_if); 994 return; 995 } 996 mii = device_get_softc(sc_if->msk_miibus); 997 998 mii_pollstat(mii); 999 MSK_IF_UNLOCK(sc_if); 1000 ifmr->ifm_active = mii->mii_media_active; 1001 ifmr->ifm_status = mii->mii_media_status; 1002 } 1003 1004 static int 1005 msk_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1006 { 1007 struct msk_if_softc *sc_if; 1008 struct ifreq *ifr; 1009 struct mii_data *mii; 1010 int error, mask, reinit; 1011 1012 sc_if = ifp->if_softc; 1013 ifr = (struct ifreq *)data; 1014 error = 0; 1015 1016 switch(command) { 1017 case SIOCSIFMTU: 1018 MSK_IF_LOCK(sc_if); 1019 if (ifr->ifr_mtu > MSK_JUMBO_MTU || ifr->ifr_mtu < ETHERMIN) 1020 error = EINVAL; 1021 else if (ifp->if_mtu != ifr->ifr_mtu) { 1022 if (ifr->ifr_mtu > ETHERMTU) { 1023 if ((sc_if->msk_flags & MSK_FLAG_JUMBO) == 0) { 1024 error = EINVAL; 1025 MSK_IF_UNLOCK(sc_if); 1026 break; 1027 } 1028 if ((sc_if->msk_flags & 1029 MSK_FLAG_JUMBO_NOCSUM) != 0) { 1030 ifp->if_hwassist &= 1031 ~(MSK_CSUM_FEATURES | CSUM_TSO); 1032 ifp->if_capenable &= 1033 ~(IFCAP_TSO4 | IFCAP_TXCSUM); 1034 VLAN_CAPABILITIES(ifp); 1035 } 1036 } 1037 ifp->if_mtu = ifr->ifr_mtu; 1038 msk_init_locked(sc_if); 1039 } 1040 MSK_IF_UNLOCK(sc_if); 1041 break; 1042 case SIOCSIFFLAGS: 1043 MSK_IF_LOCK(sc_if); 1044 if ((ifp->if_flags & IFF_UP) != 0) { 1045 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 && 1046 ((ifp->if_flags ^ sc_if->msk_if_flags) & 1047 (IFF_PROMISC | IFF_ALLMULTI)) != 0) 1048 msk_rxfilter(sc_if); 1049 else if ((sc_if->msk_flags & MSK_FLAG_DETACH) == 0) 1050 msk_init_locked(sc_if); 1051 } else if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1052 msk_stop(sc_if); 1053 sc_if->msk_if_flags = ifp->if_flags; 1054 MSK_IF_UNLOCK(sc_if); 1055 break; 1056 case SIOCADDMULTI: 1057 case SIOCDELMULTI: 1058 MSK_IF_LOCK(sc_if); 1059 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1060 msk_rxfilter(sc_if); 1061 MSK_IF_UNLOCK(sc_if); 1062 break; 1063 case SIOCGIFMEDIA: 1064 case SIOCSIFMEDIA: 1065 mii = device_get_softc(sc_if->msk_miibus); 1066 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1067 break; 1068 case SIOCSIFCAP: 1069 reinit = 0; 1070 MSK_IF_LOCK(sc_if); 1071 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 1072 if ((mask & IFCAP_TXCSUM) != 0 && 1073 (IFCAP_TXCSUM & ifp->if_capabilities) != 0) { 1074 ifp->if_capenable ^= IFCAP_TXCSUM; 1075 if ((IFCAP_TXCSUM & ifp->if_capenable) != 0) 1076 ifp->if_hwassist |= MSK_CSUM_FEATURES; 1077 else 1078 ifp->if_hwassist &= ~MSK_CSUM_FEATURES; 1079 } 1080 if ((mask & IFCAP_RXCSUM) != 0 && 1081 (IFCAP_RXCSUM & ifp->if_capabilities) != 0) { 1082 ifp->if_capenable ^= IFCAP_RXCSUM; 1083 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0) 1084 reinit = 1; 1085 } 1086 if ((mask & IFCAP_VLAN_HWCSUM) != 0 && 1087 (IFCAP_VLAN_HWCSUM & ifp->if_capabilities) != 0) 1088 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; 1089 if ((mask & IFCAP_TSO4) != 0 && 1090 (IFCAP_TSO4 & ifp->if_capabilities) != 0) { 1091 ifp->if_capenable ^= IFCAP_TSO4; 1092 if ((IFCAP_TSO4 & ifp->if_capenable) != 0) 1093 ifp->if_hwassist |= CSUM_TSO; 1094 else 1095 ifp->if_hwassist &= ~CSUM_TSO; 1096 } 1097 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 1098 (IFCAP_VLAN_HWTSO & ifp->if_capabilities) != 0) 1099 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 1100 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 1101 (IFCAP_VLAN_HWTAGGING & ifp->if_capabilities) != 0) { 1102 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 1103 if ((IFCAP_VLAN_HWTAGGING & ifp->if_capenable) == 0) 1104 ifp->if_capenable &= 1105 ~(IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM); 1106 msk_setvlan(sc_if, ifp); 1107 } 1108 if (ifp->if_mtu > ETHERMTU && 1109 (sc_if->msk_flags & MSK_FLAG_JUMBO_NOCSUM) != 0) { 1110 ifp->if_hwassist &= ~(MSK_CSUM_FEATURES | CSUM_TSO); 1111 ifp->if_capenable &= ~(IFCAP_TSO4 | IFCAP_TXCSUM); 1112 } 1113 VLAN_CAPABILITIES(ifp); 1114 if (reinit > 0 && (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 1115 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1116 msk_init_locked(sc_if); 1117 } 1118 MSK_IF_UNLOCK(sc_if); 1119 break; 1120 default: 1121 error = ether_ioctl(ifp, command, data); 1122 break; 1123 } 1124 1125 return (error); 1126 } 1127 1128 static int 1129 mskc_probe(device_t dev) 1130 { 1131 struct msk_product *mp; 1132 uint16_t vendor, devid; 1133 int i; 1134 1135 vendor = pci_get_vendor(dev); 1136 devid = pci_get_device(dev); 1137 mp = msk_products; 1138 for (i = 0; i < sizeof(msk_products)/sizeof(msk_products[0]); 1139 i++, mp++) { 1140 if (vendor == mp->msk_vendorid && devid == mp->msk_deviceid) { 1141 device_set_desc(dev, mp->msk_name); 1142 return (BUS_PROBE_DEFAULT); 1143 } 1144 } 1145 1146 return (ENXIO); 1147 } 1148 1149 static int 1150 mskc_setup_rambuffer(struct msk_softc *sc) 1151 { 1152 int next; 1153 int i; 1154 1155 /* Get adapter SRAM size. */ 1156 sc->msk_ramsize = CSR_READ_1(sc, B2_E_0) * 4; 1157 if (bootverbose) 1158 device_printf(sc->msk_dev, 1159 "RAM buffer size : %dKB\n", sc->msk_ramsize); 1160 if (sc->msk_ramsize == 0) 1161 return (0); 1162 1163 sc->msk_pflags |= MSK_FLAG_RAMBUF; 1164 /* 1165 * Give receiver 2/3 of memory and round down to the multiple 1166 * of 1024. Tx/Rx RAM buffer size of Yukon II shoud be multiple 1167 * of 1024. 1168 */ 1169 sc->msk_rxqsize = rounddown((sc->msk_ramsize * 1024 * 2) / 3, 1024); 1170 sc->msk_txqsize = (sc->msk_ramsize * 1024) - sc->msk_rxqsize; 1171 for (i = 0, next = 0; i < sc->msk_num_port; i++) { 1172 sc->msk_rxqstart[i] = next; 1173 sc->msk_rxqend[i] = next + sc->msk_rxqsize - 1; 1174 next = sc->msk_rxqend[i] + 1; 1175 sc->msk_txqstart[i] = next; 1176 sc->msk_txqend[i] = next + sc->msk_txqsize - 1; 1177 next = sc->msk_txqend[i] + 1; 1178 if (bootverbose) { 1179 device_printf(sc->msk_dev, 1180 "Port %d : Rx Queue %dKB(0x%08x:0x%08x)\n", i, 1181 sc->msk_rxqsize / 1024, sc->msk_rxqstart[i], 1182 sc->msk_rxqend[i]); 1183 device_printf(sc->msk_dev, 1184 "Port %d : Tx Queue %dKB(0x%08x:0x%08x)\n", i, 1185 sc->msk_txqsize / 1024, sc->msk_txqstart[i], 1186 sc->msk_txqend[i]); 1187 } 1188 } 1189 1190 return (0); 1191 } 1192 1193 static void 1194 msk_phy_power(struct msk_softc *sc, int mode) 1195 { 1196 uint32_t our, val; 1197 int i; 1198 1199 switch (mode) { 1200 case MSK_PHY_POWERUP: 1201 /* Switch power to VCC (WA for VAUX problem). */ 1202 CSR_WRITE_1(sc, B0_POWER_CTRL, 1203 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON); 1204 /* Disable Core Clock Division, set Clock Select to 0. */ 1205 CSR_WRITE_4(sc, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS); 1206 1207 val = 0; 1208 if (sc->msk_hw_id == CHIP_ID_YUKON_XL && 1209 sc->msk_hw_rev > CHIP_REV_YU_XL_A1) { 1210 /* Enable bits are inverted. */ 1211 val = Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS | 1212 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS | 1213 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS; 1214 } 1215 /* 1216 * Enable PCI & Core Clock, enable clock gating for both Links. 1217 */ 1218 CSR_WRITE_1(sc, B2_Y2_CLK_GATE, val); 1219 1220 val = CSR_PCI_READ_4(sc, PCI_OUR_REG_1); 1221 val &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD); 1222 if (sc->msk_hw_id == CHIP_ID_YUKON_XL) { 1223 if (sc->msk_hw_rev > CHIP_REV_YU_XL_A1) { 1224 /* Deassert Low Power for 1st PHY. */ 1225 val |= PCI_Y2_PHY1_COMA; 1226 if (sc->msk_num_port > 1) 1227 val |= PCI_Y2_PHY2_COMA; 1228 } 1229 } 1230 /* Release PHY from PowerDown/COMA mode. */ 1231 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_1, val); 1232 switch (sc->msk_hw_id) { 1233 case CHIP_ID_YUKON_EC_U: 1234 case CHIP_ID_YUKON_EX: 1235 case CHIP_ID_YUKON_FE_P: 1236 case CHIP_ID_YUKON_UL_2: 1237 case CHIP_ID_YUKON_OPT: 1238 CSR_WRITE_2(sc, B0_CTST, Y2_HW_WOL_OFF); 1239 1240 /* Enable all clocks. */ 1241 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_3, 0); 1242 our = CSR_PCI_READ_4(sc, PCI_OUR_REG_4); 1243 our &= (PCI_FORCE_ASPM_REQUEST|PCI_ASPM_GPHY_LINK_DOWN| 1244 PCI_ASPM_INT_FIFO_EMPTY|PCI_ASPM_CLKRUN_REQUEST); 1245 /* Set all bits to 0 except bits 15..12. */ 1246 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_4, our); 1247 our = CSR_PCI_READ_4(sc, PCI_OUR_REG_5); 1248 our &= PCI_CTL_TIM_VMAIN_AV_MSK; 1249 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_5, our); 1250 CSR_PCI_WRITE_4(sc, PCI_CFG_REG_1, 0); 1251 /* 1252 * Disable status race, workaround for 1253 * Yukon EC Ultra & Yukon EX. 1254 */ 1255 val = CSR_READ_4(sc, B2_GP_IO); 1256 val |= GLB_GPIO_STAT_RACE_DIS; 1257 CSR_WRITE_4(sc, B2_GP_IO, val); 1258 CSR_READ_4(sc, B2_GP_IO); 1259 break; 1260 default: 1261 break; 1262 } 1263 for (i = 0; i < sc->msk_num_port; i++) { 1264 CSR_WRITE_2(sc, MR_ADDR(i, GMAC_LINK_CTRL), 1265 GMLC_RST_SET); 1266 CSR_WRITE_2(sc, MR_ADDR(i, GMAC_LINK_CTRL), 1267 GMLC_RST_CLR); 1268 } 1269 break; 1270 case MSK_PHY_POWERDOWN: 1271 val = CSR_PCI_READ_4(sc, PCI_OUR_REG_1); 1272 val |= PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD; 1273 if (sc->msk_hw_id == CHIP_ID_YUKON_XL && 1274 sc->msk_hw_rev > CHIP_REV_YU_XL_A1) { 1275 val &= ~PCI_Y2_PHY1_COMA; 1276 if (sc->msk_num_port > 1) 1277 val &= ~PCI_Y2_PHY2_COMA; 1278 } 1279 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_1, val); 1280 1281 val = Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS | 1282 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS | 1283 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS; 1284 if (sc->msk_hw_id == CHIP_ID_YUKON_XL && 1285 sc->msk_hw_rev > CHIP_REV_YU_XL_A1) { 1286 /* Enable bits are inverted. */ 1287 val = 0; 1288 } 1289 /* 1290 * Disable PCI & Core Clock, disable clock gating for 1291 * both Links. 1292 */ 1293 CSR_WRITE_1(sc, B2_Y2_CLK_GATE, val); 1294 CSR_WRITE_1(sc, B0_POWER_CTRL, 1295 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_ON | PC_VCC_OFF); 1296 break; 1297 default: 1298 break; 1299 } 1300 } 1301 1302 static void 1303 mskc_reset(struct msk_softc *sc) 1304 { 1305 bus_addr_t addr; 1306 uint16_t status; 1307 uint32_t val; 1308 int i; 1309 1310 CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR); 1311 1312 /* Disable ASF. */ 1313 if (sc->msk_hw_id == CHIP_ID_YUKON_EX) { 1314 status = CSR_READ_2(sc, B28_Y2_ASF_HCU_CCSR); 1315 /* Clear AHB bridge & microcontroller reset. */ 1316 status &= ~(Y2_ASF_HCU_CCSR_AHB_RST | 1317 Y2_ASF_HCU_CCSR_CPU_RST_MODE); 1318 /* Clear ASF microcontroller state. */ 1319 status &= ~ Y2_ASF_HCU_CCSR_UC_STATE_MSK; 1320 CSR_WRITE_2(sc, B28_Y2_ASF_HCU_CCSR, status); 1321 } else 1322 CSR_WRITE_1(sc, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET); 1323 CSR_WRITE_2(sc, B0_CTST, Y2_ASF_DISABLE); 1324 1325 /* 1326 * Since we disabled ASF, S/W reset is required for Power Management. 1327 */ 1328 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); 1329 CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR); 1330 1331 /* Clear all error bits in the PCI status register. */ 1332 status = pci_read_config(sc->msk_dev, PCIR_STATUS, 2); 1333 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON); 1334 1335 pci_write_config(sc->msk_dev, PCIR_STATUS, status | 1336 PCIM_STATUS_PERR | PCIM_STATUS_SERR | PCIM_STATUS_RMABORT | 1337 PCIM_STATUS_RTABORT | PCIM_STATUS_PERRREPORT, 2); 1338 CSR_WRITE_2(sc, B0_CTST, CS_MRST_CLR); 1339 1340 switch (sc->msk_bustype) { 1341 case MSK_PEX_BUS: 1342 /* Clear all PEX errors. */ 1343 CSR_PCI_WRITE_4(sc, PEX_UNC_ERR_STAT, 0xffffffff); 1344 val = CSR_PCI_READ_4(sc, PEX_UNC_ERR_STAT); 1345 if ((val & PEX_RX_OV) != 0) { 1346 sc->msk_intrmask &= ~Y2_IS_HW_ERR; 1347 sc->msk_intrhwemask &= ~Y2_IS_PCI_EXP; 1348 } 1349 break; 1350 case MSK_PCI_BUS: 1351 case MSK_PCIX_BUS: 1352 /* Set Cache Line Size to 2(8bytes) if configured to 0. */ 1353 val = pci_read_config(sc->msk_dev, PCIR_CACHELNSZ, 1); 1354 if (val == 0) 1355 pci_write_config(sc->msk_dev, PCIR_CACHELNSZ, 2, 1); 1356 if (sc->msk_bustype == MSK_PCIX_BUS) { 1357 /* Set Cache Line Size opt. */ 1358 val = pci_read_config(sc->msk_dev, PCI_OUR_REG_1, 4); 1359 val |= PCI_CLS_OPT; 1360 pci_write_config(sc->msk_dev, PCI_OUR_REG_1, val, 4); 1361 } 1362 break; 1363 } 1364 /* Set PHY power state. */ 1365 msk_phy_power(sc, MSK_PHY_POWERUP); 1366 1367 /* Reset GPHY/GMAC Control */ 1368 for (i = 0; i < sc->msk_num_port; i++) { 1369 /* GPHY Control reset. */ 1370 CSR_WRITE_4(sc, MR_ADDR(i, GPHY_CTRL), GPC_RST_SET); 1371 CSR_WRITE_4(sc, MR_ADDR(i, GPHY_CTRL), GPC_RST_CLR); 1372 /* GMAC Control reset. */ 1373 CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), GMC_RST_SET); 1374 CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), GMC_RST_CLR); 1375 CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), GMC_F_LOOPB_OFF); 1376 if (sc->msk_hw_id == CHIP_ID_YUKON_EX) 1377 CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), 1378 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON | 1379 GMC_BYP_RETR_ON); 1380 } 1381 if (sc->msk_hw_id == CHIP_ID_YUKON_OPT && sc->msk_hw_rev == 0) { 1382 /* Disable PCIe PHY powerdown(reg 0x80, bit7). */ 1383 CSR_WRITE_4(sc, Y2_PEX_PHY_DATA, (0x0080 << 16) | 0x0080); 1384 } 1385 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 1386 1387 /* LED On. */ 1388 CSR_WRITE_2(sc, B0_CTST, Y2_LED_STAT_ON); 1389 1390 /* Clear TWSI IRQ. */ 1391 CSR_WRITE_4(sc, B2_I2C_IRQ, I2C_CLR_IRQ); 1392 1393 /* Turn off hardware timer. */ 1394 CSR_WRITE_1(sc, B2_TI_CTRL, TIM_STOP); 1395 CSR_WRITE_1(sc, B2_TI_CTRL, TIM_CLR_IRQ); 1396 1397 /* Turn off descriptor polling. */ 1398 CSR_WRITE_1(sc, B28_DPT_CTRL, DPT_STOP); 1399 1400 /* Turn off time stamps. */ 1401 CSR_WRITE_1(sc, GMAC_TI_ST_CTRL, GMT_ST_STOP); 1402 CSR_WRITE_1(sc, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ); 1403 1404 /* Configure timeout values. */ 1405 for (i = 0; i < sc->msk_num_port; i++) { 1406 CSR_WRITE_2(sc, SELECT_RAM_BUFFER(i, B3_RI_CTRL), RI_RST_SET); 1407 CSR_WRITE_2(sc, SELECT_RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR); 1408 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_R1), 1409 MSK_RI_TO_53); 1410 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XA1), 1411 MSK_RI_TO_53); 1412 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XS1), 1413 MSK_RI_TO_53); 1414 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_R1), 1415 MSK_RI_TO_53); 1416 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XA1), 1417 MSK_RI_TO_53); 1418 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XS1), 1419 MSK_RI_TO_53); 1420 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_R2), 1421 MSK_RI_TO_53); 1422 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XA2), 1423 MSK_RI_TO_53); 1424 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XS2), 1425 MSK_RI_TO_53); 1426 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_R2), 1427 MSK_RI_TO_53); 1428 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XA2), 1429 MSK_RI_TO_53); 1430 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XS2), 1431 MSK_RI_TO_53); 1432 } 1433 1434 /* Disable all interrupts. */ 1435 CSR_WRITE_4(sc, B0_HWE_IMSK, 0); 1436 CSR_READ_4(sc, B0_HWE_IMSK); 1437 CSR_WRITE_4(sc, B0_IMSK, 0); 1438 CSR_READ_4(sc, B0_IMSK); 1439 1440 /* 1441 * On dual port PCI-X card, there is an problem where status 1442 * can be received out of order due to split transactions. 1443 */ 1444 if (sc->msk_pcixcap != 0 && sc->msk_num_port > 1) { 1445 uint16_t pcix_cmd; 1446 1447 pcix_cmd = pci_read_config(sc->msk_dev, 1448 sc->msk_pcixcap + PCIXR_COMMAND, 2); 1449 /* Clear Max Outstanding Split Transactions. */ 1450 pcix_cmd &= ~PCIXM_COMMAND_MAX_SPLITS; 1451 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON); 1452 pci_write_config(sc->msk_dev, 1453 sc->msk_pcixcap + PCIXR_COMMAND, pcix_cmd, 2); 1454 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 1455 } 1456 if (sc->msk_expcap != 0) { 1457 /* Change Max. Read Request Size to 2048 bytes. */ 1458 if (pci_get_max_read_req(sc->msk_dev) == 512) 1459 pci_set_max_read_req(sc->msk_dev, 2048); 1460 } 1461 1462 /* Clear status list. */ 1463 bzero(sc->msk_stat_ring, 1464 sizeof(struct msk_stat_desc) * MSK_STAT_RING_CNT); 1465 sc->msk_stat_cons = 0; 1466 bus_dmamap_sync(sc->msk_stat_tag, sc->msk_stat_map, 1467 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1468 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_RST_SET); 1469 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_RST_CLR); 1470 /* Set the status list base address. */ 1471 addr = sc->msk_stat_ring_paddr; 1472 CSR_WRITE_4(sc, STAT_LIST_ADDR_LO, MSK_ADDR_LO(addr)); 1473 CSR_WRITE_4(sc, STAT_LIST_ADDR_HI, MSK_ADDR_HI(addr)); 1474 /* Set the status list last index. */ 1475 CSR_WRITE_2(sc, STAT_LAST_IDX, MSK_STAT_RING_CNT - 1); 1476 if (sc->msk_hw_id == CHIP_ID_YUKON_EC && 1477 sc->msk_hw_rev == CHIP_REV_YU_EC_A1) { 1478 /* WA for dev. #4.3 */ 1479 CSR_WRITE_2(sc, STAT_TX_IDX_TH, ST_TXTH_IDX_MASK); 1480 /* WA for dev. #4.18 */ 1481 CSR_WRITE_1(sc, STAT_FIFO_WM, 0x21); 1482 CSR_WRITE_1(sc, STAT_FIFO_ISR_WM, 0x07); 1483 } else { 1484 CSR_WRITE_2(sc, STAT_TX_IDX_TH, 0x0a); 1485 CSR_WRITE_1(sc, STAT_FIFO_WM, 0x10); 1486 if (sc->msk_hw_id == CHIP_ID_YUKON_XL && 1487 sc->msk_hw_rev == CHIP_REV_YU_XL_A0) 1488 CSR_WRITE_1(sc, STAT_FIFO_ISR_WM, 0x04); 1489 else 1490 CSR_WRITE_1(sc, STAT_FIFO_ISR_WM, 0x10); 1491 CSR_WRITE_4(sc, STAT_ISR_TIMER_INI, 0x0190); 1492 } 1493 /* 1494 * Use default value for STAT_ISR_TIMER_INI, STAT_LEV_TIMER_INI. 1495 */ 1496 CSR_WRITE_4(sc, STAT_TX_TIMER_INI, MSK_USECS(sc, 1000)); 1497 1498 /* Enable status unit. */ 1499 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_OP_ON); 1500 1501 CSR_WRITE_1(sc, STAT_TX_TIMER_CTRL, TIM_START); 1502 CSR_WRITE_1(sc, STAT_LEV_TIMER_CTRL, TIM_START); 1503 CSR_WRITE_1(sc, STAT_ISR_TIMER_CTRL, TIM_START); 1504 } 1505 1506 static int 1507 msk_probe(device_t dev) 1508 { 1509 struct msk_softc *sc; 1510 char desc[100]; 1511 1512 sc = device_get_softc(device_get_parent(dev)); 1513 /* 1514 * Not much to do here. We always know there will be 1515 * at least one GMAC present, and if there are two, 1516 * mskc_attach() will create a second device instance 1517 * for us. 1518 */ 1519 snprintf(desc, sizeof(desc), 1520 "Marvell Technology Group Ltd. %s Id 0x%02x Rev 0x%02x", 1521 model_name[sc->msk_hw_id - CHIP_ID_YUKON_XL], sc->msk_hw_id, 1522 sc->msk_hw_rev); 1523 device_set_desc_copy(dev, desc); 1524 1525 return (BUS_PROBE_DEFAULT); 1526 } 1527 1528 static int 1529 msk_attach(device_t dev) 1530 { 1531 struct msk_softc *sc; 1532 struct msk_if_softc *sc_if; 1533 struct ifnet *ifp; 1534 struct msk_mii_data *mmd; 1535 int i, port, error; 1536 uint8_t eaddr[6]; 1537 1538 if (dev == NULL) 1539 return (EINVAL); 1540 1541 error = 0; 1542 sc_if = device_get_softc(dev); 1543 sc = device_get_softc(device_get_parent(dev)); 1544 mmd = device_get_ivars(dev); 1545 port = mmd->port; 1546 1547 sc_if->msk_if_dev = dev; 1548 sc_if->msk_port = port; 1549 sc_if->msk_softc = sc; 1550 sc_if->msk_flags = sc->msk_pflags; 1551 sc->msk_if[port] = sc_if; 1552 /* Setup Tx/Rx queue register offsets. */ 1553 if (port == MSK_PORT_A) { 1554 sc_if->msk_txq = Q_XA1; 1555 sc_if->msk_txsq = Q_XS1; 1556 sc_if->msk_rxq = Q_R1; 1557 } else { 1558 sc_if->msk_txq = Q_XA2; 1559 sc_if->msk_txsq = Q_XS2; 1560 sc_if->msk_rxq = Q_R2; 1561 } 1562 1563 callout_init_mtx(&sc_if->msk_tick_ch, &sc_if->msk_softc->msk_mtx, 0); 1564 msk_sysctl_node(sc_if); 1565 1566 if ((error = msk_txrx_dma_alloc(sc_if) != 0)) 1567 goto fail; 1568 msk_rx_dma_jalloc(sc_if); 1569 1570 ifp = sc_if->msk_ifp = if_alloc(IFT_ETHER); 1571 if (ifp == NULL) { 1572 device_printf(sc_if->msk_if_dev, "can not if_alloc()\n"); 1573 error = ENOSPC; 1574 goto fail; 1575 } 1576 ifp->if_softc = sc_if; 1577 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1578 ifp->if_mtu = ETHERMTU; 1579 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1580 ifp->if_capabilities = IFCAP_TXCSUM | IFCAP_TSO4; 1581 /* 1582 * Enable Rx checksum offloading if controller supports 1583 * new descriptor formant and controller is not Yukon XL. 1584 */ 1585 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0 && 1586 sc->msk_hw_id != CHIP_ID_YUKON_XL) 1587 ifp->if_capabilities |= IFCAP_RXCSUM; 1588 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) != 0 && 1589 (sc_if->msk_flags & MSK_FLAG_NORX_CSUM) == 0) 1590 ifp->if_capabilities |= IFCAP_RXCSUM; 1591 ifp->if_hwassist = MSK_CSUM_FEATURES | CSUM_TSO; 1592 ifp->if_capenable = ifp->if_capabilities; 1593 ifp->if_ioctl = msk_ioctl; 1594 ifp->if_start = msk_start; 1595 ifp->if_init = msk_init; 1596 IFQ_SET_MAXLEN(&ifp->if_snd, MSK_TX_RING_CNT - 1); 1597 ifp->if_snd.ifq_drv_maxlen = MSK_TX_RING_CNT - 1; 1598 IFQ_SET_READY(&ifp->if_snd); 1599 /* 1600 * Get station address for this interface. Note that 1601 * dual port cards actually come with three station 1602 * addresses: one for each port, plus an extra. The 1603 * extra one is used by the SysKonnect driver software 1604 * as a 'virtual' station address for when both ports 1605 * are operating in failover mode. Currently we don't 1606 * use this extra address. 1607 */ 1608 MSK_IF_LOCK(sc_if); 1609 for (i = 0; i < ETHER_ADDR_LEN; i++) 1610 eaddr[i] = CSR_READ_1(sc, B2_MAC_1 + (port * 8) + i); 1611 1612 /* 1613 * Call MI attach routine. Can't hold locks when calling into ether_*. 1614 */ 1615 MSK_IF_UNLOCK(sc_if); 1616 ether_ifattach(ifp, eaddr); 1617 MSK_IF_LOCK(sc_if); 1618 1619 /* VLAN capability setup */ 1620 ifp->if_capabilities |= IFCAP_VLAN_MTU; 1621 if ((sc_if->msk_flags & MSK_FLAG_NOHWVLAN) == 0) { 1622 /* 1623 * Due to Tx checksum offload hardware bugs, msk(4) manually 1624 * computes checksum for short frames. For VLAN tagged frames 1625 * this workaround does not work so disable checksum offload 1626 * for VLAN interface. 1627 */ 1628 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWTSO; 1629 /* 1630 * Enable Rx checksum offloading for VLAN taggedd frames 1631 * if controller support new descriptor format. 1632 */ 1633 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) != 0 && 1634 (sc_if->msk_flags & MSK_FLAG_NORX_CSUM) == 0) 1635 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM; 1636 } 1637 ifp->if_capenable = ifp->if_capabilities; 1638 1639 /* 1640 * Tell the upper layer(s) we support long frames. 1641 * Must appear after the call to ether_ifattach() because 1642 * ether_ifattach() sets ifi_hdrlen to the default value. 1643 */ 1644 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1645 1646 /* 1647 * Do miibus setup. 1648 */ 1649 MSK_IF_UNLOCK(sc_if); 1650 error = mii_phy_probe(dev, &sc_if->msk_miibus, msk_mediachange, 1651 msk_mediastatus); 1652 if (error != 0) { 1653 device_printf(sc_if->msk_if_dev, "no PHY found!\n"); 1654 ether_ifdetach(ifp); 1655 error = ENXIO; 1656 goto fail; 1657 } 1658 1659 fail: 1660 if (error != 0) { 1661 /* Access should be ok even though lock has been dropped */ 1662 sc->msk_if[port] = NULL; 1663 msk_detach(dev); 1664 } 1665 1666 return (error); 1667 } 1668 1669 /* 1670 * Attach the interface. Allocate softc structures, do ifmedia 1671 * setup and ethernet/BPF attach. 1672 */ 1673 static int 1674 mskc_attach(device_t dev) 1675 { 1676 struct msk_softc *sc; 1677 struct msk_mii_data *mmd; 1678 int error, msic, msir, reg; 1679 1680 sc = device_get_softc(dev); 1681 sc->msk_dev = dev; 1682 mtx_init(&sc->msk_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1683 MTX_DEF); 1684 1685 /* 1686 * Map control/status registers. 1687 */ 1688 pci_enable_busmaster(dev); 1689 1690 /* Allocate I/O resource */ 1691 #ifdef MSK_USEIOSPACE 1692 sc->msk_res_spec = msk_res_spec_io; 1693 #else 1694 sc->msk_res_spec = msk_res_spec_mem; 1695 #endif 1696 sc->msk_irq_spec = msk_irq_spec_legacy; 1697 error = bus_alloc_resources(dev, sc->msk_res_spec, sc->msk_res); 1698 if (error) { 1699 if (sc->msk_res_spec == msk_res_spec_mem) 1700 sc->msk_res_spec = msk_res_spec_io; 1701 else 1702 sc->msk_res_spec = msk_res_spec_mem; 1703 error = bus_alloc_resources(dev, sc->msk_res_spec, sc->msk_res); 1704 if (error) { 1705 device_printf(dev, "couldn't allocate %s resources\n", 1706 sc->msk_res_spec == msk_res_spec_mem ? "memory" : 1707 "I/O"); 1708 mtx_destroy(&sc->msk_mtx); 1709 return (ENXIO); 1710 } 1711 } 1712 1713 CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR); 1714 sc->msk_hw_id = CSR_READ_1(sc, B2_CHIP_ID); 1715 sc->msk_hw_rev = (CSR_READ_1(sc, B2_MAC_CFG) >> 4) & 0x0f; 1716 /* Bail out if chip is not recognized. */ 1717 if (sc->msk_hw_id < CHIP_ID_YUKON_XL || 1718 sc->msk_hw_id > CHIP_ID_YUKON_OPT || 1719 sc->msk_hw_id == CHIP_ID_YUKON_SUPR || 1720 sc->msk_hw_id == CHIP_ID_YUKON_UNKNOWN) { 1721 device_printf(dev, "unknown device: id=0x%02x, rev=0x%02x\n", 1722 sc->msk_hw_id, sc->msk_hw_rev); 1723 mtx_destroy(&sc->msk_mtx); 1724 return (ENXIO); 1725 } 1726 1727 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 1728 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 1729 OID_AUTO, "process_limit", CTLTYPE_INT | CTLFLAG_RW, 1730 &sc->msk_process_limit, 0, sysctl_hw_msk_proc_limit, "I", 1731 "max number of Rx events to process"); 1732 1733 sc->msk_process_limit = MSK_PROC_DEFAULT; 1734 error = resource_int_value(device_get_name(dev), device_get_unit(dev), 1735 "process_limit", &sc->msk_process_limit); 1736 if (error == 0) { 1737 if (sc->msk_process_limit < MSK_PROC_MIN || 1738 sc->msk_process_limit > MSK_PROC_MAX) { 1739 device_printf(dev, "process_limit value out of range; " 1740 "using default: %d\n", MSK_PROC_DEFAULT); 1741 sc->msk_process_limit = MSK_PROC_DEFAULT; 1742 } 1743 } 1744 1745 sc->msk_int_holdoff = MSK_INT_HOLDOFF_DEFAULT; 1746 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 1747 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 1748 "int_holdoff", CTLFLAG_RW, &sc->msk_int_holdoff, 0, 1749 "Maximum number of time to delay interrupts"); 1750 resource_int_value(device_get_name(dev), device_get_unit(dev), 1751 "int_holdoff", &sc->msk_int_holdoff); 1752 1753 /* Soft reset. */ 1754 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); 1755 CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR); 1756 sc->msk_pmd = CSR_READ_1(sc, B2_PMD_TYP); 1757 /* Check number of MACs. */ 1758 sc->msk_num_port = 1; 1759 if ((CSR_READ_1(sc, B2_Y2_HW_RES) & CFG_DUAL_MAC_MSK) == 1760 CFG_DUAL_MAC_MSK) { 1761 if (!(CSR_READ_1(sc, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC)) 1762 sc->msk_num_port++; 1763 } 1764 1765 /* Check bus type. */ 1766 if (pci_find_extcap(sc->msk_dev, PCIY_EXPRESS, ®) == 0) { 1767 sc->msk_bustype = MSK_PEX_BUS; 1768 sc->msk_expcap = reg; 1769 } else if (pci_find_extcap(sc->msk_dev, PCIY_PCIX, ®) == 0) { 1770 sc->msk_bustype = MSK_PCIX_BUS; 1771 sc->msk_pcixcap = reg; 1772 } else 1773 sc->msk_bustype = MSK_PCI_BUS; 1774 1775 switch (sc->msk_hw_id) { 1776 case CHIP_ID_YUKON_EC: 1777 sc->msk_clock = 125; /* 125 MHz */ 1778 sc->msk_pflags |= MSK_FLAG_JUMBO; 1779 break; 1780 case CHIP_ID_YUKON_EC_U: 1781 sc->msk_clock = 125; /* 125 MHz */ 1782 sc->msk_pflags |= MSK_FLAG_JUMBO | MSK_FLAG_JUMBO_NOCSUM; 1783 break; 1784 case CHIP_ID_YUKON_EX: 1785 sc->msk_clock = 125; /* 125 MHz */ 1786 sc->msk_pflags |= MSK_FLAG_JUMBO | MSK_FLAG_DESCV2 | 1787 MSK_FLAG_AUTOTX_CSUM; 1788 /* 1789 * Yukon Extreme seems to have silicon bug for 1790 * automatic Tx checksum calculation capability. 1791 */ 1792 if (sc->msk_hw_rev == CHIP_REV_YU_EX_B0) 1793 sc->msk_pflags &= ~MSK_FLAG_AUTOTX_CSUM; 1794 /* 1795 * Yukon Extreme A0 could not use store-and-forward 1796 * for jumbo frames, so disable Tx checksum 1797 * offloading for jumbo frames. 1798 */ 1799 if (sc->msk_hw_rev == CHIP_REV_YU_EX_A0) 1800 sc->msk_pflags |= MSK_FLAG_JUMBO_NOCSUM; 1801 break; 1802 case CHIP_ID_YUKON_FE: 1803 sc->msk_clock = 100; /* 100 MHz */ 1804 sc->msk_pflags |= MSK_FLAG_FASTETHER; 1805 break; 1806 case CHIP_ID_YUKON_FE_P: 1807 sc->msk_clock = 50; /* 50 MHz */ 1808 sc->msk_pflags |= MSK_FLAG_FASTETHER | MSK_FLAG_DESCV2 | 1809 MSK_FLAG_AUTOTX_CSUM; 1810 if (sc->msk_hw_rev == CHIP_REV_YU_FE_P_A0) { 1811 /* 1812 * XXX 1813 * FE+ A0 has status LE writeback bug so msk(4) 1814 * does not rely on status word of received frame 1815 * in msk_rxeof() which in turn disables all 1816 * hardware assistance bits reported by the status 1817 * word as well as validity of the recevied frame. 1818 * Just pass received frames to upper stack with 1819 * minimal test and let upper stack handle them. 1820 */ 1821 sc->msk_pflags |= MSK_FLAG_NOHWVLAN | 1822 MSK_FLAG_NORXCHK | MSK_FLAG_NORX_CSUM; 1823 } 1824 break; 1825 case CHIP_ID_YUKON_XL: 1826 sc->msk_clock = 156; /* 156 MHz */ 1827 sc->msk_pflags |= MSK_FLAG_JUMBO; 1828 break; 1829 case CHIP_ID_YUKON_UL_2: 1830 sc->msk_clock = 125; /* 125 MHz */ 1831 sc->msk_pflags |= MSK_FLAG_JUMBO; 1832 break; 1833 case CHIP_ID_YUKON_OPT: 1834 sc->msk_clock = 125; /* 125 MHz */ 1835 sc->msk_pflags |= MSK_FLAG_JUMBO | MSK_FLAG_DESCV2; 1836 break; 1837 default: 1838 sc->msk_clock = 156; /* 156 MHz */ 1839 break; 1840 } 1841 1842 /* Allocate IRQ resources. */ 1843 msic = pci_msi_count(dev); 1844 if (bootverbose) 1845 device_printf(dev, "MSI count : %d\n", msic); 1846 if (legacy_intr != 0) 1847 msi_disable = 1; 1848 if (msi_disable == 0 && msic > 0) { 1849 msir = 1; 1850 if (pci_alloc_msi(dev, &msir) == 0) { 1851 if (msir == 1) { 1852 sc->msk_pflags |= MSK_FLAG_MSI; 1853 sc->msk_irq_spec = msk_irq_spec_msi; 1854 } else 1855 pci_release_msi(dev); 1856 } 1857 } 1858 1859 error = bus_alloc_resources(dev, sc->msk_irq_spec, sc->msk_irq); 1860 if (error) { 1861 device_printf(dev, "couldn't allocate IRQ resources\n"); 1862 goto fail; 1863 } 1864 1865 if ((error = msk_status_dma_alloc(sc)) != 0) 1866 goto fail; 1867 1868 /* Set base interrupt mask. */ 1869 sc->msk_intrmask = Y2_IS_HW_ERR | Y2_IS_STAT_BMU; 1870 sc->msk_intrhwemask = Y2_IS_TIST_OV | Y2_IS_MST_ERR | 1871 Y2_IS_IRQ_STAT | Y2_IS_PCI_EXP | Y2_IS_PCI_NEXP; 1872 1873 /* Reset the adapter. */ 1874 mskc_reset(sc); 1875 1876 if ((error = mskc_setup_rambuffer(sc)) != 0) 1877 goto fail; 1878 1879 sc->msk_devs[MSK_PORT_A] = device_add_child(dev, "msk", -1); 1880 if (sc->msk_devs[MSK_PORT_A] == NULL) { 1881 device_printf(dev, "failed to add child for PORT_A\n"); 1882 error = ENXIO; 1883 goto fail; 1884 } 1885 mmd = malloc(sizeof(struct msk_mii_data), M_DEVBUF, M_WAITOK | M_ZERO); 1886 if (mmd == NULL) { 1887 device_printf(dev, "failed to allocate memory for " 1888 "ivars of PORT_A\n"); 1889 error = ENXIO; 1890 goto fail; 1891 } 1892 mmd->port = MSK_PORT_A; 1893 mmd->pmd = sc->msk_pmd; 1894 if (sc->msk_pmd == 'L' || sc->msk_pmd == 'S' || sc->msk_pmd == 'P') 1895 mmd->mii_flags |= MIIF_HAVEFIBER; 1896 device_set_ivars(sc->msk_devs[MSK_PORT_A], mmd); 1897 1898 if (sc->msk_num_port > 1) { 1899 sc->msk_devs[MSK_PORT_B] = device_add_child(dev, "msk", -1); 1900 if (sc->msk_devs[MSK_PORT_B] == NULL) { 1901 device_printf(dev, "failed to add child for PORT_B\n"); 1902 error = ENXIO; 1903 goto fail; 1904 } 1905 mmd = malloc(sizeof(struct msk_mii_data), M_DEVBUF, M_WAITOK | M_ZERO); 1906 if (mmd == NULL) { 1907 device_printf(dev, "failed to allocate memory for " 1908 "ivars of PORT_B\n"); 1909 error = ENXIO; 1910 goto fail; 1911 } 1912 mmd->port = MSK_PORT_B; 1913 mmd->pmd = sc->msk_pmd; 1914 if (sc->msk_pmd == 'L' || sc->msk_pmd == 'S' || sc->msk_pmd == 'P') 1915 mmd->mii_flags |= MIIF_HAVEFIBER; 1916 device_set_ivars(sc->msk_devs[MSK_PORT_B], mmd); 1917 } 1918 1919 error = bus_generic_attach(dev); 1920 if (error) { 1921 device_printf(dev, "failed to attach port(s)\n"); 1922 goto fail; 1923 } 1924 1925 /* Hook interrupt last to avoid having to lock softc. */ 1926 error = bus_setup_intr(dev, sc->msk_irq[0], INTR_TYPE_NET | 1927 INTR_MPSAFE, NULL, msk_intr, sc, &sc->msk_intrhand); 1928 if (error != 0) { 1929 device_printf(dev, "couldn't set up interrupt handler\n"); 1930 goto fail; 1931 } 1932 fail: 1933 if (error != 0) 1934 mskc_detach(dev); 1935 1936 return (error); 1937 } 1938 1939 /* 1940 * Shutdown hardware and free up resources. This can be called any 1941 * time after the mutex has been initialized. It is called in both 1942 * the error case in attach and the normal detach case so it needs 1943 * to be careful about only freeing resources that have actually been 1944 * allocated. 1945 */ 1946 static int 1947 msk_detach(device_t dev) 1948 { 1949 struct msk_softc *sc; 1950 struct msk_if_softc *sc_if; 1951 struct ifnet *ifp; 1952 1953 sc_if = device_get_softc(dev); 1954 KASSERT(mtx_initialized(&sc_if->msk_softc->msk_mtx), 1955 ("msk mutex not initialized in msk_detach")); 1956 MSK_IF_LOCK(sc_if); 1957 1958 ifp = sc_if->msk_ifp; 1959 if (device_is_attached(dev)) { 1960 /* XXX */ 1961 sc_if->msk_flags |= MSK_FLAG_DETACH; 1962 msk_stop(sc_if); 1963 /* Can't hold locks while calling detach. */ 1964 MSK_IF_UNLOCK(sc_if); 1965 callout_drain(&sc_if->msk_tick_ch); 1966 ether_ifdetach(ifp); 1967 MSK_IF_LOCK(sc_if); 1968 } 1969 1970 /* 1971 * We're generally called from mskc_detach() which is using 1972 * device_delete_child() to get to here. It's already trashed 1973 * miibus for us, so don't do it here or we'll panic. 1974 * 1975 * if (sc_if->msk_miibus != NULL) { 1976 * device_delete_child(dev, sc_if->msk_miibus); 1977 * sc_if->msk_miibus = NULL; 1978 * } 1979 */ 1980 1981 msk_rx_dma_jfree(sc_if); 1982 msk_txrx_dma_free(sc_if); 1983 bus_generic_detach(dev); 1984 1985 if (ifp) 1986 if_free(ifp); 1987 sc = sc_if->msk_softc; 1988 sc->msk_if[sc_if->msk_port] = NULL; 1989 MSK_IF_UNLOCK(sc_if); 1990 1991 return (0); 1992 } 1993 1994 static int 1995 mskc_detach(device_t dev) 1996 { 1997 struct msk_softc *sc; 1998 1999 sc = device_get_softc(dev); 2000 KASSERT(mtx_initialized(&sc->msk_mtx), ("msk mutex not initialized")); 2001 2002 if (device_is_alive(dev)) { 2003 if (sc->msk_devs[MSK_PORT_A] != NULL) { 2004 free(device_get_ivars(sc->msk_devs[MSK_PORT_A]), 2005 M_DEVBUF); 2006 device_delete_child(dev, sc->msk_devs[MSK_PORT_A]); 2007 } 2008 if (sc->msk_devs[MSK_PORT_B] != NULL) { 2009 free(device_get_ivars(sc->msk_devs[MSK_PORT_B]), 2010 M_DEVBUF); 2011 device_delete_child(dev, sc->msk_devs[MSK_PORT_B]); 2012 } 2013 bus_generic_detach(dev); 2014 } 2015 2016 /* Disable all interrupts. */ 2017 CSR_WRITE_4(sc, B0_IMSK, 0); 2018 CSR_READ_4(sc, B0_IMSK); 2019 CSR_WRITE_4(sc, B0_HWE_IMSK, 0); 2020 CSR_READ_4(sc, B0_HWE_IMSK); 2021 2022 /* LED Off. */ 2023 CSR_WRITE_2(sc, B0_CTST, Y2_LED_STAT_OFF); 2024 2025 /* Put hardware reset. */ 2026 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); 2027 2028 msk_status_dma_free(sc); 2029 2030 if (sc->msk_intrhand) { 2031 bus_teardown_intr(dev, sc->msk_irq[0], sc->msk_intrhand); 2032 sc->msk_intrhand = NULL; 2033 } 2034 bus_release_resources(dev, sc->msk_irq_spec, sc->msk_irq); 2035 if ((sc->msk_pflags & MSK_FLAG_MSI) != 0) 2036 pci_release_msi(dev); 2037 bus_release_resources(dev, sc->msk_res_spec, sc->msk_res); 2038 mtx_destroy(&sc->msk_mtx); 2039 2040 return (0); 2041 } 2042 2043 struct msk_dmamap_arg { 2044 bus_addr_t msk_busaddr; 2045 }; 2046 2047 static void 2048 msk_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 2049 { 2050 struct msk_dmamap_arg *ctx; 2051 2052 if (error != 0) 2053 return; 2054 ctx = arg; 2055 ctx->msk_busaddr = segs[0].ds_addr; 2056 } 2057 2058 /* Create status DMA region. */ 2059 static int 2060 msk_status_dma_alloc(struct msk_softc *sc) 2061 { 2062 struct msk_dmamap_arg ctx; 2063 int error; 2064 2065 error = bus_dma_tag_create( 2066 bus_get_dma_tag(sc->msk_dev), /* parent */ 2067 MSK_STAT_ALIGN, 0, /* alignment, boundary */ 2068 BUS_SPACE_MAXADDR, /* lowaddr */ 2069 BUS_SPACE_MAXADDR, /* highaddr */ 2070 NULL, NULL, /* filter, filterarg */ 2071 MSK_STAT_RING_SZ, /* maxsize */ 2072 1, /* nsegments */ 2073 MSK_STAT_RING_SZ, /* maxsegsize */ 2074 0, /* flags */ 2075 NULL, NULL, /* lockfunc, lockarg */ 2076 &sc->msk_stat_tag); 2077 if (error != 0) { 2078 device_printf(sc->msk_dev, 2079 "failed to create status DMA tag\n"); 2080 return (error); 2081 } 2082 2083 /* Allocate DMA'able memory and load the DMA map for status ring. */ 2084 error = bus_dmamem_alloc(sc->msk_stat_tag, 2085 (void **)&sc->msk_stat_ring, BUS_DMA_WAITOK | BUS_DMA_COHERENT | 2086 BUS_DMA_ZERO, &sc->msk_stat_map); 2087 if (error != 0) { 2088 device_printf(sc->msk_dev, 2089 "failed to allocate DMA'able memory for status ring\n"); 2090 return (error); 2091 } 2092 2093 ctx.msk_busaddr = 0; 2094 error = bus_dmamap_load(sc->msk_stat_tag, 2095 sc->msk_stat_map, sc->msk_stat_ring, MSK_STAT_RING_SZ, 2096 msk_dmamap_cb, &ctx, 0); 2097 if (error != 0) { 2098 device_printf(sc->msk_dev, 2099 "failed to load DMA'able memory for status ring\n"); 2100 return (error); 2101 } 2102 sc->msk_stat_ring_paddr = ctx.msk_busaddr; 2103 2104 return (0); 2105 } 2106 2107 static void 2108 msk_status_dma_free(struct msk_softc *sc) 2109 { 2110 2111 /* Destroy status block. */ 2112 if (sc->msk_stat_tag) { 2113 if (sc->msk_stat_map) { 2114 bus_dmamap_unload(sc->msk_stat_tag, sc->msk_stat_map); 2115 if (sc->msk_stat_ring) { 2116 bus_dmamem_free(sc->msk_stat_tag, 2117 sc->msk_stat_ring, sc->msk_stat_map); 2118 sc->msk_stat_ring = NULL; 2119 } 2120 sc->msk_stat_map = NULL; 2121 } 2122 bus_dma_tag_destroy(sc->msk_stat_tag); 2123 sc->msk_stat_tag = NULL; 2124 } 2125 } 2126 2127 static int 2128 msk_txrx_dma_alloc(struct msk_if_softc *sc_if) 2129 { 2130 struct msk_dmamap_arg ctx; 2131 struct msk_txdesc *txd; 2132 struct msk_rxdesc *rxd; 2133 bus_size_t rxalign; 2134 int error, i; 2135 2136 /* Create parent DMA tag. */ 2137 /* 2138 * XXX 2139 * It seems that Yukon II supports full 64bits DMA operations. But 2140 * it needs two descriptors(list elements) for 64bits DMA operations. 2141 * Since we don't know what DMA address mappings(32bits or 64bits) 2142 * would be used in advance for each mbufs, we limits its DMA space 2143 * to be in range of 32bits address space. Otherwise, we should check 2144 * what DMA address is used and chain another descriptor for the 2145 * 64bits DMA operation. This also means descriptor ring size is 2146 * variable. Limiting DMA address to be in 32bit address space greatly 2147 * simplyfies descriptor handling and possibly would increase 2148 * performance a bit due to efficient handling of descriptors. 2149 * Apart from harassing checksum offloading mechanisms, it seems 2150 * it's really bad idea to use a seperate descriptor for 64bit 2151 * DMA operation to save small descriptor memory. Anyway, I've 2152 * never seen these exotic scheme on ethernet interface hardware. 2153 */ 2154 error = bus_dma_tag_create( 2155 bus_get_dma_tag(sc_if->msk_if_dev), /* parent */ 2156 1, 0, /* alignment, boundary */ 2157 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 2158 BUS_SPACE_MAXADDR, /* highaddr */ 2159 NULL, NULL, /* filter, filterarg */ 2160 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 2161 0, /* nsegments */ 2162 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 2163 0, /* flags */ 2164 NULL, NULL, /* lockfunc, lockarg */ 2165 &sc_if->msk_cdata.msk_parent_tag); 2166 if (error != 0) { 2167 device_printf(sc_if->msk_if_dev, 2168 "failed to create parent DMA tag\n"); 2169 goto fail; 2170 } 2171 /* Create tag for Tx ring. */ 2172 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2173 MSK_RING_ALIGN, 0, /* alignment, boundary */ 2174 BUS_SPACE_MAXADDR, /* lowaddr */ 2175 BUS_SPACE_MAXADDR, /* highaddr */ 2176 NULL, NULL, /* filter, filterarg */ 2177 MSK_TX_RING_SZ, /* maxsize */ 2178 1, /* nsegments */ 2179 MSK_TX_RING_SZ, /* maxsegsize */ 2180 0, /* flags */ 2181 NULL, NULL, /* lockfunc, lockarg */ 2182 &sc_if->msk_cdata.msk_tx_ring_tag); 2183 if (error != 0) { 2184 device_printf(sc_if->msk_if_dev, 2185 "failed to create Tx ring DMA tag\n"); 2186 goto fail; 2187 } 2188 2189 /* Create tag for Rx ring. */ 2190 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2191 MSK_RING_ALIGN, 0, /* alignment, boundary */ 2192 BUS_SPACE_MAXADDR, /* lowaddr */ 2193 BUS_SPACE_MAXADDR, /* highaddr */ 2194 NULL, NULL, /* filter, filterarg */ 2195 MSK_RX_RING_SZ, /* maxsize */ 2196 1, /* nsegments */ 2197 MSK_RX_RING_SZ, /* maxsegsize */ 2198 0, /* flags */ 2199 NULL, NULL, /* lockfunc, lockarg */ 2200 &sc_if->msk_cdata.msk_rx_ring_tag); 2201 if (error != 0) { 2202 device_printf(sc_if->msk_if_dev, 2203 "failed to create Rx ring DMA tag\n"); 2204 goto fail; 2205 } 2206 2207 /* Create tag for Tx buffers. */ 2208 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2209 1, 0, /* alignment, boundary */ 2210 BUS_SPACE_MAXADDR, /* lowaddr */ 2211 BUS_SPACE_MAXADDR, /* highaddr */ 2212 NULL, NULL, /* filter, filterarg */ 2213 MSK_TSO_MAXSIZE, /* maxsize */ 2214 MSK_MAXTXSEGS, /* nsegments */ 2215 MSK_TSO_MAXSGSIZE, /* maxsegsize */ 2216 0, /* flags */ 2217 NULL, NULL, /* lockfunc, lockarg */ 2218 &sc_if->msk_cdata.msk_tx_tag); 2219 if (error != 0) { 2220 device_printf(sc_if->msk_if_dev, 2221 "failed to create Tx DMA tag\n"); 2222 goto fail; 2223 } 2224 2225 rxalign = 1; 2226 /* 2227 * Workaround hardware hang which seems to happen when Rx buffer 2228 * is not aligned on multiple of FIFO word(8 bytes). 2229 */ 2230 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) != 0) 2231 rxalign = MSK_RX_BUF_ALIGN; 2232 /* Create tag for Rx buffers. */ 2233 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2234 rxalign, 0, /* alignment, boundary */ 2235 BUS_SPACE_MAXADDR, /* lowaddr */ 2236 BUS_SPACE_MAXADDR, /* highaddr */ 2237 NULL, NULL, /* filter, filterarg */ 2238 MCLBYTES, /* maxsize */ 2239 1, /* nsegments */ 2240 MCLBYTES, /* maxsegsize */ 2241 0, /* flags */ 2242 NULL, NULL, /* lockfunc, lockarg */ 2243 &sc_if->msk_cdata.msk_rx_tag); 2244 if (error != 0) { 2245 device_printf(sc_if->msk_if_dev, 2246 "failed to create Rx DMA tag\n"); 2247 goto fail; 2248 } 2249 2250 /* Allocate DMA'able memory and load the DMA map for Tx ring. */ 2251 error = bus_dmamem_alloc(sc_if->msk_cdata.msk_tx_ring_tag, 2252 (void **)&sc_if->msk_rdata.msk_tx_ring, BUS_DMA_WAITOK | 2253 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc_if->msk_cdata.msk_tx_ring_map); 2254 if (error != 0) { 2255 device_printf(sc_if->msk_if_dev, 2256 "failed to allocate DMA'able memory for Tx ring\n"); 2257 goto fail; 2258 } 2259 2260 ctx.msk_busaddr = 0; 2261 error = bus_dmamap_load(sc_if->msk_cdata.msk_tx_ring_tag, 2262 sc_if->msk_cdata.msk_tx_ring_map, sc_if->msk_rdata.msk_tx_ring, 2263 MSK_TX_RING_SZ, msk_dmamap_cb, &ctx, 0); 2264 if (error != 0) { 2265 device_printf(sc_if->msk_if_dev, 2266 "failed to load DMA'able memory for Tx ring\n"); 2267 goto fail; 2268 } 2269 sc_if->msk_rdata.msk_tx_ring_paddr = ctx.msk_busaddr; 2270 2271 /* Allocate DMA'able memory and load the DMA map for Rx ring. */ 2272 error = bus_dmamem_alloc(sc_if->msk_cdata.msk_rx_ring_tag, 2273 (void **)&sc_if->msk_rdata.msk_rx_ring, BUS_DMA_WAITOK | 2274 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc_if->msk_cdata.msk_rx_ring_map); 2275 if (error != 0) { 2276 device_printf(sc_if->msk_if_dev, 2277 "failed to allocate DMA'able memory for Rx ring\n"); 2278 goto fail; 2279 } 2280 2281 ctx.msk_busaddr = 0; 2282 error = bus_dmamap_load(sc_if->msk_cdata.msk_rx_ring_tag, 2283 sc_if->msk_cdata.msk_rx_ring_map, sc_if->msk_rdata.msk_rx_ring, 2284 MSK_RX_RING_SZ, msk_dmamap_cb, &ctx, 0); 2285 if (error != 0) { 2286 device_printf(sc_if->msk_if_dev, 2287 "failed to load DMA'able memory for Rx ring\n"); 2288 goto fail; 2289 } 2290 sc_if->msk_rdata.msk_rx_ring_paddr = ctx.msk_busaddr; 2291 2292 /* Create DMA maps for Tx buffers. */ 2293 for (i = 0; i < MSK_TX_RING_CNT; i++) { 2294 txd = &sc_if->msk_cdata.msk_txdesc[i]; 2295 txd->tx_m = NULL; 2296 txd->tx_dmamap = NULL; 2297 error = bus_dmamap_create(sc_if->msk_cdata.msk_tx_tag, 0, 2298 &txd->tx_dmamap); 2299 if (error != 0) { 2300 device_printf(sc_if->msk_if_dev, 2301 "failed to create Tx dmamap\n"); 2302 goto fail; 2303 } 2304 } 2305 /* Create DMA maps for Rx buffers. */ 2306 if ((error = bus_dmamap_create(sc_if->msk_cdata.msk_rx_tag, 0, 2307 &sc_if->msk_cdata.msk_rx_sparemap)) != 0) { 2308 device_printf(sc_if->msk_if_dev, 2309 "failed to create spare Rx dmamap\n"); 2310 goto fail; 2311 } 2312 for (i = 0; i < MSK_RX_RING_CNT; i++) { 2313 rxd = &sc_if->msk_cdata.msk_rxdesc[i]; 2314 rxd->rx_m = NULL; 2315 rxd->rx_dmamap = NULL; 2316 error = bus_dmamap_create(sc_if->msk_cdata.msk_rx_tag, 0, 2317 &rxd->rx_dmamap); 2318 if (error != 0) { 2319 device_printf(sc_if->msk_if_dev, 2320 "failed to create Rx dmamap\n"); 2321 goto fail; 2322 } 2323 } 2324 2325 fail: 2326 return (error); 2327 } 2328 2329 static int 2330 msk_rx_dma_jalloc(struct msk_if_softc *sc_if) 2331 { 2332 struct msk_dmamap_arg ctx; 2333 struct msk_rxdesc *jrxd; 2334 bus_size_t rxalign; 2335 int error, i; 2336 2337 if (jumbo_disable != 0 || (sc_if->msk_flags & MSK_FLAG_JUMBO) == 0) { 2338 sc_if->msk_flags &= ~MSK_FLAG_JUMBO; 2339 device_printf(sc_if->msk_if_dev, 2340 "disabling jumbo frame support\n"); 2341 return (0); 2342 } 2343 /* Create tag for jumbo Rx ring. */ 2344 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2345 MSK_RING_ALIGN, 0, /* alignment, boundary */ 2346 BUS_SPACE_MAXADDR, /* lowaddr */ 2347 BUS_SPACE_MAXADDR, /* highaddr */ 2348 NULL, NULL, /* filter, filterarg */ 2349 MSK_JUMBO_RX_RING_SZ, /* maxsize */ 2350 1, /* nsegments */ 2351 MSK_JUMBO_RX_RING_SZ, /* maxsegsize */ 2352 0, /* flags */ 2353 NULL, NULL, /* lockfunc, lockarg */ 2354 &sc_if->msk_cdata.msk_jumbo_rx_ring_tag); 2355 if (error != 0) { 2356 device_printf(sc_if->msk_if_dev, 2357 "failed to create jumbo Rx ring DMA tag\n"); 2358 goto jumbo_fail; 2359 } 2360 2361 rxalign = 1; 2362 /* 2363 * Workaround hardware hang which seems to happen when Rx buffer 2364 * is not aligned on multiple of FIFO word(8 bytes). 2365 */ 2366 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) != 0) 2367 rxalign = MSK_RX_BUF_ALIGN; 2368 /* Create tag for jumbo Rx buffers. */ 2369 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2370 rxalign, 0, /* alignment, boundary */ 2371 BUS_SPACE_MAXADDR, /* lowaddr */ 2372 BUS_SPACE_MAXADDR, /* highaddr */ 2373 NULL, NULL, /* filter, filterarg */ 2374 MJUM9BYTES, /* maxsize */ 2375 1, /* nsegments */ 2376 MJUM9BYTES, /* maxsegsize */ 2377 0, /* flags */ 2378 NULL, NULL, /* lockfunc, lockarg */ 2379 &sc_if->msk_cdata.msk_jumbo_rx_tag); 2380 if (error != 0) { 2381 device_printf(sc_if->msk_if_dev, 2382 "failed to create jumbo Rx DMA tag\n"); 2383 goto jumbo_fail; 2384 } 2385 2386 /* Allocate DMA'able memory and load the DMA map for jumbo Rx ring. */ 2387 error = bus_dmamem_alloc(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 2388 (void **)&sc_if->msk_rdata.msk_jumbo_rx_ring, 2389 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 2390 &sc_if->msk_cdata.msk_jumbo_rx_ring_map); 2391 if (error != 0) { 2392 device_printf(sc_if->msk_if_dev, 2393 "failed to allocate DMA'able memory for jumbo Rx ring\n"); 2394 goto jumbo_fail; 2395 } 2396 2397 ctx.msk_busaddr = 0; 2398 error = bus_dmamap_load(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 2399 sc_if->msk_cdata.msk_jumbo_rx_ring_map, 2400 sc_if->msk_rdata.msk_jumbo_rx_ring, MSK_JUMBO_RX_RING_SZ, 2401 msk_dmamap_cb, &ctx, 0); 2402 if (error != 0) { 2403 device_printf(sc_if->msk_if_dev, 2404 "failed to load DMA'able memory for jumbo Rx ring\n"); 2405 goto jumbo_fail; 2406 } 2407 sc_if->msk_rdata.msk_jumbo_rx_ring_paddr = ctx.msk_busaddr; 2408 2409 /* Create DMA maps for jumbo Rx buffers. */ 2410 if ((error = bus_dmamap_create(sc_if->msk_cdata.msk_jumbo_rx_tag, 0, 2411 &sc_if->msk_cdata.msk_jumbo_rx_sparemap)) != 0) { 2412 device_printf(sc_if->msk_if_dev, 2413 "failed to create spare jumbo Rx dmamap\n"); 2414 goto jumbo_fail; 2415 } 2416 for (i = 0; i < MSK_JUMBO_RX_RING_CNT; i++) { 2417 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[i]; 2418 jrxd->rx_m = NULL; 2419 jrxd->rx_dmamap = NULL; 2420 error = bus_dmamap_create(sc_if->msk_cdata.msk_jumbo_rx_tag, 0, 2421 &jrxd->rx_dmamap); 2422 if (error != 0) { 2423 device_printf(sc_if->msk_if_dev, 2424 "failed to create jumbo Rx dmamap\n"); 2425 goto jumbo_fail; 2426 } 2427 } 2428 2429 return (0); 2430 2431 jumbo_fail: 2432 msk_rx_dma_jfree(sc_if); 2433 device_printf(sc_if->msk_if_dev, "disabling jumbo frame support " 2434 "due to resource shortage\n"); 2435 sc_if->msk_flags &= ~MSK_FLAG_JUMBO; 2436 return (error); 2437 } 2438 2439 static void 2440 msk_txrx_dma_free(struct msk_if_softc *sc_if) 2441 { 2442 struct msk_txdesc *txd; 2443 struct msk_rxdesc *rxd; 2444 int i; 2445 2446 /* Tx ring. */ 2447 if (sc_if->msk_cdata.msk_tx_ring_tag) { 2448 if (sc_if->msk_cdata.msk_tx_ring_map) 2449 bus_dmamap_unload(sc_if->msk_cdata.msk_tx_ring_tag, 2450 sc_if->msk_cdata.msk_tx_ring_map); 2451 if (sc_if->msk_cdata.msk_tx_ring_map && 2452 sc_if->msk_rdata.msk_tx_ring) 2453 bus_dmamem_free(sc_if->msk_cdata.msk_tx_ring_tag, 2454 sc_if->msk_rdata.msk_tx_ring, 2455 sc_if->msk_cdata.msk_tx_ring_map); 2456 sc_if->msk_rdata.msk_tx_ring = NULL; 2457 sc_if->msk_cdata.msk_tx_ring_map = NULL; 2458 bus_dma_tag_destroy(sc_if->msk_cdata.msk_tx_ring_tag); 2459 sc_if->msk_cdata.msk_tx_ring_tag = NULL; 2460 } 2461 /* Rx ring. */ 2462 if (sc_if->msk_cdata.msk_rx_ring_tag) { 2463 if (sc_if->msk_cdata.msk_rx_ring_map) 2464 bus_dmamap_unload(sc_if->msk_cdata.msk_rx_ring_tag, 2465 sc_if->msk_cdata.msk_rx_ring_map); 2466 if (sc_if->msk_cdata.msk_rx_ring_map && 2467 sc_if->msk_rdata.msk_rx_ring) 2468 bus_dmamem_free(sc_if->msk_cdata.msk_rx_ring_tag, 2469 sc_if->msk_rdata.msk_rx_ring, 2470 sc_if->msk_cdata.msk_rx_ring_map); 2471 sc_if->msk_rdata.msk_rx_ring = NULL; 2472 sc_if->msk_cdata.msk_rx_ring_map = NULL; 2473 bus_dma_tag_destroy(sc_if->msk_cdata.msk_rx_ring_tag); 2474 sc_if->msk_cdata.msk_rx_ring_tag = NULL; 2475 } 2476 /* Tx buffers. */ 2477 if (sc_if->msk_cdata.msk_tx_tag) { 2478 for (i = 0; i < MSK_TX_RING_CNT; i++) { 2479 txd = &sc_if->msk_cdata.msk_txdesc[i]; 2480 if (txd->tx_dmamap) { 2481 bus_dmamap_destroy(sc_if->msk_cdata.msk_tx_tag, 2482 txd->tx_dmamap); 2483 txd->tx_dmamap = NULL; 2484 } 2485 } 2486 bus_dma_tag_destroy(sc_if->msk_cdata.msk_tx_tag); 2487 sc_if->msk_cdata.msk_tx_tag = NULL; 2488 } 2489 /* Rx buffers. */ 2490 if (sc_if->msk_cdata.msk_rx_tag) { 2491 for (i = 0; i < MSK_RX_RING_CNT; i++) { 2492 rxd = &sc_if->msk_cdata.msk_rxdesc[i]; 2493 if (rxd->rx_dmamap) { 2494 bus_dmamap_destroy(sc_if->msk_cdata.msk_rx_tag, 2495 rxd->rx_dmamap); 2496 rxd->rx_dmamap = NULL; 2497 } 2498 } 2499 if (sc_if->msk_cdata.msk_rx_sparemap) { 2500 bus_dmamap_destroy(sc_if->msk_cdata.msk_rx_tag, 2501 sc_if->msk_cdata.msk_rx_sparemap); 2502 sc_if->msk_cdata.msk_rx_sparemap = 0; 2503 } 2504 bus_dma_tag_destroy(sc_if->msk_cdata.msk_rx_tag); 2505 sc_if->msk_cdata.msk_rx_tag = NULL; 2506 } 2507 if (sc_if->msk_cdata.msk_parent_tag) { 2508 bus_dma_tag_destroy(sc_if->msk_cdata.msk_parent_tag); 2509 sc_if->msk_cdata.msk_parent_tag = NULL; 2510 } 2511 } 2512 2513 static void 2514 msk_rx_dma_jfree(struct msk_if_softc *sc_if) 2515 { 2516 struct msk_rxdesc *jrxd; 2517 int i; 2518 2519 /* Jumbo Rx ring. */ 2520 if (sc_if->msk_cdata.msk_jumbo_rx_ring_tag) { 2521 if (sc_if->msk_cdata.msk_jumbo_rx_ring_map) 2522 bus_dmamap_unload(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 2523 sc_if->msk_cdata.msk_jumbo_rx_ring_map); 2524 if (sc_if->msk_cdata.msk_jumbo_rx_ring_map && 2525 sc_if->msk_rdata.msk_jumbo_rx_ring) 2526 bus_dmamem_free(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 2527 sc_if->msk_rdata.msk_jumbo_rx_ring, 2528 sc_if->msk_cdata.msk_jumbo_rx_ring_map); 2529 sc_if->msk_rdata.msk_jumbo_rx_ring = NULL; 2530 sc_if->msk_cdata.msk_jumbo_rx_ring_map = NULL; 2531 bus_dma_tag_destroy(sc_if->msk_cdata.msk_jumbo_rx_ring_tag); 2532 sc_if->msk_cdata.msk_jumbo_rx_ring_tag = NULL; 2533 } 2534 /* Jumbo Rx buffers. */ 2535 if (sc_if->msk_cdata.msk_jumbo_rx_tag) { 2536 for (i = 0; i < MSK_JUMBO_RX_RING_CNT; i++) { 2537 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[i]; 2538 if (jrxd->rx_dmamap) { 2539 bus_dmamap_destroy( 2540 sc_if->msk_cdata.msk_jumbo_rx_tag, 2541 jrxd->rx_dmamap); 2542 jrxd->rx_dmamap = NULL; 2543 } 2544 } 2545 if (sc_if->msk_cdata.msk_jumbo_rx_sparemap) { 2546 bus_dmamap_destroy(sc_if->msk_cdata.msk_jumbo_rx_tag, 2547 sc_if->msk_cdata.msk_jumbo_rx_sparemap); 2548 sc_if->msk_cdata.msk_jumbo_rx_sparemap = 0; 2549 } 2550 bus_dma_tag_destroy(sc_if->msk_cdata.msk_jumbo_rx_tag); 2551 sc_if->msk_cdata.msk_jumbo_rx_tag = NULL; 2552 } 2553 } 2554 2555 static int 2556 msk_encap(struct msk_if_softc *sc_if, struct mbuf **m_head) 2557 { 2558 struct msk_txdesc *txd, *txd_last; 2559 struct msk_tx_desc *tx_le; 2560 struct mbuf *m; 2561 bus_dmamap_t map; 2562 bus_dma_segment_t txsegs[MSK_MAXTXSEGS]; 2563 uint32_t control, csum, prod, si; 2564 uint16_t offset, tcp_offset, tso_mtu; 2565 int error, i, nseg, tso; 2566 2567 MSK_IF_LOCK_ASSERT(sc_if); 2568 2569 tcp_offset = offset = 0; 2570 m = *m_head; 2571 if (((sc_if->msk_flags & MSK_FLAG_AUTOTX_CSUM) == 0 && 2572 (m->m_pkthdr.csum_flags & MSK_CSUM_FEATURES) != 0) || 2573 ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0 && 2574 (m->m_pkthdr.csum_flags & CSUM_TSO) != 0)) { 2575 /* 2576 * Since mbuf has no protocol specific structure information 2577 * in it we have to inspect protocol information here to 2578 * setup TSO and checksum offload. I don't know why Marvell 2579 * made a such decision in chip design because other GigE 2580 * hardwares normally takes care of all these chores in 2581 * hardware. However, TSO performance of Yukon II is very 2582 * good such that it's worth to implement it. 2583 */ 2584 struct ether_header *eh; 2585 struct ip *ip; 2586 struct tcphdr *tcp; 2587 2588 if (M_WRITABLE(m) == 0) { 2589 /* Get a writable copy. */ 2590 m = m_dup(*m_head, M_DONTWAIT); 2591 m_freem(*m_head); 2592 if (m == NULL) { 2593 *m_head = NULL; 2594 return (ENOBUFS); 2595 } 2596 *m_head = m; 2597 } 2598 2599 offset = sizeof(struct ether_header); 2600 m = m_pullup(m, offset); 2601 if (m == NULL) { 2602 *m_head = NULL; 2603 return (ENOBUFS); 2604 } 2605 eh = mtod(m, struct ether_header *); 2606 /* Check if hardware VLAN insertion is off. */ 2607 if (eh->ether_type == htons(ETHERTYPE_VLAN)) { 2608 offset = sizeof(struct ether_vlan_header); 2609 m = m_pullup(m, offset); 2610 if (m == NULL) { 2611 *m_head = NULL; 2612 return (ENOBUFS); 2613 } 2614 } 2615 m = m_pullup(m, offset + sizeof(struct ip)); 2616 if (m == NULL) { 2617 *m_head = NULL; 2618 return (ENOBUFS); 2619 } 2620 ip = (struct ip *)(mtod(m, char *) + offset); 2621 offset += (ip->ip_hl << 2); 2622 tcp_offset = offset; 2623 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 2624 m = m_pullup(m, offset + sizeof(struct tcphdr)); 2625 if (m == NULL) { 2626 *m_head = NULL; 2627 return (ENOBUFS); 2628 } 2629 tcp = (struct tcphdr *)(mtod(m, char *) + offset); 2630 offset += (tcp->th_off << 2); 2631 } else if ((sc_if->msk_flags & MSK_FLAG_AUTOTX_CSUM) == 0 && 2632 (m->m_pkthdr.len < MSK_MIN_FRAMELEN) && 2633 (m->m_pkthdr.csum_flags & CSUM_TCP) != 0) { 2634 /* 2635 * It seems that Yukon II has Tx checksum offload bug 2636 * for small TCP packets that's less than 60 bytes in 2637 * size (e.g. TCP window probe packet, pure ACK packet). 2638 * Common work around like padding with zeros to make 2639 * the frame minimum ethernet frame size didn't work at 2640 * all. 2641 * Instead of disabling checksum offload completely we 2642 * resort to S/W checksum routine when we encounter 2643 * short TCP frames. 2644 * Short UDP packets appear to be handled correctly by 2645 * Yukon II. Also I assume this bug does not happen on 2646 * controllers that use newer descriptor format or 2647 * automatic Tx checksum calaulcation. 2648 */ 2649 m = m_pullup(m, offset + sizeof(struct tcphdr)); 2650 if (m == NULL) { 2651 *m_head = NULL; 2652 return (ENOBUFS); 2653 } 2654 *(uint16_t *)(m->m_data + offset + 2655 m->m_pkthdr.csum_data) = in_cksum_skip(m, 2656 m->m_pkthdr.len, offset); 2657 m->m_pkthdr.csum_flags &= ~CSUM_TCP; 2658 } 2659 *m_head = m; 2660 } 2661 2662 prod = sc_if->msk_cdata.msk_tx_prod; 2663 txd = &sc_if->msk_cdata.msk_txdesc[prod]; 2664 txd_last = txd; 2665 map = txd->tx_dmamap; 2666 error = bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_tx_tag, map, 2667 *m_head, txsegs, &nseg, BUS_DMA_NOWAIT); 2668 if (error == EFBIG) { 2669 m = m_collapse(*m_head, M_DONTWAIT, MSK_MAXTXSEGS); 2670 if (m == NULL) { 2671 m_freem(*m_head); 2672 *m_head = NULL; 2673 return (ENOBUFS); 2674 } 2675 *m_head = m; 2676 error = bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_tx_tag, 2677 map, *m_head, txsegs, &nseg, BUS_DMA_NOWAIT); 2678 if (error != 0) { 2679 m_freem(*m_head); 2680 *m_head = NULL; 2681 return (error); 2682 } 2683 } else if (error != 0) 2684 return (error); 2685 if (nseg == 0) { 2686 m_freem(*m_head); 2687 *m_head = NULL; 2688 return (EIO); 2689 } 2690 2691 /* Check number of available descriptors. */ 2692 if (sc_if->msk_cdata.msk_tx_cnt + nseg >= 2693 (MSK_TX_RING_CNT - MSK_RESERVED_TX_DESC_CNT)) { 2694 bus_dmamap_unload(sc_if->msk_cdata.msk_tx_tag, map); 2695 return (ENOBUFS); 2696 } 2697 2698 control = 0; 2699 tso = 0; 2700 tx_le = NULL; 2701 2702 /* Check TSO support. */ 2703 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 2704 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) != 0) 2705 tso_mtu = m->m_pkthdr.tso_segsz; 2706 else 2707 tso_mtu = offset + m->m_pkthdr.tso_segsz; 2708 if (tso_mtu != sc_if->msk_cdata.msk_tso_mtu) { 2709 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2710 tx_le->msk_addr = htole32(tso_mtu); 2711 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) != 0) 2712 tx_le->msk_control = htole32(OP_MSS | HW_OWNER); 2713 else 2714 tx_le->msk_control = 2715 htole32(OP_LRGLEN | HW_OWNER); 2716 sc_if->msk_cdata.msk_tx_cnt++; 2717 MSK_INC(prod, MSK_TX_RING_CNT); 2718 sc_if->msk_cdata.msk_tso_mtu = tso_mtu; 2719 } 2720 tso++; 2721 } 2722 /* Check if we have a VLAN tag to insert. */ 2723 if ((m->m_flags & M_VLANTAG) != 0) { 2724 if (tx_le == NULL) { 2725 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2726 tx_le->msk_addr = htole32(0); 2727 tx_le->msk_control = htole32(OP_VLAN | HW_OWNER | 2728 htons(m->m_pkthdr.ether_vtag)); 2729 sc_if->msk_cdata.msk_tx_cnt++; 2730 MSK_INC(prod, MSK_TX_RING_CNT); 2731 } else { 2732 tx_le->msk_control |= htole32(OP_VLAN | 2733 htons(m->m_pkthdr.ether_vtag)); 2734 } 2735 control |= INS_VLAN; 2736 } 2737 /* Check if we have to handle checksum offload. */ 2738 if (tso == 0 && (m->m_pkthdr.csum_flags & MSK_CSUM_FEATURES) != 0) { 2739 if ((sc_if->msk_flags & MSK_FLAG_AUTOTX_CSUM) != 0) 2740 control |= CALSUM; 2741 else { 2742 control |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM; 2743 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0) 2744 control |= UDPTCP; 2745 /* Checksum write position. */ 2746 csum = (tcp_offset + m->m_pkthdr.csum_data) & 0xffff; 2747 /* Checksum start position. */ 2748 csum |= (uint32_t)tcp_offset << 16; 2749 if (csum != sc_if->msk_cdata.msk_last_csum) { 2750 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2751 tx_le->msk_addr = htole32(csum); 2752 tx_le->msk_control = htole32(1 << 16 | 2753 (OP_TCPLISW | HW_OWNER)); 2754 sc_if->msk_cdata.msk_tx_cnt++; 2755 MSK_INC(prod, MSK_TX_RING_CNT); 2756 sc_if->msk_cdata.msk_last_csum = csum; 2757 } 2758 } 2759 } 2760 2761 si = prod; 2762 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2763 tx_le->msk_addr = htole32(MSK_ADDR_LO(txsegs[0].ds_addr)); 2764 if (tso == 0) 2765 tx_le->msk_control = htole32(txsegs[0].ds_len | control | 2766 OP_PACKET); 2767 else 2768 tx_le->msk_control = htole32(txsegs[0].ds_len | control | 2769 OP_LARGESEND); 2770 sc_if->msk_cdata.msk_tx_cnt++; 2771 MSK_INC(prod, MSK_TX_RING_CNT); 2772 2773 for (i = 1; i < nseg; i++) { 2774 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2775 tx_le->msk_addr = htole32(MSK_ADDR_LO(txsegs[i].ds_addr)); 2776 tx_le->msk_control = htole32(txsegs[i].ds_len | control | 2777 OP_BUFFER | HW_OWNER); 2778 sc_if->msk_cdata.msk_tx_cnt++; 2779 MSK_INC(prod, MSK_TX_RING_CNT); 2780 } 2781 /* Update producer index. */ 2782 sc_if->msk_cdata.msk_tx_prod = prod; 2783 2784 /* Set EOP on the last desciptor. */ 2785 prod = (prod + MSK_TX_RING_CNT - 1) % MSK_TX_RING_CNT; 2786 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2787 tx_le->msk_control |= htole32(EOP); 2788 2789 /* Turn the first descriptor ownership to hardware. */ 2790 tx_le = &sc_if->msk_rdata.msk_tx_ring[si]; 2791 tx_le->msk_control |= htole32(HW_OWNER); 2792 2793 txd = &sc_if->msk_cdata.msk_txdesc[prod]; 2794 map = txd_last->tx_dmamap; 2795 txd_last->tx_dmamap = txd->tx_dmamap; 2796 txd->tx_dmamap = map; 2797 txd->tx_m = m; 2798 2799 /* Sync descriptors. */ 2800 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_tag, map, BUS_DMASYNC_PREWRITE); 2801 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_ring_tag, 2802 sc_if->msk_cdata.msk_tx_ring_map, 2803 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2804 2805 return (0); 2806 } 2807 2808 static void 2809 msk_start(struct ifnet *ifp) 2810 { 2811 struct msk_if_softc *sc_if; 2812 2813 sc_if = ifp->if_softc; 2814 MSK_IF_LOCK(sc_if); 2815 msk_start_locked(ifp); 2816 MSK_IF_UNLOCK(sc_if); 2817 } 2818 2819 static void 2820 msk_start_locked(struct ifnet *ifp) 2821 { 2822 struct msk_if_softc *sc_if; 2823 struct mbuf *m_head; 2824 int enq; 2825 2826 sc_if = ifp->if_softc; 2827 MSK_IF_LOCK_ASSERT(sc_if); 2828 2829 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2830 IFF_DRV_RUNNING || (sc_if->msk_flags & MSK_FLAG_LINK) == 0) 2831 return; 2832 2833 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 2834 sc_if->msk_cdata.msk_tx_cnt < 2835 (MSK_TX_RING_CNT - MSK_RESERVED_TX_DESC_CNT); ) { 2836 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2837 if (m_head == NULL) 2838 break; 2839 /* 2840 * Pack the data into the transmit ring. If we 2841 * don't have room, set the OACTIVE flag and wait 2842 * for the NIC to drain the ring. 2843 */ 2844 if (msk_encap(sc_if, &m_head) != 0) { 2845 if (m_head == NULL) 2846 break; 2847 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2848 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2849 break; 2850 } 2851 2852 enq++; 2853 /* 2854 * If there's a BPF listener, bounce a copy of this frame 2855 * to him. 2856 */ 2857 ETHER_BPF_MTAP(ifp, m_head); 2858 } 2859 2860 if (enq > 0) { 2861 /* Transmit */ 2862 CSR_WRITE_2(sc_if->msk_softc, 2863 Y2_PREF_Q_ADDR(sc_if->msk_txq, PREF_UNIT_PUT_IDX_REG), 2864 sc_if->msk_cdata.msk_tx_prod); 2865 2866 /* Set a timeout in case the chip goes out to lunch. */ 2867 sc_if->msk_watchdog_timer = MSK_TX_TIMEOUT; 2868 } 2869 } 2870 2871 static void 2872 msk_watchdog(struct msk_if_softc *sc_if) 2873 { 2874 struct ifnet *ifp; 2875 2876 MSK_IF_LOCK_ASSERT(sc_if); 2877 2878 if (sc_if->msk_watchdog_timer == 0 || --sc_if->msk_watchdog_timer) 2879 return; 2880 ifp = sc_if->msk_ifp; 2881 if ((sc_if->msk_flags & MSK_FLAG_LINK) == 0) { 2882 if (bootverbose) 2883 if_printf(sc_if->msk_ifp, "watchdog timeout " 2884 "(missed link)\n"); 2885 ifp->if_oerrors++; 2886 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2887 msk_init_locked(sc_if); 2888 return; 2889 } 2890 2891 if_printf(ifp, "watchdog timeout\n"); 2892 ifp->if_oerrors++; 2893 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2894 msk_init_locked(sc_if); 2895 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2896 msk_start_locked(ifp); 2897 } 2898 2899 static int 2900 mskc_shutdown(device_t dev) 2901 { 2902 struct msk_softc *sc; 2903 int i; 2904 2905 sc = device_get_softc(dev); 2906 MSK_LOCK(sc); 2907 for (i = 0; i < sc->msk_num_port; i++) { 2908 if (sc->msk_if[i] != NULL && sc->msk_if[i]->msk_ifp != NULL && 2909 ((sc->msk_if[i]->msk_ifp->if_drv_flags & 2910 IFF_DRV_RUNNING) != 0)) 2911 msk_stop(sc->msk_if[i]); 2912 } 2913 MSK_UNLOCK(sc); 2914 2915 /* Put hardware reset. */ 2916 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); 2917 return (0); 2918 } 2919 2920 static int 2921 mskc_suspend(device_t dev) 2922 { 2923 struct msk_softc *sc; 2924 int i; 2925 2926 sc = device_get_softc(dev); 2927 2928 MSK_LOCK(sc); 2929 2930 for (i = 0; i < sc->msk_num_port; i++) { 2931 if (sc->msk_if[i] != NULL && sc->msk_if[i]->msk_ifp != NULL && 2932 ((sc->msk_if[i]->msk_ifp->if_drv_flags & 2933 IFF_DRV_RUNNING) != 0)) 2934 msk_stop(sc->msk_if[i]); 2935 } 2936 2937 /* Disable all interrupts. */ 2938 CSR_WRITE_4(sc, B0_IMSK, 0); 2939 CSR_READ_4(sc, B0_IMSK); 2940 CSR_WRITE_4(sc, B0_HWE_IMSK, 0); 2941 CSR_READ_4(sc, B0_HWE_IMSK); 2942 2943 msk_phy_power(sc, MSK_PHY_POWERDOWN); 2944 2945 /* Put hardware reset. */ 2946 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); 2947 sc->msk_pflags |= MSK_FLAG_SUSPEND; 2948 2949 MSK_UNLOCK(sc); 2950 2951 return (0); 2952 } 2953 2954 static int 2955 mskc_resume(device_t dev) 2956 { 2957 struct msk_softc *sc; 2958 int i; 2959 2960 sc = device_get_softc(dev); 2961 2962 MSK_LOCK(sc); 2963 2964 mskc_reset(sc); 2965 for (i = 0; i < sc->msk_num_port; i++) { 2966 if (sc->msk_if[i] != NULL && sc->msk_if[i]->msk_ifp != NULL && 2967 ((sc->msk_if[i]->msk_ifp->if_flags & IFF_UP) != 0)) { 2968 sc->msk_if[i]->msk_ifp->if_drv_flags &= 2969 ~IFF_DRV_RUNNING; 2970 msk_init_locked(sc->msk_if[i]); 2971 } 2972 } 2973 sc->msk_pflags &= ~MSK_FLAG_SUSPEND; 2974 2975 MSK_UNLOCK(sc); 2976 2977 return (0); 2978 } 2979 2980 #ifndef __NO_STRICT_ALIGNMENT 2981 static __inline void 2982 msk_fixup_rx(struct mbuf *m) 2983 { 2984 int i; 2985 uint16_t *src, *dst; 2986 2987 src = mtod(m, uint16_t *); 2988 dst = src - 3; 2989 2990 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 2991 *dst++ = *src++; 2992 2993 m->m_data -= (MSK_RX_BUF_ALIGN - ETHER_ALIGN); 2994 } 2995 #endif 2996 2997 static __inline void 2998 msk_rxcsum(struct msk_if_softc *sc_if, uint32_t control, struct mbuf *m) 2999 { 3000 struct ether_header *eh; 3001 struct ip *ip; 3002 struct udphdr *uh; 3003 int32_t hlen, len, pktlen, temp32; 3004 uint16_t csum, *opts; 3005 3006 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) != 0) { 3007 if ((control & (CSS_IPV4 | CSS_IPFRAG)) == CSS_IPV4) { 3008 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 3009 if ((control & CSS_IPV4_CSUM_OK) != 0) 3010 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 3011 if ((control & (CSS_TCP | CSS_UDP)) != 0 && 3012 (control & (CSS_TCPUDP_CSUM_OK)) != 0) { 3013 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID | 3014 CSUM_PSEUDO_HDR; 3015 m->m_pkthdr.csum_data = 0xffff; 3016 } 3017 } 3018 return; 3019 } 3020 /* 3021 * Marvell Yukon controllers that support OP_RXCHKS has known 3022 * to have various Rx checksum offloading bugs. These 3023 * controllers can be configured to compute simple checksum 3024 * at two different positions. So we can compute IP and TCP/UDP 3025 * checksum at the same time. We intentionally have controller 3026 * compute TCP/UDP checksum twice by specifying the same 3027 * checksum start position and compare the result. If the value 3028 * is different it would indicate the hardware logic was wrong. 3029 */ 3030 if ((sc_if->msk_csum & 0xFFFF) != (sc_if->msk_csum >> 16)) { 3031 if (bootverbose) 3032 device_printf(sc_if->msk_if_dev, 3033 "Rx checksum value mismatch!\n"); 3034 return; 3035 } 3036 pktlen = m->m_pkthdr.len; 3037 if (pktlen < sizeof(struct ether_header) + sizeof(struct ip)) 3038 return; 3039 eh = mtod(m, struct ether_header *); 3040 if (eh->ether_type != htons(ETHERTYPE_IP)) 3041 return; 3042 ip = (struct ip *)(eh + 1); 3043 if (ip->ip_v != IPVERSION) 3044 return; 3045 3046 hlen = ip->ip_hl << 2; 3047 pktlen -= sizeof(struct ether_header); 3048 if (hlen < sizeof(struct ip)) 3049 return; 3050 if (ntohs(ip->ip_len) < hlen) 3051 return; 3052 if (ntohs(ip->ip_len) != pktlen) 3053 return; 3054 if (ip->ip_off & htons(IP_MF | IP_OFFMASK)) 3055 return; /* can't handle fragmented packet. */ 3056 3057 switch (ip->ip_p) { 3058 case IPPROTO_TCP: 3059 if (pktlen < (hlen + sizeof(struct tcphdr))) 3060 return; 3061 break; 3062 case IPPROTO_UDP: 3063 if (pktlen < (hlen + sizeof(struct udphdr))) 3064 return; 3065 uh = (struct udphdr *)((caddr_t)ip + hlen); 3066 if (uh->uh_sum == 0) 3067 return; /* no checksum */ 3068 break; 3069 default: 3070 return; 3071 } 3072 csum = ntohs(sc_if->msk_csum & 0xFFFF); 3073 /* Checksum fixup for IP options. */ 3074 len = hlen - sizeof(struct ip); 3075 if (len > 0) { 3076 opts = (uint16_t *)(ip + 1); 3077 for (; len > 0; len -= sizeof(uint16_t), opts++) { 3078 temp32 = csum - *opts; 3079 temp32 = (temp32 >> 16) + (temp32 & 65535); 3080 csum = temp32 & 65535; 3081 } 3082 } 3083 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID; 3084 m->m_pkthdr.csum_data = csum; 3085 } 3086 3087 static void 3088 msk_rxeof(struct msk_if_softc *sc_if, uint32_t status, uint32_t control, 3089 int len) 3090 { 3091 struct mbuf *m; 3092 struct ifnet *ifp; 3093 struct msk_rxdesc *rxd; 3094 int cons, rxlen; 3095 3096 ifp = sc_if->msk_ifp; 3097 3098 MSK_IF_LOCK_ASSERT(sc_if); 3099 3100 cons = sc_if->msk_cdata.msk_rx_cons; 3101 do { 3102 rxlen = status >> 16; 3103 if ((status & GMR_FS_VLAN) != 0 && 3104 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 3105 rxlen -= ETHER_VLAN_ENCAP_LEN; 3106 if ((sc_if->msk_flags & MSK_FLAG_NORXCHK) != 0) { 3107 /* 3108 * For controllers that returns bogus status code 3109 * just do minimal check and let upper stack 3110 * handle this frame. 3111 */ 3112 if (len > MSK_MAX_FRAMELEN || len < ETHER_HDR_LEN) { 3113 ifp->if_ierrors++; 3114 msk_discard_rxbuf(sc_if, cons); 3115 break; 3116 } 3117 } else if (len > sc_if->msk_framesize || 3118 ((status & GMR_FS_ANY_ERR) != 0) || 3119 ((status & GMR_FS_RX_OK) == 0) || (rxlen != len)) { 3120 /* Don't count flow-control packet as errors. */ 3121 if ((status & GMR_FS_GOOD_FC) == 0) 3122 ifp->if_ierrors++; 3123 msk_discard_rxbuf(sc_if, cons); 3124 break; 3125 } 3126 rxd = &sc_if->msk_cdata.msk_rxdesc[cons]; 3127 m = rxd->rx_m; 3128 if (msk_newbuf(sc_if, cons) != 0) { 3129 ifp->if_iqdrops++; 3130 /* Reuse old buffer. */ 3131 msk_discard_rxbuf(sc_if, cons); 3132 break; 3133 } 3134 m->m_pkthdr.rcvif = ifp; 3135 m->m_pkthdr.len = m->m_len = len; 3136 #ifndef __NO_STRICT_ALIGNMENT 3137 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) != 0) 3138 msk_fixup_rx(m); 3139 #endif 3140 ifp->if_ipackets++; 3141 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 3142 msk_rxcsum(sc_if, control, m); 3143 /* Check for VLAN tagged packets. */ 3144 if ((status & GMR_FS_VLAN) != 0 && 3145 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) { 3146 m->m_pkthdr.ether_vtag = sc_if->msk_vtag; 3147 m->m_flags |= M_VLANTAG; 3148 } 3149 MSK_IF_UNLOCK(sc_if); 3150 (*ifp->if_input)(ifp, m); 3151 MSK_IF_LOCK(sc_if); 3152 } while (0); 3153 3154 MSK_INC(sc_if->msk_cdata.msk_rx_cons, MSK_RX_RING_CNT); 3155 MSK_INC(sc_if->msk_cdata.msk_rx_prod, MSK_RX_RING_CNT); 3156 } 3157 3158 static void 3159 msk_jumbo_rxeof(struct msk_if_softc *sc_if, uint32_t status, uint32_t control, 3160 int len) 3161 { 3162 struct mbuf *m; 3163 struct ifnet *ifp; 3164 struct msk_rxdesc *jrxd; 3165 int cons, rxlen; 3166 3167 ifp = sc_if->msk_ifp; 3168 3169 MSK_IF_LOCK_ASSERT(sc_if); 3170 3171 cons = sc_if->msk_cdata.msk_rx_cons; 3172 do { 3173 rxlen = status >> 16; 3174 if ((status & GMR_FS_VLAN) != 0 && 3175 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 3176 rxlen -= ETHER_VLAN_ENCAP_LEN; 3177 if (len > sc_if->msk_framesize || 3178 ((status & GMR_FS_ANY_ERR) != 0) || 3179 ((status & GMR_FS_RX_OK) == 0) || (rxlen != len)) { 3180 /* Don't count flow-control packet as errors. */ 3181 if ((status & GMR_FS_GOOD_FC) == 0) 3182 ifp->if_ierrors++; 3183 msk_discard_jumbo_rxbuf(sc_if, cons); 3184 break; 3185 } 3186 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[cons]; 3187 m = jrxd->rx_m; 3188 if (msk_jumbo_newbuf(sc_if, cons) != 0) { 3189 ifp->if_iqdrops++; 3190 /* Reuse old buffer. */ 3191 msk_discard_jumbo_rxbuf(sc_if, cons); 3192 break; 3193 } 3194 m->m_pkthdr.rcvif = ifp; 3195 m->m_pkthdr.len = m->m_len = len; 3196 #ifndef __NO_STRICT_ALIGNMENT 3197 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) != 0) 3198 msk_fixup_rx(m); 3199 #endif 3200 ifp->if_ipackets++; 3201 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 3202 msk_rxcsum(sc_if, control, m); 3203 /* Check for VLAN tagged packets. */ 3204 if ((status & GMR_FS_VLAN) != 0 && 3205 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) { 3206 m->m_pkthdr.ether_vtag = sc_if->msk_vtag; 3207 m->m_flags |= M_VLANTAG; 3208 } 3209 MSK_IF_UNLOCK(sc_if); 3210 (*ifp->if_input)(ifp, m); 3211 MSK_IF_LOCK(sc_if); 3212 } while (0); 3213 3214 MSK_INC(sc_if->msk_cdata.msk_rx_cons, MSK_JUMBO_RX_RING_CNT); 3215 MSK_INC(sc_if->msk_cdata.msk_rx_prod, MSK_JUMBO_RX_RING_CNT); 3216 } 3217 3218 static void 3219 msk_txeof(struct msk_if_softc *sc_if, int idx) 3220 { 3221 struct msk_txdesc *txd; 3222 struct msk_tx_desc *cur_tx; 3223 struct ifnet *ifp; 3224 uint32_t control; 3225 int cons, prog; 3226 3227 MSK_IF_LOCK_ASSERT(sc_if); 3228 3229 ifp = sc_if->msk_ifp; 3230 3231 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_ring_tag, 3232 sc_if->msk_cdata.msk_tx_ring_map, 3233 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3234 /* 3235 * Go through our tx ring and free mbufs for those 3236 * frames that have been sent. 3237 */ 3238 cons = sc_if->msk_cdata.msk_tx_cons; 3239 prog = 0; 3240 for (; cons != idx; MSK_INC(cons, MSK_TX_RING_CNT)) { 3241 if (sc_if->msk_cdata.msk_tx_cnt <= 0) 3242 break; 3243 prog++; 3244 cur_tx = &sc_if->msk_rdata.msk_tx_ring[cons]; 3245 control = le32toh(cur_tx->msk_control); 3246 sc_if->msk_cdata.msk_tx_cnt--; 3247 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3248 if ((control & EOP) == 0) 3249 continue; 3250 txd = &sc_if->msk_cdata.msk_txdesc[cons]; 3251 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_tag, txd->tx_dmamap, 3252 BUS_DMASYNC_POSTWRITE); 3253 bus_dmamap_unload(sc_if->msk_cdata.msk_tx_tag, txd->tx_dmamap); 3254 3255 ifp->if_opackets++; 3256 KASSERT(txd->tx_m != NULL, ("%s: freeing NULL mbuf!", 3257 __func__)); 3258 m_freem(txd->tx_m); 3259 txd->tx_m = NULL; 3260 } 3261 3262 if (prog > 0) { 3263 sc_if->msk_cdata.msk_tx_cons = cons; 3264 if (sc_if->msk_cdata.msk_tx_cnt == 0) 3265 sc_if->msk_watchdog_timer = 0; 3266 /* No need to sync LEs as we didn't update LEs. */ 3267 } 3268 } 3269 3270 static void 3271 msk_tick(void *xsc_if) 3272 { 3273 struct msk_if_softc *sc_if; 3274 struct mii_data *mii; 3275 3276 sc_if = xsc_if; 3277 3278 MSK_IF_LOCK_ASSERT(sc_if); 3279 3280 mii = device_get_softc(sc_if->msk_miibus); 3281 3282 mii_tick(mii); 3283 if ((sc_if->msk_flags & MSK_FLAG_LINK) == 0) 3284 msk_miibus_statchg(sc_if->msk_if_dev); 3285 msk_handle_events(sc_if->msk_softc); 3286 msk_watchdog(sc_if); 3287 callout_reset(&sc_if->msk_tick_ch, hz, msk_tick, sc_if); 3288 } 3289 3290 static void 3291 msk_intr_phy(struct msk_if_softc *sc_if) 3292 { 3293 uint16_t status; 3294 3295 msk_phy_readreg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_STAT); 3296 status = msk_phy_readreg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_STAT); 3297 /* Handle FIFO Underrun/Overflow? */ 3298 if ((status & PHY_M_IS_FIFO_ERROR)) 3299 device_printf(sc_if->msk_if_dev, 3300 "PHY FIFO underrun/overflow.\n"); 3301 } 3302 3303 static void 3304 msk_intr_gmac(struct msk_if_softc *sc_if) 3305 { 3306 struct msk_softc *sc; 3307 uint8_t status; 3308 3309 sc = sc_if->msk_softc; 3310 status = CSR_READ_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_SRC)); 3311 3312 /* GMAC Rx FIFO overrun. */ 3313 if ((status & GM_IS_RX_FF_OR) != 0) 3314 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), 3315 GMF_CLI_RX_FO); 3316 /* GMAC Tx FIFO underrun. */ 3317 if ((status & GM_IS_TX_FF_UR) != 0) { 3318 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 3319 GMF_CLI_TX_FU); 3320 device_printf(sc_if->msk_if_dev, "Tx FIFO underrun!\n"); 3321 /* 3322 * XXX 3323 * In case of Tx underrun, we may need to flush/reset 3324 * Tx MAC but that would also require resynchronization 3325 * with status LEs. Reintializing status LEs would 3326 * affect other port in dual MAC configuration so it 3327 * should be avoided as possible as we can. 3328 * Due to lack of documentation it's all vague guess but 3329 * it needs more investigation. 3330 */ 3331 } 3332 } 3333 3334 static void 3335 msk_handle_hwerr(struct msk_if_softc *sc_if, uint32_t status) 3336 { 3337 struct msk_softc *sc; 3338 3339 sc = sc_if->msk_softc; 3340 if ((status & Y2_IS_PAR_RD1) != 0) { 3341 device_printf(sc_if->msk_if_dev, 3342 "RAM buffer read parity error\n"); 3343 /* Clear IRQ. */ 3344 CSR_WRITE_2(sc, SELECT_RAM_BUFFER(sc_if->msk_port, B3_RI_CTRL), 3345 RI_CLR_RD_PERR); 3346 } 3347 if ((status & Y2_IS_PAR_WR1) != 0) { 3348 device_printf(sc_if->msk_if_dev, 3349 "RAM buffer write parity error\n"); 3350 /* Clear IRQ. */ 3351 CSR_WRITE_2(sc, SELECT_RAM_BUFFER(sc_if->msk_port, B3_RI_CTRL), 3352 RI_CLR_WR_PERR); 3353 } 3354 if ((status & Y2_IS_PAR_MAC1) != 0) { 3355 device_printf(sc_if->msk_if_dev, "Tx MAC parity error\n"); 3356 /* Clear IRQ. */ 3357 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 3358 GMF_CLI_TX_PE); 3359 } 3360 if ((status & Y2_IS_PAR_RX1) != 0) { 3361 device_printf(sc_if->msk_if_dev, "Rx parity error\n"); 3362 /* Clear IRQ. */ 3363 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_CLR_IRQ_PAR); 3364 } 3365 if ((status & (Y2_IS_TCP_TXS1 | Y2_IS_TCP_TXA1)) != 0) { 3366 device_printf(sc_if->msk_if_dev, "TCP segmentation error\n"); 3367 /* Clear IRQ. */ 3368 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_CLR_IRQ_TCP); 3369 } 3370 } 3371 3372 static void 3373 msk_intr_hwerr(struct msk_softc *sc) 3374 { 3375 uint32_t status; 3376 uint32_t tlphead[4]; 3377 3378 status = CSR_READ_4(sc, B0_HWE_ISRC); 3379 /* Time Stamp timer overflow. */ 3380 if ((status & Y2_IS_TIST_OV) != 0) 3381 CSR_WRITE_1(sc, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ); 3382 if ((status & Y2_IS_PCI_NEXP) != 0) { 3383 /* 3384 * PCI Express Error occured which is not described in PEX 3385 * spec. 3386 * This error is also mapped either to Master Abort( 3387 * Y2_IS_MST_ERR) or Target Abort (Y2_IS_IRQ_STAT) bit and 3388 * can only be cleared there. 3389 */ 3390 device_printf(sc->msk_dev, 3391 "PCI Express protocol violation error\n"); 3392 } 3393 3394 if ((status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) != 0) { 3395 uint16_t v16; 3396 3397 if ((status & Y2_IS_MST_ERR) != 0) 3398 device_printf(sc->msk_dev, 3399 "unexpected IRQ Status error\n"); 3400 else 3401 device_printf(sc->msk_dev, 3402 "unexpected IRQ Master error\n"); 3403 /* Reset all bits in the PCI status register. */ 3404 v16 = pci_read_config(sc->msk_dev, PCIR_STATUS, 2); 3405 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON); 3406 pci_write_config(sc->msk_dev, PCIR_STATUS, v16 | 3407 PCIM_STATUS_PERR | PCIM_STATUS_SERR | PCIM_STATUS_RMABORT | 3408 PCIM_STATUS_RTABORT | PCIM_STATUS_PERRREPORT, 2); 3409 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 3410 } 3411 3412 /* Check for PCI Express Uncorrectable Error. */ 3413 if ((status & Y2_IS_PCI_EXP) != 0) { 3414 uint32_t v32; 3415 3416 /* 3417 * On PCI Express bus bridges are called root complexes (RC). 3418 * PCI Express errors are recognized by the root complex too, 3419 * which requests the system to handle the problem. After 3420 * error occurence it may be that no access to the adapter 3421 * may be performed any longer. 3422 */ 3423 3424 v32 = CSR_PCI_READ_4(sc, PEX_UNC_ERR_STAT); 3425 if ((v32 & PEX_UNSUP_REQ) != 0) { 3426 /* Ignore unsupported request error. */ 3427 device_printf(sc->msk_dev, 3428 "Uncorrectable PCI Express error\n"); 3429 } 3430 if ((v32 & (PEX_FATAL_ERRORS | PEX_POIS_TLP)) != 0) { 3431 int i; 3432 3433 /* Get TLP header form Log Registers. */ 3434 for (i = 0; i < 4; i++) 3435 tlphead[i] = CSR_PCI_READ_4(sc, 3436 PEX_HEADER_LOG + i * 4); 3437 /* Check for vendor defined broadcast message. */ 3438 if (!(tlphead[0] == 0x73004001 && tlphead[1] == 0x7f)) { 3439 sc->msk_intrhwemask &= ~Y2_IS_PCI_EXP; 3440 CSR_WRITE_4(sc, B0_HWE_IMSK, 3441 sc->msk_intrhwemask); 3442 CSR_READ_4(sc, B0_HWE_IMSK); 3443 } 3444 } 3445 /* Clear the interrupt. */ 3446 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON); 3447 CSR_PCI_WRITE_4(sc, PEX_UNC_ERR_STAT, 0xffffffff); 3448 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 3449 } 3450 3451 if ((status & Y2_HWE_L1_MASK) != 0 && sc->msk_if[MSK_PORT_A] != NULL) 3452 msk_handle_hwerr(sc->msk_if[MSK_PORT_A], status); 3453 if ((status & Y2_HWE_L2_MASK) != 0 && sc->msk_if[MSK_PORT_B] != NULL) 3454 msk_handle_hwerr(sc->msk_if[MSK_PORT_B], status >> 8); 3455 } 3456 3457 static __inline void 3458 msk_rxput(struct msk_if_softc *sc_if) 3459 { 3460 struct msk_softc *sc; 3461 3462 sc = sc_if->msk_softc; 3463 if (sc_if->msk_framesize > (MCLBYTES - MSK_RX_BUF_ALIGN)) 3464 bus_dmamap_sync( 3465 sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 3466 sc_if->msk_cdata.msk_jumbo_rx_ring_map, 3467 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3468 else 3469 bus_dmamap_sync( 3470 sc_if->msk_cdata.msk_rx_ring_tag, 3471 sc_if->msk_cdata.msk_rx_ring_map, 3472 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3473 CSR_WRITE_2(sc, Y2_PREF_Q_ADDR(sc_if->msk_rxq, 3474 PREF_UNIT_PUT_IDX_REG), sc_if->msk_cdata.msk_rx_prod); 3475 } 3476 3477 static int 3478 msk_handle_events(struct msk_softc *sc) 3479 { 3480 struct msk_if_softc *sc_if; 3481 int rxput[2]; 3482 struct msk_stat_desc *sd; 3483 uint32_t control, status; 3484 int cons, len, port, rxprog; 3485 3486 if (sc->msk_stat_cons == CSR_READ_2(sc, STAT_PUT_IDX)) 3487 return (0); 3488 3489 /* Sync status LEs. */ 3490 bus_dmamap_sync(sc->msk_stat_tag, sc->msk_stat_map, 3491 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3492 3493 rxput[MSK_PORT_A] = rxput[MSK_PORT_B] = 0; 3494 rxprog = 0; 3495 cons = sc->msk_stat_cons; 3496 for (;;) { 3497 sd = &sc->msk_stat_ring[cons]; 3498 control = le32toh(sd->msk_control); 3499 if ((control & HW_OWNER) == 0) 3500 break; 3501 control &= ~HW_OWNER; 3502 sd->msk_control = htole32(control); 3503 status = le32toh(sd->msk_status); 3504 len = control & STLE_LEN_MASK; 3505 port = (control >> 16) & 0x01; 3506 sc_if = sc->msk_if[port]; 3507 if (sc_if == NULL) { 3508 device_printf(sc->msk_dev, "invalid port opcode " 3509 "0x%08x\n", control & STLE_OP_MASK); 3510 continue; 3511 } 3512 3513 switch (control & STLE_OP_MASK) { 3514 case OP_RXVLAN: 3515 sc_if->msk_vtag = ntohs(len); 3516 break; 3517 case OP_RXCHKSVLAN: 3518 sc_if->msk_vtag = ntohs(len); 3519 /* FALLTHROUGH */ 3520 case OP_RXCHKS: 3521 sc_if->msk_csum = status; 3522 break; 3523 case OP_RXSTAT: 3524 if (!(sc_if->msk_ifp->if_drv_flags & IFF_DRV_RUNNING)) 3525 break; 3526 if (sc_if->msk_framesize > 3527 (MCLBYTES - MSK_RX_BUF_ALIGN)) 3528 msk_jumbo_rxeof(sc_if, status, control, len); 3529 else 3530 msk_rxeof(sc_if, status, control, len); 3531 rxprog++; 3532 /* 3533 * Because there is no way to sync single Rx LE 3534 * put the DMA sync operation off until the end of 3535 * event processing. 3536 */ 3537 rxput[port]++; 3538 /* Update prefetch unit if we've passed water mark. */ 3539 if (rxput[port] >= sc_if->msk_cdata.msk_rx_putwm) { 3540 msk_rxput(sc_if); 3541 rxput[port] = 0; 3542 } 3543 break; 3544 case OP_TXINDEXLE: 3545 if (sc->msk_if[MSK_PORT_A] != NULL) 3546 msk_txeof(sc->msk_if[MSK_PORT_A], 3547 status & STLE_TXA1_MSKL); 3548 if (sc->msk_if[MSK_PORT_B] != NULL) 3549 msk_txeof(sc->msk_if[MSK_PORT_B], 3550 ((status & STLE_TXA2_MSKL) >> 3551 STLE_TXA2_SHIFTL) | 3552 ((len & STLE_TXA2_MSKH) << 3553 STLE_TXA2_SHIFTH)); 3554 break; 3555 default: 3556 device_printf(sc->msk_dev, "unhandled opcode 0x%08x\n", 3557 control & STLE_OP_MASK); 3558 break; 3559 } 3560 MSK_INC(cons, MSK_STAT_RING_CNT); 3561 if (rxprog > sc->msk_process_limit) 3562 break; 3563 } 3564 3565 sc->msk_stat_cons = cons; 3566 bus_dmamap_sync(sc->msk_stat_tag, sc->msk_stat_map, 3567 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3568 3569 if (rxput[MSK_PORT_A] > 0) 3570 msk_rxput(sc->msk_if[MSK_PORT_A]); 3571 if (rxput[MSK_PORT_B] > 0) 3572 msk_rxput(sc->msk_if[MSK_PORT_B]); 3573 3574 return (sc->msk_stat_cons != CSR_READ_2(sc, STAT_PUT_IDX)); 3575 } 3576 3577 static void 3578 msk_intr(void *xsc) 3579 { 3580 struct msk_softc *sc; 3581 struct msk_if_softc *sc_if0, *sc_if1; 3582 struct ifnet *ifp0, *ifp1; 3583 uint32_t status; 3584 int domore; 3585 3586 sc = xsc; 3587 MSK_LOCK(sc); 3588 3589 /* Reading B0_Y2_SP_ISRC2 masks further interrupts. */ 3590 status = CSR_READ_4(sc, B0_Y2_SP_ISRC2); 3591 if (status == 0 || status == 0xffffffff || 3592 (sc->msk_pflags & MSK_FLAG_SUSPEND) != 0 || 3593 (status & sc->msk_intrmask) == 0) { 3594 CSR_WRITE_4(sc, B0_Y2_SP_ICR, 2); 3595 MSK_UNLOCK(sc); 3596 return; 3597 } 3598 3599 sc_if0 = sc->msk_if[MSK_PORT_A]; 3600 sc_if1 = sc->msk_if[MSK_PORT_B]; 3601 ifp0 = ifp1 = NULL; 3602 if (sc_if0 != NULL) 3603 ifp0 = sc_if0->msk_ifp; 3604 if (sc_if1 != NULL) 3605 ifp1 = sc_if1->msk_ifp; 3606 3607 if ((status & Y2_IS_IRQ_PHY1) != 0 && sc_if0 != NULL) 3608 msk_intr_phy(sc_if0); 3609 if ((status & Y2_IS_IRQ_PHY2) != 0 && sc_if1 != NULL) 3610 msk_intr_phy(sc_if1); 3611 if ((status & Y2_IS_IRQ_MAC1) != 0 && sc_if0 != NULL) 3612 msk_intr_gmac(sc_if0); 3613 if ((status & Y2_IS_IRQ_MAC2) != 0 && sc_if1 != NULL) 3614 msk_intr_gmac(sc_if1); 3615 if ((status & (Y2_IS_CHK_RX1 | Y2_IS_CHK_RX2)) != 0) { 3616 device_printf(sc->msk_dev, "Rx descriptor error\n"); 3617 sc->msk_intrmask &= ~(Y2_IS_CHK_RX1 | Y2_IS_CHK_RX2); 3618 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask); 3619 CSR_READ_4(sc, B0_IMSK); 3620 } 3621 if ((status & (Y2_IS_CHK_TXA1 | Y2_IS_CHK_TXA2)) != 0) { 3622 device_printf(sc->msk_dev, "Tx descriptor error\n"); 3623 sc->msk_intrmask &= ~(Y2_IS_CHK_TXA1 | Y2_IS_CHK_TXA2); 3624 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask); 3625 CSR_READ_4(sc, B0_IMSK); 3626 } 3627 if ((status & Y2_IS_HW_ERR) != 0) 3628 msk_intr_hwerr(sc); 3629 3630 domore = msk_handle_events(sc); 3631 if ((status & Y2_IS_STAT_BMU) != 0 && domore == 0) 3632 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_CLR_IRQ); 3633 3634 /* Reenable interrupts. */ 3635 CSR_WRITE_4(sc, B0_Y2_SP_ICR, 2); 3636 3637 if (ifp0 != NULL && (ifp0->if_drv_flags & IFF_DRV_RUNNING) != 0 && 3638 !IFQ_DRV_IS_EMPTY(&ifp0->if_snd)) 3639 msk_start_locked(ifp0); 3640 if (ifp1 != NULL && (ifp1->if_drv_flags & IFF_DRV_RUNNING) != 0 && 3641 !IFQ_DRV_IS_EMPTY(&ifp1->if_snd)) 3642 msk_start_locked(ifp1); 3643 3644 MSK_UNLOCK(sc); 3645 } 3646 3647 static void 3648 msk_set_tx_stfwd(struct msk_if_softc *sc_if) 3649 { 3650 struct msk_softc *sc; 3651 struct ifnet *ifp; 3652 3653 ifp = sc_if->msk_ifp; 3654 sc = sc_if->msk_softc; 3655 switch (sc->msk_hw_id) { 3656 case CHIP_ID_YUKON_EX: 3657 if (sc->msk_hw_rev == CHIP_REV_YU_EX_A0) 3658 goto yukon_ex_workaround; 3659 if (ifp->if_mtu > ETHERMTU) 3660 CSR_WRITE_4(sc, 3661 MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 3662 TX_JUMBO_ENA | TX_STFW_ENA); 3663 else 3664 CSR_WRITE_4(sc, 3665 MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 3666 TX_JUMBO_DIS | TX_STFW_ENA); 3667 break; 3668 default: 3669 yukon_ex_workaround: 3670 if (ifp->if_mtu > ETHERMTU) { 3671 /* Set Tx GMAC FIFO Almost Empty Threshold. */ 3672 CSR_WRITE_4(sc, 3673 MR_ADDR(sc_if->msk_port, TX_GMF_AE_THR), 3674 MSK_ECU_JUMBO_WM << 16 | MSK_ECU_AE_THR); 3675 /* Disable Store & Forward mode for Tx. */ 3676 CSR_WRITE_4(sc, 3677 MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 3678 TX_JUMBO_ENA | TX_STFW_DIS); 3679 } else { 3680 /* Enable Store & Forward mode for Tx. */ 3681 CSR_WRITE_4(sc, 3682 MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 3683 TX_JUMBO_DIS | TX_STFW_ENA); 3684 } 3685 break; 3686 } 3687 } 3688 3689 static void 3690 msk_init(void *xsc) 3691 { 3692 struct msk_if_softc *sc_if = xsc; 3693 3694 MSK_IF_LOCK(sc_if); 3695 msk_init_locked(sc_if); 3696 MSK_IF_UNLOCK(sc_if); 3697 } 3698 3699 static void 3700 msk_init_locked(struct msk_if_softc *sc_if) 3701 { 3702 struct msk_softc *sc; 3703 struct ifnet *ifp; 3704 struct mii_data *mii; 3705 uint8_t *eaddr; 3706 uint16_t gmac; 3707 uint32_t reg; 3708 int error; 3709 3710 MSK_IF_LOCK_ASSERT(sc_if); 3711 3712 ifp = sc_if->msk_ifp; 3713 sc = sc_if->msk_softc; 3714 mii = device_get_softc(sc_if->msk_miibus); 3715 3716 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 3717 return; 3718 3719 error = 0; 3720 /* Cancel pending I/O and free all Rx/Tx buffers. */ 3721 msk_stop(sc_if); 3722 3723 if (ifp->if_mtu < ETHERMTU) 3724 sc_if->msk_framesize = ETHERMTU; 3725 else 3726 sc_if->msk_framesize = ifp->if_mtu; 3727 sc_if->msk_framesize += ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 3728 if (ifp->if_mtu > ETHERMTU && 3729 (sc_if->msk_flags & MSK_FLAG_JUMBO_NOCSUM) != 0) { 3730 ifp->if_hwassist &= ~(MSK_CSUM_FEATURES | CSUM_TSO); 3731 ifp->if_capenable &= ~(IFCAP_TSO4 | IFCAP_TXCSUM); 3732 } 3733 3734 /* GMAC Control reset. */ 3735 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_RST_SET); 3736 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_RST_CLR); 3737 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_F_LOOPB_OFF); 3738 if (sc->msk_hw_id == CHIP_ID_YUKON_EX) 3739 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), 3740 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON | 3741 GMC_BYP_RETR_ON); 3742 3743 /* 3744 * Initialize GMAC first such that speed/duplex/flow-control 3745 * parameters are renegotiated when interface is brought up. 3746 */ 3747 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, 0); 3748 3749 /* Dummy read the Interrupt Source Register. */ 3750 CSR_READ_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_SRC)); 3751 3752 /* Clear MIB stats. */ 3753 msk_stats_clear(sc_if); 3754 3755 /* Disable FCS. */ 3756 GMAC_WRITE_2(sc, sc_if->msk_port, GM_RX_CTRL, GM_RXCR_CRC_DIS); 3757 3758 /* Setup Transmit Control Register. */ 3759 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF)); 3760 3761 /* Setup Transmit Flow Control Register. */ 3762 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_FLOW_CTRL, 0xffff); 3763 3764 /* Setup Transmit Parameter Register. */ 3765 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_PARAM, 3766 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) | TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) | 3767 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) | TX_BACK_OFF_LIM(TX_BOF_LIM_DEF)); 3768 3769 gmac = DATA_BLIND_VAL(DATA_BLIND_DEF) | 3770 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF); 3771 3772 if (ifp->if_mtu > ETHERMTU) 3773 gmac |= GM_SMOD_JUMBO_ENA; 3774 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SERIAL_MODE, gmac); 3775 3776 /* Set station address. */ 3777 eaddr = IF_LLADDR(ifp); 3778 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_1L, 3779 eaddr[0] | (eaddr[1] << 8)); 3780 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_1M, 3781 eaddr[2] | (eaddr[3] << 8)); 3782 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_1H, 3783 eaddr[4] | (eaddr[5] << 8)); 3784 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_2L, 3785 eaddr[0] | (eaddr[1] << 8)); 3786 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_2M, 3787 eaddr[2] | (eaddr[3] << 8)); 3788 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_2H, 3789 eaddr[4] | (eaddr[5] << 8)); 3790 3791 /* Disable interrupts for counter overflows. */ 3792 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_IRQ_MSK, 0); 3793 GMAC_WRITE_2(sc, sc_if->msk_port, GM_RX_IRQ_MSK, 0); 3794 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TR_IRQ_MSK, 0); 3795 3796 /* Configure Rx MAC FIFO. */ 3797 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), GMF_RST_SET); 3798 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), GMF_RST_CLR); 3799 reg = GMF_OPER_ON | GMF_RX_F_FL_ON; 3800 if (sc->msk_hw_id == CHIP_ID_YUKON_FE_P || 3801 sc->msk_hw_id == CHIP_ID_YUKON_EX) 3802 reg |= GMF_RX_OVER_ON; 3803 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), reg); 3804 3805 /* Set receive filter. */ 3806 msk_rxfilter(sc_if); 3807 3808 if (sc->msk_hw_id == CHIP_ID_YUKON_XL) { 3809 /* Clear flush mask - HW bug. */ 3810 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_FL_MSK), 0); 3811 } else { 3812 /* Flush Rx MAC FIFO on any flow control or error. */ 3813 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_FL_MSK), 3814 GMR_FS_ANY_ERR); 3815 } 3816 3817 /* 3818 * Set Rx FIFO flush threshold to 64 bytes + 1 FIFO word 3819 * due to hardware hang on receipt of pause frames. 3820 */ 3821 reg = RX_GMF_FL_THR_DEF + 1; 3822 /* Another magic for Yukon FE+ - From Linux. */ 3823 if (sc->msk_hw_id == CHIP_ID_YUKON_FE_P && 3824 sc->msk_hw_rev == CHIP_REV_YU_FE_P_A0) 3825 reg = 0x178; 3826 CSR_WRITE_2(sc, MR_ADDR(sc_if->msk_port, RX_GMF_FL_THR), reg); 3827 3828 /* Configure Tx MAC FIFO. */ 3829 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_RST_SET); 3830 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_RST_CLR); 3831 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_OPER_ON); 3832 3833 /* Configure hardware VLAN tag insertion/stripping. */ 3834 msk_setvlan(sc_if, ifp); 3835 3836 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) == 0) { 3837 /* Set Rx Pause threshould. */ 3838 CSR_WRITE_2(sc, MR_ADDR(sc_if->msk_port, RX_GMF_LP_THR), 3839 MSK_ECU_LLPP); 3840 CSR_WRITE_2(sc, MR_ADDR(sc_if->msk_port, RX_GMF_UP_THR), 3841 MSK_ECU_ULPP); 3842 /* Configure store-and-forward for Tx. */ 3843 msk_set_tx_stfwd(sc_if); 3844 } 3845 3846 if (sc->msk_hw_id == CHIP_ID_YUKON_FE_P && 3847 sc->msk_hw_rev == CHIP_REV_YU_FE_P_A0) { 3848 /* Disable dynamic watermark - from Linux. */ 3849 reg = CSR_READ_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_EA)); 3850 reg &= ~0x03; 3851 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_EA), reg); 3852 } 3853 3854 /* 3855 * Disable Force Sync bit and Alloc bit in Tx RAM interface 3856 * arbiter as we don't use Sync Tx queue. 3857 */ 3858 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, TXA_CTRL), 3859 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC); 3860 /* Enable the RAM Interface Arbiter. */ 3861 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, TXA_CTRL), TXA_ENA_ARB); 3862 3863 /* Setup RAM buffer. */ 3864 msk_set_rambuffer(sc_if); 3865 3866 /* Disable Tx sync Queue. */ 3867 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txsq, RB_CTRL), RB_RST_SET); 3868 3869 /* Setup Tx Queue Bus Memory Interface. */ 3870 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_CLR_RESET); 3871 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_OPER_INIT); 3872 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_FIFO_OP_ON); 3873 CSR_WRITE_2(sc, Q_ADDR(sc_if->msk_txq, Q_WM), MSK_BMU_TX_WM); 3874 switch (sc->msk_hw_id) { 3875 case CHIP_ID_YUKON_EC_U: 3876 if (sc->msk_hw_rev == CHIP_REV_YU_EC_U_A0) { 3877 /* Fix for Yukon-EC Ultra: set BMU FIFO level */ 3878 CSR_WRITE_2(sc, Q_ADDR(sc_if->msk_txq, Q_AL), 3879 MSK_ECU_TXFF_LEV); 3880 } 3881 break; 3882 case CHIP_ID_YUKON_EX: 3883 /* 3884 * Yukon Extreme seems to have silicon bug for 3885 * automatic Tx checksum calculation capability. 3886 */ 3887 if (sc->msk_hw_rev == CHIP_REV_YU_EX_B0) 3888 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_F), 3889 F_TX_CHK_AUTO_OFF); 3890 break; 3891 } 3892 3893 /* Setup Rx Queue Bus Memory Interface. */ 3894 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_CLR_RESET); 3895 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_OPER_INIT); 3896 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_FIFO_OP_ON); 3897 CSR_WRITE_2(sc, Q_ADDR(sc_if->msk_rxq, Q_WM), MSK_BMU_RX_WM); 3898 if (sc->msk_hw_id == CHIP_ID_YUKON_EC_U && 3899 sc->msk_hw_rev >= CHIP_REV_YU_EC_U_A1) { 3900 /* MAC Rx RAM Read is controlled by hardware. */ 3901 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_F), F_M_RX_RAM_DIS); 3902 } 3903 3904 msk_set_prefetch(sc, sc_if->msk_txq, 3905 sc_if->msk_rdata.msk_tx_ring_paddr, MSK_TX_RING_CNT - 1); 3906 msk_init_tx_ring(sc_if); 3907 3908 /* Disable Rx checksum offload and RSS hash. */ 3909 reg = BMU_DIS_RX_RSS_HASH; 3910 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0 && 3911 (ifp->if_capenable & IFCAP_RXCSUM) != 0) 3912 reg |= BMU_ENA_RX_CHKSUM; 3913 else 3914 reg |= BMU_DIS_RX_CHKSUM; 3915 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), reg); 3916 if (sc_if->msk_framesize > (MCLBYTES - MSK_RX_BUF_ALIGN)) { 3917 msk_set_prefetch(sc, sc_if->msk_rxq, 3918 sc_if->msk_rdata.msk_jumbo_rx_ring_paddr, 3919 MSK_JUMBO_RX_RING_CNT - 1); 3920 error = msk_init_jumbo_rx_ring(sc_if); 3921 } else { 3922 msk_set_prefetch(sc, sc_if->msk_rxq, 3923 sc_if->msk_rdata.msk_rx_ring_paddr, 3924 MSK_RX_RING_CNT - 1); 3925 error = msk_init_rx_ring(sc_if); 3926 } 3927 if (error != 0) { 3928 device_printf(sc_if->msk_if_dev, 3929 "initialization failed: no memory for Rx buffers\n"); 3930 msk_stop(sc_if); 3931 return; 3932 } 3933 if (sc->msk_hw_id == CHIP_ID_YUKON_EX) { 3934 /* Disable flushing of non-ASF packets. */ 3935 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), 3936 GMF_RX_MACSEC_FLUSH_OFF); 3937 } 3938 3939 /* Configure interrupt handling. */ 3940 if (sc_if->msk_port == MSK_PORT_A) { 3941 sc->msk_intrmask |= Y2_IS_PORT_A; 3942 sc->msk_intrhwemask |= Y2_HWE_L1_MASK; 3943 } else { 3944 sc->msk_intrmask |= Y2_IS_PORT_B; 3945 sc->msk_intrhwemask |= Y2_HWE_L2_MASK; 3946 } 3947 /* Configure IRQ moderation mask. */ 3948 CSR_WRITE_4(sc, B2_IRQM_MSK, sc->msk_intrmask); 3949 if (sc->msk_int_holdoff > 0) { 3950 /* Configure initial IRQ moderation timer value. */ 3951 CSR_WRITE_4(sc, B2_IRQM_INI, 3952 MSK_USECS(sc, sc->msk_int_holdoff)); 3953 CSR_WRITE_4(sc, B2_IRQM_VAL, 3954 MSK_USECS(sc, sc->msk_int_holdoff)); 3955 /* Start IRQ moderation. */ 3956 CSR_WRITE_1(sc, B2_IRQM_CTRL, TIM_START); 3957 } 3958 CSR_WRITE_4(sc, B0_HWE_IMSK, sc->msk_intrhwemask); 3959 CSR_READ_4(sc, B0_HWE_IMSK); 3960 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask); 3961 CSR_READ_4(sc, B0_IMSK); 3962 3963 sc_if->msk_flags &= ~MSK_FLAG_LINK; 3964 mii_mediachg(mii); 3965 3966 ifp->if_drv_flags |= IFF_DRV_RUNNING; 3967 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3968 3969 callout_reset(&sc_if->msk_tick_ch, hz, msk_tick, sc_if); 3970 } 3971 3972 static void 3973 msk_set_rambuffer(struct msk_if_softc *sc_if) 3974 { 3975 struct msk_softc *sc; 3976 int ltpp, utpp; 3977 3978 sc = sc_if->msk_softc; 3979 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) == 0) 3980 return; 3981 3982 /* Setup Rx Queue. */ 3983 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_RST_CLR); 3984 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_START), 3985 sc->msk_rxqstart[sc_if->msk_port] / 8); 3986 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_END), 3987 sc->msk_rxqend[sc_if->msk_port] / 8); 3988 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_WP), 3989 sc->msk_rxqstart[sc_if->msk_port] / 8); 3990 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_RP), 3991 sc->msk_rxqstart[sc_if->msk_port] / 8); 3992 3993 utpp = (sc->msk_rxqend[sc_if->msk_port] + 1 - 3994 sc->msk_rxqstart[sc_if->msk_port] - MSK_RB_ULPP) / 8; 3995 ltpp = (sc->msk_rxqend[sc_if->msk_port] + 1 - 3996 sc->msk_rxqstart[sc_if->msk_port] - MSK_RB_LLPP_B) / 8; 3997 if (sc->msk_rxqsize < MSK_MIN_RXQ_SIZE) 3998 ltpp += (MSK_RB_LLPP_B - MSK_RB_LLPP_S) / 8; 3999 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_RX_UTPP), utpp); 4000 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_RX_LTPP), ltpp); 4001 /* Set Rx priority(RB_RX_UTHP/RB_RX_LTHP) thresholds? */ 4002 4003 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_ENA_OP_MD); 4004 CSR_READ_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL)); 4005 4006 /* Setup Tx Queue. */ 4007 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_RST_CLR); 4008 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_START), 4009 sc->msk_txqstart[sc_if->msk_port] / 8); 4010 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_END), 4011 sc->msk_txqend[sc_if->msk_port] / 8); 4012 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_WP), 4013 sc->msk_txqstart[sc_if->msk_port] / 8); 4014 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_RP), 4015 sc->msk_txqstart[sc_if->msk_port] / 8); 4016 /* Enable Store & Forward for Tx side. */ 4017 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_ENA_STFWD); 4018 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_ENA_OP_MD); 4019 CSR_READ_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL)); 4020 } 4021 4022 static void 4023 msk_set_prefetch(struct msk_softc *sc, int qaddr, bus_addr_t addr, 4024 uint32_t count) 4025 { 4026 4027 /* Reset the prefetch unit. */ 4028 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG), 4029 PREF_UNIT_RST_SET); 4030 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG), 4031 PREF_UNIT_RST_CLR); 4032 /* Set LE base address. */ 4033 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_ADDR_LOW_REG), 4034 MSK_ADDR_LO(addr)); 4035 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_ADDR_HI_REG), 4036 MSK_ADDR_HI(addr)); 4037 /* Set the list last index. */ 4038 CSR_WRITE_2(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_LAST_IDX_REG), 4039 count); 4040 /* Turn on prefetch unit. */ 4041 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG), 4042 PREF_UNIT_OP_ON); 4043 /* Dummy read to ensure write. */ 4044 CSR_READ_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG)); 4045 } 4046 4047 static void 4048 msk_stop(struct msk_if_softc *sc_if) 4049 { 4050 struct msk_softc *sc; 4051 struct msk_txdesc *txd; 4052 struct msk_rxdesc *rxd; 4053 struct msk_rxdesc *jrxd; 4054 struct ifnet *ifp; 4055 uint32_t val; 4056 int i; 4057 4058 MSK_IF_LOCK_ASSERT(sc_if); 4059 sc = sc_if->msk_softc; 4060 ifp = sc_if->msk_ifp; 4061 4062 callout_stop(&sc_if->msk_tick_ch); 4063 sc_if->msk_watchdog_timer = 0; 4064 4065 /* Disable interrupts. */ 4066 if (sc_if->msk_port == MSK_PORT_A) { 4067 sc->msk_intrmask &= ~Y2_IS_PORT_A; 4068 sc->msk_intrhwemask &= ~Y2_HWE_L1_MASK; 4069 } else { 4070 sc->msk_intrmask &= ~Y2_IS_PORT_B; 4071 sc->msk_intrhwemask &= ~Y2_HWE_L2_MASK; 4072 } 4073 CSR_WRITE_4(sc, B0_HWE_IMSK, sc->msk_intrhwemask); 4074 CSR_READ_4(sc, B0_HWE_IMSK); 4075 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask); 4076 CSR_READ_4(sc, B0_IMSK); 4077 4078 /* Disable Tx/Rx MAC. */ 4079 val = GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL); 4080 val &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA); 4081 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, val); 4082 /* Read again to ensure writing. */ 4083 GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL); 4084 /* Update stats and clear counters. */ 4085 msk_stats_update(sc_if); 4086 4087 /* Stop Tx BMU. */ 4088 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_STOP); 4089 val = CSR_READ_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR)); 4090 for (i = 0; i < MSK_TIMEOUT; i++) { 4091 if ((val & (BMU_STOP | BMU_IDLE)) == 0) { 4092 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), 4093 BMU_STOP); 4094 val = CSR_READ_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR)); 4095 } else 4096 break; 4097 DELAY(1); 4098 } 4099 if (i == MSK_TIMEOUT) 4100 device_printf(sc_if->msk_if_dev, "Tx BMU stop failed\n"); 4101 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), 4102 RB_RST_SET | RB_DIS_OP_MD); 4103 4104 /* Disable all GMAC interrupt. */ 4105 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_MSK), 0); 4106 /* Disable PHY interrupt. */ 4107 msk_phy_writereg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_MASK, 0); 4108 4109 /* Disable the RAM Interface Arbiter. */ 4110 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, TXA_CTRL), TXA_DIS_ARB); 4111 4112 /* Reset the PCI FIFO of the async Tx queue */ 4113 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), 4114 BMU_RST_SET | BMU_FIFO_RST); 4115 4116 /* Reset the Tx prefetch units. */ 4117 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(sc_if->msk_txq, PREF_UNIT_CTRL_REG), 4118 PREF_UNIT_RST_SET); 4119 4120 /* Reset the RAM Buffer async Tx queue. */ 4121 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_RST_SET); 4122 4123 /* Reset Tx MAC FIFO. */ 4124 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_RST_SET); 4125 /* Set Pause Off. */ 4126 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_PAUSE_OFF); 4127 4128 /* 4129 * The Rx Stop command will not work for Yukon-2 if the BMU does not 4130 * reach the end of packet and since we can't make sure that we have 4131 * incoming data, we must reset the BMU while it is not during a DMA 4132 * transfer. Since it is possible that the Rx path is still active, 4133 * the Rx RAM buffer will be stopped first, so any possible incoming 4134 * data will not trigger a DMA. After the RAM buffer is stopped, the 4135 * BMU is polled until any DMA in progress is ended and only then it 4136 * will be reset. 4137 */ 4138 4139 /* Disable the RAM Buffer receive queue. */ 4140 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_DIS_OP_MD); 4141 for (i = 0; i < MSK_TIMEOUT; i++) { 4142 if (CSR_READ_1(sc, RB_ADDR(sc_if->msk_rxq, Q_RSL)) == 4143 CSR_READ_1(sc, RB_ADDR(sc_if->msk_rxq, Q_RL))) 4144 break; 4145 DELAY(1); 4146 } 4147 if (i == MSK_TIMEOUT) 4148 device_printf(sc_if->msk_if_dev, "Rx BMU stop failed\n"); 4149 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), 4150 BMU_RST_SET | BMU_FIFO_RST); 4151 /* Reset the Rx prefetch unit. */ 4152 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_CTRL_REG), 4153 PREF_UNIT_RST_SET); 4154 /* Reset the RAM Buffer receive queue. */ 4155 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_RST_SET); 4156 /* Reset Rx MAC FIFO. */ 4157 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), GMF_RST_SET); 4158 4159 /* Free Rx and Tx mbufs still in the queues. */ 4160 for (i = 0; i < MSK_RX_RING_CNT; i++) { 4161 rxd = &sc_if->msk_cdata.msk_rxdesc[i]; 4162 if (rxd->rx_m != NULL) { 4163 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_tag, 4164 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 4165 bus_dmamap_unload(sc_if->msk_cdata.msk_rx_tag, 4166 rxd->rx_dmamap); 4167 m_freem(rxd->rx_m); 4168 rxd->rx_m = NULL; 4169 } 4170 } 4171 for (i = 0; i < MSK_JUMBO_RX_RING_CNT; i++) { 4172 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[i]; 4173 if (jrxd->rx_m != NULL) { 4174 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_tag, 4175 jrxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 4176 bus_dmamap_unload(sc_if->msk_cdata.msk_jumbo_rx_tag, 4177 jrxd->rx_dmamap); 4178 m_freem(jrxd->rx_m); 4179 jrxd->rx_m = NULL; 4180 } 4181 } 4182 for (i = 0; i < MSK_TX_RING_CNT; i++) { 4183 txd = &sc_if->msk_cdata.msk_txdesc[i]; 4184 if (txd->tx_m != NULL) { 4185 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_tag, 4186 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 4187 bus_dmamap_unload(sc_if->msk_cdata.msk_tx_tag, 4188 txd->tx_dmamap); 4189 m_freem(txd->tx_m); 4190 txd->tx_m = NULL; 4191 } 4192 } 4193 4194 /* 4195 * Mark the interface down. 4196 */ 4197 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 4198 sc_if->msk_flags &= ~MSK_FLAG_LINK; 4199 } 4200 4201 /* 4202 * When GM_PAR_MIB_CLR bit of GM_PHY_ADDR is set, reading lower 4203 * counter clears high 16 bits of the counter such that accessing 4204 * lower 16 bits should be the last operation. 4205 */ 4206 #define MSK_READ_MIB32(x, y) \ 4207 (((uint32_t)GMAC_READ_2(sc, x, (y) + 4)) << 16) + \ 4208 (uint32_t)GMAC_READ_2(sc, x, y) 4209 #define MSK_READ_MIB64(x, y) \ 4210 (((uint64_t)MSK_READ_MIB32(x, (y) + 8)) << 32) + \ 4211 (uint64_t)MSK_READ_MIB32(x, y) 4212 4213 static void 4214 msk_stats_clear(struct msk_if_softc *sc_if) 4215 { 4216 struct msk_softc *sc; 4217 uint32_t reg; 4218 uint16_t gmac; 4219 int i; 4220 4221 MSK_IF_LOCK_ASSERT(sc_if); 4222 4223 sc = sc_if->msk_softc; 4224 /* Set MIB Clear Counter Mode. */ 4225 gmac = GMAC_READ_2(sc, sc_if->msk_port, GM_PHY_ADDR); 4226 GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac | GM_PAR_MIB_CLR); 4227 /* Read all MIB Counters with Clear Mode set. */ 4228 for (i = GM_RXF_UC_OK; i <= GM_TXE_FIFO_UR; i += sizeof(uint32_t)) 4229 reg = MSK_READ_MIB32(sc_if->msk_port, i); 4230 /* Clear MIB Clear Counter Mode. */ 4231 gmac &= ~GM_PAR_MIB_CLR; 4232 GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac); 4233 } 4234 4235 static void 4236 msk_stats_update(struct msk_if_softc *sc_if) 4237 { 4238 struct msk_softc *sc; 4239 struct ifnet *ifp; 4240 struct msk_hw_stats *stats; 4241 uint16_t gmac; 4242 uint32_t reg; 4243 4244 MSK_IF_LOCK_ASSERT(sc_if); 4245 4246 ifp = sc_if->msk_ifp; 4247 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 4248 return; 4249 sc = sc_if->msk_softc; 4250 stats = &sc_if->msk_stats; 4251 /* Set MIB Clear Counter Mode. */ 4252 gmac = GMAC_READ_2(sc, sc_if->msk_port, GM_PHY_ADDR); 4253 GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac | GM_PAR_MIB_CLR); 4254 4255 /* Rx stats. */ 4256 stats->rx_ucast_frames += 4257 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_UC_OK); 4258 stats->rx_bcast_frames += 4259 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_BC_OK); 4260 stats->rx_pause_frames += 4261 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_MPAUSE); 4262 stats->rx_mcast_frames += 4263 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_MC_OK); 4264 stats->rx_crc_errs += 4265 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_FCS_ERR); 4266 reg = MSK_READ_MIB32(sc_if->msk_port, GM_RXF_SPARE1); 4267 stats->rx_good_octets += 4268 MSK_READ_MIB64(sc_if->msk_port, GM_RXO_OK_LO); 4269 stats->rx_bad_octets += 4270 MSK_READ_MIB64(sc_if->msk_port, GM_RXO_ERR_LO); 4271 stats->rx_runts += 4272 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_SHT); 4273 stats->rx_runt_errs += 4274 MSK_READ_MIB32(sc_if->msk_port, GM_RXE_FRAG); 4275 stats->rx_pkts_64 += 4276 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_64B); 4277 stats->rx_pkts_65_127 += 4278 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_127B); 4279 stats->rx_pkts_128_255 += 4280 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_255B); 4281 stats->rx_pkts_256_511 += 4282 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_511B); 4283 stats->rx_pkts_512_1023 += 4284 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_1023B); 4285 stats->rx_pkts_1024_1518 += 4286 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_1518B); 4287 stats->rx_pkts_1519_max += 4288 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_MAX_SZ); 4289 stats->rx_pkts_too_long += 4290 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_LNG_ERR); 4291 stats->rx_pkts_jabbers += 4292 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_JAB_PKT); 4293 reg = MSK_READ_MIB32(sc_if->msk_port, GM_RXF_SPARE2); 4294 stats->rx_fifo_oflows += 4295 MSK_READ_MIB32(sc_if->msk_port, GM_RXE_FIFO_OV); 4296 reg = MSK_READ_MIB32(sc_if->msk_port, GM_RXF_SPARE3); 4297 4298 /* Tx stats. */ 4299 stats->tx_ucast_frames += 4300 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_UC_OK); 4301 stats->tx_bcast_frames += 4302 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_BC_OK); 4303 stats->tx_pause_frames += 4304 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_MPAUSE); 4305 stats->tx_mcast_frames += 4306 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_MC_OK); 4307 stats->tx_octets += 4308 MSK_READ_MIB64(sc_if->msk_port, GM_TXO_OK_LO); 4309 stats->tx_pkts_64 += 4310 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_64B); 4311 stats->tx_pkts_65_127 += 4312 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_127B); 4313 stats->tx_pkts_128_255 += 4314 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_255B); 4315 stats->tx_pkts_256_511 += 4316 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_511B); 4317 stats->tx_pkts_512_1023 += 4318 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_1023B); 4319 stats->tx_pkts_1024_1518 += 4320 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_1518B); 4321 stats->tx_pkts_1519_max += 4322 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_MAX_SZ); 4323 reg = MSK_READ_MIB32(sc_if->msk_port, GM_TXF_SPARE1); 4324 stats->tx_colls += 4325 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_COL); 4326 stats->tx_late_colls += 4327 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_LAT_COL); 4328 stats->tx_excess_colls += 4329 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_ABO_COL); 4330 stats->tx_multi_colls += 4331 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_MUL_COL); 4332 stats->tx_single_colls += 4333 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_SNG_COL); 4334 stats->tx_underflows += 4335 MSK_READ_MIB32(sc_if->msk_port, GM_TXE_FIFO_UR); 4336 /* Clear MIB Clear Counter Mode. */ 4337 gmac &= ~GM_PAR_MIB_CLR; 4338 GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac); 4339 } 4340 4341 static int 4342 msk_sysctl_stat32(SYSCTL_HANDLER_ARGS) 4343 { 4344 struct msk_softc *sc; 4345 struct msk_if_softc *sc_if; 4346 uint32_t result, *stat; 4347 int off; 4348 4349 sc_if = (struct msk_if_softc *)arg1; 4350 sc = sc_if->msk_softc; 4351 off = arg2; 4352 stat = (uint32_t *)((uint8_t *)&sc_if->msk_stats + off); 4353 4354 MSK_IF_LOCK(sc_if); 4355 result = MSK_READ_MIB32(sc_if->msk_port, GM_MIB_CNT_BASE + off * 2); 4356 result += *stat; 4357 MSK_IF_UNLOCK(sc_if); 4358 4359 return (sysctl_handle_int(oidp, &result, 0, req)); 4360 } 4361 4362 static int 4363 msk_sysctl_stat64(SYSCTL_HANDLER_ARGS) 4364 { 4365 struct msk_softc *sc; 4366 struct msk_if_softc *sc_if; 4367 uint64_t result, *stat; 4368 int off; 4369 4370 sc_if = (struct msk_if_softc *)arg1; 4371 sc = sc_if->msk_softc; 4372 off = arg2; 4373 stat = (uint64_t *)((uint8_t *)&sc_if->msk_stats + off); 4374 4375 MSK_IF_LOCK(sc_if); 4376 result = MSK_READ_MIB64(sc_if->msk_port, GM_MIB_CNT_BASE + off * 2); 4377 result += *stat; 4378 MSK_IF_UNLOCK(sc_if); 4379 4380 return (sysctl_handle_quad(oidp, &result, 0, req)); 4381 } 4382 4383 #undef MSK_READ_MIB32 4384 #undef MSK_READ_MIB64 4385 4386 #define MSK_SYSCTL_STAT32(sc, c, o, p, n, d) \ 4387 SYSCTL_ADD_PROC(c, p, OID_AUTO, o, CTLTYPE_UINT | CTLFLAG_RD, \ 4388 sc, offsetof(struct msk_hw_stats, n), msk_sysctl_stat32, \ 4389 "IU", d) 4390 #define MSK_SYSCTL_STAT64(sc, c, o, p, n, d) \ 4391 SYSCTL_ADD_PROC(c, p, OID_AUTO, o, CTLTYPE_UINT | CTLFLAG_RD, \ 4392 sc, offsetof(struct msk_hw_stats, n), msk_sysctl_stat64, \ 4393 "Q", d) 4394 4395 static void 4396 msk_sysctl_node(struct msk_if_softc *sc_if) 4397 { 4398 struct sysctl_ctx_list *ctx; 4399 struct sysctl_oid_list *child, *schild; 4400 struct sysctl_oid *tree; 4401 4402 ctx = device_get_sysctl_ctx(sc_if->msk_if_dev); 4403 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc_if->msk_if_dev)); 4404 4405 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD, 4406 NULL, "MSK Statistics"); 4407 schild = child = SYSCTL_CHILDREN(tree); 4408 tree = SYSCTL_ADD_NODE(ctx, schild, OID_AUTO, "rx", CTLFLAG_RD, 4409 NULL, "MSK RX Statistics"); 4410 child = SYSCTL_CHILDREN(tree); 4411 MSK_SYSCTL_STAT32(sc_if, ctx, "ucast_frames", 4412 child, rx_ucast_frames, "Good unicast frames"); 4413 MSK_SYSCTL_STAT32(sc_if, ctx, "bcast_frames", 4414 child, rx_bcast_frames, "Good broadcast frames"); 4415 MSK_SYSCTL_STAT32(sc_if, ctx, "pause_frames", 4416 child, rx_pause_frames, "Pause frames"); 4417 MSK_SYSCTL_STAT32(sc_if, ctx, "mcast_frames", 4418 child, rx_mcast_frames, "Multicast frames"); 4419 MSK_SYSCTL_STAT32(sc_if, ctx, "crc_errs", 4420 child, rx_crc_errs, "CRC errors"); 4421 MSK_SYSCTL_STAT64(sc_if, ctx, "good_octets", 4422 child, rx_good_octets, "Good octets"); 4423 MSK_SYSCTL_STAT64(sc_if, ctx, "bad_octets", 4424 child, rx_bad_octets, "Bad octets"); 4425 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_64", 4426 child, rx_pkts_64, "64 bytes frames"); 4427 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_65_127", 4428 child, rx_pkts_65_127, "65 to 127 bytes frames"); 4429 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_128_255", 4430 child, rx_pkts_128_255, "128 to 255 bytes frames"); 4431 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_256_511", 4432 child, rx_pkts_256_511, "256 to 511 bytes frames"); 4433 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_512_1023", 4434 child, rx_pkts_512_1023, "512 to 1023 bytes frames"); 4435 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_1024_1518", 4436 child, rx_pkts_1024_1518, "1024 to 1518 bytes frames"); 4437 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_1519_max", 4438 child, rx_pkts_1519_max, "1519 to max frames"); 4439 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_too_long", 4440 child, rx_pkts_too_long, "frames too long"); 4441 MSK_SYSCTL_STAT32(sc_if, ctx, "jabbers", 4442 child, rx_pkts_jabbers, "Jabber errors"); 4443 MSK_SYSCTL_STAT32(sc_if, ctx, "overflows", 4444 child, rx_fifo_oflows, "FIFO overflows"); 4445 4446 tree = SYSCTL_ADD_NODE(ctx, schild, OID_AUTO, "tx", CTLFLAG_RD, 4447 NULL, "MSK TX Statistics"); 4448 child = SYSCTL_CHILDREN(tree); 4449 MSK_SYSCTL_STAT32(sc_if, ctx, "ucast_frames", 4450 child, tx_ucast_frames, "Unicast frames"); 4451 MSK_SYSCTL_STAT32(sc_if, ctx, "bcast_frames", 4452 child, tx_bcast_frames, "Broadcast frames"); 4453 MSK_SYSCTL_STAT32(sc_if, ctx, "pause_frames", 4454 child, tx_pause_frames, "Pause frames"); 4455 MSK_SYSCTL_STAT32(sc_if, ctx, "mcast_frames", 4456 child, tx_mcast_frames, "Multicast frames"); 4457 MSK_SYSCTL_STAT64(sc_if, ctx, "octets", 4458 child, tx_octets, "Octets"); 4459 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_64", 4460 child, tx_pkts_64, "64 bytes frames"); 4461 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_65_127", 4462 child, tx_pkts_65_127, "65 to 127 bytes frames"); 4463 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_128_255", 4464 child, tx_pkts_128_255, "128 to 255 bytes frames"); 4465 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_256_511", 4466 child, tx_pkts_256_511, "256 to 511 bytes frames"); 4467 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_512_1023", 4468 child, tx_pkts_512_1023, "512 to 1023 bytes frames"); 4469 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_1024_1518", 4470 child, tx_pkts_1024_1518, "1024 to 1518 bytes frames"); 4471 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_1519_max", 4472 child, tx_pkts_1519_max, "1519 to max frames"); 4473 MSK_SYSCTL_STAT32(sc_if, ctx, "colls", 4474 child, tx_colls, "Collisions"); 4475 MSK_SYSCTL_STAT32(sc_if, ctx, "late_colls", 4476 child, tx_late_colls, "Late collisions"); 4477 MSK_SYSCTL_STAT32(sc_if, ctx, "excess_colls", 4478 child, tx_excess_colls, "Excessive collisions"); 4479 MSK_SYSCTL_STAT32(sc_if, ctx, "multi_colls", 4480 child, tx_multi_colls, "Multiple collisions"); 4481 MSK_SYSCTL_STAT32(sc_if, ctx, "single_colls", 4482 child, tx_single_colls, "Single collisions"); 4483 MSK_SYSCTL_STAT32(sc_if, ctx, "underflows", 4484 child, tx_underflows, "FIFO underflows"); 4485 } 4486 4487 #undef MSK_SYSCTL_STAT32 4488 #undef MSK_SYSCTL_STAT64 4489 4490 static int 4491 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 4492 { 4493 int error, value; 4494 4495 if (!arg1) 4496 return (EINVAL); 4497 value = *(int *)arg1; 4498 error = sysctl_handle_int(oidp, &value, 0, req); 4499 if (error || !req->newptr) 4500 return (error); 4501 if (value < low || value > high) 4502 return (EINVAL); 4503 *(int *)arg1 = value; 4504 4505 return (0); 4506 } 4507 4508 static int 4509 sysctl_hw_msk_proc_limit(SYSCTL_HANDLER_ARGS) 4510 { 4511 4512 return (sysctl_int_range(oidp, arg1, arg2, req, MSK_PROC_MIN, 4513 MSK_PROC_MAX)); 4514 } 4515