1 /****************************************************************************** 2 * 3 * Name : sky2.c 4 * Project: Gigabit Ethernet Driver for FreeBSD 5.x/6.x 5 * Version: $Revision: 1.23 $ 6 * Date : $Date: 2005/12/22 09:04:11 $ 7 * Purpose: Main driver source file 8 * 9 *****************************************************************************/ 10 11 /****************************************************************************** 12 * 13 * LICENSE: 14 * Copyright (C) Marvell International Ltd. and/or its affiliates 15 * 16 * The computer program files contained in this folder ("Files") 17 * are provided to you under the BSD-type license terms provided 18 * below, and any use of such Files and any derivative works 19 * thereof created by you shall be governed by the following terms 20 * and conditions: 21 * 22 * - Redistributions of source code must retain the above copyright 23 * notice, this list of conditions and the following disclaimer. 24 * - Redistributions in binary form must reproduce the above 25 * copyright notice, this list of conditions and the following 26 * disclaimer in the documentation and/or other materials provided 27 * with the distribution. 28 * - Neither the name of Marvell nor the names of its contributors 29 * may be used to endorse or promote products derived from this 30 * software without specific prior written permission. 31 * 32 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 33 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 34 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 35 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 36 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 37 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 38 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 39 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 40 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 41 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 42 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED 43 * OF THE POSSIBILITY OF SUCH DAMAGE. 44 * /LICENSE 45 * 46 *****************************************************************************/ 47 48 /*- 49 * Copyright (c) 1997, 1998, 1999, 2000 50 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 51 * 52 * Redistribution and use in source and binary forms, with or without 53 * modification, are permitted provided that the following conditions 54 * are met: 55 * 1. Redistributions of source code must retain the above copyright 56 * notice, this list of conditions and the following disclaimer. 57 * 2. Redistributions in binary form must reproduce the above copyright 58 * notice, this list of conditions and the following disclaimer in the 59 * documentation and/or other materials provided with the distribution. 60 * 3. All advertising materials mentioning features or use of this software 61 * must display the following acknowledgement: 62 * This product includes software developed by Bill Paul. 63 * 4. Neither the name of the author nor the names of any co-contributors 64 * may be used to endorse or promote products derived from this software 65 * without specific prior written permission. 66 * 67 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 68 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 69 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 70 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 71 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 72 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 73 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 74 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 75 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 76 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 77 * THE POSSIBILITY OF SUCH DAMAGE. 78 */ 79 /*- 80 * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu> 81 * 82 * Permission to use, copy, modify, and distribute this software for any 83 * purpose with or without fee is hereby granted, provided that the above 84 * copyright notice and this permission notice appear in all copies. 85 * 86 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 87 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 88 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 89 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 90 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 91 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 92 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 93 */ 94 95 /* 96 * Device driver for the Marvell Yukon II Ethernet controller. 97 * Due to lack of documentation, this driver is based on the code from 98 * sk(4) and Marvell's myk(4) driver for FreeBSD 5.x. 99 */ 100 101 #include <sys/cdefs.h> 102 __FBSDID("$FreeBSD$"); 103 104 #include <sys/param.h> 105 #include <sys/systm.h> 106 #include <sys/bus.h> 107 #include <sys/endian.h> 108 #include <sys/mbuf.h> 109 #include <sys/malloc.h> 110 #include <sys/kernel.h> 111 #include <sys/module.h> 112 #include <sys/socket.h> 113 #include <sys/sockio.h> 114 #include <sys/queue.h> 115 #include <sys/sysctl.h> 116 117 #include <net/bpf.h> 118 #include <net/ethernet.h> 119 #include <net/if.h> 120 #include <net/if_arp.h> 121 #include <net/if_dl.h> 122 #include <net/if_media.h> 123 #include <net/if_types.h> 124 #include <net/if_vlan_var.h> 125 126 #include <netinet/in.h> 127 #include <netinet/in_systm.h> 128 #include <netinet/ip.h> 129 #include <netinet/tcp.h> 130 #include <netinet/udp.h> 131 132 #include <machine/bus.h> 133 #include <machine/in_cksum.h> 134 #include <machine/resource.h> 135 #include <sys/rman.h> 136 137 #include <dev/mii/mii.h> 138 #include <dev/mii/miivar.h> 139 140 #include <dev/pci/pcireg.h> 141 #include <dev/pci/pcivar.h> 142 143 #include <dev/msk/if_mskreg.h> 144 145 MODULE_DEPEND(msk, pci, 1, 1, 1); 146 MODULE_DEPEND(msk, ether, 1, 1, 1); 147 MODULE_DEPEND(msk, miibus, 1, 1, 1); 148 149 /* "device miibus" required. See GENERIC if you get errors here. */ 150 #include "miibus_if.h" 151 152 /* Tunables. */ 153 static int msi_disable = 0; 154 TUNABLE_INT("hw.msk.msi_disable", &msi_disable); 155 static int legacy_intr = 0; 156 TUNABLE_INT("hw.msk.legacy_intr", &legacy_intr); 157 static int jumbo_disable = 0; 158 TUNABLE_INT("hw.msk.jumbo_disable", &jumbo_disable); 159 160 #define MSK_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 161 162 /* 163 * Devices supported by this driver. 164 */ 165 static struct msk_product { 166 uint16_t msk_vendorid; 167 uint16_t msk_deviceid; 168 const char *msk_name; 169 } msk_products[] = { 170 { VENDORID_SK, DEVICEID_SK_YUKON2, 171 "SK-9Sxx Gigabit Ethernet" }, 172 { VENDORID_SK, DEVICEID_SK_YUKON2_EXPR, 173 "SK-9Exx Gigabit Ethernet"}, 174 { VENDORID_MARVELL, DEVICEID_MRVL_8021CU, 175 "Marvell Yukon 88E8021CU Gigabit Ethernet" }, 176 { VENDORID_MARVELL, DEVICEID_MRVL_8021X, 177 "Marvell Yukon 88E8021 SX/LX Gigabit Ethernet" }, 178 { VENDORID_MARVELL, DEVICEID_MRVL_8022CU, 179 "Marvell Yukon 88E8022CU Gigabit Ethernet" }, 180 { VENDORID_MARVELL, DEVICEID_MRVL_8022X, 181 "Marvell Yukon 88E8022 SX/LX Gigabit Ethernet" }, 182 { VENDORID_MARVELL, DEVICEID_MRVL_8061CU, 183 "Marvell Yukon 88E8061CU Gigabit Ethernet" }, 184 { VENDORID_MARVELL, DEVICEID_MRVL_8061X, 185 "Marvell Yukon 88E8061 SX/LX Gigabit Ethernet" }, 186 { VENDORID_MARVELL, DEVICEID_MRVL_8062CU, 187 "Marvell Yukon 88E8062CU Gigabit Ethernet" }, 188 { VENDORID_MARVELL, DEVICEID_MRVL_8062X, 189 "Marvell Yukon 88E8062 SX/LX Gigabit Ethernet" }, 190 { VENDORID_MARVELL, DEVICEID_MRVL_8035, 191 "Marvell Yukon 88E8035 Fast Ethernet" }, 192 { VENDORID_MARVELL, DEVICEID_MRVL_8036, 193 "Marvell Yukon 88E8036 Fast Ethernet" }, 194 { VENDORID_MARVELL, DEVICEID_MRVL_8038, 195 "Marvell Yukon 88E8038 Fast Ethernet" }, 196 { VENDORID_MARVELL, DEVICEID_MRVL_8039, 197 "Marvell Yukon 88E8039 Fast Ethernet" }, 198 { VENDORID_MARVELL, DEVICEID_MRVL_8040, 199 "Marvell Yukon 88E8040 Fast Ethernet" }, 200 { VENDORID_MARVELL, DEVICEID_MRVL_8040T, 201 "Marvell Yukon 88E8040T Fast Ethernet" }, 202 { VENDORID_MARVELL, DEVICEID_MRVL_8042, 203 "Marvell Yukon 88E8042 Fast Ethernet" }, 204 { VENDORID_MARVELL, DEVICEID_MRVL_8048, 205 "Marvell Yukon 88E8048 Fast Ethernet" }, 206 { VENDORID_MARVELL, DEVICEID_MRVL_4361, 207 "Marvell Yukon 88E8050 Gigabit Ethernet" }, 208 { VENDORID_MARVELL, DEVICEID_MRVL_4360, 209 "Marvell Yukon 88E8052 Gigabit Ethernet" }, 210 { VENDORID_MARVELL, DEVICEID_MRVL_4362, 211 "Marvell Yukon 88E8053 Gigabit Ethernet" }, 212 { VENDORID_MARVELL, DEVICEID_MRVL_4363, 213 "Marvell Yukon 88E8055 Gigabit Ethernet" }, 214 { VENDORID_MARVELL, DEVICEID_MRVL_4364, 215 "Marvell Yukon 88E8056 Gigabit Ethernet" }, 216 { VENDORID_MARVELL, DEVICEID_MRVL_4365, 217 "Marvell Yukon 88E8070 Gigabit Ethernet" }, 218 { VENDORID_MARVELL, DEVICEID_MRVL_436A, 219 "Marvell Yukon 88E8058 Gigabit Ethernet" }, 220 { VENDORID_MARVELL, DEVICEID_MRVL_436B, 221 "Marvell Yukon 88E8071 Gigabit Ethernet" }, 222 { VENDORID_MARVELL, DEVICEID_MRVL_436C, 223 "Marvell Yukon 88E8072 Gigabit Ethernet" }, 224 { VENDORID_MARVELL, DEVICEID_MRVL_4380, 225 "Marvell Yukon 88E8057 Gigabit Ethernet" }, 226 { VENDORID_MARVELL, DEVICEID_MRVL_4381, 227 "Marvell Yukon 88E8059 Gigabit Ethernet" }, 228 { VENDORID_DLINK, DEVICEID_DLINK_DGE550SX, 229 "D-Link 550SX Gigabit Ethernet" }, 230 { VENDORID_DLINK, DEVICEID_DLINK_DGE560SX, 231 "D-Link 560SX Gigabit Ethernet" }, 232 { VENDORID_DLINK, DEVICEID_DLINK_DGE560T, 233 "D-Link 560T Gigabit Ethernet" } 234 }; 235 236 static const char *model_name[] = { 237 "Yukon XL", 238 "Yukon EC Ultra", 239 "Yukon EX", 240 "Yukon EC", 241 "Yukon FE", 242 "Yukon FE+", 243 "Yukon Supreme", 244 "Yukon Ultra 2", 245 "Yukon Unknown", 246 "Yukon Optima", 247 }; 248 249 static int mskc_probe(device_t); 250 static int mskc_attach(device_t); 251 static int mskc_detach(device_t); 252 static int mskc_shutdown(device_t); 253 static int mskc_setup_rambuffer(struct msk_softc *); 254 static int mskc_suspend(device_t); 255 static int mskc_resume(device_t); 256 static void mskc_reset(struct msk_softc *); 257 258 static int msk_probe(device_t); 259 static int msk_attach(device_t); 260 static int msk_detach(device_t); 261 262 static void msk_tick(void *); 263 static void msk_intr(void *); 264 static void msk_intr_phy(struct msk_if_softc *); 265 static void msk_intr_gmac(struct msk_if_softc *); 266 static __inline void msk_rxput(struct msk_if_softc *); 267 static int msk_handle_events(struct msk_softc *); 268 static void msk_handle_hwerr(struct msk_if_softc *, uint32_t); 269 static void msk_intr_hwerr(struct msk_softc *); 270 #ifndef __NO_STRICT_ALIGNMENT 271 static __inline void msk_fixup_rx(struct mbuf *); 272 #endif 273 static __inline void msk_rxcsum(struct msk_if_softc *, uint32_t, struct mbuf *); 274 static void msk_rxeof(struct msk_if_softc *, uint32_t, uint32_t, int); 275 static void msk_jumbo_rxeof(struct msk_if_softc *, uint32_t, uint32_t, int); 276 static void msk_txeof(struct msk_if_softc *, int); 277 static int msk_encap(struct msk_if_softc *, struct mbuf **); 278 static void msk_start(struct ifnet *); 279 static void msk_start_locked(struct ifnet *); 280 static int msk_ioctl(struct ifnet *, u_long, caddr_t); 281 static void msk_set_prefetch(struct msk_softc *, int, bus_addr_t, uint32_t); 282 static void msk_set_rambuffer(struct msk_if_softc *); 283 static void msk_set_tx_stfwd(struct msk_if_softc *); 284 static void msk_init(void *); 285 static void msk_init_locked(struct msk_if_softc *); 286 static void msk_stop(struct msk_if_softc *); 287 static void msk_watchdog(struct msk_if_softc *); 288 static int msk_mediachange(struct ifnet *); 289 static void msk_mediastatus(struct ifnet *, struct ifmediareq *); 290 static void msk_phy_power(struct msk_softc *, int); 291 static void msk_dmamap_cb(void *, bus_dma_segment_t *, int, int); 292 static int msk_status_dma_alloc(struct msk_softc *); 293 static void msk_status_dma_free(struct msk_softc *); 294 static int msk_txrx_dma_alloc(struct msk_if_softc *); 295 static int msk_rx_dma_jalloc(struct msk_if_softc *); 296 static void msk_txrx_dma_free(struct msk_if_softc *); 297 static void msk_rx_dma_jfree(struct msk_if_softc *); 298 static int msk_rx_fill(struct msk_if_softc *, int); 299 static int msk_init_rx_ring(struct msk_if_softc *); 300 static int msk_init_jumbo_rx_ring(struct msk_if_softc *); 301 static void msk_init_tx_ring(struct msk_if_softc *); 302 static __inline void msk_discard_rxbuf(struct msk_if_softc *, int); 303 static __inline void msk_discard_jumbo_rxbuf(struct msk_if_softc *, int); 304 static int msk_newbuf(struct msk_if_softc *, int); 305 static int msk_jumbo_newbuf(struct msk_if_softc *, int); 306 307 static int msk_phy_readreg(struct msk_if_softc *, int, int); 308 static int msk_phy_writereg(struct msk_if_softc *, int, int, int); 309 static int msk_miibus_readreg(device_t, int, int); 310 static int msk_miibus_writereg(device_t, int, int, int); 311 static void msk_miibus_statchg(device_t); 312 313 static void msk_rxfilter(struct msk_if_softc *); 314 static void msk_setvlan(struct msk_if_softc *, struct ifnet *); 315 316 static void msk_stats_clear(struct msk_if_softc *); 317 static void msk_stats_update(struct msk_if_softc *); 318 static int msk_sysctl_stat32(SYSCTL_HANDLER_ARGS); 319 static int msk_sysctl_stat64(SYSCTL_HANDLER_ARGS); 320 static void msk_sysctl_node(struct msk_if_softc *); 321 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int); 322 static int sysctl_hw_msk_proc_limit(SYSCTL_HANDLER_ARGS); 323 324 static device_method_t mskc_methods[] = { 325 /* Device interface */ 326 DEVMETHOD(device_probe, mskc_probe), 327 DEVMETHOD(device_attach, mskc_attach), 328 DEVMETHOD(device_detach, mskc_detach), 329 DEVMETHOD(device_suspend, mskc_suspend), 330 DEVMETHOD(device_resume, mskc_resume), 331 DEVMETHOD(device_shutdown, mskc_shutdown), 332 333 /* bus interface */ 334 DEVMETHOD(bus_print_child, bus_generic_print_child), 335 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 336 337 { NULL, NULL } 338 }; 339 340 static driver_t mskc_driver = { 341 "mskc", 342 mskc_methods, 343 sizeof(struct msk_softc) 344 }; 345 346 static devclass_t mskc_devclass; 347 348 static device_method_t msk_methods[] = { 349 /* Device interface */ 350 DEVMETHOD(device_probe, msk_probe), 351 DEVMETHOD(device_attach, msk_attach), 352 DEVMETHOD(device_detach, msk_detach), 353 DEVMETHOD(device_shutdown, bus_generic_shutdown), 354 355 /* bus interface */ 356 DEVMETHOD(bus_print_child, bus_generic_print_child), 357 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 358 359 /* MII interface */ 360 DEVMETHOD(miibus_readreg, msk_miibus_readreg), 361 DEVMETHOD(miibus_writereg, msk_miibus_writereg), 362 DEVMETHOD(miibus_statchg, msk_miibus_statchg), 363 364 { NULL, NULL } 365 }; 366 367 static driver_t msk_driver = { 368 "msk", 369 msk_methods, 370 sizeof(struct msk_if_softc) 371 }; 372 373 static devclass_t msk_devclass; 374 375 DRIVER_MODULE(mskc, pci, mskc_driver, mskc_devclass, 0, 0); 376 DRIVER_MODULE(msk, mskc, msk_driver, msk_devclass, 0, 0); 377 DRIVER_MODULE(miibus, msk, miibus_driver, miibus_devclass, 0, 0); 378 379 static struct resource_spec msk_res_spec_io[] = { 380 { SYS_RES_IOPORT, PCIR_BAR(1), RF_ACTIVE }, 381 { -1, 0, 0 } 382 }; 383 384 static struct resource_spec msk_res_spec_mem[] = { 385 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 386 { -1, 0, 0 } 387 }; 388 389 static struct resource_spec msk_irq_spec_legacy[] = { 390 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 391 { -1, 0, 0 } 392 }; 393 394 static struct resource_spec msk_irq_spec_msi[] = { 395 { SYS_RES_IRQ, 1, RF_ACTIVE }, 396 { -1, 0, 0 } 397 }; 398 399 static int 400 msk_miibus_readreg(device_t dev, int phy, int reg) 401 { 402 struct msk_if_softc *sc_if; 403 404 sc_if = device_get_softc(dev); 405 406 return (msk_phy_readreg(sc_if, phy, reg)); 407 } 408 409 static int 410 msk_phy_readreg(struct msk_if_softc *sc_if, int phy, int reg) 411 { 412 struct msk_softc *sc; 413 int i, val; 414 415 sc = sc_if->msk_softc; 416 417 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SMI_CTRL, 418 GM_SMI_CT_PHY_AD(phy) | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD); 419 420 for (i = 0; i < MSK_TIMEOUT; i++) { 421 DELAY(1); 422 val = GMAC_READ_2(sc, sc_if->msk_port, GM_SMI_CTRL); 423 if ((val & GM_SMI_CT_RD_VAL) != 0) { 424 val = GMAC_READ_2(sc, sc_if->msk_port, GM_SMI_DATA); 425 break; 426 } 427 } 428 429 if (i == MSK_TIMEOUT) { 430 if_printf(sc_if->msk_ifp, "phy failed to come ready\n"); 431 val = 0; 432 } 433 434 return (val); 435 } 436 437 static int 438 msk_miibus_writereg(device_t dev, int phy, int reg, int val) 439 { 440 struct msk_if_softc *sc_if; 441 442 sc_if = device_get_softc(dev); 443 444 return (msk_phy_writereg(sc_if, phy, reg, val)); 445 } 446 447 static int 448 msk_phy_writereg(struct msk_if_softc *sc_if, int phy, int reg, int val) 449 { 450 struct msk_softc *sc; 451 int i; 452 453 sc = sc_if->msk_softc; 454 455 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SMI_DATA, val); 456 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SMI_CTRL, 457 GM_SMI_CT_PHY_AD(phy) | GM_SMI_CT_REG_AD(reg)); 458 for (i = 0; i < MSK_TIMEOUT; i++) { 459 DELAY(1); 460 if ((GMAC_READ_2(sc, sc_if->msk_port, GM_SMI_CTRL) & 461 GM_SMI_CT_BUSY) == 0) 462 break; 463 } 464 if (i == MSK_TIMEOUT) 465 if_printf(sc_if->msk_ifp, "phy write timeout\n"); 466 467 return (0); 468 } 469 470 static void 471 msk_miibus_statchg(device_t dev) 472 { 473 struct msk_softc *sc; 474 struct msk_if_softc *sc_if; 475 struct mii_data *mii; 476 struct ifnet *ifp; 477 uint32_t gmac; 478 479 sc_if = device_get_softc(dev); 480 sc = sc_if->msk_softc; 481 482 MSK_IF_LOCK_ASSERT(sc_if); 483 484 mii = device_get_softc(sc_if->msk_miibus); 485 ifp = sc_if->msk_ifp; 486 if (mii == NULL || ifp == NULL || 487 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 488 return; 489 490 sc_if->msk_flags &= ~MSK_FLAG_LINK; 491 if ((mii->mii_media_status & (IFM_AVALID | IFM_ACTIVE)) == 492 (IFM_AVALID | IFM_ACTIVE)) { 493 switch (IFM_SUBTYPE(mii->mii_media_active)) { 494 case IFM_10_T: 495 case IFM_100_TX: 496 sc_if->msk_flags |= MSK_FLAG_LINK; 497 break; 498 case IFM_1000_T: 499 case IFM_1000_SX: 500 case IFM_1000_LX: 501 case IFM_1000_CX: 502 if ((sc_if->msk_flags & MSK_FLAG_FASTETHER) == 0) 503 sc_if->msk_flags |= MSK_FLAG_LINK; 504 break; 505 default: 506 break; 507 } 508 } 509 510 if ((sc_if->msk_flags & MSK_FLAG_LINK) != 0) { 511 /* Enable Tx FIFO Underrun. */ 512 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_MSK), 513 GM_IS_TX_FF_UR | GM_IS_RX_FF_OR); 514 /* 515 * Because mii(4) notify msk(4) that it detected link status 516 * change, there is no need to enable automatic 517 * speed/flow-control/duplex updates. 518 */ 519 gmac = GM_GPCR_AU_ALL_DIS; 520 switch (IFM_SUBTYPE(mii->mii_media_active)) { 521 case IFM_1000_SX: 522 case IFM_1000_T: 523 gmac |= GM_GPCR_SPEED_1000; 524 break; 525 case IFM_100_TX: 526 gmac |= GM_GPCR_SPEED_100; 527 break; 528 case IFM_10_T: 529 break; 530 } 531 532 if ((IFM_OPTIONS(mii->mii_media_active) & 533 IFM_ETH_RXPAUSE) == 0) 534 gmac |= GM_GPCR_FC_RX_DIS; 535 if ((IFM_OPTIONS(mii->mii_media_active) & 536 IFM_ETH_TXPAUSE) == 0) 537 gmac |= GM_GPCR_FC_TX_DIS; 538 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) 539 gmac |= GM_GPCR_DUP_FULL; 540 else 541 gmac |= GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS; 542 gmac |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA; 543 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, gmac); 544 /* Read again to ensure writing. */ 545 GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL); 546 gmac = GMC_PAUSE_OFF; 547 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 548 if ((IFM_OPTIONS(mii->mii_media_active) & 549 IFM_ETH_RXPAUSE) != 0) 550 gmac = GMC_PAUSE_ON; 551 } 552 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), gmac); 553 554 /* Enable PHY interrupt for FIFO underrun/overflow. */ 555 msk_phy_writereg(sc_if, PHY_ADDR_MARV, 556 PHY_MARV_INT_MASK, PHY_M_IS_FIFO_ERROR); 557 } else { 558 /* 559 * Link state changed to down. 560 * Disable PHY interrupts. 561 */ 562 msk_phy_writereg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_MASK, 0); 563 /* Disable Rx/Tx MAC. */ 564 gmac = GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL); 565 if ((GM_GPCR_RX_ENA | GM_GPCR_TX_ENA) != 0) { 566 gmac &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA); 567 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, gmac); 568 /* Read again to ensure writing. */ 569 GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL); 570 } 571 } 572 } 573 574 static void 575 msk_rxfilter(struct msk_if_softc *sc_if) 576 { 577 struct msk_softc *sc; 578 struct ifnet *ifp; 579 struct ifmultiaddr *ifma; 580 uint32_t mchash[2]; 581 uint32_t crc; 582 uint16_t mode; 583 584 sc = sc_if->msk_softc; 585 586 MSK_IF_LOCK_ASSERT(sc_if); 587 588 ifp = sc_if->msk_ifp; 589 590 bzero(mchash, sizeof(mchash)); 591 mode = GMAC_READ_2(sc, sc_if->msk_port, GM_RX_CTRL); 592 if ((ifp->if_flags & IFF_PROMISC) != 0) 593 mode &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA); 594 else if ((ifp->if_flags & IFF_ALLMULTI) != 0) { 595 mode |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA; 596 mchash[0] = 0xffff; 597 mchash[1] = 0xffff; 598 } else { 599 mode |= GM_RXCR_UCF_ENA; 600 if_maddr_rlock(ifp); 601 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 602 if (ifma->ifma_addr->sa_family != AF_LINK) 603 continue; 604 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *) 605 ifma->ifma_addr), ETHER_ADDR_LEN); 606 /* Just want the 6 least significant bits. */ 607 crc &= 0x3f; 608 /* Set the corresponding bit in the hash table. */ 609 mchash[crc >> 5] |= 1 << (crc & 0x1f); 610 } 611 if_maddr_runlock(ifp); 612 if (mchash[0] != 0 || mchash[1] != 0) 613 mode |= GM_RXCR_MCF_ENA; 614 } 615 616 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H1, 617 mchash[0] & 0xffff); 618 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H2, 619 (mchash[0] >> 16) & 0xffff); 620 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H3, 621 mchash[1] & 0xffff); 622 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H4, 623 (mchash[1] >> 16) & 0xffff); 624 GMAC_WRITE_2(sc, sc_if->msk_port, GM_RX_CTRL, mode); 625 } 626 627 static void 628 msk_setvlan(struct msk_if_softc *sc_if, struct ifnet *ifp) 629 { 630 struct msk_softc *sc; 631 632 sc = sc_if->msk_softc; 633 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) { 634 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), 635 RX_VLAN_STRIP_ON); 636 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 637 TX_VLAN_TAG_ON); 638 } else { 639 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), 640 RX_VLAN_STRIP_OFF); 641 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 642 TX_VLAN_TAG_OFF); 643 } 644 } 645 646 static int 647 msk_rx_fill(struct msk_if_softc *sc_if, int jumbo) 648 { 649 uint16_t idx; 650 int i; 651 652 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0 && 653 (sc_if->msk_ifp->if_capenable & IFCAP_RXCSUM) != 0) { 654 /* Wait until controller executes OP_TCPSTART command. */ 655 for (i = 10; i > 0; i--) { 656 DELAY(10); 657 idx = CSR_READ_2(sc_if->msk_softc, 658 Y2_PREF_Q_ADDR(sc_if->msk_rxq, 659 PREF_UNIT_GET_IDX_REG)); 660 if (idx != 0) 661 break; 662 } 663 if (i == 0) { 664 device_printf(sc_if->msk_if_dev, 665 "prefetch unit stuck?\n"); 666 return (ETIMEDOUT); 667 } 668 /* 669 * Fill consumed LE with free buffer. This can be done 670 * in Rx handler but we don't want to add special code 671 * in fast handler. 672 */ 673 if (jumbo > 0) { 674 if (msk_jumbo_newbuf(sc_if, 0) != 0) 675 return (ENOBUFS); 676 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 677 sc_if->msk_cdata.msk_jumbo_rx_ring_map, 678 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 679 } else { 680 if (msk_newbuf(sc_if, 0) != 0) 681 return (ENOBUFS); 682 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_ring_tag, 683 sc_if->msk_cdata.msk_rx_ring_map, 684 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 685 } 686 sc_if->msk_cdata.msk_rx_prod = 0; 687 CSR_WRITE_2(sc_if->msk_softc, 688 Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_PUT_IDX_REG), 689 sc_if->msk_cdata.msk_rx_prod); 690 } 691 return (0); 692 } 693 694 static int 695 msk_init_rx_ring(struct msk_if_softc *sc_if) 696 { 697 struct msk_ring_data *rd; 698 struct msk_rxdesc *rxd; 699 int i, prod; 700 701 MSK_IF_LOCK_ASSERT(sc_if); 702 703 sc_if->msk_cdata.msk_rx_cons = 0; 704 sc_if->msk_cdata.msk_rx_prod = 0; 705 sc_if->msk_cdata.msk_rx_putwm = MSK_PUT_WM; 706 707 rd = &sc_if->msk_rdata; 708 bzero(rd->msk_rx_ring, sizeof(struct msk_rx_desc) * MSK_RX_RING_CNT); 709 prod = sc_if->msk_cdata.msk_rx_prod; 710 i = 0; 711 /* Have controller know how to compute Rx checksum. */ 712 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0 && 713 (sc_if->msk_ifp->if_capenable & IFCAP_RXCSUM) != 0) { 714 rxd = &sc_if->msk_cdata.msk_rxdesc[prod]; 715 rxd->rx_m = NULL; 716 rxd->rx_le = &rd->msk_rx_ring[prod]; 717 rxd->rx_le->msk_addr = htole32(ETHER_HDR_LEN << 16 | 718 ETHER_HDR_LEN); 719 rxd->rx_le->msk_control = htole32(OP_TCPSTART | HW_OWNER); 720 MSK_INC(prod, MSK_RX_RING_CNT); 721 MSK_INC(sc_if->msk_cdata.msk_rx_cons, MSK_RX_RING_CNT); 722 i++; 723 } 724 for (; i < MSK_RX_RING_CNT; i++) { 725 rxd = &sc_if->msk_cdata.msk_rxdesc[prod]; 726 rxd->rx_m = NULL; 727 rxd->rx_le = &rd->msk_rx_ring[prod]; 728 if (msk_newbuf(sc_if, prod) != 0) 729 return (ENOBUFS); 730 MSK_INC(prod, MSK_RX_RING_CNT); 731 } 732 733 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_ring_tag, 734 sc_if->msk_cdata.msk_rx_ring_map, 735 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 736 737 /* Update prefetch unit. */ 738 sc_if->msk_cdata.msk_rx_prod = MSK_RX_RING_CNT - 1; 739 CSR_WRITE_2(sc_if->msk_softc, 740 Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_PUT_IDX_REG), 741 sc_if->msk_cdata.msk_rx_prod); 742 if (msk_rx_fill(sc_if, 0) != 0) 743 return (ENOBUFS); 744 return (0); 745 } 746 747 static int 748 msk_init_jumbo_rx_ring(struct msk_if_softc *sc_if) 749 { 750 struct msk_ring_data *rd; 751 struct msk_rxdesc *rxd; 752 int i, prod; 753 754 MSK_IF_LOCK_ASSERT(sc_if); 755 756 sc_if->msk_cdata.msk_rx_cons = 0; 757 sc_if->msk_cdata.msk_rx_prod = 0; 758 sc_if->msk_cdata.msk_rx_putwm = MSK_PUT_WM; 759 760 rd = &sc_if->msk_rdata; 761 bzero(rd->msk_jumbo_rx_ring, 762 sizeof(struct msk_rx_desc) * MSK_JUMBO_RX_RING_CNT); 763 prod = sc_if->msk_cdata.msk_rx_prod; 764 i = 0; 765 /* Have controller know how to compute Rx checksum. */ 766 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0 && 767 (sc_if->msk_ifp->if_capenable & IFCAP_RXCSUM) != 0) { 768 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[prod]; 769 rxd->rx_m = NULL; 770 rxd->rx_le = &rd->msk_jumbo_rx_ring[prod]; 771 rxd->rx_le->msk_addr = htole32(ETHER_HDR_LEN << 16 | 772 ETHER_HDR_LEN); 773 rxd->rx_le->msk_control = htole32(OP_TCPSTART | HW_OWNER); 774 MSK_INC(prod, MSK_JUMBO_RX_RING_CNT); 775 MSK_INC(sc_if->msk_cdata.msk_rx_cons, MSK_JUMBO_RX_RING_CNT); 776 i++; 777 } 778 for (; i < MSK_JUMBO_RX_RING_CNT; i++) { 779 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[prod]; 780 rxd->rx_m = NULL; 781 rxd->rx_le = &rd->msk_jumbo_rx_ring[prod]; 782 if (msk_jumbo_newbuf(sc_if, prod) != 0) 783 return (ENOBUFS); 784 MSK_INC(prod, MSK_JUMBO_RX_RING_CNT); 785 } 786 787 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 788 sc_if->msk_cdata.msk_jumbo_rx_ring_map, 789 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 790 791 sc_if->msk_cdata.msk_rx_prod = MSK_JUMBO_RX_RING_CNT - 1; 792 CSR_WRITE_2(sc_if->msk_softc, 793 Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_PUT_IDX_REG), 794 sc_if->msk_cdata.msk_rx_prod); 795 if (msk_rx_fill(sc_if, 1) != 0) 796 return (ENOBUFS); 797 return (0); 798 } 799 800 static void 801 msk_init_tx_ring(struct msk_if_softc *sc_if) 802 { 803 struct msk_ring_data *rd; 804 struct msk_txdesc *txd; 805 int i; 806 807 sc_if->msk_cdata.msk_tso_mtu = 0; 808 sc_if->msk_cdata.msk_last_csum = 0; 809 sc_if->msk_cdata.msk_tx_prod = 0; 810 sc_if->msk_cdata.msk_tx_cons = 0; 811 sc_if->msk_cdata.msk_tx_cnt = 0; 812 813 rd = &sc_if->msk_rdata; 814 bzero(rd->msk_tx_ring, sizeof(struct msk_tx_desc) * MSK_TX_RING_CNT); 815 for (i = 0; i < MSK_TX_RING_CNT; i++) { 816 txd = &sc_if->msk_cdata.msk_txdesc[i]; 817 txd->tx_m = NULL; 818 txd->tx_le = &rd->msk_tx_ring[i]; 819 } 820 821 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_ring_tag, 822 sc_if->msk_cdata.msk_tx_ring_map, 823 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 824 } 825 826 static __inline void 827 msk_discard_rxbuf(struct msk_if_softc *sc_if, int idx) 828 { 829 struct msk_rx_desc *rx_le; 830 struct msk_rxdesc *rxd; 831 struct mbuf *m; 832 833 rxd = &sc_if->msk_cdata.msk_rxdesc[idx]; 834 m = rxd->rx_m; 835 rx_le = rxd->rx_le; 836 rx_le->msk_control = htole32(m->m_len | OP_PACKET | HW_OWNER); 837 } 838 839 static __inline void 840 msk_discard_jumbo_rxbuf(struct msk_if_softc *sc_if, int idx) 841 { 842 struct msk_rx_desc *rx_le; 843 struct msk_rxdesc *rxd; 844 struct mbuf *m; 845 846 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[idx]; 847 m = rxd->rx_m; 848 rx_le = rxd->rx_le; 849 rx_le->msk_control = htole32(m->m_len | OP_PACKET | HW_OWNER); 850 } 851 852 static int 853 msk_newbuf(struct msk_if_softc *sc_if, int idx) 854 { 855 struct msk_rx_desc *rx_le; 856 struct msk_rxdesc *rxd; 857 struct mbuf *m; 858 bus_dma_segment_t segs[1]; 859 bus_dmamap_t map; 860 int nsegs; 861 862 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 863 if (m == NULL) 864 return (ENOBUFS); 865 866 m->m_len = m->m_pkthdr.len = MCLBYTES; 867 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) == 0) 868 m_adj(m, ETHER_ALIGN); 869 #ifndef __NO_STRICT_ALIGNMENT 870 else 871 m_adj(m, MSK_RX_BUF_ALIGN); 872 #endif 873 874 if (bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_rx_tag, 875 sc_if->msk_cdata.msk_rx_sparemap, m, segs, &nsegs, 876 BUS_DMA_NOWAIT) != 0) { 877 m_freem(m); 878 return (ENOBUFS); 879 } 880 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 881 882 rxd = &sc_if->msk_cdata.msk_rxdesc[idx]; 883 if (rxd->rx_m != NULL) { 884 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_tag, rxd->rx_dmamap, 885 BUS_DMASYNC_POSTREAD); 886 bus_dmamap_unload(sc_if->msk_cdata.msk_rx_tag, rxd->rx_dmamap); 887 } 888 map = rxd->rx_dmamap; 889 rxd->rx_dmamap = sc_if->msk_cdata.msk_rx_sparemap; 890 sc_if->msk_cdata.msk_rx_sparemap = map; 891 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_tag, rxd->rx_dmamap, 892 BUS_DMASYNC_PREREAD); 893 rxd->rx_m = m; 894 rx_le = rxd->rx_le; 895 rx_le->msk_addr = htole32(MSK_ADDR_LO(segs[0].ds_addr)); 896 rx_le->msk_control = 897 htole32(segs[0].ds_len | OP_PACKET | HW_OWNER); 898 899 return (0); 900 } 901 902 static int 903 msk_jumbo_newbuf(struct msk_if_softc *sc_if, int idx) 904 { 905 struct msk_rx_desc *rx_le; 906 struct msk_rxdesc *rxd; 907 struct mbuf *m; 908 bus_dma_segment_t segs[1]; 909 bus_dmamap_t map; 910 int nsegs; 911 912 m = m_getjcl(M_DONTWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES); 913 if (m == NULL) 914 return (ENOBUFS); 915 if ((m->m_flags & M_EXT) == 0) { 916 m_freem(m); 917 return (ENOBUFS); 918 } 919 m->m_len = m->m_pkthdr.len = MJUM9BYTES; 920 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) == 0) 921 m_adj(m, ETHER_ALIGN); 922 #ifndef __NO_STRICT_ALIGNMENT 923 else 924 m_adj(m, MSK_RX_BUF_ALIGN); 925 #endif 926 927 if (bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_jumbo_rx_tag, 928 sc_if->msk_cdata.msk_jumbo_rx_sparemap, m, segs, &nsegs, 929 BUS_DMA_NOWAIT) != 0) { 930 m_freem(m); 931 return (ENOBUFS); 932 } 933 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 934 935 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[idx]; 936 if (rxd->rx_m != NULL) { 937 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_tag, 938 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 939 bus_dmamap_unload(sc_if->msk_cdata.msk_jumbo_rx_tag, 940 rxd->rx_dmamap); 941 } 942 map = rxd->rx_dmamap; 943 rxd->rx_dmamap = sc_if->msk_cdata.msk_jumbo_rx_sparemap; 944 sc_if->msk_cdata.msk_jumbo_rx_sparemap = map; 945 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_tag, rxd->rx_dmamap, 946 BUS_DMASYNC_PREREAD); 947 rxd->rx_m = m; 948 rx_le = rxd->rx_le; 949 rx_le->msk_addr = htole32(MSK_ADDR_LO(segs[0].ds_addr)); 950 rx_le->msk_control = 951 htole32(segs[0].ds_len | OP_PACKET | HW_OWNER); 952 953 return (0); 954 } 955 956 /* 957 * Set media options. 958 */ 959 static int 960 msk_mediachange(struct ifnet *ifp) 961 { 962 struct msk_if_softc *sc_if; 963 struct mii_data *mii; 964 int error; 965 966 sc_if = ifp->if_softc; 967 968 MSK_IF_LOCK(sc_if); 969 mii = device_get_softc(sc_if->msk_miibus); 970 error = mii_mediachg(mii); 971 MSK_IF_UNLOCK(sc_if); 972 973 return (error); 974 } 975 976 /* 977 * Report current media status. 978 */ 979 static void 980 msk_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 981 { 982 struct msk_if_softc *sc_if; 983 struct mii_data *mii; 984 985 sc_if = ifp->if_softc; 986 MSK_IF_LOCK(sc_if); 987 if ((ifp->if_flags & IFF_UP) == 0) { 988 MSK_IF_UNLOCK(sc_if); 989 return; 990 } 991 mii = device_get_softc(sc_if->msk_miibus); 992 993 mii_pollstat(mii); 994 MSK_IF_UNLOCK(sc_if); 995 ifmr->ifm_active = mii->mii_media_active; 996 ifmr->ifm_status = mii->mii_media_status; 997 } 998 999 static int 1000 msk_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1001 { 1002 struct msk_if_softc *sc_if; 1003 struct ifreq *ifr; 1004 struct mii_data *mii; 1005 int error, mask, reinit; 1006 1007 sc_if = ifp->if_softc; 1008 ifr = (struct ifreq *)data; 1009 error = 0; 1010 1011 switch(command) { 1012 case SIOCSIFMTU: 1013 MSK_IF_LOCK(sc_if); 1014 if (ifr->ifr_mtu > MSK_JUMBO_MTU || ifr->ifr_mtu < ETHERMIN) 1015 error = EINVAL; 1016 else if (ifp->if_mtu != ifr->ifr_mtu) { 1017 if (ifr->ifr_mtu > ETHERMTU) { 1018 if ((sc_if->msk_flags & MSK_FLAG_JUMBO) == 0) { 1019 error = EINVAL; 1020 MSK_IF_UNLOCK(sc_if); 1021 break; 1022 } 1023 if ((sc_if->msk_flags & 1024 MSK_FLAG_JUMBO_NOCSUM) != 0) { 1025 ifp->if_hwassist &= 1026 ~(MSK_CSUM_FEATURES | CSUM_TSO); 1027 ifp->if_capenable &= 1028 ~(IFCAP_TSO4 | IFCAP_TXCSUM); 1029 VLAN_CAPABILITIES(ifp); 1030 } 1031 } 1032 ifp->if_mtu = ifr->ifr_mtu; 1033 msk_init_locked(sc_if); 1034 } 1035 MSK_IF_UNLOCK(sc_if); 1036 break; 1037 case SIOCSIFFLAGS: 1038 MSK_IF_LOCK(sc_if); 1039 if ((ifp->if_flags & IFF_UP) != 0) { 1040 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 && 1041 ((ifp->if_flags ^ sc_if->msk_if_flags) & 1042 (IFF_PROMISC | IFF_ALLMULTI)) != 0) 1043 msk_rxfilter(sc_if); 1044 else if ((sc_if->msk_flags & MSK_FLAG_DETACH) == 0) 1045 msk_init_locked(sc_if); 1046 } else if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1047 msk_stop(sc_if); 1048 sc_if->msk_if_flags = ifp->if_flags; 1049 MSK_IF_UNLOCK(sc_if); 1050 break; 1051 case SIOCADDMULTI: 1052 case SIOCDELMULTI: 1053 MSK_IF_LOCK(sc_if); 1054 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1055 msk_rxfilter(sc_if); 1056 MSK_IF_UNLOCK(sc_if); 1057 break; 1058 case SIOCGIFMEDIA: 1059 case SIOCSIFMEDIA: 1060 mii = device_get_softc(sc_if->msk_miibus); 1061 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1062 break; 1063 case SIOCSIFCAP: 1064 reinit = 0; 1065 MSK_IF_LOCK(sc_if); 1066 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 1067 if ((mask & IFCAP_TXCSUM) != 0 && 1068 (IFCAP_TXCSUM & ifp->if_capabilities) != 0) { 1069 ifp->if_capenable ^= IFCAP_TXCSUM; 1070 if ((IFCAP_TXCSUM & ifp->if_capenable) != 0) 1071 ifp->if_hwassist |= MSK_CSUM_FEATURES; 1072 else 1073 ifp->if_hwassist &= ~MSK_CSUM_FEATURES; 1074 } 1075 if ((mask & IFCAP_RXCSUM) != 0 && 1076 (IFCAP_RXCSUM & ifp->if_capabilities) != 0) { 1077 ifp->if_capenable ^= IFCAP_RXCSUM; 1078 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0) 1079 reinit = 1; 1080 } 1081 if ((mask & IFCAP_VLAN_HWCSUM) != 0 && 1082 (IFCAP_VLAN_HWCSUM & ifp->if_capabilities) != 0) 1083 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; 1084 if ((mask & IFCAP_TSO4) != 0 && 1085 (IFCAP_TSO4 & ifp->if_capabilities) != 0) { 1086 ifp->if_capenable ^= IFCAP_TSO4; 1087 if ((IFCAP_TSO4 & ifp->if_capenable) != 0) 1088 ifp->if_hwassist |= CSUM_TSO; 1089 else 1090 ifp->if_hwassist &= ~CSUM_TSO; 1091 } 1092 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 1093 (IFCAP_VLAN_HWTSO & ifp->if_capabilities) != 0) 1094 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 1095 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 1096 (IFCAP_VLAN_HWTAGGING & ifp->if_capabilities) != 0) { 1097 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 1098 if ((IFCAP_VLAN_HWTAGGING & ifp->if_capenable) == 0) 1099 ifp->if_capenable &= 1100 ~(IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM); 1101 msk_setvlan(sc_if, ifp); 1102 } 1103 if (ifp->if_mtu > ETHERMTU && 1104 (sc_if->msk_flags & MSK_FLAG_JUMBO_NOCSUM) != 0) { 1105 ifp->if_hwassist &= ~(MSK_CSUM_FEATURES | CSUM_TSO); 1106 ifp->if_capenable &= ~(IFCAP_TSO4 | IFCAP_TXCSUM); 1107 } 1108 VLAN_CAPABILITIES(ifp); 1109 if (reinit > 0 && (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 1110 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1111 msk_init_locked(sc_if); 1112 } 1113 MSK_IF_UNLOCK(sc_if); 1114 break; 1115 default: 1116 error = ether_ioctl(ifp, command, data); 1117 break; 1118 } 1119 1120 return (error); 1121 } 1122 1123 static int 1124 mskc_probe(device_t dev) 1125 { 1126 struct msk_product *mp; 1127 uint16_t vendor, devid; 1128 int i; 1129 1130 vendor = pci_get_vendor(dev); 1131 devid = pci_get_device(dev); 1132 mp = msk_products; 1133 for (i = 0; i < sizeof(msk_products)/sizeof(msk_products[0]); 1134 i++, mp++) { 1135 if (vendor == mp->msk_vendorid && devid == mp->msk_deviceid) { 1136 device_set_desc(dev, mp->msk_name); 1137 return (BUS_PROBE_DEFAULT); 1138 } 1139 } 1140 1141 return (ENXIO); 1142 } 1143 1144 static int 1145 mskc_setup_rambuffer(struct msk_softc *sc) 1146 { 1147 int next; 1148 int i; 1149 1150 /* Get adapter SRAM size. */ 1151 sc->msk_ramsize = CSR_READ_1(sc, B2_E_0) * 4; 1152 if (bootverbose) 1153 device_printf(sc->msk_dev, 1154 "RAM buffer size : %dKB\n", sc->msk_ramsize); 1155 if (sc->msk_ramsize == 0) 1156 return (0); 1157 1158 sc->msk_pflags |= MSK_FLAG_RAMBUF; 1159 /* 1160 * Give receiver 2/3 of memory and round down to the multiple 1161 * of 1024. Tx/Rx RAM buffer size of Yukon II should be multiple 1162 * of 1024. 1163 */ 1164 sc->msk_rxqsize = rounddown((sc->msk_ramsize * 1024 * 2) / 3, 1024); 1165 sc->msk_txqsize = (sc->msk_ramsize * 1024) - sc->msk_rxqsize; 1166 for (i = 0, next = 0; i < sc->msk_num_port; i++) { 1167 sc->msk_rxqstart[i] = next; 1168 sc->msk_rxqend[i] = next + sc->msk_rxqsize - 1; 1169 next = sc->msk_rxqend[i] + 1; 1170 sc->msk_txqstart[i] = next; 1171 sc->msk_txqend[i] = next + sc->msk_txqsize - 1; 1172 next = sc->msk_txqend[i] + 1; 1173 if (bootverbose) { 1174 device_printf(sc->msk_dev, 1175 "Port %d : Rx Queue %dKB(0x%08x:0x%08x)\n", i, 1176 sc->msk_rxqsize / 1024, sc->msk_rxqstart[i], 1177 sc->msk_rxqend[i]); 1178 device_printf(sc->msk_dev, 1179 "Port %d : Tx Queue %dKB(0x%08x:0x%08x)\n", i, 1180 sc->msk_txqsize / 1024, sc->msk_txqstart[i], 1181 sc->msk_txqend[i]); 1182 } 1183 } 1184 1185 return (0); 1186 } 1187 1188 static void 1189 msk_phy_power(struct msk_softc *sc, int mode) 1190 { 1191 uint32_t our, val; 1192 int i; 1193 1194 switch (mode) { 1195 case MSK_PHY_POWERUP: 1196 /* Switch power to VCC (WA for VAUX problem). */ 1197 CSR_WRITE_1(sc, B0_POWER_CTRL, 1198 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON); 1199 /* Disable Core Clock Division, set Clock Select to 0. */ 1200 CSR_WRITE_4(sc, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS); 1201 1202 val = 0; 1203 if (sc->msk_hw_id == CHIP_ID_YUKON_XL && 1204 sc->msk_hw_rev > CHIP_REV_YU_XL_A1) { 1205 /* Enable bits are inverted. */ 1206 val = Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS | 1207 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS | 1208 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS; 1209 } 1210 /* 1211 * Enable PCI & Core Clock, enable clock gating for both Links. 1212 */ 1213 CSR_WRITE_1(sc, B2_Y2_CLK_GATE, val); 1214 1215 val = CSR_PCI_READ_4(sc, PCI_OUR_REG_1); 1216 val &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD); 1217 if (sc->msk_hw_id == CHIP_ID_YUKON_XL) { 1218 if (sc->msk_hw_rev > CHIP_REV_YU_XL_A1) { 1219 /* Deassert Low Power for 1st PHY. */ 1220 val |= PCI_Y2_PHY1_COMA; 1221 if (sc->msk_num_port > 1) 1222 val |= PCI_Y2_PHY2_COMA; 1223 } 1224 } 1225 /* Release PHY from PowerDown/COMA mode. */ 1226 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_1, val); 1227 switch (sc->msk_hw_id) { 1228 case CHIP_ID_YUKON_EC_U: 1229 case CHIP_ID_YUKON_EX: 1230 case CHIP_ID_YUKON_FE_P: 1231 case CHIP_ID_YUKON_UL_2: 1232 case CHIP_ID_YUKON_OPT: 1233 CSR_WRITE_2(sc, B0_CTST, Y2_HW_WOL_OFF); 1234 1235 /* Enable all clocks. */ 1236 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_3, 0); 1237 our = CSR_PCI_READ_4(sc, PCI_OUR_REG_4); 1238 our &= (PCI_FORCE_ASPM_REQUEST|PCI_ASPM_GPHY_LINK_DOWN| 1239 PCI_ASPM_INT_FIFO_EMPTY|PCI_ASPM_CLKRUN_REQUEST); 1240 /* Set all bits to 0 except bits 15..12. */ 1241 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_4, our); 1242 our = CSR_PCI_READ_4(sc, PCI_OUR_REG_5); 1243 our &= PCI_CTL_TIM_VMAIN_AV_MSK; 1244 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_5, our); 1245 CSR_PCI_WRITE_4(sc, PCI_CFG_REG_1, 0); 1246 /* 1247 * Disable status race, workaround for 1248 * Yukon EC Ultra & Yukon EX. 1249 */ 1250 val = CSR_READ_4(sc, B2_GP_IO); 1251 val |= GLB_GPIO_STAT_RACE_DIS; 1252 CSR_WRITE_4(sc, B2_GP_IO, val); 1253 CSR_READ_4(sc, B2_GP_IO); 1254 break; 1255 default: 1256 break; 1257 } 1258 for (i = 0; i < sc->msk_num_port; i++) { 1259 CSR_WRITE_2(sc, MR_ADDR(i, GMAC_LINK_CTRL), 1260 GMLC_RST_SET); 1261 CSR_WRITE_2(sc, MR_ADDR(i, GMAC_LINK_CTRL), 1262 GMLC_RST_CLR); 1263 } 1264 break; 1265 case MSK_PHY_POWERDOWN: 1266 val = CSR_PCI_READ_4(sc, PCI_OUR_REG_1); 1267 val |= PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD; 1268 if (sc->msk_hw_id == CHIP_ID_YUKON_XL && 1269 sc->msk_hw_rev > CHIP_REV_YU_XL_A1) { 1270 val &= ~PCI_Y2_PHY1_COMA; 1271 if (sc->msk_num_port > 1) 1272 val &= ~PCI_Y2_PHY2_COMA; 1273 } 1274 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_1, val); 1275 1276 val = Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS | 1277 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS | 1278 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS; 1279 if (sc->msk_hw_id == CHIP_ID_YUKON_XL && 1280 sc->msk_hw_rev > CHIP_REV_YU_XL_A1) { 1281 /* Enable bits are inverted. */ 1282 val = 0; 1283 } 1284 /* 1285 * Disable PCI & Core Clock, disable clock gating for 1286 * both Links. 1287 */ 1288 CSR_WRITE_1(sc, B2_Y2_CLK_GATE, val); 1289 CSR_WRITE_1(sc, B0_POWER_CTRL, 1290 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_ON | PC_VCC_OFF); 1291 break; 1292 default: 1293 break; 1294 } 1295 } 1296 1297 static void 1298 mskc_reset(struct msk_softc *sc) 1299 { 1300 bus_addr_t addr; 1301 uint16_t status; 1302 uint32_t val; 1303 int i; 1304 1305 CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR); 1306 1307 /* Disable ASF. */ 1308 if (sc->msk_hw_id == CHIP_ID_YUKON_EX) { 1309 status = CSR_READ_2(sc, B28_Y2_ASF_HCU_CCSR); 1310 /* Clear AHB bridge & microcontroller reset. */ 1311 status &= ~(Y2_ASF_HCU_CCSR_AHB_RST | 1312 Y2_ASF_HCU_CCSR_CPU_RST_MODE); 1313 /* Clear ASF microcontroller state. */ 1314 status &= ~ Y2_ASF_HCU_CCSR_UC_STATE_MSK; 1315 CSR_WRITE_2(sc, B28_Y2_ASF_HCU_CCSR, status); 1316 } else 1317 CSR_WRITE_1(sc, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET); 1318 CSR_WRITE_2(sc, B0_CTST, Y2_ASF_DISABLE); 1319 1320 /* 1321 * Since we disabled ASF, S/W reset is required for Power Management. 1322 */ 1323 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); 1324 CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR); 1325 1326 /* Clear all error bits in the PCI status register. */ 1327 status = pci_read_config(sc->msk_dev, PCIR_STATUS, 2); 1328 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON); 1329 1330 pci_write_config(sc->msk_dev, PCIR_STATUS, status | 1331 PCIM_STATUS_PERR | PCIM_STATUS_SERR | PCIM_STATUS_RMABORT | 1332 PCIM_STATUS_RTABORT | PCIM_STATUS_MDPERR, 2); 1333 CSR_WRITE_2(sc, B0_CTST, CS_MRST_CLR); 1334 1335 switch (sc->msk_bustype) { 1336 case MSK_PEX_BUS: 1337 /* Clear all PEX errors. */ 1338 CSR_PCI_WRITE_4(sc, PEX_UNC_ERR_STAT, 0xffffffff); 1339 val = CSR_PCI_READ_4(sc, PEX_UNC_ERR_STAT); 1340 if ((val & PEX_RX_OV) != 0) { 1341 sc->msk_intrmask &= ~Y2_IS_HW_ERR; 1342 sc->msk_intrhwemask &= ~Y2_IS_PCI_EXP; 1343 } 1344 break; 1345 case MSK_PCI_BUS: 1346 case MSK_PCIX_BUS: 1347 /* Set Cache Line Size to 2(8bytes) if configured to 0. */ 1348 val = pci_read_config(sc->msk_dev, PCIR_CACHELNSZ, 1); 1349 if (val == 0) 1350 pci_write_config(sc->msk_dev, PCIR_CACHELNSZ, 2, 1); 1351 if (sc->msk_bustype == MSK_PCIX_BUS) { 1352 /* Set Cache Line Size opt. */ 1353 val = pci_read_config(sc->msk_dev, PCI_OUR_REG_1, 4); 1354 val |= PCI_CLS_OPT; 1355 pci_write_config(sc->msk_dev, PCI_OUR_REG_1, val, 4); 1356 } 1357 break; 1358 } 1359 /* Set PHY power state. */ 1360 msk_phy_power(sc, MSK_PHY_POWERUP); 1361 1362 /* Reset GPHY/GMAC Control */ 1363 for (i = 0; i < sc->msk_num_port; i++) { 1364 /* GPHY Control reset. */ 1365 CSR_WRITE_4(sc, MR_ADDR(i, GPHY_CTRL), GPC_RST_SET); 1366 CSR_WRITE_4(sc, MR_ADDR(i, GPHY_CTRL), GPC_RST_CLR); 1367 /* GMAC Control reset. */ 1368 CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), GMC_RST_SET); 1369 CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), GMC_RST_CLR); 1370 CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), GMC_F_LOOPB_OFF); 1371 if (sc->msk_hw_id == CHIP_ID_YUKON_EX) 1372 CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), 1373 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON | 1374 GMC_BYP_RETR_ON); 1375 } 1376 if (sc->msk_hw_id == CHIP_ID_YUKON_OPT && sc->msk_hw_rev == 0) { 1377 /* Disable PCIe PHY powerdown(reg 0x80, bit7). */ 1378 CSR_WRITE_4(sc, Y2_PEX_PHY_DATA, (0x0080 << 16) | 0x0080); 1379 } 1380 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 1381 1382 /* LED On. */ 1383 CSR_WRITE_2(sc, B0_CTST, Y2_LED_STAT_ON); 1384 1385 /* Clear TWSI IRQ. */ 1386 CSR_WRITE_4(sc, B2_I2C_IRQ, I2C_CLR_IRQ); 1387 1388 /* Turn off hardware timer. */ 1389 CSR_WRITE_1(sc, B2_TI_CTRL, TIM_STOP); 1390 CSR_WRITE_1(sc, B2_TI_CTRL, TIM_CLR_IRQ); 1391 1392 /* Turn off descriptor polling. */ 1393 CSR_WRITE_1(sc, B28_DPT_CTRL, DPT_STOP); 1394 1395 /* Turn off time stamps. */ 1396 CSR_WRITE_1(sc, GMAC_TI_ST_CTRL, GMT_ST_STOP); 1397 CSR_WRITE_1(sc, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ); 1398 1399 /* Configure timeout values. */ 1400 for (i = 0; i < sc->msk_num_port; i++) { 1401 CSR_WRITE_2(sc, SELECT_RAM_BUFFER(i, B3_RI_CTRL), RI_RST_SET); 1402 CSR_WRITE_2(sc, SELECT_RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR); 1403 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_R1), 1404 MSK_RI_TO_53); 1405 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XA1), 1406 MSK_RI_TO_53); 1407 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XS1), 1408 MSK_RI_TO_53); 1409 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_R1), 1410 MSK_RI_TO_53); 1411 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XA1), 1412 MSK_RI_TO_53); 1413 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XS1), 1414 MSK_RI_TO_53); 1415 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_R2), 1416 MSK_RI_TO_53); 1417 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XA2), 1418 MSK_RI_TO_53); 1419 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XS2), 1420 MSK_RI_TO_53); 1421 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_R2), 1422 MSK_RI_TO_53); 1423 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XA2), 1424 MSK_RI_TO_53); 1425 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XS2), 1426 MSK_RI_TO_53); 1427 } 1428 1429 /* Disable all interrupts. */ 1430 CSR_WRITE_4(sc, B0_HWE_IMSK, 0); 1431 CSR_READ_4(sc, B0_HWE_IMSK); 1432 CSR_WRITE_4(sc, B0_IMSK, 0); 1433 CSR_READ_4(sc, B0_IMSK); 1434 1435 /* 1436 * On dual port PCI-X card, there is an problem where status 1437 * can be received out of order due to split transactions. 1438 */ 1439 if (sc->msk_pcixcap != 0 && sc->msk_num_port > 1) { 1440 uint16_t pcix_cmd; 1441 1442 pcix_cmd = pci_read_config(sc->msk_dev, 1443 sc->msk_pcixcap + PCIXR_COMMAND, 2); 1444 /* Clear Max Outstanding Split Transactions. */ 1445 pcix_cmd &= ~PCIXM_COMMAND_MAX_SPLITS; 1446 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON); 1447 pci_write_config(sc->msk_dev, 1448 sc->msk_pcixcap + PCIXR_COMMAND, pcix_cmd, 2); 1449 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 1450 } 1451 if (sc->msk_expcap != 0) { 1452 /* Change Max. Read Request Size to 2048 bytes. */ 1453 if (pci_get_max_read_req(sc->msk_dev) == 512) 1454 pci_set_max_read_req(sc->msk_dev, 2048); 1455 } 1456 1457 /* Clear status list. */ 1458 bzero(sc->msk_stat_ring, 1459 sizeof(struct msk_stat_desc) * MSK_STAT_RING_CNT); 1460 sc->msk_stat_cons = 0; 1461 bus_dmamap_sync(sc->msk_stat_tag, sc->msk_stat_map, 1462 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1463 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_RST_SET); 1464 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_RST_CLR); 1465 /* Set the status list base address. */ 1466 addr = sc->msk_stat_ring_paddr; 1467 CSR_WRITE_4(sc, STAT_LIST_ADDR_LO, MSK_ADDR_LO(addr)); 1468 CSR_WRITE_4(sc, STAT_LIST_ADDR_HI, MSK_ADDR_HI(addr)); 1469 /* Set the status list last index. */ 1470 CSR_WRITE_2(sc, STAT_LAST_IDX, MSK_STAT_RING_CNT - 1); 1471 if (sc->msk_hw_id == CHIP_ID_YUKON_EC && 1472 sc->msk_hw_rev == CHIP_REV_YU_EC_A1) { 1473 /* WA for dev. #4.3 */ 1474 CSR_WRITE_2(sc, STAT_TX_IDX_TH, ST_TXTH_IDX_MASK); 1475 /* WA for dev. #4.18 */ 1476 CSR_WRITE_1(sc, STAT_FIFO_WM, 0x21); 1477 CSR_WRITE_1(sc, STAT_FIFO_ISR_WM, 0x07); 1478 } else { 1479 CSR_WRITE_2(sc, STAT_TX_IDX_TH, 0x0a); 1480 CSR_WRITE_1(sc, STAT_FIFO_WM, 0x10); 1481 if (sc->msk_hw_id == CHIP_ID_YUKON_XL && 1482 sc->msk_hw_rev == CHIP_REV_YU_XL_A0) 1483 CSR_WRITE_1(sc, STAT_FIFO_ISR_WM, 0x04); 1484 else 1485 CSR_WRITE_1(sc, STAT_FIFO_ISR_WM, 0x10); 1486 CSR_WRITE_4(sc, STAT_ISR_TIMER_INI, 0x0190); 1487 } 1488 /* 1489 * Use default value for STAT_ISR_TIMER_INI, STAT_LEV_TIMER_INI. 1490 */ 1491 CSR_WRITE_4(sc, STAT_TX_TIMER_INI, MSK_USECS(sc, 1000)); 1492 1493 /* Enable status unit. */ 1494 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_OP_ON); 1495 1496 CSR_WRITE_1(sc, STAT_TX_TIMER_CTRL, TIM_START); 1497 CSR_WRITE_1(sc, STAT_LEV_TIMER_CTRL, TIM_START); 1498 CSR_WRITE_1(sc, STAT_ISR_TIMER_CTRL, TIM_START); 1499 } 1500 1501 static int 1502 msk_probe(device_t dev) 1503 { 1504 struct msk_softc *sc; 1505 char desc[100]; 1506 1507 sc = device_get_softc(device_get_parent(dev)); 1508 /* 1509 * Not much to do here. We always know there will be 1510 * at least one GMAC present, and if there are two, 1511 * mskc_attach() will create a second device instance 1512 * for us. 1513 */ 1514 snprintf(desc, sizeof(desc), 1515 "Marvell Technology Group Ltd. %s Id 0x%02x Rev 0x%02x", 1516 model_name[sc->msk_hw_id - CHIP_ID_YUKON_XL], sc->msk_hw_id, 1517 sc->msk_hw_rev); 1518 device_set_desc_copy(dev, desc); 1519 1520 return (BUS_PROBE_DEFAULT); 1521 } 1522 1523 static int 1524 msk_attach(device_t dev) 1525 { 1526 struct msk_softc *sc; 1527 struct msk_if_softc *sc_if; 1528 struct ifnet *ifp; 1529 struct msk_mii_data *mmd; 1530 int i, port, error; 1531 uint8_t eaddr[6]; 1532 1533 if (dev == NULL) 1534 return (EINVAL); 1535 1536 error = 0; 1537 sc_if = device_get_softc(dev); 1538 sc = device_get_softc(device_get_parent(dev)); 1539 mmd = device_get_ivars(dev); 1540 port = mmd->port; 1541 1542 sc_if->msk_if_dev = dev; 1543 sc_if->msk_port = port; 1544 sc_if->msk_softc = sc; 1545 sc_if->msk_flags = sc->msk_pflags; 1546 sc->msk_if[port] = sc_if; 1547 /* Setup Tx/Rx queue register offsets. */ 1548 if (port == MSK_PORT_A) { 1549 sc_if->msk_txq = Q_XA1; 1550 sc_if->msk_txsq = Q_XS1; 1551 sc_if->msk_rxq = Q_R1; 1552 } else { 1553 sc_if->msk_txq = Q_XA2; 1554 sc_if->msk_txsq = Q_XS2; 1555 sc_if->msk_rxq = Q_R2; 1556 } 1557 1558 callout_init_mtx(&sc_if->msk_tick_ch, &sc_if->msk_softc->msk_mtx, 0); 1559 msk_sysctl_node(sc_if); 1560 1561 if ((error = msk_txrx_dma_alloc(sc_if) != 0)) 1562 goto fail; 1563 msk_rx_dma_jalloc(sc_if); 1564 1565 ifp = sc_if->msk_ifp = if_alloc(IFT_ETHER); 1566 if (ifp == NULL) { 1567 device_printf(sc_if->msk_if_dev, "can not if_alloc()\n"); 1568 error = ENOSPC; 1569 goto fail; 1570 } 1571 ifp->if_softc = sc_if; 1572 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1573 ifp->if_mtu = ETHERMTU; 1574 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1575 ifp->if_capabilities = IFCAP_TXCSUM | IFCAP_TSO4; 1576 /* 1577 * Enable Rx checksum offloading if controller supports 1578 * new descriptor formant and controller is not Yukon XL. 1579 */ 1580 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0 && 1581 sc->msk_hw_id != CHIP_ID_YUKON_XL) 1582 ifp->if_capabilities |= IFCAP_RXCSUM; 1583 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) != 0 && 1584 (sc_if->msk_flags & MSK_FLAG_NORX_CSUM) == 0) 1585 ifp->if_capabilities |= IFCAP_RXCSUM; 1586 ifp->if_hwassist = MSK_CSUM_FEATURES | CSUM_TSO; 1587 ifp->if_capenable = ifp->if_capabilities; 1588 ifp->if_ioctl = msk_ioctl; 1589 ifp->if_start = msk_start; 1590 ifp->if_init = msk_init; 1591 IFQ_SET_MAXLEN(&ifp->if_snd, MSK_TX_RING_CNT - 1); 1592 ifp->if_snd.ifq_drv_maxlen = MSK_TX_RING_CNT - 1; 1593 IFQ_SET_READY(&ifp->if_snd); 1594 /* 1595 * Get station address for this interface. Note that 1596 * dual port cards actually come with three station 1597 * addresses: one for each port, plus an extra. The 1598 * extra one is used by the SysKonnect driver software 1599 * as a 'virtual' station address for when both ports 1600 * are operating in failover mode. Currently we don't 1601 * use this extra address. 1602 */ 1603 MSK_IF_LOCK(sc_if); 1604 for (i = 0; i < ETHER_ADDR_LEN; i++) 1605 eaddr[i] = CSR_READ_1(sc, B2_MAC_1 + (port * 8) + i); 1606 1607 /* 1608 * Call MI attach routine. Can't hold locks when calling into ether_*. 1609 */ 1610 MSK_IF_UNLOCK(sc_if); 1611 ether_ifattach(ifp, eaddr); 1612 MSK_IF_LOCK(sc_if); 1613 1614 /* VLAN capability setup */ 1615 ifp->if_capabilities |= IFCAP_VLAN_MTU; 1616 if ((sc_if->msk_flags & MSK_FLAG_NOHWVLAN) == 0) { 1617 /* 1618 * Due to Tx checksum offload hardware bugs, msk(4) manually 1619 * computes checksum for short frames. For VLAN tagged frames 1620 * this workaround does not work so disable checksum offload 1621 * for VLAN interface. 1622 */ 1623 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWTSO; 1624 /* 1625 * Enable Rx checksum offloading for VLAN tagged frames 1626 * if controller support new descriptor format. 1627 */ 1628 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) != 0 && 1629 (sc_if->msk_flags & MSK_FLAG_NORX_CSUM) == 0) 1630 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM; 1631 } 1632 ifp->if_capenable = ifp->if_capabilities; 1633 1634 /* 1635 * Tell the upper layer(s) we support long frames. 1636 * Must appear after the call to ether_ifattach() because 1637 * ether_ifattach() sets ifi_hdrlen to the default value. 1638 */ 1639 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1640 1641 /* 1642 * Do miibus setup. 1643 */ 1644 MSK_IF_UNLOCK(sc_if); 1645 error = mii_attach(dev, &sc_if->msk_miibus, ifp, msk_mediachange, 1646 msk_mediastatus, BMSR_DEFCAPMASK, PHY_ADDR_MARV, MII_OFFSET_ANY, 1647 mmd->mii_flags); 1648 if (error != 0) { 1649 device_printf(sc_if->msk_if_dev, "attaching PHYs failed\n"); 1650 ether_ifdetach(ifp); 1651 error = ENXIO; 1652 goto fail; 1653 } 1654 1655 fail: 1656 if (error != 0) { 1657 /* Access should be ok even though lock has been dropped */ 1658 sc->msk_if[port] = NULL; 1659 msk_detach(dev); 1660 } 1661 1662 return (error); 1663 } 1664 1665 /* 1666 * Attach the interface. Allocate softc structures, do ifmedia 1667 * setup and ethernet/BPF attach. 1668 */ 1669 static int 1670 mskc_attach(device_t dev) 1671 { 1672 struct msk_softc *sc; 1673 struct msk_mii_data *mmd; 1674 int error, msic, msir, reg; 1675 1676 sc = device_get_softc(dev); 1677 sc->msk_dev = dev; 1678 mtx_init(&sc->msk_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1679 MTX_DEF); 1680 1681 /* 1682 * Map control/status registers. 1683 */ 1684 pci_enable_busmaster(dev); 1685 1686 /* Allocate I/O resource */ 1687 #ifdef MSK_USEIOSPACE 1688 sc->msk_res_spec = msk_res_spec_io; 1689 #else 1690 sc->msk_res_spec = msk_res_spec_mem; 1691 #endif 1692 sc->msk_irq_spec = msk_irq_spec_legacy; 1693 error = bus_alloc_resources(dev, sc->msk_res_spec, sc->msk_res); 1694 if (error) { 1695 if (sc->msk_res_spec == msk_res_spec_mem) 1696 sc->msk_res_spec = msk_res_spec_io; 1697 else 1698 sc->msk_res_spec = msk_res_spec_mem; 1699 error = bus_alloc_resources(dev, sc->msk_res_spec, sc->msk_res); 1700 if (error) { 1701 device_printf(dev, "couldn't allocate %s resources\n", 1702 sc->msk_res_spec == msk_res_spec_mem ? "memory" : 1703 "I/O"); 1704 mtx_destroy(&sc->msk_mtx); 1705 return (ENXIO); 1706 } 1707 } 1708 1709 CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR); 1710 sc->msk_hw_id = CSR_READ_1(sc, B2_CHIP_ID); 1711 sc->msk_hw_rev = (CSR_READ_1(sc, B2_MAC_CFG) >> 4) & 0x0f; 1712 /* Bail out if chip is not recognized. */ 1713 if (sc->msk_hw_id < CHIP_ID_YUKON_XL || 1714 sc->msk_hw_id > CHIP_ID_YUKON_OPT || 1715 sc->msk_hw_id == CHIP_ID_YUKON_SUPR || 1716 sc->msk_hw_id == CHIP_ID_YUKON_UNKNOWN) { 1717 device_printf(dev, "unknown device: id=0x%02x, rev=0x%02x\n", 1718 sc->msk_hw_id, sc->msk_hw_rev); 1719 mtx_destroy(&sc->msk_mtx); 1720 return (ENXIO); 1721 } 1722 1723 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 1724 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 1725 OID_AUTO, "process_limit", CTLTYPE_INT | CTLFLAG_RW, 1726 &sc->msk_process_limit, 0, sysctl_hw_msk_proc_limit, "I", 1727 "max number of Rx events to process"); 1728 1729 sc->msk_process_limit = MSK_PROC_DEFAULT; 1730 error = resource_int_value(device_get_name(dev), device_get_unit(dev), 1731 "process_limit", &sc->msk_process_limit); 1732 if (error == 0) { 1733 if (sc->msk_process_limit < MSK_PROC_MIN || 1734 sc->msk_process_limit > MSK_PROC_MAX) { 1735 device_printf(dev, "process_limit value out of range; " 1736 "using default: %d\n", MSK_PROC_DEFAULT); 1737 sc->msk_process_limit = MSK_PROC_DEFAULT; 1738 } 1739 } 1740 1741 sc->msk_int_holdoff = MSK_INT_HOLDOFF_DEFAULT; 1742 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 1743 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 1744 "int_holdoff", CTLFLAG_RW, &sc->msk_int_holdoff, 0, 1745 "Maximum number of time to delay interrupts"); 1746 resource_int_value(device_get_name(dev), device_get_unit(dev), 1747 "int_holdoff", &sc->msk_int_holdoff); 1748 1749 /* Soft reset. */ 1750 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); 1751 CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR); 1752 sc->msk_pmd = CSR_READ_1(sc, B2_PMD_TYP); 1753 /* Check number of MACs. */ 1754 sc->msk_num_port = 1; 1755 if ((CSR_READ_1(sc, B2_Y2_HW_RES) & CFG_DUAL_MAC_MSK) == 1756 CFG_DUAL_MAC_MSK) { 1757 if (!(CSR_READ_1(sc, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC)) 1758 sc->msk_num_port++; 1759 } 1760 1761 /* Check bus type. */ 1762 if (pci_find_extcap(sc->msk_dev, PCIY_EXPRESS, ®) == 0) { 1763 sc->msk_bustype = MSK_PEX_BUS; 1764 sc->msk_expcap = reg; 1765 } else if (pci_find_extcap(sc->msk_dev, PCIY_PCIX, ®) == 0) { 1766 sc->msk_bustype = MSK_PCIX_BUS; 1767 sc->msk_pcixcap = reg; 1768 } else 1769 sc->msk_bustype = MSK_PCI_BUS; 1770 1771 switch (sc->msk_hw_id) { 1772 case CHIP_ID_YUKON_EC: 1773 sc->msk_clock = 125; /* 125 MHz */ 1774 sc->msk_pflags |= MSK_FLAG_JUMBO; 1775 break; 1776 case CHIP_ID_YUKON_EC_U: 1777 sc->msk_clock = 125; /* 125 MHz */ 1778 sc->msk_pflags |= MSK_FLAG_JUMBO | MSK_FLAG_JUMBO_NOCSUM; 1779 break; 1780 case CHIP_ID_YUKON_EX: 1781 sc->msk_clock = 125; /* 125 MHz */ 1782 sc->msk_pflags |= MSK_FLAG_JUMBO | MSK_FLAG_DESCV2 | 1783 MSK_FLAG_AUTOTX_CSUM; 1784 /* 1785 * Yukon Extreme seems to have silicon bug for 1786 * automatic Tx checksum calculation capability. 1787 */ 1788 if (sc->msk_hw_rev == CHIP_REV_YU_EX_B0) 1789 sc->msk_pflags &= ~MSK_FLAG_AUTOTX_CSUM; 1790 /* 1791 * Yukon Extreme A0 could not use store-and-forward 1792 * for jumbo frames, so disable Tx checksum 1793 * offloading for jumbo frames. 1794 */ 1795 if (sc->msk_hw_rev == CHIP_REV_YU_EX_A0) 1796 sc->msk_pflags |= MSK_FLAG_JUMBO_NOCSUM; 1797 break; 1798 case CHIP_ID_YUKON_FE: 1799 sc->msk_clock = 100; /* 100 MHz */ 1800 sc->msk_pflags |= MSK_FLAG_FASTETHER; 1801 break; 1802 case CHIP_ID_YUKON_FE_P: 1803 sc->msk_clock = 50; /* 50 MHz */ 1804 sc->msk_pflags |= MSK_FLAG_FASTETHER | MSK_FLAG_DESCV2 | 1805 MSK_FLAG_AUTOTX_CSUM; 1806 if (sc->msk_hw_rev == CHIP_REV_YU_FE_P_A0) { 1807 /* 1808 * XXX 1809 * FE+ A0 has status LE writeback bug so msk(4) 1810 * does not rely on status word of received frame 1811 * in msk_rxeof() which in turn disables all 1812 * hardware assistance bits reported by the status 1813 * word as well as validity of the received frame. 1814 * Just pass received frames to upper stack with 1815 * minimal test and let upper stack handle them. 1816 */ 1817 sc->msk_pflags |= MSK_FLAG_NOHWVLAN | 1818 MSK_FLAG_NORXCHK | MSK_FLAG_NORX_CSUM; 1819 } 1820 break; 1821 case CHIP_ID_YUKON_XL: 1822 sc->msk_clock = 156; /* 156 MHz */ 1823 sc->msk_pflags |= MSK_FLAG_JUMBO; 1824 break; 1825 case CHIP_ID_YUKON_UL_2: 1826 sc->msk_clock = 125; /* 125 MHz */ 1827 sc->msk_pflags |= MSK_FLAG_JUMBO; 1828 break; 1829 case CHIP_ID_YUKON_OPT: 1830 sc->msk_clock = 125; /* 125 MHz */ 1831 sc->msk_pflags |= MSK_FLAG_JUMBO | MSK_FLAG_DESCV2; 1832 break; 1833 default: 1834 sc->msk_clock = 156; /* 156 MHz */ 1835 break; 1836 } 1837 1838 /* Allocate IRQ resources. */ 1839 msic = pci_msi_count(dev); 1840 if (bootverbose) 1841 device_printf(dev, "MSI count : %d\n", msic); 1842 if (legacy_intr != 0) 1843 msi_disable = 1; 1844 if (msi_disable == 0 && msic > 0) { 1845 msir = 1; 1846 if (pci_alloc_msi(dev, &msir) == 0) { 1847 if (msir == 1) { 1848 sc->msk_pflags |= MSK_FLAG_MSI; 1849 sc->msk_irq_spec = msk_irq_spec_msi; 1850 } else 1851 pci_release_msi(dev); 1852 } 1853 } 1854 1855 error = bus_alloc_resources(dev, sc->msk_irq_spec, sc->msk_irq); 1856 if (error) { 1857 device_printf(dev, "couldn't allocate IRQ resources\n"); 1858 goto fail; 1859 } 1860 1861 if ((error = msk_status_dma_alloc(sc)) != 0) 1862 goto fail; 1863 1864 /* Set base interrupt mask. */ 1865 sc->msk_intrmask = Y2_IS_HW_ERR | Y2_IS_STAT_BMU; 1866 sc->msk_intrhwemask = Y2_IS_TIST_OV | Y2_IS_MST_ERR | 1867 Y2_IS_IRQ_STAT | Y2_IS_PCI_EXP | Y2_IS_PCI_NEXP; 1868 1869 /* Reset the adapter. */ 1870 mskc_reset(sc); 1871 1872 if ((error = mskc_setup_rambuffer(sc)) != 0) 1873 goto fail; 1874 1875 sc->msk_devs[MSK_PORT_A] = device_add_child(dev, "msk", -1); 1876 if (sc->msk_devs[MSK_PORT_A] == NULL) { 1877 device_printf(dev, "failed to add child for PORT_A\n"); 1878 error = ENXIO; 1879 goto fail; 1880 } 1881 mmd = malloc(sizeof(struct msk_mii_data), M_DEVBUF, M_WAITOK | M_ZERO); 1882 if (mmd == NULL) { 1883 device_printf(dev, "failed to allocate memory for " 1884 "ivars of PORT_A\n"); 1885 error = ENXIO; 1886 goto fail; 1887 } 1888 mmd->port = MSK_PORT_A; 1889 mmd->pmd = sc->msk_pmd; 1890 mmd->mii_flags |= MIIF_DOPAUSE; 1891 if (sc->msk_pmd == 'L' || sc->msk_pmd == 'S') 1892 mmd->mii_flags |= MIIF_HAVEFIBER; 1893 if (sc->msk_pmd == 'P') 1894 mmd->mii_flags |= MIIF_HAVEFIBER | MIIF_MACPRIV0; 1895 device_set_ivars(sc->msk_devs[MSK_PORT_A], mmd); 1896 1897 if (sc->msk_num_port > 1) { 1898 sc->msk_devs[MSK_PORT_B] = device_add_child(dev, "msk", -1); 1899 if (sc->msk_devs[MSK_PORT_B] == NULL) { 1900 device_printf(dev, "failed to add child for PORT_B\n"); 1901 error = ENXIO; 1902 goto fail; 1903 } 1904 mmd = malloc(sizeof(struct msk_mii_data), M_DEVBUF, M_WAITOK | M_ZERO); 1905 if (mmd == NULL) { 1906 device_printf(dev, "failed to allocate memory for " 1907 "ivars of PORT_B\n"); 1908 error = ENXIO; 1909 goto fail; 1910 } 1911 mmd->port = MSK_PORT_B; 1912 mmd->pmd = sc->msk_pmd; 1913 if (sc->msk_pmd == 'L' || sc->msk_pmd == 'S') 1914 mmd->mii_flags |= MIIF_HAVEFIBER; 1915 if (sc->msk_pmd == 'P') 1916 mmd->mii_flags |= MIIF_HAVEFIBER | MIIF_MACPRIV0; 1917 device_set_ivars(sc->msk_devs[MSK_PORT_B], mmd); 1918 } 1919 1920 error = bus_generic_attach(dev); 1921 if (error) { 1922 device_printf(dev, "failed to attach port(s)\n"); 1923 goto fail; 1924 } 1925 1926 /* Hook interrupt last to avoid having to lock softc. */ 1927 error = bus_setup_intr(dev, sc->msk_irq[0], INTR_TYPE_NET | 1928 INTR_MPSAFE, NULL, msk_intr, sc, &sc->msk_intrhand); 1929 if (error != 0) { 1930 device_printf(dev, "couldn't set up interrupt handler\n"); 1931 goto fail; 1932 } 1933 fail: 1934 if (error != 0) 1935 mskc_detach(dev); 1936 1937 return (error); 1938 } 1939 1940 /* 1941 * Shutdown hardware and free up resources. This can be called any 1942 * time after the mutex has been initialized. It is called in both 1943 * the error case in attach and the normal detach case so it needs 1944 * to be careful about only freeing resources that have actually been 1945 * allocated. 1946 */ 1947 static int 1948 msk_detach(device_t dev) 1949 { 1950 struct msk_softc *sc; 1951 struct msk_if_softc *sc_if; 1952 struct ifnet *ifp; 1953 1954 sc_if = device_get_softc(dev); 1955 KASSERT(mtx_initialized(&sc_if->msk_softc->msk_mtx), 1956 ("msk mutex not initialized in msk_detach")); 1957 MSK_IF_LOCK(sc_if); 1958 1959 ifp = sc_if->msk_ifp; 1960 if (device_is_attached(dev)) { 1961 /* XXX */ 1962 sc_if->msk_flags |= MSK_FLAG_DETACH; 1963 msk_stop(sc_if); 1964 /* Can't hold locks while calling detach. */ 1965 MSK_IF_UNLOCK(sc_if); 1966 callout_drain(&sc_if->msk_tick_ch); 1967 ether_ifdetach(ifp); 1968 MSK_IF_LOCK(sc_if); 1969 } 1970 1971 /* 1972 * We're generally called from mskc_detach() which is using 1973 * device_delete_child() to get to here. It's already trashed 1974 * miibus for us, so don't do it here or we'll panic. 1975 * 1976 * if (sc_if->msk_miibus != NULL) { 1977 * device_delete_child(dev, sc_if->msk_miibus); 1978 * sc_if->msk_miibus = NULL; 1979 * } 1980 */ 1981 1982 msk_rx_dma_jfree(sc_if); 1983 msk_txrx_dma_free(sc_if); 1984 bus_generic_detach(dev); 1985 1986 if (ifp) 1987 if_free(ifp); 1988 sc = sc_if->msk_softc; 1989 sc->msk_if[sc_if->msk_port] = NULL; 1990 MSK_IF_UNLOCK(sc_if); 1991 1992 return (0); 1993 } 1994 1995 static int 1996 mskc_detach(device_t dev) 1997 { 1998 struct msk_softc *sc; 1999 2000 sc = device_get_softc(dev); 2001 KASSERT(mtx_initialized(&sc->msk_mtx), ("msk mutex not initialized")); 2002 2003 if (device_is_alive(dev)) { 2004 if (sc->msk_devs[MSK_PORT_A] != NULL) { 2005 free(device_get_ivars(sc->msk_devs[MSK_PORT_A]), 2006 M_DEVBUF); 2007 device_delete_child(dev, sc->msk_devs[MSK_PORT_A]); 2008 } 2009 if (sc->msk_devs[MSK_PORT_B] != NULL) { 2010 free(device_get_ivars(sc->msk_devs[MSK_PORT_B]), 2011 M_DEVBUF); 2012 device_delete_child(dev, sc->msk_devs[MSK_PORT_B]); 2013 } 2014 bus_generic_detach(dev); 2015 } 2016 2017 /* Disable all interrupts. */ 2018 CSR_WRITE_4(sc, B0_IMSK, 0); 2019 CSR_READ_4(sc, B0_IMSK); 2020 CSR_WRITE_4(sc, B0_HWE_IMSK, 0); 2021 CSR_READ_4(sc, B0_HWE_IMSK); 2022 2023 /* LED Off. */ 2024 CSR_WRITE_2(sc, B0_CTST, Y2_LED_STAT_OFF); 2025 2026 /* Put hardware reset. */ 2027 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); 2028 2029 msk_status_dma_free(sc); 2030 2031 if (sc->msk_intrhand) { 2032 bus_teardown_intr(dev, sc->msk_irq[0], sc->msk_intrhand); 2033 sc->msk_intrhand = NULL; 2034 } 2035 bus_release_resources(dev, sc->msk_irq_spec, sc->msk_irq); 2036 if ((sc->msk_pflags & MSK_FLAG_MSI) != 0) 2037 pci_release_msi(dev); 2038 bus_release_resources(dev, sc->msk_res_spec, sc->msk_res); 2039 mtx_destroy(&sc->msk_mtx); 2040 2041 return (0); 2042 } 2043 2044 struct msk_dmamap_arg { 2045 bus_addr_t msk_busaddr; 2046 }; 2047 2048 static void 2049 msk_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 2050 { 2051 struct msk_dmamap_arg *ctx; 2052 2053 if (error != 0) 2054 return; 2055 ctx = arg; 2056 ctx->msk_busaddr = segs[0].ds_addr; 2057 } 2058 2059 /* Create status DMA region. */ 2060 static int 2061 msk_status_dma_alloc(struct msk_softc *sc) 2062 { 2063 struct msk_dmamap_arg ctx; 2064 int error; 2065 2066 error = bus_dma_tag_create( 2067 bus_get_dma_tag(sc->msk_dev), /* parent */ 2068 MSK_STAT_ALIGN, 0, /* alignment, boundary */ 2069 BUS_SPACE_MAXADDR, /* lowaddr */ 2070 BUS_SPACE_MAXADDR, /* highaddr */ 2071 NULL, NULL, /* filter, filterarg */ 2072 MSK_STAT_RING_SZ, /* maxsize */ 2073 1, /* nsegments */ 2074 MSK_STAT_RING_SZ, /* maxsegsize */ 2075 0, /* flags */ 2076 NULL, NULL, /* lockfunc, lockarg */ 2077 &sc->msk_stat_tag); 2078 if (error != 0) { 2079 device_printf(sc->msk_dev, 2080 "failed to create status DMA tag\n"); 2081 return (error); 2082 } 2083 2084 /* Allocate DMA'able memory and load the DMA map for status ring. */ 2085 error = bus_dmamem_alloc(sc->msk_stat_tag, 2086 (void **)&sc->msk_stat_ring, BUS_DMA_WAITOK | BUS_DMA_COHERENT | 2087 BUS_DMA_ZERO, &sc->msk_stat_map); 2088 if (error != 0) { 2089 device_printf(sc->msk_dev, 2090 "failed to allocate DMA'able memory for status ring\n"); 2091 return (error); 2092 } 2093 2094 ctx.msk_busaddr = 0; 2095 error = bus_dmamap_load(sc->msk_stat_tag, 2096 sc->msk_stat_map, sc->msk_stat_ring, MSK_STAT_RING_SZ, 2097 msk_dmamap_cb, &ctx, 0); 2098 if (error != 0) { 2099 device_printf(sc->msk_dev, 2100 "failed to load DMA'able memory for status ring\n"); 2101 return (error); 2102 } 2103 sc->msk_stat_ring_paddr = ctx.msk_busaddr; 2104 2105 return (0); 2106 } 2107 2108 static void 2109 msk_status_dma_free(struct msk_softc *sc) 2110 { 2111 2112 /* Destroy status block. */ 2113 if (sc->msk_stat_tag) { 2114 if (sc->msk_stat_map) { 2115 bus_dmamap_unload(sc->msk_stat_tag, sc->msk_stat_map); 2116 if (sc->msk_stat_ring) { 2117 bus_dmamem_free(sc->msk_stat_tag, 2118 sc->msk_stat_ring, sc->msk_stat_map); 2119 sc->msk_stat_ring = NULL; 2120 } 2121 sc->msk_stat_map = NULL; 2122 } 2123 bus_dma_tag_destroy(sc->msk_stat_tag); 2124 sc->msk_stat_tag = NULL; 2125 } 2126 } 2127 2128 static int 2129 msk_txrx_dma_alloc(struct msk_if_softc *sc_if) 2130 { 2131 struct msk_dmamap_arg ctx; 2132 struct msk_txdesc *txd; 2133 struct msk_rxdesc *rxd; 2134 bus_size_t rxalign; 2135 int error, i; 2136 2137 /* Create parent DMA tag. */ 2138 /* 2139 * XXX 2140 * It seems that Yukon II supports full 64bits DMA operations. But 2141 * it needs two descriptors(list elements) for 64bits DMA operations. 2142 * Since we don't know what DMA address mappings(32bits or 64bits) 2143 * would be used in advance for each mbufs, we limits its DMA space 2144 * to be in range of 32bits address space. Otherwise, we should check 2145 * what DMA address is used and chain another descriptor for the 2146 * 64bits DMA operation. This also means descriptor ring size is 2147 * variable. Limiting DMA address to be in 32bit address space greatly 2148 * simplifies descriptor handling and possibly would increase 2149 * performance a bit due to efficient handling of descriptors. 2150 * Apart from harassing checksum offloading mechanisms, it seems 2151 * it's really bad idea to use a separate descriptor for 64bit 2152 * DMA operation to save small descriptor memory. Anyway, I've 2153 * never seen these exotic scheme on ethernet interface hardware. 2154 */ 2155 error = bus_dma_tag_create( 2156 bus_get_dma_tag(sc_if->msk_if_dev), /* parent */ 2157 1, 0, /* alignment, boundary */ 2158 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 2159 BUS_SPACE_MAXADDR, /* highaddr */ 2160 NULL, NULL, /* filter, filterarg */ 2161 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 2162 0, /* nsegments */ 2163 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 2164 0, /* flags */ 2165 NULL, NULL, /* lockfunc, lockarg */ 2166 &sc_if->msk_cdata.msk_parent_tag); 2167 if (error != 0) { 2168 device_printf(sc_if->msk_if_dev, 2169 "failed to create parent DMA tag\n"); 2170 goto fail; 2171 } 2172 /* Create tag for Tx ring. */ 2173 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2174 MSK_RING_ALIGN, 0, /* alignment, boundary */ 2175 BUS_SPACE_MAXADDR, /* lowaddr */ 2176 BUS_SPACE_MAXADDR, /* highaddr */ 2177 NULL, NULL, /* filter, filterarg */ 2178 MSK_TX_RING_SZ, /* maxsize */ 2179 1, /* nsegments */ 2180 MSK_TX_RING_SZ, /* maxsegsize */ 2181 0, /* flags */ 2182 NULL, NULL, /* lockfunc, lockarg */ 2183 &sc_if->msk_cdata.msk_tx_ring_tag); 2184 if (error != 0) { 2185 device_printf(sc_if->msk_if_dev, 2186 "failed to create Tx ring DMA tag\n"); 2187 goto fail; 2188 } 2189 2190 /* Create tag for Rx ring. */ 2191 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2192 MSK_RING_ALIGN, 0, /* alignment, boundary */ 2193 BUS_SPACE_MAXADDR, /* lowaddr */ 2194 BUS_SPACE_MAXADDR, /* highaddr */ 2195 NULL, NULL, /* filter, filterarg */ 2196 MSK_RX_RING_SZ, /* maxsize */ 2197 1, /* nsegments */ 2198 MSK_RX_RING_SZ, /* maxsegsize */ 2199 0, /* flags */ 2200 NULL, NULL, /* lockfunc, lockarg */ 2201 &sc_if->msk_cdata.msk_rx_ring_tag); 2202 if (error != 0) { 2203 device_printf(sc_if->msk_if_dev, 2204 "failed to create Rx ring DMA tag\n"); 2205 goto fail; 2206 } 2207 2208 /* Create tag for Tx buffers. */ 2209 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2210 1, 0, /* alignment, boundary */ 2211 BUS_SPACE_MAXADDR, /* lowaddr */ 2212 BUS_SPACE_MAXADDR, /* highaddr */ 2213 NULL, NULL, /* filter, filterarg */ 2214 MSK_TSO_MAXSIZE, /* maxsize */ 2215 MSK_MAXTXSEGS, /* nsegments */ 2216 MSK_TSO_MAXSGSIZE, /* maxsegsize */ 2217 0, /* flags */ 2218 NULL, NULL, /* lockfunc, lockarg */ 2219 &sc_if->msk_cdata.msk_tx_tag); 2220 if (error != 0) { 2221 device_printf(sc_if->msk_if_dev, 2222 "failed to create Tx DMA tag\n"); 2223 goto fail; 2224 } 2225 2226 rxalign = 1; 2227 /* 2228 * Workaround hardware hang which seems to happen when Rx buffer 2229 * is not aligned on multiple of FIFO word(8 bytes). 2230 */ 2231 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) != 0) 2232 rxalign = MSK_RX_BUF_ALIGN; 2233 /* Create tag for Rx buffers. */ 2234 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2235 rxalign, 0, /* alignment, boundary */ 2236 BUS_SPACE_MAXADDR, /* lowaddr */ 2237 BUS_SPACE_MAXADDR, /* highaddr */ 2238 NULL, NULL, /* filter, filterarg */ 2239 MCLBYTES, /* maxsize */ 2240 1, /* nsegments */ 2241 MCLBYTES, /* maxsegsize */ 2242 0, /* flags */ 2243 NULL, NULL, /* lockfunc, lockarg */ 2244 &sc_if->msk_cdata.msk_rx_tag); 2245 if (error != 0) { 2246 device_printf(sc_if->msk_if_dev, 2247 "failed to create Rx DMA tag\n"); 2248 goto fail; 2249 } 2250 2251 /* Allocate DMA'able memory and load the DMA map for Tx ring. */ 2252 error = bus_dmamem_alloc(sc_if->msk_cdata.msk_tx_ring_tag, 2253 (void **)&sc_if->msk_rdata.msk_tx_ring, BUS_DMA_WAITOK | 2254 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc_if->msk_cdata.msk_tx_ring_map); 2255 if (error != 0) { 2256 device_printf(sc_if->msk_if_dev, 2257 "failed to allocate DMA'able memory for Tx ring\n"); 2258 goto fail; 2259 } 2260 2261 ctx.msk_busaddr = 0; 2262 error = bus_dmamap_load(sc_if->msk_cdata.msk_tx_ring_tag, 2263 sc_if->msk_cdata.msk_tx_ring_map, sc_if->msk_rdata.msk_tx_ring, 2264 MSK_TX_RING_SZ, msk_dmamap_cb, &ctx, 0); 2265 if (error != 0) { 2266 device_printf(sc_if->msk_if_dev, 2267 "failed to load DMA'able memory for Tx ring\n"); 2268 goto fail; 2269 } 2270 sc_if->msk_rdata.msk_tx_ring_paddr = ctx.msk_busaddr; 2271 2272 /* Allocate DMA'able memory and load the DMA map for Rx ring. */ 2273 error = bus_dmamem_alloc(sc_if->msk_cdata.msk_rx_ring_tag, 2274 (void **)&sc_if->msk_rdata.msk_rx_ring, BUS_DMA_WAITOK | 2275 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc_if->msk_cdata.msk_rx_ring_map); 2276 if (error != 0) { 2277 device_printf(sc_if->msk_if_dev, 2278 "failed to allocate DMA'able memory for Rx ring\n"); 2279 goto fail; 2280 } 2281 2282 ctx.msk_busaddr = 0; 2283 error = bus_dmamap_load(sc_if->msk_cdata.msk_rx_ring_tag, 2284 sc_if->msk_cdata.msk_rx_ring_map, sc_if->msk_rdata.msk_rx_ring, 2285 MSK_RX_RING_SZ, msk_dmamap_cb, &ctx, 0); 2286 if (error != 0) { 2287 device_printf(sc_if->msk_if_dev, 2288 "failed to load DMA'able memory for Rx ring\n"); 2289 goto fail; 2290 } 2291 sc_if->msk_rdata.msk_rx_ring_paddr = ctx.msk_busaddr; 2292 2293 /* Create DMA maps for Tx buffers. */ 2294 for (i = 0; i < MSK_TX_RING_CNT; i++) { 2295 txd = &sc_if->msk_cdata.msk_txdesc[i]; 2296 txd->tx_m = NULL; 2297 txd->tx_dmamap = NULL; 2298 error = bus_dmamap_create(sc_if->msk_cdata.msk_tx_tag, 0, 2299 &txd->tx_dmamap); 2300 if (error != 0) { 2301 device_printf(sc_if->msk_if_dev, 2302 "failed to create Tx dmamap\n"); 2303 goto fail; 2304 } 2305 } 2306 /* Create DMA maps for Rx buffers. */ 2307 if ((error = bus_dmamap_create(sc_if->msk_cdata.msk_rx_tag, 0, 2308 &sc_if->msk_cdata.msk_rx_sparemap)) != 0) { 2309 device_printf(sc_if->msk_if_dev, 2310 "failed to create spare Rx dmamap\n"); 2311 goto fail; 2312 } 2313 for (i = 0; i < MSK_RX_RING_CNT; i++) { 2314 rxd = &sc_if->msk_cdata.msk_rxdesc[i]; 2315 rxd->rx_m = NULL; 2316 rxd->rx_dmamap = NULL; 2317 error = bus_dmamap_create(sc_if->msk_cdata.msk_rx_tag, 0, 2318 &rxd->rx_dmamap); 2319 if (error != 0) { 2320 device_printf(sc_if->msk_if_dev, 2321 "failed to create Rx dmamap\n"); 2322 goto fail; 2323 } 2324 } 2325 2326 fail: 2327 return (error); 2328 } 2329 2330 static int 2331 msk_rx_dma_jalloc(struct msk_if_softc *sc_if) 2332 { 2333 struct msk_dmamap_arg ctx; 2334 struct msk_rxdesc *jrxd; 2335 bus_size_t rxalign; 2336 int error, i; 2337 2338 if (jumbo_disable != 0 || (sc_if->msk_flags & MSK_FLAG_JUMBO) == 0) { 2339 sc_if->msk_flags &= ~MSK_FLAG_JUMBO; 2340 device_printf(sc_if->msk_if_dev, 2341 "disabling jumbo frame support\n"); 2342 return (0); 2343 } 2344 /* Create tag for jumbo Rx ring. */ 2345 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2346 MSK_RING_ALIGN, 0, /* alignment, boundary */ 2347 BUS_SPACE_MAXADDR, /* lowaddr */ 2348 BUS_SPACE_MAXADDR, /* highaddr */ 2349 NULL, NULL, /* filter, filterarg */ 2350 MSK_JUMBO_RX_RING_SZ, /* maxsize */ 2351 1, /* nsegments */ 2352 MSK_JUMBO_RX_RING_SZ, /* maxsegsize */ 2353 0, /* flags */ 2354 NULL, NULL, /* lockfunc, lockarg */ 2355 &sc_if->msk_cdata.msk_jumbo_rx_ring_tag); 2356 if (error != 0) { 2357 device_printf(sc_if->msk_if_dev, 2358 "failed to create jumbo Rx ring DMA tag\n"); 2359 goto jumbo_fail; 2360 } 2361 2362 rxalign = 1; 2363 /* 2364 * Workaround hardware hang which seems to happen when Rx buffer 2365 * is not aligned on multiple of FIFO word(8 bytes). 2366 */ 2367 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) != 0) 2368 rxalign = MSK_RX_BUF_ALIGN; 2369 /* Create tag for jumbo Rx buffers. */ 2370 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2371 rxalign, 0, /* alignment, boundary */ 2372 BUS_SPACE_MAXADDR, /* lowaddr */ 2373 BUS_SPACE_MAXADDR, /* highaddr */ 2374 NULL, NULL, /* filter, filterarg */ 2375 MJUM9BYTES, /* maxsize */ 2376 1, /* nsegments */ 2377 MJUM9BYTES, /* maxsegsize */ 2378 0, /* flags */ 2379 NULL, NULL, /* lockfunc, lockarg */ 2380 &sc_if->msk_cdata.msk_jumbo_rx_tag); 2381 if (error != 0) { 2382 device_printf(sc_if->msk_if_dev, 2383 "failed to create jumbo Rx DMA tag\n"); 2384 goto jumbo_fail; 2385 } 2386 2387 /* Allocate DMA'able memory and load the DMA map for jumbo Rx ring. */ 2388 error = bus_dmamem_alloc(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 2389 (void **)&sc_if->msk_rdata.msk_jumbo_rx_ring, 2390 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 2391 &sc_if->msk_cdata.msk_jumbo_rx_ring_map); 2392 if (error != 0) { 2393 device_printf(sc_if->msk_if_dev, 2394 "failed to allocate DMA'able memory for jumbo Rx ring\n"); 2395 goto jumbo_fail; 2396 } 2397 2398 ctx.msk_busaddr = 0; 2399 error = bus_dmamap_load(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 2400 sc_if->msk_cdata.msk_jumbo_rx_ring_map, 2401 sc_if->msk_rdata.msk_jumbo_rx_ring, MSK_JUMBO_RX_RING_SZ, 2402 msk_dmamap_cb, &ctx, 0); 2403 if (error != 0) { 2404 device_printf(sc_if->msk_if_dev, 2405 "failed to load DMA'able memory for jumbo Rx ring\n"); 2406 goto jumbo_fail; 2407 } 2408 sc_if->msk_rdata.msk_jumbo_rx_ring_paddr = ctx.msk_busaddr; 2409 2410 /* Create DMA maps for jumbo Rx buffers. */ 2411 if ((error = bus_dmamap_create(sc_if->msk_cdata.msk_jumbo_rx_tag, 0, 2412 &sc_if->msk_cdata.msk_jumbo_rx_sparemap)) != 0) { 2413 device_printf(sc_if->msk_if_dev, 2414 "failed to create spare jumbo Rx dmamap\n"); 2415 goto jumbo_fail; 2416 } 2417 for (i = 0; i < MSK_JUMBO_RX_RING_CNT; i++) { 2418 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[i]; 2419 jrxd->rx_m = NULL; 2420 jrxd->rx_dmamap = NULL; 2421 error = bus_dmamap_create(sc_if->msk_cdata.msk_jumbo_rx_tag, 0, 2422 &jrxd->rx_dmamap); 2423 if (error != 0) { 2424 device_printf(sc_if->msk_if_dev, 2425 "failed to create jumbo Rx dmamap\n"); 2426 goto jumbo_fail; 2427 } 2428 } 2429 2430 return (0); 2431 2432 jumbo_fail: 2433 msk_rx_dma_jfree(sc_if); 2434 device_printf(sc_if->msk_if_dev, "disabling jumbo frame support " 2435 "due to resource shortage\n"); 2436 sc_if->msk_flags &= ~MSK_FLAG_JUMBO; 2437 return (error); 2438 } 2439 2440 static void 2441 msk_txrx_dma_free(struct msk_if_softc *sc_if) 2442 { 2443 struct msk_txdesc *txd; 2444 struct msk_rxdesc *rxd; 2445 int i; 2446 2447 /* Tx ring. */ 2448 if (sc_if->msk_cdata.msk_tx_ring_tag) { 2449 if (sc_if->msk_cdata.msk_tx_ring_map) 2450 bus_dmamap_unload(sc_if->msk_cdata.msk_tx_ring_tag, 2451 sc_if->msk_cdata.msk_tx_ring_map); 2452 if (sc_if->msk_cdata.msk_tx_ring_map && 2453 sc_if->msk_rdata.msk_tx_ring) 2454 bus_dmamem_free(sc_if->msk_cdata.msk_tx_ring_tag, 2455 sc_if->msk_rdata.msk_tx_ring, 2456 sc_if->msk_cdata.msk_tx_ring_map); 2457 sc_if->msk_rdata.msk_tx_ring = NULL; 2458 sc_if->msk_cdata.msk_tx_ring_map = NULL; 2459 bus_dma_tag_destroy(sc_if->msk_cdata.msk_tx_ring_tag); 2460 sc_if->msk_cdata.msk_tx_ring_tag = NULL; 2461 } 2462 /* Rx ring. */ 2463 if (sc_if->msk_cdata.msk_rx_ring_tag) { 2464 if (sc_if->msk_cdata.msk_rx_ring_map) 2465 bus_dmamap_unload(sc_if->msk_cdata.msk_rx_ring_tag, 2466 sc_if->msk_cdata.msk_rx_ring_map); 2467 if (sc_if->msk_cdata.msk_rx_ring_map && 2468 sc_if->msk_rdata.msk_rx_ring) 2469 bus_dmamem_free(sc_if->msk_cdata.msk_rx_ring_tag, 2470 sc_if->msk_rdata.msk_rx_ring, 2471 sc_if->msk_cdata.msk_rx_ring_map); 2472 sc_if->msk_rdata.msk_rx_ring = NULL; 2473 sc_if->msk_cdata.msk_rx_ring_map = NULL; 2474 bus_dma_tag_destroy(sc_if->msk_cdata.msk_rx_ring_tag); 2475 sc_if->msk_cdata.msk_rx_ring_tag = NULL; 2476 } 2477 /* Tx buffers. */ 2478 if (sc_if->msk_cdata.msk_tx_tag) { 2479 for (i = 0; i < MSK_TX_RING_CNT; i++) { 2480 txd = &sc_if->msk_cdata.msk_txdesc[i]; 2481 if (txd->tx_dmamap) { 2482 bus_dmamap_destroy(sc_if->msk_cdata.msk_tx_tag, 2483 txd->tx_dmamap); 2484 txd->tx_dmamap = NULL; 2485 } 2486 } 2487 bus_dma_tag_destroy(sc_if->msk_cdata.msk_tx_tag); 2488 sc_if->msk_cdata.msk_tx_tag = NULL; 2489 } 2490 /* Rx buffers. */ 2491 if (sc_if->msk_cdata.msk_rx_tag) { 2492 for (i = 0; i < MSK_RX_RING_CNT; i++) { 2493 rxd = &sc_if->msk_cdata.msk_rxdesc[i]; 2494 if (rxd->rx_dmamap) { 2495 bus_dmamap_destroy(sc_if->msk_cdata.msk_rx_tag, 2496 rxd->rx_dmamap); 2497 rxd->rx_dmamap = NULL; 2498 } 2499 } 2500 if (sc_if->msk_cdata.msk_rx_sparemap) { 2501 bus_dmamap_destroy(sc_if->msk_cdata.msk_rx_tag, 2502 sc_if->msk_cdata.msk_rx_sparemap); 2503 sc_if->msk_cdata.msk_rx_sparemap = 0; 2504 } 2505 bus_dma_tag_destroy(sc_if->msk_cdata.msk_rx_tag); 2506 sc_if->msk_cdata.msk_rx_tag = NULL; 2507 } 2508 if (sc_if->msk_cdata.msk_parent_tag) { 2509 bus_dma_tag_destroy(sc_if->msk_cdata.msk_parent_tag); 2510 sc_if->msk_cdata.msk_parent_tag = NULL; 2511 } 2512 } 2513 2514 static void 2515 msk_rx_dma_jfree(struct msk_if_softc *sc_if) 2516 { 2517 struct msk_rxdesc *jrxd; 2518 int i; 2519 2520 /* Jumbo Rx ring. */ 2521 if (sc_if->msk_cdata.msk_jumbo_rx_ring_tag) { 2522 if (sc_if->msk_cdata.msk_jumbo_rx_ring_map) 2523 bus_dmamap_unload(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 2524 sc_if->msk_cdata.msk_jumbo_rx_ring_map); 2525 if (sc_if->msk_cdata.msk_jumbo_rx_ring_map && 2526 sc_if->msk_rdata.msk_jumbo_rx_ring) 2527 bus_dmamem_free(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 2528 sc_if->msk_rdata.msk_jumbo_rx_ring, 2529 sc_if->msk_cdata.msk_jumbo_rx_ring_map); 2530 sc_if->msk_rdata.msk_jumbo_rx_ring = NULL; 2531 sc_if->msk_cdata.msk_jumbo_rx_ring_map = NULL; 2532 bus_dma_tag_destroy(sc_if->msk_cdata.msk_jumbo_rx_ring_tag); 2533 sc_if->msk_cdata.msk_jumbo_rx_ring_tag = NULL; 2534 } 2535 /* Jumbo Rx buffers. */ 2536 if (sc_if->msk_cdata.msk_jumbo_rx_tag) { 2537 for (i = 0; i < MSK_JUMBO_RX_RING_CNT; i++) { 2538 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[i]; 2539 if (jrxd->rx_dmamap) { 2540 bus_dmamap_destroy( 2541 sc_if->msk_cdata.msk_jumbo_rx_tag, 2542 jrxd->rx_dmamap); 2543 jrxd->rx_dmamap = NULL; 2544 } 2545 } 2546 if (sc_if->msk_cdata.msk_jumbo_rx_sparemap) { 2547 bus_dmamap_destroy(sc_if->msk_cdata.msk_jumbo_rx_tag, 2548 sc_if->msk_cdata.msk_jumbo_rx_sparemap); 2549 sc_if->msk_cdata.msk_jumbo_rx_sparemap = 0; 2550 } 2551 bus_dma_tag_destroy(sc_if->msk_cdata.msk_jumbo_rx_tag); 2552 sc_if->msk_cdata.msk_jumbo_rx_tag = NULL; 2553 } 2554 } 2555 2556 static int 2557 msk_encap(struct msk_if_softc *sc_if, struct mbuf **m_head) 2558 { 2559 struct msk_txdesc *txd, *txd_last; 2560 struct msk_tx_desc *tx_le; 2561 struct mbuf *m; 2562 bus_dmamap_t map; 2563 bus_dma_segment_t txsegs[MSK_MAXTXSEGS]; 2564 uint32_t control, csum, prod, si; 2565 uint16_t offset, tcp_offset, tso_mtu; 2566 int error, i, nseg, tso; 2567 2568 MSK_IF_LOCK_ASSERT(sc_if); 2569 2570 tcp_offset = offset = 0; 2571 m = *m_head; 2572 if (((sc_if->msk_flags & MSK_FLAG_AUTOTX_CSUM) == 0 && 2573 (m->m_pkthdr.csum_flags & MSK_CSUM_FEATURES) != 0) || 2574 ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0 && 2575 (m->m_pkthdr.csum_flags & CSUM_TSO) != 0)) { 2576 /* 2577 * Since mbuf has no protocol specific structure information 2578 * in it we have to inspect protocol information here to 2579 * setup TSO and checksum offload. I don't know why Marvell 2580 * made a such decision in chip design because other GigE 2581 * hardwares normally takes care of all these chores in 2582 * hardware. However, TSO performance of Yukon II is very 2583 * good such that it's worth to implement it. 2584 */ 2585 struct ether_header *eh; 2586 struct ip *ip; 2587 struct tcphdr *tcp; 2588 2589 if (M_WRITABLE(m) == 0) { 2590 /* Get a writable copy. */ 2591 m = m_dup(*m_head, M_DONTWAIT); 2592 m_freem(*m_head); 2593 if (m == NULL) { 2594 *m_head = NULL; 2595 return (ENOBUFS); 2596 } 2597 *m_head = m; 2598 } 2599 2600 offset = sizeof(struct ether_header); 2601 m = m_pullup(m, offset); 2602 if (m == NULL) { 2603 *m_head = NULL; 2604 return (ENOBUFS); 2605 } 2606 eh = mtod(m, struct ether_header *); 2607 /* Check if hardware VLAN insertion is off. */ 2608 if (eh->ether_type == htons(ETHERTYPE_VLAN)) { 2609 offset = sizeof(struct ether_vlan_header); 2610 m = m_pullup(m, offset); 2611 if (m == NULL) { 2612 *m_head = NULL; 2613 return (ENOBUFS); 2614 } 2615 } 2616 m = m_pullup(m, offset + sizeof(struct ip)); 2617 if (m == NULL) { 2618 *m_head = NULL; 2619 return (ENOBUFS); 2620 } 2621 ip = (struct ip *)(mtod(m, char *) + offset); 2622 offset += (ip->ip_hl << 2); 2623 tcp_offset = offset; 2624 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 2625 m = m_pullup(m, offset + sizeof(struct tcphdr)); 2626 if (m == NULL) { 2627 *m_head = NULL; 2628 return (ENOBUFS); 2629 } 2630 tcp = (struct tcphdr *)(mtod(m, char *) + offset); 2631 offset += (tcp->th_off << 2); 2632 } else if ((sc_if->msk_flags & MSK_FLAG_AUTOTX_CSUM) == 0 && 2633 (m->m_pkthdr.len < MSK_MIN_FRAMELEN) && 2634 (m->m_pkthdr.csum_flags & CSUM_TCP) != 0) { 2635 /* 2636 * It seems that Yukon II has Tx checksum offload bug 2637 * for small TCP packets that's less than 60 bytes in 2638 * size (e.g. TCP window probe packet, pure ACK packet). 2639 * Common work around like padding with zeros to make 2640 * the frame minimum ethernet frame size didn't work at 2641 * all. 2642 * Instead of disabling checksum offload completely we 2643 * resort to S/W checksum routine when we encounter 2644 * short TCP frames. 2645 * Short UDP packets appear to be handled correctly by 2646 * Yukon II. Also I assume this bug does not happen on 2647 * controllers that use newer descriptor format or 2648 * automatic Tx checksum calculation. 2649 */ 2650 m = m_pullup(m, offset + sizeof(struct tcphdr)); 2651 if (m == NULL) { 2652 *m_head = NULL; 2653 return (ENOBUFS); 2654 } 2655 *(uint16_t *)(m->m_data + offset + 2656 m->m_pkthdr.csum_data) = in_cksum_skip(m, 2657 m->m_pkthdr.len, offset); 2658 m->m_pkthdr.csum_flags &= ~CSUM_TCP; 2659 } 2660 *m_head = m; 2661 } 2662 2663 prod = sc_if->msk_cdata.msk_tx_prod; 2664 txd = &sc_if->msk_cdata.msk_txdesc[prod]; 2665 txd_last = txd; 2666 map = txd->tx_dmamap; 2667 error = bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_tx_tag, map, 2668 *m_head, txsegs, &nseg, BUS_DMA_NOWAIT); 2669 if (error == EFBIG) { 2670 m = m_collapse(*m_head, M_DONTWAIT, MSK_MAXTXSEGS); 2671 if (m == NULL) { 2672 m_freem(*m_head); 2673 *m_head = NULL; 2674 return (ENOBUFS); 2675 } 2676 *m_head = m; 2677 error = bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_tx_tag, 2678 map, *m_head, txsegs, &nseg, BUS_DMA_NOWAIT); 2679 if (error != 0) { 2680 m_freem(*m_head); 2681 *m_head = NULL; 2682 return (error); 2683 } 2684 } else if (error != 0) 2685 return (error); 2686 if (nseg == 0) { 2687 m_freem(*m_head); 2688 *m_head = NULL; 2689 return (EIO); 2690 } 2691 2692 /* Check number of available descriptors. */ 2693 if (sc_if->msk_cdata.msk_tx_cnt + nseg >= 2694 (MSK_TX_RING_CNT - MSK_RESERVED_TX_DESC_CNT)) { 2695 bus_dmamap_unload(sc_if->msk_cdata.msk_tx_tag, map); 2696 return (ENOBUFS); 2697 } 2698 2699 control = 0; 2700 tso = 0; 2701 tx_le = NULL; 2702 2703 /* Check TSO support. */ 2704 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 2705 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) != 0) 2706 tso_mtu = m->m_pkthdr.tso_segsz; 2707 else 2708 tso_mtu = offset + m->m_pkthdr.tso_segsz; 2709 if (tso_mtu != sc_if->msk_cdata.msk_tso_mtu) { 2710 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2711 tx_le->msk_addr = htole32(tso_mtu); 2712 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) != 0) 2713 tx_le->msk_control = htole32(OP_MSS | HW_OWNER); 2714 else 2715 tx_le->msk_control = 2716 htole32(OP_LRGLEN | HW_OWNER); 2717 sc_if->msk_cdata.msk_tx_cnt++; 2718 MSK_INC(prod, MSK_TX_RING_CNT); 2719 sc_if->msk_cdata.msk_tso_mtu = tso_mtu; 2720 } 2721 tso++; 2722 } 2723 /* Check if we have a VLAN tag to insert. */ 2724 if ((m->m_flags & M_VLANTAG) != 0) { 2725 if (tx_le == NULL) { 2726 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2727 tx_le->msk_addr = htole32(0); 2728 tx_le->msk_control = htole32(OP_VLAN | HW_OWNER | 2729 htons(m->m_pkthdr.ether_vtag)); 2730 sc_if->msk_cdata.msk_tx_cnt++; 2731 MSK_INC(prod, MSK_TX_RING_CNT); 2732 } else { 2733 tx_le->msk_control |= htole32(OP_VLAN | 2734 htons(m->m_pkthdr.ether_vtag)); 2735 } 2736 control |= INS_VLAN; 2737 } 2738 /* Check if we have to handle checksum offload. */ 2739 if (tso == 0 && (m->m_pkthdr.csum_flags & MSK_CSUM_FEATURES) != 0) { 2740 if ((sc_if->msk_flags & MSK_FLAG_AUTOTX_CSUM) != 0) 2741 control |= CALSUM; 2742 else { 2743 control |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM; 2744 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0) 2745 control |= UDPTCP; 2746 /* Checksum write position. */ 2747 csum = (tcp_offset + m->m_pkthdr.csum_data) & 0xffff; 2748 /* Checksum start position. */ 2749 csum |= (uint32_t)tcp_offset << 16; 2750 if (csum != sc_if->msk_cdata.msk_last_csum) { 2751 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2752 tx_le->msk_addr = htole32(csum); 2753 tx_le->msk_control = htole32(1 << 16 | 2754 (OP_TCPLISW | HW_OWNER)); 2755 sc_if->msk_cdata.msk_tx_cnt++; 2756 MSK_INC(prod, MSK_TX_RING_CNT); 2757 sc_if->msk_cdata.msk_last_csum = csum; 2758 } 2759 } 2760 } 2761 2762 si = prod; 2763 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2764 tx_le->msk_addr = htole32(MSK_ADDR_LO(txsegs[0].ds_addr)); 2765 if (tso == 0) 2766 tx_le->msk_control = htole32(txsegs[0].ds_len | control | 2767 OP_PACKET); 2768 else 2769 tx_le->msk_control = htole32(txsegs[0].ds_len | control | 2770 OP_LARGESEND); 2771 sc_if->msk_cdata.msk_tx_cnt++; 2772 MSK_INC(prod, MSK_TX_RING_CNT); 2773 2774 for (i = 1; i < nseg; i++) { 2775 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2776 tx_le->msk_addr = htole32(MSK_ADDR_LO(txsegs[i].ds_addr)); 2777 tx_le->msk_control = htole32(txsegs[i].ds_len | control | 2778 OP_BUFFER | HW_OWNER); 2779 sc_if->msk_cdata.msk_tx_cnt++; 2780 MSK_INC(prod, MSK_TX_RING_CNT); 2781 } 2782 /* Update producer index. */ 2783 sc_if->msk_cdata.msk_tx_prod = prod; 2784 2785 /* Set EOP on the last descriptor. */ 2786 prod = (prod + MSK_TX_RING_CNT - 1) % MSK_TX_RING_CNT; 2787 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2788 tx_le->msk_control |= htole32(EOP); 2789 2790 /* Turn the first descriptor ownership to hardware. */ 2791 tx_le = &sc_if->msk_rdata.msk_tx_ring[si]; 2792 tx_le->msk_control |= htole32(HW_OWNER); 2793 2794 txd = &sc_if->msk_cdata.msk_txdesc[prod]; 2795 map = txd_last->tx_dmamap; 2796 txd_last->tx_dmamap = txd->tx_dmamap; 2797 txd->tx_dmamap = map; 2798 txd->tx_m = m; 2799 2800 /* Sync descriptors. */ 2801 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_tag, map, BUS_DMASYNC_PREWRITE); 2802 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_ring_tag, 2803 sc_if->msk_cdata.msk_tx_ring_map, 2804 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2805 2806 return (0); 2807 } 2808 2809 static void 2810 msk_start(struct ifnet *ifp) 2811 { 2812 struct msk_if_softc *sc_if; 2813 2814 sc_if = ifp->if_softc; 2815 MSK_IF_LOCK(sc_if); 2816 msk_start_locked(ifp); 2817 MSK_IF_UNLOCK(sc_if); 2818 } 2819 2820 static void 2821 msk_start_locked(struct ifnet *ifp) 2822 { 2823 struct msk_if_softc *sc_if; 2824 struct mbuf *m_head; 2825 int enq; 2826 2827 sc_if = ifp->if_softc; 2828 MSK_IF_LOCK_ASSERT(sc_if); 2829 2830 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2831 IFF_DRV_RUNNING || (sc_if->msk_flags & MSK_FLAG_LINK) == 0) 2832 return; 2833 2834 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 2835 sc_if->msk_cdata.msk_tx_cnt < 2836 (MSK_TX_RING_CNT - MSK_RESERVED_TX_DESC_CNT); ) { 2837 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2838 if (m_head == NULL) 2839 break; 2840 /* 2841 * Pack the data into the transmit ring. If we 2842 * don't have room, set the OACTIVE flag and wait 2843 * for the NIC to drain the ring. 2844 */ 2845 if (msk_encap(sc_if, &m_head) != 0) { 2846 if (m_head == NULL) 2847 break; 2848 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2849 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2850 break; 2851 } 2852 2853 enq++; 2854 /* 2855 * If there's a BPF listener, bounce a copy of this frame 2856 * to him. 2857 */ 2858 ETHER_BPF_MTAP(ifp, m_head); 2859 } 2860 2861 if (enq > 0) { 2862 /* Transmit */ 2863 CSR_WRITE_2(sc_if->msk_softc, 2864 Y2_PREF_Q_ADDR(sc_if->msk_txq, PREF_UNIT_PUT_IDX_REG), 2865 sc_if->msk_cdata.msk_tx_prod); 2866 2867 /* Set a timeout in case the chip goes out to lunch. */ 2868 sc_if->msk_watchdog_timer = MSK_TX_TIMEOUT; 2869 } 2870 } 2871 2872 static void 2873 msk_watchdog(struct msk_if_softc *sc_if) 2874 { 2875 struct ifnet *ifp; 2876 2877 MSK_IF_LOCK_ASSERT(sc_if); 2878 2879 if (sc_if->msk_watchdog_timer == 0 || --sc_if->msk_watchdog_timer) 2880 return; 2881 ifp = sc_if->msk_ifp; 2882 if ((sc_if->msk_flags & MSK_FLAG_LINK) == 0) { 2883 if (bootverbose) 2884 if_printf(sc_if->msk_ifp, "watchdog timeout " 2885 "(missed link)\n"); 2886 ifp->if_oerrors++; 2887 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2888 msk_init_locked(sc_if); 2889 return; 2890 } 2891 2892 if_printf(ifp, "watchdog timeout\n"); 2893 ifp->if_oerrors++; 2894 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2895 msk_init_locked(sc_if); 2896 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2897 msk_start_locked(ifp); 2898 } 2899 2900 static int 2901 mskc_shutdown(device_t dev) 2902 { 2903 struct msk_softc *sc; 2904 int i; 2905 2906 sc = device_get_softc(dev); 2907 MSK_LOCK(sc); 2908 for (i = 0; i < sc->msk_num_port; i++) { 2909 if (sc->msk_if[i] != NULL && sc->msk_if[i]->msk_ifp != NULL && 2910 ((sc->msk_if[i]->msk_ifp->if_drv_flags & 2911 IFF_DRV_RUNNING) != 0)) 2912 msk_stop(sc->msk_if[i]); 2913 } 2914 MSK_UNLOCK(sc); 2915 2916 /* Put hardware reset. */ 2917 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); 2918 return (0); 2919 } 2920 2921 static int 2922 mskc_suspend(device_t dev) 2923 { 2924 struct msk_softc *sc; 2925 int i; 2926 2927 sc = device_get_softc(dev); 2928 2929 MSK_LOCK(sc); 2930 2931 for (i = 0; i < sc->msk_num_port; i++) { 2932 if (sc->msk_if[i] != NULL && sc->msk_if[i]->msk_ifp != NULL && 2933 ((sc->msk_if[i]->msk_ifp->if_drv_flags & 2934 IFF_DRV_RUNNING) != 0)) 2935 msk_stop(sc->msk_if[i]); 2936 } 2937 2938 /* Disable all interrupts. */ 2939 CSR_WRITE_4(sc, B0_IMSK, 0); 2940 CSR_READ_4(sc, B0_IMSK); 2941 CSR_WRITE_4(sc, B0_HWE_IMSK, 0); 2942 CSR_READ_4(sc, B0_HWE_IMSK); 2943 2944 msk_phy_power(sc, MSK_PHY_POWERDOWN); 2945 2946 /* Put hardware reset. */ 2947 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); 2948 sc->msk_pflags |= MSK_FLAG_SUSPEND; 2949 2950 MSK_UNLOCK(sc); 2951 2952 return (0); 2953 } 2954 2955 static int 2956 mskc_resume(device_t dev) 2957 { 2958 struct msk_softc *sc; 2959 int i; 2960 2961 sc = device_get_softc(dev); 2962 2963 MSK_LOCK(sc); 2964 2965 mskc_reset(sc); 2966 for (i = 0; i < sc->msk_num_port; i++) { 2967 if (sc->msk_if[i] != NULL && sc->msk_if[i]->msk_ifp != NULL && 2968 ((sc->msk_if[i]->msk_ifp->if_flags & IFF_UP) != 0)) { 2969 sc->msk_if[i]->msk_ifp->if_drv_flags &= 2970 ~IFF_DRV_RUNNING; 2971 msk_init_locked(sc->msk_if[i]); 2972 } 2973 } 2974 sc->msk_pflags &= ~MSK_FLAG_SUSPEND; 2975 2976 MSK_UNLOCK(sc); 2977 2978 return (0); 2979 } 2980 2981 #ifndef __NO_STRICT_ALIGNMENT 2982 static __inline void 2983 msk_fixup_rx(struct mbuf *m) 2984 { 2985 int i; 2986 uint16_t *src, *dst; 2987 2988 src = mtod(m, uint16_t *); 2989 dst = src - 3; 2990 2991 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 2992 *dst++ = *src++; 2993 2994 m->m_data -= (MSK_RX_BUF_ALIGN - ETHER_ALIGN); 2995 } 2996 #endif 2997 2998 static __inline void 2999 msk_rxcsum(struct msk_if_softc *sc_if, uint32_t control, struct mbuf *m) 3000 { 3001 struct ether_header *eh; 3002 struct ip *ip; 3003 struct udphdr *uh; 3004 int32_t hlen, len, pktlen, temp32; 3005 uint16_t csum, *opts; 3006 3007 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) != 0) { 3008 if ((control & (CSS_IPV4 | CSS_IPFRAG)) == CSS_IPV4) { 3009 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 3010 if ((control & CSS_IPV4_CSUM_OK) != 0) 3011 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 3012 if ((control & (CSS_TCP | CSS_UDP)) != 0 && 3013 (control & (CSS_TCPUDP_CSUM_OK)) != 0) { 3014 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID | 3015 CSUM_PSEUDO_HDR; 3016 m->m_pkthdr.csum_data = 0xffff; 3017 } 3018 } 3019 return; 3020 } 3021 /* 3022 * Marvell Yukon controllers that support OP_RXCHKS has known 3023 * to have various Rx checksum offloading bugs. These 3024 * controllers can be configured to compute simple checksum 3025 * at two different positions. So we can compute IP and TCP/UDP 3026 * checksum at the same time. We intentionally have controller 3027 * compute TCP/UDP checksum twice by specifying the same 3028 * checksum start position and compare the result. If the value 3029 * is different it would indicate the hardware logic was wrong. 3030 */ 3031 if ((sc_if->msk_csum & 0xFFFF) != (sc_if->msk_csum >> 16)) { 3032 if (bootverbose) 3033 device_printf(sc_if->msk_if_dev, 3034 "Rx checksum value mismatch!\n"); 3035 return; 3036 } 3037 pktlen = m->m_pkthdr.len; 3038 if (pktlen < sizeof(struct ether_header) + sizeof(struct ip)) 3039 return; 3040 eh = mtod(m, struct ether_header *); 3041 if (eh->ether_type != htons(ETHERTYPE_IP)) 3042 return; 3043 ip = (struct ip *)(eh + 1); 3044 if (ip->ip_v != IPVERSION) 3045 return; 3046 3047 hlen = ip->ip_hl << 2; 3048 pktlen -= sizeof(struct ether_header); 3049 if (hlen < sizeof(struct ip)) 3050 return; 3051 if (ntohs(ip->ip_len) < hlen) 3052 return; 3053 if (ntohs(ip->ip_len) != pktlen) 3054 return; 3055 if (ip->ip_off & htons(IP_MF | IP_OFFMASK)) 3056 return; /* can't handle fragmented packet. */ 3057 3058 switch (ip->ip_p) { 3059 case IPPROTO_TCP: 3060 if (pktlen < (hlen + sizeof(struct tcphdr))) 3061 return; 3062 break; 3063 case IPPROTO_UDP: 3064 if (pktlen < (hlen + sizeof(struct udphdr))) 3065 return; 3066 uh = (struct udphdr *)((caddr_t)ip + hlen); 3067 if (uh->uh_sum == 0) 3068 return; /* no checksum */ 3069 break; 3070 default: 3071 return; 3072 } 3073 csum = bswap16(sc_if->msk_csum & 0xFFFF); 3074 /* Checksum fixup for IP options. */ 3075 len = hlen - sizeof(struct ip); 3076 if (len > 0) { 3077 opts = (uint16_t *)(ip + 1); 3078 for (; len > 0; len -= sizeof(uint16_t), opts++) { 3079 temp32 = csum - *opts; 3080 temp32 = (temp32 >> 16) + (temp32 & 65535); 3081 csum = temp32 & 65535; 3082 } 3083 } 3084 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID; 3085 m->m_pkthdr.csum_data = csum; 3086 } 3087 3088 static void 3089 msk_rxeof(struct msk_if_softc *sc_if, uint32_t status, uint32_t control, 3090 int len) 3091 { 3092 struct mbuf *m; 3093 struct ifnet *ifp; 3094 struct msk_rxdesc *rxd; 3095 int cons, rxlen; 3096 3097 ifp = sc_if->msk_ifp; 3098 3099 MSK_IF_LOCK_ASSERT(sc_if); 3100 3101 cons = sc_if->msk_cdata.msk_rx_cons; 3102 do { 3103 rxlen = status >> 16; 3104 if ((status & GMR_FS_VLAN) != 0 && 3105 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 3106 rxlen -= ETHER_VLAN_ENCAP_LEN; 3107 if ((sc_if->msk_flags & MSK_FLAG_NORXCHK) != 0) { 3108 /* 3109 * For controllers that returns bogus status code 3110 * just do minimal check and let upper stack 3111 * handle this frame. 3112 */ 3113 if (len > MSK_MAX_FRAMELEN || len < ETHER_HDR_LEN) { 3114 ifp->if_ierrors++; 3115 msk_discard_rxbuf(sc_if, cons); 3116 break; 3117 } 3118 } else if (len > sc_if->msk_framesize || 3119 ((status & GMR_FS_ANY_ERR) != 0) || 3120 ((status & GMR_FS_RX_OK) == 0) || (rxlen != len)) { 3121 /* Don't count flow-control packet as errors. */ 3122 if ((status & GMR_FS_GOOD_FC) == 0) 3123 ifp->if_ierrors++; 3124 msk_discard_rxbuf(sc_if, cons); 3125 break; 3126 } 3127 rxd = &sc_if->msk_cdata.msk_rxdesc[cons]; 3128 m = rxd->rx_m; 3129 if (msk_newbuf(sc_if, cons) != 0) { 3130 ifp->if_iqdrops++; 3131 /* Reuse old buffer. */ 3132 msk_discard_rxbuf(sc_if, cons); 3133 break; 3134 } 3135 m->m_pkthdr.rcvif = ifp; 3136 m->m_pkthdr.len = m->m_len = len; 3137 #ifndef __NO_STRICT_ALIGNMENT 3138 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) != 0) 3139 msk_fixup_rx(m); 3140 #endif 3141 ifp->if_ipackets++; 3142 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 3143 msk_rxcsum(sc_if, control, m); 3144 /* Check for VLAN tagged packets. */ 3145 if ((status & GMR_FS_VLAN) != 0 && 3146 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) { 3147 m->m_pkthdr.ether_vtag = sc_if->msk_vtag; 3148 m->m_flags |= M_VLANTAG; 3149 } 3150 MSK_IF_UNLOCK(sc_if); 3151 (*ifp->if_input)(ifp, m); 3152 MSK_IF_LOCK(sc_if); 3153 } while (0); 3154 3155 MSK_INC(sc_if->msk_cdata.msk_rx_cons, MSK_RX_RING_CNT); 3156 MSK_INC(sc_if->msk_cdata.msk_rx_prod, MSK_RX_RING_CNT); 3157 } 3158 3159 static void 3160 msk_jumbo_rxeof(struct msk_if_softc *sc_if, uint32_t status, uint32_t control, 3161 int len) 3162 { 3163 struct mbuf *m; 3164 struct ifnet *ifp; 3165 struct msk_rxdesc *jrxd; 3166 int cons, rxlen; 3167 3168 ifp = sc_if->msk_ifp; 3169 3170 MSK_IF_LOCK_ASSERT(sc_if); 3171 3172 cons = sc_if->msk_cdata.msk_rx_cons; 3173 do { 3174 rxlen = status >> 16; 3175 if ((status & GMR_FS_VLAN) != 0 && 3176 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 3177 rxlen -= ETHER_VLAN_ENCAP_LEN; 3178 if (len > sc_if->msk_framesize || 3179 ((status & GMR_FS_ANY_ERR) != 0) || 3180 ((status & GMR_FS_RX_OK) == 0) || (rxlen != len)) { 3181 /* Don't count flow-control packet as errors. */ 3182 if ((status & GMR_FS_GOOD_FC) == 0) 3183 ifp->if_ierrors++; 3184 msk_discard_jumbo_rxbuf(sc_if, cons); 3185 break; 3186 } 3187 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[cons]; 3188 m = jrxd->rx_m; 3189 if (msk_jumbo_newbuf(sc_if, cons) != 0) { 3190 ifp->if_iqdrops++; 3191 /* Reuse old buffer. */ 3192 msk_discard_jumbo_rxbuf(sc_if, cons); 3193 break; 3194 } 3195 m->m_pkthdr.rcvif = ifp; 3196 m->m_pkthdr.len = m->m_len = len; 3197 #ifndef __NO_STRICT_ALIGNMENT 3198 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) != 0) 3199 msk_fixup_rx(m); 3200 #endif 3201 ifp->if_ipackets++; 3202 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 3203 msk_rxcsum(sc_if, control, m); 3204 /* Check for VLAN tagged packets. */ 3205 if ((status & GMR_FS_VLAN) != 0 && 3206 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) { 3207 m->m_pkthdr.ether_vtag = sc_if->msk_vtag; 3208 m->m_flags |= M_VLANTAG; 3209 } 3210 MSK_IF_UNLOCK(sc_if); 3211 (*ifp->if_input)(ifp, m); 3212 MSK_IF_LOCK(sc_if); 3213 } while (0); 3214 3215 MSK_INC(sc_if->msk_cdata.msk_rx_cons, MSK_JUMBO_RX_RING_CNT); 3216 MSK_INC(sc_if->msk_cdata.msk_rx_prod, MSK_JUMBO_RX_RING_CNT); 3217 } 3218 3219 static void 3220 msk_txeof(struct msk_if_softc *sc_if, int idx) 3221 { 3222 struct msk_txdesc *txd; 3223 struct msk_tx_desc *cur_tx; 3224 struct ifnet *ifp; 3225 uint32_t control; 3226 int cons, prog; 3227 3228 MSK_IF_LOCK_ASSERT(sc_if); 3229 3230 ifp = sc_if->msk_ifp; 3231 3232 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_ring_tag, 3233 sc_if->msk_cdata.msk_tx_ring_map, 3234 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3235 /* 3236 * Go through our tx ring and free mbufs for those 3237 * frames that have been sent. 3238 */ 3239 cons = sc_if->msk_cdata.msk_tx_cons; 3240 prog = 0; 3241 for (; cons != idx; MSK_INC(cons, MSK_TX_RING_CNT)) { 3242 if (sc_if->msk_cdata.msk_tx_cnt <= 0) 3243 break; 3244 prog++; 3245 cur_tx = &sc_if->msk_rdata.msk_tx_ring[cons]; 3246 control = le32toh(cur_tx->msk_control); 3247 sc_if->msk_cdata.msk_tx_cnt--; 3248 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3249 if ((control & EOP) == 0) 3250 continue; 3251 txd = &sc_if->msk_cdata.msk_txdesc[cons]; 3252 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_tag, txd->tx_dmamap, 3253 BUS_DMASYNC_POSTWRITE); 3254 bus_dmamap_unload(sc_if->msk_cdata.msk_tx_tag, txd->tx_dmamap); 3255 3256 ifp->if_opackets++; 3257 KASSERT(txd->tx_m != NULL, ("%s: freeing NULL mbuf!", 3258 __func__)); 3259 m_freem(txd->tx_m); 3260 txd->tx_m = NULL; 3261 } 3262 3263 if (prog > 0) { 3264 sc_if->msk_cdata.msk_tx_cons = cons; 3265 if (sc_if->msk_cdata.msk_tx_cnt == 0) 3266 sc_if->msk_watchdog_timer = 0; 3267 /* No need to sync LEs as we didn't update LEs. */ 3268 } 3269 } 3270 3271 static void 3272 msk_tick(void *xsc_if) 3273 { 3274 struct msk_if_softc *sc_if; 3275 struct mii_data *mii; 3276 3277 sc_if = xsc_if; 3278 3279 MSK_IF_LOCK_ASSERT(sc_if); 3280 3281 mii = device_get_softc(sc_if->msk_miibus); 3282 3283 mii_tick(mii); 3284 if ((sc_if->msk_flags & MSK_FLAG_LINK) == 0) 3285 msk_miibus_statchg(sc_if->msk_if_dev); 3286 msk_handle_events(sc_if->msk_softc); 3287 msk_watchdog(sc_if); 3288 callout_reset(&sc_if->msk_tick_ch, hz, msk_tick, sc_if); 3289 } 3290 3291 static void 3292 msk_intr_phy(struct msk_if_softc *sc_if) 3293 { 3294 uint16_t status; 3295 3296 msk_phy_readreg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_STAT); 3297 status = msk_phy_readreg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_STAT); 3298 /* Handle FIFO Underrun/Overflow? */ 3299 if ((status & PHY_M_IS_FIFO_ERROR)) 3300 device_printf(sc_if->msk_if_dev, 3301 "PHY FIFO underrun/overflow.\n"); 3302 } 3303 3304 static void 3305 msk_intr_gmac(struct msk_if_softc *sc_if) 3306 { 3307 struct msk_softc *sc; 3308 uint8_t status; 3309 3310 sc = sc_if->msk_softc; 3311 status = CSR_READ_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_SRC)); 3312 3313 /* GMAC Rx FIFO overrun. */ 3314 if ((status & GM_IS_RX_FF_OR) != 0) 3315 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), 3316 GMF_CLI_RX_FO); 3317 /* GMAC Tx FIFO underrun. */ 3318 if ((status & GM_IS_TX_FF_UR) != 0) { 3319 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 3320 GMF_CLI_TX_FU); 3321 device_printf(sc_if->msk_if_dev, "Tx FIFO underrun!\n"); 3322 /* 3323 * XXX 3324 * In case of Tx underrun, we may need to flush/reset 3325 * Tx MAC but that would also require resynchronization 3326 * with status LEs. Reinitializing status LEs would 3327 * affect other port in dual MAC configuration so it 3328 * should be avoided as possible as we can. 3329 * Due to lack of documentation it's all vague guess but 3330 * it needs more investigation. 3331 */ 3332 } 3333 } 3334 3335 static void 3336 msk_handle_hwerr(struct msk_if_softc *sc_if, uint32_t status) 3337 { 3338 struct msk_softc *sc; 3339 3340 sc = sc_if->msk_softc; 3341 if ((status & Y2_IS_PAR_RD1) != 0) { 3342 device_printf(sc_if->msk_if_dev, 3343 "RAM buffer read parity error\n"); 3344 /* Clear IRQ. */ 3345 CSR_WRITE_2(sc, SELECT_RAM_BUFFER(sc_if->msk_port, B3_RI_CTRL), 3346 RI_CLR_RD_PERR); 3347 } 3348 if ((status & Y2_IS_PAR_WR1) != 0) { 3349 device_printf(sc_if->msk_if_dev, 3350 "RAM buffer write parity error\n"); 3351 /* Clear IRQ. */ 3352 CSR_WRITE_2(sc, SELECT_RAM_BUFFER(sc_if->msk_port, B3_RI_CTRL), 3353 RI_CLR_WR_PERR); 3354 } 3355 if ((status & Y2_IS_PAR_MAC1) != 0) { 3356 device_printf(sc_if->msk_if_dev, "Tx MAC parity error\n"); 3357 /* Clear IRQ. */ 3358 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 3359 GMF_CLI_TX_PE); 3360 } 3361 if ((status & Y2_IS_PAR_RX1) != 0) { 3362 device_printf(sc_if->msk_if_dev, "Rx parity error\n"); 3363 /* Clear IRQ. */ 3364 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_CLR_IRQ_PAR); 3365 } 3366 if ((status & (Y2_IS_TCP_TXS1 | Y2_IS_TCP_TXA1)) != 0) { 3367 device_printf(sc_if->msk_if_dev, "TCP segmentation error\n"); 3368 /* Clear IRQ. */ 3369 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_CLR_IRQ_TCP); 3370 } 3371 } 3372 3373 static void 3374 msk_intr_hwerr(struct msk_softc *sc) 3375 { 3376 uint32_t status; 3377 uint32_t tlphead[4]; 3378 3379 status = CSR_READ_4(sc, B0_HWE_ISRC); 3380 /* Time Stamp timer overflow. */ 3381 if ((status & Y2_IS_TIST_OV) != 0) 3382 CSR_WRITE_1(sc, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ); 3383 if ((status & Y2_IS_PCI_NEXP) != 0) { 3384 /* 3385 * PCI Express Error occured which is not described in PEX 3386 * spec. 3387 * This error is also mapped either to Master Abort( 3388 * Y2_IS_MST_ERR) or Target Abort (Y2_IS_IRQ_STAT) bit and 3389 * can only be cleared there. 3390 */ 3391 device_printf(sc->msk_dev, 3392 "PCI Express protocol violation error\n"); 3393 } 3394 3395 if ((status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) != 0) { 3396 uint16_t v16; 3397 3398 if ((status & Y2_IS_MST_ERR) != 0) 3399 device_printf(sc->msk_dev, 3400 "unexpected IRQ Status error\n"); 3401 else 3402 device_printf(sc->msk_dev, 3403 "unexpected IRQ Master error\n"); 3404 /* Reset all bits in the PCI status register. */ 3405 v16 = pci_read_config(sc->msk_dev, PCIR_STATUS, 2); 3406 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON); 3407 pci_write_config(sc->msk_dev, PCIR_STATUS, v16 | 3408 PCIM_STATUS_PERR | PCIM_STATUS_SERR | PCIM_STATUS_RMABORT | 3409 PCIM_STATUS_RTABORT | PCIM_STATUS_MDPERR, 2); 3410 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 3411 } 3412 3413 /* Check for PCI Express Uncorrectable Error. */ 3414 if ((status & Y2_IS_PCI_EXP) != 0) { 3415 uint32_t v32; 3416 3417 /* 3418 * On PCI Express bus bridges are called root complexes (RC). 3419 * PCI Express errors are recognized by the root complex too, 3420 * which requests the system to handle the problem. After 3421 * error occurence it may be that no access to the adapter 3422 * may be performed any longer. 3423 */ 3424 3425 v32 = CSR_PCI_READ_4(sc, PEX_UNC_ERR_STAT); 3426 if ((v32 & PEX_UNSUP_REQ) != 0) { 3427 /* Ignore unsupported request error. */ 3428 device_printf(sc->msk_dev, 3429 "Uncorrectable PCI Express error\n"); 3430 } 3431 if ((v32 & (PEX_FATAL_ERRORS | PEX_POIS_TLP)) != 0) { 3432 int i; 3433 3434 /* Get TLP header form Log Registers. */ 3435 for (i = 0; i < 4; i++) 3436 tlphead[i] = CSR_PCI_READ_4(sc, 3437 PEX_HEADER_LOG + i * 4); 3438 /* Check for vendor defined broadcast message. */ 3439 if (!(tlphead[0] == 0x73004001 && tlphead[1] == 0x7f)) { 3440 sc->msk_intrhwemask &= ~Y2_IS_PCI_EXP; 3441 CSR_WRITE_4(sc, B0_HWE_IMSK, 3442 sc->msk_intrhwemask); 3443 CSR_READ_4(sc, B0_HWE_IMSK); 3444 } 3445 } 3446 /* Clear the interrupt. */ 3447 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON); 3448 CSR_PCI_WRITE_4(sc, PEX_UNC_ERR_STAT, 0xffffffff); 3449 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 3450 } 3451 3452 if ((status & Y2_HWE_L1_MASK) != 0 && sc->msk_if[MSK_PORT_A] != NULL) 3453 msk_handle_hwerr(sc->msk_if[MSK_PORT_A], status); 3454 if ((status & Y2_HWE_L2_MASK) != 0 && sc->msk_if[MSK_PORT_B] != NULL) 3455 msk_handle_hwerr(sc->msk_if[MSK_PORT_B], status >> 8); 3456 } 3457 3458 static __inline void 3459 msk_rxput(struct msk_if_softc *sc_if) 3460 { 3461 struct msk_softc *sc; 3462 3463 sc = sc_if->msk_softc; 3464 if (sc_if->msk_framesize > (MCLBYTES - MSK_RX_BUF_ALIGN)) 3465 bus_dmamap_sync( 3466 sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 3467 sc_if->msk_cdata.msk_jumbo_rx_ring_map, 3468 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3469 else 3470 bus_dmamap_sync( 3471 sc_if->msk_cdata.msk_rx_ring_tag, 3472 sc_if->msk_cdata.msk_rx_ring_map, 3473 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3474 CSR_WRITE_2(sc, Y2_PREF_Q_ADDR(sc_if->msk_rxq, 3475 PREF_UNIT_PUT_IDX_REG), sc_if->msk_cdata.msk_rx_prod); 3476 } 3477 3478 static int 3479 msk_handle_events(struct msk_softc *sc) 3480 { 3481 struct msk_if_softc *sc_if; 3482 int rxput[2]; 3483 struct msk_stat_desc *sd; 3484 uint32_t control, status; 3485 int cons, len, port, rxprog; 3486 3487 if (sc->msk_stat_cons == CSR_READ_2(sc, STAT_PUT_IDX)) 3488 return (0); 3489 3490 /* Sync status LEs. */ 3491 bus_dmamap_sync(sc->msk_stat_tag, sc->msk_stat_map, 3492 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3493 3494 rxput[MSK_PORT_A] = rxput[MSK_PORT_B] = 0; 3495 rxprog = 0; 3496 cons = sc->msk_stat_cons; 3497 for (;;) { 3498 sd = &sc->msk_stat_ring[cons]; 3499 control = le32toh(sd->msk_control); 3500 if ((control & HW_OWNER) == 0) 3501 break; 3502 control &= ~HW_OWNER; 3503 sd->msk_control = htole32(control); 3504 status = le32toh(sd->msk_status); 3505 len = control & STLE_LEN_MASK; 3506 port = (control >> 16) & 0x01; 3507 sc_if = sc->msk_if[port]; 3508 if (sc_if == NULL) { 3509 device_printf(sc->msk_dev, "invalid port opcode " 3510 "0x%08x\n", control & STLE_OP_MASK); 3511 continue; 3512 } 3513 3514 switch (control & STLE_OP_MASK) { 3515 case OP_RXVLAN: 3516 sc_if->msk_vtag = ntohs(len); 3517 break; 3518 case OP_RXCHKSVLAN: 3519 sc_if->msk_vtag = ntohs(len); 3520 /* FALLTHROUGH */ 3521 case OP_RXCHKS: 3522 sc_if->msk_csum = status; 3523 break; 3524 case OP_RXSTAT: 3525 if (!(sc_if->msk_ifp->if_drv_flags & IFF_DRV_RUNNING)) 3526 break; 3527 if (sc_if->msk_framesize > 3528 (MCLBYTES - MSK_RX_BUF_ALIGN)) 3529 msk_jumbo_rxeof(sc_if, status, control, len); 3530 else 3531 msk_rxeof(sc_if, status, control, len); 3532 rxprog++; 3533 /* 3534 * Because there is no way to sync single Rx LE 3535 * put the DMA sync operation off until the end of 3536 * event processing. 3537 */ 3538 rxput[port]++; 3539 /* Update prefetch unit if we've passed water mark. */ 3540 if (rxput[port] >= sc_if->msk_cdata.msk_rx_putwm) { 3541 msk_rxput(sc_if); 3542 rxput[port] = 0; 3543 } 3544 break; 3545 case OP_TXINDEXLE: 3546 if (sc->msk_if[MSK_PORT_A] != NULL) 3547 msk_txeof(sc->msk_if[MSK_PORT_A], 3548 status & STLE_TXA1_MSKL); 3549 if (sc->msk_if[MSK_PORT_B] != NULL) 3550 msk_txeof(sc->msk_if[MSK_PORT_B], 3551 ((status & STLE_TXA2_MSKL) >> 3552 STLE_TXA2_SHIFTL) | 3553 ((len & STLE_TXA2_MSKH) << 3554 STLE_TXA2_SHIFTH)); 3555 break; 3556 default: 3557 device_printf(sc->msk_dev, "unhandled opcode 0x%08x\n", 3558 control & STLE_OP_MASK); 3559 break; 3560 } 3561 MSK_INC(cons, MSK_STAT_RING_CNT); 3562 if (rxprog > sc->msk_process_limit) 3563 break; 3564 } 3565 3566 sc->msk_stat_cons = cons; 3567 bus_dmamap_sync(sc->msk_stat_tag, sc->msk_stat_map, 3568 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3569 3570 if (rxput[MSK_PORT_A] > 0) 3571 msk_rxput(sc->msk_if[MSK_PORT_A]); 3572 if (rxput[MSK_PORT_B] > 0) 3573 msk_rxput(sc->msk_if[MSK_PORT_B]); 3574 3575 return (sc->msk_stat_cons != CSR_READ_2(sc, STAT_PUT_IDX)); 3576 } 3577 3578 static void 3579 msk_intr(void *xsc) 3580 { 3581 struct msk_softc *sc; 3582 struct msk_if_softc *sc_if0, *sc_if1; 3583 struct ifnet *ifp0, *ifp1; 3584 uint32_t status; 3585 int domore; 3586 3587 sc = xsc; 3588 MSK_LOCK(sc); 3589 3590 /* Reading B0_Y2_SP_ISRC2 masks further interrupts. */ 3591 status = CSR_READ_4(sc, B0_Y2_SP_ISRC2); 3592 if (status == 0 || status == 0xffffffff || 3593 (sc->msk_pflags & MSK_FLAG_SUSPEND) != 0 || 3594 (status & sc->msk_intrmask) == 0) { 3595 CSR_WRITE_4(sc, B0_Y2_SP_ICR, 2); 3596 MSK_UNLOCK(sc); 3597 return; 3598 } 3599 3600 sc_if0 = sc->msk_if[MSK_PORT_A]; 3601 sc_if1 = sc->msk_if[MSK_PORT_B]; 3602 ifp0 = ifp1 = NULL; 3603 if (sc_if0 != NULL) 3604 ifp0 = sc_if0->msk_ifp; 3605 if (sc_if1 != NULL) 3606 ifp1 = sc_if1->msk_ifp; 3607 3608 if ((status & Y2_IS_IRQ_PHY1) != 0 && sc_if0 != NULL) 3609 msk_intr_phy(sc_if0); 3610 if ((status & Y2_IS_IRQ_PHY2) != 0 && sc_if1 != NULL) 3611 msk_intr_phy(sc_if1); 3612 if ((status & Y2_IS_IRQ_MAC1) != 0 && sc_if0 != NULL) 3613 msk_intr_gmac(sc_if0); 3614 if ((status & Y2_IS_IRQ_MAC2) != 0 && sc_if1 != NULL) 3615 msk_intr_gmac(sc_if1); 3616 if ((status & (Y2_IS_CHK_RX1 | Y2_IS_CHK_RX2)) != 0) { 3617 device_printf(sc->msk_dev, "Rx descriptor error\n"); 3618 sc->msk_intrmask &= ~(Y2_IS_CHK_RX1 | Y2_IS_CHK_RX2); 3619 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask); 3620 CSR_READ_4(sc, B0_IMSK); 3621 } 3622 if ((status & (Y2_IS_CHK_TXA1 | Y2_IS_CHK_TXA2)) != 0) { 3623 device_printf(sc->msk_dev, "Tx descriptor error\n"); 3624 sc->msk_intrmask &= ~(Y2_IS_CHK_TXA1 | Y2_IS_CHK_TXA2); 3625 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask); 3626 CSR_READ_4(sc, B0_IMSK); 3627 } 3628 if ((status & Y2_IS_HW_ERR) != 0) 3629 msk_intr_hwerr(sc); 3630 3631 domore = msk_handle_events(sc); 3632 if ((status & Y2_IS_STAT_BMU) != 0 && domore == 0) 3633 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_CLR_IRQ); 3634 3635 /* Reenable interrupts. */ 3636 CSR_WRITE_4(sc, B0_Y2_SP_ICR, 2); 3637 3638 if (ifp0 != NULL && (ifp0->if_drv_flags & IFF_DRV_RUNNING) != 0 && 3639 !IFQ_DRV_IS_EMPTY(&ifp0->if_snd)) 3640 msk_start_locked(ifp0); 3641 if (ifp1 != NULL && (ifp1->if_drv_flags & IFF_DRV_RUNNING) != 0 && 3642 !IFQ_DRV_IS_EMPTY(&ifp1->if_snd)) 3643 msk_start_locked(ifp1); 3644 3645 MSK_UNLOCK(sc); 3646 } 3647 3648 static void 3649 msk_set_tx_stfwd(struct msk_if_softc *sc_if) 3650 { 3651 struct msk_softc *sc; 3652 struct ifnet *ifp; 3653 3654 ifp = sc_if->msk_ifp; 3655 sc = sc_if->msk_softc; 3656 switch (sc->msk_hw_id) { 3657 case CHIP_ID_YUKON_EX: 3658 if (sc->msk_hw_rev == CHIP_REV_YU_EX_A0) 3659 goto yukon_ex_workaround; 3660 if (ifp->if_mtu > ETHERMTU) 3661 CSR_WRITE_4(sc, 3662 MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 3663 TX_JUMBO_ENA | TX_STFW_ENA); 3664 else 3665 CSR_WRITE_4(sc, 3666 MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 3667 TX_JUMBO_DIS | TX_STFW_ENA); 3668 break; 3669 default: 3670 yukon_ex_workaround: 3671 if (ifp->if_mtu > ETHERMTU) { 3672 /* Set Tx GMAC FIFO Almost Empty Threshold. */ 3673 CSR_WRITE_4(sc, 3674 MR_ADDR(sc_if->msk_port, TX_GMF_AE_THR), 3675 MSK_ECU_JUMBO_WM << 16 | MSK_ECU_AE_THR); 3676 /* Disable Store & Forward mode for Tx. */ 3677 CSR_WRITE_4(sc, 3678 MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 3679 TX_JUMBO_ENA | TX_STFW_DIS); 3680 } else { 3681 /* Enable Store & Forward mode for Tx. */ 3682 CSR_WRITE_4(sc, 3683 MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 3684 TX_JUMBO_DIS | TX_STFW_ENA); 3685 } 3686 break; 3687 } 3688 } 3689 3690 static void 3691 msk_init(void *xsc) 3692 { 3693 struct msk_if_softc *sc_if = xsc; 3694 3695 MSK_IF_LOCK(sc_if); 3696 msk_init_locked(sc_if); 3697 MSK_IF_UNLOCK(sc_if); 3698 } 3699 3700 static void 3701 msk_init_locked(struct msk_if_softc *sc_if) 3702 { 3703 struct msk_softc *sc; 3704 struct ifnet *ifp; 3705 struct mii_data *mii; 3706 uint8_t *eaddr; 3707 uint16_t gmac; 3708 uint32_t reg; 3709 int error; 3710 3711 MSK_IF_LOCK_ASSERT(sc_if); 3712 3713 ifp = sc_if->msk_ifp; 3714 sc = sc_if->msk_softc; 3715 mii = device_get_softc(sc_if->msk_miibus); 3716 3717 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 3718 return; 3719 3720 error = 0; 3721 /* Cancel pending I/O and free all Rx/Tx buffers. */ 3722 msk_stop(sc_if); 3723 3724 if (ifp->if_mtu < ETHERMTU) 3725 sc_if->msk_framesize = ETHERMTU; 3726 else 3727 sc_if->msk_framesize = ifp->if_mtu; 3728 sc_if->msk_framesize += ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 3729 if (ifp->if_mtu > ETHERMTU && 3730 (sc_if->msk_flags & MSK_FLAG_JUMBO_NOCSUM) != 0) { 3731 ifp->if_hwassist &= ~(MSK_CSUM_FEATURES | CSUM_TSO); 3732 ifp->if_capenable &= ~(IFCAP_TSO4 | IFCAP_TXCSUM); 3733 } 3734 3735 /* GMAC Control reset. */ 3736 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_RST_SET); 3737 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_RST_CLR); 3738 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_F_LOOPB_OFF); 3739 if (sc->msk_hw_id == CHIP_ID_YUKON_EX) 3740 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), 3741 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON | 3742 GMC_BYP_RETR_ON); 3743 3744 /* 3745 * Initialize GMAC first such that speed/duplex/flow-control 3746 * parameters are renegotiated when interface is brought up. 3747 */ 3748 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, 0); 3749 3750 /* Dummy read the Interrupt Source Register. */ 3751 CSR_READ_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_SRC)); 3752 3753 /* Clear MIB stats. */ 3754 msk_stats_clear(sc_if); 3755 3756 /* Disable FCS. */ 3757 GMAC_WRITE_2(sc, sc_if->msk_port, GM_RX_CTRL, GM_RXCR_CRC_DIS); 3758 3759 /* Setup Transmit Control Register. */ 3760 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF)); 3761 3762 /* Setup Transmit Flow Control Register. */ 3763 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_FLOW_CTRL, 0xffff); 3764 3765 /* Setup Transmit Parameter Register. */ 3766 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_PARAM, 3767 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) | TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) | 3768 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) | TX_BACK_OFF_LIM(TX_BOF_LIM_DEF)); 3769 3770 gmac = DATA_BLIND_VAL(DATA_BLIND_DEF) | 3771 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF); 3772 3773 if (ifp->if_mtu > ETHERMTU) 3774 gmac |= GM_SMOD_JUMBO_ENA; 3775 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SERIAL_MODE, gmac); 3776 3777 /* Set station address. */ 3778 eaddr = IF_LLADDR(ifp); 3779 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_1L, 3780 eaddr[0] | (eaddr[1] << 8)); 3781 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_1M, 3782 eaddr[2] | (eaddr[3] << 8)); 3783 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_1H, 3784 eaddr[4] | (eaddr[5] << 8)); 3785 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_2L, 3786 eaddr[0] | (eaddr[1] << 8)); 3787 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_2M, 3788 eaddr[2] | (eaddr[3] << 8)); 3789 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_2H, 3790 eaddr[4] | (eaddr[5] << 8)); 3791 3792 /* Disable interrupts for counter overflows. */ 3793 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_IRQ_MSK, 0); 3794 GMAC_WRITE_2(sc, sc_if->msk_port, GM_RX_IRQ_MSK, 0); 3795 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TR_IRQ_MSK, 0); 3796 3797 /* Configure Rx MAC FIFO. */ 3798 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), GMF_RST_SET); 3799 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), GMF_RST_CLR); 3800 reg = GMF_OPER_ON | GMF_RX_F_FL_ON; 3801 if (sc->msk_hw_id == CHIP_ID_YUKON_FE_P || 3802 sc->msk_hw_id == CHIP_ID_YUKON_EX) 3803 reg |= GMF_RX_OVER_ON; 3804 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), reg); 3805 3806 /* Set receive filter. */ 3807 msk_rxfilter(sc_if); 3808 3809 if (sc->msk_hw_id == CHIP_ID_YUKON_XL) { 3810 /* Clear flush mask - HW bug. */ 3811 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_FL_MSK), 0); 3812 } else { 3813 /* Flush Rx MAC FIFO on any flow control or error. */ 3814 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_FL_MSK), 3815 GMR_FS_ANY_ERR); 3816 } 3817 3818 /* 3819 * Set Rx FIFO flush threshold to 64 bytes + 1 FIFO word 3820 * due to hardware hang on receipt of pause frames. 3821 */ 3822 reg = RX_GMF_FL_THR_DEF + 1; 3823 /* Another magic for Yukon FE+ - From Linux. */ 3824 if (sc->msk_hw_id == CHIP_ID_YUKON_FE_P && 3825 sc->msk_hw_rev == CHIP_REV_YU_FE_P_A0) 3826 reg = 0x178; 3827 CSR_WRITE_2(sc, MR_ADDR(sc_if->msk_port, RX_GMF_FL_THR), reg); 3828 3829 /* Configure Tx MAC FIFO. */ 3830 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_RST_SET); 3831 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_RST_CLR); 3832 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_OPER_ON); 3833 3834 /* Configure hardware VLAN tag insertion/stripping. */ 3835 msk_setvlan(sc_if, ifp); 3836 3837 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) == 0) { 3838 /* Set Rx Pause threshold. */ 3839 CSR_WRITE_2(sc, MR_ADDR(sc_if->msk_port, RX_GMF_LP_THR), 3840 MSK_ECU_LLPP); 3841 CSR_WRITE_2(sc, MR_ADDR(sc_if->msk_port, RX_GMF_UP_THR), 3842 MSK_ECU_ULPP); 3843 /* Configure store-and-forward for Tx. */ 3844 msk_set_tx_stfwd(sc_if); 3845 } 3846 3847 if (sc->msk_hw_id == CHIP_ID_YUKON_FE_P && 3848 sc->msk_hw_rev == CHIP_REV_YU_FE_P_A0) { 3849 /* Disable dynamic watermark - from Linux. */ 3850 reg = CSR_READ_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_EA)); 3851 reg &= ~0x03; 3852 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_EA), reg); 3853 } 3854 3855 /* 3856 * Disable Force Sync bit and Alloc bit in Tx RAM interface 3857 * arbiter as we don't use Sync Tx queue. 3858 */ 3859 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, TXA_CTRL), 3860 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC); 3861 /* Enable the RAM Interface Arbiter. */ 3862 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, TXA_CTRL), TXA_ENA_ARB); 3863 3864 /* Setup RAM buffer. */ 3865 msk_set_rambuffer(sc_if); 3866 3867 /* Disable Tx sync Queue. */ 3868 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txsq, RB_CTRL), RB_RST_SET); 3869 3870 /* Setup Tx Queue Bus Memory Interface. */ 3871 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_CLR_RESET); 3872 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_OPER_INIT); 3873 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_FIFO_OP_ON); 3874 CSR_WRITE_2(sc, Q_ADDR(sc_if->msk_txq, Q_WM), MSK_BMU_TX_WM); 3875 switch (sc->msk_hw_id) { 3876 case CHIP_ID_YUKON_EC_U: 3877 if (sc->msk_hw_rev == CHIP_REV_YU_EC_U_A0) { 3878 /* Fix for Yukon-EC Ultra: set BMU FIFO level */ 3879 CSR_WRITE_2(sc, Q_ADDR(sc_if->msk_txq, Q_AL), 3880 MSK_ECU_TXFF_LEV); 3881 } 3882 break; 3883 case CHIP_ID_YUKON_EX: 3884 /* 3885 * Yukon Extreme seems to have silicon bug for 3886 * automatic Tx checksum calculation capability. 3887 */ 3888 if (sc->msk_hw_rev == CHIP_REV_YU_EX_B0) 3889 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_F), 3890 F_TX_CHK_AUTO_OFF); 3891 break; 3892 } 3893 3894 /* Setup Rx Queue Bus Memory Interface. */ 3895 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_CLR_RESET); 3896 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_OPER_INIT); 3897 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_FIFO_OP_ON); 3898 CSR_WRITE_2(sc, Q_ADDR(sc_if->msk_rxq, Q_WM), MSK_BMU_RX_WM); 3899 if (sc->msk_hw_id == CHIP_ID_YUKON_EC_U && 3900 sc->msk_hw_rev >= CHIP_REV_YU_EC_U_A1) { 3901 /* MAC Rx RAM Read is controlled by hardware. */ 3902 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_F), F_M_RX_RAM_DIS); 3903 } 3904 3905 msk_set_prefetch(sc, sc_if->msk_txq, 3906 sc_if->msk_rdata.msk_tx_ring_paddr, MSK_TX_RING_CNT - 1); 3907 msk_init_tx_ring(sc_if); 3908 3909 /* Disable Rx checksum offload and RSS hash. */ 3910 reg = BMU_DIS_RX_RSS_HASH; 3911 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0 && 3912 (ifp->if_capenable & IFCAP_RXCSUM) != 0) 3913 reg |= BMU_ENA_RX_CHKSUM; 3914 else 3915 reg |= BMU_DIS_RX_CHKSUM; 3916 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), reg); 3917 if (sc_if->msk_framesize > (MCLBYTES - MSK_RX_BUF_ALIGN)) { 3918 msk_set_prefetch(sc, sc_if->msk_rxq, 3919 sc_if->msk_rdata.msk_jumbo_rx_ring_paddr, 3920 MSK_JUMBO_RX_RING_CNT - 1); 3921 error = msk_init_jumbo_rx_ring(sc_if); 3922 } else { 3923 msk_set_prefetch(sc, sc_if->msk_rxq, 3924 sc_if->msk_rdata.msk_rx_ring_paddr, 3925 MSK_RX_RING_CNT - 1); 3926 error = msk_init_rx_ring(sc_if); 3927 } 3928 if (error != 0) { 3929 device_printf(sc_if->msk_if_dev, 3930 "initialization failed: no memory for Rx buffers\n"); 3931 msk_stop(sc_if); 3932 return; 3933 } 3934 if (sc->msk_hw_id == CHIP_ID_YUKON_EX) { 3935 /* Disable flushing of non-ASF packets. */ 3936 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), 3937 GMF_RX_MACSEC_FLUSH_OFF); 3938 } 3939 3940 /* Configure interrupt handling. */ 3941 if (sc_if->msk_port == MSK_PORT_A) { 3942 sc->msk_intrmask |= Y2_IS_PORT_A; 3943 sc->msk_intrhwemask |= Y2_HWE_L1_MASK; 3944 } else { 3945 sc->msk_intrmask |= Y2_IS_PORT_B; 3946 sc->msk_intrhwemask |= Y2_HWE_L2_MASK; 3947 } 3948 /* Configure IRQ moderation mask. */ 3949 CSR_WRITE_4(sc, B2_IRQM_MSK, sc->msk_intrmask); 3950 if (sc->msk_int_holdoff > 0) { 3951 /* Configure initial IRQ moderation timer value. */ 3952 CSR_WRITE_4(sc, B2_IRQM_INI, 3953 MSK_USECS(sc, sc->msk_int_holdoff)); 3954 CSR_WRITE_4(sc, B2_IRQM_VAL, 3955 MSK_USECS(sc, sc->msk_int_holdoff)); 3956 /* Start IRQ moderation. */ 3957 CSR_WRITE_1(sc, B2_IRQM_CTRL, TIM_START); 3958 } 3959 CSR_WRITE_4(sc, B0_HWE_IMSK, sc->msk_intrhwemask); 3960 CSR_READ_4(sc, B0_HWE_IMSK); 3961 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask); 3962 CSR_READ_4(sc, B0_IMSK); 3963 3964 sc_if->msk_flags &= ~MSK_FLAG_LINK; 3965 mii_mediachg(mii); 3966 3967 ifp->if_drv_flags |= IFF_DRV_RUNNING; 3968 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3969 3970 callout_reset(&sc_if->msk_tick_ch, hz, msk_tick, sc_if); 3971 } 3972 3973 static void 3974 msk_set_rambuffer(struct msk_if_softc *sc_if) 3975 { 3976 struct msk_softc *sc; 3977 int ltpp, utpp; 3978 3979 sc = sc_if->msk_softc; 3980 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) == 0) 3981 return; 3982 3983 /* Setup Rx Queue. */ 3984 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_RST_CLR); 3985 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_START), 3986 sc->msk_rxqstart[sc_if->msk_port] / 8); 3987 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_END), 3988 sc->msk_rxqend[sc_if->msk_port] / 8); 3989 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_WP), 3990 sc->msk_rxqstart[sc_if->msk_port] / 8); 3991 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_RP), 3992 sc->msk_rxqstart[sc_if->msk_port] / 8); 3993 3994 utpp = (sc->msk_rxqend[sc_if->msk_port] + 1 - 3995 sc->msk_rxqstart[sc_if->msk_port] - MSK_RB_ULPP) / 8; 3996 ltpp = (sc->msk_rxqend[sc_if->msk_port] + 1 - 3997 sc->msk_rxqstart[sc_if->msk_port] - MSK_RB_LLPP_B) / 8; 3998 if (sc->msk_rxqsize < MSK_MIN_RXQ_SIZE) 3999 ltpp += (MSK_RB_LLPP_B - MSK_RB_LLPP_S) / 8; 4000 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_RX_UTPP), utpp); 4001 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_RX_LTPP), ltpp); 4002 /* Set Rx priority(RB_RX_UTHP/RB_RX_LTHP) thresholds? */ 4003 4004 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_ENA_OP_MD); 4005 CSR_READ_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL)); 4006 4007 /* Setup Tx Queue. */ 4008 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_RST_CLR); 4009 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_START), 4010 sc->msk_txqstart[sc_if->msk_port] / 8); 4011 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_END), 4012 sc->msk_txqend[sc_if->msk_port] / 8); 4013 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_WP), 4014 sc->msk_txqstart[sc_if->msk_port] / 8); 4015 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_RP), 4016 sc->msk_txqstart[sc_if->msk_port] / 8); 4017 /* Enable Store & Forward for Tx side. */ 4018 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_ENA_STFWD); 4019 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_ENA_OP_MD); 4020 CSR_READ_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL)); 4021 } 4022 4023 static void 4024 msk_set_prefetch(struct msk_softc *sc, int qaddr, bus_addr_t addr, 4025 uint32_t count) 4026 { 4027 4028 /* Reset the prefetch unit. */ 4029 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG), 4030 PREF_UNIT_RST_SET); 4031 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG), 4032 PREF_UNIT_RST_CLR); 4033 /* Set LE base address. */ 4034 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_ADDR_LOW_REG), 4035 MSK_ADDR_LO(addr)); 4036 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_ADDR_HI_REG), 4037 MSK_ADDR_HI(addr)); 4038 /* Set the list last index. */ 4039 CSR_WRITE_2(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_LAST_IDX_REG), 4040 count); 4041 /* Turn on prefetch unit. */ 4042 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG), 4043 PREF_UNIT_OP_ON); 4044 /* Dummy read to ensure write. */ 4045 CSR_READ_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG)); 4046 } 4047 4048 static void 4049 msk_stop(struct msk_if_softc *sc_if) 4050 { 4051 struct msk_softc *sc; 4052 struct msk_txdesc *txd; 4053 struct msk_rxdesc *rxd; 4054 struct msk_rxdesc *jrxd; 4055 struct ifnet *ifp; 4056 uint32_t val; 4057 int i; 4058 4059 MSK_IF_LOCK_ASSERT(sc_if); 4060 sc = sc_if->msk_softc; 4061 ifp = sc_if->msk_ifp; 4062 4063 callout_stop(&sc_if->msk_tick_ch); 4064 sc_if->msk_watchdog_timer = 0; 4065 4066 /* Disable interrupts. */ 4067 if (sc_if->msk_port == MSK_PORT_A) { 4068 sc->msk_intrmask &= ~Y2_IS_PORT_A; 4069 sc->msk_intrhwemask &= ~Y2_HWE_L1_MASK; 4070 } else { 4071 sc->msk_intrmask &= ~Y2_IS_PORT_B; 4072 sc->msk_intrhwemask &= ~Y2_HWE_L2_MASK; 4073 } 4074 CSR_WRITE_4(sc, B0_HWE_IMSK, sc->msk_intrhwemask); 4075 CSR_READ_4(sc, B0_HWE_IMSK); 4076 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask); 4077 CSR_READ_4(sc, B0_IMSK); 4078 4079 /* Disable Tx/Rx MAC. */ 4080 val = GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL); 4081 val &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA); 4082 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, val); 4083 /* Read again to ensure writing. */ 4084 GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL); 4085 /* Update stats and clear counters. */ 4086 msk_stats_update(sc_if); 4087 4088 /* Stop Tx BMU. */ 4089 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_STOP); 4090 val = CSR_READ_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR)); 4091 for (i = 0; i < MSK_TIMEOUT; i++) { 4092 if ((val & (BMU_STOP | BMU_IDLE)) == 0) { 4093 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), 4094 BMU_STOP); 4095 val = CSR_READ_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR)); 4096 } else 4097 break; 4098 DELAY(1); 4099 } 4100 if (i == MSK_TIMEOUT) 4101 device_printf(sc_if->msk_if_dev, "Tx BMU stop failed\n"); 4102 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), 4103 RB_RST_SET | RB_DIS_OP_MD); 4104 4105 /* Disable all GMAC interrupt. */ 4106 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_MSK), 0); 4107 /* Disable PHY interrupt. */ 4108 msk_phy_writereg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_MASK, 0); 4109 4110 /* Disable the RAM Interface Arbiter. */ 4111 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, TXA_CTRL), TXA_DIS_ARB); 4112 4113 /* Reset the PCI FIFO of the async Tx queue */ 4114 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), 4115 BMU_RST_SET | BMU_FIFO_RST); 4116 4117 /* Reset the Tx prefetch units. */ 4118 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(sc_if->msk_txq, PREF_UNIT_CTRL_REG), 4119 PREF_UNIT_RST_SET); 4120 4121 /* Reset the RAM Buffer async Tx queue. */ 4122 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_RST_SET); 4123 4124 /* Reset Tx MAC FIFO. */ 4125 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_RST_SET); 4126 /* Set Pause Off. */ 4127 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_PAUSE_OFF); 4128 4129 /* 4130 * The Rx Stop command will not work for Yukon-2 if the BMU does not 4131 * reach the end of packet and since we can't make sure that we have 4132 * incoming data, we must reset the BMU while it is not during a DMA 4133 * transfer. Since it is possible that the Rx path is still active, 4134 * the Rx RAM buffer will be stopped first, so any possible incoming 4135 * data will not trigger a DMA. After the RAM buffer is stopped, the 4136 * BMU is polled until any DMA in progress is ended and only then it 4137 * will be reset. 4138 */ 4139 4140 /* Disable the RAM Buffer receive queue. */ 4141 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_DIS_OP_MD); 4142 for (i = 0; i < MSK_TIMEOUT; i++) { 4143 if (CSR_READ_1(sc, RB_ADDR(sc_if->msk_rxq, Q_RSL)) == 4144 CSR_READ_1(sc, RB_ADDR(sc_if->msk_rxq, Q_RL))) 4145 break; 4146 DELAY(1); 4147 } 4148 if (i == MSK_TIMEOUT) 4149 device_printf(sc_if->msk_if_dev, "Rx BMU stop failed\n"); 4150 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), 4151 BMU_RST_SET | BMU_FIFO_RST); 4152 /* Reset the Rx prefetch unit. */ 4153 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_CTRL_REG), 4154 PREF_UNIT_RST_SET); 4155 /* Reset the RAM Buffer receive queue. */ 4156 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_RST_SET); 4157 /* Reset Rx MAC FIFO. */ 4158 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), GMF_RST_SET); 4159 4160 /* Free Rx and Tx mbufs still in the queues. */ 4161 for (i = 0; i < MSK_RX_RING_CNT; i++) { 4162 rxd = &sc_if->msk_cdata.msk_rxdesc[i]; 4163 if (rxd->rx_m != NULL) { 4164 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_tag, 4165 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 4166 bus_dmamap_unload(sc_if->msk_cdata.msk_rx_tag, 4167 rxd->rx_dmamap); 4168 m_freem(rxd->rx_m); 4169 rxd->rx_m = NULL; 4170 } 4171 } 4172 for (i = 0; i < MSK_JUMBO_RX_RING_CNT; i++) { 4173 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[i]; 4174 if (jrxd->rx_m != NULL) { 4175 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_tag, 4176 jrxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 4177 bus_dmamap_unload(sc_if->msk_cdata.msk_jumbo_rx_tag, 4178 jrxd->rx_dmamap); 4179 m_freem(jrxd->rx_m); 4180 jrxd->rx_m = NULL; 4181 } 4182 } 4183 for (i = 0; i < MSK_TX_RING_CNT; i++) { 4184 txd = &sc_if->msk_cdata.msk_txdesc[i]; 4185 if (txd->tx_m != NULL) { 4186 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_tag, 4187 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 4188 bus_dmamap_unload(sc_if->msk_cdata.msk_tx_tag, 4189 txd->tx_dmamap); 4190 m_freem(txd->tx_m); 4191 txd->tx_m = NULL; 4192 } 4193 } 4194 4195 /* 4196 * Mark the interface down. 4197 */ 4198 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 4199 sc_if->msk_flags &= ~MSK_FLAG_LINK; 4200 } 4201 4202 /* 4203 * When GM_PAR_MIB_CLR bit of GM_PHY_ADDR is set, reading lower 4204 * counter clears high 16 bits of the counter such that accessing 4205 * lower 16 bits should be the last operation. 4206 */ 4207 #define MSK_READ_MIB32(x, y) \ 4208 (((uint32_t)GMAC_READ_2(sc, x, (y) + 4)) << 16) + \ 4209 (uint32_t)GMAC_READ_2(sc, x, y) 4210 #define MSK_READ_MIB64(x, y) \ 4211 (((uint64_t)MSK_READ_MIB32(x, (y) + 8)) << 32) + \ 4212 (uint64_t)MSK_READ_MIB32(x, y) 4213 4214 static void 4215 msk_stats_clear(struct msk_if_softc *sc_if) 4216 { 4217 struct msk_softc *sc; 4218 uint32_t reg; 4219 uint16_t gmac; 4220 int i; 4221 4222 MSK_IF_LOCK_ASSERT(sc_if); 4223 4224 sc = sc_if->msk_softc; 4225 /* Set MIB Clear Counter Mode. */ 4226 gmac = GMAC_READ_2(sc, sc_if->msk_port, GM_PHY_ADDR); 4227 GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac | GM_PAR_MIB_CLR); 4228 /* Read all MIB Counters with Clear Mode set. */ 4229 for (i = GM_RXF_UC_OK; i <= GM_TXE_FIFO_UR; i += sizeof(uint32_t)) 4230 reg = MSK_READ_MIB32(sc_if->msk_port, i); 4231 /* Clear MIB Clear Counter Mode. */ 4232 gmac &= ~GM_PAR_MIB_CLR; 4233 GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac); 4234 } 4235 4236 static void 4237 msk_stats_update(struct msk_if_softc *sc_if) 4238 { 4239 struct msk_softc *sc; 4240 struct ifnet *ifp; 4241 struct msk_hw_stats *stats; 4242 uint16_t gmac; 4243 uint32_t reg; 4244 4245 MSK_IF_LOCK_ASSERT(sc_if); 4246 4247 ifp = sc_if->msk_ifp; 4248 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 4249 return; 4250 sc = sc_if->msk_softc; 4251 stats = &sc_if->msk_stats; 4252 /* Set MIB Clear Counter Mode. */ 4253 gmac = GMAC_READ_2(sc, sc_if->msk_port, GM_PHY_ADDR); 4254 GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac | GM_PAR_MIB_CLR); 4255 4256 /* Rx stats. */ 4257 stats->rx_ucast_frames += 4258 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_UC_OK); 4259 stats->rx_bcast_frames += 4260 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_BC_OK); 4261 stats->rx_pause_frames += 4262 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_MPAUSE); 4263 stats->rx_mcast_frames += 4264 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_MC_OK); 4265 stats->rx_crc_errs += 4266 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_FCS_ERR); 4267 reg = MSK_READ_MIB32(sc_if->msk_port, GM_RXF_SPARE1); 4268 stats->rx_good_octets += 4269 MSK_READ_MIB64(sc_if->msk_port, GM_RXO_OK_LO); 4270 stats->rx_bad_octets += 4271 MSK_READ_MIB64(sc_if->msk_port, GM_RXO_ERR_LO); 4272 stats->rx_runts += 4273 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_SHT); 4274 stats->rx_runt_errs += 4275 MSK_READ_MIB32(sc_if->msk_port, GM_RXE_FRAG); 4276 stats->rx_pkts_64 += 4277 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_64B); 4278 stats->rx_pkts_65_127 += 4279 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_127B); 4280 stats->rx_pkts_128_255 += 4281 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_255B); 4282 stats->rx_pkts_256_511 += 4283 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_511B); 4284 stats->rx_pkts_512_1023 += 4285 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_1023B); 4286 stats->rx_pkts_1024_1518 += 4287 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_1518B); 4288 stats->rx_pkts_1519_max += 4289 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_MAX_SZ); 4290 stats->rx_pkts_too_long += 4291 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_LNG_ERR); 4292 stats->rx_pkts_jabbers += 4293 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_JAB_PKT); 4294 reg = MSK_READ_MIB32(sc_if->msk_port, GM_RXF_SPARE2); 4295 stats->rx_fifo_oflows += 4296 MSK_READ_MIB32(sc_if->msk_port, GM_RXE_FIFO_OV); 4297 reg = MSK_READ_MIB32(sc_if->msk_port, GM_RXF_SPARE3); 4298 4299 /* Tx stats. */ 4300 stats->tx_ucast_frames += 4301 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_UC_OK); 4302 stats->tx_bcast_frames += 4303 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_BC_OK); 4304 stats->tx_pause_frames += 4305 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_MPAUSE); 4306 stats->tx_mcast_frames += 4307 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_MC_OK); 4308 stats->tx_octets += 4309 MSK_READ_MIB64(sc_if->msk_port, GM_TXO_OK_LO); 4310 stats->tx_pkts_64 += 4311 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_64B); 4312 stats->tx_pkts_65_127 += 4313 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_127B); 4314 stats->tx_pkts_128_255 += 4315 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_255B); 4316 stats->tx_pkts_256_511 += 4317 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_511B); 4318 stats->tx_pkts_512_1023 += 4319 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_1023B); 4320 stats->tx_pkts_1024_1518 += 4321 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_1518B); 4322 stats->tx_pkts_1519_max += 4323 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_MAX_SZ); 4324 reg = MSK_READ_MIB32(sc_if->msk_port, GM_TXF_SPARE1); 4325 stats->tx_colls += 4326 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_COL); 4327 stats->tx_late_colls += 4328 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_LAT_COL); 4329 stats->tx_excess_colls += 4330 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_ABO_COL); 4331 stats->tx_multi_colls += 4332 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_MUL_COL); 4333 stats->tx_single_colls += 4334 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_SNG_COL); 4335 stats->tx_underflows += 4336 MSK_READ_MIB32(sc_if->msk_port, GM_TXE_FIFO_UR); 4337 /* Clear MIB Clear Counter Mode. */ 4338 gmac &= ~GM_PAR_MIB_CLR; 4339 GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac); 4340 } 4341 4342 static int 4343 msk_sysctl_stat32(SYSCTL_HANDLER_ARGS) 4344 { 4345 struct msk_softc *sc; 4346 struct msk_if_softc *sc_if; 4347 uint32_t result, *stat; 4348 int off; 4349 4350 sc_if = (struct msk_if_softc *)arg1; 4351 sc = sc_if->msk_softc; 4352 off = arg2; 4353 stat = (uint32_t *)((uint8_t *)&sc_if->msk_stats + off); 4354 4355 MSK_IF_LOCK(sc_if); 4356 result = MSK_READ_MIB32(sc_if->msk_port, GM_MIB_CNT_BASE + off * 2); 4357 result += *stat; 4358 MSK_IF_UNLOCK(sc_if); 4359 4360 return (sysctl_handle_int(oidp, &result, 0, req)); 4361 } 4362 4363 static int 4364 msk_sysctl_stat64(SYSCTL_HANDLER_ARGS) 4365 { 4366 struct msk_softc *sc; 4367 struct msk_if_softc *sc_if; 4368 uint64_t result, *stat; 4369 int off; 4370 4371 sc_if = (struct msk_if_softc *)arg1; 4372 sc = sc_if->msk_softc; 4373 off = arg2; 4374 stat = (uint64_t *)((uint8_t *)&sc_if->msk_stats + off); 4375 4376 MSK_IF_LOCK(sc_if); 4377 result = MSK_READ_MIB64(sc_if->msk_port, GM_MIB_CNT_BASE + off * 2); 4378 result += *stat; 4379 MSK_IF_UNLOCK(sc_if); 4380 4381 return (sysctl_handle_64(oidp, &result, 0, req)); 4382 } 4383 4384 #undef MSK_READ_MIB32 4385 #undef MSK_READ_MIB64 4386 4387 #define MSK_SYSCTL_STAT32(sc, c, o, p, n, d) \ 4388 SYSCTL_ADD_PROC(c, p, OID_AUTO, o, CTLTYPE_UINT | CTLFLAG_RD, \ 4389 sc, offsetof(struct msk_hw_stats, n), msk_sysctl_stat32, \ 4390 "IU", d) 4391 #define MSK_SYSCTL_STAT64(sc, c, o, p, n, d) \ 4392 SYSCTL_ADD_PROC(c, p, OID_AUTO, o, CTLTYPE_U64 | CTLFLAG_RD, \ 4393 sc, offsetof(struct msk_hw_stats, n), msk_sysctl_stat64, \ 4394 "QU", d) 4395 4396 static void 4397 msk_sysctl_node(struct msk_if_softc *sc_if) 4398 { 4399 struct sysctl_ctx_list *ctx; 4400 struct sysctl_oid_list *child, *schild; 4401 struct sysctl_oid *tree; 4402 4403 ctx = device_get_sysctl_ctx(sc_if->msk_if_dev); 4404 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc_if->msk_if_dev)); 4405 4406 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD, 4407 NULL, "MSK Statistics"); 4408 schild = child = SYSCTL_CHILDREN(tree); 4409 tree = SYSCTL_ADD_NODE(ctx, schild, OID_AUTO, "rx", CTLFLAG_RD, 4410 NULL, "MSK RX Statistics"); 4411 child = SYSCTL_CHILDREN(tree); 4412 MSK_SYSCTL_STAT32(sc_if, ctx, "ucast_frames", 4413 child, rx_ucast_frames, "Good unicast frames"); 4414 MSK_SYSCTL_STAT32(sc_if, ctx, "bcast_frames", 4415 child, rx_bcast_frames, "Good broadcast frames"); 4416 MSK_SYSCTL_STAT32(sc_if, ctx, "pause_frames", 4417 child, rx_pause_frames, "Pause frames"); 4418 MSK_SYSCTL_STAT32(sc_if, ctx, "mcast_frames", 4419 child, rx_mcast_frames, "Multicast frames"); 4420 MSK_SYSCTL_STAT32(sc_if, ctx, "crc_errs", 4421 child, rx_crc_errs, "CRC errors"); 4422 MSK_SYSCTL_STAT64(sc_if, ctx, "good_octets", 4423 child, rx_good_octets, "Good octets"); 4424 MSK_SYSCTL_STAT64(sc_if, ctx, "bad_octets", 4425 child, rx_bad_octets, "Bad octets"); 4426 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_64", 4427 child, rx_pkts_64, "64 bytes frames"); 4428 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_65_127", 4429 child, rx_pkts_65_127, "65 to 127 bytes frames"); 4430 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_128_255", 4431 child, rx_pkts_128_255, "128 to 255 bytes frames"); 4432 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_256_511", 4433 child, rx_pkts_256_511, "256 to 511 bytes frames"); 4434 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_512_1023", 4435 child, rx_pkts_512_1023, "512 to 1023 bytes frames"); 4436 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_1024_1518", 4437 child, rx_pkts_1024_1518, "1024 to 1518 bytes frames"); 4438 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_1519_max", 4439 child, rx_pkts_1519_max, "1519 to max frames"); 4440 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_too_long", 4441 child, rx_pkts_too_long, "frames too long"); 4442 MSK_SYSCTL_STAT32(sc_if, ctx, "jabbers", 4443 child, rx_pkts_jabbers, "Jabber errors"); 4444 MSK_SYSCTL_STAT32(sc_if, ctx, "overflows", 4445 child, rx_fifo_oflows, "FIFO overflows"); 4446 4447 tree = SYSCTL_ADD_NODE(ctx, schild, OID_AUTO, "tx", CTLFLAG_RD, 4448 NULL, "MSK TX Statistics"); 4449 child = SYSCTL_CHILDREN(tree); 4450 MSK_SYSCTL_STAT32(sc_if, ctx, "ucast_frames", 4451 child, tx_ucast_frames, "Unicast frames"); 4452 MSK_SYSCTL_STAT32(sc_if, ctx, "bcast_frames", 4453 child, tx_bcast_frames, "Broadcast frames"); 4454 MSK_SYSCTL_STAT32(sc_if, ctx, "pause_frames", 4455 child, tx_pause_frames, "Pause frames"); 4456 MSK_SYSCTL_STAT32(sc_if, ctx, "mcast_frames", 4457 child, tx_mcast_frames, "Multicast frames"); 4458 MSK_SYSCTL_STAT64(sc_if, ctx, "octets", 4459 child, tx_octets, "Octets"); 4460 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_64", 4461 child, tx_pkts_64, "64 bytes frames"); 4462 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_65_127", 4463 child, tx_pkts_65_127, "65 to 127 bytes frames"); 4464 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_128_255", 4465 child, tx_pkts_128_255, "128 to 255 bytes frames"); 4466 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_256_511", 4467 child, tx_pkts_256_511, "256 to 511 bytes frames"); 4468 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_512_1023", 4469 child, tx_pkts_512_1023, "512 to 1023 bytes frames"); 4470 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_1024_1518", 4471 child, tx_pkts_1024_1518, "1024 to 1518 bytes frames"); 4472 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_1519_max", 4473 child, tx_pkts_1519_max, "1519 to max frames"); 4474 MSK_SYSCTL_STAT32(sc_if, ctx, "colls", 4475 child, tx_colls, "Collisions"); 4476 MSK_SYSCTL_STAT32(sc_if, ctx, "late_colls", 4477 child, tx_late_colls, "Late collisions"); 4478 MSK_SYSCTL_STAT32(sc_if, ctx, "excess_colls", 4479 child, tx_excess_colls, "Excessive collisions"); 4480 MSK_SYSCTL_STAT32(sc_if, ctx, "multi_colls", 4481 child, tx_multi_colls, "Multiple collisions"); 4482 MSK_SYSCTL_STAT32(sc_if, ctx, "single_colls", 4483 child, tx_single_colls, "Single collisions"); 4484 MSK_SYSCTL_STAT32(sc_if, ctx, "underflows", 4485 child, tx_underflows, "FIFO underflows"); 4486 } 4487 4488 #undef MSK_SYSCTL_STAT32 4489 #undef MSK_SYSCTL_STAT64 4490 4491 static int 4492 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 4493 { 4494 int error, value; 4495 4496 if (!arg1) 4497 return (EINVAL); 4498 value = *(int *)arg1; 4499 error = sysctl_handle_int(oidp, &value, 0, req); 4500 if (error || !req->newptr) 4501 return (error); 4502 if (value < low || value > high) 4503 return (EINVAL); 4504 *(int *)arg1 = value; 4505 4506 return (0); 4507 } 4508 4509 static int 4510 sysctl_hw_msk_proc_limit(SYSCTL_HANDLER_ARGS) 4511 { 4512 4513 return (sysctl_int_range(oidp, arg1, arg2, req, MSK_PROC_MIN, 4514 MSK_PROC_MAX)); 4515 } 4516