1 /****************************************************************************** 2 * 3 * Name : sky2.c 4 * Project: Gigabit Ethernet Driver for FreeBSD 5.x/6.x 5 * Version: $Revision: 1.23 $ 6 * Date : $Date: 2005/12/22 09:04:11 $ 7 * Purpose: Main driver source file 8 * 9 *****************************************************************************/ 10 11 /****************************************************************************** 12 * 13 * LICENSE: 14 * Copyright (C) Marvell International Ltd. and/or its affiliates 15 * 16 * The computer program files contained in this folder ("Files") 17 * are provided to you under the BSD-type license terms provided 18 * below, and any use of such Files and any derivative works 19 * thereof created by you shall be governed by the following terms 20 * and conditions: 21 * 22 * - Redistributions of source code must retain the above copyright 23 * notice, this list of conditions and the following disclaimer. 24 * - Redistributions in binary form must reproduce the above 25 * copyright notice, this list of conditions and the following 26 * disclaimer in the documentation and/or other materials provided 27 * with the distribution. 28 * - Neither the name of Marvell nor the names of its contributors 29 * may be used to endorse or promote products derived from this 30 * software without specific prior written permission. 31 * 32 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 33 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 34 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 35 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 36 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 37 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 38 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 39 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 40 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 41 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 42 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED 43 * OF THE POSSIBILITY OF SUCH DAMAGE. 44 * /LICENSE 45 * 46 *****************************************************************************/ 47 48 /*- 49 * Copyright (c) 1997, 1998, 1999, 2000 50 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 51 * 52 * Redistribution and use in source and binary forms, with or without 53 * modification, are permitted provided that the following conditions 54 * are met: 55 * 1. Redistributions of source code must retain the above copyright 56 * notice, this list of conditions and the following disclaimer. 57 * 2. Redistributions in binary form must reproduce the above copyright 58 * notice, this list of conditions and the following disclaimer in the 59 * documentation and/or other materials provided with the distribution. 60 * 3. All advertising materials mentioning features or use of this software 61 * must display the following acknowledgement: 62 * This product includes software developed by Bill Paul. 63 * 4. Neither the name of the author nor the names of any co-contributors 64 * may be used to endorse or promote products derived from this software 65 * without specific prior written permission. 66 * 67 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 68 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 69 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 70 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 71 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 72 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 73 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 74 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 75 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 76 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 77 * THE POSSIBILITY OF SUCH DAMAGE. 78 */ 79 /*- 80 * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu> 81 * 82 * Permission to use, copy, modify, and distribute this software for any 83 * purpose with or without fee is hereby granted, provided that the above 84 * copyright notice and this permission notice appear in all copies. 85 * 86 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 87 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 88 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 89 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 90 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 91 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 92 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 93 */ 94 95 /* 96 * Device driver for the Marvell Yukon II Ethernet controller. 97 * Due to lack of documentation, this driver is based on the code from 98 * sk(4) and Marvell's myk(4) driver for FreeBSD 5.x. 99 */ 100 101 #include <sys/cdefs.h> 102 __FBSDID("$FreeBSD$"); 103 104 #include <sys/param.h> 105 #include <sys/systm.h> 106 #include <sys/bus.h> 107 #include <sys/endian.h> 108 #include <sys/mbuf.h> 109 #include <sys/malloc.h> 110 #include <sys/kernel.h> 111 #include <sys/module.h> 112 #include <sys/socket.h> 113 #include <sys/sockio.h> 114 #include <sys/queue.h> 115 #include <sys/sysctl.h> 116 117 #include <net/bpf.h> 118 #include <net/ethernet.h> 119 #include <net/if.h> 120 #include <net/if_arp.h> 121 #include <net/if_dl.h> 122 #include <net/if_media.h> 123 #include <net/if_types.h> 124 #include <net/if_vlan_var.h> 125 126 #include <netinet/in.h> 127 #include <netinet/in_systm.h> 128 #include <netinet/ip.h> 129 #include <netinet/tcp.h> 130 #include <netinet/udp.h> 131 132 #include <machine/bus.h> 133 #include <machine/in_cksum.h> 134 #include <machine/resource.h> 135 #include <sys/rman.h> 136 137 #include <dev/mii/mii.h> 138 #include <dev/mii/miivar.h> 139 140 #include <dev/pci/pcireg.h> 141 #include <dev/pci/pcivar.h> 142 143 #include <dev/msk/if_mskreg.h> 144 145 MODULE_DEPEND(msk, pci, 1, 1, 1); 146 MODULE_DEPEND(msk, ether, 1, 1, 1); 147 MODULE_DEPEND(msk, miibus, 1, 1, 1); 148 149 /* "device miibus" required. See GENERIC if you get errors here. */ 150 #include "miibus_if.h" 151 152 /* Tunables. */ 153 static int msi_disable = 0; 154 TUNABLE_INT("hw.msk.msi_disable", &msi_disable); 155 static int legacy_intr = 0; 156 TUNABLE_INT("hw.msk.legacy_intr", &legacy_intr); 157 static int jumbo_disable = 0; 158 TUNABLE_INT("hw.msk.jumbo_disable", &jumbo_disable); 159 160 #define MSK_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 161 162 /* 163 * Devices supported by this driver. 164 */ 165 static struct msk_product { 166 uint16_t msk_vendorid; 167 uint16_t msk_deviceid; 168 const char *msk_name; 169 } msk_products[] = { 170 { VENDORID_SK, DEVICEID_SK_YUKON2, 171 "SK-9Sxx Gigabit Ethernet" }, 172 { VENDORID_SK, DEVICEID_SK_YUKON2_EXPR, 173 "SK-9Exx Gigabit Ethernet"}, 174 { VENDORID_MARVELL, DEVICEID_MRVL_8021CU, 175 "Marvell Yukon 88E8021CU Gigabit Ethernet" }, 176 { VENDORID_MARVELL, DEVICEID_MRVL_8021X, 177 "Marvell Yukon 88E8021 SX/LX Gigabit Ethernet" }, 178 { VENDORID_MARVELL, DEVICEID_MRVL_8022CU, 179 "Marvell Yukon 88E8022CU Gigabit Ethernet" }, 180 { VENDORID_MARVELL, DEVICEID_MRVL_8022X, 181 "Marvell Yukon 88E8022 SX/LX Gigabit Ethernet" }, 182 { VENDORID_MARVELL, DEVICEID_MRVL_8061CU, 183 "Marvell Yukon 88E8061CU Gigabit Ethernet" }, 184 { VENDORID_MARVELL, DEVICEID_MRVL_8061X, 185 "Marvell Yukon 88E8061 SX/LX Gigabit Ethernet" }, 186 { VENDORID_MARVELL, DEVICEID_MRVL_8062CU, 187 "Marvell Yukon 88E8062CU Gigabit Ethernet" }, 188 { VENDORID_MARVELL, DEVICEID_MRVL_8062X, 189 "Marvell Yukon 88E8062 SX/LX Gigabit Ethernet" }, 190 { VENDORID_MARVELL, DEVICEID_MRVL_8035, 191 "Marvell Yukon 88E8035 Fast Ethernet" }, 192 { VENDORID_MARVELL, DEVICEID_MRVL_8036, 193 "Marvell Yukon 88E8036 Fast Ethernet" }, 194 { VENDORID_MARVELL, DEVICEID_MRVL_8038, 195 "Marvell Yukon 88E8038 Fast Ethernet" }, 196 { VENDORID_MARVELL, DEVICEID_MRVL_8039, 197 "Marvell Yukon 88E8039 Fast Ethernet" }, 198 { VENDORID_MARVELL, DEVICEID_MRVL_8040, 199 "Marvell Yukon 88E8040 Fast Ethernet" }, 200 { VENDORID_MARVELL, DEVICEID_MRVL_8040T, 201 "Marvell Yukon 88E8040T Fast Ethernet" }, 202 { VENDORID_MARVELL, DEVICEID_MRVL_8042, 203 "Marvell Yukon 88E8042 Fast Ethernet" }, 204 { VENDORID_MARVELL, DEVICEID_MRVL_8048, 205 "Marvell Yukon 88E8048 Fast Ethernet" }, 206 { VENDORID_MARVELL, DEVICEID_MRVL_4361, 207 "Marvell Yukon 88E8050 Gigabit Ethernet" }, 208 { VENDORID_MARVELL, DEVICEID_MRVL_4360, 209 "Marvell Yukon 88E8052 Gigabit Ethernet" }, 210 { VENDORID_MARVELL, DEVICEID_MRVL_4362, 211 "Marvell Yukon 88E8053 Gigabit Ethernet" }, 212 { VENDORID_MARVELL, DEVICEID_MRVL_4363, 213 "Marvell Yukon 88E8055 Gigabit Ethernet" }, 214 { VENDORID_MARVELL, DEVICEID_MRVL_4364, 215 "Marvell Yukon 88E8056 Gigabit Ethernet" }, 216 { VENDORID_MARVELL, DEVICEID_MRVL_4365, 217 "Marvell Yukon 88E8070 Gigabit Ethernet" }, 218 { VENDORID_MARVELL, DEVICEID_MRVL_436A, 219 "Marvell Yukon 88E8058 Gigabit Ethernet" }, 220 { VENDORID_MARVELL, DEVICEID_MRVL_436B, 221 "Marvell Yukon 88E8071 Gigabit Ethernet" }, 222 { VENDORID_MARVELL, DEVICEID_MRVL_436C, 223 "Marvell Yukon 88E8072 Gigabit Ethernet" }, 224 { VENDORID_MARVELL, DEVICEID_MRVL_4380, 225 "Marvell Yukon 88E8057 Gigabit Ethernet" }, 226 { VENDORID_MARVELL, DEVICEID_MRVL_4381, 227 "Marvell Yukon 88E8059 Gigabit Ethernet" }, 228 { VENDORID_DLINK, DEVICEID_DLINK_DGE550SX, 229 "D-Link 550SX Gigabit Ethernet" }, 230 { VENDORID_DLINK, DEVICEID_DLINK_DGE560SX, 231 "D-Link 560SX Gigabit Ethernet" }, 232 { VENDORID_DLINK, DEVICEID_DLINK_DGE560T, 233 "D-Link 560T Gigabit Ethernet" } 234 }; 235 236 static const char *model_name[] = { 237 "Yukon XL", 238 "Yukon EC Ultra", 239 "Yukon EX", 240 "Yukon EC", 241 "Yukon FE", 242 "Yukon FE+", 243 "Yukon Supreme", 244 "Yukon Ultra 2", 245 "Yukon Unknown", 246 "Yukon Optima", 247 }; 248 249 static int mskc_probe(device_t); 250 static int mskc_attach(device_t); 251 static int mskc_detach(device_t); 252 static int mskc_shutdown(device_t); 253 static int mskc_setup_rambuffer(struct msk_softc *); 254 static int mskc_suspend(device_t); 255 static int mskc_resume(device_t); 256 static void mskc_reset(struct msk_softc *); 257 258 static int msk_probe(device_t); 259 static int msk_attach(device_t); 260 static int msk_detach(device_t); 261 262 static void msk_tick(void *); 263 static void msk_intr(void *); 264 static void msk_intr_phy(struct msk_if_softc *); 265 static void msk_intr_gmac(struct msk_if_softc *); 266 static __inline void msk_rxput(struct msk_if_softc *); 267 static int msk_handle_events(struct msk_softc *); 268 static void msk_handle_hwerr(struct msk_if_softc *, uint32_t); 269 static void msk_intr_hwerr(struct msk_softc *); 270 #ifndef __NO_STRICT_ALIGNMENT 271 static __inline void msk_fixup_rx(struct mbuf *); 272 #endif 273 static __inline void msk_rxcsum(struct msk_if_softc *, uint32_t, struct mbuf *); 274 static void msk_rxeof(struct msk_if_softc *, uint32_t, uint32_t, int); 275 static void msk_jumbo_rxeof(struct msk_if_softc *, uint32_t, uint32_t, int); 276 static void msk_txeof(struct msk_if_softc *, int); 277 static int msk_encap(struct msk_if_softc *, struct mbuf **); 278 static void msk_start(struct ifnet *); 279 static void msk_start_locked(struct ifnet *); 280 static int msk_ioctl(struct ifnet *, u_long, caddr_t); 281 static void msk_set_prefetch(struct msk_softc *, int, bus_addr_t, uint32_t); 282 static void msk_set_rambuffer(struct msk_if_softc *); 283 static void msk_set_tx_stfwd(struct msk_if_softc *); 284 static void msk_init(void *); 285 static void msk_init_locked(struct msk_if_softc *); 286 static void msk_stop(struct msk_if_softc *); 287 static void msk_watchdog(struct msk_if_softc *); 288 static int msk_mediachange(struct ifnet *); 289 static void msk_mediastatus(struct ifnet *, struct ifmediareq *); 290 static void msk_phy_power(struct msk_softc *, int); 291 static void msk_dmamap_cb(void *, bus_dma_segment_t *, int, int); 292 static int msk_status_dma_alloc(struct msk_softc *); 293 static void msk_status_dma_free(struct msk_softc *); 294 static int msk_txrx_dma_alloc(struct msk_if_softc *); 295 static int msk_rx_dma_jalloc(struct msk_if_softc *); 296 static void msk_txrx_dma_free(struct msk_if_softc *); 297 static void msk_rx_dma_jfree(struct msk_if_softc *); 298 static int msk_rx_fill(struct msk_if_softc *, int); 299 static int msk_init_rx_ring(struct msk_if_softc *); 300 static int msk_init_jumbo_rx_ring(struct msk_if_softc *); 301 static void msk_init_tx_ring(struct msk_if_softc *); 302 static __inline void msk_discard_rxbuf(struct msk_if_softc *, int); 303 static __inline void msk_discard_jumbo_rxbuf(struct msk_if_softc *, int); 304 static int msk_newbuf(struct msk_if_softc *, int); 305 static int msk_jumbo_newbuf(struct msk_if_softc *, int); 306 307 static int msk_phy_readreg(struct msk_if_softc *, int, int); 308 static int msk_phy_writereg(struct msk_if_softc *, int, int, int); 309 static int msk_miibus_readreg(device_t, int, int); 310 static int msk_miibus_writereg(device_t, int, int, int); 311 static void msk_miibus_statchg(device_t); 312 313 static void msk_rxfilter(struct msk_if_softc *); 314 static void msk_setvlan(struct msk_if_softc *, struct ifnet *); 315 316 static void msk_stats_clear(struct msk_if_softc *); 317 static void msk_stats_update(struct msk_if_softc *); 318 static int msk_sysctl_stat32(SYSCTL_HANDLER_ARGS); 319 static int msk_sysctl_stat64(SYSCTL_HANDLER_ARGS); 320 static void msk_sysctl_node(struct msk_if_softc *); 321 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int); 322 static int sysctl_hw_msk_proc_limit(SYSCTL_HANDLER_ARGS); 323 324 static device_method_t mskc_methods[] = { 325 /* Device interface */ 326 DEVMETHOD(device_probe, mskc_probe), 327 DEVMETHOD(device_attach, mskc_attach), 328 DEVMETHOD(device_detach, mskc_detach), 329 DEVMETHOD(device_suspend, mskc_suspend), 330 DEVMETHOD(device_resume, mskc_resume), 331 DEVMETHOD(device_shutdown, mskc_shutdown), 332 333 /* bus interface */ 334 DEVMETHOD(bus_print_child, bus_generic_print_child), 335 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 336 337 { NULL, NULL } 338 }; 339 340 static driver_t mskc_driver = { 341 "mskc", 342 mskc_methods, 343 sizeof(struct msk_softc) 344 }; 345 346 static devclass_t mskc_devclass; 347 348 static device_method_t msk_methods[] = { 349 /* Device interface */ 350 DEVMETHOD(device_probe, msk_probe), 351 DEVMETHOD(device_attach, msk_attach), 352 DEVMETHOD(device_detach, msk_detach), 353 DEVMETHOD(device_shutdown, bus_generic_shutdown), 354 355 /* bus interface */ 356 DEVMETHOD(bus_print_child, bus_generic_print_child), 357 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 358 359 /* MII interface */ 360 DEVMETHOD(miibus_readreg, msk_miibus_readreg), 361 DEVMETHOD(miibus_writereg, msk_miibus_writereg), 362 DEVMETHOD(miibus_statchg, msk_miibus_statchg), 363 364 { NULL, NULL } 365 }; 366 367 static driver_t msk_driver = { 368 "msk", 369 msk_methods, 370 sizeof(struct msk_if_softc) 371 }; 372 373 static devclass_t msk_devclass; 374 375 DRIVER_MODULE(mskc, pci, mskc_driver, mskc_devclass, 0, 0); 376 DRIVER_MODULE(msk, mskc, msk_driver, msk_devclass, 0, 0); 377 DRIVER_MODULE(miibus, msk, miibus_driver, miibus_devclass, 0, 0); 378 379 static struct resource_spec msk_res_spec_io[] = { 380 { SYS_RES_IOPORT, PCIR_BAR(1), RF_ACTIVE }, 381 { -1, 0, 0 } 382 }; 383 384 static struct resource_spec msk_res_spec_mem[] = { 385 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 386 { -1, 0, 0 } 387 }; 388 389 static struct resource_spec msk_irq_spec_legacy[] = { 390 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 391 { -1, 0, 0 } 392 }; 393 394 static struct resource_spec msk_irq_spec_msi[] = { 395 { SYS_RES_IRQ, 1, RF_ACTIVE }, 396 { -1, 0, 0 } 397 }; 398 399 static int 400 msk_miibus_readreg(device_t dev, int phy, int reg) 401 { 402 struct msk_if_softc *sc_if; 403 404 sc_if = device_get_softc(dev); 405 406 return (msk_phy_readreg(sc_if, phy, reg)); 407 } 408 409 static int 410 msk_phy_readreg(struct msk_if_softc *sc_if, int phy, int reg) 411 { 412 struct msk_softc *sc; 413 int i, val; 414 415 sc = sc_if->msk_softc; 416 417 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SMI_CTRL, 418 GM_SMI_CT_PHY_AD(phy) | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD); 419 420 for (i = 0; i < MSK_TIMEOUT; i++) { 421 DELAY(1); 422 val = GMAC_READ_2(sc, sc_if->msk_port, GM_SMI_CTRL); 423 if ((val & GM_SMI_CT_RD_VAL) != 0) { 424 val = GMAC_READ_2(sc, sc_if->msk_port, GM_SMI_DATA); 425 break; 426 } 427 } 428 429 if (i == MSK_TIMEOUT) { 430 if_printf(sc_if->msk_ifp, "phy failed to come ready\n"); 431 val = 0; 432 } 433 434 return (val); 435 } 436 437 static int 438 msk_miibus_writereg(device_t dev, int phy, int reg, int val) 439 { 440 struct msk_if_softc *sc_if; 441 442 sc_if = device_get_softc(dev); 443 444 return (msk_phy_writereg(sc_if, phy, reg, val)); 445 } 446 447 static int 448 msk_phy_writereg(struct msk_if_softc *sc_if, int phy, int reg, int val) 449 { 450 struct msk_softc *sc; 451 int i; 452 453 sc = sc_if->msk_softc; 454 455 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SMI_DATA, val); 456 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SMI_CTRL, 457 GM_SMI_CT_PHY_AD(phy) | GM_SMI_CT_REG_AD(reg)); 458 for (i = 0; i < MSK_TIMEOUT; i++) { 459 DELAY(1); 460 if ((GMAC_READ_2(sc, sc_if->msk_port, GM_SMI_CTRL) & 461 GM_SMI_CT_BUSY) == 0) 462 break; 463 } 464 if (i == MSK_TIMEOUT) 465 if_printf(sc_if->msk_ifp, "phy write timeout\n"); 466 467 return (0); 468 } 469 470 static void 471 msk_miibus_statchg(device_t dev) 472 { 473 struct msk_softc *sc; 474 struct msk_if_softc *sc_if; 475 struct mii_data *mii; 476 struct ifnet *ifp; 477 uint32_t gmac; 478 479 sc_if = device_get_softc(dev); 480 sc = sc_if->msk_softc; 481 482 MSK_IF_LOCK_ASSERT(sc_if); 483 484 mii = device_get_softc(sc_if->msk_miibus); 485 ifp = sc_if->msk_ifp; 486 if (mii == NULL || ifp == NULL || 487 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 488 return; 489 490 sc_if->msk_flags &= ~MSK_FLAG_LINK; 491 if ((mii->mii_media_status & (IFM_AVALID | IFM_ACTIVE)) == 492 (IFM_AVALID | IFM_ACTIVE)) { 493 switch (IFM_SUBTYPE(mii->mii_media_active)) { 494 case IFM_10_T: 495 case IFM_100_TX: 496 sc_if->msk_flags |= MSK_FLAG_LINK; 497 break; 498 case IFM_1000_T: 499 case IFM_1000_SX: 500 case IFM_1000_LX: 501 case IFM_1000_CX: 502 if ((sc_if->msk_flags & MSK_FLAG_FASTETHER) == 0) 503 sc_if->msk_flags |= MSK_FLAG_LINK; 504 break; 505 default: 506 break; 507 } 508 } 509 510 if ((sc_if->msk_flags & MSK_FLAG_LINK) != 0) { 511 /* Enable Tx FIFO Underrun. */ 512 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_MSK), 513 GM_IS_TX_FF_UR | GM_IS_RX_FF_OR); 514 /* 515 * Because mii(4) notify msk(4) that it detected link status 516 * change, there is no need to enable automatic 517 * speed/flow-control/duplex updates. 518 */ 519 gmac = GM_GPCR_AU_ALL_DIS; 520 switch (IFM_SUBTYPE(mii->mii_media_active)) { 521 case IFM_1000_SX: 522 case IFM_1000_T: 523 gmac |= GM_GPCR_SPEED_1000; 524 break; 525 case IFM_100_TX: 526 gmac |= GM_GPCR_SPEED_100; 527 break; 528 case IFM_10_T: 529 break; 530 } 531 532 /* Disable Rx flow control. */ 533 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FLAG0) == 0) 534 gmac |= GM_GPCR_FC_RX_DIS; 535 /* Disable Tx flow control. */ 536 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FLAG1) == 0) 537 gmac |= GM_GPCR_FC_TX_DIS; 538 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) 539 gmac |= GM_GPCR_DUP_FULL; 540 else 541 gmac |= GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS; 542 gmac |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA; 543 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, gmac); 544 /* Read again to ensure writing. */ 545 GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL); 546 gmac = GMC_PAUSE_OFF; 547 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 548 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FLAG0) != 0) 549 gmac = GMC_PAUSE_ON; 550 } 551 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), gmac); 552 553 /* Enable PHY interrupt for FIFO underrun/overflow. */ 554 msk_phy_writereg(sc_if, PHY_ADDR_MARV, 555 PHY_MARV_INT_MASK, PHY_M_IS_FIFO_ERROR); 556 } else { 557 /* 558 * Link state changed to down. 559 * Disable PHY interrupts. 560 */ 561 msk_phy_writereg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_MASK, 0); 562 /* Disable Rx/Tx MAC. */ 563 gmac = GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL); 564 if ((GM_GPCR_RX_ENA | GM_GPCR_TX_ENA) != 0) { 565 gmac &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA); 566 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, gmac); 567 /* Read again to ensure writing. */ 568 GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL); 569 } 570 } 571 } 572 573 static void 574 msk_rxfilter(struct msk_if_softc *sc_if) 575 { 576 struct msk_softc *sc; 577 struct ifnet *ifp; 578 struct ifmultiaddr *ifma; 579 uint32_t mchash[2]; 580 uint32_t crc; 581 uint16_t mode; 582 583 sc = sc_if->msk_softc; 584 585 MSK_IF_LOCK_ASSERT(sc_if); 586 587 ifp = sc_if->msk_ifp; 588 589 bzero(mchash, sizeof(mchash)); 590 mode = GMAC_READ_2(sc, sc_if->msk_port, GM_RX_CTRL); 591 if ((ifp->if_flags & IFF_PROMISC) != 0) 592 mode &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA); 593 else if ((ifp->if_flags & IFF_ALLMULTI) != 0) { 594 mode |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA; 595 mchash[0] = 0xffff; 596 mchash[1] = 0xffff; 597 } else { 598 mode |= GM_RXCR_UCF_ENA; 599 if_maddr_rlock(ifp); 600 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 601 if (ifma->ifma_addr->sa_family != AF_LINK) 602 continue; 603 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *) 604 ifma->ifma_addr), ETHER_ADDR_LEN); 605 /* Just want the 6 least significant bits. */ 606 crc &= 0x3f; 607 /* Set the corresponding bit in the hash table. */ 608 mchash[crc >> 5] |= 1 << (crc & 0x1f); 609 } 610 if_maddr_runlock(ifp); 611 if (mchash[0] != 0 || mchash[1] != 0) 612 mode |= GM_RXCR_MCF_ENA; 613 } 614 615 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H1, 616 mchash[0] & 0xffff); 617 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H2, 618 (mchash[0] >> 16) & 0xffff); 619 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H3, 620 mchash[1] & 0xffff); 621 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H4, 622 (mchash[1] >> 16) & 0xffff); 623 GMAC_WRITE_2(sc, sc_if->msk_port, GM_RX_CTRL, mode); 624 } 625 626 static void 627 msk_setvlan(struct msk_if_softc *sc_if, struct ifnet *ifp) 628 { 629 struct msk_softc *sc; 630 631 sc = sc_if->msk_softc; 632 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) { 633 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), 634 RX_VLAN_STRIP_ON); 635 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 636 TX_VLAN_TAG_ON); 637 } else { 638 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), 639 RX_VLAN_STRIP_OFF); 640 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 641 TX_VLAN_TAG_OFF); 642 } 643 } 644 645 static int 646 msk_rx_fill(struct msk_if_softc *sc_if, int jumbo) 647 { 648 uint16_t idx; 649 int i; 650 651 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0 && 652 (sc_if->msk_ifp->if_capenable & IFCAP_RXCSUM) != 0) { 653 /* Wait until controller executes OP_TCPSTART command. */ 654 for (i = 10; i > 0; i--) { 655 DELAY(10); 656 idx = CSR_READ_2(sc_if->msk_softc, 657 Y2_PREF_Q_ADDR(sc_if->msk_rxq, 658 PREF_UNIT_GET_IDX_REG)); 659 if (idx != 0) 660 break; 661 } 662 if (i == 0) { 663 device_printf(sc_if->msk_if_dev, 664 "prefetch unit stuck?\n"); 665 return (ETIMEDOUT); 666 } 667 /* 668 * Fill consumed LE with free buffer. This can be done 669 * in Rx handler but we don't want to add special code 670 * in fast handler. 671 */ 672 if (jumbo > 0) { 673 if (msk_jumbo_newbuf(sc_if, 0) != 0) 674 return (ENOBUFS); 675 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 676 sc_if->msk_cdata.msk_jumbo_rx_ring_map, 677 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 678 } else { 679 if (msk_newbuf(sc_if, 0) != 0) 680 return (ENOBUFS); 681 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_ring_tag, 682 sc_if->msk_cdata.msk_rx_ring_map, 683 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 684 } 685 sc_if->msk_cdata.msk_rx_prod = 0; 686 CSR_WRITE_2(sc_if->msk_softc, 687 Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_PUT_IDX_REG), 688 sc_if->msk_cdata.msk_rx_prod); 689 } 690 return (0); 691 } 692 693 static int 694 msk_init_rx_ring(struct msk_if_softc *sc_if) 695 { 696 struct msk_ring_data *rd; 697 struct msk_rxdesc *rxd; 698 int i, prod; 699 700 MSK_IF_LOCK_ASSERT(sc_if); 701 702 sc_if->msk_cdata.msk_rx_cons = 0; 703 sc_if->msk_cdata.msk_rx_prod = 0; 704 sc_if->msk_cdata.msk_rx_putwm = MSK_PUT_WM; 705 706 rd = &sc_if->msk_rdata; 707 bzero(rd->msk_rx_ring, sizeof(struct msk_rx_desc) * MSK_RX_RING_CNT); 708 prod = sc_if->msk_cdata.msk_rx_prod; 709 i = 0; 710 /* Have controller know how to compute Rx checksum. */ 711 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0 && 712 (sc_if->msk_ifp->if_capenable & IFCAP_RXCSUM) != 0) { 713 rxd = &sc_if->msk_cdata.msk_rxdesc[prod]; 714 rxd->rx_m = NULL; 715 rxd->rx_le = &rd->msk_rx_ring[prod]; 716 rxd->rx_le->msk_addr = htole32(ETHER_HDR_LEN << 16 | 717 ETHER_HDR_LEN); 718 rxd->rx_le->msk_control = htole32(OP_TCPSTART | HW_OWNER); 719 MSK_INC(prod, MSK_RX_RING_CNT); 720 MSK_INC(sc_if->msk_cdata.msk_rx_cons, MSK_RX_RING_CNT); 721 i++; 722 } 723 for (; i < MSK_RX_RING_CNT; i++) { 724 rxd = &sc_if->msk_cdata.msk_rxdesc[prod]; 725 rxd->rx_m = NULL; 726 rxd->rx_le = &rd->msk_rx_ring[prod]; 727 if (msk_newbuf(sc_if, prod) != 0) 728 return (ENOBUFS); 729 MSK_INC(prod, MSK_RX_RING_CNT); 730 } 731 732 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_ring_tag, 733 sc_if->msk_cdata.msk_rx_ring_map, 734 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 735 736 /* Update prefetch unit. */ 737 sc_if->msk_cdata.msk_rx_prod = MSK_RX_RING_CNT - 1; 738 CSR_WRITE_2(sc_if->msk_softc, 739 Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_PUT_IDX_REG), 740 sc_if->msk_cdata.msk_rx_prod); 741 if (msk_rx_fill(sc_if, 0) != 0) 742 return (ENOBUFS); 743 return (0); 744 } 745 746 static int 747 msk_init_jumbo_rx_ring(struct msk_if_softc *sc_if) 748 { 749 struct msk_ring_data *rd; 750 struct msk_rxdesc *rxd; 751 int i, prod; 752 753 MSK_IF_LOCK_ASSERT(sc_if); 754 755 sc_if->msk_cdata.msk_rx_cons = 0; 756 sc_if->msk_cdata.msk_rx_prod = 0; 757 sc_if->msk_cdata.msk_rx_putwm = MSK_PUT_WM; 758 759 rd = &sc_if->msk_rdata; 760 bzero(rd->msk_jumbo_rx_ring, 761 sizeof(struct msk_rx_desc) * MSK_JUMBO_RX_RING_CNT); 762 prod = sc_if->msk_cdata.msk_rx_prod; 763 i = 0; 764 /* Have controller know how to compute Rx checksum. */ 765 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0 && 766 (sc_if->msk_ifp->if_capenable & IFCAP_RXCSUM) != 0) { 767 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[prod]; 768 rxd->rx_m = NULL; 769 rxd->rx_le = &rd->msk_jumbo_rx_ring[prod]; 770 rxd->rx_le->msk_addr = htole32(ETHER_HDR_LEN << 16 | 771 ETHER_HDR_LEN); 772 rxd->rx_le->msk_control = htole32(OP_TCPSTART | HW_OWNER); 773 MSK_INC(prod, MSK_JUMBO_RX_RING_CNT); 774 MSK_INC(sc_if->msk_cdata.msk_rx_cons, MSK_JUMBO_RX_RING_CNT); 775 i++; 776 } 777 for (; i < MSK_JUMBO_RX_RING_CNT; i++) { 778 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[prod]; 779 rxd->rx_m = NULL; 780 rxd->rx_le = &rd->msk_jumbo_rx_ring[prod]; 781 if (msk_jumbo_newbuf(sc_if, prod) != 0) 782 return (ENOBUFS); 783 MSK_INC(prod, MSK_JUMBO_RX_RING_CNT); 784 } 785 786 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 787 sc_if->msk_cdata.msk_jumbo_rx_ring_map, 788 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 789 790 sc_if->msk_cdata.msk_rx_prod = MSK_JUMBO_RX_RING_CNT - 1; 791 CSR_WRITE_2(sc_if->msk_softc, 792 Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_PUT_IDX_REG), 793 sc_if->msk_cdata.msk_rx_prod); 794 if (msk_rx_fill(sc_if, 1) != 0) 795 return (ENOBUFS); 796 return (0); 797 } 798 799 static void 800 msk_init_tx_ring(struct msk_if_softc *sc_if) 801 { 802 struct msk_ring_data *rd; 803 struct msk_txdesc *txd; 804 int i; 805 806 sc_if->msk_cdata.msk_tso_mtu = 0; 807 sc_if->msk_cdata.msk_last_csum = 0; 808 sc_if->msk_cdata.msk_tx_prod = 0; 809 sc_if->msk_cdata.msk_tx_cons = 0; 810 sc_if->msk_cdata.msk_tx_cnt = 0; 811 812 rd = &sc_if->msk_rdata; 813 bzero(rd->msk_tx_ring, sizeof(struct msk_tx_desc) * MSK_TX_RING_CNT); 814 for (i = 0; i < MSK_TX_RING_CNT; i++) { 815 txd = &sc_if->msk_cdata.msk_txdesc[i]; 816 txd->tx_m = NULL; 817 txd->tx_le = &rd->msk_tx_ring[i]; 818 } 819 820 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_ring_tag, 821 sc_if->msk_cdata.msk_tx_ring_map, 822 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 823 } 824 825 static __inline void 826 msk_discard_rxbuf(struct msk_if_softc *sc_if, int idx) 827 { 828 struct msk_rx_desc *rx_le; 829 struct msk_rxdesc *rxd; 830 struct mbuf *m; 831 832 rxd = &sc_if->msk_cdata.msk_rxdesc[idx]; 833 m = rxd->rx_m; 834 rx_le = rxd->rx_le; 835 rx_le->msk_control = htole32(m->m_len | OP_PACKET | HW_OWNER); 836 } 837 838 static __inline void 839 msk_discard_jumbo_rxbuf(struct msk_if_softc *sc_if, int idx) 840 { 841 struct msk_rx_desc *rx_le; 842 struct msk_rxdesc *rxd; 843 struct mbuf *m; 844 845 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[idx]; 846 m = rxd->rx_m; 847 rx_le = rxd->rx_le; 848 rx_le->msk_control = htole32(m->m_len | OP_PACKET | HW_OWNER); 849 } 850 851 static int 852 msk_newbuf(struct msk_if_softc *sc_if, int idx) 853 { 854 struct msk_rx_desc *rx_le; 855 struct msk_rxdesc *rxd; 856 struct mbuf *m; 857 bus_dma_segment_t segs[1]; 858 bus_dmamap_t map; 859 int nsegs; 860 861 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 862 if (m == NULL) 863 return (ENOBUFS); 864 865 m->m_len = m->m_pkthdr.len = MCLBYTES; 866 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) == 0) 867 m_adj(m, ETHER_ALIGN); 868 #ifndef __NO_STRICT_ALIGNMENT 869 else 870 m_adj(m, MSK_RX_BUF_ALIGN); 871 #endif 872 873 if (bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_rx_tag, 874 sc_if->msk_cdata.msk_rx_sparemap, m, segs, &nsegs, 875 BUS_DMA_NOWAIT) != 0) { 876 m_freem(m); 877 return (ENOBUFS); 878 } 879 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 880 881 rxd = &sc_if->msk_cdata.msk_rxdesc[idx]; 882 if (rxd->rx_m != NULL) { 883 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_tag, rxd->rx_dmamap, 884 BUS_DMASYNC_POSTREAD); 885 bus_dmamap_unload(sc_if->msk_cdata.msk_rx_tag, rxd->rx_dmamap); 886 } 887 map = rxd->rx_dmamap; 888 rxd->rx_dmamap = sc_if->msk_cdata.msk_rx_sparemap; 889 sc_if->msk_cdata.msk_rx_sparemap = map; 890 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_tag, rxd->rx_dmamap, 891 BUS_DMASYNC_PREREAD); 892 rxd->rx_m = m; 893 rx_le = rxd->rx_le; 894 rx_le->msk_addr = htole32(MSK_ADDR_LO(segs[0].ds_addr)); 895 rx_le->msk_control = 896 htole32(segs[0].ds_len | OP_PACKET | HW_OWNER); 897 898 return (0); 899 } 900 901 static int 902 msk_jumbo_newbuf(struct msk_if_softc *sc_if, int idx) 903 { 904 struct msk_rx_desc *rx_le; 905 struct msk_rxdesc *rxd; 906 struct mbuf *m; 907 bus_dma_segment_t segs[1]; 908 bus_dmamap_t map; 909 int nsegs; 910 911 m = m_getjcl(M_DONTWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES); 912 if (m == NULL) 913 return (ENOBUFS); 914 if ((m->m_flags & M_EXT) == 0) { 915 m_freem(m); 916 return (ENOBUFS); 917 } 918 m->m_len = m->m_pkthdr.len = MJUM9BYTES; 919 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) == 0) 920 m_adj(m, ETHER_ALIGN); 921 #ifndef __NO_STRICT_ALIGNMENT 922 else 923 m_adj(m, MSK_RX_BUF_ALIGN); 924 #endif 925 926 if (bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_jumbo_rx_tag, 927 sc_if->msk_cdata.msk_jumbo_rx_sparemap, m, segs, &nsegs, 928 BUS_DMA_NOWAIT) != 0) { 929 m_freem(m); 930 return (ENOBUFS); 931 } 932 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 933 934 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[idx]; 935 if (rxd->rx_m != NULL) { 936 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_tag, 937 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 938 bus_dmamap_unload(sc_if->msk_cdata.msk_jumbo_rx_tag, 939 rxd->rx_dmamap); 940 } 941 map = rxd->rx_dmamap; 942 rxd->rx_dmamap = sc_if->msk_cdata.msk_jumbo_rx_sparemap; 943 sc_if->msk_cdata.msk_jumbo_rx_sparemap = map; 944 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_tag, rxd->rx_dmamap, 945 BUS_DMASYNC_PREREAD); 946 rxd->rx_m = m; 947 rx_le = rxd->rx_le; 948 rx_le->msk_addr = htole32(MSK_ADDR_LO(segs[0].ds_addr)); 949 rx_le->msk_control = 950 htole32(segs[0].ds_len | OP_PACKET | HW_OWNER); 951 952 return (0); 953 } 954 955 /* 956 * Set media options. 957 */ 958 static int 959 msk_mediachange(struct ifnet *ifp) 960 { 961 struct msk_if_softc *sc_if; 962 struct mii_data *mii; 963 int error; 964 965 sc_if = ifp->if_softc; 966 967 MSK_IF_LOCK(sc_if); 968 mii = device_get_softc(sc_if->msk_miibus); 969 error = mii_mediachg(mii); 970 MSK_IF_UNLOCK(sc_if); 971 972 return (error); 973 } 974 975 /* 976 * Report current media status. 977 */ 978 static void 979 msk_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 980 { 981 struct msk_if_softc *sc_if; 982 struct mii_data *mii; 983 984 sc_if = ifp->if_softc; 985 MSK_IF_LOCK(sc_if); 986 if ((ifp->if_flags & IFF_UP) == 0) { 987 MSK_IF_UNLOCK(sc_if); 988 return; 989 } 990 mii = device_get_softc(sc_if->msk_miibus); 991 992 mii_pollstat(mii); 993 MSK_IF_UNLOCK(sc_if); 994 ifmr->ifm_active = mii->mii_media_active; 995 ifmr->ifm_status = mii->mii_media_status; 996 } 997 998 static int 999 msk_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1000 { 1001 struct msk_if_softc *sc_if; 1002 struct ifreq *ifr; 1003 struct mii_data *mii; 1004 int error, mask, reinit; 1005 1006 sc_if = ifp->if_softc; 1007 ifr = (struct ifreq *)data; 1008 error = 0; 1009 1010 switch(command) { 1011 case SIOCSIFMTU: 1012 MSK_IF_LOCK(sc_if); 1013 if (ifr->ifr_mtu > MSK_JUMBO_MTU || ifr->ifr_mtu < ETHERMIN) 1014 error = EINVAL; 1015 else if (ifp->if_mtu != ifr->ifr_mtu) { 1016 if (ifr->ifr_mtu > ETHERMTU) { 1017 if ((sc_if->msk_flags & MSK_FLAG_JUMBO) == 0) { 1018 error = EINVAL; 1019 MSK_IF_UNLOCK(sc_if); 1020 break; 1021 } 1022 if ((sc_if->msk_flags & 1023 MSK_FLAG_JUMBO_NOCSUM) != 0) { 1024 ifp->if_hwassist &= 1025 ~(MSK_CSUM_FEATURES | CSUM_TSO); 1026 ifp->if_capenable &= 1027 ~(IFCAP_TSO4 | IFCAP_TXCSUM); 1028 VLAN_CAPABILITIES(ifp); 1029 } 1030 } 1031 ifp->if_mtu = ifr->ifr_mtu; 1032 msk_init_locked(sc_if); 1033 } 1034 MSK_IF_UNLOCK(sc_if); 1035 break; 1036 case SIOCSIFFLAGS: 1037 MSK_IF_LOCK(sc_if); 1038 if ((ifp->if_flags & IFF_UP) != 0) { 1039 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 && 1040 ((ifp->if_flags ^ sc_if->msk_if_flags) & 1041 (IFF_PROMISC | IFF_ALLMULTI)) != 0) 1042 msk_rxfilter(sc_if); 1043 else if ((sc_if->msk_flags & MSK_FLAG_DETACH) == 0) 1044 msk_init_locked(sc_if); 1045 } else if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1046 msk_stop(sc_if); 1047 sc_if->msk_if_flags = ifp->if_flags; 1048 MSK_IF_UNLOCK(sc_if); 1049 break; 1050 case SIOCADDMULTI: 1051 case SIOCDELMULTI: 1052 MSK_IF_LOCK(sc_if); 1053 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1054 msk_rxfilter(sc_if); 1055 MSK_IF_UNLOCK(sc_if); 1056 break; 1057 case SIOCGIFMEDIA: 1058 case SIOCSIFMEDIA: 1059 mii = device_get_softc(sc_if->msk_miibus); 1060 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1061 break; 1062 case SIOCSIFCAP: 1063 reinit = 0; 1064 MSK_IF_LOCK(sc_if); 1065 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 1066 if ((mask & IFCAP_TXCSUM) != 0 && 1067 (IFCAP_TXCSUM & ifp->if_capabilities) != 0) { 1068 ifp->if_capenable ^= IFCAP_TXCSUM; 1069 if ((IFCAP_TXCSUM & ifp->if_capenable) != 0) 1070 ifp->if_hwassist |= MSK_CSUM_FEATURES; 1071 else 1072 ifp->if_hwassist &= ~MSK_CSUM_FEATURES; 1073 } 1074 if ((mask & IFCAP_RXCSUM) != 0 && 1075 (IFCAP_RXCSUM & ifp->if_capabilities) != 0) { 1076 ifp->if_capenable ^= IFCAP_RXCSUM; 1077 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0) 1078 reinit = 1; 1079 } 1080 if ((mask & IFCAP_VLAN_HWCSUM) != 0 && 1081 (IFCAP_VLAN_HWCSUM & ifp->if_capabilities) != 0) 1082 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; 1083 if ((mask & IFCAP_TSO4) != 0 && 1084 (IFCAP_TSO4 & ifp->if_capabilities) != 0) { 1085 ifp->if_capenable ^= IFCAP_TSO4; 1086 if ((IFCAP_TSO4 & ifp->if_capenable) != 0) 1087 ifp->if_hwassist |= CSUM_TSO; 1088 else 1089 ifp->if_hwassist &= ~CSUM_TSO; 1090 } 1091 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 1092 (IFCAP_VLAN_HWTSO & ifp->if_capabilities) != 0) 1093 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 1094 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 1095 (IFCAP_VLAN_HWTAGGING & ifp->if_capabilities) != 0) { 1096 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 1097 if ((IFCAP_VLAN_HWTAGGING & ifp->if_capenable) == 0) 1098 ifp->if_capenable &= 1099 ~(IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM); 1100 msk_setvlan(sc_if, ifp); 1101 } 1102 if (ifp->if_mtu > ETHERMTU && 1103 (sc_if->msk_flags & MSK_FLAG_JUMBO_NOCSUM) != 0) { 1104 ifp->if_hwassist &= ~(MSK_CSUM_FEATURES | CSUM_TSO); 1105 ifp->if_capenable &= ~(IFCAP_TSO4 | IFCAP_TXCSUM); 1106 } 1107 VLAN_CAPABILITIES(ifp); 1108 if (reinit > 0 && (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 1109 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1110 msk_init_locked(sc_if); 1111 } 1112 MSK_IF_UNLOCK(sc_if); 1113 break; 1114 default: 1115 error = ether_ioctl(ifp, command, data); 1116 break; 1117 } 1118 1119 return (error); 1120 } 1121 1122 static int 1123 mskc_probe(device_t dev) 1124 { 1125 struct msk_product *mp; 1126 uint16_t vendor, devid; 1127 int i; 1128 1129 vendor = pci_get_vendor(dev); 1130 devid = pci_get_device(dev); 1131 mp = msk_products; 1132 for (i = 0; i < sizeof(msk_products)/sizeof(msk_products[0]); 1133 i++, mp++) { 1134 if (vendor == mp->msk_vendorid && devid == mp->msk_deviceid) { 1135 device_set_desc(dev, mp->msk_name); 1136 return (BUS_PROBE_DEFAULT); 1137 } 1138 } 1139 1140 return (ENXIO); 1141 } 1142 1143 static int 1144 mskc_setup_rambuffer(struct msk_softc *sc) 1145 { 1146 int next; 1147 int i; 1148 1149 /* Get adapter SRAM size. */ 1150 sc->msk_ramsize = CSR_READ_1(sc, B2_E_0) * 4; 1151 if (bootverbose) 1152 device_printf(sc->msk_dev, 1153 "RAM buffer size : %dKB\n", sc->msk_ramsize); 1154 if (sc->msk_ramsize == 0) 1155 return (0); 1156 1157 sc->msk_pflags |= MSK_FLAG_RAMBUF; 1158 /* 1159 * Give receiver 2/3 of memory and round down to the multiple 1160 * of 1024. Tx/Rx RAM buffer size of Yukon II should be multiple 1161 * of 1024. 1162 */ 1163 sc->msk_rxqsize = rounddown((sc->msk_ramsize * 1024 * 2) / 3, 1024); 1164 sc->msk_txqsize = (sc->msk_ramsize * 1024) - sc->msk_rxqsize; 1165 for (i = 0, next = 0; i < sc->msk_num_port; i++) { 1166 sc->msk_rxqstart[i] = next; 1167 sc->msk_rxqend[i] = next + sc->msk_rxqsize - 1; 1168 next = sc->msk_rxqend[i] + 1; 1169 sc->msk_txqstart[i] = next; 1170 sc->msk_txqend[i] = next + sc->msk_txqsize - 1; 1171 next = sc->msk_txqend[i] + 1; 1172 if (bootverbose) { 1173 device_printf(sc->msk_dev, 1174 "Port %d : Rx Queue %dKB(0x%08x:0x%08x)\n", i, 1175 sc->msk_rxqsize / 1024, sc->msk_rxqstart[i], 1176 sc->msk_rxqend[i]); 1177 device_printf(sc->msk_dev, 1178 "Port %d : Tx Queue %dKB(0x%08x:0x%08x)\n", i, 1179 sc->msk_txqsize / 1024, sc->msk_txqstart[i], 1180 sc->msk_txqend[i]); 1181 } 1182 } 1183 1184 return (0); 1185 } 1186 1187 static void 1188 msk_phy_power(struct msk_softc *sc, int mode) 1189 { 1190 uint32_t our, val; 1191 int i; 1192 1193 switch (mode) { 1194 case MSK_PHY_POWERUP: 1195 /* Switch power to VCC (WA for VAUX problem). */ 1196 CSR_WRITE_1(sc, B0_POWER_CTRL, 1197 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON); 1198 /* Disable Core Clock Division, set Clock Select to 0. */ 1199 CSR_WRITE_4(sc, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS); 1200 1201 val = 0; 1202 if (sc->msk_hw_id == CHIP_ID_YUKON_XL && 1203 sc->msk_hw_rev > CHIP_REV_YU_XL_A1) { 1204 /* Enable bits are inverted. */ 1205 val = Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS | 1206 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS | 1207 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS; 1208 } 1209 /* 1210 * Enable PCI & Core Clock, enable clock gating for both Links. 1211 */ 1212 CSR_WRITE_1(sc, B2_Y2_CLK_GATE, val); 1213 1214 val = CSR_PCI_READ_4(sc, PCI_OUR_REG_1); 1215 val &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD); 1216 if (sc->msk_hw_id == CHIP_ID_YUKON_XL) { 1217 if (sc->msk_hw_rev > CHIP_REV_YU_XL_A1) { 1218 /* Deassert Low Power for 1st PHY. */ 1219 val |= PCI_Y2_PHY1_COMA; 1220 if (sc->msk_num_port > 1) 1221 val |= PCI_Y2_PHY2_COMA; 1222 } 1223 } 1224 /* Release PHY from PowerDown/COMA mode. */ 1225 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_1, val); 1226 switch (sc->msk_hw_id) { 1227 case CHIP_ID_YUKON_EC_U: 1228 case CHIP_ID_YUKON_EX: 1229 case CHIP_ID_YUKON_FE_P: 1230 case CHIP_ID_YUKON_UL_2: 1231 case CHIP_ID_YUKON_OPT: 1232 CSR_WRITE_2(sc, B0_CTST, Y2_HW_WOL_OFF); 1233 1234 /* Enable all clocks. */ 1235 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_3, 0); 1236 our = CSR_PCI_READ_4(sc, PCI_OUR_REG_4); 1237 our &= (PCI_FORCE_ASPM_REQUEST|PCI_ASPM_GPHY_LINK_DOWN| 1238 PCI_ASPM_INT_FIFO_EMPTY|PCI_ASPM_CLKRUN_REQUEST); 1239 /* Set all bits to 0 except bits 15..12. */ 1240 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_4, our); 1241 our = CSR_PCI_READ_4(sc, PCI_OUR_REG_5); 1242 our &= PCI_CTL_TIM_VMAIN_AV_MSK; 1243 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_5, our); 1244 CSR_PCI_WRITE_4(sc, PCI_CFG_REG_1, 0); 1245 /* 1246 * Disable status race, workaround for 1247 * Yukon EC Ultra & Yukon EX. 1248 */ 1249 val = CSR_READ_4(sc, B2_GP_IO); 1250 val |= GLB_GPIO_STAT_RACE_DIS; 1251 CSR_WRITE_4(sc, B2_GP_IO, val); 1252 CSR_READ_4(sc, B2_GP_IO); 1253 break; 1254 default: 1255 break; 1256 } 1257 for (i = 0; i < sc->msk_num_port; i++) { 1258 CSR_WRITE_2(sc, MR_ADDR(i, GMAC_LINK_CTRL), 1259 GMLC_RST_SET); 1260 CSR_WRITE_2(sc, MR_ADDR(i, GMAC_LINK_CTRL), 1261 GMLC_RST_CLR); 1262 } 1263 break; 1264 case MSK_PHY_POWERDOWN: 1265 val = CSR_PCI_READ_4(sc, PCI_OUR_REG_1); 1266 val |= PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD; 1267 if (sc->msk_hw_id == CHIP_ID_YUKON_XL && 1268 sc->msk_hw_rev > CHIP_REV_YU_XL_A1) { 1269 val &= ~PCI_Y2_PHY1_COMA; 1270 if (sc->msk_num_port > 1) 1271 val &= ~PCI_Y2_PHY2_COMA; 1272 } 1273 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_1, val); 1274 1275 val = Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS | 1276 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS | 1277 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS; 1278 if (sc->msk_hw_id == CHIP_ID_YUKON_XL && 1279 sc->msk_hw_rev > CHIP_REV_YU_XL_A1) { 1280 /* Enable bits are inverted. */ 1281 val = 0; 1282 } 1283 /* 1284 * Disable PCI & Core Clock, disable clock gating for 1285 * both Links. 1286 */ 1287 CSR_WRITE_1(sc, B2_Y2_CLK_GATE, val); 1288 CSR_WRITE_1(sc, B0_POWER_CTRL, 1289 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_ON | PC_VCC_OFF); 1290 break; 1291 default: 1292 break; 1293 } 1294 } 1295 1296 static void 1297 mskc_reset(struct msk_softc *sc) 1298 { 1299 bus_addr_t addr; 1300 uint16_t status; 1301 uint32_t val; 1302 int i; 1303 1304 CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR); 1305 1306 /* Disable ASF. */ 1307 if (sc->msk_hw_id == CHIP_ID_YUKON_EX) { 1308 status = CSR_READ_2(sc, B28_Y2_ASF_HCU_CCSR); 1309 /* Clear AHB bridge & microcontroller reset. */ 1310 status &= ~(Y2_ASF_HCU_CCSR_AHB_RST | 1311 Y2_ASF_HCU_CCSR_CPU_RST_MODE); 1312 /* Clear ASF microcontroller state. */ 1313 status &= ~ Y2_ASF_HCU_CCSR_UC_STATE_MSK; 1314 CSR_WRITE_2(sc, B28_Y2_ASF_HCU_CCSR, status); 1315 } else 1316 CSR_WRITE_1(sc, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET); 1317 CSR_WRITE_2(sc, B0_CTST, Y2_ASF_DISABLE); 1318 1319 /* 1320 * Since we disabled ASF, S/W reset is required for Power Management. 1321 */ 1322 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); 1323 CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR); 1324 1325 /* Clear all error bits in the PCI status register. */ 1326 status = pci_read_config(sc->msk_dev, PCIR_STATUS, 2); 1327 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON); 1328 1329 pci_write_config(sc->msk_dev, PCIR_STATUS, status | 1330 PCIM_STATUS_PERR | PCIM_STATUS_SERR | PCIM_STATUS_RMABORT | 1331 PCIM_STATUS_RTABORT | PCIM_STATUS_MDPERR, 2); 1332 CSR_WRITE_2(sc, B0_CTST, CS_MRST_CLR); 1333 1334 switch (sc->msk_bustype) { 1335 case MSK_PEX_BUS: 1336 /* Clear all PEX errors. */ 1337 CSR_PCI_WRITE_4(sc, PEX_UNC_ERR_STAT, 0xffffffff); 1338 val = CSR_PCI_READ_4(sc, PEX_UNC_ERR_STAT); 1339 if ((val & PEX_RX_OV) != 0) { 1340 sc->msk_intrmask &= ~Y2_IS_HW_ERR; 1341 sc->msk_intrhwemask &= ~Y2_IS_PCI_EXP; 1342 } 1343 break; 1344 case MSK_PCI_BUS: 1345 case MSK_PCIX_BUS: 1346 /* Set Cache Line Size to 2(8bytes) if configured to 0. */ 1347 val = pci_read_config(sc->msk_dev, PCIR_CACHELNSZ, 1); 1348 if (val == 0) 1349 pci_write_config(sc->msk_dev, PCIR_CACHELNSZ, 2, 1); 1350 if (sc->msk_bustype == MSK_PCIX_BUS) { 1351 /* Set Cache Line Size opt. */ 1352 val = pci_read_config(sc->msk_dev, PCI_OUR_REG_1, 4); 1353 val |= PCI_CLS_OPT; 1354 pci_write_config(sc->msk_dev, PCI_OUR_REG_1, val, 4); 1355 } 1356 break; 1357 } 1358 /* Set PHY power state. */ 1359 msk_phy_power(sc, MSK_PHY_POWERUP); 1360 1361 /* Reset GPHY/GMAC Control */ 1362 for (i = 0; i < sc->msk_num_port; i++) { 1363 /* GPHY Control reset. */ 1364 CSR_WRITE_4(sc, MR_ADDR(i, GPHY_CTRL), GPC_RST_SET); 1365 CSR_WRITE_4(sc, MR_ADDR(i, GPHY_CTRL), GPC_RST_CLR); 1366 /* GMAC Control reset. */ 1367 CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), GMC_RST_SET); 1368 CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), GMC_RST_CLR); 1369 CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), GMC_F_LOOPB_OFF); 1370 if (sc->msk_hw_id == CHIP_ID_YUKON_EX) 1371 CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), 1372 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON | 1373 GMC_BYP_RETR_ON); 1374 } 1375 if (sc->msk_hw_id == CHIP_ID_YUKON_OPT && sc->msk_hw_rev == 0) { 1376 /* Disable PCIe PHY powerdown(reg 0x80, bit7). */ 1377 CSR_WRITE_4(sc, Y2_PEX_PHY_DATA, (0x0080 << 16) | 0x0080); 1378 } 1379 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 1380 1381 /* LED On. */ 1382 CSR_WRITE_2(sc, B0_CTST, Y2_LED_STAT_ON); 1383 1384 /* Clear TWSI IRQ. */ 1385 CSR_WRITE_4(sc, B2_I2C_IRQ, I2C_CLR_IRQ); 1386 1387 /* Turn off hardware timer. */ 1388 CSR_WRITE_1(sc, B2_TI_CTRL, TIM_STOP); 1389 CSR_WRITE_1(sc, B2_TI_CTRL, TIM_CLR_IRQ); 1390 1391 /* Turn off descriptor polling. */ 1392 CSR_WRITE_1(sc, B28_DPT_CTRL, DPT_STOP); 1393 1394 /* Turn off time stamps. */ 1395 CSR_WRITE_1(sc, GMAC_TI_ST_CTRL, GMT_ST_STOP); 1396 CSR_WRITE_1(sc, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ); 1397 1398 /* Configure timeout values. */ 1399 for (i = 0; i < sc->msk_num_port; i++) { 1400 CSR_WRITE_2(sc, SELECT_RAM_BUFFER(i, B3_RI_CTRL), RI_RST_SET); 1401 CSR_WRITE_2(sc, SELECT_RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR); 1402 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_R1), 1403 MSK_RI_TO_53); 1404 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XA1), 1405 MSK_RI_TO_53); 1406 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XS1), 1407 MSK_RI_TO_53); 1408 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_R1), 1409 MSK_RI_TO_53); 1410 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XA1), 1411 MSK_RI_TO_53); 1412 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XS1), 1413 MSK_RI_TO_53); 1414 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_R2), 1415 MSK_RI_TO_53); 1416 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XA2), 1417 MSK_RI_TO_53); 1418 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XS2), 1419 MSK_RI_TO_53); 1420 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_R2), 1421 MSK_RI_TO_53); 1422 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XA2), 1423 MSK_RI_TO_53); 1424 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XS2), 1425 MSK_RI_TO_53); 1426 } 1427 1428 /* Disable all interrupts. */ 1429 CSR_WRITE_4(sc, B0_HWE_IMSK, 0); 1430 CSR_READ_4(sc, B0_HWE_IMSK); 1431 CSR_WRITE_4(sc, B0_IMSK, 0); 1432 CSR_READ_4(sc, B0_IMSK); 1433 1434 /* 1435 * On dual port PCI-X card, there is an problem where status 1436 * can be received out of order due to split transactions. 1437 */ 1438 if (sc->msk_pcixcap != 0 && sc->msk_num_port > 1) { 1439 uint16_t pcix_cmd; 1440 1441 pcix_cmd = pci_read_config(sc->msk_dev, 1442 sc->msk_pcixcap + PCIXR_COMMAND, 2); 1443 /* Clear Max Outstanding Split Transactions. */ 1444 pcix_cmd &= ~PCIXM_COMMAND_MAX_SPLITS; 1445 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON); 1446 pci_write_config(sc->msk_dev, 1447 sc->msk_pcixcap + PCIXR_COMMAND, pcix_cmd, 2); 1448 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 1449 } 1450 if (sc->msk_expcap != 0) { 1451 /* Change Max. Read Request Size to 2048 bytes. */ 1452 if (pci_get_max_read_req(sc->msk_dev) == 512) 1453 pci_set_max_read_req(sc->msk_dev, 2048); 1454 } 1455 1456 /* Clear status list. */ 1457 bzero(sc->msk_stat_ring, 1458 sizeof(struct msk_stat_desc) * MSK_STAT_RING_CNT); 1459 sc->msk_stat_cons = 0; 1460 bus_dmamap_sync(sc->msk_stat_tag, sc->msk_stat_map, 1461 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1462 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_RST_SET); 1463 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_RST_CLR); 1464 /* Set the status list base address. */ 1465 addr = sc->msk_stat_ring_paddr; 1466 CSR_WRITE_4(sc, STAT_LIST_ADDR_LO, MSK_ADDR_LO(addr)); 1467 CSR_WRITE_4(sc, STAT_LIST_ADDR_HI, MSK_ADDR_HI(addr)); 1468 /* Set the status list last index. */ 1469 CSR_WRITE_2(sc, STAT_LAST_IDX, MSK_STAT_RING_CNT - 1); 1470 if (sc->msk_hw_id == CHIP_ID_YUKON_EC && 1471 sc->msk_hw_rev == CHIP_REV_YU_EC_A1) { 1472 /* WA for dev. #4.3 */ 1473 CSR_WRITE_2(sc, STAT_TX_IDX_TH, ST_TXTH_IDX_MASK); 1474 /* WA for dev. #4.18 */ 1475 CSR_WRITE_1(sc, STAT_FIFO_WM, 0x21); 1476 CSR_WRITE_1(sc, STAT_FIFO_ISR_WM, 0x07); 1477 } else { 1478 CSR_WRITE_2(sc, STAT_TX_IDX_TH, 0x0a); 1479 CSR_WRITE_1(sc, STAT_FIFO_WM, 0x10); 1480 if (sc->msk_hw_id == CHIP_ID_YUKON_XL && 1481 sc->msk_hw_rev == CHIP_REV_YU_XL_A0) 1482 CSR_WRITE_1(sc, STAT_FIFO_ISR_WM, 0x04); 1483 else 1484 CSR_WRITE_1(sc, STAT_FIFO_ISR_WM, 0x10); 1485 CSR_WRITE_4(sc, STAT_ISR_TIMER_INI, 0x0190); 1486 } 1487 /* 1488 * Use default value for STAT_ISR_TIMER_INI, STAT_LEV_TIMER_INI. 1489 */ 1490 CSR_WRITE_4(sc, STAT_TX_TIMER_INI, MSK_USECS(sc, 1000)); 1491 1492 /* Enable status unit. */ 1493 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_OP_ON); 1494 1495 CSR_WRITE_1(sc, STAT_TX_TIMER_CTRL, TIM_START); 1496 CSR_WRITE_1(sc, STAT_LEV_TIMER_CTRL, TIM_START); 1497 CSR_WRITE_1(sc, STAT_ISR_TIMER_CTRL, TIM_START); 1498 } 1499 1500 static int 1501 msk_probe(device_t dev) 1502 { 1503 struct msk_softc *sc; 1504 char desc[100]; 1505 1506 sc = device_get_softc(device_get_parent(dev)); 1507 /* 1508 * Not much to do here. We always know there will be 1509 * at least one GMAC present, and if there are two, 1510 * mskc_attach() will create a second device instance 1511 * for us. 1512 */ 1513 snprintf(desc, sizeof(desc), 1514 "Marvell Technology Group Ltd. %s Id 0x%02x Rev 0x%02x", 1515 model_name[sc->msk_hw_id - CHIP_ID_YUKON_XL], sc->msk_hw_id, 1516 sc->msk_hw_rev); 1517 device_set_desc_copy(dev, desc); 1518 1519 return (BUS_PROBE_DEFAULT); 1520 } 1521 1522 static int 1523 msk_attach(device_t dev) 1524 { 1525 struct msk_softc *sc; 1526 struct msk_if_softc *sc_if; 1527 struct ifnet *ifp; 1528 struct msk_mii_data *mmd; 1529 int i, port, error; 1530 uint8_t eaddr[6]; 1531 1532 if (dev == NULL) 1533 return (EINVAL); 1534 1535 error = 0; 1536 sc_if = device_get_softc(dev); 1537 sc = device_get_softc(device_get_parent(dev)); 1538 mmd = device_get_ivars(dev); 1539 port = mmd->port; 1540 1541 sc_if->msk_if_dev = dev; 1542 sc_if->msk_port = port; 1543 sc_if->msk_softc = sc; 1544 sc_if->msk_flags = sc->msk_pflags; 1545 sc->msk_if[port] = sc_if; 1546 /* Setup Tx/Rx queue register offsets. */ 1547 if (port == MSK_PORT_A) { 1548 sc_if->msk_txq = Q_XA1; 1549 sc_if->msk_txsq = Q_XS1; 1550 sc_if->msk_rxq = Q_R1; 1551 } else { 1552 sc_if->msk_txq = Q_XA2; 1553 sc_if->msk_txsq = Q_XS2; 1554 sc_if->msk_rxq = Q_R2; 1555 } 1556 1557 callout_init_mtx(&sc_if->msk_tick_ch, &sc_if->msk_softc->msk_mtx, 0); 1558 msk_sysctl_node(sc_if); 1559 1560 if ((error = msk_txrx_dma_alloc(sc_if) != 0)) 1561 goto fail; 1562 msk_rx_dma_jalloc(sc_if); 1563 1564 ifp = sc_if->msk_ifp = if_alloc(IFT_ETHER); 1565 if (ifp == NULL) { 1566 device_printf(sc_if->msk_if_dev, "can not if_alloc()\n"); 1567 error = ENOSPC; 1568 goto fail; 1569 } 1570 ifp->if_softc = sc_if; 1571 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1572 ifp->if_mtu = ETHERMTU; 1573 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1574 ifp->if_capabilities = IFCAP_TXCSUM | IFCAP_TSO4; 1575 /* 1576 * Enable Rx checksum offloading if controller supports 1577 * new descriptor formant and controller is not Yukon XL. 1578 */ 1579 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0 && 1580 sc->msk_hw_id != CHIP_ID_YUKON_XL) 1581 ifp->if_capabilities |= IFCAP_RXCSUM; 1582 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) != 0 && 1583 (sc_if->msk_flags & MSK_FLAG_NORX_CSUM) == 0) 1584 ifp->if_capabilities |= IFCAP_RXCSUM; 1585 ifp->if_hwassist = MSK_CSUM_FEATURES | CSUM_TSO; 1586 ifp->if_capenable = ifp->if_capabilities; 1587 ifp->if_ioctl = msk_ioctl; 1588 ifp->if_start = msk_start; 1589 ifp->if_init = msk_init; 1590 IFQ_SET_MAXLEN(&ifp->if_snd, MSK_TX_RING_CNT - 1); 1591 ifp->if_snd.ifq_drv_maxlen = MSK_TX_RING_CNT - 1; 1592 IFQ_SET_READY(&ifp->if_snd); 1593 /* 1594 * Get station address for this interface. Note that 1595 * dual port cards actually come with three station 1596 * addresses: one for each port, plus an extra. The 1597 * extra one is used by the SysKonnect driver software 1598 * as a 'virtual' station address for when both ports 1599 * are operating in failover mode. Currently we don't 1600 * use this extra address. 1601 */ 1602 MSK_IF_LOCK(sc_if); 1603 for (i = 0; i < ETHER_ADDR_LEN; i++) 1604 eaddr[i] = CSR_READ_1(sc, B2_MAC_1 + (port * 8) + i); 1605 1606 /* 1607 * Call MI attach routine. Can't hold locks when calling into ether_*. 1608 */ 1609 MSK_IF_UNLOCK(sc_if); 1610 ether_ifattach(ifp, eaddr); 1611 MSK_IF_LOCK(sc_if); 1612 1613 /* VLAN capability setup */ 1614 ifp->if_capabilities |= IFCAP_VLAN_MTU; 1615 if ((sc_if->msk_flags & MSK_FLAG_NOHWVLAN) == 0) { 1616 /* 1617 * Due to Tx checksum offload hardware bugs, msk(4) manually 1618 * computes checksum for short frames. For VLAN tagged frames 1619 * this workaround does not work so disable checksum offload 1620 * for VLAN interface. 1621 */ 1622 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWTSO; 1623 /* 1624 * Enable Rx checksum offloading for VLAN tagged frames 1625 * if controller support new descriptor format. 1626 */ 1627 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) != 0 && 1628 (sc_if->msk_flags & MSK_FLAG_NORX_CSUM) == 0) 1629 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM; 1630 } 1631 ifp->if_capenable = ifp->if_capabilities; 1632 1633 /* 1634 * Tell the upper layer(s) we support long frames. 1635 * Must appear after the call to ether_ifattach() because 1636 * ether_ifattach() sets ifi_hdrlen to the default value. 1637 */ 1638 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1639 1640 /* 1641 * Do miibus setup. 1642 */ 1643 MSK_IF_UNLOCK(sc_if); 1644 error = mii_attach(dev, &sc_if->msk_miibus, ifp, msk_mediachange, 1645 msk_mediastatus, BMSR_DEFCAPMASK, PHY_ADDR_MARV, MII_OFFSET_ANY, 1646 mmd->mii_flags); 1647 if (error != 0) { 1648 device_printf(sc_if->msk_if_dev, "attaching PHYs failed\n"); 1649 ether_ifdetach(ifp); 1650 error = ENXIO; 1651 goto fail; 1652 } 1653 1654 fail: 1655 if (error != 0) { 1656 /* Access should be ok even though lock has been dropped */ 1657 sc->msk_if[port] = NULL; 1658 msk_detach(dev); 1659 } 1660 1661 return (error); 1662 } 1663 1664 /* 1665 * Attach the interface. Allocate softc structures, do ifmedia 1666 * setup and ethernet/BPF attach. 1667 */ 1668 static int 1669 mskc_attach(device_t dev) 1670 { 1671 struct msk_softc *sc; 1672 struct msk_mii_data *mmd; 1673 int error, msic, msir, reg; 1674 1675 sc = device_get_softc(dev); 1676 sc->msk_dev = dev; 1677 mtx_init(&sc->msk_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1678 MTX_DEF); 1679 1680 /* 1681 * Map control/status registers. 1682 */ 1683 pci_enable_busmaster(dev); 1684 1685 /* Allocate I/O resource */ 1686 #ifdef MSK_USEIOSPACE 1687 sc->msk_res_spec = msk_res_spec_io; 1688 #else 1689 sc->msk_res_spec = msk_res_spec_mem; 1690 #endif 1691 sc->msk_irq_spec = msk_irq_spec_legacy; 1692 error = bus_alloc_resources(dev, sc->msk_res_spec, sc->msk_res); 1693 if (error) { 1694 if (sc->msk_res_spec == msk_res_spec_mem) 1695 sc->msk_res_spec = msk_res_spec_io; 1696 else 1697 sc->msk_res_spec = msk_res_spec_mem; 1698 error = bus_alloc_resources(dev, sc->msk_res_spec, sc->msk_res); 1699 if (error) { 1700 device_printf(dev, "couldn't allocate %s resources\n", 1701 sc->msk_res_spec == msk_res_spec_mem ? "memory" : 1702 "I/O"); 1703 mtx_destroy(&sc->msk_mtx); 1704 return (ENXIO); 1705 } 1706 } 1707 1708 CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR); 1709 sc->msk_hw_id = CSR_READ_1(sc, B2_CHIP_ID); 1710 sc->msk_hw_rev = (CSR_READ_1(sc, B2_MAC_CFG) >> 4) & 0x0f; 1711 /* Bail out if chip is not recognized. */ 1712 if (sc->msk_hw_id < CHIP_ID_YUKON_XL || 1713 sc->msk_hw_id > CHIP_ID_YUKON_OPT || 1714 sc->msk_hw_id == CHIP_ID_YUKON_SUPR || 1715 sc->msk_hw_id == CHIP_ID_YUKON_UNKNOWN) { 1716 device_printf(dev, "unknown device: id=0x%02x, rev=0x%02x\n", 1717 sc->msk_hw_id, sc->msk_hw_rev); 1718 mtx_destroy(&sc->msk_mtx); 1719 return (ENXIO); 1720 } 1721 1722 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 1723 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 1724 OID_AUTO, "process_limit", CTLTYPE_INT | CTLFLAG_RW, 1725 &sc->msk_process_limit, 0, sysctl_hw_msk_proc_limit, "I", 1726 "max number of Rx events to process"); 1727 1728 sc->msk_process_limit = MSK_PROC_DEFAULT; 1729 error = resource_int_value(device_get_name(dev), device_get_unit(dev), 1730 "process_limit", &sc->msk_process_limit); 1731 if (error == 0) { 1732 if (sc->msk_process_limit < MSK_PROC_MIN || 1733 sc->msk_process_limit > MSK_PROC_MAX) { 1734 device_printf(dev, "process_limit value out of range; " 1735 "using default: %d\n", MSK_PROC_DEFAULT); 1736 sc->msk_process_limit = MSK_PROC_DEFAULT; 1737 } 1738 } 1739 1740 sc->msk_int_holdoff = MSK_INT_HOLDOFF_DEFAULT; 1741 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 1742 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 1743 "int_holdoff", CTLFLAG_RW, &sc->msk_int_holdoff, 0, 1744 "Maximum number of time to delay interrupts"); 1745 resource_int_value(device_get_name(dev), device_get_unit(dev), 1746 "int_holdoff", &sc->msk_int_holdoff); 1747 1748 /* Soft reset. */ 1749 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); 1750 CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR); 1751 sc->msk_pmd = CSR_READ_1(sc, B2_PMD_TYP); 1752 /* Check number of MACs. */ 1753 sc->msk_num_port = 1; 1754 if ((CSR_READ_1(sc, B2_Y2_HW_RES) & CFG_DUAL_MAC_MSK) == 1755 CFG_DUAL_MAC_MSK) { 1756 if (!(CSR_READ_1(sc, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC)) 1757 sc->msk_num_port++; 1758 } 1759 1760 /* Check bus type. */ 1761 if (pci_find_extcap(sc->msk_dev, PCIY_EXPRESS, ®) == 0) { 1762 sc->msk_bustype = MSK_PEX_BUS; 1763 sc->msk_expcap = reg; 1764 } else if (pci_find_extcap(sc->msk_dev, PCIY_PCIX, ®) == 0) { 1765 sc->msk_bustype = MSK_PCIX_BUS; 1766 sc->msk_pcixcap = reg; 1767 } else 1768 sc->msk_bustype = MSK_PCI_BUS; 1769 1770 switch (sc->msk_hw_id) { 1771 case CHIP_ID_YUKON_EC: 1772 sc->msk_clock = 125; /* 125 MHz */ 1773 sc->msk_pflags |= MSK_FLAG_JUMBO; 1774 break; 1775 case CHIP_ID_YUKON_EC_U: 1776 sc->msk_clock = 125; /* 125 MHz */ 1777 sc->msk_pflags |= MSK_FLAG_JUMBO | MSK_FLAG_JUMBO_NOCSUM; 1778 break; 1779 case CHIP_ID_YUKON_EX: 1780 sc->msk_clock = 125; /* 125 MHz */ 1781 sc->msk_pflags |= MSK_FLAG_JUMBO | MSK_FLAG_DESCV2 | 1782 MSK_FLAG_AUTOTX_CSUM; 1783 /* 1784 * Yukon Extreme seems to have silicon bug for 1785 * automatic Tx checksum calculation capability. 1786 */ 1787 if (sc->msk_hw_rev == CHIP_REV_YU_EX_B0) 1788 sc->msk_pflags &= ~MSK_FLAG_AUTOTX_CSUM; 1789 /* 1790 * Yukon Extreme A0 could not use store-and-forward 1791 * for jumbo frames, so disable Tx checksum 1792 * offloading for jumbo frames. 1793 */ 1794 if (sc->msk_hw_rev == CHIP_REV_YU_EX_A0) 1795 sc->msk_pflags |= MSK_FLAG_JUMBO_NOCSUM; 1796 break; 1797 case CHIP_ID_YUKON_FE: 1798 sc->msk_clock = 100; /* 100 MHz */ 1799 sc->msk_pflags |= MSK_FLAG_FASTETHER; 1800 break; 1801 case CHIP_ID_YUKON_FE_P: 1802 sc->msk_clock = 50; /* 50 MHz */ 1803 sc->msk_pflags |= MSK_FLAG_FASTETHER | MSK_FLAG_DESCV2 | 1804 MSK_FLAG_AUTOTX_CSUM; 1805 if (sc->msk_hw_rev == CHIP_REV_YU_FE_P_A0) { 1806 /* 1807 * XXX 1808 * FE+ A0 has status LE writeback bug so msk(4) 1809 * does not rely on status word of received frame 1810 * in msk_rxeof() which in turn disables all 1811 * hardware assistance bits reported by the status 1812 * word as well as validity of the received frame. 1813 * Just pass received frames to upper stack with 1814 * minimal test and let upper stack handle them. 1815 */ 1816 sc->msk_pflags |= MSK_FLAG_NOHWVLAN | 1817 MSK_FLAG_NORXCHK | MSK_FLAG_NORX_CSUM; 1818 } 1819 break; 1820 case CHIP_ID_YUKON_XL: 1821 sc->msk_clock = 156; /* 156 MHz */ 1822 sc->msk_pflags |= MSK_FLAG_JUMBO; 1823 break; 1824 case CHIP_ID_YUKON_UL_2: 1825 sc->msk_clock = 125; /* 125 MHz */ 1826 sc->msk_pflags |= MSK_FLAG_JUMBO; 1827 break; 1828 case CHIP_ID_YUKON_OPT: 1829 sc->msk_clock = 125; /* 125 MHz */ 1830 sc->msk_pflags |= MSK_FLAG_JUMBO | MSK_FLAG_DESCV2; 1831 break; 1832 default: 1833 sc->msk_clock = 156; /* 156 MHz */ 1834 break; 1835 } 1836 1837 /* Allocate IRQ resources. */ 1838 msic = pci_msi_count(dev); 1839 if (bootverbose) 1840 device_printf(dev, "MSI count : %d\n", msic); 1841 if (legacy_intr != 0) 1842 msi_disable = 1; 1843 if (msi_disable == 0 && msic > 0) { 1844 msir = 1; 1845 if (pci_alloc_msi(dev, &msir) == 0) { 1846 if (msir == 1) { 1847 sc->msk_pflags |= MSK_FLAG_MSI; 1848 sc->msk_irq_spec = msk_irq_spec_msi; 1849 } else 1850 pci_release_msi(dev); 1851 } 1852 } 1853 1854 error = bus_alloc_resources(dev, sc->msk_irq_spec, sc->msk_irq); 1855 if (error) { 1856 device_printf(dev, "couldn't allocate IRQ resources\n"); 1857 goto fail; 1858 } 1859 1860 if ((error = msk_status_dma_alloc(sc)) != 0) 1861 goto fail; 1862 1863 /* Set base interrupt mask. */ 1864 sc->msk_intrmask = Y2_IS_HW_ERR | Y2_IS_STAT_BMU; 1865 sc->msk_intrhwemask = Y2_IS_TIST_OV | Y2_IS_MST_ERR | 1866 Y2_IS_IRQ_STAT | Y2_IS_PCI_EXP | Y2_IS_PCI_NEXP; 1867 1868 /* Reset the adapter. */ 1869 mskc_reset(sc); 1870 1871 if ((error = mskc_setup_rambuffer(sc)) != 0) 1872 goto fail; 1873 1874 sc->msk_devs[MSK_PORT_A] = device_add_child(dev, "msk", -1); 1875 if (sc->msk_devs[MSK_PORT_A] == NULL) { 1876 device_printf(dev, "failed to add child for PORT_A\n"); 1877 error = ENXIO; 1878 goto fail; 1879 } 1880 mmd = malloc(sizeof(struct msk_mii_data), M_DEVBUF, M_WAITOK | M_ZERO); 1881 if (mmd == NULL) { 1882 device_printf(dev, "failed to allocate memory for " 1883 "ivars of PORT_A\n"); 1884 error = ENXIO; 1885 goto fail; 1886 } 1887 mmd->port = MSK_PORT_A; 1888 mmd->pmd = sc->msk_pmd; 1889 if (sc->msk_pmd == 'L' || sc->msk_pmd == 'S') 1890 mmd->mii_flags |= MIIF_HAVEFIBER; 1891 if (sc->msk_pmd == 'P') 1892 mmd->mii_flags |= MIIF_HAVEFIBER | MIIF_MACPRIV0; 1893 device_set_ivars(sc->msk_devs[MSK_PORT_A], mmd); 1894 1895 if (sc->msk_num_port > 1) { 1896 sc->msk_devs[MSK_PORT_B] = device_add_child(dev, "msk", -1); 1897 if (sc->msk_devs[MSK_PORT_B] == NULL) { 1898 device_printf(dev, "failed to add child for PORT_B\n"); 1899 error = ENXIO; 1900 goto fail; 1901 } 1902 mmd = malloc(sizeof(struct msk_mii_data), M_DEVBUF, M_WAITOK | M_ZERO); 1903 if (mmd == NULL) { 1904 device_printf(dev, "failed to allocate memory for " 1905 "ivars of PORT_B\n"); 1906 error = ENXIO; 1907 goto fail; 1908 } 1909 mmd->port = MSK_PORT_B; 1910 mmd->pmd = sc->msk_pmd; 1911 if (sc->msk_pmd == 'L' || sc->msk_pmd == 'S') 1912 mmd->mii_flags |= MIIF_HAVEFIBER; 1913 if (sc->msk_pmd == 'P') 1914 mmd->mii_flags |= MIIF_HAVEFIBER | MIIF_MACPRIV0; 1915 device_set_ivars(sc->msk_devs[MSK_PORT_B], mmd); 1916 } 1917 1918 error = bus_generic_attach(dev); 1919 if (error) { 1920 device_printf(dev, "failed to attach port(s)\n"); 1921 goto fail; 1922 } 1923 1924 /* Hook interrupt last to avoid having to lock softc. */ 1925 error = bus_setup_intr(dev, sc->msk_irq[0], INTR_TYPE_NET | 1926 INTR_MPSAFE, NULL, msk_intr, sc, &sc->msk_intrhand); 1927 if (error != 0) { 1928 device_printf(dev, "couldn't set up interrupt handler\n"); 1929 goto fail; 1930 } 1931 fail: 1932 if (error != 0) 1933 mskc_detach(dev); 1934 1935 return (error); 1936 } 1937 1938 /* 1939 * Shutdown hardware and free up resources. This can be called any 1940 * time after the mutex has been initialized. It is called in both 1941 * the error case in attach and the normal detach case so it needs 1942 * to be careful about only freeing resources that have actually been 1943 * allocated. 1944 */ 1945 static int 1946 msk_detach(device_t dev) 1947 { 1948 struct msk_softc *sc; 1949 struct msk_if_softc *sc_if; 1950 struct ifnet *ifp; 1951 1952 sc_if = device_get_softc(dev); 1953 KASSERT(mtx_initialized(&sc_if->msk_softc->msk_mtx), 1954 ("msk mutex not initialized in msk_detach")); 1955 MSK_IF_LOCK(sc_if); 1956 1957 ifp = sc_if->msk_ifp; 1958 if (device_is_attached(dev)) { 1959 /* XXX */ 1960 sc_if->msk_flags |= MSK_FLAG_DETACH; 1961 msk_stop(sc_if); 1962 /* Can't hold locks while calling detach. */ 1963 MSK_IF_UNLOCK(sc_if); 1964 callout_drain(&sc_if->msk_tick_ch); 1965 ether_ifdetach(ifp); 1966 MSK_IF_LOCK(sc_if); 1967 } 1968 1969 /* 1970 * We're generally called from mskc_detach() which is using 1971 * device_delete_child() to get to here. It's already trashed 1972 * miibus for us, so don't do it here or we'll panic. 1973 * 1974 * if (sc_if->msk_miibus != NULL) { 1975 * device_delete_child(dev, sc_if->msk_miibus); 1976 * sc_if->msk_miibus = NULL; 1977 * } 1978 */ 1979 1980 msk_rx_dma_jfree(sc_if); 1981 msk_txrx_dma_free(sc_if); 1982 bus_generic_detach(dev); 1983 1984 if (ifp) 1985 if_free(ifp); 1986 sc = sc_if->msk_softc; 1987 sc->msk_if[sc_if->msk_port] = NULL; 1988 MSK_IF_UNLOCK(sc_if); 1989 1990 return (0); 1991 } 1992 1993 static int 1994 mskc_detach(device_t dev) 1995 { 1996 struct msk_softc *sc; 1997 1998 sc = device_get_softc(dev); 1999 KASSERT(mtx_initialized(&sc->msk_mtx), ("msk mutex not initialized")); 2000 2001 if (device_is_alive(dev)) { 2002 if (sc->msk_devs[MSK_PORT_A] != NULL) { 2003 free(device_get_ivars(sc->msk_devs[MSK_PORT_A]), 2004 M_DEVBUF); 2005 device_delete_child(dev, sc->msk_devs[MSK_PORT_A]); 2006 } 2007 if (sc->msk_devs[MSK_PORT_B] != NULL) { 2008 free(device_get_ivars(sc->msk_devs[MSK_PORT_B]), 2009 M_DEVBUF); 2010 device_delete_child(dev, sc->msk_devs[MSK_PORT_B]); 2011 } 2012 bus_generic_detach(dev); 2013 } 2014 2015 /* Disable all interrupts. */ 2016 CSR_WRITE_4(sc, B0_IMSK, 0); 2017 CSR_READ_4(sc, B0_IMSK); 2018 CSR_WRITE_4(sc, B0_HWE_IMSK, 0); 2019 CSR_READ_4(sc, B0_HWE_IMSK); 2020 2021 /* LED Off. */ 2022 CSR_WRITE_2(sc, B0_CTST, Y2_LED_STAT_OFF); 2023 2024 /* Put hardware reset. */ 2025 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); 2026 2027 msk_status_dma_free(sc); 2028 2029 if (sc->msk_intrhand) { 2030 bus_teardown_intr(dev, sc->msk_irq[0], sc->msk_intrhand); 2031 sc->msk_intrhand = NULL; 2032 } 2033 bus_release_resources(dev, sc->msk_irq_spec, sc->msk_irq); 2034 if ((sc->msk_pflags & MSK_FLAG_MSI) != 0) 2035 pci_release_msi(dev); 2036 bus_release_resources(dev, sc->msk_res_spec, sc->msk_res); 2037 mtx_destroy(&sc->msk_mtx); 2038 2039 return (0); 2040 } 2041 2042 struct msk_dmamap_arg { 2043 bus_addr_t msk_busaddr; 2044 }; 2045 2046 static void 2047 msk_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 2048 { 2049 struct msk_dmamap_arg *ctx; 2050 2051 if (error != 0) 2052 return; 2053 ctx = arg; 2054 ctx->msk_busaddr = segs[0].ds_addr; 2055 } 2056 2057 /* Create status DMA region. */ 2058 static int 2059 msk_status_dma_alloc(struct msk_softc *sc) 2060 { 2061 struct msk_dmamap_arg ctx; 2062 int error; 2063 2064 error = bus_dma_tag_create( 2065 bus_get_dma_tag(sc->msk_dev), /* parent */ 2066 MSK_STAT_ALIGN, 0, /* alignment, boundary */ 2067 BUS_SPACE_MAXADDR, /* lowaddr */ 2068 BUS_SPACE_MAXADDR, /* highaddr */ 2069 NULL, NULL, /* filter, filterarg */ 2070 MSK_STAT_RING_SZ, /* maxsize */ 2071 1, /* nsegments */ 2072 MSK_STAT_RING_SZ, /* maxsegsize */ 2073 0, /* flags */ 2074 NULL, NULL, /* lockfunc, lockarg */ 2075 &sc->msk_stat_tag); 2076 if (error != 0) { 2077 device_printf(sc->msk_dev, 2078 "failed to create status DMA tag\n"); 2079 return (error); 2080 } 2081 2082 /* Allocate DMA'able memory and load the DMA map for status ring. */ 2083 error = bus_dmamem_alloc(sc->msk_stat_tag, 2084 (void **)&sc->msk_stat_ring, BUS_DMA_WAITOK | BUS_DMA_COHERENT | 2085 BUS_DMA_ZERO, &sc->msk_stat_map); 2086 if (error != 0) { 2087 device_printf(sc->msk_dev, 2088 "failed to allocate DMA'able memory for status ring\n"); 2089 return (error); 2090 } 2091 2092 ctx.msk_busaddr = 0; 2093 error = bus_dmamap_load(sc->msk_stat_tag, 2094 sc->msk_stat_map, sc->msk_stat_ring, MSK_STAT_RING_SZ, 2095 msk_dmamap_cb, &ctx, 0); 2096 if (error != 0) { 2097 device_printf(sc->msk_dev, 2098 "failed to load DMA'able memory for status ring\n"); 2099 return (error); 2100 } 2101 sc->msk_stat_ring_paddr = ctx.msk_busaddr; 2102 2103 return (0); 2104 } 2105 2106 static void 2107 msk_status_dma_free(struct msk_softc *sc) 2108 { 2109 2110 /* Destroy status block. */ 2111 if (sc->msk_stat_tag) { 2112 if (sc->msk_stat_map) { 2113 bus_dmamap_unload(sc->msk_stat_tag, sc->msk_stat_map); 2114 if (sc->msk_stat_ring) { 2115 bus_dmamem_free(sc->msk_stat_tag, 2116 sc->msk_stat_ring, sc->msk_stat_map); 2117 sc->msk_stat_ring = NULL; 2118 } 2119 sc->msk_stat_map = NULL; 2120 } 2121 bus_dma_tag_destroy(sc->msk_stat_tag); 2122 sc->msk_stat_tag = NULL; 2123 } 2124 } 2125 2126 static int 2127 msk_txrx_dma_alloc(struct msk_if_softc *sc_if) 2128 { 2129 struct msk_dmamap_arg ctx; 2130 struct msk_txdesc *txd; 2131 struct msk_rxdesc *rxd; 2132 bus_size_t rxalign; 2133 int error, i; 2134 2135 /* Create parent DMA tag. */ 2136 /* 2137 * XXX 2138 * It seems that Yukon II supports full 64bits DMA operations. But 2139 * it needs two descriptors(list elements) for 64bits DMA operations. 2140 * Since we don't know what DMA address mappings(32bits or 64bits) 2141 * would be used in advance for each mbufs, we limits its DMA space 2142 * to be in range of 32bits address space. Otherwise, we should check 2143 * what DMA address is used and chain another descriptor for the 2144 * 64bits DMA operation. This also means descriptor ring size is 2145 * variable. Limiting DMA address to be in 32bit address space greatly 2146 * simplifies descriptor handling and possibly would increase 2147 * performance a bit due to efficient handling of descriptors. 2148 * Apart from harassing checksum offloading mechanisms, it seems 2149 * it's really bad idea to use a separate descriptor for 64bit 2150 * DMA operation to save small descriptor memory. Anyway, I've 2151 * never seen these exotic scheme on ethernet interface hardware. 2152 */ 2153 error = bus_dma_tag_create( 2154 bus_get_dma_tag(sc_if->msk_if_dev), /* parent */ 2155 1, 0, /* alignment, boundary */ 2156 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 2157 BUS_SPACE_MAXADDR, /* highaddr */ 2158 NULL, NULL, /* filter, filterarg */ 2159 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 2160 0, /* nsegments */ 2161 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 2162 0, /* flags */ 2163 NULL, NULL, /* lockfunc, lockarg */ 2164 &sc_if->msk_cdata.msk_parent_tag); 2165 if (error != 0) { 2166 device_printf(sc_if->msk_if_dev, 2167 "failed to create parent DMA tag\n"); 2168 goto fail; 2169 } 2170 /* Create tag for Tx ring. */ 2171 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2172 MSK_RING_ALIGN, 0, /* alignment, boundary */ 2173 BUS_SPACE_MAXADDR, /* lowaddr */ 2174 BUS_SPACE_MAXADDR, /* highaddr */ 2175 NULL, NULL, /* filter, filterarg */ 2176 MSK_TX_RING_SZ, /* maxsize */ 2177 1, /* nsegments */ 2178 MSK_TX_RING_SZ, /* maxsegsize */ 2179 0, /* flags */ 2180 NULL, NULL, /* lockfunc, lockarg */ 2181 &sc_if->msk_cdata.msk_tx_ring_tag); 2182 if (error != 0) { 2183 device_printf(sc_if->msk_if_dev, 2184 "failed to create Tx ring DMA tag\n"); 2185 goto fail; 2186 } 2187 2188 /* Create tag for Rx ring. */ 2189 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2190 MSK_RING_ALIGN, 0, /* alignment, boundary */ 2191 BUS_SPACE_MAXADDR, /* lowaddr */ 2192 BUS_SPACE_MAXADDR, /* highaddr */ 2193 NULL, NULL, /* filter, filterarg */ 2194 MSK_RX_RING_SZ, /* maxsize */ 2195 1, /* nsegments */ 2196 MSK_RX_RING_SZ, /* maxsegsize */ 2197 0, /* flags */ 2198 NULL, NULL, /* lockfunc, lockarg */ 2199 &sc_if->msk_cdata.msk_rx_ring_tag); 2200 if (error != 0) { 2201 device_printf(sc_if->msk_if_dev, 2202 "failed to create Rx ring DMA tag\n"); 2203 goto fail; 2204 } 2205 2206 /* Create tag for Tx buffers. */ 2207 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2208 1, 0, /* alignment, boundary */ 2209 BUS_SPACE_MAXADDR, /* lowaddr */ 2210 BUS_SPACE_MAXADDR, /* highaddr */ 2211 NULL, NULL, /* filter, filterarg */ 2212 MSK_TSO_MAXSIZE, /* maxsize */ 2213 MSK_MAXTXSEGS, /* nsegments */ 2214 MSK_TSO_MAXSGSIZE, /* maxsegsize */ 2215 0, /* flags */ 2216 NULL, NULL, /* lockfunc, lockarg */ 2217 &sc_if->msk_cdata.msk_tx_tag); 2218 if (error != 0) { 2219 device_printf(sc_if->msk_if_dev, 2220 "failed to create Tx DMA tag\n"); 2221 goto fail; 2222 } 2223 2224 rxalign = 1; 2225 /* 2226 * Workaround hardware hang which seems to happen when Rx buffer 2227 * is not aligned on multiple of FIFO word(8 bytes). 2228 */ 2229 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) != 0) 2230 rxalign = MSK_RX_BUF_ALIGN; 2231 /* Create tag for Rx buffers. */ 2232 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2233 rxalign, 0, /* alignment, boundary */ 2234 BUS_SPACE_MAXADDR, /* lowaddr */ 2235 BUS_SPACE_MAXADDR, /* highaddr */ 2236 NULL, NULL, /* filter, filterarg */ 2237 MCLBYTES, /* maxsize */ 2238 1, /* nsegments */ 2239 MCLBYTES, /* maxsegsize */ 2240 0, /* flags */ 2241 NULL, NULL, /* lockfunc, lockarg */ 2242 &sc_if->msk_cdata.msk_rx_tag); 2243 if (error != 0) { 2244 device_printf(sc_if->msk_if_dev, 2245 "failed to create Rx DMA tag\n"); 2246 goto fail; 2247 } 2248 2249 /* Allocate DMA'able memory and load the DMA map for Tx ring. */ 2250 error = bus_dmamem_alloc(sc_if->msk_cdata.msk_tx_ring_tag, 2251 (void **)&sc_if->msk_rdata.msk_tx_ring, BUS_DMA_WAITOK | 2252 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc_if->msk_cdata.msk_tx_ring_map); 2253 if (error != 0) { 2254 device_printf(sc_if->msk_if_dev, 2255 "failed to allocate DMA'able memory for Tx ring\n"); 2256 goto fail; 2257 } 2258 2259 ctx.msk_busaddr = 0; 2260 error = bus_dmamap_load(sc_if->msk_cdata.msk_tx_ring_tag, 2261 sc_if->msk_cdata.msk_tx_ring_map, sc_if->msk_rdata.msk_tx_ring, 2262 MSK_TX_RING_SZ, msk_dmamap_cb, &ctx, 0); 2263 if (error != 0) { 2264 device_printf(sc_if->msk_if_dev, 2265 "failed to load DMA'able memory for Tx ring\n"); 2266 goto fail; 2267 } 2268 sc_if->msk_rdata.msk_tx_ring_paddr = ctx.msk_busaddr; 2269 2270 /* Allocate DMA'able memory and load the DMA map for Rx ring. */ 2271 error = bus_dmamem_alloc(sc_if->msk_cdata.msk_rx_ring_tag, 2272 (void **)&sc_if->msk_rdata.msk_rx_ring, BUS_DMA_WAITOK | 2273 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc_if->msk_cdata.msk_rx_ring_map); 2274 if (error != 0) { 2275 device_printf(sc_if->msk_if_dev, 2276 "failed to allocate DMA'able memory for Rx ring\n"); 2277 goto fail; 2278 } 2279 2280 ctx.msk_busaddr = 0; 2281 error = bus_dmamap_load(sc_if->msk_cdata.msk_rx_ring_tag, 2282 sc_if->msk_cdata.msk_rx_ring_map, sc_if->msk_rdata.msk_rx_ring, 2283 MSK_RX_RING_SZ, msk_dmamap_cb, &ctx, 0); 2284 if (error != 0) { 2285 device_printf(sc_if->msk_if_dev, 2286 "failed to load DMA'able memory for Rx ring\n"); 2287 goto fail; 2288 } 2289 sc_if->msk_rdata.msk_rx_ring_paddr = ctx.msk_busaddr; 2290 2291 /* Create DMA maps for Tx buffers. */ 2292 for (i = 0; i < MSK_TX_RING_CNT; i++) { 2293 txd = &sc_if->msk_cdata.msk_txdesc[i]; 2294 txd->tx_m = NULL; 2295 txd->tx_dmamap = NULL; 2296 error = bus_dmamap_create(sc_if->msk_cdata.msk_tx_tag, 0, 2297 &txd->tx_dmamap); 2298 if (error != 0) { 2299 device_printf(sc_if->msk_if_dev, 2300 "failed to create Tx dmamap\n"); 2301 goto fail; 2302 } 2303 } 2304 /* Create DMA maps for Rx buffers. */ 2305 if ((error = bus_dmamap_create(sc_if->msk_cdata.msk_rx_tag, 0, 2306 &sc_if->msk_cdata.msk_rx_sparemap)) != 0) { 2307 device_printf(sc_if->msk_if_dev, 2308 "failed to create spare Rx dmamap\n"); 2309 goto fail; 2310 } 2311 for (i = 0; i < MSK_RX_RING_CNT; i++) { 2312 rxd = &sc_if->msk_cdata.msk_rxdesc[i]; 2313 rxd->rx_m = NULL; 2314 rxd->rx_dmamap = NULL; 2315 error = bus_dmamap_create(sc_if->msk_cdata.msk_rx_tag, 0, 2316 &rxd->rx_dmamap); 2317 if (error != 0) { 2318 device_printf(sc_if->msk_if_dev, 2319 "failed to create Rx dmamap\n"); 2320 goto fail; 2321 } 2322 } 2323 2324 fail: 2325 return (error); 2326 } 2327 2328 static int 2329 msk_rx_dma_jalloc(struct msk_if_softc *sc_if) 2330 { 2331 struct msk_dmamap_arg ctx; 2332 struct msk_rxdesc *jrxd; 2333 bus_size_t rxalign; 2334 int error, i; 2335 2336 if (jumbo_disable != 0 || (sc_if->msk_flags & MSK_FLAG_JUMBO) == 0) { 2337 sc_if->msk_flags &= ~MSK_FLAG_JUMBO; 2338 device_printf(sc_if->msk_if_dev, 2339 "disabling jumbo frame support\n"); 2340 return (0); 2341 } 2342 /* Create tag for jumbo Rx ring. */ 2343 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2344 MSK_RING_ALIGN, 0, /* alignment, boundary */ 2345 BUS_SPACE_MAXADDR, /* lowaddr */ 2346 BUS_SPACE_MAXADDR, /* highaddr */ 2347 NULL, NULL, /* filter, filterarg */ 2348 MSK_JUMBO_RX_RING_SZ, /* maxsize */ 2349 1, /* nsegments */ 2350 MSK_JUMBO_RX_RING_SZ, /* maxsegsize */ 2351 0, /* flags */ 2352 NULL, NULL, /* lockfunc, lockarg */ 2353 &sc_if->msk_cdata.msk_jumbo_rx_ring_tag); 2354 if (error != 0) { 2355 device_printf(sc_if->msk_if_dev, 2356 "failed to create jumbo Rx ring DMA tag\n"); 2357 goto jumbo_fail; 2358 } 2359 2360 rxalign = 1; 2361 /* 2362 * Workaround hardware hang which seems to happen when Rx buffer 2363 * is not aligned on multiple of FIFO word(8 bytes). 2364 */ 2365 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) != 0) 2366 rxalign = MSK_RX_BUF_ALIGN; 2367 /* Create tag for jumbo Rx buffers. */ 2368 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2369 rxalign, 0, /* alignment, boundary */ 2370 BUS_SPACE_MAXADDR, /* lowaddr */ 2371 BUS_SPACE_MAXADDR, /* highaddr */ 2372 NULL, NULL, /* filter, filterarg */ 2373 MJUM9BYTES, /* maxsize */ 2374 1, /* nsegments */ 2375 MJUM9BYTES, /* maxsegsize */ 2376 0, /* flags */ 2377 NULL, NULL, /* lockfunc, lockarg */ 2378 &sc_if->msk_cdata.msk_jumbo_rx_tag); 2379 if (error != 0) { 2380 device_printf(sc_if->msk_if_dev, 2381 "failed to create jumbo Rx DMA tag\n"); 2382 goto jumbo_fail; 2383 } 2384 2385 /* Allocate DMA'able memory and load the DMA map for jumbo Rx ring. */ 2386 error = bus_dmamem_alloc(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 2387 (void **)&sc_if->msk_rdata.msk_jumbo_rx_ring, 2388 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 2389 &sc_if->msk_cdata.msk_jumbo_rx_ring_map); 2390 if (error != 0) { 2391 device_printf(sc_if->msk_if_dev, 2392 "failed to allocate DMA'able memory for jumbo Rx ring\n"); 2393 goto jumbo_fail; 2394 } 2395 2396 ctx.msk_busaddr = 0; 2397 error = bus_dmamap_load(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 2398 sc_if->msk_cdata.msk_jumbo_rx_ring_map, 2399 sc_if->msk_rdata.msk_jumbo_rx_ring, MSK_JUMBO_RX_RING_SZ, 2400 msk_dmamap_cb, &ctx, 0); 2401 if (error != 0) { 2402 device_printf(sc_if->msk_if_dev, 2403 "failed to load DMA'able memory for jumbo Rx ring\n"); 2404 goto jumbo_fail; 2405 } 2406 sc_if->msk_rdata.msk_jumbo_rx_ring_paddr = ctx.msk_busaddr; 2407 2408 /* Create DMA maps for jumbo Rx buffers. */ 2409 if ((error = bus_dmamap_create(sc_if->msk_cdata.msk_jumbo_rx_tag, 0, 2410 &sc_if->msk_cdata.msk_jumbo_rx_sparemap)) != 0) { 2411 device_printf(sc_if->msk_if_dev, 2412 "failed to create spare jumbo Rx dmamap\n"); 2413 goto jumbo_fail; 2414 } 2415 for (i = 0; i < MSK_JUMBO_RX_RING_CNT; i++) { 2416 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[i]; 2417 jrxd->rx_m = NULL; 2418 jrxd->rx_dmamap = NULL; 2419 error = bus_dmamap_create(sc_if->msk_cdata.msk_jumbo_rx_tag, 0, 2420 &jrxd->rx_dmamap); 2421 if (error != 0) { 2422 device_printf(sc_if->msk_if_dev, 2423 "failed to create jumbo Rx dmamap\n"); 2424 goto jumbo_fail; 2425 } 2426 } 2427 2428 return (0); 2429 2430 jumbo_fail: 2431 msk_rx_dma_jfree(sc_if); 2432 device_printf(sc_if->msk_if_dev, "disabling jumbo frame support " 2433 "due to resource shortage\n"); 2434 sc_if->msk_flags &= ~MSK_FLAG_JUMBO; 2435 return (error); 2436 } 2437 2438 static void 2439 msk_txrx_dma_free(struct msk_if_softc *sc_if) 2440 { 2441 struct msk_txdesc *txd; 2442 struct msk_rxdesc *rxd; 2443 int i; 2444 2445 /* Tx ring. */ 2446 if (sc_if->msk_cdata.msk_tx_ring_tag) { 2447 if (sc_if->msk_cdata.msk_tx_ring_map) 2448 bus_dmamap_unload(sc_if->msk_cdata.msk_tx_ring_tag, 2449 sc_if->msk_cdata.msk_tx_ring_map); 2450 if (sc_if->msk_cdata.msk_tx_ring_map && 2451 sc_if->msk_rdata.msk_tx_ring) 2452 bus_dmamem_free(sc_if->msk_cdata.msk_tx_ring_tag, 2453 sc_if->msk_rdata.msk_tx_ring, 2454 sc_if->msk_cdata.msk_tx_ring_map); 2455 sc_if->msk_rdata.msk_tx_ring = NULL; 2456 sc_if->msk_cdata.msk_tx_ring_map = NULL; 2457 bus_dma_tag_destroy(sc_if->msk_cdata.msk_tx_ring_tag); 2458 sc_if->msk_cdata.msk_tx_ring_tag = NULL; 2459 } 2460 /* Rx ring. */ 2461 if (sc_if->msk_cdata.msk_rx_ring_tag) { 2462 if (sc_if->msk_cdata.msk_rx_ring_map) 2463 bus_dmamap_unload(sc_if->msk_cdata.msk_rx_ring_tag, 2464 sc_if->msk_cdata.msk_rx_ring_map); 2465 if (sc_if->msk_cdata.msk_rx_ring_map && 2466 sc_if->msk_rdata.msk_rx_ring) 2467 bus_dmamem_free(sc_if->msk_cdata.msk_rx_ring_tag, 2468 sc_if->msk_rdata.msk_rx_ring, 2469 sc_if->msk_cdata.msk_rx_ring_map); 2470 sc_if->msk_rdata.msk_rx_ring = NULL; 2471 sc_if->msk_cdata.msk_rx_ring_map = NULL; 2472 bus_dma_tag_destroy(sc_if->msk_cdata.msk_rx_ring_tag); 2473 sc_if->msk_cdata.msk_rx_ring_tag = NULL; 2474 } 2475 /* Tx buffers. */ 2476 if (sc_if->msk_cdata.msk_tx_tag) { 2477 for (i = 0; i < MSK_TX_RING_CNT; i++) { 2478 txd = &sc_if->msk_cdata.msk_txdesc[i]; 2479 if (txd->tx_dmamap) { 2480 bus_dmamap_destroy(sc_if->msk_cdata.msk_tx_tag, 2481 txd->tx_dmamap); 2482 txd->tx_dmamap = NULL; 2483 } 2484 } 2485 bus_dma_tag_destroy(sc_if->msk_cdata.msk_tx_tag); 2486 sc_if->msk_cdata.msk_tx_tag = NULL; 2487 } 2488 /* Rx buffers. */ 2489 if (sc_if->msk_cdata.msk_rx_tag) { 2490 for (i = 0; i < MSK_RX_RING_CNT; i++) { 2491 rxd = &sc_if->msk_cdata.msk_rxdesc[i]; 2492 if (rxd->rx_dmamap) { 2493 bus_dmamap_destroy(sc_if->msk_cdata.msk_rx_tag, 2494 rxd->rx_dmamap); 2495 rxd->rx_dmamap = NULL; 2496 } 2497 } 2498 if (sc_if->msk_cdata.msk_rx_sparemap) { 2499 bus_dmamap_destroy(sc_if->msk_cdata.msk_rx_tag, 2500 sc_if->msk_cdata.msk_rx_sparemap); 2501 sc_if->msk_cdata.msk_rx_sparemap = 0; 2502 } 2503 bus_dma_tag_destroy(sc_if->msk_cdata.msk_rx_tag); 2504 sc_if->msk_cdata.msk_rx_tag = NULL; 2505 } 2506 if (sc_if->msk_cdata.msk_parent_tag) { 2507 bus_dma_tag_destroy(sc_if->msk_cdata.msk_parent_tag); 2508 sc_if->msk_cdata.msk_parent_tag = NULL; 2509 } 2510 } 2511 2512 static void 2513 msk_rx_dma_jfree(struct msk_if_softc *sc_if) 2514 { 2515 struct msk_rxdesc *jrxd; 2516 int i; 2517 2518 /* Jumbo Rx ring. */ 2519 if (sc_if->msk_cdata.msk_jumbo_rx_ring_tag) { 2520 if (sc_if->msk_cdata.msk_jumbo_rx_ring_map) 2521 bus_dmamap_unload(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 2522 sc_if->msk_cdata.msk_jumbo_rx_ring_map); 2523 if (sc_if->msk_cdata.msk_jumbo_rx_ring_map && 2524 sc_if->msk_rdata.msk_jumbo_rx_ring) 2525 bus_dmamem_free(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 2526 sc_if->msk_rdata.msk_jumbo_rx_ring, 2527 sc_if->msk_cdata.msk_jumbo_rx_ring_map); 2528 sc_if->msk_rdata.msk_jumbo_rx_ring = NULL; 2529 sc_if->msk_cdata.msk_jumbo_rx_ring_map = NULL; 2530 bus_dma_tag_destroy(sc_if->msk_cdata.msk_jumbo_rx_ring_tag); 2531 sc_if->msk_cdata.msk_jumbo_rx_ring_tag = NULL; 2532 } 2533 /* Jumbo Rx buffers. */ 2534 if (sc_if->msk_cdata.msk_jumbo_rx_tag) { 2535 for (i = 0; i < MSK_JUMBO_RX_RING_CNT; i++) { 2536 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[i]; 2537 if (jrxd->rx_dmamap) { 2538 bus_dmamap_destroy( 2539 sc_if->msk_cdata.msk_jumbo_rx_tag, 2540 jrxd->rx_dmamap); 2541 jrxd->rx_dmamap = NULL; 2542 } 2543 } 2544 if (sc_if->msk_cdata.msk_jumbo_rx_sparemap) { 2545 bus_dmamap_destroy(sc_if->msk_cdata.msk_jumbo_rx_tag, 2546 sc_if->msk_cdata.msk_jumbo_rx_sparemap); 2547 sc_if->msk_cdata.msk_jumbo_rx_sparemap = 0; 2548 } 2549 bus_dma_tag_destroy(sc_if->msk_cdata.msk_jumbo_rx_tag); 2550 sc_if->msk_cdata.msk_jumbo_rx_tag = NULL; 2551 } 2552 } 2553 2554 static int 2555 msk_encap(struct msk_if_softc *sc_if, struct mbuf **m_head) 2556 { 2557 struct msk_txdesc *txd, *txd_last; 2558 struct msk_tx_desc *tx_le; 2559 struct mbuf *m; 2560 bus_dmamap_t map; 2561 bus_dma_segment_t txsegs[MSK_MAXTXSEGS]; 2562 uint32_t control, csum, prod, si; 2563 uint16_t offset, tcp_offset, tso_mtu; 2564 int error, i, nseg, tso; 2565 2566 MSK_IF_LOCK_ASSERT(sc_if); 2567 2568 tcp_offset = offset = 0; 2569 m = *m_head; 2570 if (((sc_if->msk_flags & MSK_FLAG_AUTOTX_CSUM) == 0 && 2571 (m->m_pkthdr.csum_flags & MSK_CSUM_FEATURES) != 0) || 2572 ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0 && 2573 (m->m_pkthdr.csum_flags & CSUM_TSO) != 0)) { 2574 /* 2575 * Since mbuf has no protocol specific structure information 2576 * in it we have to inspect protocol information here to 2577 * setup TSO and checksum offload. I don't know why Marvell 2578 * made a such decision in chip design because other GigE 2579 * hardwares normally takes care of all these chores in 2580 * hardware. However, TSO performance of Yukon II is very 2581 * good such that it's worth to implement it. 2582 */ 2583 struct ether_header *eh; 2584 struct ip *ip; 2585 struct tcphdr *tcp; 2586 2587 if (M_WRITABLE(m) == 0) { 2588 /* Get a writable copy. */ 2589 m = m_dup(*m_head, M_DONTWAIT); 2590 m_freem(*m_head); 2591 if (m == NULL) { 2592 *m_head = NULL; 2593 return (ENOBUFS); 2594 } 2595 *m_head = m; 2596 } 2597 2598 offset = sizeof(struct ether_header); 2599 m = m_pullup(m, offset); 2600 if (m == NULL) { 2601 *m_head = NULL; 2602 return (ENOBUFS); 2603 } 2604 eh = mtod(m, struct ether_header *); 2605 /* Check if hardware VLAN insertion is off. */ 2606 if (eh->ether_type == htons(ETHERTYPE_VLAN)) { 2607 offset = sizeof(struct ether_vlan_header); 2608 m = m_pullup(m, offset); 2609 if (m == NULL) { 2610 *m_head = NULL; 2611 return (ENOBUFS); 2612 } 2613 } 2614 m = m_pullup(m, offset + sizeof(struct ip)); 2615 if (m == NULL) { 2616 *m_head = NULL; 2617 return (ENOBUFS); 2618 } 2619 ip = (struct ip *)(mtod(m, char *) + offset); 2620 offset += (ip->ip_hl << 2); 2621 tcp_offset = offset; 2622 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 2623 m = m_pullup(m, offset + sizeof(struct tcphdr)); 2624 if (m == NULL) { 2625 *m_head = NULL; 2626 return (ENOBUFS); 2627 } 2628 tcp = (struct tcphdr *)(mtod(m, char *) + offset); 2629 offset += (tcp->th_off << 2); 2630 } else if ((sc_if->msk_flags & MSK_FLAG_AUTOTX_CSUM) == 0 && 2631 (m->m_pkthdr.len < MSK_MIN_FRAMELEN) && 2632 (m->m_pkthdr.csum_flags & CSUM_TCP) != 0) { 2633 /* 2634 * It seems that Yukon II has Tx checksum offload bug 2635 * for small TCP packets that's less than 60 bytes in 2636 * size (e.g. TCP window probe packet, pure ACK packet). 2637 * Common work around like padding with zeros to make 2638 * the frame minimum ethernet frame size didn't work at 2639 * all. 2640 * Instead of disabling checksum offload completely we 2641 * resort to S/W checksum routine when we encounter 2642 * short TCP frames. 2643 * Short UDP packets appear to be handled correctly by 2644 * Yukon II. Also I assume this bug does not happen on 2645 * controllers that use newer descriptor format or 2646 * automatic Tx checksum calculation. 2647 */ 2648 m = m_pullup(m, offset + sizeof(struct tcphdr)); 2649 if (m == NULL) { 2650 *m_head = NULL; 2651 return (ENOBUFS); 2652 } 2653 *(uint16_t *)(m->m_data + offset + 2654 m->m_pkthdr.csum_data) = in_cksum_skip(m, 2655 m->m_pkthdr.len, offset); 2656 m->m_pkthdr.csum_flags &= ~CSUM_TCP; 2657 } 2658 *m_head = m; 2659 } 2660 2661 prod = sc_if->msk_cdata.msk_tx_prod; 2662 txd = &sc_if->msk_cdata.msk_txdesc[prod]; 2663 txd_last = txd; 2664 map = txd->tx_dmamap; 2665 error = bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_tx_tag, map, 2666 *m_head, txsegs, &nseg, BUS_DMA_NOWAIT); 2667 if (error == EFBIG) { 2668 m = m_collapse(*m_head, M_DONTWAIT, MSK_MAXTXSEGS); 2669 if (m == NULL) { 2670 m_freem(*m_head); 2671 *m_head = NULL; 2672 return (ENOBUFS); 2673 } 2674 *m_head = m; 2675 error = bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_tx_tag, 2676 map, *m_head, txsegs, &nseg, BUS_DMA_NOWAIT); 2677 if (error != 0) { 2678 m_freem(*m_head); 2679 *m_head = NULL; 2680 return (error); 2681 } 2682 } else if (error != 0) 2683 return (error); 2684 if (nseg == 0) { 2685 m_freem(*m_head); 2686 *m_head = NULL; 2687 return (EIO); 2688 } 2689 2690 /* Check number of available descriptors. */ 2691 if (sc_if->msk_cdata.msk_tx_cnt + nseg >= 2692 (MSK_TX_RING_CNT - MSK_RESERVED_TX_DESC_CNT)) { 2693 bus_dmamap_unload(sc_if->msk_cdata.msk_tx_tag, map); 2694 return (ENOBUFS); 2695 } 2696 2697 control = 0; 2698 tso = 0; 2699 tx_le = NULL; 2700 2701 /* Check TSO support. */ 2702 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 2703 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) != 0) 2704 tso_mtu = m->m_pkthdr.tso_segsz; 2705 else 2706 tso_mtu = offset + m->m_pkthdr.tso_segsz; 2707 if (tso_mtu != sc_if->msk_cdata.msk_tso_mtu) { 2708 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2709 tx_le->msk_addr = htole32(tso_mtu); 2710 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) != 0) 2711 tx_le->msk_control = htole32(OP_MSS | HW_OWNER); 2712 else 2713 tx_le->msk_control = 2714 htole32(OP_LRGLEN | HW_OWNER); 2715 sc_if->msk_cdata.msk_tx_cnt++; 2716 MSK_INC(prod, MSK_TX_RING_CNT); 2717 sc_if->msk_cdata.msk_tso_mtu = tso_mtu; 2718 } 2719 tso++; 2720 } 2721 /* Check if we have a VLAN tag to insert. */ 2722 if ((m->m_flags & M_VLANTAG) != 0) { 2723 if (tx_le == NULL) { 2724 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2725 tx_le->msk_addr = htole32(0); 2726 tx_le->msk_control = htole32(OP_VLAN | HW_OWNER | 2727 htons(m->m_pkthdr.ether_vtag)); 2728 sc_if->msk_cdata.msk_tx_cnt++; 2729 MSK_INC(prod, MSK_TX_RING_CNT); 2730 } else { 2731 tx_le->msk_control |= htole32(OP_VLAN | 2732 htons(m->m_pkthdr.ether_vtag)); 2733 } 2734 control |= INS_VLAN; 2735 } 2736 /* Check if we have to handle checksum offload. */ 2737 if (tso == 0 && (m->m_pkthdr.csum_flags & MSK_CSUM_FEATURES) != 0) { 2738 if ((sc_if->msk_flags & MSK_FLAG_AUTOTX_CSUM) != 0) 2739 control |= CALSUM; 2740 else { 2741 control |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM; 2742 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0) 2743 control |= UDPTCP; 2744 /* Checksum write position. */ 2745 csum = (tcp_offset + m->m_pkthdr.csum_data) & 0xffff; 2746 /* Checksum start position. */ 2747 csum |= (uint32_t)tcp_offset << 16; 2748 if (csum != sc_if->msk_cdata.msk_last_csum) { 2749 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2750 tx_le->msk_addr = htole32(csum); 2751 tx_le->msk_control = htole32(1 << 16 | 2752 (OP_TCPLISW | HW_OWNER)); 2753 sc_if->msk_cdata.msk_tx_cnt++; 2754 MSK_INC(prod, MSK_TX_RING_CNT); 2755 sc_if->msk_cdata.msk_last_csum = csum; 2756 } 2757 } 2758 } 2759 2760 si = prod; 2761 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2762 tx_le->msk_addr = htole32(MSK_ADDR_LO(txsegs[0].ds_addr)); 2763 if (tso == 0) 2764 tx_le->msk_control = htole32(txsegs[0].ds_len | control | 2765 OP_PACKET); 2766 else 2767 tx_le->msk_control = htole32(txsegs[0].ds_len | control | 2768 OP_LARGESEND); 2769 sc_if->msk_cdata.msk_tx_cnt++; 2770 MSK_INC(prod, MSK_TX_RING_CNT); 2771 2772 for (i = 1; i < nseg; i++) { 2773 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2774 tx_le->msk_addr = htole32(MSK_ADDR_LO(txsegs[i].ds_addr)); 2775 tx_le->msk_control = htole32(txsegs[i].ds_len | control | 2776 OP_BUFFER | HW_OWNER); 2777 sc_if->msk_cdata.msk_tx_cnt++; 2778 MSK_INC(prod, MSK_TX_RING_CNT); 2779 } 2780 /* Update producer index. */ 2781 sc_if->msk_cdata.msk_tx_prod = prod; 2782 2783 /* Set EOP on the last descriptor. */ 2784 prod = (prod + MSK_TX_RING_CNT - 1) % MSK_TX_RING_CNT; 2785 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2786 tx_le->msk_control |= htole32(EOP); 2787 2788 /* Turn the first descriptor ownership to hardware. */ 2789 tx_le = &sc_if->msk_rdata.msk_tx_ring[si]; 2790 tx_le->msk_control |= htole32(HW_OWNER); 2791 2792 txd = &sc_if->msk_cdata.msk_txdesc[prod]; 2793 map = txd_last->tx_dmamap; 2794 txd_last->tx_dmamap = txd->tx_dmamap; 2795 txd->tx_dmamap = map; 2796 txd->tx_m = m; 2797 2798 /* Sync descriptors. */ 2799 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_tag, map, BUS_DMASYNC_PREWRITE); 2800 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_ring_tag, 2801 sc_if->msk_cdata.msk_tx_ring_map, 2802 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2803 2804 return (0); 2805 } 2806 2807 static void 2808 msk_start(struct ifnet *ifp) 2809 { 2810 struct msk_if_softc *sc_if; 2811 2812 sc_if = ifp->if_softc; 2813 MSK_IF_LOCK(sc_if); 2814 msk_start_locked(ifp); 2815 MSK_IF_UNLOCK(sc_if); 2816 } 2817 2818 static void 2819 msk_start_locked(struct ifnet *ifp) 2820 { 2821 struct msk_if_softc *sc_if; 2822 struct mbuf *m_head; 2823 int enq; 2824 2825 sc_if = ifp->if_softc; 2826 MSK_IF_LOCK_ASSERT(sc_if); 2827 2828 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2829 IFF_DRV_RUNNING || (sc_if->msk_flags & MSK_FLAG_LINK) == 0) 2830 return; 2831 2832 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 2833 sc_if->msk_cdata.msk_tx_cnt < 2834 (MSK_TX_RING_CNT - MSK_RESERVED_TX_DESC_CNT); ) { 2835 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2836 if (m_head == NULL) 2837 break; 2838 /* 2839 * Pack the data into the transmit ring. If we 2840 * don't have room, set the OACTIVE flag and wait 2841 * for the NIC to drain the ring. 2842 */ 2843 if (msk_encap(sc_if, &m_head) != 0) { 2844 if (m_head == NULL) 2845 break; 2846 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2847 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2848 break; 2849 } 2850 2851 enq++; 2852 /* 2853 * If there's a BPF listener, bounce a copy of this frame 2854 * to him. 2855 */ 2856 ETHER_BPF_MTAP(ifp, m_head); 2857 } 2858 2859 if (enq > 0) { 2860 /* Transmit */ 2861 CSR_WRITE_2(sc_if->msk_softc, 2862 Y2_PREF_Q_ADDR(sc_if->msk_txq, PREF_UNIT_PUT_IDX_REG), 2863 sc_if->msk_cdata.msk_tx_prod); 2864 2865 /* Set a timeout in case the chip goes out to lunch. */ 2866 sc_if->msk_watchdog_timer = MSK_TX_TIMEOUT; 2867 } 2868 } 2869 2870 static void 2871 msk_watchdog(struct msk_if_softc *sc_if) 2872 { 2873 struct ifnet *ifp; 2874 2875 MSK_IF_LOCK_ASSERT(sc_if); 2876 2877 if (sc_if->msk_watchdog_timer == 0 || --sc_if->msk_watchdog_timer) 2878 return; 2879 ifp = sc_if->msk_ifp; 2880 if ((sc_if->msk_flags & MSK_FLAG_LINK) == 0) { 2881 if (bootverbose) 2882 if_printf(sc_if->msk_ifp, "watchdog timeout " 2883 "(missed link)\n"); 2884 ifp->if_oerrors++; 2885 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2886 msk_init_locked(sc_if); 2887 return; 2888 } 2889 2890 if_printf(ifp, "watchdog timeout\n"); 2891 ifp->if_oerrors++; 2892 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2893 msk_init_locked(sc_if); 2894 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2895 msk_start_locked(ifp); 2896 } 2897 2898 static int 2899 mskc_shutdown(device_t dev) 2900 { 2901 struct msk_softc *sc; 2902 int i; 2903 2904 sc = device_get_softc(dev); 2905 MSK_LOCK(sc); 2906 for (i = 0; i < sc->msk_num_port; i++) { 2907 if (sc->msk_if[i] != NULL && sc->msk_if[i]->msk_ifp != NULL && 2908 ((sc->msk_if[i]->msk_ifp->if_drv_flags & 2909 IFF_DRV_RUNNING) != 0)) 2910 msk_stop(sc->msk_if[i]); 2911 } 2912 MSK_UNLOCK(sc); 2913 2914 /* Put hardware reset. */ 2915 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); 2916 return (0); 2917 } 2918 2919 static int 2920 mskc_suspend(device_t dev) 2921 { 2922 struct msk_softc *sc; 2923 int i; 2924 2925 sc = device_get_softc(dev); 2926 2927 MSK_LOCK(sc); 2928 2929 for (i = 0; i < sc->msk_num_port; i++) { 2930 if (sc->msk_if[i] != NULL && sc->msk_if[i]->msk_ifp != NULL && 2931 ((sc->msk_if[i]->msk_ifp->if_drv_flags & 2932 IFF_DRV_RUNNING) != 0)) 2933 msk_stop(sc->msk_if[i]); 2934 } 2935 2936 /* Disable all interrupts. */ 2937 CSR_WRITE_4(sc, B0_IMSK, 0); 2938 CSR_READ_4(sc, B0_IMSK); 2939 CSR_WRITE_4(sc, B0_HWE_IMSK, 0); 2940 CSR_READ_4(sc, B0_HWE_IMSK); 2941 2942 msk_phy_power(sc, MSK_PHY_POWERDOWN); 2943 2944 /* Put hardware reset. */ 2945 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); 2946 sc->msk_pflags |= MSK_FLAG_SUSPEND; 2947 2948 MSK_UNLOCK(sc); 2949 2950 return (0); 2951 } 2952 2953 static int 2954 mskc_resume(device_t dev) 2955 { 2956 struct msk_softc *sc; 2957 int i; 2958 2959 sc = device_get_softc(dev); 2960 2961 MSK_LOCK(sc); 2962 2963 mskc_reset(sc); 2964 for (i = 0; i < sc->msk_num_port; i++) { 2965 if (sc->msk_if[i] != NULL && sc->msk_if[i]->msk_ifp != NULL && 2966 ((sc->msk_if[i]->msk_ifp->if_flags & IFF_UP) != 0)) { 2967 sc->msk_if[i]->msk_ifp->if_drv_flags &= 2968 ~IFF_DRV_RUNNING; 2969 msk_init_locked(sc->msk_if[i]); 2970 } 2971 } 2972 sc->msk_pflags &= ~MSK_FLAG_SUSPEND; 2973 2974 MSK_UNLOCK(sc); 2975 2976 return (0); 2977 } 2978 2979 #ifndef __NO_STRICT_ALIGNMENT 2980 static __inline void 2981 msk_fixup_rx(struct mbuf *m) 2982 { 2983 int i; 2984 uint16_t *src, *dst; 2985 2986 src = mtod(m, uint16_t *); 2987 dst = src - 3; 2988 2989 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 2990 *dst++ = *src++; 2991 2992 m->m_data -= (MSK_RX_BUF_ALIGN - ETHER_ALIGN); 2993 } 2994 #endif 2995 2996 static __inline void 2997 msk_rxcsum(struct msk_if_softc *sc_if, uint32_t control, struct mbuf *m) 2998 { 2999 struct ether_header *eh; 3000 struct ip *ip; 3001 struct udphdr *uh; 3002 int32_t hlen, len, pktlen, temp32; 3003 uint16_t csum, *opts; 3004 3005 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) != 0) { 3006 if ((control & (CSS_IPV4 | CSS_IPFRAG)) == CSS_IPV4) { 3007 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 3008 if ((control & CSS_IPV4_CSUM_OK) != 0) 3009 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 3010 if ((control & (CSS_TCP | CSS_UDP)) != 0 && 3011 (control & (CSS_TCPUDP_CSUM_OK)) != 0) { 3012 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID | 3013 CSUM_PSEUDO_HDR; 3014 m->m_pkthdr.csum_data = 0xffff; 3015 } 3016 } 3017 return; 3018 } 3019 /* 3020 * Marvell Yukon controllers that support OP_RXCHKS has known 3021 * to have various Rx checksum offloading bugs. These 3022 * controllers can be configured to compute simple checksum 3023 * at two different positions. So we can compute IP and TCP/UDP 3024 * checksum at the same time. We intentionally have controller 3025 * compute TCP/UDP checksum twice by specifying the same 3026 * checksum start position and compare the result. If the value 3027 * is different it would indicate the hardware logic was wrong. 3028 */ 3029 if ((sc_if->msk_csum & 0xFFFF) != (sc_if->msk_csum >> 16)) { 3030 if (bootverbose) 3031 device_printf(sc_if->msk_if_dev, 3032 "Rx checksum value mismatch!\n"); 3033 return; 3034 } 3035 pktlen = m->m_pkthdr.len; 3036 if (pktlen < sizeof(struct ether_header) + sizeof(struct ip)) 3037 return; 3038 eh = mtod(m, struct ether_header *); 3039 if (eh->ether_type != htons(ETHERTYPE_IP)) 3040 return; 3041 ip = (struct ip *)(eh + 1); 3042 if (ip->ip_v != IPVERSION) 3043 return; 3044 3045 hlen = ip->ip_hl << 2; 3046 pktlen -= sizeof(struct ether_header); 3047 if (hlen < sizeof(struct ip)) 3048 return; 3049 if (ntohs(ip->ip_len) < hlen) 3050 return; 3051 if (ntohs(ip->ip_len) != pktlen) 3052 return; 3053 if (ip->ip_off & htons(IP_MF | IP_OFFMASK)) 3054 return; /* can't handle fragmented packet. */ 3055 3056 switch (ip->ip_p) { 3057 case IPPROTO_TCP: 3058 if (pktlen < (hlen + sizeof(struct tcphdr))) 3059 return; 3060 break; 3061 case IPPROTO_UDP: 3062 if (pktlen < (hlen + sizeof(struct udphdr))) 3063 return; 3064 uh = (struct udphdr *)((caddr_t)ip + hlen); 3065 if (uh->uh_sum == 0) 3066 return; /* no checksum */ 3067 break; 3068 default: 3069 return; 3070 } 3071 csum = ntohs(sc_if->msk_csum & 0xFFFF); 3072 /* Checksum fixup for IP options. */ 3073 len = hlen - sizeof(struct ip); 3074 if (len > 0) { 3075 opts = (uint16_t *)(ip + 1); 3076 for (; len > 0; len -= sizeof(uint16_t), opts++) { 3077 temp32 = csum - *opts; 3078 temp32 = (temp32 >> 16) + (temp32 & 65535); 3079 csum = temp32 & 65535; 3080 } 3081 } 3082 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID; 3083 m->m_pkthdr.csum_data = csum; 3084 } 3085 3086 static void 3087 msk_rxeof(struct msk_if_softc *sc_if, uint32_t status, uint32_t control, 3088 int len) 3089 { 3090 struct mbuf *m; 3091 struct ifnet *ifp; 3092 struct msk_rxdesc *rxd; 3093 int cons, rxlen; 3094 3095 ifp = sc_if->msk_ifp; 3096 3097 MSK_IF_LOCK_ASSERT(sc_if); 3098 3099 cons = sc_if->msk_cdata.msk_rx_cons; 3100 do { 3101 rxlen = status >> 16; 3102 if ((status & GMR_FS_VLAN) != 0 && 3103 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 3104 rxlen -= ETHER_VLAN_ENCAP_LEN; 3105 if ((sc_if->msk_flags & MSK_FLAG_NORXCHK) != 0) { 3106 /* 3107 * For controllers that returns bogus status code 3108 * just do minimal check and let upper stack 3109 * handle this frame. 3110 */ 3111 if (len > MSK_MAX_FRAMELEN || len < ETHER_HDR_LEN) { 3112 ifp->if_ierrors++; 3113 msk_discard_rxbuf(sc_if, cons); 3114 break; 3115 } 3116 } else if (len > sc_if->msk_framesize || 3117 ((status & GMR_FS_ANY_ERR) != 0) || 3118 ((status & GMR_FS_RX_OK) == 0) || (rxlen != len)) { 3119 /* Don't count flow-control packet as errors. */ 3120 if ((status & GMR_FS_GOOD_FC) == 0) 3121 ifp->if_ierrors++; 3122 msk_discard_rxbuf(sc_if, cons); 3123 break; 3124 } 3125 rxd = &sc_if->msk_cdata.msk_rxdesc[cons]; 3126 m = rxd->rx_m; 3127 if (msk_newbuf(sc_if, cons) != 0) { 3128 ifp->if_iqdrops++; 3129 /* Reuse old buffer. */ 3130 msk_discard_rxbuf(sc_if, cons); 3131 break; 3132 } 3133 m->m_pkthdr.rcvif = ifp; 3134 m->m_pkthdr.len = m->m_len = len; 3135 #ifndef __NO_STRICT_ALIGNMENT 3136 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) != 0) 3137 msk_fixup_rx(m); 3138 #endif 3139 ifp->if_ipackets++; 3140 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 3141 msk_rxcsum(sc_if, control, m); 3142 /* Check for VLAN tagged packets. */ 3143 if ((status & GMR_FS_VLAN) != 0 && 3144 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) { 3145 m->m_pkthdr.ether_vtag = sc_if->msk_vtag; 3146 m->m_flags |= M_VLANTAG; 3147 } 3148 MSK_IF_UNLOCK(sc_if); 3149 (*ifp->if_input)(ifp, m); 3150 MSK_IF_LOCK(sc_if); 3151 } while (0); 3152 3153 MSK_INC(sc_if->msk_cdata.msk_rx_cons, MSK_RX_RING_CNT); 3154 MSK_INC(sc_if->msk_cdata.msk_rx_prod, MSK_RX_RING_CNT); 3155 } 3156 3157 static void 3158 msk_jumbo_rxeof(struct msk_if_softc *sc_if, uint32_t status, uint32_t control, 3159 int len) 3160 { 3161 struct mbuf *m; 3162 struct ifnet *ifp; 3163 struct msk_rxdesc *jrxd; 3164 int cons, rxlen; 3165 3166 ifp = sc_if->msk_ifp; 3167 3168 MSK_IF_LOCK_ASSERT(sc_if); 3169 3170 cons = sc_if->msk_cdata.msk_rx_cons; 3171 do { 3172 rxlen = status >> 16; 3173 if ((status & GMR_FS_VLAN) != 0 && 3174 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 3175 rxlen -= ETHER_VLAN_ENCAP_LEN; 3176 if (len > sc_if->msk_framesize || 3177 ((status & GMR_FS_ANY_ERR) != 0) || 3178 ((status & GMR_FS_RX_OK) == 0) || (rxlen != len)) { 3179 /* Don't count flow-control packet as errors. */ 3180 if ((status & GMR_FS_GOOD_FC) == 0) 3181 ifp->if_ierrors++; 3182 msk_discard_jumbo_rxbuf(sc_if, cons); 3183 break; 3184 } 3185 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[cons]; 3186 m = jrxd->rx_m; 3187 if (msk_jumbo_newbuf(sc_if, cons) != 0) { 3188 ifp->if_iqdrops++; 3189 /* Reuse old buffer. */ 3190 msk_discard_jumbo_rxbuf(sc_if, cons); 3191 break; 3192 } 3193 m->m_pkthdr.rcvif = ifp; 3194 m->m_pkthdr.len = m->m_len = len; 3195 #ifndef __NO_STRICT_ALIGNMENT 3196 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) != 0) 3197 msk_fixup_rx(m); 3198 #endif 3199 ifp->if_ipackets++; 3200 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 3201 msk_rxcsum(sc_if, control, m); 3202 /* Check for VLAN tagged packets. */ 3203 if ((status & GMR_FS_VLAN) != 0 && 3204 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) { 3205 m->m_pkthdr.ether_vtag = sc_if->msk_vtag; 3206 m->m_flags |= M_VLANTAG; 3207 } 3208 MSK_IF_UNLOCK(sc_if); 3209 (*ifp->if_input)(ifp, m); 3210 MSK_IF_LOCK(sc_if); 3211 } while (0); 3212 3213 MSK_INC(sc_if->msk_cdata.msk_rx_cons, MSK_JUMBO_RX_RING_CNT); 3214 MSK_INC(sc_if->msk_cdata.msk_rx_prod, MSK_JUMBO_RX_RING_CNT); 3215 } 3216 3217 static void 3218 msk_txeof(struct msk_if_softc *sc_if, int idx) 3219 { 3220 struct msk_txdesc *txd; 3221 struct msk_tx_desc *cur_tx; 3222 struct ifnet *ifp; 3223 uint32_t control; 3224 int cons, prog; 3225 3226 MSK_IF_LOCK_ASSERT(sc_if); 3227 3228 ifp = sc_if->msk_ifp; 3229 3230 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_ring_tag, 3231 sc_if->msk_cdata.msk_tx_ring_map, 3232 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3233 /* 3234 * Go through our tx ring and free mbufs for those 3235 * frames that have been sent. 3236 */ 3237 cons = sc_if->msk_cdata.msk_tx_cons; 3238 prog = 0; 3239 for (; cons != idx; MSK_INC(cons, MSK_TX_RING_CNT)) { 3240 if (sc_if->msk_cdata.msk_tx_cnt <= 0) 3241 break; 3242 prog++; 3243 cur_tx = &sc_if->msk_rdata.msk_tx_ring[cons]; 3244 control = le32toh(cur_tx->msk_control); 3245 sc_if->msk_cdata.msk_tx_cnt--; 3246 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3247 if ((control & EOP) == 0) 3248 continue; 3249 txd = &sc_if->msk_cdata.msk_txdesc[cons]; 3250 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_tag, txd->tx_dmamap, 3251 BUS_DMASYNC_POSTWRITE); 3252 bus_dmamap_unload(sc_if->msk_cdata.msk_tx_tag, txd->tx_dmamap); 3253 3254 ifp->if_opackets++; 3255 KASSERT(txd->tx_m != NULL, ("%s: freeing NULL mbuf!", 3256 __func__)); 3257 m_freem(txd->tx_m); 3258 txd->tx_m = NULL; 3259 } 3260 3261 if (prog > 0) { 3262 sc_if->msk_cdata.msk_tx_cons = cons; 3263 if (sc_if->msk_cdata.msk_tx_cnt == 0) 3264 sc_if->msk_watchdog_timer = 0; 3265 /* No need to sync LEs as we didn't update LEs. */ 3266 } 3267 } 3268 3269 static void 3270 msk_tick(void *xsc_if) 3271 { 3272 struct msk_if_softc *sc_if; 3273 struct mii_data *mii; 3274 3275 sc_if = xsc_if; 3276 3277 MSK_IF_LOCK_ASSERT(sc_if); 3278 3279 mii = device_get_softc(sc_if->msk_miibus); 3280 3281 mii_tick(mii); 3282 if ((sc_if->msk_flags & MSK_FLAG_LINK) == 0) 3283 msk_miibus_statchg(sc_if->msk_if_dev); 3284 msk_handle_events(sc_if->msk_softc); 3285 msk_watchdog(sc_if); 3286 callout_reset(&sc_if->msk_tick_ch, hz, msk_tick, sc_if); 3287 } 3288 3289 static void 3290 msk_intr_phy(struct msk_if_softc *sc_if) 3291 { 3292 uint16_t status; 3293 3294 msk_phy_readreg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_STAT); 3295 status = msk_phy_readreg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_STAT); 3296 /* Handle FIFO Underrun/Overflow? */ 3297 if ((status & PHY_M_IS_FIFO_ERROR)) 3298 device_printf(sc_if->msk_if_dev, 3299 "PHY FIFO underrun/overflow.\n"); 3300 } 3301 3302 static void 3303 msk_intr_gmac(struct msk_if_softc *sc_if) 3304 { 3305 struct msk_softc *sc; 3306 uint8_t status; 3307 3308 sc = sc_if->msk_softc; 3309 status = CSR_READ_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_SRC)); 3310 3311 /* GMAC Rx FIFO overrun. */ 3312 if ((status & GM_IS_RX_FF_OR) != 0) 3313 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), 3314 GMF_CLI_RX_FO); 3315 /* GMAC Tx FIFO underrun. */ 3316 if ((status & GM_IS_TX_FF_UR) != 0) { 3317 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 3318 GMF_CLI_TX_FU); 3319 device_printf(sc_if->msk_if_dev, "Tx FIFO underrun!\n"); 3320 /* 3321 * XXX 3322 * In case of Tx underrun, we may need to flush/reset 3323 * Tx MAC but that would also require resynchronization 3324 * with status LEs. Reinitializing status LEs would 3325 * affect other port in dual MAC configuration so it 3326 * should be avoided as possible as we can. 3327 * Due to lack of documentation it's all vague guess but 3328 * it needs more investigation. 3329 */ 3330 } 3331 } 3332 3333 static void 3334 msk_handle_hwerr(struct msk_if_softc *sc_if, uint32_t status) 3335 { 3336 struct msk_softc *sc; 3337 3338 sc = sc_if->msk_softc; 3339 if ((status & Y2_IS_PAR_RD1) != 0) { 3340 device_printf(sc_if->msk_if_dev, 3341 "RAM buffer read parity error\n"); 3342 /* Clear IRQ. */ 3343 CSR_WRITE_2(sc, SELECT_RAM_BUFFER(sc_if->msk_port, B3_RI_CTRL), 3344 RI_CLR_RD_PERR); 3345 } 3346 if ((status & Y2_IS_PAR_WR1) != 0) { 3347 device_printf(sc_if->msk_if_dev, 3348 "RAM buffer write parity error\n"); 3349 /* Clear IRQ. */ 3350 CSR_WRITE_2(sc, SELECT_RAM_BUFFER(sc_if->msk_port, B3_RI_CTRL), 3351 RI_CLR_WR_PERR); 3352 } 3353 if ((status & Y2_IS_PAR_MAC1) != 0) { 3354 device_printf(sc_if->msk_if_dev, "Tx MAC parity error\n"); 3355 /* Clear IRQ. */ 3356 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 3357 GMF_CLI_TX_PE); 3358 } 3359 if ((status & Y2_IS_PAR_RX1) != 0) { 3360 device_printf(sc_if->msk_if_dev, "Rx parity error\n"); 3361 /* Clear IRQ. */ 3362 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_CLR_IRQ_PAR); 3363 } 3364 if ((status & (Y2_IS_TCP_TXS1 | Y2_IS_TCP_TXA1)) != 0) { 3365 device_printf(sc_if->msk_if_dev, "TCP segmentation error\n"); 3366 /* Clear IRQ. */ 3367 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_CLR_IRQ_TCP); 3368 } 3369 } 3370 3371 static void 3372 msk_intr_hwerr(struct msk_softc *sc) 3373 { 3374 uint32_t status; 3375 uint32_t tlphead[4]; 3376 3377 status = CSR_READ_4(sc, B0_HWE_ISRC); 3378 /* Time Stamp timer overflow. */ 3379 if ((status & Y2_IS_TIST_OV) != 0) 3380 CSR_WRITE_1(sc, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ); 3381 if ((status & Y2_IS_PCI_NEXP) != 0) { 3382 /* 3383 * PCI Express Error occured which is not described in PEX 3384 * spec. 3385 * This error is also mapped either to Master Abort( 3386 * Y2_IS_MST_ERR) or Target Abort (Y2_IS_IRQ_STAT) bit and 3387 * can only be cleared there. 3388 */ 3389 device_printf(sc->msk_dev, 3390 "PCI Express protocol violation error\n"); 3391 } 3392 3393 if ((status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) != 0) { 3394 uint16_t v16; 3395 3396 if ((status & Y2_IS_MST_ERR) != 0) 3397 device_printf(sc->msk_dev, 3398 "unexpected IRQ Status error\n"); 3399 else 3400 device_printf(sc->msk_dev, 3401 "unexpected IRQ Master error\n"); 3402 /* Reset all bits in the PCI status register. */ 3403 v16 = pci_read_config(sc->msk_dev, PCIR_STATUS, 2); 3404 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON); 3405 pci_write_config(sc->msk_dev, PCIR_STATUS, v16 | 3406 PCIM_STATUS_PERR | PCIM_STATUS_SERR | PCIM_STATUS_RMABORT | 3407 PCIM_STATUS_RTABORT | PCIM_STATUS_MDPERR, 2); 3408 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 3409 } 3410 3411 /* Check for PCI Express Uncorrectable Error. */ 3412 if ((status & Y2_IS_PCI_EXP) != 0) { 3413 uint32_t v32; 3414 3415 /* 3416 * On PCI Express bus bridges are called root complexes (RC). 3417 * PCI Express errors are recognized by the root complex too, 3418 * which requests the system to handle the problem. After 3419 * error occurence it may be that no access to the adapter 3420 * may be performed any longer. 3421 */ 3422 3423 v32 = CSR_PCI_READ_4(sc, PEX_UNC_ERR_STAT); 3424 if ((v32 & PEX_UNSUP_REQ) != 0) { 3425 /* Ignore unsupported request error. */ 3426 device_printf(sc->msk_dev, 3427 "Uncorrectable PCI Express error\n"); 3428 } 3429 if ((v32 & (PEX_FATAL_ERRORS | PEX_POIS_TLP)) != 0) { 3430 int i; 3431 3432 /* Get TLP header form Log Registers. */ 3433 for (i = 0; i < 4; i++) 3434 tlphead[i] = CSR_PCI_READ_4(sc, 3435 PEX_HEADER_LOG + i * 4); 3436 /* Check for vendor defined broadcast message. */ 3437 if (!(tlphead[0] == 0x73004001 && tlphead[1] == 0x7f)) { 3438 sc->msk_intrhwemask &= ~Y2_IS_PCI_EXP; 3439 CSR_WRITE_4(sc, B0_HWE_IMSK, 3440 sc->msk_intrhwemask); 3441 CSR_READ_4(sc, B0_HWE_IMSK); 3442 } 3443 } 3444 /* Clear the interrupt. */ 3445 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON); 3446 CSR_PCI_WRITE_4(sc, PEX_UNC_ERR_STAT, 0xffffffff); 3447 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 3448 } 3449 3450 if ((status & Y2_HWE_L1_MASK) != 0 && sc->msk_if[MSK_PORT_A] != NULL) 3451 msk_handle_hwerr(sc->msk_if[MSK_PORT_A], status); 3452 if ((status & Y2_HWE_L2_MASK) != 0 && sc->msk_if[MSK_PORT_B] != NULL) 3453 msk_handle_hwerr(sc->msk_if[MSK_PORT_B], status >> 8); 3454 } 3455 3456 static __inline void 3457 msk_rxput(struct msk_if_softc *sc_if) 3458 { 3459 struct msk_softc *sc; 3460 3461 sc = sc_if->msk_softc; 3462 if (sc_if->msk_framesize > (MCLBYTES - MSK_RX_BUF_ALIGN)) 3463 bus_dmamap_sync( 3464 sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 3465 sc_if->msk_cdata.msk_jumbo_rx_ring_map, 3466 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3467 else 3468 bus_dmamap_sync( 3469 sc_if->msk_cdata.msk_rx_ring_tag, 3470 sc_if->msk_cdata.msk_rx_ring_map, 3471 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3472 CSR_WRITE_2(sc, Y2_PREF_Q_ADDR(sc_if->msk_rxq, 3473 PREF_UNIT_PUT_IDX_REG), sc_if->msk_cdata.msk_rx_prod); 3474 } 3475 3476 static int 3477 msk_handle_events(struct msk_softc *sc) 3478 { 3479 struct msk_if_softc *sc_if; 3480 int rxput[2]; 3481 struct msk_stat_desc *sd; 3482 uint32_t control, status; 3483 int cons, len, port, rxprog; 3484 3485 if (sc->msk_stat_cons == CSR_READ_2(sc, STAT_PUT_IDX)) 3486 return (0); 3487 3488 /* Sync status LEs. */ 3489 bus_dmamap_sync(sc->msk_stat_tag, sc->msk_stat_map, 3490 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3491 3492 rxput[MSK_PORT_A] = rxput[MSK_PORT_B] = 0; 3493 rxprog = 0; 3494 cons = sc->msk_stat_cons; 3495 for (;;) { 3496 sd = &sc->msk_stat_ring[cons]; 3497 control = le32toh(sd->msk_control); 3498 if ((control & HW_OWNER) == 0) 3499 break; 3500 control &= ~HW_OWNER; 3501 sd->msk_control = htole32(control); 3502 status = le32toh(sd->msk_status); 3503 len = control & STLE_LEN_MASK; 3504 port = (control >> 16) & 0x01; 3505 sc_if = sc->msk_if[port]; 3506 if (sc_if == NULL) { 3507 device_printf(sc->msk_dev, "invalid port opcode " 3508 "0x%08x\n", control & STLE_OP_MASK); 3509 continue; 3510 } 3511 3512 switch (control & STLE_OP_MASK) { 3513 case OP_RXVLAN: 3514 sc_if->msk_vtag = ntohs(len); 3515 break; 3516 case OP_RXCHKSVLAN: 3517 sc_if->msk_vtag = ntohs(len); 3518 /* FALLTHROUGH */ 3519 case OP_RXCHKS: 3520 sc_if->msk_csum = status; 3521 break; 3522 case OP_RXSTAT: 3523 if (!(sc_if->msk_ifp->if_drv_flags & IFF_DRV_RUNNING)) 3524 break; 3525 if (sc_if->msk_framesize > 3526 (MCLBYTES - MSK_RX_BUF_ALIGN)) 3527 msk_jumbo_rxeof(sc_if, status, control, len); 3528 else 3529 msk_rxeof(sc_if, status, control, len); 3530 rxprog++; 3531 /* 3532 * Because there is no way to sync single Rx LE 3533 * put the DMA sync operation off until the end of 3534 * event processing. 3535 */ 3536 rxput[port]++; 3537 /* Update prefetch unit if we've passed water mark. */ 3538 if (rxput[port] >= sc_if->msk_cdata.msk_rx_putwm) { 3539 msk_rxput(sc_if); 3540 rxput[port] = 0; 3541 } 3542 break; 3543 case OP_TXINDEXLE: 3544 if (sc->msk_if[MSK_PORT_A] != NULL) 3545 msk_txeof(sc->msk_if[MSK_PORT_A], 3546 status & STLE_TXA1_MSKL); 3547 if (sc->msk_if[MSK_PORT_B] != NULL) 3548 msk_txeof(sc->msk_if[MSK_PORT_B], 3549 ((status & STLE_TXA2_MSKL) >> 3550 STLE_TXA2_SHIFTL) | 3551 ((len & STLE_TXA2_MSKH) << 3552 STLE_TXA2_SHIFTH)); 3553 break; 3554 default: 3555 device_printf(sc->msk_dev, "unhandled opcode 0x%08x\n", 3556 control & STLE_OP_MASK); 3557 break; 3558 } 3559 MSK_INC(cons, MSK_STAT_RING_CNT); 3560 if (rxprog > sc->msk_process_limit) 3561 break; 3562 } 3563 3564 sc->msk_stat_cons = cons; 3565 bus_dmamap_sync(sc->msk_stat_tag, sc->msk_stat_map, 3566 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3567 3568 if (rxput[MSK_PORT_A] > 0) 3569 msk_rxput(sc->msk_if[MSK_PORT_A]); 3570 if (rxput[MSK_PORT_B] > 0) 3571 msk_rxput(sc->msk_if[MSK_PORT_B]); 3572 3573 return (sc->msk_stat_cons != CSR_READ_2(sc, STAT_PUT_IDX)); 3574 } 3575 3576 static void 3577 msk_intr(void *xsc) 3578 { 3579 struct msk_softc *sc; 3580 struct msk_if_softc *sc_if0, *sc_if1; 3581 struct ifnet *ifp0, *ifp1; 3582 uint32_t status; 3583 int domore; 3584 3585 sc = xsc; 3586 MSK_LOCK(sc); 3587 3588 /* Reading B0_Y2_SP_ISRC2 masks further interrupts. */ 3589 status = CSR_READ_4(sc, B0_Y2_SP_ISRC2); 3590 if (status == 0 || status == 0xffffffff || 3591 (sc->msk_pflags & MSK_FLAG_SUSPEND) != 0 || 3592 (status & sc->msk_intrmask) == 0) { 3593 CSR_WRITE_4(sc, B0_Y2_SP_ICR, 2); 3594 MSK_UNLOCK(sc); 3595 return; 3596 } 3597 3598 sc_if0 = sc->msk_if[MSK_PORT_A]; 3599 sc_if1 = sc->msk_if[MSK_PORT_B]; 3600 ifp0 = ifp1 = NULL; 3601 if (sc_if0 != NULL) 3602 ifp0 = sc_if0->msk_ifp; 3603 if (sc_if1 != NULL) 3604 ifp1 = sc_if1->msk_ifp; 3605 3606 if ((status & Y2_IS_IRQ_PHY1) != 0 && sc_if0 != NULL) 3607 msk_intr_phy(sc_if0); 3608 if ((status & Y2_IS_IRQ_PHY2) != 0 && sc_if1 != NULL) 3609 msk_intr_phy(sc_if1); 3610 if ((status & Y2_IS_IRQ_MAC1) != 0 && sc_if0 != NULL) 3611 msk_intr_gmac(sc_if0); 3612 if ((status & Y2_IS_IRQ_MAC2) != 0 && sc_if1 != NULL) 3613 msk_intr_gmac(sc_if1); 3614 if ((status & (Y2_IS_CHK_RX1 | Y2_IS_CHK_RX2)) != 0) { 3615 device_printf(sc->msk_dev, "Rx descriptor error\n"); 3616 sc->msk_intrmask &= ~(Y2_IS_CHK_RX1 | Y2_IS_CHK_RX2); 3617 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask); 3618 CSR_READ_4(sc, B0_IMSK); 3619 } 3620 if ((status & (Y2_IS_CHK_TXA1 | Y2_IS_CHK_TXA2)) != 0) { 3621 device_printf(sc->msk_dev, "Tx descriptor error\n"); 3622 sc->msk_intrmask &= ~(Y2_IS_CHK_TXA1 | Y2_IS_CHK_TXA2); 3623 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask); 3624 CSR_READ_4(sc, B0_IMSK); 3625 } 3626 if ((status & Y2_IS_HW_ERR) != 0) 3627 msk_intr_hwerr(sc); 3628 3629 domore = msk_handle_events(sc); 3630 if ((status & Y2_IS_STAT_BMU) != 0 && domore == 0) 3631 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_CLR_IRQ); 3632 3633 /* Reenable interrupts. */ 3634 CSR_WRITE_4(sc, B0_Y2_SP_ICR, 2); 3635 3636 if (ifp0 != NULL && (ifp0->if_drv_flags & IFF_DRV_RUNNING) != 0 && 3637 !IFQ_DRV_IS_EMPTY(&ifp0->if_snd)) 3638 msk_start_locked(ifp0); 3639 if (ifp1 != NULL && (ifp1->if_drv_flags & IFF_DRV_RUNNING) != 0 && 3640 !IFQ_DRV_IS_EMPTY(&ifp1->if_snd)) 3641 msk_start_locked(ifp1); 3642 3643 MSK_UNLOCK(sc); 3644 } 3645 3646 static void 3647 msk_set_tx_stfwd(struct msk_if_softc *sc_if) 3648 { 3649 struct msk_softc *sc; 3650 struct ifnet *ifp; 3651 3652 ifp = sc_if->msk_ifp; 3653 sc = sc_if->msk_softc; 3654 switch (sc->msk_hw_id) { 3655 case CHIP_ID_YUKON_EX: 3656 if (sc->msk_hw_rev == CHIP_REV_YU_EX_A0) 3657 goto yukon_ex_workaround; 3658 if (ifp->if_mtu > ETHERMTU) 3659 CSR_WRITE_4(sc, 3660 MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 3661 TX_JUMBO_ENA | TX_STFW_ENA); 3662 else 3663 CSR_WRITE_4(sc, 3664 MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 3665 TX_JUMBO_DIS | TX_STFW_ENA); 3666 break; 3667 default: 3668 yukon_ex_workaround: 3669 if (ifp->if_mtu > ETHERMTU) { 3670 /* Set Tx GMAC FIFO Almost Empty Threshold. */ 3671 CSR_WRITE_4(sc, 3672 MR_ADDR(sc_if->msk_port, TX_GMF_AE_THR), 3673 MSK_ECU_JUMBO_WM << 16 | MSK_ECU_AE_THR); 3674 /* Disable Store & Forward mode for Tx. */ 3675 CSR_WRITE_4(sc, 3676 MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 3677 TX_JUMBO_ENA | TX_STFW_DIS); 3678 } else { 3679 /* Enable Store & Forward mode for Tx. */ 3680 CSR_WRITE_4(sc, 3681 MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 3682 TX_JUMBO_DIS | TX_STFW_ENA); 3683 } 3684 break; 3685 } 3686 } 3687 3688 static void 3689 msk_init(void *xsc) 3690 { 3691 struct msk_if_softc *sc_if = xsc; 3692 3693 MSK_IF_LOCK(sc_if); 3694 msk_init_locked(sc_if); 3695 MSK_IF_UNLOCK(sc_if); 3696 } 3697 3698 static void 3699 msk_init_locked(struct msk_if_softc *sc_if) 3700 { 3701 struct msk_softc *sc; 3702 struct ifnet *ifp; 3703 struct mii_data *mii; 3704 uint8_t *eaddr; 3705 uint16_t gmac; 3706 uint32_t reg; 3707 int error; 3708 3709 MSK_IF_LOCK_ASSERT(sc_if); 3710 3711 ifp = sc_if->msk_ifp; 3712 sc = sc_if->msk_softc; 3713 mii = device_get_softc(sc_if->msk_miibus); 3714 3715 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 3716 return; 3717 3718 error = 0; 3719 /* Cancel pending I/O and free all Rx/Tx buffers. */ 3720 msk_stop(sc_if); 3721 3722 if (ifp->if_mtu < ETHERMTU) 3723 sc_if->msk_framesize = ETHERMTU; 3724 else 3725 sc_if->msk_framesize = ifp->if_mtu; 3726 sc_if->msk_framesize += ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 3727 if (ifp->if_mtu > ETHERMTU && 3728 (sc_if->msk_flags & MSK_FLAG_JUMBO_NOCSUM) != 0) { 3729 ifp->if_hwassist &= ~(MSK_CSUM_FEATURES | CSUM_TSO); 3730 ifp->if_capenable &= ~(IFCAP_TSO4 | IFCAP_TXCSUM); 3731 } 3732 3733 /* GMAC Control reset. */ 3734 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_RST_SET); 3735 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_RST_CLR); 3736 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_F_LOOPB_OFF); 3737 if (sc->msk_hw_id == CHIP_ID_YUKON_EX) 3738 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), 3739 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON | 3740 GMC_BYP_RETR_ON); 3741 3742 /* 3743 * Initialize GMAC first such that speed/duplex/flow-control 3744 * parameters are renegotiated when interface is brought up. 3745 */ 3746 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, 0); 3747 3748 /* Dummy read the Interrupt Source Register. */ 3749 CSR_READ_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_SRC)); 3750 3751 /* Clear MIB stats. */ 3752 msk_stats_clear(sc_if); 3753 3754 /* Disable FCS. */ 3755 GMAC_WRITE_2(sc, sc_if->msk_port, GM_RX_CTRL, GM_RXCR_CRC_DIS); 3756 3757 /* Setup Transmit Control Register. */ 3758 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF)); 3759 3760 /* Setup Transmit Flow Control Register. */ 3761 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_FLOW_CTRL, 0xffff); 3762 3763 /* Setup Transmit Parameter Register. */ 3764 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_PARAM, 3765 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) | TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) | 3766 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) | TX_BACK_OFF_LIM(TX_BOF_LIM_DEF)); 3767 3768 gmac = DATA_BLIND_VAL(DATA_BLIND_DEF) | 3769 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF); 3770 3771 if (ifp->if_mtu > ETHERMTU) 3772 gmac |= GM_SMOD_JUMBO_ENA; 3773 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SERIAL_MODE, gmac); 3774 3775 /* Set station address. */ 3776 eaddr = IF_LLADDR(ifp); 3777 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_1L, 3778 eaddr[0] | (eaddr[1] << 8)); 3779 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_1M, 3780 eaddr[2] | (eaddr[3] << 8)); 3781 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_1H, 3782 eaddr[4] | (eaddr[5] << 8)); 3783 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_2L, 3784 eaddr[0] | (eaddr[1] << 8)); 3785 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_2M, 3786 eaddr[2] | (eaddr[3] << 8)); 3787 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_2H, 3788 eaddr[4] | (eaddr[5] << 8)); 3789 3790 /* Disable interrupts for counter overflows. */ 3791 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_IRQ_MSK, 0); 3792 GMAC_WRITE_2(sc, sc_if->msk_port, GM_RX_IRQ_MSK, 0); 3793 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TR_IRQ_MSK, 0); 3794 3795 /* Configure Rx MAC FIFO. */ 3796 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), GMF_RST_SET); 3797 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), GMF_RST_CLR); 3798 reg = GMF_OPER_ON | GMF_RX_F_FL_ON; 3799 if (sc->msk_hw_id == CHIP_ID_YUKON_FE_P || 3800 sc->msk_hw_id == CHIP_ID_YUKON_EX) 3801 reg |= GMF_RX_OVER_ON; 3802 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), reg); 3803 3804 /* Set receive filter. */ 3805 msk_rxfilter(sc_if); 3806 3807 if (sc->msk_hw_id == CHIP_ID_YUKON_XL) { 3808 /* Clear flush mask - HW bug. */ 3809 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_FL_MSK), 0); 3810 } else { 3811 /* Flush Rx MAC FIFO on any flow control or error. */ 3812 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_FL_MSK), 3813 GMR_FS_ANY_ERR); 3814 } 3815 3816 /* 3817 * Set Rx FIFO flush threshold to 64 bytes + 1 FIFO word 3818 * due to hardware hang on receipt of pause frames. 3819 */ 3820 reg = RX_GMF_FL_THR_DEF + 1; 3821 /* Another magic for Yukon FE+ - From Linux. */ 3822 if (sc->msk_hw_id == CHIP_ID_YUKON_FE_P && 3823 sc->msk_hw_rev == CHIP_REV_YU_FE_P_A0) 3824 reg = 0x178; 3825 CSR_WRITE_2(sc, MR_ADDR(sc_if->msk_port, RX_GMF_FL_THR), reg); 3826 3827 /* Configure Tx MAC FIFO. */ 3828 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_RST_SET); 3829 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_RST_CLR); 3830 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_OPER_ON); 3831 3832 /* Configure hardware VLAN tag insertion/stripping. */ 3833 msk_setvlan(sc_if, ifp); 3834 3835 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) == 0) { 3836 /* Set Rx Pause threshold. */ 3837 CSR_WRITE_2(sc, MR_ADDR(sc_if->msk_port, RX_GMF_LP_THR), 3838 MSK_ECU_LLPP); 3839 CSR_WRITE_2(sc, MR_ADDR(sc_if->msk_port, RX_GMF_UP_THR), 3840 MSK_ECU_ULPP); 3841 /* Configure store-and-forward for Tx. */ 3842 msk_set_tx_stfwd(sc_if); 3843 } 3844 3845 if (sc->msk_hw_id == CHIP_ID_YUKON_FE_P && 3846 sc->msk_hw_rev == CHIP_REV_YU_FE_P_A0) { 3847 /* Disable dynamic watermark - from Linux. */ 3848 reg = CSR_READ_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_EA)); 3849 reg &= ~0x03; 3850 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_EA), reg); 3851 } 3852 3853 /* 3854 * Disable Force Sync bit and Alloc bit in Tx RAM interface 3855 * arbiter as we don't use Sync Tx queue. 3856 */ 3857 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, TXA_CTRL), 3858 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC); 3859 /* Enable the RAM Interface Arbiter. */ 3860 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, TXA_CTRL), TXA_ENA_ARB); 3861 3862 /* Setup RAM buffer. */ 3863 msk_set_rambuffer(sc_if); 3864 3865 /* Disable Tx sync Queue. */ 3866 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txsq, RB_CTRL), RB_RST_SET); 3867 3868 /* Setup Tx Queue Bus Memory Interface. */ 3869 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_CLR_RESET); 3870 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_OPER_INIT); 3871 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_FIFO_OP_ON); 3872 CSR_WRITE_2(sc, Q_ADDR(sc_if->msk_txq, Q_WM), MSK_BMU_TX_WM); 3873 switch (sc->msk_hw_id) { 3874 case CHIP_ID_YUKON_EC_U: 3875 if (sc->msk_hw_rev == CHIP_REV_YU_EC_U_A0) { 3876 /* Fix for Yukon-EC Ultra: set BMU FIFO level */ 3877 CSR_WRITE_2(sc, Q_ADDR(sc_if->msk_txq, Q_AL), 3878 MSK_ECU_TXFF_LEV); 3879 } 3880 break; 3881 case CHIP_ID_YUKON_EX: 3882 /* 3883 * Yukon Extreme seems to have silicon bug for 3884 * automatic Tx checksum calculation capability. 3885 */ 3886 if (sc->msk_hw_rev == CHIP_REV_YU_EX_B0) 3887 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_F), 3888 F_TX_CHK_AUTO_OFF); 3889 break; 3890 } 3891 3892 /* Setup Rx Queue Bus Memory Interface. */ 3893 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_CLR_RESET); 3894 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_OPER_INIT); 3895 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_FIFO_OP_ON); 3896 CSR_WRITE_2(sc, Q_ADDR(sc_if->msk_rxq, Q_WM), MSK_BMU_RX_WM); 3897 if (sc->msk_hw_id == CHIP_ID_YUKON_EC_U && 3898 sc->msk_hw_rev >= CHIP_REV_YU_EC_U_A1) { 3899 /* MAC Rx RAM Read is controlled by hardware. */ 3900 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_F), F_M_RX_RAM_DIS); 3901 } 3902 3903 msk_set_prefetch(sc, sc_if->msk_txq, 3904 sc_if->msk_rdata.msk_tx_ring_paddr, MSK_TX_RING_CNT - 1); 3905 msk_init_tx_ring(sc_if); 3906 3907 /* Disable Rx checksum offload and RSS hash. */ 3908 reg = BMU_DIS_RX_RSS_HASH; 3909 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0 && 3910 (ifp->if_capenable & IFCAP_RXCSUM) != 0) 3911 reg |= BMU_ENA_RX_CHKSUM; 3912 else 3913 reg |= BMU_DIS_RX_CHKSUM; 3914 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), reg); 3915 if (sc_if->msk_framesize > (MCLBYTES - MSK_RX_BUF_ALIGN)) { 3916 msk_set_prefetch(sc, sc_if->msk_rxq, 3917 sc_if->msk_rdata.msk_jumbo_rx_ring_paddr, 3918 MSK_JUMBO_RX_RING_CNT - 1); 3919 error = msk_init_jumbo_rx_ring(sc_if); 3920 } else { 3921 msk_set_prefetch(sc, sc_if->msk_rxq, 3922 sc_if->msk_rdata.msk_rx_ring_paddr, 3923 MSK_RX_RING_CNT - 1); 3924 error = msk_init_rx_ring(sc_if); 3925 } 3926 if (error != 0) { 3927 device_printf(sc_if->msk_if_dev, 3928 "initialization failed: no memory for Rx buffers\n"); 3929 msk_stop(sc_if); 3930 return; 3931 } 3932 if (sc->msk_hw_id == CHIP_ID_YUKON_EX) { 3933 /* Disable flushing of non-ASF packets. */ 3934 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), 3935 GMF_RX_MACSEC_FLUSH_OFF); 3936 } 3937 3938 /* Configure interrupt handling. */ 3939 if (sc_if->msk_port == MSK_PORT_A) { 3940 sc->msk_intrmask |= Y2_IS_PORT_A; 3941 sc->msk_intrhwemask |= Y2_HWE_L1_MASK; 3942 } else { 3943 sc->msk_intrmask |= Y2_IS_PORT_B; 3944 sc->msk_intrhwemask |= Y2_HWE_L2_MASK; 3945 } 3946 /* Configure IRQ moderation mask. */ 3947 CSR_WRITE_4(sc, B2_IRQM_MSK, sc->msk_intrmask); 3948 if (sc->msk_int_holdoff > 0) { 3949 /* Configure initial IRQ moderation timer value. */ 3950 CSR_WRITE_4(sc, B2_IRQM_INI, 3951 MSK_USECS(sc, sc->msk_int_holdoff)); 3952 CSR_WRITE_4(sc, B2_IRQM_VAL, 3953 MSK_USECS(sc, sc->msk_int_holdoff)); 3954 /* Start IRQ moderation. */ 3955 CSR_WRITE_1(sc, B2_IRQM_CTRL, TIM_START); 3956 } 3957 CSR_WRITE_4(sc, B0_HWE_IMSK, sc->msk_intrhwemask); 3958 CSR_READ_4(sc, B0_HWE_IMSK); 3959 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask); 3960 CSR_READ_4(sc, B0_IMSK); 3961 3962 sc_if->msk_flags &= ~MSK_FLAG_LINK; 3963 mii_mediachg(mii); 3964 3965 ifp->if_drv_flags |= IFF_DRV_RUNNING; 3966 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3967 3968 callout_reset(&sc_if->msk_tick_ch, hz, msk_tick, sc_if); 3969 } 3970 3971 static void 3972 msk_set_rambuffer(struct msk_if_softc *sc_if) 3973 { 3974 struct msk_softc *sc; 3975 int ltpp, utpp; 3976 3977 sc = sc_if->msk_softc; 3978 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) == 0) 3979 return; 3980 3981 /* Setup Rx Queue. */ 3982 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_RST_CLR); 3983 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_START), 3984 sc->msk_rxqstart[sc_if->msk_port] / 8); 3985 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_END), 3986 sc->msk_rxqend[sc_if->msk_port] / 8); 3987 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_WP), 3988 sc->msk_rxqstart[sc_if->msk_port] / 8); 3989 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_RP), 3990 sc->msk_rxqstart[sc_if->msk_port] / 8); 3991 3992 utpp = (sc->msk_rxqend[sc_if->msk_port] + 1 - 3993 sc->msk_rxqstart[sc_if->msk_port] - MSK_RB_ULPP) / 8; 3994 ltpp = (sc->msk_rxqend[sc_if->msk_port] + 1 - 3995 sc->msk_rxqstart[sc_if->msk_port] - MSK_RB_LLPP_B) / 8; 3996 if (sc->msk_rxqsize < MSK_MIN_RXQ_SIZE) 3997 ltpp += (MSK_RB_LLPP_B - MSK_RB_LLPP_S) / 8; 3998 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_RX_UTPP), utpp); 3999 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_RX_LTPP), ltpp); 4000 /* Set Rx priority(RB_RX_UTHP/RB_RX_LTHP) thresholds? */ 4001 4002 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_ENA_OP_MD); 4003 CSR_READ_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL)); 4004 4005 /* Setup Tx Queue. */ 4006 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_RST_CLR); 4007 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_START), 4008 sc->msk_txqstart[sc_if->msk_port] / 8); 4009 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_END), 4010 sc->msk_txqend[sc_if->msk_port] / 8); 4011 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_WP), 4012 sc->msk_txqstart[sc_if->msk_port] / 8); 4013 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_RP), 4014 sc->msk_txqstart[sc_if->msk_port] / 8); 4015 /* Enable Store & Forward for Tx side. */ 4016 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_ENA_STFWD); 4017 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_ENA_OP_MD); 4018 CSR_READ_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL)); 4019 } 4020 4021 static void 4022 msk_set_prefetch(struct msk_softc *sc, int qaddr, bus_addr_t addr, 4023 uint32_t count) 4024 { 4025 4026 /* Reset the prefetch unit. */ 4027 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG), 4028 PREF_UNIT_RST_SET); 4029 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG), 4030 PREF_UNIT_RST_CLR); 4031 /* Set LE base address. */ 4032 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_ADDR_LOW_REG), 4033 MSK_ADDR_LO(addr)); 4034 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_ADDR_HI_REG), 4035 MSK_ADDR_HI(addr)); 4036 /* Set the list last index. */ 4037 CSR_WRITE_2(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_LAST_IDX_REG), 4038 count); 4039 /* Turn on prefetch unit. */ 4040 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG), 4041 PREF_UNIT_OP_ON); 4042 /* Dummy read to ensure write. */ 4043 CSR_READ_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG)); 4044 } 4045 4046 static void 4047 msk_stop(struct msk_if_softc *sc_if) 4048 { 4049 struct msk_softc *sc; 4050 struct msk_txdesc *txd; 4051 struct msk_rxdesc *rxd; 4052 struct msk_rxdesc *jrxd; 4053 struct ifnet *ifp; 4054 uint32_t val; 4055 int i; 4056 4057 MSK_IF_LOCK_ASSERT(sc_if); 4058 sc = sc_if->msk_softc; 4059 ifp = sc_if->msk_ifp; 4060 4061 callout_stop(&sc_if->msk_tick_ch); 4062 sc_if->msk_watchdog_timer = 0; 4063 4064 /* Disable interrupts. */ 4065 if (sc_if->msk_port == MSK_PORT_A) { 4066 sc->msk_intrmask &= ~Y2_IS_PORT_A; 4067 sc->msk_intrhwemask &= ~Y2_HWE_L1_MASK; 4068 } else { 4069 sc->msk_intrmask &= ~Y2_IS_PORT_B; 4070 sc->msk_intrhwemask &= ~Y2_HWE_L2_MASK; 4071 } 4072 CSR_WRITE_4(sc, B0_HWE_IMSK, sc->msk_intrhwemask); 4073 CSR_READ_4(sc, B0_HWE_IMSK); 4074 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask); 4075 CSR_READ_4(sc, B0_IMSK); 4076 4077 /* Disable Tx/Rx MAC. */ 4078 val = GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL); 4079 val &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA); 4080 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, val); 4081 /* Read again to ensure writing. */ 4082 GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL); 4083 /* Update stats and clear counters. */ 4084 msk_stats_update(sc_if); 4085 4086 /* Stop Tx BMU. */ 4087 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_STOP); 4088 val = CSR_READ_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR)); 4089 for (i = 0; i < MSK_TIMEOUT; i++) { 4090 if ((val & (BMU_STOP | BMU_IDLE)) == 0) { 4091 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), 4092 BMU_STOP); 4093 val = CSR_READ_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR)); 4094 } else 4095 break; 4096 DELAY(1); 4097 } 4098 if (i == MSK_TIMEOUT) 4099 device_printf(sc_if->msk_if_dev, "Tx BMU stop failed\n"); 4100 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), 4101 RB_RST_SET | RB_DIS_OP_MD); 4102 4103 /* Disable all GMAC interrupt. */ 4104 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_MSK), 0); 4105 /* Disable PHY interrupt. */ 4106 msk_phy_writereg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_MASK, 0); 4107 4108 /* Disable the RAM Interface Arbiter. */ 4109 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, TXA_CTRL), TXA_DIS_ARB); 4110 4111 /* Reset the PCI FIFO of the async Tx queue */ 4112 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), 4113 BMU_RST_SET | BMU_FIFO_RST); 4114 4115 /* Reset the Tx prefetch units. */ 4116 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(sc_if->msk_txq, PREF_UNIT_CTRL_REG), 4117 PREF_UNIT_RST_SET); 4118 4119 /* Reset the RAM Buffer async Tx queue. */ 4120 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_RST_SET); 4121 4122 /* Reset Tx MAC FIFO. */ 4123 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_RST_SET); 4124 /* Set Pause Off. */ 4125 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_PAUSE_OFF); 4126 4127 /* 4128 * The Rx Stop command will not work for Yukon-2 if the BMU does not 4129 * reach the end of packet and since we can't make sure that we have 4130 * incoming data, we must reset the BMU while it is not during a DMA 4131 * transfer. Since it is possible that the Rx path is still active, 4132 * the Rx RAM buffer will be stopped first, so any possible incoming 4133 * data will not trigger a DMA. After the RAM buffer is stopped, the 4134 * BMU is polled until any DMA in progress is ended and only then it 4135 * will be reset. 4136 */ 4137 4138 /* Disable the RAM Buffer receive queue. */ 4139 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_DIS_OP_MD); 4140 for (i = 0; i < MSK_TIMEOUT; i++) { 4141 if (CSR_READ_1(sc, RB_ADDR(sc_if->msk_rxq, Q_RSL)) == 4142 CSR_READ_1(sc, RB_ADDR(sc_if->msk_rxq, Q_RL))) 4143 break; 4144 DELAY(1); 4145 } 4146 if (i == MSK_TIMEOUT) 4147 device_printf(sc_if->msk_if_dev, "Rx BMU stop failed\n"); 4148 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), 4149 BMU_RST_SET | BMU_FIFO_RST); 4150 /* Reset the Rx prefetch unit. */ 4151 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_CTRL_REG), 4152 PREF_UNIT_RST_SET); 4153 /* Reset the RAM Buffer receive queue. */ 4154 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_RST_SET); 4155 /* Reset Rx MAC FIFO. */ 4156 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), GMF_RST_SET); 4157 4158 /* Free Rx and Tx mbufs still in the queues. */ 4159 for (i = 0; i < MSK_RX_RING_CNT; i++) { 4160 rxd = &sc_if->msk_cdata.msk_rxdesc[i]; 4161 if (rxd->rx_m != NULL) { 4162 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_tag, 4163 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 4164 bus_dmamap_unload(sc_if->msk_cdata.msk_rx_tag, 4165 rxd->rx_dmamap); 4166 m_freem(rxd->rx_m); 4167 rxd->rx_m = NULL; 4168 } 4169 } 4170 for (i = 0; i < MSK_JUMBO_RX_RING_CNT; i++) { 4171 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[i]; 4172 if (jrxd->rx_m != NULL) { 4173 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_tag, 4174 jrxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 4175 bus_dmamap_unload(sc_if->msk_cdata.msk_jumbo_rx_tag, 4176 jrxd->rx_dmamap); 4177 m_freem(jrxd->rx_m); 4178 jrxd->rx_m = NULL; 4179 } 4180 } 4181 for (i = 0; i < MSK_TX_RING_CNT; i++) { 4182 txd = &sc_if->msk_cdata.msk_txdesc[i]; 4183 if (txd->tx_m != NULL) { 4184 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_tag, 4185 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 4186 bus_dmamap_unload(sc_if->msk_cdata.msk_tx_tag, 4187 txd->tx_dmamap); 4188 m_freem(txd->tx_m); 4189 txd->tx_m = NULL; 4190 } 4191 } 4192 4193 /* 4194 * Mark the interface down. 4195 */ 4196 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 4197 sc_if->msk_flags &= ~MSK_FLAG_LINK; 4198 } 4199 4200 /* 4201 * When GM_PAR_MIB_CLR bit of GM_PHY_ADDR is set, reading lower 4202 * counter clears high 16 bits of the counter such that accessing 4203 * lower 16 bits should be the last operation. 4204 */ 4205 #define MSK_READ_MIB32(x, y) \ 4206 (((uint32_t)GMAC_READ_2(sc, x, (y) + 4)) << 16) + \ 4207 (uint32_t)GMAC_READ_2(sc, x, y) 4208 #define MSK_READ_MIB64(x, y) \ 4209 (((uint64_t)MSK_READ_MIB32(x, (y) + 8)) << 32) + \ 4210 (uint64_t)MSK_READ_MIB32(x, y) 4211 4212 static void 4213 msk_stats_clear(struct msk_if_softc *sc_if) 4214 { 4215 struct msk_softc *sc; 4216 uint32_t reg; 4217 uint16_t gmac; 4218 int i; 4219 4220 MSK_IF_LOCK_ASSERT(sc_if); 4221 4222 sc = sc_if->msk_softc; 4223 /* Set MIB Clear Counter Mode. */ 4224 gmac = GMAC_READ_2(sc, sc_if->msk_port, GM_PHY_ADDR); 4225 GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac | GM_PAR_MIB_CLR); 4226 /* Read all MIB Counters with Clear Mode set. */ 4227 for (i = GM_RXF_UC_OK; i <= GM_TXE_FIFO_UR; i += sizeof(uint32_t)) 4228 reg = MSK_READ_MIB32(sc_if->msk_port, i); 4229 /* Clear MIB Clear Counter Mode. */ 4230 gmac &= ~GM_PAR_MIB_CLR; 4231 GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac); 4232 } 4233 4234 static void 4235 msk_stats_update(struct msk_if_softc *sc_if) 4236 { 4237 struct msk_softc *sc; 4238 struct ifnet *ifp; 4239 struct msk_hw_stats *stats; 4240 uint16_t gmac; 4241 uint32_t reg; 4242 4243 MSK_IF_LOCK_ASSERT(sc_if); 4244 4245 ifp = sc_if->msk_ifp; 4246 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 4247 return; 4248 sc = sc_if->msk_softc; 4249 stats = &sc_if->msk_stats; 4250 /* Set MIB Clear Counter Mode. */ 4251 gmac = GMAC_READ_2(sc, sc_if->msk_port, GM_PHY_ADDR); 4252 GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac | GM_PAR_MIB_CLR); 4253 4254 /* Rx stats. */ 4255 stats->rx_ucast_frames += 4256 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_UC_OK); 4257 stats->rx_bcast_frames += 4258 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_BC_OK); 4259 stats->rx_pause_frames += 4260 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_MPAUSE); 4261 stats->rx_mcast_frames += 4262 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_MC_OK); 4263 stats->rx_crc_errs += 4264 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_FCS_ERR); 4265 reg = MSK_READ_MIB32(sc_if->msk_port, GM_RXF_SPARE1); 4266 stats->rx_good_octets += 4267 MSK_READ_MIB64(sc_if->msk_port, GM_RXO_OK_LO); 4268 stats->rx_bad_octets += 4269 MSK_READ_MIB64(sc_if->msk_port, GM_RXO_ERR_LO); 4270 stats->rx_runts += 4271 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_SHT); 4272 stats->rx_runt_errs += 4273 MSK_READ_MIB32(sc_if->msk_port, GM_RXE_FRAG); 4274 stats->rx_pkts_64 += 4275 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_64B); 4276 stats->rx_pkts_65_127 += 4277 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_127B); 4278 stats->rx_pkts_128_255 += 4279 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_255B); 4280 stats->rx_pkts_256_511 += 4281 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_511B); 4282 stats->rx_pkts_512_1023 += 4283 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_1023B); 4284 stats->rx_pkts_1024_1518 += 4285 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_1518B); 4286 stats->rx_pkts_1519_max += 4287 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_MAX_SZ); 4288 stats->rx_pkts_too_long += 4289 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_LNG_ERR); 4290 stats->rx_pkts_jabbers += 4291 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_JAB_PKT); 4292 reg = MSK_READ_MIB32(sc_if->msk_port, GM_RXF_SPARE2); 4293 stats->rx_fifo_oflows += 4294 MSK_READ_MIB32(sc_if->msk_port, GM_RXE_FIFO_OV); 4295 reg = MSK_READ_MIB32(sc_if->msk_port, GM_RXF_SPARE3); 4296 4297 /* Tx stats. */ 4298 stats->tx_ucast_frames += 4299 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_UC_OK); 4300 stats->tx_bcast_frames += 4301 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_BC_OK); 4302 stats->tx_pause_frames += 4303 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_MPAUSE); 4304 stats->tx_mcast_frames += 4305 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_MC_OK); 4306 stats->tx_octets += 4307 MSK_READ_MIB64(sc_if->msk_port, GM_TXO_OK_LO); 4308 stats->tx_pkts_64 += 4309 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_64B); 4310 stats->tx_pkts_65_127 += 4311 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_127B); 4312 stats->tx_pkts_128_255 += 4313 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_255B); 4314 stats->tx_pkts_256_511 += 4315 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_511B); 4316 stats->tx_pkts_512_1023 += 4317 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_1023B); 4318 stats->tx_pkts_1024_1518 += 4319 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_1518B); 4320 stats->tx_pkts_1519_max += 4321 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_MAX_SZ); 4322 reg = MSK_READ_MIB32(sc_if->msk_port, GM_TXF_SPARE1); 4323 stats->tx_colls += 4324 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_COL); 4325 stats->tx_late_colls += 4326 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_LAT_COL); 4327 stats->tx_excess_colls += 4328 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_ABO_COL); 4329 stats->tx_multi_colls += 4330 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_MUL_COL); 4331 stats->tx_single_colls += 4332 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_SNG_COL); 4333 stats->tx_underflows += 4334 MSK_READ_MIB32(sc_if->msk_port, GM_TXE_FIFO_UR); 4335 /* Clear MIB Clear Counter Mode. */ 4336 gmac &= ~GM_PAR_MIB_CLR; 4337 GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac); 4338 } 4339 4340 static int 4341 msk_sysctl_stat32(SYSCTL_HANDLER_ARGS) 4342 { 4343 struct msk_softc *sc; 4344 struct msk_if_softc *sc_if; 4345 uint32_t result, *stat; 4346 int off; 4347 4348 sc_if = (struct msk_if_softc *)arg1; 4349 sc = sc_if->msk_softc; 4350 off = arg2; 4351 stat = (uint32_t *)((uint8_t *)&sc_if->msk_stats + off); 4352 4353 MSK_IF_LOCK(sc_if); 4354 result = MSK_READ_MIB32(sc_if->msk_port, GM_MIB_CNT_BASE + off * 2); 4355 result += *stat; 4356 MSK_IF_UNLOCK(sc_if); 4357 4358 return (sysctl_handle_int(oidp, &result, 0, req)); 4359 } 4360 4361 static int 4362 msk_sysctl_stat64(SYSCTL_HANDLER_ARGS) 4363 { 4364 struct msk_softc *sc; 4365 struct msk_if_softc *sc_if; 4366 uint64_t result, *stat; 4367 int off; 4368 4369 sc_if = (struct msk_if_softc *)arg1; 4370 sc = sc_if->msk_softc; 4371 off = arg2; 4372 stat = (uint64_t *)((uint8_t *)&sc_if->msk_stats + off); 4373 4374 MSK_IF_LOCK(sc_if); 4375 result = MSK_READ_MIB64(sc_if->msk_port, GM_MIB_CNT_BASE + off * 2); 4376 result += *stat; 4377 MSK_IF_UNLOCK(sc_if); 4378 4379 return (sysctl_handle_quad(oidp, &result, 0, req)); 4380 } 4381 4382 #undef MSK_READ_MIB32 4383 #undef MSK_READ_MIB64 4384 4385 #define MSK_SYSCTL_STAT32(sc, c, o, p, n, d) \ 4386 SYSCTL_ADD_PROC(c, p, OID_AUTO, o, CTLTYPE_UINT | CTLFLAG_RD, \ 4387 sc, offsetof(struct msk_hw_stats, n), msk_sysctl_stat32, \ 4388 "IU", d) 4389 #define MSK_SYSCTL_STAT64(sc, c, o, p, n, d) \ 4390 SYSCTL_ADD_PROC(c, p, OID_AUTO, o, CTLTYPE_UINT | CTLFLAG_RD, \ 4391 sc, offsetof(struct msk_hw_stats, n), msk_sysctl_stat64, \ 4392 "Q", d) 4393 4394 static void 4395 msk_sysctl_node(struct msk_if_softc *sc_if) 4396 { 4397 struct sysctl_ctx_list *ctx; 4398 struct sysctl_oid_list *child, *schild; 4399 struct sysctl_oid *tree; 4400 4401 ctx = device_get_sysctl_ctx(sc_if->msk_if_dev); 4402 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc_if->msk_if_dev)); 4403 4404 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD, 4405 NULL, "MSK Statistics"); 4406 schild = child = SYSCTL_CHILDREN(tree); 4407 tree = SYSCTL_ADD_NODE(ctx, schild, OID_AUTO, "rx", CTLFLAG_RD, 4408 NULL, "MSK RX Statistics"); 4409 child = SYSCTL_CHILDREN(tree); 4410 MSK_SYSCTL_STAT32(sc_if, ctx, "ucast_frames", 4411 child, rx_ucast_frames, "Good unicast frames"); 4412 MSK_SYSCTL_STAT32(sc_if, ctx, "bcast_frames", 4413 child, rx_bcast_frames, "Good broadcast frames"); 4414 MSK_SYSCTL_STAT32(sc_if, ctx, "pause_frames", 4415 child, rx_pause_frames, "Pause frames"); 4416 MSK_SYSCTL_STAT32(sc_if, ctx, "mcast_frames", 4417 child, rx_mcast_frames, "Multicast frames"); 4418 MSK_SYSCTL_STAT32(sc_if, ctx, "crc_errs", 4419 child, rx_crc_errs, "CRC errors"); 4420 MSK_SYSCTL_STAT64(sc_if, ctx, "good_octets", 4421 child, rx_good_octets, "Good octets"); 4422 MSK_SYSCTL_STAT64(sc_if, ctx, "bad_octets", 4423 child, rx_bad_octets, "Bad octets"); 4424 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_64", 4425 child, rx_pkts_64, "64 bytes frames"); 4426 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_65_127", 4427 child, rx_pkts_65_127, "65 to 127 bytes frames"); 4428 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_128_255", 4429 child, rx_pkts_128_255, "128 to 255 bytes frames"); 4430 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_256_511", 4431 child, rx_pkts_256_511, "256 to 511 bytes frames"); 4432 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_512_1023", 4433 child, rx_pkts_512_1023, "512 to 1023 bytes frames"); 4434 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_1024_1518", 4435 child, rx_pkts_1024_1518, "1024 to 1518 bytes frames"); 4436 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_1519_max", 4437 child, rx_pkts_1519_max, "1519 to max frames"); 4438 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_too_long", 4439 child, rx_pkts_too_long, "frames too long"); 4440 MSK_SYSCTL_STAT32(sc_if, ctx, "jabbers", 4441 child, rx_pkts_jabbers, "Jabber errors"); 4442 MSK_SYSCTL_STAT32(sc_if, ctx, "overflows", 4443 child, rx_fifo_oflows, "FIFO overflows"); 4444 4445 tree = SYSCTL_ADD_NODE(ctx, schild, OID_AUTO, "tx", CTLFLAG_RD, 4446 NULL, "MSK TX Statistics"); 4447 child = SYSCTL_CHILDREN(tree); 4448 MSK_SYSCTL_STAT32(sc_if, ctx, "ucast_frames", 4449 child, tx_ucast_frames, "Unicast frames"); 4450 MSK_SYSCTL_STAT32(sc_if, ctx, "bcast_frames", 4451 child, tx_bcast_frames, "Broadcast frames"); 4452 MSK_SYSCTL_STAT32(sc_if, ctx, "pause_frames", 4453 child, tx_pause_frames, "Pause frames"); 4454 MSK_SYSCTL_STAT32(sc_if, ctx, "mcast_frames", 4455 child, tx_mcast_frames, "Multicast frames"); 4456 MSK_SYSCTL_STAT64(sc_if, ctx, "octets", 4457 child, tx_octets, "Octets"); 4458 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_64", 4459 child, tx_pkts_64, "64 bytes frames"); 4460 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_65_127", 4461 child, tx_pkts_65_127, "65 to 127 bytes frames"); 4462 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_128_255", 4463 child, tx_pkts_128_255, "128 to 255 bytes frames"); 4464 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_256_511", 4465 child, tx_pkts_256_511, "256 to 511 bytes frames"); 4466 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_512_1023", 4467 child, tx_pkts_512_1023, "512 to 1023 bytes frames"); 4468 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_1024_1518", 4469 child, tx_pkts_1024_1518, "1024 to 1518 bytes frames"); 4470 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_1519_max", 4471 child, tx_pkts_1519_max, "1519 to max frames"); 4472 MSK_SYSCTL_STAT32(sc_if, ctx, "colls", 4473 child, tx_colls, "Collisions"); 4474 MSK_SYSCTL_STAT32(sc_if, ctx, "late_colls", 4475 child, tx_late_colls, "Late collisions"); 4476 MSK_SYSCTL_STAT32(sc_if, ctx, "excess_colls", 4477 child, tx_excess_colls, "Excessive collisions"); 4478 MSK_SYSCTL_STAT32(sc_if, ctx, "multi_colls", 4479 child, tx_multi_colls, "Multiple collisions"); 4480 MSK_SYSCTL_STAT32(sc_if, ctx, "single_colls", 4481 child, tx_single_colls, "Single collisions"); 4482 MSK_SYSCTL_STAT32(sc_if, ctx, "underflows", 4483 child, tx_underflows, "FIFO underflows"); 4484 } 4485 4486 #undef MSK_SYSCTL_STAT32 4487 #undef MSK_SYSCTL_STAT64 4488 4489 static int 4490 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 4491 { 4492 int error, value; 4493 4494 if (!arg1) 4495 return (EINVAL); 4496 value = *(int *)arg1; 4497 error = sysctl_handle_int(oidp, &value, 0, req); 4498 if (error || !req->newptr) 4499 return (error); 4500 if (value < low || value > high) 4501 return (EINVAL); 4502 *(int *)arg1 = value; 4503 4504 return (0); 4505 } 4506 4507 static int 4508 sysctl_hw_msk_proc_limit(SYSCTL_HANDLER_ARGS) 4509 { 4510 4511 return (sysctl_int_range(oidp, arg1, arg2, req, MSK_PROC_MIN, 4512 MSK_PROC_MAX)); 4513 } 4514