1 /****************************************************************************** 2 * 3 * Name : sky2.c 4 * Project: Gigabit Ethernet Driver for FreeBSD 5.x/6.x 5 * Version: $Revision: 1.23 $ 6 * Date : $Date: 2005/12/22 09:04:11 $ 7 * Purpose: Main driver source file 8 * 9 *****************************************************************************/ 10 11 /****************************************************************************** 12 * 13 * LICENSE: 14 * Copyright (C) Marvell International Ltd. and/or its affiliates 15 * 16 * The computer program files contained in this folder ("Files") 17 * are provided to you under the BSD-type license terms provided 18 * below, and any use of such Files and any derivative works 19 * thereof created by you shall be governed by the following terms 20 * and conditions: 21 * 22 * - Redistributions of source code must retain the above copyright 23 * notice, this list of conditions and the following disclaimer. 24 * - Redistributions in binary form must reproduce the above 25 * copyright notice, this list of conditions and the following 26 * disclaimer in the documentation and/or other materials provided 27 * with the distribution. 28 * - Neither the name of Marvell nor the names of its contributors 29 * may be used to endorse or promote products derived from this 30 * software without specific prior written permission. 31 * 32 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 33 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 34 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 35 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 36 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 37 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 38 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 39 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 40 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 41 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 42 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED 43 * OF THE POSSIBILITY OF SUCH DAMAGE. 44 * /LICENSE 45 * 46 *****************************************************************************/ 47 48 /*- 49 * Copyright (c) 1997, 1998, 1999, 2000 50 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 51 * 52 * Redistribution and use in source and binary forms, with or without 53 * modification, are permitted provided that the following conditions 54 * are met: 55 * 1. Redistributions of source code must retain the above copyright 56 * notice, this list of conditions and the following disclaimer. 57 * 2. Redistributions in binary form must reproduce the above copyright 58 * notice, this list of conditions and the following disclaimer in the 59 * documentation and/or other materials provided with the distribution. 60 * 3. All advertising materials mentioning features or use of this software 61 * must display the following acknowledgement: 62 * This product includes software developed by Bill Paul. 63 * 4. Neither the name of the author nor the names of any co-contributors 64 * may be used to endorse or promote products derived from this software 65 * without specific prior written permission. 66 * 67 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 68 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 69 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 70 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 71 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 72 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 73 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 74 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 75 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 76 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 77 * THE POSSIBILITY OF SUCH DAMAGE. 78 */ 79 /*- 80 * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu> 81 * 82 * Permission to use, copy, modify, and distribute this software for any 83 * purpose with or without fee is hereby granted, provided that the above 84 * copyright notice and this permission notice appear in all copies. 85 * 86 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 87 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 88 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 89 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 90 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 91 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 92 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 93 */ 94 95 /* 96 * Device driver for the Marvell Yukon II Ethernet controller. 97 * Due to lack of documentation, this driver is based on the code from 98 * sk(4) and Marvell's myk(4) driver for FreeBSD 5.x. 99 */ 100 101 #include <sys/cdefs.h> 102 __FBSDID("$FreeBSD$"); 103 104 #include <sys/param.h> 105 #include <sys/systm.h> 106 #include <sys/bus.h> 107 #include <sys/endian.h> 108 #include <sys/mbuf.h> 109 #include <sys/malloc.h> 110 #include <sys/kernel.h> 111 #include <sys/module.h> 112 #include <sys/socket.h> 113 #include <sys/sockio.h> 114 #include <sys/queue.h> 115 #include <sys/sysctl.h> 116 #include <sys/taskqueue.h> 117 118 #include <net/bpf.h> 119 #include <net/ethernet.h> 120 #include <net/if.h> 121 #include <net/if_arp.h> 122 #include <net/if_dl.h> 123 #include <net/if_media.h> 124 #include <net/if_types.h> 125 #include <net/if_vlan_var.h> 126 127 #include <netinet/in.h> 128 #include <netinet/in_systm.h> 129 #include <netinet/ip.h> 130 #include <netinet/tcp.h> 131 #include <netinet/udp.h> 132 133 #include <machine/bus.h> 134 #include <machine/in_cksum.h> 135 #include <machine/resource.h> 136 #include <sys/rman.h> 137 138 #include <dev/mii/mii.h> 139 #include <dev/mii/miivar.h> 140 141 #include <dev/pci/pcireg.h> 142 #include <dev/pci/pcivar.h> 143 144 #include <dev/msk/if_mskreg.h> 145 146 MODULE_DEPEND(msk, pci, 1, 1, 1); 147 MODULE_DEPEND(msk, ether, 1, 1, 1); 148 MODULE_DEPEND(msk, miibus, 1, 1, 1); 149 150 /* "device miibus" required. See GENERIC if you get errors here. */ 151 #include "miibus_if.h" 152 153 /* Tunables. */ 154 static int msi_disable = 0; 155 TUNABLE_INT("hw.msk.msi_disable", &msi_disable); 156 static int legacy_intr = 0; 157 TUNABLE_INT("hw.msk.legacy_intr", &legacy_intr); 158 static int jumbo_disable = 0; 159 TUNABLE_INT("hw.msk.jumbo_disable", &jumbo_disable); 160 161 #define MSK_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 162 163 /* 164 * Devices supported by this driver. 165 */ 166 static struct msk_product { 167 uint16_t msk_vendorid; 168 uint16_t msk_deviceid; 169 const char *msk_name; 170 } msk_products[] = { 171 { VENDORID_SK, DEVICEID_SK_YUKON2, 172 "SK-9Sxx Gigabit Ethernet" }, 173 { VENDORID_SK, DEVICEID_SK_YUKON2_EXPR, 174 "SK-9Exx Gigabit Ethernet"}, 175 { VENDORID_MARVELL, DEVICEID_MRVL_8021CU, 176 "Marvell Yukon 88E8021CU Gigabit Ethernet" }, 177 { VENDORID_MARVELL, DEVICEID_MRVL_8021X, 178 "Marvell Yukon 88E8021 SX/LX Gigabit Ethernet" }, 179 { VENDORID_MARVELL, DEVICEID_MRVL_8022CU, 180 "Marvell Yukon 88E8022CU Gigabit Ethernet" }, 181 { VENDORID_MARVELL, DEVICEID_MRVL_8022X, 182 "Marvell Yukon 88E8022 SX/LX Gigabit Ethernet" }, 183 { VENDORID_MARVELL, DEVICEID_MRVL_8061CU, 184 "Marvell Yukon 88E8061CU Gigabit Ethernet" }, 185 { VENDORID_MARVELL, DEVICEID_MRVL_8061X, 186 "Marvell Yukon 88E8061 SX/LX Gigabit Ethernet" }, 187 { VENDORID_MARVELL, DEVICEID_MRVL_8062CU, 188 "Marvell Yukon 88E8062CU Gigabit Ethernet" }, 189 { VENDORID_MARVELL, DEVICEID_MRVL_8062X, 190 "Marvell Yukon 88E8062 SX/LX Gigabit Ethernet" }, 191 { VENDORID_MARVELL, DEVICEID_MRVL_8035, 192 "Marvell Yukon 88E8035 Fast Ethernet" }, 193 { VENDORID_MARVELL, DEVICEID_MRVL_8036, 194 "Marvell Yukon 88E8036 Fast Ethernet" }, 195 { VENDORID_MARVELL, DEVICEID_MRVL_8038, 196 "Marvell Yukon 88E8038 Fast Ethernet" }, 197 { VENDORID_MARVELL, DEVICEID_MRVL_8039, 198 "Marvell Yukon 88E8039 Fast Ethernet" }, 199 { VENDORID_MARVELL, DEVICEID_MRVL_8040, 200 "Marvell Yukon 88E8040 Fast Ethernet" }, 201 { VENDORID_MARVELL, DEVICEID_MRVL_8040T, 202 "Marvell Yukon 88E8040T Fast Ethernet" }, 203 { VENDORID_MARVELL, DEVICEID_MRVL_8042, 204 "Marvell Yukon 88E8042 Fast Ethernet" }, 205 { VENDORID_MARVELL, DEVICEID_MRVL_8048, 206 "Marvell Yukon 88E8048 Fast Ethernet" }, 207 { VENDORID_MARVELL, DEVICEID_MRVL_4361, 208 "Marvell Yukon 88E8050 Gigabit Ethernet" }, 209 { VENDORID_MARVELL, DEVICEID_MRVL_4360, 210 "Marvell Yukon 88E8052 Gigabit Ethernet" }, 211 { VENDORID_MARVELL, DEVICEID_MRVL_4362, 212 "Marvell Yukon 88E8053 Gigabit Ethernet" }, 213 { VENDORID_MARVELL, DEVICEID_MRVL_4363, 214 "Marvell Yukon 88E8055 Gigabit Ethernet" }, 215 { VENDORID_MARVELL, DEVICEID_MRVL_4364, 216 "Marvell Yukon 88E8056 Gigabit Ethernet" }, 217 { VENDORID_MARVELL, DEVICEID_MRVL_4365, 218 "Marvell Yukon 88E8070 Gigabit Ethernet" }, 219 { VENDORID_MARVELL, DEVICEID_MRVL_436A, 220 "Marvell Yukon 88E8058 Gigabit Ethernet" }, 221 { VENDORID_MARVELL, DEVICEID_MRVL_436B, 222 "Marvell Yukon 88E8071 Gigabit Ethernet" }, 223 { VENDORID_MARVELL, DEVICEID_MRVL_436C, 224 "Marvell Yukon 88E8072 Gigabit Ethernet" }, 225 { VENDORID_MARVELL, DEVICEID_MRVL_4380, 226 "Marvell Yukon 88E8057 Gigabit Ethernet" }, 227 { VENDORID_DLINK, DEVICEID_DLINK_DGE550SX, 228 "D-Link 550SX Gigabit Ethernet" }, 229 { VENDORID_DLINK, DEVICEID_DLINK_DGE560SX, 230 "D-Link 560SX Gigabit Ethernet" }, 231 { VENDORID_DLINK, DEVICEID_DLINK_DGE560T, 232 "D-Link 560T Gigabit Ethernet" } 233 }; 234 235 static const char *model_name[] = { 236 "Yukon XL", 237 "Yukon EC Ultra", 238 "Yukon EX", 239 "Yukon EC", 240 "Yukon FE", 241 "Yukon FE+", 242 "Yukon Supreme", 243 "Yukon Ultra 2" 244 }; 245 246 static int mskc_probe(device_t); 247 static int mskc_attach(device_t); 248 static int mskc_detach(device_t); 249 static int mskc_shutdown(device_t); 250 static int mskc_setup_rambuffer(struct msk_softc *); 251 static int mskc_suspend(device_t); 252 static int mskc_resume(device_t); 253 static void mskc_reset(struct msk_softc *); 254 255 static int msk_probe(device_t); 256 static int msk_attach(device_t); 257 static int msk_detach(device_t); 258 259 static void msk_tick(void *); 260 static void msk_legacy_intr(void *); 261 static int msk_intr(void *); 262 static void msk_int_task(void *, int); 263 static void msk_intr_phy(struct msk_if_softc *); 264 static void msk_intr_gmac(struct msk_if_softc *); 265 static __inline void msk_rxput(struct msk_if_softc *); 266 static int msk_handle_events(struct msk_softc *); 267 static void msk_handle_hwerr(struct msk_if_softc *, uint32_t); 268 static void msk_intr_hwerr(struct msk_softc *); 269 #ifndef __NO_STRICT_ALIGNMENT 270 static __inline void msk_fixup_rx(struct mbuf *); 271 #endif 272 static void msk_rxeof(struct msk_if_softc *, uint32_t, uint32_t, int); 273 static void msk_jumbo_rxeof(struct msk_if_softc *, uint32_t, uint32_t, int); 274 static void msk_txeof(struct msk_if_softc *, int); 275 static int msk_encap(struct msk_if_softc *, struct mbuf **); 276 static void msk_tx_task(void *, int); 277 static void msk_start(struct ifnet *); 278 static int msk_ioctl(struct ifnet *, u_long, caddr_t); 279 static void msk_set_prefetch(struct msk_softc *, int, bus_addr_t, uint32_t); 280 static void msk_set_rambuffer(struct msk_if_softc *); 281 static void msk_set_tx_stfwd(struct msk_if_softc *); 282 static void msk_init(void *); 283 static void msk_init_locked(struct msk_if_softc *); 284 static void msk_stop(struct msk_if_softc *); 285 static void msk_watchdog(struct msk_if_softc *); 286 static int msk_mediachange(struct ifnet *); 287 static void msk_mediastatus(struct ifnet *, struct ifmediareq *); 288 static void msk_phy_power(struct msk_softc *, int); 289 static void msk_dmamap_cb(void *, bus_dma_segment_t *, int, int); 290 static int msk_status_dma_alloc(struct msk_softc *); 291 static void msk_status_dma_free(struct msk_softc *); 292 static int msk_txrx_dma_alloc(struct msk_if_softc *); 293 static int msk_rx_dma_jalloc(struct msk_if_softc *); 294 static void msk_txrx_dma_free(struct msk_if_softc *); 295 static void msk_rx_dma_jfree(struct msk_if_softc *); 296 static int msk_init_rx_ring(struct msk_if_softc *); 297 static int msk_init_jumbo_rx_ring(struct msk_if_softc *); 298 static void msk_init_tx_ring(struct msk_if_softc *); 299 static __inline void msk_discard_rxbuf(struct msk_if_softc *, int); 300 static __inline void msk_discard_jumbo_rxbuf(struct msk_if_softc *, int); 301 static int msk_newbuf(struct msk_if_softc *, int); 302 static int msk_jumbo_newbuf(struct msk_if_softc *, int); 303 304 static int msk_phy_readreg(struct msk_if_softc *, int, int); 305 static int msk_phy_writereg(struct msk_if_softc *, int, int, int); 306 static int msk_miibus_readreg(device_t, int, int); 307 static int msk_miibus_writereg(device_t, int, int, int); 308 static void msk_miibus_statchg(device_t); 309 310 static void msk_rxfilter(struct msk_if_softc *); 311 static void msk_setvlan(struct msk_if_softc *, struct ifnet *); 312 313 static void msk_stats_clear(struct msk_if_softc *); 314 static void msk_stats_update(struct msk_if_softc *); 315 static int msk_sysctl_stat32(SYSCTL_HANDLER_ARGS); 316 static int msk_sysctl_stat64(SYSCTL_HANDLER_ARGS); 317 static void msk_sysctl_node(struct msk_if_softc *); 318 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int); 319 static int sysctl_hw_msk_proc_limit(SYSCTL_HANDLER_ARGS); 320 321 static device_method_t mskc_methods[] = { 322 /* Device interface */ 323 DEVMETHOD(device_probe, mskc_probe), 324 DEVMETHOD(device_attach, mskc_attach), 325 DEVMETHOD(device_detach, mskc_detach), 326 DEVMETHOD(device_suspend, mskc_suspend), 327 DEVMETHOD(device_resume, mskc_resume), 328 DEVMETHOD(device_shutdown, mskc_shutdown), 329 330 /* bus interface */ 331 DEVMETHOD(bus_print_child, bus_generic_print_child), 332 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 333 334 { NULL, NULL } 335 }; 336 337 static driver_t mskc_driver = { 338 "mskc", 339 mskc_methods, 340 sizeof(struct msk_softc) 341 }; 342 343 static devclass_t mskc_devclass; 344 345 static device_method_t msk_methods[] = { 346 /* Device interface */ 347 DEVMETHOD(device_probe, msk_probe), 348 DEVMETHOD(device_attach, msk_attach), 349 DEVMETHOD(device_detach, msk_detach), 350 DEVMETHOD(device_shutdown, bus_generic_shutdown), 351 352 /* bus interface */ 353 DEVMETHOD(bus_print_child, bus_generic_print_child), 354 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 355 356 /* MII interface */ 357 DEVMETHOD(miibus_readreg, msk_miibus_readreg), 358 DEVMETHOD(miibus_writereg, msk_miibus_writereg), 359 DEVMETHOD(miibus_statchg, msk_miibus_statchg), 360 361 { NULL, NULL } 362 }; 363 364 static driver_t msk_driver = { 365 "msk", 366 msk_methods, 367 sizeof(struct msk_if_softc) 368 }; 369 370 static devclass_t msk_devclass; 371 372 DRIVER_MODULE(mskc, pci, mskc_driver, mskc_devclass, 0, 0); 373 DRIVER_MODULE(msk, mskc, msk_driver, msk_devclass, 0, 0); 374 DRIVER_MODULE(miibus, msk, miibus_driver, miibus_devclass, 0, 0); 375 376 static struct resource_spec msk_res_spec_io[] = { 377 { SYS_RES_IOPORT, PCIR_BAR(1), RF_ACTIVE }, 378 { -1, 0, 0 } 379 }; 380 381 static struct resource_spec msk_res_spec_mem[] = { 382 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 383 { -1, 0, 0 } 384 }; 385 386 static struct resource_spec msk_irq_spec_legacy[] = { 387 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 388 { -1, 0, 0 } 389 }; 390 391 static struct resource_spec msk_irq_spec_msi[] = { 392 { SYS_RES_IRQ, 1, RF_ACTIVE }, 393 { -1, 0, 0 } 394 }; 395 396 static struct resource_spec msk_irq_spec_msi2[] = { 397 { SYS_RES_IRQ, 1, RF_ACTIVE }, 398 { SYS_RES_IRQ, 2, RF_ACTIVE }, 399 { -1, 0, 0 } 400 }; 401 402 static int 403 msk_miibus_readreg(device_t dev, int phy, int reg) 404 { 405 struct msk_if_softc *sc_if; 406 407 if (phy != PHY_ADDR_MARV) 408 return (0); 409 410 sc_if = device_get_softc(dev); 411 412 return (msk_phy_readreg(sc_if, phy, reg)); 413 } 414 415 static int 416 msk_phy_readreg(struct msk_if_softc *sc_if, int phy, int reg) 417 { 418 struct msk_softc *sc; 419 int i, val; 420 421 sc = sc_if->msk_softc; 422 423 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SMI_CTRL, 424 GM_SMI_CT_PHY_AD(phy) | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD); 425 426 for (i = 0; i < MSK_TIMEOUT; i++) { 427 DELAY(1); 428 val = GMAC_READ_2(sc, sc_if->msk_port, GM_SMI_CTRL); 429 if ((val & GM_SMI_CT_RD_VAL) != 0) { 430 val = GMAC_READ_2(sc, sc_if->msk_port, GM_SMI_DATA); 431 break; 432 } 433 } 434 435 if (i == MSK_TIMEOUT) { 436 if_printf(sc_if->msk_ifp, "phy failed to come ready\n"); 437 val = 0; 438 } 439 440 return (val); 441 } 442 443 static int 444 msk_miibus_writereg(device_t dev, int phy, int reg, int val) 445 { 446 struct msk_if_softc *sc_if; 447 448 if (phy != PHY_ADDR_MARV) 449 return (0); 450 451 sc_if = device_get_softc(dev); 452 453 return (msk_phy_writereg(sc_if, phy, reg, val)); 454 } 455 456 static int 457 msk_phy_writereg(struct msk_if_softc *sc_if, int phy, int reg, int val) 458 { 459 struct msk_softc *sc; 460 int i; 461 462 sc = sc_if->msk_softc; 463 464 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SMI_DATA, val); 465 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SMI_CTRL, 466 GM_SMI_CT_PHY_AD(phy) | GM_SMI_CT_REG_AD(reg)); 467 for (i = 0; i < MSK_TIMEOUT; i++) { 468 DELAY(1); 469 if ((GMAC_READ_2(sc, sc_if->msk_port, GM_SMI_CTRL) & 470 GM_SMI_CT_BUSY) == 0) 471 break; 472 } 473 if (i == MSK_TIMEOUT) 474 if_printf(sc_if->msk_ifp, "phy write timeout\n"); 475 476 return (0); 477 } 478 479 static void 480 msk_miibus_statchg(device_t dev) 481 { 482 struct msk_softc *sc; 483 struct msk_if_softc *sc_if; 484 struct mii_data *mii; 485 struct ifnet *ifp; 486 uint32_t gmac; 487 488 sc_if = device_get_softc(dev); 489 sc = sc_if->msk_softc; 490 491 MSK_IF_LOCK_ASSERT(sc_if); 492 493 mii = device_get_softc(sc_if->msk_miibus); 494 ifp = sc_if->msk_ifp; 495 if (mii == NULL || ifp == NULL || 496 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 497 return; 498 499 sc_if->msk_flags &= ~MSK_FLAG_LINK; 500 if ((mii->mii_media_status & (IFM_AVALID | IFM_ACTIVE)) == 501 (IFM_AVALID | IFM_ACTIVE)) { 502 switch (IFM_SUBTYPE(mii->mii_media_active)) { 503 case IFM_10_T: 504 case IFM_100_TX: 505 sc_if->msk_flags |= MSK_FLAG_LINK; 506 break; 507 case IFM_1000_T: 508 case IFM_1000_SX: 509 case IFM_1000_LX: 510 case IFM_1000_CX: 511 if ((sc_if->msk_flags & MSK_FLAG_FASTETHER) == 0) 512 sc_if->msk_flags |= MSK_FLAG_LINK; 513 break; 514 default: 515 break; 516 } 517 } 518 519 if ((sc_if->msk_flags & MSK_FLAG_LINK) != 0) { 520 /* Enable Tx FIFO Underrun. */ 521 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_MSK), 522 GM_IS_TX_FF_UR | GM_IS_RX_FF_OR); 523 /* 524 * Because mii(4) notify msk(4) that it detected link status 525 * change, there is no need to enable automatic 526 * speed/flow-control/duplex updates. 527 */ 528 gmac = GM_GPCR_AU_ALL_DIS; 529 switch (IFM_SUBTYPE(mii->mii_media_active)) { 530 case IFM_1000_SX: 531 case IFM_1000_T: 532 gmac |= GM_GPCR_SPEED_1000; 533 break; 534 case IFM_100_TX: 535 gmac |= GM_GPCR_SPEED_100; 536 break; 537 case IFM_10_T: 538 break; 539 } 540 541 if (((mii->mii_media_active & IFM_GMASK) & IFM_FDX) != 0) 542 gmac |= GM_GPCR_DUP_FULL; 543 /* Disable Rx flow control. */ 544 if (((mii->mii_media_active & IFM_GMASK) & IFM_FLAG0) == 0) 545 gmac |= GM_GPCR_FC_RX_DIS; 546 /* Disable Tx flow control. */ 547 if (((mii->mii_media_active & IFM_GMASK) & IFM_FLAG1) == 0) 548 gmac |= GM_GPCR_FC_TX_DIS; 549 gmac |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA; 550 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, gmac); 551 /* Read again to ensure writing. */ 552 GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL); 553 554 gmac = GMC_PAUSE_ON; 555 if (((mii->mii_media_active & IFM_GMASK) & 556 (IFM_FLAG0 | IFM_FLAG1)) == 0) 557 gmac = GMC_PAUSE_OFF; 558 /* Diable pause for 10/100 Mbps in half-duplex mode. */ 559 if ((((mii->mii_media_active & IFM_GMASK) & IFM_FDX) == 0) && 560 (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX || 561 IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T)) 562 gmac = GMC_PAUSE_OFF; 563 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), gmac); 564 565 /* Enable PHY interrupt for FIFO underrun/overflow. */ 566 msk_phy_writereg(sc_if, PHY_ADDR_MARV, 567 PHY_MARV_INT_MASK, PHY_M_IS_FIFO_ERROR); 568 } else { 569 /* 570 * Link state changed to down. 571 * Disable PHY interrupts. 572 */ 573 msk_phy_writereg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_MASK, 0); 574 /* Disable Rx/Tx MAC. */ 575 gmac = GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL); 576 if ((GM_GPCR_RX_ENA | GM_GPCR_TX_ENA) != 0) { 577 gmac &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA); 578 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, gmac); 579 /* Read again to ensure writing. */ 580 GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL); 581 } 582 } 583 } 584 585 static void 586 msk_rxfilter(struct msk_if_softc *sc_if) 587 { 588 struct msk_softc *sc; 589 struct ifnet *ifp; 590 struct ifmultiaddr *ifma; 591 uint32_t mchash[2]; 592 uint32_t crc; 593 uint16_t mode; 594 595 sc = sc_if->msk_softc; 596 597 MSK_IF_LOCK_ASSERT(sc_if); 598 599 ifp = sc_if->msk_ifp; 600 601 bzero(mchash, sizeof(mchash)); 602 mode = GMAC_READ_2(sc, sc_if->msk_port, GM_RX_CTRL); 603 if ((ifp->if_flags & IFF_PROMISC) != 0) 604 mode &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA); 605 else if ((ifp->if_flags & IFF_ALLMULTI) != 0) { 606 mode |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA; 607 mchash[0] = 0xffff; 608 mchash[1] = 0xffff; 609 } else { 610 mode |= GM_RXCR_UCF_ENA; 611 if_maddr_rlock(ifp); 612 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 613 if (ifma->ifma_addr->sa_family != AF_LINK) 614 continue; 615 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *) 616 ifma->ifma_addr), ETHER_ADDR_LEN); 617 /* Just want the 6 least significant bits. */ 618 crc &= 0x3f; 619 /* Set the corresponding bit in the hash table. */ 620 mchash[crc >> 5] |= 1 << (crc & 0x1f); 621 } 622 if_maddr_runlock(ifp); 623 if (mchash[0] != 0 || mchash[1] != 0) 624 mode |= GM_RXCR_MCF_ENA; 625 } 626 627 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H1, 628 mchash[0] & 0xffff); 629 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H2, 630 (mchash[0] >> 16) & 0xffff); 631 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H3, 632 mchash[1] & 0xffff); 633 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H4, 634 (mchash[1] >> 16) & 0xffff); 635 GMAC_WRITE_2(sc, sc_if->msk_port, GM_RX_CTRL, mode); 636 } 637 638 static void 639 msk_setvlan(struct msk_if_softc *sc_if, struct ifnet *ifp) 640 { 641 struct msk_softc *sc; 642 643 sc = sc_if->msk_softc; 644 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) { 645 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), 646 RX_VLAN_STRIP_ON); 647 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 648 TX_VLAN_TAG_ON); 649 } else { 650 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), 651 RX_VLAN_STRIP_OFF); 652 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 653 TX_VLAN_TAG_OFF); 654 } 655 } 656 657 static int 658 msk_init_rx_ring(struct msk_if_softc *sc_if) 659 { 660 struct msk_ring_data *rd; 661 struct msk_rxdesc *rxd; 662 int i, prod; 663 664 MSK_IF_LOCK_ASSERT(sc_if); 665 666 sc_if->msk_cdata.msk_rx_cons = 0; 667 sc_if->msk_cdata.msk_rx_prod = 0; 668 sc_if->msk_cdata.msk_rx_putwm = MSK_PUT_WM; 669 670 rd = &sc_if->msk_rdata; 671 bzero(rd->msk_rx_ring, sizeof(struct msk_rx_desc) * MSK_RX_RING_CNT); 672 prod = sc_if->msk_cdata.msk_rx_prod; 673 for (i = 0; i < MSK_RX_RING_CNT; i++) { 674 rxd = &sc_if->msk_cdata.msk_rxdesc[prod]; 675 rxd->rx_m = NULL; 676 rxd->rx_le = &rd->msk_rx_ring[prod]; 677 if (msk_newbuf(sc_if, prod) != 0) 678 return (ENOBUFS); 679 MSK_INC(prod, MSK_RX_RING_CNT); 680 } 681 682 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_ring_tag, 683 sc_if->msk_cdata.msk_rx_ring_map, 684 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 685 686 /* Update prefetch unit. */ 687 sc_if->msk_cdata.msk_rx_prod = MSK_RX_RING_CNT - 1; 688 CSR_WRITE_2(sc_if->msk_softc, 689 Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_PUT_IDX_REG), 690 sc_if->msk_cdata.msk_rx_prod); 691 692 return (0); 693 } 694 695 static int 696 msk_init_jumbo_rx_ring(struct msk_if_softc *sc_if) 697 { 698 struct msk_ring_data *rd; 699 struct msk_rxdesc *rxd; 700 int i, prod; 701 702 MSK_IF_LOCK_ASSERT(sc_if); 703 704 sc_if->msk_cdata.msk_rx_cons = 0; 705 sc_if->msk_cdata.msk_rx_prod = 0; 706 sc_if->msk_cdata.msk_rx_putwm = MSK_PUT_WM; 707 708 rd = &sc_if->msk_rdata; 709 bzero(rd->msk_jumbo_rx_ring, 710 sizeof(struct msk_rx_desc) * MSK_JUMBO_RX_RING_CNT); 711 prod = sc_if->msk_cdata.msk_rx_prod; 712 for (i = 0; i < MSK_JUMBO_RX_RING_CNT; i++) { 713 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[prod]; 714 rxd->rx_m = NULL; 715 rxd->rx_le = &rd->msk_jumbo_rx_ring[prod]; 716 if (msk_jumbo_newbuf(sc_if, prod) != 0) 717 return (ENOBUFS); 718 MSK_INC(prod, MSK_JUMBO_RX_RING_CNT); 719 } 720 721 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 722 sc_if->msk_cdata.msk_jumbo_rx_ring_map, 723 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 724 725 sc_if->msk_cdata.msk_rx_prod = MSK_JUMBO_RX_RING_CNT - 1; 726 CSR_WRITE_2(sc_if->msk_softc, 727 Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_PUT_IDX_REG), 728 sc_if->msk_cdata.msk_rx_prod); 729 730 return (0); 731 } 732 733 static void 734 msk_init_tx_ring(struct msk_if_softc *sc_if) 735 { 736 struct msk_ring_data *rd; 737 struct msk_txdesc *txd; 738 int i; 739 740 sc_if->msk_cdata.msk_tso_mtu = 0; 741 sc_if->msk_cdata.msk_tx_prod = 0; 742 sc_if->msk_cdata.msk_tx_cons = 0; 743 sc_if->msk_cdata.msk_tx_cnt = 0; 744 745 rd = &sc_if->msk_rdata; 746 bzero(rd->msk_tx_ring, sizeof(struct msk_tx_desc) * MSK_TX_RING_CNT); 747 for (i = 0; i < MSK_TX_RING_CNT; i++) { 748 txd = &sc_if->msk_cdata.msk_txdesc[i]; 749 txd->tx_m = NULL; 750 txd->tx_le = &rd->msk_tx_ring[i]; 751 } 752 753 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_ring_tag, 754 sc_if->msk_cdata.msk_tx_ring_map, 755 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 756 } 757 758 static __inline void 759 msk_discard_rxbuf(struct msk_if_softc *sc_if, int idx) 760 { 761 struct msk_rx_desc *rx_le; 762 struct msk_rxdesc *rxd; 763 struct mbuf *m; 764 765 rxd = &sc_if->msk_cdata.msk_rxdesc[idx]; 766 m = rxd->rx_m; 767 rx_le = rxd->rx_le; 768 rx_le->msk_control = htole32(m->m_len | OP_PACKET | HW_OWNER); 769 } 770 771 static __inline void 772 msk_discard_jumbo_rxbuf(struct msk_if_softc *sc_if, int idx) 773 { 774 struct msk_rx_desc *rx_le; 775 struct msk_rxdesc *rxd; 776 struct mbuf *m; 777 778 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[idx]; 779 m = rxd->rx_m; 780 rx_le = rxd->rx_le; 781 rx_le->msk_control = htole32(m->m_len | OP_PACKET | HW_OWNER); 782 } 783 784 static int 785 msk_newbuf(struct msk_if_softc *sc_if, int idx) 786 { 787 struct msk_rx_desc *rx_le; 788 struct msk_rxdesc *rxd; 789 struct mbuf *m; 790 bus_dma_segment_t segs[1]; 791 bus_dmamap_t map; 792 int nsegs; 793 794 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 795 if (m == NULL) 796 return (ENOBUFS); 797 798 m->m_len = m->m_pkthdr.len = MCLBYTES; 799 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) == 0) 800 m_adj(m, ETHER_ALIGN); 801 #ifndef __NO_STRICT_ALIGNMENT 802 else 803 m_adj(m, MSK_RX_BUF_ALIGN); 804 #endif 805 806 if (bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_rx_tag, 807 sc_if->msk_cdata.msk_rx_sparemap, m, segs, &nsegs, 808 BUS_DMA_NOWAIT) != 0) { 809 m_freem(m); 810 return (ENOBUFS); 811 } 812 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 813 814 rxd = &sc_if->msk_cdata.msk_rxdesc[idx]; 815 if (rxd->rx_m != NULL) { 816 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_tag, rxd->rx_dmamap, 817 BUS_DMASYNC_POSTREAD); 818 bus_dmamap_unload(sc_if->msk_cdata.msk_rx_tag, rxd->rx_dmamap); 819 } 820 map = rxd->rx_dmamap; 821 rxd->rx_dmamap = sc_if->msk_cdata.msk_rx_sparemap; 822 sc_if->msk_cdata.msk_rx_sparemap = map; 823 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_tag, rxd->rx_dmamap, 824 BUS_DMASYNC_PREREAD); 825 rxd->rx_m = m; 826 rx_le = rxd->rx_le; 827 rx_le->msk_addr = htole32(MSK_ADDR_LO(segs[0].ds_addr)); 828 rx_le->msk_control = 829 htole32(segs[0].ds_len | OP_PACKET | HW_OWNER); 830 831 return (0); 832 } 833 834 static int 835 msk_jumbo_newbuf(struct msk_if_softc *sc_if, int idx) 836 { 837 struct msk_rx_desc *rx_le; 838 struct msk_rxdesc *rxd; 839 struct mbuf *m; 840 bus_dma_segment_t segs[1]; 841 bus_dmamap_t map; 842 int nsegs; 843 844 m = m_getjcl(M_DONTWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES); 845 if (m == NULL) 846 return (ENOBUFS); 847 if ((m->m_flags & M_EXT) == 0) { 848 m_freem(m); 849 return (ENOBUFS); 850 } 851 m->m_len = m->m_pkthdr.len = MJUM9BYTES; 852 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) == 0) 853 m_adj(m, ETHER_ALIGN); 854 #ifndef __NO_STRICT_ALIGNMENT 855 else 856 m_adj(m, MSK_RX_BUF_ALIGN); 857 #endif 858 859 if (bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_jumbo_rx_tag, 860 sc_if->msk_cdata.msk_jumbo_rx_sparemap, m, segs, &nsegs, 861 BUS_DMA_NOWAIT) != 0) { 862 m_freem(m); 863 return (ENOBUFS); 864 } 865 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 866 867 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[idx]; 868 if (rxd->rx_m != NULL) { 869 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_tag, 870 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 871 bus_dmamap_unload(sc_if->msk_cdata.msk_jumbo_rx_tag, 872 rxd->rx_dmamap); 873 } 874 map = rxd->rx_dmamap; 875 rxd->rx_dmamap = sc_if->msk_cdata.msk_jumbo_rx_sparemap; 876 sc_if->msk_cdata.msk_jumbo_rx_sparemap = map; 877 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_tag, rxd->rx_dmamap, 878 BUS_DMASYNC_PREREAD); 879 rxd->rx_m = m; 880 rx_le = rxd->rx_le; 881 rx_le->msk_addr = htole32(MSK_ADDR_LO(segs[0].ds_addr)); 882 rx_le->msk_control = 883 htole32(segs[0].ds_len | OP_PACKET | HW_OWNER); 884 885 return (0); 886 } 887 888 /* 889 * Set media options. 890 */ 891 static int 892 msk_mediachange(struct ifnet *ifp) 893 { 894 struct msk_if_softc *sc_if; 895 struct mii_data *mii; 896 int error; 897 898 sc_if = ifp->if_softc; 899 900 MSK_IF_LOCK(sc_if); 901 mii = device_get_softc(sc_if->msk_miibus); 902 error = mii_mediachg(mii); 903 MSK_IF_UNLOCK(sc_if); 904 905 return (error); 906 } 907 908 /* 909 * Report current media status. 910 */ 911 static void 912 msk_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 913 { 914 struct msk_if_softc *sc_if; 915 struct mii_data *mii; 916 917 sc_if = ifp->if_softc; 918 MSK_IF_LOCK(sc_if); 919 if ((ifp->if_flags & IFF_UP) == 0) { 920 MSK_IF_UNLOCK(sc_if); 921 return; 922 } 923 mii = device_get_softc(sc_if->msk_miibus); 924 925 mii_pollstat(mii); 926 MSK_IF_UNLOCK(sc_if); 927 ifmr->ifm_active = mii->mii_media_active; 928 ifmr->ifm_status = mii->mii_media_status; 929 } 930 931 static int 932 msk_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 933 { 934 struct msk_if_softc *sc_if; 935 struct ifreq *ifr; 936 struct mii_data *mii; 937 int error, mask; 938 939 sc_if = ifp->if_softc; 940 ifr = (struct ifreq *)data; 941 error = 0; 942 943 switch(command) { 944 case SIOCSIFMTU: 945 MSK_IF_LOCK(sc_if); 946 if (ifr->ifr_mtu > MSK_JUMBO_MTU || ifr->ifr_mtu < ETHERMIN) 947 error = EINVAL; 948 else if (ifp->if_mtu != ifr->ifr_mtu) { 949 if (ifr->ifr_mtu > ETHERMTU) { 950 if ((sc_if->msk_flags & MSK_FLAG_JUMBO) == 0) { 951 error = EINVAL; 952 MSK_IF_UNLOCK(sc_if); 953 break; 954 } 955 if ((sc_if->msk_flags & 956 MSK_FLAG_JUMBO_NOCSUM) != 0) { 957 ifp->if_hwassist &= 958 ~(MSK_CSUM_FEATURES | CSUM_TSO); 959 ifp->if_capenable &= 960 ~(IFCAP_TSO4 | IFCAP_TXCSUM); 961 VLAN_CAPABILITIES(ifp); 962 } 963 } 964 ifp->if_mtu = ifr->ifr_mtu; 965 msk_init_locked(sc_if); 966 } 967 MSK_IF_UNLOCK(sc_if); 968 break; 969 case SIOCSIFFLAGS: 970 MSK_IF_LOCK(sc_if); 971 if ((ifp->if_flags & IFF_UP) != 0) { 972 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 && 973 ((ifp->if_flags ^ sc_if->msk_if_flags) & 974 (IFF_PROMISC | IFF_ALLMULTI)) != 0) 975 msk_rxfilter(sc_if); 976 else if ((sc_if->msk_flags & MSK_FLAG_DETACH) == 0) 977 msk_init_locked(sc_if); 978 } else if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 979 msk_stop(sc_if); 980 sc_if->msk_if_flags = ifp->if_flags; 981 MSK_IF_UNLOCK(sc_if); 982 break; 983 case SIOCADDMULTI: 984 case SIOCDELMULTI: 985 MSK_IF_LOCK(sc_if); 986 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 987 msk_rxfilter(sc_if); 988 MSK_IF_UNLOCK(sc_if); 989 break; 990 case SIOCGIFMEDIA: 991 case SIOCSIFMEDIA: 992 mii = device_get_softc(sc_if->msk_miibus); 993 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 994 break; 995 case SIOCSIFCAP: 996 MSK_IF_LOCK(sc_if); 997 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 998 if ((mask & IFCAP_TXCSUM) != 0 && 999 (IFCAP_TXCSUM & ifp->if_capabilities) != 0) { 1000 ifp->if_capenable ^= IFCAP_TXCSUM; 1001 if ((IFCAP_TXCSUM & ifp->if_capenable) != 0) 1002 ifp->if_hwassist |= MSK_CSUM_FEATURES; 1003 else 1004 ifp->if_hwassist &= ~MSK_CSUM_FEATURES; 1005 } 1006 if ((mask & IFCAP_RXCSUM) != 0 && 1007 (IFCAP_RXCSUM & ifp->if_capabilities) != 0) 1008 ifp->if_capenable ^= IFCAP_RXCSUM; 1009 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 1010 (IFCAP_VLAN_HWTAGGING & ifp->if_capabilities) != 0) { 1011 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 1012 msk_setvlan(sc_if, ifp); 1013 } 1014 if ((mask & IFCAP_VLAN_HWCSUM) != 0 && 1015 (IFCAP_VLAN_HWCSUM & ifp->if_capabilities) != 0) 1016 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; 1017 if ((mask & IFCAP_TSO4) != 0 && 1018 (IFCAP_TSO4 & ifp->if_capabilities) != 0) { 1019 ifp->if_capenable ^= IFCAP_TSO4; 1020 if ((IFCAP_TSO4 & ifp->if_capenable) != 0) 1021 ifp->if_hwassist |= CSUM_TSO; 1022 else 1023 ifp->if_hwassist &= ~CSUM_TSO; 1024 } 1025 if (ifp->if_mtu > ETHERMTU && 1026 (sc_if->msk_flags & MSK_FLAG_JUMBO_NOCSUM) != 0) { 1027 ifp->if_hwassist &= ~(MSK_CSUM_FEATURES | CSUM_TSO); 1028 ifp->if_capenable &= ~(IFCAP_TSO4 | IFCAP_TXCSUM); 1029 } 1030 1031 VLAN_CAPABILITIES(ifp); 1032 MSK_IF_UNLOCK(sc_if); 1033 break; 1034 default: 1035 error = ether_ioctl(ifp, command, data); 1036 break; 1037 } 1038 1039 return (error); 1040 } 1041 1042 static int 1043 mskc_probe(device_t dev) 1044 { 1045 struct msk_product *mp; 1046 uint16_t vendor, devid; 1047 int i; 1048 1049 vendor = pci_get_vendor(dev); 1050 devid = pci_get_device(dev); 1051 mp = msk_products; 1052 for (i = 0; i < sizeof(msk_products)/sizeof(msk_products[0]); 1053 i++, mp++) { 1054 if (vendor == mp->msk_vendorid && devid == mp->msk_deviceid) { 1055 device_set_desc(dev, mp->msk_name); 1056 return (BUS_PROBE_DEFAULT); 1057 } 1058 } 1059 1060 return (ENXIO); 1061 } 1062 1063 static int 1064 mskc_setup_rambuffer(struct msk_softc *sc) 1065 { 1066 int next; 1067 int i; 1068 1069 /* Get adapter SRAM size. */ 1070 sc->msk_ramsize = CSR_READ_1(sc, B2_E_0) * 4; 1071 if (bootverbose) 1072 device_printf(sc->msk_dev, 1073 "RAM buffer size : %dKB\n", sc->msk_ramsize); 1074 if (sc->msk_ramsize == 0) 1075 return (0); 1076 1077 sc->msk_pflags |= MSK_FLAG_RAMBUF; 1078 /* 1079 * Give receiver 2/3 of memory and round down to the multiple 1080 * of 1024. Tx/Rx RAM buffer size of Yukon II shoud be multiple 1081 * of 1024. 1082 */ 1083 sc->msk_rxqsize = rounddown((sc->msk_ramsize * 1024 * 2) / 3, 1024); 1084 sc->msk_txqsize = (sc->msk_ramsize * 1024) - sc->msk_rxqsize; 1085 for (i = 0, next = 0; i < sc->msk_num_port; i++) { 1086 sc->msk_rxqstart[i] = next; 1087 sc->msk_rxqend[i] = next + sc->msk_rxqsize - 1; 1088 next = sc->msk_rxqend[i] + 1; 1089 sc->msk_txqstart[i] = next; 1090 sc->msk_txqend[i] = next + sc->msk_txqsize - 1; 1091 next = sc->msk_txqend[i] + 1; 1092 if (bootverbose) { 1093 device_printf(sc->msk_dev, 1094 "Port %d : Rx Queue %dKB(0x%08x:0x%08x)\n", i, 1095 sc->msk_rxqsize / 1024, sc->msk_rxqstart[i], 1096 sc->msk_rxqend[i]); 1097 device_printf(sc->msk_dev, 1098 "Port %d : Tx Queue %dKB(0x%08x:0x%08x)\n", i, 1099 sc->msk_txqsize / 1024, sc->msk_txqstart[i], 1100 sc->msk_txqend[i]); 1101 } 1102 } 1103 1104 return (0); 1105 } 1106 1107 static void 1108 msk_phy_power(struct msk_softc *sc, int mode) 1109 { 1110 uint32_t our, val; 1111 int i; 1112 1113 switch (mode) { 1114 case MSK_PHY_POWERUP: 1115 /* Switch power to VCC (WA for VAUX problem). */ 1116 CSR_WRITE_1(sc, B0_POWER_CTRL, 1117 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON); 1118 /* Disable Core Clock Division, set Clock Select to 0. */ 1119 CSR_WRITE_4(sc, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS); 1120 1121 val = 0; 1122 if (sc->msk_hw_id == CHIP_ID_YUKON_XL && 1123 sc->msk_hw_rev > CHIP_REV_YU_XL_A1) { 1124 /* Enable bits are inverted. */ 1125 val = Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS | 1126 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS | 1127 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS; 1128 } 1129 /* 1130 * Enable PCI & Core Clock, enable clock gating for both Links. 1131 */ 1132 CSR_WRITE_1(sc, B2_Y2_CLK_GATE, val); 1133 1134 val = pci_read_config(sc->msk_dev, PCI_OUR_REG_1, 4); 1135 val &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD); 1136 if (sc->msk_hw_id == CHIP_ID_YUKON_XL) { 1137 if (sc->msk_hw_rev > CHIP_REV_YU_XL_A1) { 1138 /* Deassert Low Power for 1st PHY. */ 1139 val |= PCI_Y2_PHY1_COMA; 1140 if (sc->msk_num_port > 1) 1141 val |= PCI_Y2_PHY2_COMA; 1142 } 1143 } 1144 /* Release PHY from PowerDown/COMA mode. */ 1145 pci_write_config(sc->msk_dev, PCI_OUR_REG_1, val, 4); 1146 switch (sc->msk_hw_id) { 1147 case CHIP_ID_YUKON_EC_U: 1148 case CHIP_ID_YUKON_EX: 1149 case CHIP_ID_YUKON_FE_P: 1150 case CHIP_ID_YUKON_UL_2: 1151 CSR_WRITE_2(sc, B0_CTST, Y2_HW_WOL_OFF); 1152 1153 /* Enable all clocks. */ 1154 pci_write_config(sc->msk_dev, PCI_OUR_REG_3, 0, 4); 1155 our = pci_read_config(sc->msk_dev, PCI_OUR_REG_4, 4); 1156 our &= (PCI_FORCE_ASPM_REQUEST|PCI_ASPM_GPHY_LINK_DOWN| 1157 PCI_ASPM_INT_FIFO_EMPTY|PCI_ASPM_CLKRUN_REQUEST); 1158 /* Set all bits to 0 except bits 15..12. */ 1159 pci_write_config(sc->msk_dev, PCI_OUR_REG_4, our, 4); 1160 our = pci_read_config(sc->msk_dev, PCI_OUR_REG_5, 4); 1161 our &= PCI_CTL_TIM_VMAIN_AV_MSK; 1162 pci_write_config(sc->msk_dev, PCI_OUR_REG_5, our, 4); 1163 pci_write_config(sc->msk_dev, PCI_CFG_REG_1, 0, 4); 1164 /* 1165 * Disable status race, workaround for 1166 * Yukon EC Ultra & Yukon EX. 1167 */ 1168 val = CSR_READ_4(sc, B2_GP_IO); 1169 val |= GLB_GPIO_STAT_RACE_DIS; 1170 CSR_WRITE_4(sc, B2_GP_IO, val); 1171 CSR_READ_4(sc, B2_GP_IO); 1172 break; 1173 default: 1174 break; 1175 } 1176 for (i = 0; i < sc->msk_num_port; i++) { 1177 CSR_WRITE_2(sc, MR_ADDR(i, GMAC_LINK_CTRL), 1178 GMLC_RST_SET); 1179 CSR_WRITE_2(sc, MR_ADDR(i, GMAC_LINK_CTRL), 1180 GMLC_RST_CLR); 1181 } 1182 break; 1183 case MSK_PHY_POWERDOWN: 1184 val = pci_read_config(sc->msk_dev, PCI_OUR_REG_1, 4); 1185 val |= PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD; 1186 if (sc->msk_hw_id == CHIP_ID_YUKON_XL && 1187 sc->msk_hw_rev > CHIP_REV_YU_XL_A1) { 1188 val &= ~PCI_Y2_PHY1_COMA; 1189 if (sc->msk_num_port > 1) 1190 val &= ~PCI_Y2_PHY2_COMA; 1191 } 1192 pci_write_config(sc->msk_dev, PCI_OUR_REG_1, val, 4); 1193 1194 val = Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS | 1195 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS | 1196 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS; 1197 if (sc->msk_hw_id == CHIP_ID_YUKON_XL && 1198 sc->msk_hw_rev > CHIP_REV_YU_XL_A1) { 1199 /* Enable bits are inverted. */ 1200 val = 0; 1201 } 1202 /* 1203 * Disable PCI & Core Clock, disable clock gating for 1204 * both Links. 1205 */ 1206 CSR_WRITE_1(sc, B2_Y2_CLK_GATE, val); 1207 CSR_WRITE_1(sc, B0_POWER_CTRL, 1208 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_ON | PC_VCC_OFF); 1209 break; 1210 default: 1211 break; 1212 } 1213 } 1214 1215 static void 1216 mskc_reset(struct msk_softc *sc) 1217 { 1218 bus_addr_t addr; 1219 uint16_t status; 1220 uint32_t val; 1221 int i; 1222 1223 CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR); 1224 1225 /* Disable ASF. */ 1226 if (sc->msk_hw_id == CHIP_ID_YUKON_EX) { 1227 status = CSR_READ_2(sc, B28_Y2_ASF_HCU_CCSR); 1228 /* Clear AHB bridge & microcontroller reset. */ 1229 status &= ~(Y2_ASF_HCU_CCSR_AHB_RST | 1230 Y2_ASF_HCU_CCSR_CPU_RST_MODE); 1231 /* Clear ASF microcontroller state. */ 1232 status &= ~ Y2_ASF_HCU_CCSR_UC_STATE_MSK; 1233 CSR_WRITE_2(sc, B28_Y2_ASF_HCU_CCSR, status); 1234 } else 1235 CSR_WRITE_1(sc, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET); 1236 CSR_WRITE_2(sc, B0_CTST, Y2_ASF_DISABLE); 1237 1238 /* 1239 * Since we disabled ASF, S/W reset is required for Power Management. 1240 */ 1241 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); 1242 CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR); 1243 1244 /* Clear all error bits in the PCI status register. */ 1245 status = pci_read_config(sc->msk_dev, PCIR_STATUS, 2); 1246 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON); 1247 1248 pci_write_config(sc->msk_dev, PCIR_STATUS, status | 1249 PCIM_STATUS_PERR | PCIM_STATUS_SERR | PCIM_STATUS_RMABORT | 1250 PCIM_STATUS_RTABORT | PCIM_STATUS_PERRREPORT, 2); 1251 CSR_WRITE_2(sc, B0_CTST, CS_MRST_CLR); 1252 1253 switch (sc->msk_bustype) { 1254 case MSK_PEX_BUS: 1255 /* Clear all PEX errors. */ 1256 CSR_PCI_WRITE_4(sc, PEX_UNC_ERR_STAT, 0xffffffff); 1257 val = CSR_PCI_READ_4(sc, PEX_UNC_ERR_STAT); 1258 if ((val & PEX_RX_OV) != 0) { 1259 sc->msk_intrmask &= ~Y2_IS_HW_ERR; 1260 sc->msk_intrhwemask &= ~Y2_IS_PCI_EXP; 1261 } 1262 break; 1263 case MSK_PCI_BUS: 1264 case MSK_PCIX_BUS: 1265 /* Set Cache Line Size to 2(8bytes) if configured to 0. */ 1266 val = pci_read_config(sc->msk_dev, PCIR_CACHELNSZ, 1); 1267 if (val == 0) 1268 pci_write_config(sc->msk_dev, PCIR_CACHELNSZ, 2, 1); 1269 if (sc->msk_bustype == MSK_PCIX_BUS) { 1270 /* Set Cache Line Size opt. */ 1271 val = pci_read_config(sc->msk_dev, PCI_OUR_REG_1, 4); 1272 val |= PCI_CLS_OPT; 1273 pci_write_config(sc->msk_dev, PCI_OUR_REG_1, val, 4); 1274 } 1275 break; 1276 } 1277 /* Set PHY power state. */ 1278 msk_phy_power(sc, MSK_PHY_POWERUP); 1279 1280 /* Reset GPHY/GMAC Control */ 1281 for (i = 0; i < sc->msk_num_port; i++) { 1282 /* GPHY Control reset. */ 1283 CSR_WRITE_4(sc, MR_ADDR(i, GPHY_CTRL), GPC_RST_SET); 1284 CSR_WRITE_4(sc, MR_ADDR(i, GPHY_CTRL), GPC_RST_CLR); 1285 /* GMAC Control reset. */ 1286 CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), GMC_RST_SET); 1287 CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), GMC_RST_CLR); 1288 CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), GMC_F_LOOPB_OFF); 1289 if (sc->msk_hw_id == CHIP_ID_YUKON_EX) 1290 CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), 1291 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON | 1292 GMC_BYP_RETR_ON); 1293 } 1294 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 1295 1296 /* LED On. */ 1297 CSR_WRITE_2(sc, B0_CTST, Y2_LED_STAT_ON); 1298 1299 /* Clear TWSI IRQ. */ 1300 CSR_WRITE_4(sc, B2_I2C_IRQ, I2C_CLR_IRQ); 1301 1302 /* Turn off hardware timer. */ 1303 CSR_WRITE_1(sc, B2_TI_CTRL, TIM_STOP); 1304 CSR_WRITE_1(sc, B2_TI_CTRL, TIM_CLR_IRQ); 1305 1306 /* Turn off descriptor polling. */ 1307 CSR_WRITE_1(sc, B28_DPT_CTRL, DPT_STOP); 1308 1309 /* Turn off time stamps. */ 1310 CSR_WRITE_1(sc, GMAC_TI_ST_CTRL, GMT_ST_STOP); 1311 CSR_WRITE_1(sc, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ); 1312 1313 /* Configure timeout values. */ 1314 for (i = 0; i < sc->msk_num_port; i++) { 1315 CSR_WRITE_2(sc, SELECT_RAM_BUFFER(i, B3_RI_CTRL), RI_RST_SET); 1316 CSR_WRITE_2(sc, SELECT_RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR); 1317 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_R1), 1318 MSK_RI_TO_53); 1319 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XA1), 1320 MSK_RI_TO_53); 1321 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XS1), 1322 MSK_RI_TO_53); 1323 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_R1), 1324 MSK_RI_TO_53); 1325 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XA1), 1326 MSK_RI_TO_53); 1327 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XS1), 1328 MSK_RI_TO_53); 1329 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_R2), 1330 MSK_RI_TO_53); 1331 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XA2), 1332 MSK_RI_TO_53); 1333 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XS2), 1334 MSK_RI_TO_53); 1335 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_R2), 1336 MSK_RI_TO_53); 1337 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XA2), 1338 MSK_RI_TO_53); 1339 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XS2), 1340 MSK_RI_TO_53); 1341 } 1342 1343 /* Disable all interrupts. */ 1344 CSR_WRITE_4(sc, B0_HWE_IMSK, 0); 1345 CSR_READ_4(sc, B0_HWE_IMSK); 1346 CSR_WRITE_4(sc, B0_IMSK, 0); 1347 CSR_READ_4(sc, B0_IMSK); 1348 1349 /* 1350 * On dual port PCI-X card, there is an problem where status 1351 * can be received out of order due to split transactions. 1352 */ 1353 if (sc->msk_bustype == MSK_PCIX_BUS && sc->msk_num_port > 1) { 1354 int pcix; 1355 uint16_t pcix_cmd; 1356 1357 if (pci_find_extcap(sc->msk_dev, PCIY_PCIX, &pcix) == 0) { 1358 pcix_cmd = pci_read_config(sc->msk_dev, pcix + 2, 2); 1359 /* Clear Max Outstanding Split Transactions. */ 1360 pcix_cmd &= ~0x70; 1361 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON); 1362 pci_write_config(sc->msk_dev, pcix + 2, pcix_cmd, 2); 1363 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 1364 } 1365 } 1366 if (sc->msk_bustype == MSK_PEX_BUS) { 1367 uint16_t v, width; 1368 1369 v = pci_read_config(sc->msk_dev, PEX_DEV_CTRL, 2); 1370 /* Change Max. Read Request Size to 4096 bytes. */ 1371 v &= ~PEX_DC_MAX_RRS_MSK; 1372 v |= PEX_DC_MAX_RD_RQ_SIZE(5); 1373 pci_write_config(sc->msk_dev, PEX_DEV_CTRL, v, 2); 1374 width = pci_read_config(sc->msk_dev, PEX_LNK_STAT, 2); 1375 width = (width & PEX_LS_LINK_WI_MSK) >> 4; 1376 v = pci_read_config(sc->msk_dev, PEX_LNK_CAP, 2); 1377 v = (v & PEX_LS_LINK_WI_MSK) >> 4; 1378 if (v != width) 1379 device_printf(sc->msk_dev, 1380 "negotiated width of link(x%d) != " 1381 "max. width of link(x%d)\n", width, v); 1382 } 1383 1384 /* Clear status list. */ 1385 bzero(sc->msk_stat_ring, 1386 sizeof(struct msk_stat_desc) * MSK_STAT_RING_CNT); 1387 sc->msk_stat_cons = 0; 1388 bus_dmamap_sync(sc->msk_stat_tag, sc->msk_stat_map, 1389 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1390 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_RST_SET); 1391 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_RST_CLR); 1392 /* Set the status list base address. */ 1393 addr = sc->msk_stat_ring_paddr; 1394 CSR_WRITE_4(sc, STAT_LIST_ADDR_LO, MSK_ADDR_LO(addr)); 1395 CSR_WRITE_4(sc, STAT_LIST_ADDR_HI, MSK_ADDR_HI(addr)); 1396 /* Set the status list last index. */ 1397 CSR_WRITE_2(sc, STAT_LAST_IDX, MSK_STAT_RING_CNT - 1); 1398 if (sc->msk_hw_id == CHIP_ID_YUKON_EC && 1399 sc->msk_hw_rev == CHIP_REV_YU_EC_A1) { 1400 /* WA for dev. #4.3 */ 1401 CSR_WRITE_2(sc, STAT_TX_IDX_TH, ST_TXTH_IDX_MASK); 1402 /* WA for dev. #4.18 */ 1403 CSR_WRITE_1(sc, STAT_FIFO_WM, 0x21); 1404 CSR_WRITE_1(sc, STAT_FIFO_ISR_WM, 0x07); 1405 } else { 1406 CSR_WRITE_2(sc, STAT_TX_IDX_TH, 0x0a); 1407 CSR_WRITE_1(sc, STAT_FIFO_WM, 0x10); 1408 if (sc->msk_hw_id == CHIP_ID_YUKON_XL && 1409 sc->msk_hw_rev == CHIP_REV_YU_XL_A0) 1410 CSR_WRITE_1(sc, STAT_FIFO_ISR_WM, 0x04); 1411 else 1412 CSR_WRITE_1(sc, STAT_FIFO_ISR_WM, 0x10); 1413 CSR_WRITE_4(sc, STAT_ISR_TIMER_INI, 0x0190); 1414 } 1415 /* 1416 * Use default value for STAT_ISR_TIMER_INI, STAT_LEV_TIMER_INI. 1417 */ 1418 CSR_WRITE_4(sc, STAT_TX_TIMER_INI, MSK_USECS(sc, 1000)); 1419 1420 /* Enable status unit. */ 1421 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_OP_ON); 1422 1423 CSR_WRITE_1(sc, STAT_TX_TIMER_CTRL, TIM_START); 1424 CSR_WRITE_1(sc, STAT_LEV_TIMER_CTRL, TIM_START); 1425 CSR_WRITE_1(sc, STAT_ISR_TIMER_CTRL, TIM_START); 1426 } 1427 1428 static int 1429 msk_probe(device_t dev) 1430 { 1431 struct msk_softc *sc; 1432 char desc[100]; 1433 1434 sc = device_get_softc(device_get_parent(dev)); 1435 /* 1436 * Not much to do here. We always know there will be 1437 * at least one GMAC present, and if there are two, 1438 * mskc_attach() will create a second device instance 1439 * for us. 1440 */ 1441 snprintf(desc, sizeof(desc), 1442 "Marvell Technology Group Ltd. %s Id 0x%02x Rev 0x%02x", 1443 model_name[sc->msk_hw_id - CHIP_ID_YUKON_XL], sc->msk_hw_id, 1444 sc->msk_hw_rev); 1445 device_set_desc_copy(dev, desc); 1446 1447 return (BUS_PROBE_DEFAULT); 1448 } 1449 1450 static int 1451 msk_attach(device_t dev) 1452 { 1453 struct msk_softc *sc; 1454 struct msk_if_softc *sc_if; 1455 struct ifnet *ifp; 1456 struct msk_mii_data *mmd; 1457 int i, port, error; 1458 uint8_t eaddr[6]; 1459 1460 if (dev == NULL) 1461 return (EINVAL); 1462 1463 error = 0; 1464 sc_if = device_get_softc(dev); 1465 sc = device_get_softc(device_get_parent(dev)); 1466 mmd = device_get_ivars(dev); 1467 port = mmd->port; 1468 1469 sc_if->msk_if_dev = dev; 1470 sc_if->msk_port = port; 1471 sc_if->msk_softc = sc; 1472 sc_if->msk_flags = sc->msk_pflags; 1473 sc->msk_if[port] = sc_if; 1474 /* Setup Tx/Rx queue register offsets. */ 1475 if (port == MSK_PORT_A) { 1476 sc_if->msk_txq = Q_XA1; 1477 sc_if->msk_txsq = Q_XS1; 1478 sc_if->msk_rxq = Q_R1; 1479 } else { 1480 sc_if->msk_txq = Q_XA2; 1481 sc_if->msk_txsq = Q_XS2; 1482 sc_if->msk_rxq = Q_R2; 1483 } 1484 1485 callout_init_mtx(&sc_if->msk_tick_ch, &sc_if->msk_softc->msk_mtx, 0); 1486 msk_sysctl_node(sc_if); 1487 1488 if ((error = msk_txrx_dma_alloc(sc_if) != 0)) 1489 goto fail; 1490 msk_rx_dma_jalloc(sc_if); 1491 1492 ifp = sc_if->msk_ifp = if_alloc(IFT_ETHER); 1493 if (ifp == NULL) { 1494 device_printf(sc_if->msk_if_dev, "can not if_alloc()\n"); 1495 error = ENOSPC; 1496 goto fail; 1497 } 1498 ifp->if_softc = sc_if; 1499 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1500 ifp->if_mtu = ETHERMTU; 1501 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1502 /* 1503 * IFCAP_RXCSUM capability is intentionally disabled as the hardware 1504 * has serious bug in Rx checksum offload for all Yukon II family 1505 * hardware. It seems there is a workaround to make it work somtimes. 1506 * However, the workaround also have to check OP code sequences to 1507 * verify whether the OP code is correct. Sometimes it should compute 1508 * IP/TCP/UDP checksum in driver in order to verify correctness of 1509 * checksum computed by hardware. If you have to compute checksum 1510 * with software to verify the hardware's checksum why have hardware 1511 * compute the checksum? I think there is no reason to spend time to 1512 * make Rx checksum offload work on Yukon II hardware. 1513 */ 1514 ifp->if_capabilities = IFCAP_TXCSUM | IFCAP_TSO4; 1515 /* 1516 * Enable Rx checksum offloading if controller support new 1517 * descriptor format. 1518 */ 1519 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) != 0 && 1520 (sc_if->msk_flags & MSK_FLAG_NORX_CSUM) == 0) 1521 ifp->if_capabilities |= IFCAP_RXCSUM; 1522 ifp->if_hwassist = MSK_CSUM_FEATURES | CSUM_TSO; 1523 ifp->if_capenable = ifp->if_capabilities; 1524 ifp->if_ioctl = msk_ioctl; 1525 ifp->if_start = msk_start; 1526 ifp->if_init = msk_init; 1527 IFQ_SET_MAXLEN(&ifp->if_snd, MSK_TX_RING_CNT - 1); 1528 ifp->if_snd.ifq_drv_maxlen = MSK_TX_RING_CNT - 1; 1529 IFQ_SET_READY(&ifp->if_snd); 1530 1531 TASK_INIT(&sc_if->msk_tx_task, 1, msk_tx_task, ifp); 1532 1533 /* 1534 * Get station address for this interface. Note that 1535 * dual port cards actually come with three station 1536 * addresses: one for each port, plus an extra. The 1537 * extra one is used by the SysKonnect driver software 1538 * as a 'virtual' station address for when both ports 1539 * are operating in failover mode. Currently we don't 1540 * use this extra address. 1541 */ 1542 MSK_IF_LOCK(sc_if); 1543 for (i = 0; i < ETHER_ADDR_LEN; i++) 1544 eaddr[i] = CSR_READ_1(sc, B2_MAC_1 + (port * 8) + i); 1545 1546 /* 1547 * Call MI attach routine. Can't hold locks when calling into ether_*. 1548 */ 1549 MSK_IF_UNLOCK(sc_if); 1550 ether_ifattach(ifp, eaddr); 1551 MSK_IF_LOCK(sc_if); 1552 1553 /* VLAN capability setup */ 1554 ifp->if_capabilities |= IFCAP_VLAN_MTU; 1555 if ((sc_if->msk_flags & MSK_FLAG_NOHWVLAN) == 0) { 1556 /* 1557 * Due to Tx checksum offload hardware bugs, msk(4) manually 1558 * computes checksum for short frames. For VLAN tagged frames 1559 * this workaround does not work so disable checksum offload 1560 * for VLAN interface. 1561 */ 1562 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING; 1563 /* 1564 * Enable Rx checksum offloading for VLAN taggedd frames 1565 * if controller support new descriptor format. 1566 */ 1567 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) != 0 && 1568 (sc_if->msk_flags & MSK_FLAG_NORX_CSUM) == 0) 1569 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM; 1570 } 1571 ifp->if_capenable = ifp->if_capabilities; 1572 1573 /* 1574 * Tell the upper layer(s) we support long frames. 1575 * Must appear after the call to ether_ifattach() because 1576 * ether_ifattach() sets ifi_hdrlen to the default value. 1577 */ 1578 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1579 1580 /* 1581 * Do miibus setup. 1582 */ 1583 MSK_IF_UNLOCK(sc_if); 1584 error = mii_phy_probe(dev, &sc_if->msk_miibus, msk_mediachange, 1585 msk_mediastatus); 1586 if (error != 0) { 1587 device_printf(sc_if->msk_if_dev, "no PHY found!\n"); 1588 ether_ifdetach(ifp); 1589 error = ENXIO; 1590 goto fail; 1591 } 1592 1593 fail: 1594 if (error != 0) { 1595 /* Access should be ok even though lock has been dropped */ 1596 sc->msk_if[port] = NULL; 1597 msk_detach(dev); 1598 } 1599 1600 return (error); 1601 } 1602 1603 /* 1604 * Attach the interface. Allocate softc structures, do ifmedia 1605 * setup and ethernet/BPF attach. 1606 */ 1607 static int 1608 mskc_attach(device_t dev) 1609 { 1610 struct msk_softc *sc; 1611 struct msk_mii_data *mmd; 1612 int error, msic, msir, reg; 1613 1614 sc = device_get_softc(dev); 1615 sc->msk_dev = dev; 1616 mtx_init(&sc->msk_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1617 MTX_DEF); 1618 1619 /* 1620 * Map control/status registers. 1621 */ 1622 pci_enable_busmaster(dev); 1623 1624 /* Allocate I/O resource */ 1625 #ifdef MSK_USEIOSPACE 1626 sc->msk_res_spec = msk_res_spec_io; 1627 #else 1628 sc->msk_res_spec = msk_res_spec_mem; 1629 #endif 1630 sc->msk_irq_spec = msk_irq_spec_legacy; 1631 error = bus_alloc_resources(dev, sc->msk_res_spec, sc->msk_res); 1632 if (error) { 1633 if (sc->msk_res_spec == msk_res_spec_mem) 1634 sc->msk_res_spec = msk_res_spec_io; 1635 else 1636 sc->msk_res_spec = msk_res_spec_mem; 1637 error = bus_alloc_resources(dev, sc->msk_res_spec, sc->msk_res); 1638 if (error) { 1639 device_printf(dev, "couldn't allocate %s resources\n", 1640 sc->msk_res_spec == msk_res_spec_mem ? "memory" : 1641 "I/O"); 1642 mtx_destroy(&sc->msk_mtx); 1643 return (ENXIO); 1644 } 1645 } 1646 1647 CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR); 1648 sc->msk_hw_id = CSR_READ_1(sc, B2_CHIP_ID); 1649 sc->msk_hw_rev = (CSR_READ_1(sc, B2_MAC_CFG) >> 4) & 0x0f; 1650 /* Bail out if chip is not recognized. */ 1651 if (sc->msk_hw_id < CHIP_ID_YUKON_XL || 1652 sc->msk_hw_id > CHIP_ID_YUKON_UL_2 || 1653 sc->msk_hw_id == CHIP_ID_YUKON_SUPR) { 1654 device_printf(dev, "unknown device: id=0x%02x, rev=0x%02x\n", 1655 sc->msk_hw_id, sc->msk_hw_rev); 1656 mtx_destroy(&sc->msk_mtx); 1657 return (ENXIO); 1658 } 1659 1660 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 1661 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 1662 OID_AUTO, "process_limit", CTLTYPE_INT | CTLFLAG_RW, 1663 &sc->msk_process_limit, 0, sysctl_hw_msk_proc_limit, "I", 1664 "max number of Rx events to process"); 1665 1666 sc->msk_process_limit = MSK_PROC_DEFAULT; 1667 error = resource_int_value(device_get_name(dev), device_get_unit(dev), 1668 "process_limit", &sc->msk_process_limit); 1669 if (error == 0) { 1670 if (sc->msk_process_limit < MSK_PROC_MIN || 1671 sc->msk_process_limit > MSK_PROC_MAX) { 1672 device_printf(dev, "process_limit value out of range; " 1673 "using default: %d\n", MSK_PROC_DEFAULT); 1674 sc->msk_process_limit = MSK_PROC_DEFAULT; 1675 } 1676 } 1677 1678 /* Soft reset. */ 1679 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); 1680 CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR); 1681 sc->msk_pmd = CSR_READ_1(sc, B2_PMD_TYP); 1682 /* Check number of MACs. */ 1683 sc->msk_num_port = 1; 1684 if ((CSR_READ_1(sc, B2_Y2_HW_RES) & CFG_DUAL_MAC_MSK) == 1685 CFG_DUAL_MAC_MSK) { 1686 if (!(CSR_READ_1(sc, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC)) 1687 sc->msk_num_port++; 1688 } 1689 1690 /* Check bus type. */ 1691 if (pci_find_extcap(sc->msk_dev, PCIY_EXPRESS, ®) == 0) 1692 sc->msk_bustype = MSK_PEX_BUS; 1693 else if (pci_find_extcap(sc->msk_dev, PCIY_PCIX, ®) == 0) 1694 sc->msk_bustype = MSK_PCIX_BUS; 1695 else 1696 sc->msk_bustype = MSK_PCI_BUS; 1697 1698 switch (sc->msk_hw_id) { 1699 case CHIP_ID_YUKON_EC: 1700 sc->msk_clock = 125; /* 125 MHz */ 1701 sc->msk_pflags |= MSK_FLAG_JUMBO; 1702 break; 1703 case CHIP_ID_YUKON_EC_U: 1704 sc->msk_clock = 125; /* 125 MHz */ 1705 sc->msk_pflags |= MSK_FLAG_JUMBO | MSK_FLAG_JUMBO_NOCSUM; 1706 break; 1707 case CHIP_ID_YUKON_EX: 1708 sc->msk_clock = 125; /* 125 MHz */ 1709 sc->msk_pflags |= MSK_FLAG_JUMBO | MSK_FLAG_DESCV2 | 1710 MSK_FLAG_AUTOTX_CSUM; 1711 /* 1712 * Yukon Extreme seems to have silicon bug for 1713 * automatic Tx checksum calculation capability. 1714 */ 1715 if (sc->msk_hw_rev == CHIP_REV_YU_EX_B0) 1716 sc->msk_pflags &= ~MSK_FLAG_AUTOTX_CSUM; 1717 /* 1718 * Yukon Extreme A0 could not use store-and-forward 1719 * for jumbo frames, so disable Tx checksum 1720 * offloading for jumbo frames. 1721 */ 1722 if (sc->msk_hw_rev == CHIP_REV_YU_EX_A0) 1723 sc->msk_pflags |= MSK_FLAG_JUMBO_NOCSUM; 1724 break; 1725 case CHIP_ID_YUKON_FE: 1726 sc->msk_clock = 100; /* 100 MHz */ 1727 sc->msk_pflags |= MSK_FLAG_FASTETHER; 1728 break; 1729 case CHIP_ID_YUKON_FE_P: 1730 sc->msk_clock = 50; /* 50 MHz */ 1731 sc->msk_pflags |= MSK_FLAG_FASTETHER | MSK_FLAG_DESCV2 | 1732 MSK_FLAG_AUTOTX_CSUM; 1733 if (sc->msk_hw_rev == CHIP_REV_YU_FE_P_A0) { 1734 /* 1735 * XXX 1736 * FE+ A0 has status LE writeback bug so msk(4) 1737 * does not rely on status word of received frame 1738 * in msk_rxeof() which in turn disables all 1739 * hardware assistance bits reported by the status 1740 * word as well as validity of the recevied frame. 1741 * Just pass received frames to upper stack with 1742 * minimal test and let upper stack handle them. 1743 */ 1744 sc->msk_pflags |= MSK_FLAG_NOHWVLAN | 1745 MSK_FLAG_NORXCHK | MSK_FLAG_NORX_CSUM; 1746 } 1747 break; 1748 case CHIP_ID_YUKON_XL: 1749 sc->msk_clock = 156; /* 156 MHz */ 1750 sc->msk_pflags |= MSK_FLAG_JUMBO; 1751 break; 1752 case CHIP_ID_YUKON_UL_2: 1753 sc->msk_clock = 125; /* 125 MHz */ 1754 sc->msk_pflags |= MSK_FLAG_JUMBO; 1755 break; 1756 default: 1757 sc->msk_clock = 156; /* 156 MHz */ 1758 break; 1759 } 1760 1761 /* Allocate IRQ resources. */ 1762 msic = pci_msi_count(dev); 1763 if (bootverbose) 1764 device_printf(dev, "MSI count : %d\n", msic); 1765 /* 1766 * The Yukon II reports it can handle two messages, one for each 1767 * possible port. We go ahead and allocate two messages and only 1768 * setup a handler for both if we have a dual port card. 1769 * 1770 * XXX: I haven't untangled the interrupt handler to handle dual 1771 * port cards with separate MSI messages, so for now I disable MSI 1772 * on dual port cards. 1773 */ 1774 if (legacy_intr != 0) 1775 msi_disable = 1; 1776 if (msi_disable == 0) { 1777 switch (msic) { 1778 case 2: 1779 case 1: /* 88E8058 reports 1 MSI message */ 1780 msir = msic; 1781 if (sc->msk_num_port == 1 && 1782 pci_alloc_msi(dev, &msir) == 0) { 1783 if (msic == msir) { 1784 sc->msk_pflags |= MSK_FLAG_MSI; 1785 sc->msk_irq_spec = msic == 2 ? 1786 msk_irq_spec_msi2 : 1787 msk_irq_spec_msi; 1788 } else 1789 pci_release_msi(dev); 1790 } 1791 break; 1792 default: 1793 device_printf(dev, 1794 "Unexpected number of MSI messages : %d\n", msic); 1795 break; 1796 } 1797 } 1798 1799 error = bus_alloc_resources(dev, sc->msk_irq_spec, sc->msk_irq); 1800 if (error) { 1801 device_printf(dev, "couldn't allocate IRQ resources\n"); 1802 goto fail; 1803 } 1804 1805 if ((error = msk_status_dma_alloc(sc)) != 0) 1806 goto fail; 1807 1808 /* Set base interrupt mask. */ 1809 sc->msk_intrmask = Y2_IS_HW_ERR | Y2_IS_STAT_BMU; 1810 sc->msk_intrhwemask = Y2_IS_TIST_OV | Y2_IS_MST_ERR | 1811 Y2_IS_IRQ_STAT | Y2_IS_PCI_EXP | Y2_IS_PCI_NEXP; 1812 1813 /* Reset the adapter. */ 1814 mskc_reset(sc); 1815 1816 if ((error = mskc_setup_rambuffer(sc)) != 0) 1817 goto fail; 1818 1819 sc->msk_devs[MSK_PORT_A] = device_add_child(dev, "msk", -1); 1820 if (sc->msk_devs[MSK_PORT_A] == NULL) { 1821 device_printf(dev, "failed to add child for PORT_A\n"); 1822 error = ENXIO; 1823 goto fail; 1824 } 1825 mmd = malloc(sizeof(struct msk_mii_data), M_DEVBUF, M_WAITOK | M_ZERO); 1826 if (mmd == NULL) { 1827 device_printf(dev, "failed to allocate memory for " 1828 "ivars of PORT_A\n"); 1829 error = ENXIO; 1830 goto fail; 1831 } 1832 mmd->port = MSK_PORT_A; 1833 mmd->pmd = sc->msk_pmd; 1834 if (sc->msk_pmd == 'L' || sc->msk_pmd == 'S' || sc->msk_pmd == 'P') 1835 mmd->mii_flags |= MIIF_HAVEFIBER; 1836 device_set_ivars(sc->msk_devs[MSK_PORT_A], mmd); 1837 1838 if (sc->msk_num_port > 1) { 1839 sc->msk_devs[MSK_PORT_B] = device_add_child(dev, "msk", -1); 1840 if (sc->msk_devs[MSK_PORT_B] == NULL) { 1841 device_printf(dev, "failed to add child for PORT_B\n"); 1842 error = ENXIO; 1843 goto fail; 1844 } 1845 mmd = malloc(sizeof(struct msk_mii_data), M_DEVBUF, M_WAITOK | M_ZERO); 1846 if (mmd == NULL) { 1847 device_printf(dev, "failed to allocate memory for " 1848 "ivars of PORT_B\n"); 1849 error = ENXIO; 1850 goto fail; 1851 } 1852 mmd->port = MSK_PORT_B; 1853 mmd->pmd = sc->msk_pmd; 1854 if (sc->msk_pmd == 'L' || sc->msk_pmd == 'S' || sc->msk_pmd == 'P') 1855 mmd->mii_flags |= MIIF_HAVEFIBER; 1856 device_set_ivars(sc->msk_devs[MSK_PORT_B], mmd); 1857 } 1858 1859 error = bus_generic_attach(dev); 1860 if (error) { 1861 device_printf(dev, "failed to attach port(s)\n"); 1862 goto fail; 1863 } 1864 1865 /* Hook interrupt last to avoid having to lock softc. */ 1866 if (legacy_intr) 1867 error = bus_setup_intr(dev, sc->msk_irq[0], INTR_TYPE_NET | 1868 INTR_MPSAFE, NULL, msk_legacy_intr, sc, 1869 &sc->msk_intrhand[0]); 1870 else { 1871 TASK_INIT(&sc->msk_int_task, 0, msk_int_task, sc); 1872 sc->msk_tq = taskqueue_create_fast("msk_taskq", M_WAITOK, 1873 taskqueue_thread_enqueue, &sc->msk_tq); 1874 taskqueue_start_threads(&sc->msk_tq, 1, PI_NET, "%s taskq", 1875 device_get_nameunit(sc->msk_dev)); 1876 error = bus_setup_intr(dev, sc->msk_irq[0], INTR_TYPE_NET | 1877 INTR_MPSAFE, msk_intr, NULL, sc, &sc->msk_intrhand[0]); 1878 } 1879 1880 if (error != 0) { 1881 device_printf(dev, "couldn't set up interrupt handler\n"); 1882 if (legacy_intr == 0) 1883 taskqueue_free(sc->msk_tq); 1884 sc->msk_tq = NULL; 1885 goto fail; 1886 } 1887 fail: 1888 if (error != 0) 1889 mskc_detach(dev); 1890 1891 return (error); 1892 } 1893 1894 /* 1895 * Shutdown hardware and free up resources. This can be called any 1896 * time after the mutex has been initialized. It is called in both 1897 * the error case in attach and the normal detach case so it needs 1898 * to be careful about only freeing resources that have actually been 1899 * allocated. 1900 */ 1901 static int 1902 msk_detach(device_t dev) 1903 { 1904 struct msk_softc *sc; 1905 struct msk_if_softc *sc_if; 1906 struct ifnet *ifp; 1907 1908 sc_if = device_get_softc(dev); 1909 KASSERT(mtx_initialized(&sc_if->msk_softc->msk_mtx), 1910 ("msk mutex not initialized in msk_detach")); 1911 MSK_IF_LOCK(sc_if); 1912 1913 ifp = sc_if->msk_ifp; 1914 if (device_is_attached(dev)) { 1915 /* XXX */ 1916 sc_if->msk_flags |= MSK_FLAG_DETACH; 1917 msk_stop(sc_if); 1918 /* Can't hold locks while calling detach. */ 1919 MSK_IF_UNLOCK(sc_if); 1920 callout_drain(&sc_if->msk_tick_ch); 1921 taskqueue_drain(taskqueue_fast, &sc_if->msk_tx_task); 1922 ether_ifdetach(ifp); 1923 MSK_IF_LOCK(sc_if); 1924 } 1925 1926 /* 1927 * We're generally called from mskc_detach() which is using 1928 * device_delete_child() to get to here. It's already trashed 1929 * miibus for us, so don't do it here or we'll panic. 1930 * 1931 * if (sc_if->msk_miibus != NULL) { 1932 * device_delete_child(dev, sc_if->msk_miibus); 1933 * sc_if->msk_miibus = NULL; 1934 * } 1935 */ 1936 1937 msk_rx_dma_jfree(sc_if); 1938 msk_txrx_dma_free(sc_if); 1939 bus_generic_detach(dev); 1940 1941 if (ifp) 1942 if_free(ifp); 1943 sc = sc_if->msk_softc; 1944 sc->msk_if[sc_if->msk_port] = NULL; 1945 MSK_IF_UNLOCK(sc_if); 1946 1947 return (0); 1948 } 1949 1950 static int 1951 mskc_detach(device_t dev) 1952 { 1953 struct msk_softc *sc; 1954 1955 sc = device_get_softc(dev); 1956 KASSERT(mtx_initialized(&sc->msk_mtx), ("msk mutex not initialized")); 1957 1958 if (device_is_alive(dev)) { 1959 if (sc->msk_devs[MSK_PORT_A] != NULL) { 1960 free(device_get_ivars(sc->msk_devs[MSK_PORT_A]), 1961 M_DEVBUF); 1962 device_delete_child(dev, sc->msk_devs[MSK_PORT_A]); 1963 } 1964 if (sc->msk_devs[MSK_PORT_B] != NULL) { 1965 free(device_get_ivars(sc->msk_devs[MSK_PORT_B]), 1966 M_DEVBUF); 1967 device_delete_child(dev, sc->msk_devs[MSK_PORT_B]); 1968 } 1969 bus_generic_detach(dev); 1970 } 1971 1972 /* Disable all interrupts. */ 1973 CSR_WRITE_4(sc, B0_IMSK, 0); 1974 CSR_READ_4(sc, B0_IMSK); 1975 CSR_WRITE_4(sc, B0_HWE_IMSK, 0); 1976 CSR_READ_4(sc, B0_HWE_IMSK); 1977 1978 /* LED Off. */ 1979 CSR_WRITE_2(sc, B0_CTST, Y2_LED_STAT_OFF); 1980 1981 /* Put hardware reset. */ 1982 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); 1983 1984 msk_status_dma_free(sc); 1985 1986 if (legacy_intr == 0 && sc->msk_tq != NULL) { 1987 taskqueue_drain(sc->msk_tq, &sc->msk_int_task); 1988 taskqueue_free(sc->msk_tq); 1989 sc->msk_tq = NULL; 1990 } 1991 if (sc->msk_intrhand[0]) { 1992 bus_teardown_intr(dev, sc->msk_irq[0], sc->msk_intrhand[0]); 1993 sc->msk_intrhand[0] = NULL; 1994 } 1995 if (sc->msk_intrhand[1]) { 1996 bus_teardown_intr(dev, sc->msk_irq[0], sc->msk_intrhand[0]); 1997 sc->msk_intrhand[1] = NULL; 1998 } 1999 bus_release_resources(dev, sc->msk_irq_spec, sc->msk_irq); 2000 if ((sc->msk_pflags & MSK_FLAG_MSI) != 0) 2001 pci_release_msi(dev); 2002 bus_release_resources(dev, sc->msk_res_spec, sc->msk_res); 2003 mtx_destroy(&sc->msk_mtx); 2004 2005 return (0); 2006 } 2007 2008 struct msk_dmamap_arg { 2009 bus_addr_t msk_busaddr; 2010 }; 2011 2012 static void 2013 msk_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 2014 { 2015 struct msk_dmamap_arg *ctx; 2016 2017 if (error != 0) 2018 return; 2019 ctx = arg; 2020 ctx->msk_busaddr = segs[0].ds_addr; 2021 } 2022 2023 /* Create status DMA region. */ 2024 static int 2025 msk_status_dma_alloc(struct msk_softc *sc) 2026 { 2027 struct msk_dmamap_arg ctx; 2028 int error; 2029 2030 error = bus_dma_tag_create( 2031 bus_get_dma_tag(sc->msk_dev), /* parent */ 2032 MSK_STAT_ALIGN, 0, /* alignment, boundary */ 2033 BUS_SPACE_MAXADDR, /* lowaddr */ 2034 BUS_SPACE_MAXADDR, /* highaddr */ 2035 NULL, NULL, /* filter, filterarg */ 2036 MSK_STAT_RING_SZ, /* maxsize */ 2037 1, /* nsegments */ 2038 MSK_STAT_RING_SZ, /* maxsegsize */ 2039 0, /* flags */ 2040 NULL, NULL, /* lockfunc, lockarg */ 2041 &sc->msk_stat_tag); 2042 if (error != 0) { 2043 device_printf(sc->msk_dev, 2044 "failed to create status DMA tag\n"); 2045 return (error); 2046 } 2047 2048 /* Allocate DMA'able memory and load the DMA map for status ring. */ 2049 error = bus_dmamem_alloc(sc->msk_stat_tag, 2050 (void **)&sc->msk_stat_ring, BUS_DMA_WAITOK | BUS_DMA_COHERENT | 2051 BUS_DMA_ZERO, &sc->msk_stat_map); 2052 if (error != 0) { 2053 device_printf(sc->msk_dev, 2054 "failed to allocate DMA'able memory for status ring\n"); 2055 return (error); 2056 } 2057 2058 ctx.msk_busaddr = 0; 2059 error = bus_dmamap_load(sc->msk_stat_tag, 2060 sc->msk_stat_map, sc->msk_stat_ring, MSK_STAT_RING_SZ, 2061 msk_dmamap_cb, &ctx, 0); 2062 if (error != 0) { 2063 device_printf(sc->msk_dev, 2064 "failed to load DMA'able memory for status ring\n"); 2065 return (error); 2066 } 2067 sc->msk_stat_ring_paddr = ctx.msk_busaddr; 2068 2069 return (0); 2070 } 2071 2072 static void 2073 msk_status_dma_free(struct msk_softc *sc) 2074 { 2075 2076 /* Destroy status block. */ 2077 if (sc->msk_stat_tag) { 2078 if (sc->msk_stat_map) { 2079 bus_dmamap_unload(sc->msk_stat_tag, sc->msk_stat_map); 2080 if (sc->msk_stat_ring) { 2081 bus_dmamem_free(sc->msk_stat_tag, 2082 sc->msk_stat_ring, sc->msk_stat_map); 2083 sc->msk_stat_ring = NULL; 2084 } 2085 sc->msk_stat_map = NULL; 2086 } 2087 bus_dma_tag_destroy(sc->msk_stat_tag); 2088 sc->msk_stat_tag = NULL; 2089 } 2090 } 2091 2092 static int 2093 msk_txrx_dma_alloc(struct msk_if_softc *sc_if) 2094 { 2095 struct msk_dmamap_arg ctx; 2096 struct msk_txdesc *txd; 2097 struct msk_rxdesc *rxd; 2098 bus_size_t rxalign; 2099 int error, i; 2100 2101 /* Create parent DMA tag. */ 2102 /* 2103 * XXX 2104 * It seems that Yukon II supports full 64bits DMA operations. But 2105 * it needs two descriptors(list elements) for 64bits DMA operations. 2106 * Since we don't know what DMA address mappings(32bits or 64bits) 2107 * would be used in advance for each mbufs, we limits its DMA space 2108 * to be in range of 32bits address space. Otherwise, we should check 2109 * what DMA address is used and chain another descriptor for the 2110 * 64bits DMA operation. This also means descriptor ring size is 2111 * variable. Limiting DMA address to be in 32bit address space greatly 2112 * simplyfies descriptor handling and possibly would increase 2113 * performance a bit due to efficient handling of descriptors. 2114 * Apart from harassing checksum offloading mechanisms, it seems 2115 * it's really bad idea to use a seperate descriptor for 64bit 2116 * DMA operation to save small descriptor memory. Anyway, I've 2117 * never seen these exotic scheme on ethernet interface hardware. 2118 */ 2119 error = bus_dma_tag_create( 2120 bus_get_dma_tag(sc_if->msk_if_dev), /* parent */ 2121 1, 0, /* alignment, boundary */ 2122 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 2123 BUS_SPACE_MAXADDR, /* highaddr */ 2124 NULL, NULL, /* filter, filterarg */ 2125 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 2126 0, /* nsegments */ 2127 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 2128 0, /* flags */ 2129 NULL, NULL, /* lockfunc, lockarg */ 2130 &sc_if->msk_cdata.msk_parent_tag); 2131 if (error != 0) { 2132 device_printf(sc_if->msk_if_dev, 2133 "failed to create parent DMA tag\n"); 2134 goto fail; 2135 } 2136 /* Create tag for Tx ring. */ 2137 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2138 MSK_RING_ALIGN, 0, /* alignment, boundary */ 2139 BUS_SPACE_MAXADDR, /* lowaddr */ 2140 BUS_SPACE_MAXADDR, /* highaddr */ 2141 NULL, NULL, /* filter, filterarg */ 2142 MSK_TX_RING_SZ, /* maxsize */ 2143 1, /* nsegments */ 2144 MSK_TX_RING_SZ, /* maxsegsize */ 2145 0, /* flags */ 2146 NULL, NULL, /* lockfunc, lockarg */ 2147 &sc_if->msk_cdata.msk_tx_ring_tag); 2148 if (error != 0) { 2149 device_printf(sc_if->msk_if_dev, 2150 "failed to create Tx ring DMA tag\n"); 2151 goto fail; 2152 } 2153 2154 /* Create tag for Rx ring. */ 2155 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2156 MSK_RING_ALIGN, 0, /* alignment, boundary */ 2157 BUS_SPACE_MAXADDR, /* lowaddr */ 2158 BUS_SPACE_MAXADDR, /* highaddr */ 2159 NULL, NULL, /* filter, filterarg */ 2160 MSK_RX_RING_SZ, /* maxsize */ 2161 1, /* nsegments */ 2162 MSK_RX_RING_SZ, /* maxsegsize */ 2163 0, /* flags */ 2164 NULL, NULL, /* lockfunc, lockarg */ 2165 &sc_if->msk_cdata.msk_rx_ring_tag); 2166 if (error != 0) { 2167 device_printf(sc_if->msk_if_dev, 2168 "failed to create Rx ring DMA tag\n"); 2169 goto fail; 2170 } 2171 2172 /* Create tag for Tx buffers. */ 2173 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2174 1, 0, /* alignment, boundary */ 2175 BUS_SPACE_MAXADDR, /* lowaddr */ 2176 BUS_SPACE_MAXADDR, /* highaddr */ 2177 NULL, NULL, /* filter, filterarg */ 2178 MSK_TSO_MAXSIZE, /* maxsize */ 2179 MSK_MAXTXSEGS, /* nsegments */ 2180 MSK_TSO_MAXSGSIZE, /* maxsegsize */ 2181 0, /* flags */ 2182 NULL, NULL, /* lockfunc, lockarg */ 2183 &sc_if->msk_cdata.msk_tx_tag); 2184 if (error != 0) { 2185 device_printf(sc_if->msk_if_dev, 2186 "failed to create Tx DMA tag\n"); 2187 goto fail; 2188 } 2189 2190 rxalign = 1; 2191 /* 2192 * Workaround hardware hang which seems to happen when Rx buffer 2193 * is not aligned on multiple of FIFO word(8 bytes). 2194 */ 2195 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) != 0) 2196 rxalign = MSK_RX_BUF_ALIGN; 2197 /* Create tag for Rx buffers. */ 2198 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2199 rxalign, 0, /* alignment, boundary */ 2200 BUS_SPACE_MAXADDR, /* lowaddr */ 2201 BUS_SPACE_MAXADDR, /* highaddr */ 2202 NULL, NULL, /* filter, filterarg */ 2203 MCLBYTES, /* maxsize */ 2204 1, /* nsegments */ 2205 MCLBYTES, /* maxsegsize */ 2206 0, /* flags */ 2207 NULL, NULL, /* lockfunc, lockarg */ 2208 &sc_if->msk_cdata.msk_rx_tag); 2209 if (error != 0) { 2210 device_printf(sc_if->msk_if_dev, 2211 "failed to create Rx DMA tag\n"); 2212 goto fail; 2213 } 2214 2215 /* Allocate DMA'able memory and load the DMA map for Tx ring. */ 2216 error = bus_dmamem_alloc(sc_if->msk_cdata.msk_tx_ring_tag, 2217 (void **)&sc_if->msk_rdata.msk_tx_ring, BUS_DMA_WAITOK | 2218 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc_if->msk_cdata.msk_tx_ring_map); 2219 if (error != 0) { 2220 device_printf(sc_if->msk_if_dev, 2221 "failed to allocate DMA'able memory for Tx ring\n"); 2222 goto fail; 2223 } 2224 2225 ctx.msk_busaddr = 0; 2226 error = bus_dmamap_load(sc_if->msk_cdata.msk_tx_ring_tag, 2227 sc_if->msk_cdata.msk_tx_ring_map, sc_if->msk_rdata.msk_tx_ring, 2228 MSK_TX_RING_SZ, msk_dmamap_cb, &ctx, 0); 2229 if (error != 0) { 2230 device_printf(sc_if->msk_if_dev, 2231 "failed to load DMA'able memory for Tx ring\n"); 2232 goto fail; 2233 } 2234 sc_if->msk_rdata.msk_tx_ring_paddr = ctx.msk_busaddr; 2235 2236 /* Allocate DMA'able memory and load the DMA map for Rx ring. */ 2237 error = bus_dmamem_alloc(sc_if->msk_cdata.msk_rx_ring_tag, 2238 (void **)&sc_if->msk_rdata.msk_rx_ring, BUS_DMA_WAITOK | 2239 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc_if->msk_cdata.msk_rx_ring_map); 2240 if (error != 0) { 2241 device_printf(sc_if->msk_if_dev, 2242 "failed to allocate DMA'able memory for Rx ring\n"); 2243 goto fail; 2244 } 2245 2246 ctx.msk_busaddr = 0; 2247 error = bus_dmamap_load(sc_if->msk_cdata.msk_rx_ring_tag, 2248 sc_if->msk_cdata.msk_rx_ring_map, sc_if->msk_rdata.msk_rx_ring, 2249 MSK_RX_RING_SZ, msk_dmamap_cb, &ctx, 0); 2250 if (error != 0) { 2251 device_printf(sc_if->msk_if_dev, 2252 "failed to load DMA'able memory for Rx ring\n"); 2253 goto fail; 2254 } 2255 sc_if->msk_rdata.msk_rx_ring_paddr = ctx.msk_busaddr; 2256 2257 /* Create DMA maps for Tx buffers. */ 2258 for (i = 0; i < MSK_TX_RING_CNT; i++) { 2259 txd = &sc_if->msk_cdata.msk_txdesc[i]; 2260 txd->tx_m = NULL; 2261 txd->tx_dmamap = NULL; 2262 error = bus_dmamap_create(sc_if->msk_cdata.msk_tx_tag, 0, 2263 &txd->tx_dmamap); 2264 if (error != 0) { 2265 device_printf(sc_if->msk_if_dev, 2266 "failed to create Tx dmamap\n"); 2267 goto fail; 2268 } 2269 } 2270 /* Create DMA maps for Rx buffers. */ 2271 if ((error = bus_dmamap_create(sc_if->msk_cdata.msk_rx_tag, 0, 2272 &sc_if->msk_cdata.msk_rx_sparemap)) != 0) { 2273 device_printf(sc_if->msk_if_dev, 2274 "failed to create spare Rx dmamap\n"); 2275 goto fail; 2276 } 2277 for (i = 0; i < MSK_RX_RING_CNT; i++) { 2278 rxd = &sc_if->msk_cdata.msk_rxdesc[i]; 2279 rxd->rx_m = NULL; 2280 rxd->rx_dmamap = NULL; 2281 error = bus_dmamap_create(sc_if->msk_cdata.msk_rx_tag, 0, 2282 &rxd->rx_dmamap); 2283 if (error != 0) { 2284 device_printf(sc_if->msk_if_dev, 2285 "failed to create Rx dmamap\n"); 2286 goto fail; 2287 } 2288 } 2289 2290 fail: 2291 return (error); 2292 } 2293 2294 static int 2295 msk_rx_dma_jalloc(struct msk_if_softc *sc_if) 2296 { 2297 struct msk_dmamap_arg ctx; 2298 struct msk_rxdesc *jrxd; 2299 bus_size_t rxalign; 2300 int error, i; 2301 2302 if (jumbo_disable != 0 || (sc_if->msk_flags & MSK_FLAG_JUMBO) == 0) { 2303 sc_if->msk_flags &= ~MSK_FLAG_JUMBO; 2304 device_printf(sc_if->msk_if_dev, 2305 "disabling jumbo frame support\n"); 2306 return (0); 2307 } 2308 /* Create tag for jumbo Rx ring. */ 2309 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2310 MSK_RING_ALIGN, 0, /* alignment, boundary */ 2311 BUS_SPACE_MAXADDR, /* lowaddr */ 2312 BUS_SPACE_MAXADDR, /* highaddr */ 2313 NULL, NULL, /* filter, filterarg */ 2314 MSK_JUMBO_RX_RING_SZ, /* maxsize */ 2315 1, /* nsegments */ 2316 MSK_JUMBO_RX_RING_SZ, /* maxsegsize */ 2317 0, /* flags */ 2318 NULL, NULL, /* lockfunc, lockarg */ 2319 &sc_if->msk_cdata.msk_jumbo_rx_ring_tag); 2320 if (error != 0) { 2321 device_printf(sc_if->msk_if_dev, 2322 "failed to create jumbo Rx ring DMA tag\n"); 2323 goto jumbo_fail; 2324 } 2325 2326 rxalign = 1; 2327 /* 2328 * Workaround hardware hang which seems to happen when Rx buffer 2329 * is not aligned on multiple of FIFO word(8 bytes). 2330 */ 2331 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) != 0) 2332 rxalign = MSK_RX_BUF_ALIGN; 2333 /* Create tag for jumbo Rx buffers. */ 2334 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2335 rxalign, 0, /* alignment, boundary */ 2336 BUS_SPACE_MAXADDR, /* lowaddr */ 2337 BUS_SPACE_MAXADDR, /* highaddr */ 2338 NULL, NULL, /* filter, filterarg */ 2339 MJUM9BYTES, /* maxsize */ 2340 1, /* nsegments */ 2341 MJUM9BYTES, /* maxsegsize */ 2342 0, /* flags */ 2343 NULL, NULL, /* lockfunc, lockarg */ 2344 &sc_if->msk_cdata.msk_jumbo_rx_tag); 2345 if (error != 0) { 2346 device_printf(sc_if->msk_if_dev, 2347 "failed to create jumbo Rx DMA tag\n"); 2348 goto jumbo_fail; 2349 } 2350 2351 /* Allocate DMA'able memory and load the DMA map for jumbo Rx ring. */ 2352 error = bus_dmamem_alloc(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 2353 (void **)&sc_if->msk_rdata.msk_jumbo_rx_ring, 2354 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 2355 &sc_if->msk_cdata.msk_jumbo_rx_ring_map); 2356 if (error != 0) { 2357 device_printf(sc_if->msk_if_dev, 2358 "failed to allocate DMA'able memory for jumbo Rx ring\n"); 2359 goto jumbo_fail; 2360 } 2361 2362 ctx.msk_busaddr = 0; 2363 error = bus_dmamap_load(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 2364 sc_if->msk_cdata.msk_jumbo_rx_ring_map, 2365 sc_if->msk_rdata.msk_jumbo_rx_ring, MSK_JUMBO_RX_RING_SZ, 2366 msk_dmamap_cb, &ctx, 0); 2367 if (error != 0) { 2368 device_printf(sc_if->msk_if_dev, 2369 "failed to load DMA'able memory for jumbo Rx ring\n"); 2370 goto jumbo_fail; 2371 } 2372 sc_if->msk_rdata.msk_jumbo_rx_ring_paddr = ctx.msk_busaddr; 2373 2374 /* Create DMA maps for jumbo Rx buffers. */ 2375 if ((error = bus_dmamap_create(sc_if->msk_cdata.msk_jumbo_rx_tag, 0, 2376 &sc_if->msk_cdata.msk_jumbo_rx_sparemap)) != 0) { 2377 device_printf(sc_if->msk_if_dev, 2378 "failed to create spare jumbo Rx dmamap\n"); 2379 goto jumbo_fail; 2380 } 2381 for (i = 0; i < MSK_JUMBO_RX_RING_CNT; i++) { 2382 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[i]; 2383 jrxd->rx_m = NULL; 2384 jrxd->rx_dmamap = NULL; 2385 error = bus_dmamap_create(sc_if->msk_cdata.msk_jumbo_rx_tag, 0, 2386 &jrxd->rx_dmamap); 2387 if (error != 0) { 2388 device_printf(sc_if->msk_if_dev, 2389 "failed to create jumbo Rx dmamap\n"); 2390 goto jumbo_fail; 2391 } 2392 } 2393 2394 return (0); 2395 2396 jumbo_fail: 2397 msk_rx_dma_jfree(sc_if); 2398 device_printf(sc_if->msk_if_dev, "disabling jumbo frame support " 2399 "due to resource shortage\n"); 2400 sc_if->msk_flags &= ~MSK_FLAG_JUMBO; 2401 return (error); 2402 } 2403 2404 static void 2405 msk_txrx_dma_free(struct msk_if_softc *sc_if) 2406 { 2407 struct msk_txdesc *txd; 2408 struct msk_rxdesc *rxd; 2409 int i; 2410 2411 /* Tx ring. */ 2412 if (sc_if->msk_cdata.msk_tx_ring_tag) { 2413 if (sc_if->msk_cdata.msk_tx_ring_map) 2414 bus_dmamap_unload(sc_if->msk_cdata.msk_tx_ring_tag, 2415 sc_if->msk_cdata.msk_tx_ring_map); 2416 if (sc_if->msk_cdata.msk_tx_ring_map && 2417 sc_if->msk_rdata.msk_tx_ring) 2418 bus_dmamem_free(sc_if->msk_cdata.msk_tx_ring_tag, 2419 sc_if->msk_rdata.msk_tx_ring, 2420 sc_if->msk_cdata.msk_tx_ring_map); 2421 sc_if->msk_rdata.msk_tx_ring = NULL; 2422 sc_if->msk_cdata.msk_tx_ring_map = NULL; 2423 bus_dma_tag_destroy(sc_if->msk_cdata.msk_tx_ring_tag); 2424 sc_if->msk_cdata.msk_tx_ring_tag = NULL; 2425 } 2426 /* Rx ring. */ 2427 if (sc_if->msk_cdata.msk_rx_ring_tag) { 2428 if (sc_if->msk_cdata.msk_rx_ring_map) 2429 bus_dmamap_unload(sc_if->msk_cdata.msk_rx_ring_tag, 2430 sc_if->msk_cdata.msk_rx_ring_map); 2431 if (sc_if->msk_cdata.msk_rx_ring_map && 2432 sc_if->msk_rdata.msk_rx_ring) 2433 bus_dmamem_free(sc_if->msk_cdata.msk_rx_ring_tag, 2434 sc_if->msk_rdata.msk_rx_ring, 2435 sc_if->msk_cdata.msk_rx_ring_map); 2436 sc_if->msk_rdata.msk_rx_ring = NULL; 2437 sc_if->msk_cdata.msk_rx_ring_map = NULL; 2438 bus_dma_tag_destroy(sc_if->msk_cdata.msk_rx_ring_tag); 2439 sc_if->msk_cdata.msk_rx_ring_tag = NULL; 2440 } 2441 /* Tx buffers. */ 2442 if (sc_if->msk_cdata.msk_tx_tag) { 2443 for (i = 0; i < MSK_TX_RING_CNT; i++) { 2444 txd = &sc_if->msk_cdata.msk_txdesc[i]; 2445 if (txd->tx_dmamap) { 2446 bus_dmamap_destroy(sc_if->msk_cdata.msk_tx_tag, 2447 txd->tx_dmamap); 2448 txd->tx_dmamap = NULL; 2449 } 2450 } 2451 bus_dma_tag_destroy(sc_if->msk_cdata.msk_tx_tag); 2452 sc_if->msk_cdata.msk_tx_tag = NULL; 2453 } 2454 /* Rx buffers. */ 2455 if (sc_if->msk_cdata.msk_rx_tag) { 2456 for (i = 0; i < MSK_RX_RING_CNT; i++) { 2457 rxd = &sc_if->msk_cdata.msk_rxdesc[i]; 2458 if (rxd->rx_dmamap) { 2459 bus_dmamap_destroy(sc_if->msk_cdata.msk_rx_tag, 2460 rxd->rx_dmamap); 2461 rxd->rx_dmamap = NULL; 2462 } 2463 } 2464 if (sc_if->msk_cdata.msk_rx_sparemap) { 2465 bus_dmamap_destroy(sc_if->msk_cdata.msk_rx_tag, 2466 sc_if->msk_cdata.msk_rx_sparemap); 2467 sc_if->msk_cdata.msk_rx_sparemap = 0; 2468 } 2469 bus_dma_tag_destroy(sc_if->msk_cdata.msk_rx_tag); 2470 sc_if->msk_cdata.msk_rx_tag = NULL; 2471 } 2472 if (sc_if->msk_cdata.msk_parent_tag) { 2473 bus_dma_tag_destroy(sc_if->msk_cdata.msk_parent_tag); 2474 sc_if->msk_cdata.msk_parent_tag = NULL; 2475 } 2476 } 2477 2478 static void 2479 msk_rx_dma_jfree(struct msk_if_softc *sc_if) 2480 { 2481 struct msk_rxdesc *jrxd; 2482 int i; 2483 2484 /* Jumbo Rx ring. */ 2485 if (sc_if->msk_cdata.msk_jumbo_rx_ring_tag) { 2486 if (sc_if->msk_cdata.msk_jumbo_rx_ring_map) 2487 bus_dmamap_unload(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 2488 sc_if->msk_cdata.msk_jumbo_rx_ring_map); 2489 if (sc_if->msk_cdata.msk_jumbo_rx_ring_map && 2490 sc_if->msk_rdata.msk_jumbo_rx_ring) 2491 bus_dmamem_free(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 2492 sc_if->msk_rdata.msk_jumbo_rx_ring, 2493 sc_if->msk_cdata.msk_jumbo_rx_ring_map); 2494 sc_if->msk_rdata.msk_jumbo_rx_ring = NULL; 2495 sc_if->msk_cdata.msk_jumbo_rx_ring_map = NULL; 2496 bus_dma_tag_destroy(sc_if->msk_cdata.msk_jumbo_rx_ring_tag); 2497 sc_if->msk_cdata.msk_jumbo_rx_ring_tag = NULL; 2498 } 2499 /* Jumbo Rx buffers. */ 2500 if (sc_if->msk_cdata.msk_jumbo_rx_tag) { 2501 for (i = 0; i < MSK_JUMBO_RX_RING_CNT; i++) { 2502 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[i]; 2503 if (jrxd->rx_dmamap) { 2504 bus_dmamap_destroy( 2505 sc_if->msk_cdata.msk_jumbo_rx_tag, 2506 jrxd->rx_dmamap); 2507 jrxd->rx_dmamap = NULL; 2508 } 2509 } 2510 if (sc_if->msk_cdata.msk_jumbo_rx_sparemap) { 2511 bus_dmamap_destroy(sc_if->msk_cdata.msk_jumbo_rx_tag, 2512 sc_if->msk_cdata.msk_jumbo_rx_sparemap); 2513 sc_if->msk_cdata.msk_jumbo_rx_sparemap = 0; 2514 } 2515 bus_dma_tag_destroy(sc_if->msk_cdata.msk_jumbo_rx_tag); 2516 sc_if->msk_cdata.msk_jumbo_rx_tag = NULL; 2517 } 2518 } 2519 2520 static int 2521 msk_encap(struct msk_if_softc *sc_if, struct mbuf **m_head) 2522 { 2523 struct msk_txdesc *txd, *txd_last; 2524 struct msk_tx_desc *tx_le; 2525 struct mbuf *m; 2526 bus_dmamap_t map; 2527 bus_dma_segment_t txsegs[MSK_MAXTXSEGS]; 2528 uint32_t control, prod, si; 2529 uint16_t offset, tcp_offset, tso_mtu; 2530 int error, i, nseg, tso; 2531 2532 MSK_IF_LOCK_ASSERT(sc_if); 2533 2534 tcp_offset = offset = 0; 2535 m = *m_head; 2536 if (((sc_if->msk_flags & MSK_FLAG_AUTOTX_CSUM) == 0 && 2537 (m->m_pkthdr.csum_flags & MSK_CSUM_FEATURES) != 0) || 2538 ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0 && 2539 (m->m_pkthdr.csum_flags & CSUM_TSO) != 0)) { 2540 /* 2541 * Since mbuf has no protocol specific structure information 2542 * in it we have to inspect protocol information here to 2543 * setup TSO and checksum offload. I don't know why Marvell 2544 * made a such decision in chip design because other GigE 2545 * hardwares normally takes care of all these chores in 2546 * hardware. However, TSO performance of Yukon II is very 2547 * good such that it's worth to implement it. 2548 */ 2549 struct ether_header *eh; 2550 struct ip *ip; 2551 struct tcphdr *tcp; 2552 2553 if (M_WRITABLE(m) == 0) { 2554 /* Get a writable copy. */ 2555 m = m_dup(*m_head, M_DONTWAIT); 2556 m_freem(*m_head); 2557 if (m == NULL) { 2558 *m_head = NULL; 2559 return (ENOBUFS); 2560 } 2561 *m_head = m; 2562 } 2563 2564 offset = sizeof(struct ether_header); 2565 m = m_pullup(m, offset); 2566 if (m == NULL) { 2567 *m_head = NULL; 2568 return (ENOBUFS); 2569 } 2570 eh = mtod(m, struct ether_header *); 2571 /* Check if hardware VLAN insertion is off. */ 2572 if (eh->ether_type == htons(ETHERTYPE_VLAN)) { 2573 offset = sizeof(struct ether_vlan_header); 2574 m = m_pullup(m, offset); 2575 if (m == NULL) { 2576 *m_head = NULL; 2577 return (ENOBUFS); 2578 } 2579 } 2580 m = m_pullup(m, offset + sizeof(struct ip)); 2581 if (m == NULL) { 2582 *m_head = NULL; 2583 return (ENOBUFS); 2584 } 2585 ip = (struct ip *)(mtod(m, char *) + offset); 2586 offset += (ip->ip_hl << 2); 2587 tcp_offset = offset; 2588 /* 2589 * It seems that Yukon II has Tx checksum offload bug for 2590 * small TCP packets that's less than 60 bytes in size 2591 * (e.g. TCP window probe packet, pure ACK packet). 2592 * Common work around like padding with zeros to make the 2593 * frame minimum ethernet frame size didn't work at all. 2594 * Instead of disabling checksum offload completely we 2595 * resort to S/W checksum routine when we encounter short 2596 * TCP frames. 2597 * Short UDP packets appear to be handled correctly by 2598 * Yukon II. Also I assume this bug does not happen on 2599 * controllers that use newer descriptor format or 2600 * automatic Tx checksum calaulcation. 2601 */ 2602 if ((sc_if->msk_flags & MSK_FLAG_AUTOTX_CSUM) == 0 && 2603 (m->m_pkthdr.len < MSK_MIN_FRAMELEN) && 2604 (m->m_pkthdr.csum_flags & CSUM_TCP) != 0) { 2605 m = m_pullup(m, offset + sizeof(struct tcphdr)); 2606 if (m == NULL) { 2607 *m_head = NULL; 2608 return (ENOBUFS); 2609 } 2610 *(uint16_t *)(m->m_data + offset + 2611 m->m_pkthdr.csum_data) = in_cksum_skip(m, 2612 m->m_pkthdr.len, offset); 2613 m->m_pkthdr.csum_flags &= ~CSUM_TCP; 2614 } 2615 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 2616 m = m_pullup(m, offset + sizeof(struct tcphdr)); 2617 if (m == NULL) { 2618 *m_head = NULL; 2619 return (ENOBUFS); 2620 } 2621 tcp = (struct tcphdr *)(mtod(m, char *) + offset); 2622 offset += (tcp->th_off << 2); 2623 } 2624 *m_head = m; 2625 } 2626 2627 prod = sc_if->msk_cdata.msk_tx_prod; 2628 txd = &sc_if->msk_cdata.msk_txdesc[prod]; 2629 txd_last = txd; 2630 map = txd->tx_dmamap; 2631 error = bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_tx_tag, map, 2632 *m_head, txsegs, &nseg, BUS_DMA_NOWAIT); 2633 if (error == EFBIG) { 2634 m = m_collapse(*m_head, M_DONTWAIT, MSK_MAXTXSEGS); 2635 if (m == NULL) { 2636 m_freem(*m_head); 2637 *m_head = NULL; 2638 return (ENOBUFS); 2639 } 2640 *m_head = m; 2641 error = bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_tx_tag, 2642 map, *m_head, txsegs, &nseg, BUS_DMA_NOWAIT); 2643 if (error != 0) { 2644 m_freem(*m_head); 2645 *m_head = NULL; 2646 return (error); 2647 } 2648 } else if (error != 0) 2649 return (error); 2650 if (nseg == 0) { 2651 m_freem(*m_head); 2652 *m_head = NULL; 2653 return (EIO); 2654 } 2655 2656 /* Check number of available descriptors. */ 2657 if (sc_if->msk_cdata.msk_tx_cnt + nseg >= 2658 (MSK_TX_RING_CNT - MSK_RESERVED_TX_DESC_CNT)) { 2659 bus_dmamap_unload(sc_if->msk_cdata.msk_tx_tag, map); 2660 return (ENOBUFS); 2661 } 2662 2663 control = 0; 2664 tso = 0; 2665 tx_le = NULL; 2666 2667 /* Check TSO support. */ 2668 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 2669 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) != 0) 2670 tso_mtu = m->m_pkthdr.tso_segsz; 2671 else 2672 tso_mtu = offset + m->m_pkthdr.tso_segsz; 2673 if (tso_mtu != sc_if->msk_cdata.msk_tso_mtu) { 2674 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2675 tx_le->msk_addr = htole32(tso_mtu); 2676 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) != 0) 2677 tx_le->msk_control = htole32(OP_MSS | HW_OWNER); 2678 else 2679 tx_le->msk_control = 2680 htole32(OP_LRGLEN | HW_OWNER); 2681 sc_if->msk_cdata.msk_tx_cnt++; 2682 MSK_INC(prod, MSK_TX_RING_CNT); 2683 sc_if->msk_cdata.msk_tso_mtu = tso_mtu; 2684 } 2685 tso++; 2686 } 2687 /* Check if we have a VLAN tag to insert. */ 2688 if ((m->m_flags & M_VLANTAG) != 0) { 2689 if (tso == 0) { 2690 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2691 tx_le->msk_addr = htole32(0); 2692 tx_le->msk_control = htole32(OP_VLAN | HW_OWNER | 2693 htons(m->m_pkthdr.ether_vtag)); 2694 sc_if->msk_cdata.msk_tx_cnt++; 2695 MSK_INC(prod, MSK_TX_RING_CNT); 2696 } else { 2697 tx_le->msk_control |= htole32(OP_VLAN | 2698 htons(m->m_pkthdr.ether_vtag)); 2699 } 2700 control |= INS_VLAN; 2701 } 2702 /* Check if we have to handle checksum offload. */ 2703 if (tso == 0 && (m->m_pkthdr.csum_flags & MSK_CSUM_FEATURES) != 0) { 2704 if ((sc_if->msk_flags & MSK_FLAG_AUTOTX_CSUM) != 0) 2705 control |= CALSUM; 2706 else { 2707 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2708 tx_le->msk_addr = htole32(((tcp_offset + 2709 m->m_pkthdr.csum_data) & 0xffff) | 2710 ((uint32_t)tcp_offset << 16)); 2711 tx_le->msk_control = htole32(1 << 16 | 2712 (OP_TCPLISW | HW_OWNER)); 2713 control = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM; 2714 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0) 2715 control |= UDPTCP; 2716 sc_if->msk_cdata.msk_tx_cnt++; 2717 MSK_INC(prod, MSK_TX_RING_CNT); 2718 } 2719 } 2720 2721 si = prod; 2722 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2723 tx_le->msk_addr = htole32(MSK_ADDR_LO(txsegs[0].ds_addr)); 2724 if (tso == 0) 2725 tx_le->msk_control = htole32(txsegs[0].ds_len | control | 2726 OP_PACKET); 2727 else 2728 tx_le->msk_control = htole32(txsegs[0].ds_len | control | 2729 OP_LARGESEND); 2730 sc_if->msk_cdata.msk_tx_cnt++; 2731 MSK_INC(prod, MSK_TX_RING_CNT); 2732 2733 for (i = 1; i < nseg; i++) { 2734 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2735 tx_le->msk_addr = htole32(MSK_ADDR_LO(txsegs[i].ds_addr)); 2736 tx_le->msk_control = htole32(txsegs[i].ds_len | control | 2737 OP_BUFFER | HW_OWNER); 2738 sc_if->msk_cdata.msk_tx_cnt++; 2739 MSK_INC(prod, MSK_TX_RING_CNT); 2740 } 2741 /* Update producer index. */ 2742 sc_if->msk_cdata.msk_tx_prod = prod; 2743 2744 /* Set EOP on the last desciptor. */ 2745 prod = (prod + MSK_TX_RING_CNT - 1) % MSK_TX_RING_CNT; 2746 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2747 tx_le->msk_control |= htole32(EOP); 2748 2749 /* Turn the first descriptor ownership to hardware. */ 2750 tx_le = &sc_if->msk_rdata.msk_tx_ring[si]; 2751 tx_le->msk_control |= htole32(HW_OWNER); 2752 2753 txd = &sc_if->msk_cdata.msk_txdesc[prod]; 2754 map = txd_last->tx_dmamap; 2755 txd_last->tx_dmamap = txd->tx_dmamap; 2756 txd->tx_dmamap = map; 2757 txd->tx_m = m; 2758 2759 /* Sync descriptors. */ 2760 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_tag, map, BUS_DMASYNC_PREWRITE); 2761 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_ring_tag, 2762 sc_if->msk_cdata.msk_tx_ring_map, 2763 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2764 2765 return (0); 2766 } 2767 2768 static void 2769 msk_tx_task(void *arg, int pending) 2770 { 2771 struct ifnet *ifp; 2772 2773 ifp = arg; 2774 msk_start(ifp); 2775 } 2776 2777 static void 2778 msk_start(struct ifnet *ifp) 2779 { 2780 struct msk_if_softc *sc_if; 2781 struct mbuf *m_head; 2782 int enq; 2783 2784 sc_if = ifp->if_softc; 2785 2786 MSK_IF_LOCK(sc_if); 2787 2788 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2789 IFF_DRV_RUNNING || (sc_if->msk_flags & MSK_FLAG_LINK) == 0) { 2790 MSK_IF_UNLOCK(sc_if); 2791 return; 2792 } 2793 2794 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 2795 sc_if->msk_cdata.msk_tx_cnt < 2796 (MSK_TX_RING_CNT - MSK_RESERVED_TX_DESC_CNT); ) { 2797 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2798 if (m_head == NULL) 2799 break; 2800 /* 2801 * Pack the data into the transmit ring. If we 2802 * don't have room, set the OACTIVE flag and wait 2803 * for the NIC to drain the ring. 2804 */ 2805 if (msk_encap(sc_if, &m_head) != 0) { 2806 if (m_head == NULL) 2807 break; 2808 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2809 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2810 break; 2811 } 2812 2813 enq++; 2814 /* 2815 * If there's a BPF listener, bounce a copy of this frame 2816 * to him. 2817 */ 2818 ETHER_BPF_MTAP(ifp, m_head); 2819 } 2820 2821 if (enq > 0) { 2822 /* Transmit */ 2823 CSR_WRITE_2(sc_if->msk_softc, 2824 Y2_PREF_Q_ADDR(sc_if->msk_txq, PREF_UNIT_PUT_IDX_REG), 2825 sc_if->msk_cdata.msk_tx_prod); 2826 2827 /* Set a timeout in case the chip goes out to lunch. */ 2828 sc_if->msk_watchdog_timer = MSK_TX_TIMEOUT; 2829 } 2830 2831 MSK_IF_UNLOCK(sc_if); 2832 } 2833 2834 static void 2835 msk_watchdog(struct msk_if_softc *sc_if) 2836 { 2837 struct ifnet *ifp; 2838 uint32_t ridx; 2839 int idx; 2840 2841 MSK_IF_LOCK_ASSERT(sc_if); 2842 2843 if (sc_if->msk_watchdog_timer == 0 || --sc_if->msk_watchdog_timer) 2844 return; 2845 ifp = sc_if->msk_ifp; 2846 if ((sc_if->msk_flags & MSK_FLAG_LINK) == 0) { 2847 if (bootverbose) 2848 if_printf(sc_if->msk_ifp, "watchdog timeout " 2849 "(missed link)\n"); 2850 ifp->if_oerrors++; 2851 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2852 msk_init_locked(sc_if); 2853 return; 2854 } 2855 2856 /* 2857 * Reclaim first as there is a possibility of losing Tx completion 2858 * interrupts. 2859 */ 2860 ridx = sc_if->msk_port == MSK_PORT_A ? STAT_TXA1_RIDX : STAT_TXA2_RIDX; 2861 idx = CSR_READ_2(sc_if->msk_softc, ridx); 2862 if (sc_if->msk_cdata.msk_tx_cons != idx) { 2863 msk_txeof(sc_if, idx); 2864 if (sc_if->msk_cdata.msk_tx_cnt == 0) { 2865 if_printf(ifp, "watchdog timeout (missed Tx interrupts) " 2866 "-- recovering\n"); 2867 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2868 taskqueue_enqueue(taskqueue_fast, 2869 &sc_if->msk_tx_task); 2870 return; 2871 } 2872 } 2873 2874 if_printf(ifp, "watchdog timeout\n"); 2875 ifp->if_oerrors++; 2876 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2877 msk_init_locked(sc_if); 2878 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2879 taskqueue_enqueue(taskqueue_fast, &sc_if->msk_tx_task); 2880 } 2881 2882 static int 2883 mskc_shutdown(device_t dev) 2884 { 2885 struct msk_softc *sc; 2886 int i; 2887 2888 sc = device_get_softc(dev); 2889 MSK_LOCK(sc); 2890 for (i = 0; i < sc->msk_num_port; i++) { 2891 if (sc->msk_if[i] != NULL) 2892 msk_stop(sc->msk_if[i]); 2893 } 2894 2895 /* Disable all interrupts. */ 2896 CSR_WRITE_4(sc, B0_IMSK, 0); 2897 CSR_READ_4(sc, B0_IMSK); 2898 CSR_WRITE_4(sc, B0_HWE_IMSK, 0); 2899 CSR_READ_4(sc, B0_HWE_IMSK); 2900 2901 /* Put hardware reset. */ 2902 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); 2903 2904 MSK_UNLOCK(sc); 2905 return (0); 2906 } 2907 2908 static int 2909 mskc_suspend(device_t dev) 2910 { 2911 struct msk_softc *sc; 2912 int i; 2913 2914 sc = device_get_softc(dev); 2915 2916 MSK_LOCK(sc); 2917 2918 for (i = 0; i < sc->msk_num_port; i++) { 2919 if (sc->msk_if[i] != NULL && sc->msk_if[i]->msk_ifp != NULL && 2920 ((sc->msk_if[i]->msk_ifp->if_drv_flags & 2921 IFF_DRV_RUNNING) != 0)) 2922 msk_stop(sc->msk_if[i]); 2923 } 2924 2925 /* Disable all interrupts. */ 2926 CSR_WRITE_4(sc, B0_IMSK, 0); 2927 CSR_READ_4(sc, B0_IMSK); 2928 CSR_WRITE_4(sc, B0_HWE_IMSK, 0); 2929 CSR_READ_4(sc, B0_HWE_IMSK); 2930 2931 msk_phy_power(sc, MSK_PHY_POWERDOWN); 2932 2933 /* Put hardware reset. */ 2934 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); 2935 sc->msk_pflags |= MSK_FLAG_SUSPEND; 2936 2937 MSK_UNLOCK(sc); 2938 2939 return (0); 2940 } 2941 2942 static int 2943 mskc_resume(device_t dev) 2944 { 2945 struct msk_softc *sc; 2946 int i; 2947 2948 sc = device_get_softc(dev); 2949 2950 MSK_LOCK(sc); 2951 2952 mskc_reset(sc); 2953 for (i = 0; i < sc->msk_num_port; i++) { 2954 if (sc->msk_if[i] != NULL && sc->msk_if[i]->msk_ifp != NULL && 2955 ((sc->msk_if[i]->msk_ifp->if_flags & IFF_UP) != 0)) { 2956 sc->msk_if[i]->msk_ifp->if_drv_flags &= 2957 ~IFF_DRV_RUNNING; 2958 msk_init_locked(sc->msk_if[i]); 2959 } 2960 } 2961 sc->msk_pflags &= ~MSK_FLAG_SUSPEND; 2962 2963 MSK_UNLOCK(sc); 2964 2965 return (0); 2966 } 2967 2968 #ifndef __NO_STRICT_ALIGNMENT 2969 static __inline void 2970 msk_fixup_rx(struct mbuf *m) 2971 { 2972 int i; 2973 uint16_t *src, *dst; 2974 2975 src = mtod(m, uint16_t *); 2976 dst = src - 3; 2977 2978 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 2979 *dst++ = *src++; 2980 2981 m->m_data -= (MSK_RX_BUF_ALIGN - ETHER_ALIGN); 2982 } 2983 #endif 2984 2985 static void 2986 msk_rxeof(struct msk_if_softc *sc_if, uint32_t status, uint32_t control, 2987 int len) 2988 { 2989 struct mbuf *m; 2990 struct ifnet *ifp; 2991 struct msk_rxdesc *rxd; 2992 int cons, rxlen; 2993 2994 ifp = sc_if->msk_ifp; 2995 2996 MSK_IF_LOCK_ASSERT(sc_if); 2997 2998 cons = sc_if->msk_cdata.msk_rx_cons; 2999 do { 3000 rxlen = status >> 16; 3001 if ((status & GMR_FS_VLAN) != 0 && 3002 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 3003 rxlen -= ETHER_VLAN_ENCAP_LEN; 3004 if ((sc_if->msk_flags & MSK_FLAG_NORXCHK) != 0) { 3005 /* 3006 * For controllers that returns bogus status code 3007 * just do minimal check and let upper stack 3008 * handle this frame. 3009 */ 3010 if (len > MSK_MAX_FRAMELEN || len < ETHER_HDR_LEN) { 3011 ifp->if_ierrors++; 3012 msk_discard_rxbuf(sc_if, cons); 3013 break; 3014 } 3015 } else if (len > sc_if->msk_framesize || 3016 ((status & GMR_FS_ANY_ERR) != 0) || 3017 ((status & GMR_FS_RX_OK) == 0) || (rxlen != len)) { 3018 /* Don't count flow-control packet as errors. */ 3019 if ((status & GMR_FS_GOOD_FC) == 0) 3020 ifp->if_ierrors++; 3021 msk_discard_rxbuf(sc_if, cons); 3022 break; 3023 } 3024 rxd = &sc_if->msk_cdata.msk_rxdesc[cons]; 3025 m = rxd->rx_m; 3026 if (msk_newbuf(sc_if, cons) != 0) { 3027 ifp->if_iqdrops++; 3028 /* Reuse old buffer. */ 3029 msk_discard_rxbuf(sc_if, cons); 3030 break; 3031 } 3032 m->m_pkthdr.rcvif = ifp; 3033 m->m_pkthdr.len = m->m_len = len; 3034 #ifndef __NO_STRICT_ALIGNMENT 3035 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) != 0) 3036 msk_fixup_rx(m); 3037 #endif 3038 ifp->if_ipackets++; 3039 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0 && 3040 (control & (CSS_IPV4 | CSS_IPFRAG)) == CSS_IPV4) { 3041 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 3042 if ((control & CSS_IPV4_CSUM_OK) != 0) 3043 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 3044 if ((control & (CSS_TCP | CSS_UDP)) != 0 && 3045 (control & (CSS_TCPUDP_CSUM_OK)) != 0) { 3046 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID | 3047 CSUM_PSEUDO_HDR; 3048 m->m_pkthdr.csum_data = 0xffff; 3049 } 3050 } 3051 /* Check for VLAN tagged packets. */ 3052 if ((status & GMR_FS_VLAN) != 0 && 3053 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) { 3054 m->m_pkthdr.ether_vtag = sc_if->msk_vtag; 3055 m->m_flags |= M_VLANTAG; 3056 } 3057 MSK_IF_UNLOCK(sc_if); 3058 (*ifp->if_input)(ifp, m); 3059 MSK_IF_LOCK(sc_if); 3060 } while (0); 3061 3062 MSK_INC(sc_if->msk_cdata.msk_rx_cons, MSK_RX_RING_CNT); 3063 MSK_INC(sc_if->msk_cdata.msk_rx_prod, MSK_RX_RING_CNT); 3064 } 3065 3066 static void 3067 msk_jumbo_rxeof(struct msk_if_softc *sc_if, uint32_t status, uint32_t control, 3068 int len) 3069 { 3070 struct mbuf *m; 3071 struct ifnet *ifp; 3072 struct msk_rxdesc *jrxd; 3073 int cons, rxlen; 3074 3075 ifp = sc_if->msk_ifp; 3076 3077 MSK_IF_LOCK_ASSERT(sc_if); 3078 3079 cons = sc_if->msk_cdata.msk_rx_cons; 3080 do { 3081 rxlen = status >> 16; 3082 if ((status & GMR_FS_VLAN) != 0 && 3083 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 3084 rxlen -= ETHER_VLAN_ENCAP_LEN; 3085 if (len > sc_if->msk_framesize || 3086 ((status & GMR_FS_ANY_ERR) != 0) || 3087 ((status & GMR_FS_RX_OK) == 0) || (rxlen != len)) { 3088 /* Don't count flow-control packet as errors. */ 3089 if ((status & GMR_FS_GOOD_FC) == 0) 3090 ifp->if_ierrors++; 3091 msk_discard_jumbo_rxbuf(sc_if, cons); 3092 break; 3093 } 3094 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[cons]; 3095 m = jrxd->rx_m; 3096 if (msk_jumbo_newbuf(sc_if, cons) != 0) { 3097 ifp->if_iqdrops++; 3098 /* Reuse old buffer. */ 3099 msk_discard_jumbo_rxbuf(sc_if, cons); 3100 break; 3101 } 3102 m->m_pkthdr.rcvif = ifp; 3103 m->m_pkthdr.len = m->m_len = len; 3104 #ifndef __NO_STRICT_ALIGNMENT 3105 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) != 0) 3106 msk_fixup_rx(m); 3107 #endif 3108 ifp->if_ipackets++; 3109 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0 && 3110 (control & (CSS_IPV4 | CSS_IPFRAG)) == CSS_IPV4) { 3111 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 3112 if ((control & CSS_IPV4_CSUM_OK) != 0) 3113 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 3114 if ((control & (CSS_TCP | CSS_UDP)) != 0 && 3115 (control & (CSS_TCPUDP_CSUM_OK)) != 0) { 3116 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID | 3117 CSUM_PSEUDO_HDR; 3118 m->m_pkthdr.csum_data = 0xffff; 3119 } 3120 } 3121 /* Check for VLAN tagged packets. */ 3122 if ((status & GMR_FS_VLAN) != 0 && 3123 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) { 3124 m->m_pkthdr.ether_vtag = sc_if->msk_vtag; 3125 m->m_flags |= M_VLANTAG; 3126 } 3127 MSK_IF_UNLOCK(sc_if); 3128 (*ifp->if_input)(ifp, m); 3129 MSK_IF_LOCK(sc_if); 3130 } while (0); 3131 3132 MSK_INC(sc_if->msk_cdata.msk_rx_cons, MSK_JUMBO_RX_RING_CNT); 3133 MSK_INC(sc_if->msk_cdata.msk_rx_prod, MSK_JUMBO_RX_RING_CNT); 3134 } 3135 3136 static void 3137 msk_txeof(struct msk_if_softc *sc_if, int idx) 3138 { 3139 struct msk_txdesc *txd; 3140 struct msk_tx_desc *cur_tx; 3141 struct ifnet *ifp; 3142 uint32_t control; 3143 int cons, prog; 3144 3145 MSK_IF_LOCK_ASSERT(sc_if); 3146 3147 ifp = sc_if->msk_ifp; 3148 3149 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_ring_tag, 3150 sc_if->msk_cdata.msk_tx_ring_map, 3151 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3152 /* 3153 * Go through our tx ring and free mbufs for those 3154 * frames that have been sent. 3155 */ 3156 cons = sc_if->msk_cdata.msk_tx_cons; 3157 prog = 0; 3158 for (; cons != idx; MSK_INC(cons, MSK_TX_RING_CNT)) { 3159 if (sc_if->msk_cdata.msk_tx_cnt <= 0) 3160 break; 3161 prog++; 3162 cur_tx = &sc_if->msk_rdata.msk_tx_ring[cons]; 3163 control = le32toh(cur_tx->msk_control); 3164 sc_if->msk_cdata.msk_tx_cnt--; 3165 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3166 if ((control & EOP) == 0) 3167 continue; 3168 txd = &sc_if->msk_cdata.msk_txdesc[cons]; 3169 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_tag, txd->tx_dmamap, 3170 BUS_DMASYNC_POSTWRITE); 3171 bus_dmamap_unload(sc_if->msk_cdata.msk_tx_tag, txd->tx_dmamap); 3172 3173 ifp->if_opackets++; 3174 KASSERT(txd->tx_m != NULL, ("%s: freeing NULL mbuf!", 3175 __func__)); 3176 m_freem(txd->tx_m); 3177 txd->tx_m = NULL; 3178 } 3179 3180 if (prog > 0) { 3181 sc_if->msk_cdata.msk_tx_cons = cons; 3182 if (sc_if->msk_cdata.msk_tx_cnt == 0) 3183 sc_if->msk_watchdog_timer = 0; 3184 /* No need to sync LEs as we didn't update LEs. */ 3185 } 3186 } 3187 3188 static void 3189 msk_tick(void *xsc_if) 3190 { 3191 struct msk_if_softc *sc_if; 3192 struct mii_data *mii; 3193 3194 sc_if = xsc_if; 3195 3196 MSK_IF_LOCK_ASSERT(sc_if); 3197 3198 mii = device_get_softc(sc_if->msk_miibus); 3199 3200 mii_tick(mii); 3201 if ((sc_if->msk_flags & MSK_FLAG_LINK) == 0) 3202 msk_miibus_statchg(sc_if->msk_if_dev); 3203 msk_watchdog(sc_if); 3204 callout_reset(&sc_if->msk_tick_ch, hz, msk_tick, sc_if); 3205 } 3206 3207 static void 3208 msk_intr_phy(struct msk_if_softc *sc_if) 3209 { 3210 uint16_t status; 3211 3212 msk_phy_readreg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_STAT); 3213 status = msk_phy_readreg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_STAT); 3214 /* Handle FIFO Underrun/Overflow? */ 3215 if ((status & PHY_M_IS_FIFO_ERROR)) 3216 device_printf(sc_if->msk_if_dev, 3217 "PHY FIFO underrun/overflow.\n"); 3218 } 3219 3220 static void 3221 msk_intr_gmac(struct msk_if_softc *sc_if) 3222 { 3223 struct msk_softc *sc; 3224 uint8_t status; 3225 3226 sc = sc_if->msk_softc; 3227 status = CSR_READ_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_SRC)); 3228 3229 /* GMAC Rx FIFO overrun. */ 3230 if ((status & GM_IS_RX_FF_OR) != 0) 3231 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), 3232 GMF_CLI_RX_FO); 3233 /* GMAC Tx FIFO underrun. */ 3234 if ((status & GM_IS_TX_FF_UR) != 0) { 3235 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 3236 GMF_CLI_TX_FU); 3237 device_printf(sc_if->msk_if_dev, "Tx FIFO underrun!\n"); 3238 /* 3239 * XXX 3240 * In case of Tx underrun, we may need to flush/reset 3241 * Tx MAC but that would also require resynchronization 3242 * with status LEs. Reintializing status LEs would 3243 * affect other port in dual MAC configuration so it 3244 * should be avoided as possible as we can. 3245 * Due to lack of documentation it's all vague guess but 3246 * it needs more investigation. 3247 */ 3248 } 3249 } 3250 3251 static void 3252 msk_handle_hwerr(struct msk_if_softc *sc_if, uint32_t status) 3253 { 3254 struct msk_softc *sc; 3255 3256 sc = sc_if->msk_softc; 3257 if ((status & Y2_IS_PAR_RD1) != 0) { 3258 device_printf(sc_if->msk_if_dev, 3259 "RAM buffer read parity error\n"); 3260 /* Clear IRQ. */ 3261 CSR_WRITE_2(sc, SELECT_RAM_BUFFER(sc_if->msk_port, B3_RI_CTRL), 3262 RI_CLR_RD_PERR); 3263 } 3264 if ((status & Y2_IS_PAR_WR1) != 0) { 3265 device_printf(sc_if->msk_if_dev, 3266 "RAM buffer write parity error\n"); 3267 /* Clear IRQ. */ 3268 CSR_WRITE_2(sc, SELECT_RAM_BUFFER(sc_if->msk_port, B3_RI_CTRL), 3269 RI_CLR_WR_PERR); 3270 } 3271 if ((status & Y2_IS_PAR_MAC1) != 0) { 3272 device_printf(sc_if->msk_if_dev, "Tx MAC parity error\n"); 3273 /* Clear IRQ. */ 3274 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 3275 GMF_CLI_TX_PE); 3276 } 3277 if ((status & Y2_IS_PAR_RX1) != 0) { 3278 device_printf(sc_if->msk_if_dev, "Rx parity error\n"); 3279 /* Clear IRQ. */ 3280 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_CLR_IRQ_PAR); 3281 } 3282 if ((status & (Y2_IS_TCP_TXS1 | Y2_IS_TCP_TXA1)) != 0) { 3283 device_printf(sc_if->msk_if_dev, "TCP segmentation error\n"); 3284 /* Clear IRQ. */ 3285 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_CLR_IRQ_TCP); 3286 } 3287 } 3288 3289 static void 3290 msk_intr_hwerr(struct msk_softc *sc) 3291 { 3292 uint32_t status; 3293 uint32_t tlphead[4]; 3294 3295 status = CSR_READ_4(sc, B0_HWE_ISRC); 3296 /* Time Stamp timer overflow. */ 3297 if ((status & Y2_IS_TIST_OV) != 0) 3298 CSR_WRITE_1(sc, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ); 3299 if ((status & Y2_IS_PCI_NEXP) != 0) { 3300 /* 3301 * PCI Express Error occured which is not described in PEX 3302 * spec. 3303 * This error is also mapped either to Master Abort( 3304 * Y2_IS_MST_ERR) or Target Abort (Y2_IS_IRQ_STAT) bit and 3305 * can only be cleared there. 3306 */ 3307 device_printf(sc->msk_dev, 3308 "PCI Express protocol violation error\n"); 3309 } 3310 3311 if ((status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) != 0) { 3312 uint16_t v16; 3313 3314 if ((status & Y2_IS_MST_ERR) != 0) 3315 device_printf(sc->msk_dev, 3316 "unexpected IRQ Status error\n"); 3317 else 3318 device_printf(sc->msk_dev, 3319 "unexpected IRQ Master error\n"); 3320 /* Reset all bits in the PCI status register. */ 3321 v16 = pci_read_config(sc->msk_dev, PCIR_STATUS, 2); 3322 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON); 3323 pci_write_config(sc->msk_dev, PCIR_STATUS, v16 | 3324 PCIM_STATUS_PERR | PCIM_STATUS_SERR | PCIM_STATUS_RMABORT | 3325 PCIM_STATUS_RTABORT | PCIM_STATUS_PERRREPORT, 2); 3326 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 3327 } 3328 3329 /* Check for PCI Express Uncorrectable Error. */ 3330 if ((status & Y2_IS_PCI_EXP) != 0) { 3331 uint32_t v32; 3332 3333 /* 3334 * On PCI Express bus bridges are called root complexes (RC). 3335 * PCI Express errors are recognized by the root complex too, 3336 * which requests the system to handle the problem. After 3337 * error occurence it may be that no access to the adapter 3338 * may be performed any longer. 3339 */ 3340 3341 v32 = CSR_PCI_READ_4(sc, PEX_UNC_ERR_STAT); 3342 if ((v32 & PEX_UNSUP_REQ) != 0) { 3343 /* Ignore unsupported request error. */ 3344 device_printf(sc->msk_dev, 3345 "Uncorrectable PCI Express error\n"); 3346 } 3347 if ((v32 & (PEX_FATAL_ERRORS | PEX_POIS_TLP)) != 0) { 3348 int i; 3349 3350 /* Get TLP header form Log Registers. */ 3351 for (i = 0; i < 4; i++) 3352 tlphead[i] = CSR_PCI_READ_4(sc, 3353 PEX_HEADER_LOG + i * 4); 3354 /* Check for vendor defined broadcast message. */ 3355 if (!(tlphead[0] == 0x73004001 && tlphead[1] == 0x7f)) { 3356 sc->msk_intrhwemask &= ~Y2_IS_PCI_EXP; 3357 CSR_WRITE_4(sc, B0_HWE_IMSK, 3358 sc->msk_intrhwemask); 3359 CSR_READ_4(sc, B0_HWE_IMSK); 3360 } 3361 } 3362 /* Clear the interrupt. */ 3363 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON); 3364 CSR_PCI_WRITE_4(sc, PEX_UNC_ERR_STAT, 0xffffffff); 3365 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 3366 } 3367 3368 if ((status & Y2_HWE_L1_MASK) != 0 && sc->msk_if[MSK_PORT_A] != NULL) 3369 msk_handle_hwerr(sc->msk_if[MSK_PORT_A], status); 3370 if ((status & Y2_HWE_L2_MASK) != 0 && sc->msk_if[MSK_PORT_B] != NULL) 3371 msk_handle_hwerr(sc->msk_if[MSK_PORT_B], status >> 8); 3372 } 3373 3374 static __inline void 3375 msk_rxput(struct msk_if_softc *sc_if) 3376 { 3377 struct msk_softc *sc; 3378 3379 sc = sc_if->msk_softc; 3380 if (sc_if->msk_framesize > (MCLBYTES - MSK_RX_BUF_ALIGN)) 3381 bus_dmamap_sync( 3382 sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 3383 sc_if->msk_cdata.msk_jumbo_rx_ring_map, 3384 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3385 else 3386 bus_dmamap_sync( 3387 sc_if->msk_cdata.msk_rx_ring_tag, 3388 sc_if->msk_cdata.msk_rx_ring_map, 3389 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3390 CSR_WRITE_2(sc, Y2_PREF_Q_ADDR(sc_if->msk_rxq, 3391 PREF_UNIT_PUT_IDX_REG), sc_if->msk_cdata.msk_rx_prod); 3392 } 3393 3394 static int 3395 msk_handle_events(struct msk_softc *sc) 3396 { 3397 struct msk_if_softc *sc_if; 3398 int rxput[2]; 3399 struct msk_stat_desc *sd; 3400 uint32_t control, status; 3401 int cons, idx, len, port, rxprog; 3402 3403 idx = CSR_READ_2(sc, STAT_PUT_IDX); 3404 if (idx == sc->msk_stat_cons) 3405 return (0); 3406 3407 /* Sync status LEs. */ 3408 bus_dmamap_sync(sc->msk_stat_tag, sc->msk_stat_map, 3409 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3410 /* XXX Sync Rx LEs here. */ 3411 3412 rxput[MSK_PORT_A] = rxput[MSK_PORT_B] = 0; 3413 3414 rxprog = 0; 3415 for (cons = sc->msk_stat_cons; cons != idx;) { 3416 sd = &sc->msk_stat_ring[cons]; 3417 control = le32toh(sd->msk_control); 3418 if ((control & HW_OWNER) == 0) 3419 break; 3420 /* 3421 * Marvell's FreeBSD driver updates status LE after clearing 3422 * HW_OWNER. However we don't have a way to sync single LE 3423 * with bus_dma(9) API. bus_dma(9) provides a way to sync 3424 * an entire DMA map. So don't sync LE until we have a better 3425 * way to sync LEs. 3426 */ 3427 control &= ~HW_OWNER; 3428 sd->msk_control = htole32(control); 3429 status = le32toh(sd->msk_status); 3430 len = control & STLE_LEN_MASK; 3431 port = (control >> 16) & 0x01; 3432 sc_if = sc->msk_if[port]; 3433 if (sc_if == NULL) { 3434 device_printf(sc->msk_dev, "invalid port opcode " 3435 "0x%08x\n", control & STLE_OP_MASK); 3436 continue; 3437 } 3438 3439 switch (control & STLE_OP_MASK) { 3440 case OP_RXVLAN: 3441 sc_if->msk_vtag = ntohs(len); 3442 break; 3443 case OP_RXCHKSVLAN: 3444 sc_if->msk_vtag = ntohs(len); 3445 break; 3446 case OP_RXSTAT: 3447 if (sc_if->msk_framesize > 3448 (MCLBYTES - MSK_RX_BUF_ALIGN)) 3449 msk_jumbo_rxeof(sc_if, status, control, len); 3450 else 3451 msk_rxeof(sc_if, status, control, len); 3452 rxprog++; 3453 /* 3454 * Because there is no way to sync single Rx LE 3455 * put the DMA sync operation off until the end of 3456 * event processing. 3457 */ 3458 rxput[port]++; 3459 /* Update prefetch unit if we've passed water mark. */ 3460 if (rxput[port] >= sc_if->msk_cdata.msk_rx_putwm) { 3461 msk_rxput(sc_if); 3462 rxput[port] = 0; 3463 } 3464 break; 3465 case OP_TXINDEXLE: 3466 if (sc->msk_if[MSK_PORT_A] != NULL) 3467 msk_txeof(sc->msk_if[MSK_PORT_A], 3468 status & STLE_TXA1_MSKL); 3469 if (sc->msk_if[MSK_PORT_B] != NULL) 3470 msk_txeof(sc->msk_if[MSK_PORT_B], 3471 ((status & STLE_TXA2_MSKL) >> 3472 STLE_TXA2_SHIFTL) | 3473 ((len & STLE_TXA2_MSKH) << 3474 STLE_TXA2_SHIFTH)); 3475 break; 3476 default: 3477 device_printf(sc->msk_dev, "unhandled opcode 0x%08x\n", 3478 control & STLE_OP_MASK); 3479 break; 3480 } 3481 MSK_INC(cons, MSK_STAT_RING_CNT); 3482 if (rxprog > sc->msk_process_limit) 3483 break; 3484 } 3485 3486 sc->msk_stat_cons = cons; 3487 /* XXX We should sync status LEs here. See above notes. */ 3488 3489 if (rxput[MSK_PORT_A] > 0) 3490 msk_rxput(sc->msk_if[MSK_PORT_A]); 3491 if (rxput[MSK_PORT_B] > 0) 3492 msk_rxput(sc->msk_if[MSK_PORT_B]); 3493 3494 return (sc->msk_stat_cons != CSR_READ_2(sc, STAT_PUT_IDX)); 3495 } 3496 3497 /* Legacy interrupt handler for shared interrupt. */ 3498 static void 3499 msk_legacy_intr(void *xsc) 3500 { 3501 struct msk_softc *sc; 3502 struct msk_if_softc *sc_if0, *sc_if1; 3503 struct ifnet *ifp0, *ifp1; 3504 uint32_t status; 3505 3506 sc = xsc; 3507 MSK_LOCK(sc); 3508 3509 /* Reading B0_Y2_SP_ISRC2 masks further interrupts. */ 3510 status = CSR_READ_4(sc, B0_Y2_SP_ISRC2); 3511 if (status == 0 || status == 0xffffffff || 3512 (sc->msk_pflags & MSK_FLAG_SUSPEND) != 0 || 3513 (status & sc->msk_intrmask) == 0) { 3514 CSR_WRITE_4(sc, B0_Y2_SP_ICR, 2); 3515 return; 3516 } 3517 3518 sc_if0 = sc->msk_if[MSK_PORT_A]; 3519 sc_if1 = sc->msk_if[MSK_PORT_B]; 3520 ifp0 = ifp1 = NULL; 3521 if (sc_if0 != NULL) 3522 ifp0 = sc_if0->msk_ifp; 3523 if (sc_if1 != NULL) 3524 ifp1 = sc_if1->msk_ifp; 3525 3526 if ((status & Y2_IS_IRQ_PHY1) != 0 && sc_if0 != NULL) 3527 msk_intr_phy(sc_if0); 3528 if ((status & Y2_IS_IRQ_PHY2) != 0 && sc_if1 != NULL) 3529 msk_intr_phy(sc_if1); 3530 if ((status & Y2_IS_IRQ_MAC1) != 0 && sc_if0 != NULL) 3531 msk_intr_gmac(sc_if0); 3532 if ((status & Y2_IS_IRQ_MAC2) != 0 && sc_if1 != NULL) 3533 msk_intr_gmac(sc_if1); 3534 if ((status & (Y2_IS_CHK_RX1 | Y2_IS_CHK_RX2)) != 0) { 3535 device_printf(sc->msk_dev, "Rx descriptor error\n"); 3536 sc->msk_intrmask &= ~(Y2_IS_CHK_RX1 | Y2_IS_CHK_RX2); 3537 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask); 3538 CSR_READ_4(sc, B0_IMSK); 3539 } 3540 if ((status & (Y2_IS_CHK_TXA1 | Y2_IS_CHK_TXA2)) != 0) { 3541 device_printf(sc->msk_dev, "Tx descriptor error\n"); 3542 sc->msk_intrmask &= ~(Y2_IS_CHK_TXA1 | Y2_IS_CHK_TXA2); 3543 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask); 3544 CSR_READ_4(sc, B0_IMSK); 3545 } 3546 if ((status & Y2_IS_HW_ERR) != 0) 3547 msk_intr_hwerr(sc); 3548 3549 while (msk_handle_events(sc) != 0) 3550 ; 3551 if ((status & Y2_IS_STAT_BMU) != 0) 3552 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_CLR_IRQ); 3553 3554 /* Reenable interrupts. */ 3555 CSR_WRITE_4(sc, B0_Y2_SP_ICR, 2); 3556 3557 if (ifp0 != NULL && (ifp0->if_drv_flags & IFF_DRV_RUNNING) != 0 && 3558 !IFQ_DRV_IS_EMPTY(&ifp0->if_snd)) 3559 taskqueue_enqueue(taskqueue_fast, &sc_if0->msk_tx_task); 3560 if (ifp1 != NULL && (ifp1->if_drv_flags & IFF_DRV_RUNNING) != 0 && 3561 !IFQ_DRV_IS_EMPTY(&ifp1->if_snd)) 3562 taskqueue_enqueue(taskqueue_fast, &sc_if1->msk_tx_task); 3563 3564 MSK_UNLOCK(sc); 3565 } 3566 3567 static int 3568 msk_intr(void *xsc) 3569 { 3570 struct msk_softc *sc; 3571 uint32_t status; 3572 3573 sc = xsc; 3574 status = CSR_READ_4(sc, B0_Y2_SP_ISRC2); 3575 /* Reading B0_Y2_SP_ISRC2 masks further interrupts. */ 3576 if (status == 0 || status == 0xffffffff) { 3577 CSR_WRITE_4(sc, B0_Y2_SP_ICR, 2); 3578 return (FILTER_STRAY); 3579 } 3580 3581 taskqueue_enqueue(sc->msk_tq, &sc->msk_int_task); 3582 return (FILTER_HANDLED); 3583 } 3584 3585 static void 3586 msk_int_task(void *arg, int pending) 3587 { 3588 struct msk_softc *sc; 3589 struct msk_if_softc *sc_if0, *sc_if1; 3590 struct ifnet *ifp0, *ifp1; 3591 uint32_t status; 3592 int domore; 3593 3594 sc = arg; 3595 MSK_LOCK(sc); 3596 3597 /* Get interrupt source. */ 3598 status = CSR_READ_4(sc, B0_ISRC); 3599 if (status == 0 || status == 0xffffffff || 3600 (sc->msk_pflags & MSK_FLAG_SUSPEND) != 0 || 3601 (status & sc->msk_intrmask) == 0) 3602 goto done; 3603 3604 sc_if0 = sc->msk_if[MSK_PORT_A]; 3605 sc_if1 = sc->msk_if[MSK_PORT_B]; 3606 ifp0 = ifp1 = NULL; 3607 if (sc_if0 != NULL) 3608 ifp0 = sc_if0->msk_ifp; 3609 if (sc_if1 != NULL) 3610 ifp1 = sc_if1->msk_ifp; 3611 3612 if ((status & Y2_IS_IRQ_PHY1) != 0 && sc_if0 != NULL) 3613 msk_intr_phy(sc_if0); 3614 if ((status & Y2_IS_IRQ_PHY2) != 0 && sc_if1 != NULL) 3615 msk_intr_phy(sc_if1); 3616 if ((status & Y2_IS_IRQ_MAC1) != 0 && sc_if0 != NULL) 3617 msk_intr_gmac(sc_if0); 3618 if ((status & Y2_IS_IRQ_MAC2) != 0 && sc_if1 != NULL) 3619 msk_intr_gmac(sc_if1); 3620 if ((status & (Y2_IS_CHK_RX1 | Y2_IS_CHK_RX2)) != 0) { 3621 device_printf(sc->msk_dev, "Rx descriptor error\n"); 3622 sc->msk_intrmask &= ~(Y2_IS_CHK_RX1 | Y2_IS_CHK_RX2); 3623 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask); 3624 CSR_READ_4(sc, B0_IMSK); 3625 } 3626 if ((status & (Y2_IS_CHK_TXA1 | Y2_IS_CHK_TXA2)) != 0) { 3627 device_printf(sc->msk_dev, "Tx descriptor error\n"); 3628 sc->msk_intrmask &= ~(Y2_IS_CHK_TXA1 | Y2_IS_CHK_TXA2); 3629 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask); 3630 CSR_READ_4(sc, B0_IMSK); 3631 } 3632 if ((status & Y2_IS_HW_ERR) != 0) 3633 msk_intr_hwerr(sc); 3634 3635 domore = msk_handle_events(sc); 3636 if ((status & Y2_IS_STAT_BMU) != 0) 3637 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_CLR_IRQ); 3638 3639 if (ifp0 != NULL && (ifp0->if_drv_flags & IFF_DRV_RUNNING) != 0 && 3640 !IFQ_DRV_IS_EMPTY(&ifp0->if_snd)) 3641 taskqueue_enqueue(taskqueue_fast, &sc_if0->msk_tx_task); 3642 if (ifp1 != NULL && (ifp1->if_drv_flags & IFF_DRV_RUNNING) != 0 && 3643 !IFQ_DRV_IS_EMPTY(&ifp1->if_snd)) 3644 taskqueue_enqueue(taskqueue_fast, &sc_if1->msk_tx_task); 3645 3646 if (domore > 0) { 3647 taskqueue_enqueue(sc->msk_tq, &sc->msk_int_task); 3648 MSK_UNLOCK(sc); 3649 return; 3650 } 3651 done: 3652 MSK_UNLOCK(sc); 3653 3654 /* Reenable interrupts. */ 3655 CSR_WRITE_4(sc, B0_Y2_SP_ICR, 2); 3656 } 3657 3658 static void 3659 msk_set_tx_stfwd(struct msk_if_softc *sc_if) 3660 { 3661 struct msk_softc *sc; 3662 struct ifnet *ifp; 3663 3664 ifp = sc_if->msk_ifp; 3665 sc = sc_if->msk_softc; 3666 switch (sc->msk_hw_id) { 3667 case CHIP_ID_YUKON_EX: 3668 if (sc->msk_hw_rev == CHIP_REV_YU_EX_A0) 3669 goto yukon_ex_workaround; 3670 if (ifp->if_mtu > ETHERMTU) 3671 CSR_WRITE_4(sc, 3672 MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 3673 TX_JUMBO_ENA | TX_STFW_ENA); 3674 else 3675 CSR_WRITE_4(sc, 3676 MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 3677 TX_JUMBO_DIS | TX_STFW_ENA); 3678 break; 3679 default: 3680 yukon_ex_workaround: 3681 if (ifp->if_mtu > ETHERMTU) { 3682 /* Set Tx GMAC FIFO Almost Empty Threshold. */ 3683 CSR_WRITE_4(sc, 3684 MR_ADDR(sc_if->msk_port, TX_GMF_AE_THR), 3685 MSK_ECU_JUMBO_WM << 16 | MSK_ECU_AE_THR); 3686 /* Disable Store & Forward mode for Tx. */ 3687 CSR_WRITE_4(sc, 3688 MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 3689 TX_JUMBO_ENA | TX_STFW_DIS); 3690 } else { 3691 /* Enable Store & Forward mode for Tx. */ 3692 CSR_WRITE_4(sc, 3693 MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 3694 TX_JUMBO_DIS | TX_STFW_ENA); 3695 } 3696 break; 3697 } 3698 } 3699 3700 static void 3701 msk_init(void *xsc) 3702 { 3703 struct msk_if_softc *sc_if = xsc; 3704 3705 MSK_IF_LOCK(sc_if); 3706 msk_init_locked(sc_if); 3707 MSK_IF_UNLOCK(sc_if); 3708 } 3709 3710 static void 3711 msk_init_locked(struct msk_if_softc *sc_if) 3712 { 3713 struct msk_softc *sc; 3714 struct ifnet *ifp; 3715 struct mii_data *mii; 3716 uint8_t *eaddr; 3717 uint16_t gmac; 3718 uint32_t reg; 3719 int error; 3720 3721 MSK_IF_LOCK_ASSERT(sc_if); 3722 3723 ifp = sc_if->msk_ifp; 3724 sc = sc_if->msk_softc; 3725 mii = device_get_softc(sc_if->msk_miibus); 3726 3727 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 3728 return; 3729 3730 error = 0; 3731 /* Cancel pending I/O and free all Rx/Tx buffers. */ 3732 msk_stop(sc_if); 3733 3734 if (ifp->if_mtu < ETHERMTU) 3735 sc_if->msk_framesize = ETHERMTU; 3736 else 3737 sc_if->msk_framesize = ifp->if_mtu; 3738 sc_if->msk_framesize += ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 3739 if (ifp->if_mtu > ETHERMTU && 3740 (sc_if->msk_flags & MSK_FLAG_JUMBO_NOCSUM) != 0) { 3741 ifp->if_hwassist &= ~(MSK_CSUM_FEATURES | CSUM_TSO); 3742 ifp->if_capenable &= ~(IFCAP_TSO4 | IFCAP_TXCSUM); 3743 } 3744 3745 /* GMAC Control reset. */ 3746 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_RST_SET); 3747 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_RST_CLR); 3748 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_F_LOOPB_OFF); 3749 if (sc->msk_hw_id == CHIP_ID_YUKON_EX) 3750 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), 3751 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON | 3752 GMC_BYP_RETR_ON); 3753 3754 /* 3755 * Initialize GMAC first such that speed/duplex/flow-control 3756 * parameters are renegotiated when interface is brought up. 3757 */ 3758 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, 0); 3759 3760 /* Dummy read the Interrupt Source Register. */ 3761 CSR_READ_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_SRC)); 3762 3763 /* Clear MIB stats. */ 3764 msk_stats_clear(sc_if); 3765 3766 /* Disable FCS. */ 3767 GMAC_WRITE_2(sc, sc_if->msk_port, GM_RX_CTRL, GM_RXCR_CRC_DIS); 3768 3769 /* Setup Transmit Control Register. */ 3770 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF)); 3771 3772 /* Setup Transmit Flow Control Register. */ 3773 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_FLOW_CTRL, 0xffff); 3774 3775 /* Setup Transmit Parameter Register. */ 3776 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_PARAM, 3777 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) | TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) | 3778 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) | TX_BACK_OFF_LIM(TX_BOF_LIM_DEF)); 3779 3780 gmac = DATA_BLIND_VAL(DATA_BLIND_DEF) | 3781 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF); 3782 3783 if (ifp->if_mtu > ETHERMTU) 3784 gmac |= GM_SMOD_JUMBO_ENA; 3785 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SERIAL_MODE, gmac); 3786 3787 /* Set station address. */ 3788 eaddr = IF_LLADDR(ifp); 3789 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_1L, 3790 eaddr[0] | (eaddr[1] << 8)); 3791 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_1M, 3792 eaddr[2] | (eaddr[3] << 8)); 3793 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_1H, 3794 eaddr[4] | (eaddr[5] << 8)); 3795 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_2L, 3796 eaddr[0] | (eaddr[1] << 8)); 3797 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_2M, 3798 eaddr[2] | (eaddr[3] << 8)); 3799 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_2H, 3800 eaddr[4] | (eaddr[5] << 8)); 3801 3802 /* Disable interrupts for counter overflows. */ 3803 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_IRQ_MSK, 0); 3804 GMAC_WRITE_2(sc, sc_if->msk_port, GM_RX_IRQ_MSK, 0); 3805 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TR_IRQ_MSK, 0); 3806 3807 /* Configure Rx MAC FIFO. */ 3808 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), GMF_RST_SET); 3809 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), GMF_RST_CLR); 3810 reg = GMF_OPER_ON | GMF_RX_F_FL_ON; 3811 if (sc->msk_hw_id == CHIP_ID_YUKON_FE_P || 3812 sc->msk_hw_id == CHIP_ID_YUKON_EX) 3813 reg |= GMF_RX_OVER_ON; 3814 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), reg); 3815 3816 /* Set receive filter. */ 3817 msk_rxfilter(sc_if); 3818 3819 if (sc->msk_hw_id == CHIP_ID_YUKON_XL) { 3820 /* Clear flush mask - HW bug. */ 3821 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_FL_MSK), 0); 3822 } else { 3823 /* Flush Rx MAC FIFO on any flow control or error. */ 3824 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_FL_MSK), 3825 GMR_FS_ANY_ERR); 3826 } 3827 3828 /* 3829 * Set Rx FIFO flush threshold to 64 bytes + 1 FIFO word 3830 * due to hardware hang on receipt of pause frames. 3831 */ 3832 reg = RX_GMF_FL_THR_DEF + 1; 3833 /* Another magic for Yukon FE+ - From Linux. */ 3834 if (sc->msk_hw_id == CHIP_ID_YUKON_FE_P && 3835 sc->msk_hw_rev == CHIP_REV_YU_FE_P_A0) 3836 reg = 0x178; 3837 CSR_WRITE_2(sc, MR_ADDR(sc_if->msk_port, RX_GMF_FL_THR), reg); 3838 3839 /* Configure Tx MAC FIFO. */ 3840 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_RST_SET); 3841 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_RST_CLR); 3842 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_OPER_ON); 3843 3844 /* Configure hardware VLAN tag insertion/stripping. */ 3845 msk_setvlan(sc_if, ifp); 3846 3847 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) == 0) { 3848 /* Set Rx Pause threshould. */ 3849 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, RX_GMF_LP_THR), 3850 MSK_ECU_LLPP); 3851 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, RX_GMF_UP_THR), 3852 MSK_ECU_ULPP); 3853 /* Configure store-and-forward for Tx. */ 3854 msk_set_tx_stfwd(sc_if); 3855 } 3856 3857 if (sc->msk_hw_id == CHIP_ID_YUKON_FE_P && 3858 sc->msk_hw_rev == CHIP_REV_YU_FE_P_A0) { 3859 /* Disable dynamic watermark - from Linux. */ 3860 reg = CSR_READ_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_EA)); 3861 reg &= ~0x03; 3862 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_EA), reg); 3863 } 3864 3865 /* 3866 * Disable Force Sync bit and Alloc bit in Tx RAM interface 3867 * arbiter as we don't use Sync Tx queue. 3868 */ 3869 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, TXA_CTRL), 3870 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC); 3871 /* Enable the RAM Interface Arbiter. */ 3872 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, TXA_CTRL), TXA_ENA_ARB); 3873 3874 /* Setup RAM buffer. */ 3875 msk_set_rambuffer(sc_if); 3876 3877 /* Disable Tx sync Queue. */ 3878 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txsq, RB_CTRL), RB_RST_SET); 3879 3880 /* Setup Tx Queue Bus Memory Interface. */ 3881 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_CLR_RESET); 3882 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_OPER_INIT); 3883 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_FIFO_OP_ON); 3884 CSR_WRITE_2(sc, Q_ADDR(sc_if->msk_txq, Q_WM), MSK_BMU_TX_WM); 3885 switch (sc->msk_hw_id) { 3886 case CHIP_ID_YUKON_EC_U: 3887 if (sc->msk_hw_rev == CHIP_REV_YU_EC_U_A0) { 3888 /* Fix for Yukon-EC Ultra: set BMU FIFO level */ 3889 CSR_WRITE_2(sc, Q_ADDR(sc_if->msk_txq, Q_AL), 3890 MSK_ECU_TXFF_LEV); 3891 } 3892 break; 3893 case CHIP_ID_YUKON_EX: 3894 /* 3895 * Yukon Extreme seems to have silicon bug for 3896 * automatic Tx checksum calculation capability. 3897 */ 3898 if (sc->msk_hw_rev == CHIP_REV_YU_EX_B0) 3899 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_F), 3900 F_TX_CHK_AUTO_OFF); 3901 break; 3902 } 3903 3904 /* Setup Rx Queue Bus Memory Interface. */ 3905 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_CLR_RESET); 3906 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_OPER_INIT); 3907 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_FIFO_OP_ON); 3908 CSR_WRITE_2(sc, Q_ADDR(sc_if->msk_rxq, Q_WM), MSK_BMU_RX_WM); 3909 if (sc->msk_hw_id == CHIP_ID_YUKON_EC_U && 3910 sc->msk_hw_rev >= CHIP_REV_YU_EC_U_A1) { 3911 /* MAC Rx RAM Read is controlled by hardware. */ 3912 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_F), F_M_RX_RAM_DIS); 3913 } 3914 3915 msk_set_prefetch(sc, sc_if->msk_txq, 3916 sc_if->msk_rdata.msk_tx_ring_paddr, MSK_TX_RING_CNT - 1); 3917 msk_init_tx_ring(sc_if); 3918 3919 /* Disable Rx checksum offload and RSS hash. */ 3920 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), 3921 BMU_DIS_RX_CHKSUM | BMU_DIS_RX_RSS_HASH); 3922 if (sc_if->msk_framesize > (MCLBYTES - MSK_RX_BUF_ALIGN)) { 3923 msk_set_prefetch(sc, sc_if->msk_rxq, 3924 sc_if->msk_rdata.msk_jumbo_rx_ring_paddr, 3925 MSK_JUMBO_RX_RING_CNT - 1); 3926 error = msk_init_jumbo_rx_ring(sc_if); 3927 } else { 3928 msk_set_prefetch(sc, sc_if->msk_rxq, 3929 sc_if->msk_rdata.msk_rx_ring_paddr, 3930 MSK_RX_RING_CNT - 1); 3931 error = msk_init_rx_ring(sc_if); 3932 } 3933 if (error != 0) { 3934 device_printf(sc_if->msk_if_dev, 3935 "initialization failed: no memory for Rx buffers\n"); 3936 msk_stop(sc_if); 3937 return; 3938 } 3939 3940 /* Configure interrupt handling. */ 3941 if (sc_if->msk_port == MSK_PORT_A) { 3942 sc->msk_intrmask |= Y2_IS_PORT_A; 3943 sc->msk_intrhwemask |= Y2_HWE_L1_MASK; 3944 } else { 3945 sc->msk_intrmask |= Y2_IS_PORT_B; 3946 sc->msk_intrhwemask |= Y2_HWE_L2_MASK; 3947 } 3948 CSR_WRITE_4(sc, B0_HWE_IMSK, sc->msk_intrhwemask); 3949 CSR_READ_4(sc, B0_HWE_IMSK); 3950 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask); 3951 CSR_READ_4(sc, B0_IMSK); 3952 3953 sc_if->msk_flags &= ~MSK_FLAG_LINK; 3954 mii_mediachg(mii); 3955 3956 ifp->if_drv_flags |= IFF_DRV_RUNNING; 3957 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3958 3959 callout_reset(&sc_if->msk_tick_ch, hz, msk_tick, sc_if); 3960 } 3961 3962 static void 3963 msk_set_rambuffer(struct msk_if_softc *sc_if) 3964 { 3965 struct msk_softc *sc; 3966 int ltpp, utpp; 3967 3968 sc = sc_if->msk_softc; 3969 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) == 0) 3970 return; 3971 3972 /* Setup Rx Queue. */ 3973 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_RST_CLR); 3974 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_START), 3975 sc->msk_rxqstart[sc_if->msk_port] / 8); 3976 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_END), 3977 sc->msk_rxqend[sc_if->msk_port] / 8); 3978 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_WP), 3979 sc->msk_rxqstart[sc_if->msk_port] / 8); 3980 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_RP), 3981 sc->msk_rxqstart[sc_if->msk_port] / 8); 3982 3983 utpp = (sc->msk_rxqend[sc_if->msk_port] + 1 - 3984 sc->msk_rxqstart[sc_if->msk_port] - MSK_RB_ULPP) / 8; 3985 ltpp = (sc->msk_rxqend[sc_if->msk_port] + 1 - 3986 sc->msk_rxqstart[sc_if->msk_port] - MSK_RB_LLPP_B) / 8; 3987 if (sc->msk_rxqsize < MSK_MIN_RXQ_SIZE) 3988 ltpp += (MSK_RB_LLPP_B - MSK_RB_LLPP_S) / 8; 3989 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_RX_UTPP), utpp); 3990 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_RX_LTPP), ltpp); 3991 /* Set Rx priority(RB_RX_UTHP/RB_RX_LTHP) thresholds? */ 3992 3993 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_ENA_OP_MD); 3994 CSR_READ_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL)); 3995 3996 /* Setup Tx Queue. */ 3997 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_RST_CLR); 3998 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_START), 3999 sc->msk_txqstart[sc_if->msk_port] / 8); 4000 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_END), 4001 sc->msk_txqend[sc_if->msk_port] / 8); 4002 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_WP), 4003 sc->msk_txqstart[sc_if->msk_port] / 8); 4004 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_RP), 4005 sc->msk_txqstart[sc_if->msk_port] / 8); 4006 /* Enable Store & Forward for Tx side. */ 4007 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_ENA_STFWD); 4008 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_ENA_OP_MD); 4009 CSR_READ_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL)); 4010 } 4011 4012 static void 4013 msk_set_prefetch(struct msk_softc *sc, int qaddr, bus_addr_t addr, 4014 uint32_t count) 4015 { 4016 4017 /* Reset the prefetch unit. */ 4018 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG), 4019 PREF_UNIT_RST_SET); 4020 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG), 4021 PREF_UNIT_RST_CLR); 4022 /* Set LE base address. */ 4023 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_ADDR_LOW_REG), 4024 MSK_ADDR_LO(addr)); 4025 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_ADDR_HI_REG), 4026 MSK_ADDR_HI(addr)); 4027 /* Set the list last index. */ 4028 CSR_WRITE_2(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_LAST_IDX_REG), 4029 count); 4030 /* Turn on prefetch unit. */ 4031 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG), 4032 PREF_UNIT_OP_ON); 4033 /* Dummy read to ensure write. */ 4034 CSR_READ_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG)); 4035 } 4036 4037 static void 4038 msk_stop(struct msk_if_softc *sc_if) 4039 { 4040 struct msk_softc *sc; 4041 struct msk_txdesc *txd; 4042 struct msk_rxdesc *rxd; 4043 struct msk_rxdesc *jrxd; 4044 struct ifnet *ifp; 4045 uint32_t val; 4046 int i; 4047 4048 MSK_IF_LOCK_ASSERT(sc_if); 4049 sc = sc_if->msk_softc; 4050 ifp = sc_if->msk_ifp; 4051 4052 callout_stop(&sc_if->msk_tick_ch); 4053 sc_if->msk_watchdog_timer = 0; 4054 4055 /* Disable interrupts. */ 4056 if (sc_if->msk_port == MSK_PORT_A) { 4057 sc->msk_intrmask &= ~Y2_IS_PORT_A; 4058 sc->msk_intrhwemask &= ~Y2_HWE_L1_MASK; 4059 } else { 4060 sc->msk_intrmask &= ~Y2_IS_PORT_B; 4061 sc->msk_intrhwemask &= ~Y2_HWE_L2_MASK; 4062 } 4063 CSR_WRITE_4(sc, B0_HWE_IMSK, sc->msk_intrhwemask); 4064 CSR_READ_4(sc, B0_HWE_IMSK); 4065 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask); 4066 CSR_READ_4(sc, B0_IMSK); 4067 4068 /* Disable Tx/Rx MAC. */ 4069 val = GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL); 4070 val &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA); 4071 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, val); 4072 /* Read again to ensure writing. */ 4073 GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL); 4074 /* Update stats and clear counters. */ 4075 msk_stats_update(sc_if); 4076 4077 /* Stop Tx BMU. */ 4078 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_STOP); 4079 val = CSR_READ_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR)); 4080 for (i = 0; i < MSK_TIMEOUT; i++) { 4081 if ((val & (BMU_STOP | BMU_IDLE)) == 0) { 4082 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), 4083 BMU_STOP); 4084 val = CSR_READ_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR)); 4085 } else 4086 break; 4087 DELAY(1); 4088 } 4089 if (i == MSK_TIMEOUT) 4090 device_printf(sc_if->msk_if_dev, "Tx BMU stop failed\n"); 4091 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), 4092 RB_RST_SET | RB_DIS_OP_MD); 4093 4094 /* Disable all GMAC interrupt. */ 4095 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_MSK), 0); 4096 /* Disable PHY interrupt. */ 4097 msk_phy_writereg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_MASK, 0); 4098 4099 /* Disable the RAM Interface Arbiter. */ 4100 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, TXA_CTRL), TXA_DIS_ARB); 4101 4102 /* Reset the PCI FIFO of the async Tx queue */ 4103 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), 4104 BMU_RST_SET | BMU_FIFO_RST); 4105 4106 /* Reset the Tx prefetch units. */ 4107 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(sc_if->msk_txq, PREF_UNIT_CTRL_REG), 4108 PREF_UNIT_RST_SET); 4109 4110 /* Reset the RAM Buffer async Tx queue. */ 4111 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_RST_SET); 4112 4113 /* Reset Tx MAC FIFO. */ 4114 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_RST_SET); 4115 /* Set Pause Off. */ 4116 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_PAUSE_OFF); 4117 4118 /* 4119 * The Rx Stop command will not work for Yukon-2 if the BMU does not 4120 * reach the end of packet and since we can't make sure that we have 4121 * incoming data, we must reset the BMU while it is not during a DMA 4122 * transfer. Since it is possible that the Rx path is still active, 4123 * the Rx RAM buffer will be stopped first, so any possible incoming 4124 * data will not trigger a DMA. After the RAM buffer is stopped, the 4125 * BMU is polled until any DMA in progress is ended and only then it 4126 * will be reset. 4127 */ 4128 4129 /* Disable the RAM Buffer receive queue. */ 4130 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_DIS_OP_MD); 4131 for (i = 0; i < MSK_TIMEOUT; i++) { 4132 if (CSR_READ_1(sc, RB_ADDR(sc_if->msk_rxq, Q_RSL)) == 4133 CSR_READ_1(sc, RB_ADDR(sc_if->msk_rxq, Q_RL))) 4134 break; 4135 DELAY(1); 4136 } 4137 if (i == MSK_TIMEOUT) 4138 device_printf(sc_if->msk_if_dev, "Rx BMU stop failed\n"); 4139 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), 4140 BMU_RST_SET | BMU_FIFO_RST); 4141 /* Reset the Rx prefetch unit. */ 4142 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_CTRL_REG), 4143 PREF_UNIT_RST_SET); 4144 /* Reset the RAM Buffer receive queue. */ 4145 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_RST_SET); 4146 /* Reset Rx MAC FIFO. */ 4147 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), GMF_RST_SET); 4148 4149 /* Free Rx and Tx mbufs still in the queues. */ 4150 for (i = 0; i < MSK_RX_RING_CNT; i++) { 4151 rxd = &sc_if->msk_cdata.msk_rxdesc[i]; 4152 if (rxd->rx_m != NULL) { 4153 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_tag, 4154 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 4155 bus_dmamap_unload(sc_if->msk_cdata.msk_rx_tag, 4156 rxd->rx_dmamap); 4157 m_freem(rxd->rx_m); 4158 rxd->rx_m = NULL; 4159 } 4160 } 4161 for (i = 0; i < MSK_JUMBO_RX_RING_CNT; i++) { 4162 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[i]; 4163 if (jrxd->rx_m != NULL) { 4164 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_tag, 4165 jrxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 4166 bus_dmamap_unload(sc_if->msk_cdata.msk_jumbo_rx_tag, 4167 jrxd->rx_dmamap); 4168 m_freem(jrxd->rx_m); 4169 jrxd->rx_m = NULL; 4170 } 4171 } 4172 for (i = 0; i < MSK_TX_RING_CNT; i++) { 4173 txd = &sc_if->msk_cdata.msk_txdesc[i]; 4174 if (txd->tx_m != NULL) { 4175 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_tag, 4176 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 4177 bus_dmamap_unload(sc_if->msk_cdata.msk_tx_tag, 4178 txd->tx_dmamap); 4179 m_freem(txd->tx_m); 4180 txd->tx_m = NULL; 4181 } 4182 } 4183 4184 /* 4185 * Mark the interface down. 4186 */ 4187 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 4188 sc_if->msk_flags &= ~MSK_FLAG_LINK; 4189 } 4190 4191 /* 4192 * When GM_PAR_MIB_CLR bit of GM_PHY_ADDR is set, reading lower 4193 * counter clears high 16 bits of the counter such that accessing 4194 * lower 16 bits should be the last operation. 4195 */ 4196 #define MSK_READ_MIB32(x, y) \ 4197 (((uint32_t)GMAC_READ_2(sc, x, (y) + 4)) << 16) + \ 4198 (uint32_t)GMAC_READ_2(sc, x, y) 4199 #define MSK_READ_MIB64(x, y) \ 4200 (((uint64_t)MSK_READ_MIB32(x, (y) + 8)) << 32) + \ 4201 (uint64_t)MSK_READ_MIB32(x, y) 4202 4203 static void 4204 msk_stats_clear(struct msk_if_softc *sc_if) 4205 { 4206 struct msk_softc *sc; 4207 uint32_t reg; 4208 uint16_t gmac; 4209 int i; 4210 4211 MSK_IF_LOCK_ASSERT(sc_if); 4212 4213 sc = sc_if->msk_softc; 4214 /* Set MIB Clear Counter Mode. */ 4215 gmac = GMAC_READ_2(sc, sc_if->msk_port, GM_PHY_ADDR); 4216 GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac | GM_PAR_MIB_CLR); 4217 /* Read all MIB Counters with Clear Mode set. */ 4218 for (i = GM_RXF_UC_OK; i <= GM_TXE_FIFO_UR; i += sizeof(uint32_t)) 4219 reg = MSK_READ_MIB32(sc_if->msk_port, i); 4220 /* Clear MIB Clear Counter Mode. */ 4221 gmac &= ~GM_PAR_MIB_CLR; 4222 GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac); 4223 } 4224 4225 static void 4226 msk_stats_update(struct msk_if_softc *sc_if) 4227 { 4228 struct msk_softc *sc; 4229 struct ifnet *ifp; 4230 struct msk_hw_stats *stats; 4231 uint16_t gmac; 4232 uint32_t reg; 4233 4234 MSK_IF_LOCK_ASSERT(sc_if); 4235 4236 ifp = sc_if->msk_ifp; 4237 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 4238 return; 4239 sc = sc_if->msk_softc; 4240 stats = &sc_if->msk_stats; 4241 /* Set MIB Clear Counter Mode. */ 4242 gmac = GMAC_READ_2(sc, sc_if->msk_port, GM_PHY_ADDR); 4243 GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac | GM_PAR_MIB_CLR); 4244 4245 /* Rx stats. */ 4246 stats->rx_ucast_frames += 4247 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_UC_OK); 4248 stats->rx_bcast_frames += 4249 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_BC_OK); 4250 stats->rx_pause_frames += 4251 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_MPAUSE); 4252 stats->rx_mcast_frames += 4253 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_MC_OK); 4254 stats->rx_crc_errs += 4255 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_FCS_ERR); 4256 reg = MSK_READ_MIB32(sc_if->msk_port, GM_RXF_SPARE1); 4257 stats->rx_good_octets += 4258 MSK_READ_MIB64(sc_if->msk_port, GM_RXO_OK_LO); 4259 stats->rx_bad_octets += 4260 MSK_READ_MIB64(sc_if->msk_port, GM_RXO_ERR_LO); 4261 stats->rx_runts += 4262 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_SHT); 4263 stats->rx_runt_errs += 4264 MSK_READ_MIB32(sc_if->msk_port, GM_RXE_FRAG); 4265 stats->rx_pkts_64 += 4266 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_64B); 4267 stats->rx_pkts_65_127 += 4268 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_127B); 4269 stats->rx_pkts_128_255 += 4270 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_255B); 4271 stats->rx_pkts_256_511 += 4272 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_511B); 4273 stats->rx_pkts_512_1023 += 4274 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_1023B); 4275 stats->rx_pkts_1024_1518 += 4276 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_1518B); 4277 stats->rx_pkts_1519_max += 4278 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_MAX_SZ); 4279 stats->rx_pkts_too_long += 4280 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_LNG_ERR); 4281 stats->rx_pkts_jabbers += 4282 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_JAB_PKT); 4283 reg = MSK_READ_MIB32(sc_if->msk_port, GM_RXF_SPARE2); 4284 stats->rx_fifo_oflows += 4285 MSK_READ_MIB32(sc_if->msk_port, GM_RXE_FIFO_OV); 4286 reg = MSK_READ_MIB32(sc_if->msk_port, GM_RXF_SPARE3); 4287 4288 /* Tx stats. */ 4289 stats->tx_ucast_frames += 4290 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_UC_OK); 4291 stats->tx_bcast_frames += 4292 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_BC_OK); 4293 stats->tx_pause_frames += 4294 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_MPAUSE); 4295 stats->tx_mcast_frames += 4296 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_MC_OK); 4297 stats->tx_octets += 4298 MSK_READ_MIB64(sc_if->msk_port, GM_TXO_OK_LO); 4299 stats->tx_pkts_64 += 4300 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_64B); 4301 stats->tx_pkts_65_127 += 4302 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_127B); 4303 stats->tx_pkts_128_255 += 4304 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_255B); 4305 stats->tx_pkts_256_511 += 4306 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_511B); 4307 stats->tx_pkts_512_1023 += 4308 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_1023B); 4309 stats->tx_pkts_1024_1518 += 4310 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_1518B); 4311 stats->tx_pkts_1519_max += 4312 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_MAX_SZ); 4313 reg = MSK_READ_MIB32(sc_if->msk_port, GM_TXF_SPARE1); 4314 stats->tx_colls += 4315 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_COL); 4316 stats->tx_late_colls += 4317 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_LAT_COL); 4318 stats->tx_excess_colls += 4319 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_ABO_COL); 4320 stats->tx_multi_colls += 4321 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_MUL_COL); 4322 stats->tx_single_colls += 4323 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_SNG_COL); 4324 stats->tx_underflows += 4325 MSK_READ_MIB32(sc_if->msk_port, GM_TXE_FIFO_UR); 4326 /* Clear MIB Clear Counter Mode. */ 4327 gmac &= ~GM_PAR_MIB_CLR; 4328 GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac); 4329 } 4330 4331 static int 4332 msk_sysctl_stat32(SYSCTL_HANDLER_ARGS) 4333 { 4334 struct msk_softc *sc; 4335 struct msk_if_softc *sc_if; 4336 uint32_t result, *stat; 4337 int off; 4338 4339 sc_if = (struct msk_if_softc *)arg1; 4340 sc = sc_if->msk_softc; 4341 off = arg2; 4342 stat = (uint32_t *)((uint8_t *)&sc_if->msk_stats + off); 4343 4344 MSK_IF_LOCK(sc_if); 4345 result = MSK_READ_MIB32(sc_if->msk_port, GM_MIB_CNT_BASE + off * 2); 4346 result += *stat; 4347 MSK_IF_UNLOCK(sc_if); 4348 4349 return (sysctl_handle_int(oidp, &result, 0, req)); 4350 } 4351 4352 static int 4353 msk_sysctl_stat64(SYSCTL_HANDLER_ARGS) 4354 { 4355 struct msk_softc *sc; 4356 struct msk_if_softc *sc_if; 4357 uint64_t result, *stat; 4358 int off; 4359 4360 sc_if = (struct msk_if_softc *)arg1; 4361 sc = sc_if->msk_softc; 4362 off = arg2; 4363 stat = (uint64_t *)((uint8_t *)&sc_if->msk_stats + off); 4364 4365 MSK_IF_LOCK(sc_if); 4366 result = MSK_READ_MIB64(sc_if->msk_port, GM_MIB_CNT_BASE + off * 2); 4367 result += *stat; 4368 MSK_IF_UNLOCK(sc_if); 4369 4370 return (sysctl_handle_quad(oidp, &result, 0, req)); 4371 } 4372 4373 #undef MSK_READ_MIB32 4374 #undef MSK_READ_MIB64 4375 4376 #define MSK_SYSCTL_STAT32(sc, c, o, p, n, d) \ 4377 SYSCTL_ADD_PROC(c, p, OID_AUTO, o, CTLTYPE_UINT | CTLFLAG_RD, \ 4378 sc, offsetof(struct msk_hw_stats, n), msk_sysctl_stat32, \ 4379 "IU", d) 4380 #define MSK_SYSCTL_STAT64(sc, c, o, p, n, d) \ 4381 SYSCTL_ADD_PROC(c, p, OID_AUTO, o, CTLTYPE_UINT | CTLFLAG_RD, \ 4382 sc, offsetof(struct msk_hw_stats, n), msk_sysctl_stat64, \ 4383 "Q", d) 4384 4385 static void 4386 msk_sysctl_node(struct msk_if_softc *sc_if) 4387 { 4388 struct sysctl_ctx_list *ctx; 4389 struct sysctl_oid_list *child, *schild; 4390 struct sysctl_oid *tree; 4391 4392 ctx = device_get_sysctl_ctx(sc_if->msk_if_dev); 4393 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc_if->msk_if_dev)); 4394 4395 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD, 4396 NULL, "MSK Statistics"); 4397 schild = child = SYSCTL_CHILDREN(tree); 4398 tree = SYSCTL_ADD_NODE(ctx, schild, OID_AUTO, "rx", CTLFLAG_RD, 4399 NULL, "MSK RX Statistics"); 4400 child = SYSCTL_CHILDREN(tree); 4401 MSK_SYSCTL_STAT32(sc_if, ctx, "ucast_frames", 4402 child, rx_ucast_frames, "Good unicast frames"); 4403 MSK_SYSCTL_STAT32(sc_if, ctx, "bcast_frames", 4404 child, rx_bcast_frames, "Good broadcast frames"); 4405 MSK_SYSCTL_STAT32(sc_if, ctx, "pause_frames", 4406 child, rx_pause_frames, "Pause frames"); 4407 MSK_SYSCTL_STAT32(sc_if, ctx, "mcast_frames", 4408 child, rx_mcast_frames, "Multicast frames"); 4409 MSK_SYSCTL_STAT32(sc_if, ctx, "crc_errs", 4410 child, rx_crc_errs, "CRC errors"); 4411 MSK_SYSCTL_STAT64(sc_if, ctx, "good_octets", 4412 child, rx_good_octets, "Good octets"); 4413 MSK_SYSCTL_STAT64(sc_if, ctx, "bad_octets", 4414 child, rx_bad_octets, "Bad octets"); 4415 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_64", 4416 child, rx_pkts_64, "64 bytes frames"); 4417 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_65_127", 4418 child, rx_pkts_65_127, "65 to 127 bytes frames"); 4419 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_128_255", 4420 child, rx_pkts_128_255, "128 to 255 bytes frames"); 4421 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_256_511", 4422 child, rx_pkts_256_511, "256 to 511 bytes frames"); 4423 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_512_1023", 4424 child, rx_pkts_512_1023, "512 to 1023 bytes frames"); 4425 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_1024_1518", 4426 child, rx_pkts_1024_1518, "1024 to 1518 bytes frames"); 4427 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_1519_max", 4428 child, rx_pkts_1519_max, "1519 to max frames"); 4429 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_too_long", 4430 child, rx_pkts_too_long, "frames too long"); 4431 MSK_SYSCTL_STAT32(sc_if, ctx, "jabbers", 4432 child, rx_pkts_jabbers, "Jabber errors"); 4433 MSK_SYSCTL_STAT32(sc_if, ctx, "overflows", 4434 child, rx_fifo_oflows, "FIFO overflows"); 4435 4436 tree = SYSCTL_ADD_NODE(ctx, schild, OID_AUTO, "tx", CTLFLAG_RD, 4437 NULL, "MSK TX Statistics"); 4438 child = SYSCTL_CHILDREN(tree); 4439 MSK_SYSCTL_STAT32(sc_if, ctx, "ucast_frames", 4440 child, tx_ucast_frames, "Unicast frames"); 4441 MSK_SYSCTL_STAT32(sc_if, ctx, "bcast_frames", 4442 child, tx_bcast_frames, "Broadcast frames"); 4443 MSK_SYSCTL_STAT32(sc_if, ctx, "pause_frames", 4444 child, tx_pause_frames, "Pause frames"); 4445 MSK_SYSCTL_STAT32(sc_if, ctx, "mcast_frames", 4446 child, tx_mcast_frames, "Multicast frames"); 4447 MSK_SYSCTL_STAT64(sc_if, ctx, "octets", 4448 child, tx_octets, "Octets"); 4449 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_64", 4450 child, tx_pkts_64, "64 bytes frames"); 4451 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_65_127", 4452 child, tx_pkts_65_127, "65 to 127 bytes frames"); 4453 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_128_255", 4454 child, tx_pkts_128_255, "128 to 255 bytes frames"); 4455 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_256_511", 4456 child, tx_pkts_256_511, "256 to 511 bytes frames"); 4457 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_512_1023", 4458 child, tx_pkts_512_1023, "512 to 1023 bytes frames"); 4459 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_1024_1518", 4460 child, tx_pkts_1024_1518, "1024 to 1518 bytes frames"); 4461 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_1519_max", 4462 child, tx_pkts_1519_max, "1519 to max frames"); 4463 MSK_SYSCTL_STAT32(sc_if, ctx, "colls", 4464 child, tx_colls, "Collisions"); 4465 MSK_SYSCTL_STAT32(sc_if, ctx, "late_colls", 4466 child, tx_late_colls, "Late collisions"); 4467 MSK_SYSCTL_STAT32(sc_if, ctx, "excess_colls", 4468 child, tx_excess_colls, "Excessive collisions"); 4469 MSK_SYSCTL_STAT32(sc_if, ctx, "multi_colls", 4470 child, tx_multi_colls, "Multiple collisions"); 4471 MSK_SYSCTL_STAT32(sc_if, ctx, "single_colls", 4472 child, tx_single_colls, "Single collisions"); 4473 MSK_SYSCTL_STAT32(sc_if, ctx, "underflows", 4474 child, tx_underflows, "FIFO underflows"); 4475 } 4476 4477 #undef MSK_SYSCTL_STAT32 4478 #undef MSK_SYSCTL_STAT64 4479 4480 static int 4481 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 4482 { 4483 int error, value; 4484 4485 if (!arg1) 4486 return (EINVAL); 4487 value = *(int *)arg1; 4488 error = sysctl_handle_int(oidp, &value, 0, req); 4489 if (error || !req->newptr) 4490 return (error); 4491 if (value < low || value > high) 4492 return (EINVAL); 4493 *(int *)arg1 = value; 4494 4495 return (0); 4496 } 4497 4498 static int 4499 sysctl_hw_msk_proc_limit(SYSCTL_HANDLER_ARGS) 4500 { 4501 4502 return (sysctl_int_range(oidp, arg1, arg2, req, MSK_PROC_MIN, 4503 MSK_PROC_MAX)); 4504 } 4505