1 /****************************************************************************** 2 * 3 * Name : sky2.c 4 * Project: Gigabit Ethernet Driver for FreeBSD 5.x/6.x 5 * Version: $Revision: 1.23 $ 6 * Date : $Date: 2005/12/22 09:04:11 $ 7 * Purpose: Main driver source file 8 * 9 *****************************************************************************/ 10 11 /****************************************************************************** 12 * 13 * LICENSE: 14 * Copyright (C) Marvell International Ltd. and/or its affiliates 15 * 16 * The computer program files contained in this folder ("Files") 17 * are provided to you under the BSD-type license terms provided 18 * below, and any use of such Files and any derivative works 19 * thereof created by you shall be governed by the following terms 20 * and conditions: 21 * 22 * - Redistributions of source code must retain the above copyright 23 * notice, this list of conditions and the following disclaimer. 24 * - Redistributions in binary form must reproduce the above 25 * copyright notice, this list of conditions and the following 26 * disclaimer in the documentation and/or other materials provided 27 * with the distribution. 28 * - Neither the name of Marvell nor the names of its contributors 29 * may be used to endorse or promote products derived from this 30 * software without specific prior written permission. 31 * 32 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 33 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 34 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 35 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 36 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 37 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 38 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 39 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 40 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 41 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 42 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED 43 * OF THE POSSIBILITY OF SUCH DAMAGE. 44 * /LICENSE 45 * 46 *****************************************************************************/ 47 48 /*- 49 * SPDX-License-Identifier: BSD-4-Clause AND BSD-3-Clause 50 * 51 * Copyright (c) 1997, 1998, 1999, 2000 52 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 53 * 54 * Redistribution and use in source and binary forms, with or without 55 * modification, are permitted provided that the following conditions 56 * are met: 57 * 1. Redistributions of source code must retain the above copyright 58 * notice, this list of conditions and the following disclaimer. 59 * 2. Redistributions in binary form must reproduce the above copyright 60 * notice, this list of conditions and the following disclaimer in the 61 * documentation and/or other materials provided with the distribution. 62 * 3. All advertising materials mentioning features or use of this software 63 * must display the following acknowledgement: 64 * This product includes software developed by Bill Paul. 65 * 4. Neither the name of the author nor the names of any co-contributors 66 * may be used to endorse or promote products derived from this software 67 * without specific prior written permission. 68 * 69 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 70 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 71 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 72 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 73 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 74 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 75 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 76 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 77 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 78 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 79 * THE POSSIBILITY OF SUCH DAMAGE. 80 */ 81 /*- 82 * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu> 83 * 84 * Permission to use, copy, modify, and distribute this software for any 85 * purpose with or without fee is hereby granted, provided that the above 86 * copyright notice and this permission notice appear in all copies. 87 * 88 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 89 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 90 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 91 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 92 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 93 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 94 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 95 */ 96 97 /* 98 * Device driver for the Marvell Yukon II Ethernet controller. 99 * Due to lack of documentation, this driver is based on the code from 100 * sk(4) and Marvell's myk(4) driver for FreeBSD 5.x. 101 */ 102 103 #include <sys/param.h> 104 #include <sys/systm.h> 105 #include <sys/bus.h> 106 #include <sys/endian.h> 107 #include <sys/mbuf.h> 108 #include <sys/malloc.h> 109 #include <sys/kernel.h> 110 #include <sys/module.h> 111 #include <sys/socket.h> 112 #include <sys/sockio.h> 113 #include <sys/queue.h> 114 #include <sys/sysctl.h> 115 116 #include <net/bpf.h> 117 #include <net/ethernet.h> 118 #include <net/if.h> 119 #include <net/if_var.h> 120 #include <net/if_arp.h> 121 #include <net/if_dl.h> 122 #include <net/if_media.h> 123 #include <net/if_types.h> 124 #include <net/if_vlan_var.h> 125 126 #include <netinet/in.h> 127 #include <netinet/in_systm.h> 128 #include <netinet/ip.h> 129 #include <netinet/tcp.h> 130 #include <netinet/udp.h> 131 132 #include <machine/bus.h> 133 #include <machine/in_cksum.h> 134 #include <machine/resource.h> 135 #include <sys/rman.h> 136 137 #include <dev/mii/mii.h> 138 #include <dev/mii/miivar.h> 139 140 #include <dev/pci/pcireg.h> 141 #include <dev/pci/pcivar.h> 142 143 #include <dev/msk/if_mskreg.h> 144 145 MODULE_DEPEND(msk, pci, 1, 1, 1); 146 MODULE_DEPEND(msk, ether, 1, 1, 1); 147 MODULE_DEPEND(msk, miibus, 1, 1, 1); 148 149 /* "device miibus" required. See GENERIC if you get errors here. */ 150 #include "miibus_if.h" 151 152 /* Tunables. */ 153 static int msi_disable = 0; 154 TUNABLE_INT("hw.msk.msi_disable", &msi_disable); 155 static int legacy_intr = 0; 156 TUNABLE_INT("hw.msk.legacy_intr", &legacy_intr); 157 static int jumbo_disable = 0; 158 TUNABLE_INT("hw.msk.jumbo_disable", &jumbo_disable); 159 160 #define MSK_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 161 162 /* 163 * Devices supported by this driver. 164 */ 165 static const struct msk_product { 166 uint16_t msk_vendorid; 167 uint16_t msk_deviceid; 168 const char *msk_name; 169 } msk_products[] = { 170 { VENDORID_SK, DEVICEID_SK_YUKON2, 171 "SK-9Sxx Gigabit Ethernet" }, 172 { VENDORID_SK, DEVICEID_SK_YUKON2_EXPR, 173 "SK-9Exx Gigabit Ethernet"}, 174 { VENDORID_MARVELL, DEVICEID_MRVL_8021CU, 175 "Marvell Yukon 88E8021CU Gigabit Ethernet" }, 176 { VENDORID_MARVELL, DEVICEID_MRVL_8021X, 177 "Marvell Yukon 88E8021 SX/LX Gigabit Ethernet" }, 178 { VENDORID_MARVELL, DEVICEID_MRVL_8022CU, 179 "Marvell Yukon 88E8022CU Gigabit Ethernet" }, 180 { VENDORID_MARVELL, DEVICEID_MRVL_8022X, 181 "Marvell Yukon 88E8022 SX/LX Gigabit Ethernet" }, 182 { VENDORID_MARVELL, DEVICEID_MRVL_8061CU, 183 "Marvell Yukon 88E8061CU Gigabit Ethernet" }, 184 { VENDORID_MARVELL, DEVICEID_MRVL_8061X, 185 "Marvell Yukon 88E8061 SX/LX Gigabit Ethernet" }, 186 { VENDORID_MARVELL, DEVICEID_MRVL_8062CU, 187 "Marvell Yukon 88E8062CU Gigabit Ethernet" }, 188 { VENDORID_MARVELL, DEVICEID_MRVL_8062X, 189 "Marvell Yukon 88E8062 SX/LX Gigabit Ethernet" }, 190 { VENDORID_MARVELL, DEVICEID_MRVL_8035, 191 "Marvell Yukon 88E8035 Fast Ethernet" }, 192 { VENDORID_MARVELL, DEVICEID_MRVL_8036, 193 "Marvell Yukon 88E8036 Fast Ethernet" }, 194 { VENDORID_MARVELL, DEVICEID_MRVL_8038, 195 "Marvell Yukon 88E8038 Fast Ethernet" }, 196 { VENDORID_MARVELL, DEVICEID_MRVL_8039, 197 "Marvell Yukon 88E8039 Fast Ethernet" }, 198 { VENDORID_MARVELL, DEVICEID_MRVL_8040, 199 "Marvell Yukon 88E8040 Fast Ethernet" }, 200 { VENDORID_MARVELL, DEVICEID_MRVL_8040T, 201 "Marvell Yukon 88E8040T Fast Ethernet" }, 202 { VENDORID_MARVELL, DEVICEID_MRVL_8042, 203 "Marvell Yukon 88E8042 Fast Ethernet" }, 204 { VENDORID_MARVELL, DEVICEID_MRVL_8048, 205 "Marvell Yukon 88E8048 Fast Ethernet" }, 206 { VENDORID_MARVELL, DEVICEID_MRVL_4361, 207 "Marvell Yukon 88E8050 Gigabit Ethernet" }, 208 { VENDORID_MARVELL, DEVICEID_MRVL_4360, 209 "Marvell Yukon 88E8052 Gigabit Ethernet" }, 210 { VENDORID_MARVELL, DEVICEID_MRVL_4362, 211 "Marvell Yukon 88E8053 Gigabit Ethernet" }, 212 { VENDORID_MARVELL, DEVICEID_MRVL_4363, 213 "Marvell Yukon 88E8055 Gigabit Ethernet" }, 214 { VENDORID_MARVELL, DEVICEID_MRVL_4364, 215 "Marvell Yukon 88E8056 Gigabit Ethernet" }, 216 { VENDORID_MARVELL, DEVICEID_MRVL_4365, 217 "Marvell Yukon 88E8070 Gigabit Ethernet" }, 218 { VENDORID_MARVELL, DEVICEID_MRVL_436A, 219 "Marvell Yukon 88E8058 Gigabit Ethernet" }, 220 { VENDORID_MARVELL, DEVICEID_MRVL_436B, 221 "Marvell Yukon 88E8071 Gigabit Ethernet" }, 222 { VENDORID_MARVELL, DEVICEID_MRVL_436C, 223 "Marvell Yukon 88E8072 Gigabit Ethernet" }, 224 { VENDORID_MARVELL, DEVICEID_MRVL_436D, 225 "Marvell Yukon 88E8055 Gigabit Ethernet" }, 226 { VENDORID_MARVELL, DEVICEID_MRVL_4370, 227 "Marvell Yukon 88E8075 Gigabit Ethernet" }, 228 { VENDORID_MARVELL, DEVICEID_MRVL_4380, 229 "Marvell Yukon 88E8057 Gigabit Ethernet" }, 230 { VENDORID_MARVELL, DEVICEID_MRVL_4381, 231 "Marvell Yukon 88E8059 Gigabit Ethernet" }, 232 { VENDORID_DLINK, DEVICEID_DLINK_DGE550SX, 233 "D-Link 550SX Gigabit Ethernet" }, 234 { VENDORID_DLINK, DEVICEID_DLINK_DGE560SX, 235 "D-Link 560SX Gigabit Ethernet" }, 236 { VENDORID_DLINK, DEVICEID_DLINK_DGE560T, 237 "D-Link 560T Gigabit Ethernet" } 238 }; 239 240 static const char *model_name[] = { 241 "Yukon XL", 242 "Yukon EC Ultra", 243 "Yukon EX", 244 "Yukon EC", 245 "Yukon FE", 246 "Yukon FE+", 247 "Yukon Supreme", 248 "Yukon Ultra 2", 249 "Yukon Unknown", 250 "Yukon Optima", 251 }; 252 253 static int mskc_probe(device_t); 254 static int mskc_attach(device_t); 255 static int mskc_detach(device_t); 256 static int mskc_shutdown(device_t); 257 static int mskc_setup_rambuffer(struct msk_softc *); 258 static int mskc_suspend(device_t); 259 static int mskc_resume(device_t); 260 static bus_dma_tag_t mskc_get_dma_tag(device_t, device_t); 261 static void mskc_reset(struct msk_softc *); 262 263 static int msk_probe(device_t); 264 static int msk_attach(device_t); 265 static int msk_detach(device_t); 266 267 static void msk_tick(void *); 268 static void msk_intr(void *); 269 static void msk_intr_phy(struct msk_if_softc *); 270 static void msk_intr_gmac(struct msk_if_softc *); 271 static __inline void msk_rxput(struct msk_if_softc *); 272 static int msk_handle_events(struct msk_softc *); 273 static void msk_handle_hwerr(struct msk_if_softc *, uint32_t); 274 static void msk_intr_hwerr(struct msk_softc *); 275 #ifndef __NO_STRICT_ALIGNMENT 276 static __inline void msk_fixup_rx(struct mbuf *); 277 #endif 278 static __inline void msk_rxcsum(struct msk_if_softc *, uint32_t, struct mbuf *); 279 static void msk_rxeof(struct msk_if_softc *, uint32_t, uint32_t, int); 280 static void msk_jumbo_rxeof(struct msk_if_softc *, uint32_t, uint32_t, int); 281 static void msk_txeof(struct msk_if_softc *, int); 282 static int msk_encap(struct msk_if_softc *, struct mbuf **); 283 static void msk_start(if_t); 284 static void msk_start_locked(if_t); 285 static int msk_ioctl(if_t, u_long, caddr_t); 286 static void msk_set_prefetch(struct msk_softc *, int, bus_addr_t, uint32_t); 287 static void msk_set_rambuffer(struct msk_if_softc *); 288 static void msk_set_tx_stfwd(struct msk_if_softc *); 289 static void msk_init(void *); 290 static void msk_init_locked(struct msk_if_softc *); 291 static void msk_stop(struct msk_if_softc *); 292 static void msk_watchdog(struct msk_if_softc *); 293 static int msk_mediachange(if_t); 294 static void msk_mediastatus(if_t, struct ifmediareq *); 295 static void msk_phy_power(struct msk_softc *, int); 296 static void msk_dmamap_cb(void *, bus_dma_segment_t *, int, int); 297 static int msk_status_dma_alloc(struct msk_softc *); 298 static void msk_status_dma_free(struct msk_softc *); 299 static int msk_txrx_dma_alloc(struct msk_if_softc *); 300 static int msk_rx_dma_jalloc(struct msk_if_softc *); 301 static void msk_txrx_dma_free(struct msk_if_softc *); 302 static void msk_rx_dma_jfree(struct msk_if_softc *); 303 static int msk_rx_fill(struct msk_if_softc *, int); 304 static int msk_init_rx_ring(struct msk_if_softc *); 305 static int msk_init_jumbo_rx_ring(struct msk_if_softc *); 306 static void msk_init_tx_ring(struct msk_if_softc *); 307 static __inline void msk_discard_rxbuf(struct msk_if_softc *, int); 308 static __inline void msk_discard_jumbo_rxbuf(struct msk_if_softc *, int); 309 static int msk_newbuf(struct msk_if_softc *, int); 310 static int msk_jumbo_newbuf(struct msk_if_softc *, int); 311 312 static int msk_phy_readreg(struct msk_if_softc *, int, int); 313 static int msk_phy_writereg(struct msk_if_softc *, int, int, int); 314 static int msk_miibus_readreg(device_t, int, int); 315 static int msk_miibus_writereg(device_t, int, int, int); 316 static void msk_miibus_statchg(device_t); 317 318 static void msk_rxfilter(struct msk_if_softc *); 319 static void msk_setvlan(struct msk_if_softc *, if_t); 320 321 static void msk_stats_clear(struct msk_if_softc *); 322 static void msk_stats_update(struct msk_if_softc *); 323 static int msk_sysctl_stat32(SYSCTL_HANDLER_ARGS); 324 static int msk_sysctl_stat64(SYSCTL_HANDLER_ARGS); 325 static void msk_sysctl_node(struct msk_if_softc *); 326 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int); 327 static int sysctl_hw_msk_proc_limit(SYSCTL_HANDLER_ARGS); 328 329 static device_method_t mskc_methods[] = { 330 /* Device interface */ 331 DEVMETHOD(device_probe, mskc_probe), 332 DEVMETHOD(device_attach, mskc_attach), 333 DEVMETHOD(device_detach, mskc_detach), 334 DEVMETHOD(device_suspend, mskc_suspend), 335 DEVMETHOD(device_resume, mskc_resume), 336 DEVMETHOD(device_shutdown, mskc_shutdown), 337 338 DEVMETHOD(bus_get_dma_tag, mskc_get_dma_tag), 339 340 DEVMETHOD_END 341 }; 342 343 static driver_t mskc_driver = { 344 "mskc", 345 mskc_methods, 346 sizeof(struct msk_softc) 347 }; 348 349 static device_method_t msk_methods[] = { 350 /* Device interface */ 351 DEVMETHOD(device_probe, msk_probe), 352 DEVMETHOD(device_attach, msk_attach), 353 DEVMETHOD(device_detach, msk_detach), 354 DEVMETHOD(device_shutdown, bus_generic_shutdown), 355 356 /* MII interface */ 357 DEVMETHOD(miibus_readreg, msk_miibus_readreg), 358 DEVMETHOD(miibus_writereg, msk_miibus_writereg), 359 DEVMETHOD(miibus_statchg, msk_miibus_statchg), 360 361 DEVMETHOD_END 362 }; 363 364 static driver_t msk_driver = { 365 "msk", 366 msk_methods, 367 sizeof(struct msk_if_softc) 368 }; 369 370 DRIVER_MODULE(mskc, pci, mskc_driver, NULL, NULL); 371 DRIVER_MODULE(msk, mskc, msk_driver, NULL, NULL); 372 DRIVER_MODULE(miibus, msk, miibus_driver, NULL, NULL); 373 374 static struct resource_spec msk_res_spec_io[] = { 375 { SYS_RES_IOPORT, PCIR_BAR(1), RF_ACTIVE }, 376 { -1, 0, 0 } 377 }; 378 379 static struct resource_spec msk_res_spec_mem[] = { 380 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 381 { -1, 0, 0 } 382 }; 383 384 static struct resource_spec msk_irq_spec_legacy[] = { 385 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 386 { -1, 0, 0 } 387 }; 388 389 static struct resource_spec msk_irq_spec_msi[] = { 390 { SYS_RES_IRQ, 1, RF_ACTIVE }, 391 { -1, 0, 0 } 392 }; 393 394 static int 395 msk_miibus_readreg(device_t dev, int phy, int reg) 396 { 397 struct msk_if_softc *sc_if; 398 399 sc_if = device_get_softc(dev); 400 401 return (msk_phy_readreg(sc_if, phy, reg)); 402 } 403 404 static int 405 msk_phy_readreg(struct msk_if_softc *sc_if, int phy, int reg) 406 { 407 struct msk_softc *sc; 408 int i, val; 409 410 sc = sc_if->msk_softc; 411 412 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SMI_CTRL, 413 GM_SMI_CT_PHY_AD(phy) | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD); 414 415 for (i = 0; i < MSK_TIMEOUT; i++) { 416 DELAY(1); 417 val = GMAC_READ_2(sc, sc_if->msk_port, GM_SMI_CTRL); 418 if ((val & GM_SMI_CT_RD_VAL) != 0) { 419 val = GMAC_READ_2(sc, sc_if->msk_port, GM_SMI_DATA); 420 break; 421 } 422 } 423 424 if (i == MSK_TIMEOUT) { 425 if_printf(sc_if->msk_ifp, "phy failed to come ready\n"); 426 val = 0; 427 } 428 429 return (val); 430 } 431 432 static int 433 msk_miibus_writereg(device_t dev, int phy, int reg, int val) 434 { 435 struct msk_if_softc *sc_if; 436 437 sc_if = device_get_softc(dev); 438 439 return (msk_phy_writereg(sc_if, phy, reg, val)); 440 } 441 442 static int 443 msk_phy_writereg(struct msk_if_softc *sc_if, int phy, int reg, int val) 444 { 445 struct msk_softc *sc; 446 int i; 447 448 sc = sc_if->msk_softc; 449 450 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SMI_DATA, val); 451 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SMI_CTRL, 452 GM_SMI_CT_PHY_AD(phy) | GM_SMI_CT_REG_AD(reg)); 453 for (i = 0; i < MSK_TIMEOUT; i++) { 454 DELAY(1); 455 if ((GMAC_READ_2(sc, sc_if->msk_port, GM_SMI_CTRL) & 456 GM_SMI_CT_BUSY) == 0) 457 break; 458 } 459 if (i == MSK_TIMEOUT) 460 if_printf(sc_if->msk_ifp, "phy write timeout\n"); 461 462 return (0); 463 } 464 465 static void 466 msk_miibus_statchg(device_t dev) 467 { 468 struct msk_softc *sc; 469 struct msk_if_softc *sc_if; 470 struct mii_data *mii; 471 if_t ifp; 472 uint32_t gmac; 473 474 sc_if = device_get_softc(dev); 475 sc = sc_if->msk_softc; 476 477 MSK_IF_LOCK_ASSERT(sc_if); 478 479 mii = device_get_softc(sc_if->msk_miibus); 480 ifp = sc_if->msk_ifp; 481 if (mii == NULL || ifp == NULL || 482 (if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) 483 return; 484 485 sc_if->msk_flags &= ~MSK_FLAG_LINK; 486 if ((mii->mii_media_status & (IFM_AVALID | IFM_ACTIVE)) == 487 (IFM_AVALID | IFM_ACTIVE)) { 488 switch (IFM_SUBTYPE(mii->mii_media_active)) { 489 case IFM_10_T: 490 case IFM_100_TX: 491 sc_if->msk_flags |= MSK_FLAG_LINK; 492 break; 493 case IFM_1000_T: 494 case IFM_1000_SX: 495 case IFM_1000_LX: 496 case IFM_1000_CX: 497 if ((sc_if->msk_flags & MSK_FLAG_FASTETHER) == 0) 498 sc_if->msk_flags |= MSK_FLAG_LINK; 499 break; 500 default: 501 break; 502 } 503 } 504 505 if ((sc_if->msk_flags & MSK_FLAG_LINK) != 0) { 506 /* Enable Tx FIFO Underrun. */ 507 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_MSK), 508 GM_IS_TX_FF_UR | GM_IS_RX_FF_OR); 509 /* 510 * Because mii(4) notify msk(4) that it detected link status 511 * change, there is no need to enable automatic 512 * speed/flow-control/duplex updates. 513 */ 514 gmac = GM_GPCR_AU_ALL_DIS; 515 switch (IFM_SUBTYPE(mii->mii_media_active)) { 516 case IFM_1000_SX: 517 case IFM_1000_T: 518 gmac |= GM_GPCR_SPEED_1000; 519 break; 520 case IFM_100_TX: 521 gmac |= GM_GPCR_SPEED_100; 522 break; 523 case IFM_10_T: 524 break; 525 } 526 527 if ((IFM_OPTIONS(mii->mii_media_active) & 528 IFM_ETH_RXPAUSE) == 0) 529 gmac |= GM_GPCR_FC_RX_DIS; 530 if ((IFM_OPTIONS(mii->mii_media_active) & 531 IFM_ETH_TXPAUSE) == 0) 532 gmac |= GM_GPCR_FC_TX_DIS; 533 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) 534 gmac |= GM_GPCR_DUP_FULL; 535 else 536 gmac |= GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS; 537 gmac |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA; 538 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, gmac); 539 /* Read again to ensure writing. */ 540 GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL); 541 gmac = GMC_PAUSE_OFF; 542 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 543 if ((IFM_OPTIONS(mii->mii_media_active) & 544 IFM_ETH_RXPAUSE) != 0) 545 gmac = GMC_PAUSE_ON; 546 } 547 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), gmac); 548 549 /* Enable PHY interrupt for FIFO underrun/overflow. */ 550 msk_phy_writereg(sc_if, PHY_ADDR_MARV, 551 PHY_MARV_INT_MASK, PHY_M_IS_FIFO_ERROR); 552 } else { 553 /* 554 * Link state changed to down. 555 * Disable PHY interrupts. 556 */ 557 msk_phy_writereg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_MASK, 0); 558 /* Disable Rx/Tx MAC. */ 559 gmac = GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL); 560 if ((gmac & (GM_GPCR_RX_ENA | GM_GPCR_TX_ENA)) != 0) { 561 gmac &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA); 562 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, gmac); 563 /* Read again to ensure writing. */ 564 GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL); 565 } 566 } 567 } 568 569 static u_int 570 msk_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) 571 { 572 uint32_t *mchash = arg; 573 uint32_t crc; 574 575 crc = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN); 576 /* Just want the 6 least significant bits. */ 577 crc &= 0x3f; 578 /* Set the corresponding bit in the hash table. */ 579 mchash[crc >> 5] |= 1 << (crc & 0x1f); 580 581 return (1); 582 } 583 584 static void 585 msk_rxfilter(struct msk_if_softc *sc_if) 586 { 587 struct msk_softc *sc; 588 if_t ifp; 589 uint32_t mchash[2]; 590 uint16_t mode; 591 592 sc = sc_if->msk_softc; 593 594 MSK_IF_LOCK_ASSERT(sc_if); 595 596 ifp = sc_if->msk_ifp; 597 598 bzero(mchash, sizeof(mchash)); 599 mode = GMAC_READ_2(sc, sc_if->msk_port, GM_RX_CTRL); 600 if ((if_getflags(ifp) & IFF_PROMISC) != 0) 601 mode &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA); 602 else if ((if_getflags(ifp) & IFF_ALLMULTI) != 0) { 603 mode |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA; 604 mchash[0] = 0xffff; 605 mchash[1] = 0xffff; 606 } else { 607 mode |= GM_RXCR_UCF_ENA; 608 if_foreach_llmaddr(ifp, msk_hash_maddr, mchash); 609 if (mchash[0] != 0 || mchash[1] != 0) 610 mode |= GM_RXCR_MCF_ENA; 611 } 612 613 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H1, 614 mchash[0] & 0xffff); 615 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H2, 616 (mchash[0] >> 16) & 0xffff); 617 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H3, 618 mchash[1] & 0xffff); 619 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H4, 620 (mchash[1] >> 16) & 0xffff); 621 GMAC_WRITE_2(sc, sc_if->msk_port, GM_RX_CTRL, mode); 622 } 623 624 static void 625 msk_setvlan(struct msk_if_softc *sc_if, if_t ifp) 626 { 627 struct msk_softc *sc; 628 629 sc = sc_if->msk_softc; 630 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0) { 631 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), 632 RX_VLAN_STRIP_ON); 633 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 634 TX_VLAN_TAG_ON); 635 } else { 636 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), 637 RX_VLAN_STRIP_OFF); 638 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 639 TX_VLAN_TAG_OFF); 640 } 641 } 642 643 static int 644 msk_rx_fill(struct msk_if_softc *sc_if, int jumbo) 645 { 646 uint16_t idx; 647 int i; 648 649 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0 && 650 (if_getcapenable(sc_if->msk_ifp) & IFCAP_RXCSUM) != 0) { 651 /* Wait until controller executes OP_TCPSTART command. */ 652 for (i = 100; i > 0; i--) { 653 DELAY(100); 654 idx = CSR_READ_2(sc_if->msk_softc, 655 Y2_PREF_Q_ADDR(sc_if->msk_rxq, 656 PREF_UNIT_GET_IDX_REG)); 657 if (idx != 0) 658 break; 659 } 660 if (i == 0) { 661 device_printf(sc_if->msk_if_dev, 662 "prefetch unit stuck?\n"); 663 return (ETIMEDOUT); 664 } 665 /* 666 * Fill consumed LE with free buffer. This can be done 667 * in Rx handler but we don't want to add special code 668 * in fast handler. 669 */ 670 if (jumbo > 0) { 671 if (msk_jumbo_newbuf(sc_if, 0) != 0) 672 return (ENOBUFS); 673 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 674 sc_if->msk_cdata.msk_jumbo_rx_ring_map, 675 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 676 } else { 677 if (msk_newbuf(sc_if, 0) != 0) 678 return (ENOBUFS); 679 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_ring_tag, 680 sc_if->msk_cdata.msk_rx_ring_map, 681 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 682 } 683 sc_if->msk_cdata.msk_rx_prod = 0; 684 CSR_WRITE_2(sc_if->msk_softc, 685 Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_PUT_IDX_REG), 686 sc_if->msk_cdata.msk_rx_prod); 687 } 688 return (0); 689 } 690 691 static int 692 msk_init_rx_ring(struct msk_if_softc *sc_if) 693 { 694 struct msk_ring_data *rd; 695 struct msk_rxdesc *rxd; 696 int i, nbuf, prod; 697 698 MSK_IF_LOCK_ASSERT(sc_if); 699 700 sc_if->msk_cdata.msk_rx_cons = 0; 701 sc_if->msk_cdata.msk_rx_prod = 0; 702 sc_if->msk_cdata.msk_rx_putwm = MSK_PUT_WM; 703 704 rd = &sc_if->msk_rdata; 705 bzero(rd->msk_rx_ring, sizeof(struct msk_rx_desc) * MSK_RX_RING_CNT); 706 for (i = prod = 0; i < MSK_RX_RING_CNT; i++) { 707 rxd = &sc_if->msk_cdata.msk_rxdesc[prod]; 708 rxd->rx_m = NULL; 709 rxd->rx_le = &rd->msk_rx_ring[prod]; 710 MSK_INC(prod, MSK_RX_RING_CNT); 711 } 712 nbuf = MSK_RX_BUF_CNT; 713 prod = 0; 714 /* Have controller know how to compute Rx checksum. */ 715 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0 && 716 (if_getcapenable(sc_if->msk_ifp) & IFCAP_RXCSUM) != 0) { 717 #ifdef MSK_64BIT_DMA 718 rxd = &sc_if->msk_cdata.msk_rxdesc[prod]; 719 rxd->rx_m = NULL; 720 rxd->rx_le = &rd->msk_rx_ring[prod]; 721 rxd->rx_le->msk_addr = htole32(ETHER_HDR_LEN << 16 | 722 ETHER_HDR_LEN); 723 rxd->rx_le->msk_control = htole32(OP_TCPSTART | HW_OWNER); 724 MSK_INC(prod, MSK_RX_RING_CNT); 725 MSK_INC(sc_if->msk_cdata.msk_rx_cons, MSK_RX_RING_CNT); 726 #endif 727 rxd = &sc_if->msk_cdata.msk_rxdesc[prod]; 728 rxd->rx_m = NULL; 729 rxd->rx_le = &rd->msk_rx_ring[prod]; 730 rxd->rx_le->msk_addr = htole32(ETHER_HDR_LEN << 16 | 731 ETHER_HDR_LEN); 732 rxd->rx_le->msk_control = htole32(OP_TCPSTART | HW_OWNER); 733 MSK_INC(prod, MSK_RX_RING_CNT); 734 MSK_INC(sc_if->msk_cdata.msk_rx_cons, MSK_RX_RING_CNT); 735 nbuf--; 736 } 737 for (i = 0; i < nbuf; i++) { 738 if (msk_newbuf(sc_if, prod) != 0) 739 return (ENOBUFS); 740 MSK_RX_INC(prod, MSK_RX_RING_CNT); 741 } 742 743 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_ring_tag, 744 sc_if->msk_cdata.msk_rx_ring_map, 745 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 746 747 /* Update prefetch unit. */ 748 sc_if->msk_cdata.msk_rx_prod = prod; 749 CSR_WRITE_2(sc_if->msk_softc, 750 Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_PUT_IDX_REG), 751 (sc_if->msk_cdata.msk_rx_prod + MSK_RX_RING_CNT - 1) % 752 MSK_RX_RING_CNT); 753 if (msk_rx_fill(sc_if, 0) != 0) 754 return (ENOBUFS); 755 return (0); 756 } 757 758 static int 759 msk_init_jumbo_rx_ring(struct msk_if_softc *sc_if) 760 { 761 struct msk_ring_data *rd; 762 struct msk_rxdesc *rxd; 763 int i, nbuf, prod; 764 765 MSK_IF_LOCK_ASSERT(sc_if); 766 767 sc_if->msk_cdata.msk_rx_cons = 0; 768 sc_if->msk_cdata.msk_rx_prod = 0; 769 sc_if->msk_cdata.msk_rx_putwm = MSK_PUT_WM; 770 771 rd = &sc_if->msk_rdata; 772 bzero(rd->msk_jumbo_rx_ring, 773 sizeof(struct msk_rx_desc) * MSK_JUMBO_RX_RING_CNT); 774 for (i = prod = 0; i < MSK_JUMBO_RX_RING_CNT; i++) { 775 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[prod]; 776 rxd->rx_m = NULL; 777 rxd->rx_le = &rd->msk_jumbo_rx_ring[prod]; 778 MSK_INC(prod, MSK_JUMBO_RX_RING_CNT); 779 } 780 nbuf = MSK_RX_BUF_CNT; 781 prod = 0; 782 /* Have controller know how to compute Rx checksum. */ 783 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0 && 784 (if_getcapenable(sc_if->msk_ifp) & IFCAP_RXCSUM) != 0) { 785 #ifdef MSK_64BIT_DMA 786 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[prod]; 787 rxd->rx_m = NULL; 788 rxd->rx_le = &rd->msk_jumbo_rx_ring[prod]; 789 rxd->rx_le->msk_addr = htole32(ETHER_HDR_LEN << 16 | 790 ETHER_HDR_LEN); 791 rxd->rx_le->msk_control = htole32(OP_TCPSTART | HW_OWNER); 792 MSK_INC(prod, MSK_JUMBO_RX_RING_CNT); 793 MSK_INC(sc_if->msk_cdata.msk_rx_cons, MSK_JUMBO_RX_RING_CNT); 794 #endif 795 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[prod]; 796 rxd->rx_m = NULL; 797 rxd->rx_le = &rd->msk_jumbo_rx_ring[prod]; 798 rxd->rx_le->msk_addr = htole32(ETHER_HDR_LEN << 16 | 799 ETHER_HDR_LEN); 800 rxd->rx_le->msk_control = htole32(OP_TCPSTART | HW_OWNER); 801 MSK_INC(prod, MSK_JUMBO_RX_RING_CNT); 802 MSK_INC(sc_if->msk_cdata.msk_rx_cons, MSK_JUMBO_RX_RING_CNT); 803 nbuf--; 804 } 805 for (i = 0; i < nbuf; i++) { 806 if (msk_jumbo_newbuf(sc_if, prod) != 0) 807 return (ENOBUFS); 808 MSK_RX_INC(prod, MSK_JUMBO_RX_RING_CNT); 809 } 810 811 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 812 sc_if->msk_cdata.msk_jumbo_rx_ring_map, 813 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 814 815 /* Update prefetch unit. */ 816 sc_if->msk_cdata.msk_rx_prod = prod; 817 CSR_WRITE_2(sc_if->msk_softc, 818 Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_PUT_IDX_REG), 819 (sc_if->msk_cdata.msk_rx_prod + MSK_JUMBO_RX_RING_CNT - 1) % 820 MSK_JUMBO_RX_RING_CNT); 821 if (msk_rx_fill(sc_if, 1) != 0) 822 return (ENOBUFS); 823 return (0); 824 } 825 826 static void 827 msk_init_tx_ring(struct msk_if_softc *sc_if) 828 { 829 struct msk_ring_data *rd; 830 struct msk_txdesc *txd; 831 int i; 832 833 sc_if->msk_cdata.msk_tso_mtu = 0; 834 sc_if->msk_cdata.msk_last_csum = 0; 835 sc_if->msk_cdata.msk_tx_prod = 0; 836 sc_if->msk_cdata.msk_tx_cons = 0; 837 sc_if->msk_cdata.msk_tx_cnt = 0; 838 sc_if->msk_cdata.msk_tx_high_addr = 0; 839 840 rd = &sc_if->msk_rdata; 841 bzero(rd->msk_tx_ring, sizeof(struct msk_tx_desc) * MSK_TX_RING_CNT); 842 for (i = 0; i < MSK_TX_RING_CNT; i++) { 843 txd = &sc_if->msk_cdata.msk_txdesc[i]; 844 txd->tx_m = NULL; 845 txd->tx_le = &rd->msk_tx_ring[i]; 846 } 847 848 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_ring_tag, 849 sc_if->msk_cdata.msk_tx_ring_map, 850 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 851 } 852 853 static __inline void 854 msk_discard_rxbuf(struct msk_if_softc *sc_if, int idx) 855 { 856 struct msk_rx_desc *rx_le; 857 struct msk_rxdesc *rxd; 858 struct mbuf *m; 859 860 #ifdef MSK_64BIT_DMA 861 rxd = &sc_if->msk_cdata.msk_rxdesc[idx]; 862 rx_le = rxd->rx_le; 863 rx_le->msk_control = htole32(OP_ADDR64 | HW_OWNER); 864 MSK_INC(idx, MSK_RX_RING_CNT); 865 #endif 866 rxd = &sc_if->msk_cdata.msk_rxdesc[idx]; 867 m = rxd->rx_m; 868 rx_le = rxd->rx_le; 869 rx_le->msk_control = htole32(m->m_len | OP_PACKET | HW_OWNER); 870 } 871 872 static __inline void 873 msk_discard_jumbo_rxbuf(struct msk_if_softc *sc_if, int idx) 874 { 875 struct msk_rx_desc *rx_le; 876 struct msk_rxdesc *rxd; 877 struct mbuf *m; 878 879 #ifdef MSK_64BIT_DMA 880 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[idx]; 881 rx_le = rxd->rx_le; 882 rx_le->msk_control = htole32(OP_ADDR64 | HW_OWNER); 883 MSK_INC(idx, MSK_JUMBO_RX_RING_CNT); 884 #endif 885 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[idx]; 886 m = rxd->rx_m; 887 rx_le = rxd->rx_le; 888 rx_le->msk_control = htole32(m->m_len | OP_PACKET | HW_OWNER); 889 } 890 891 static int 892 msk_newbuf(struct msk_if_softc *sc_if, int idx) 893 { 894 struct msk_rx_desc *rx_le; 895 struct msk_rxdesc *rxd; 896 struct mbuf *m; 897 bus_dma_segment_t segs[1]; 898 bus_dmamap_t map; 899 int nsegs; 900 901 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 902 if (m == NULL) 903 return (ENOBUFS); 904 905 m->m_len = m->m_pkthdr.len = MCLBYTES; 906 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) == 0) 907 m_adj(m, ETHER_ALIGN); 908 #ifndef __NO_STRICT_ALIGNMENT 909 else 910 m_adj(m, MSK_RX_BUF_ALIGN); 911 #endif 912 913 if (bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_rx_tag, 914 sc_if->msk_cdata.msk_rx_sparemap, m, segs, &nsegs, 915 BUS_DMA_NOWAIT) != 0) { 916 m_freem(m); 917 return (ENOBUFS); 918 } 919 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 920 921 rxd = &sc_if->msk_cdata.msk_rxdesc[idx]; 922 #ifdef MSK_64BIT_DMA 923 rx_le = rxd->rx_le; 924 rx_le->msk_addr = htole32(MSK_ADDR_HI(segs[0].ds_addr)); 925 rx_le->msk_control = htole32(OP_ADDR64 | HW_OWNER); 926 MSK_INC(idx, MSK_RX_RING_CNT); 927 rxd = &sc_if->msk_cdata.msk_rxdesc[idx]; 928 #endif 929 if (rxd->rx_m != NULL) { 930 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_tag, rxd->rx_dmamap, 931 BUS_DMASYNC_POSTREAD); 932 bus_dmamap_unload(sc_if->msk_cdata.msk_rx_tag, rxd->rx_dmamap); 933 rxd->rx_m = NULL; 934 } 935 map = rxd->rx_dmamap; 936 rxd->rx_dmamap = sc_if->msk_cdata.msk_rx_sparemap; 937 sc_if->msk_cdata.msk_rx_sparemap = map; 938 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_tag, rxd->rx_dmamap, 939 BUS_DMASYNC_PREREAD); 940 rxd->rx_m = m; 941 rx_le = rxd->rx_le; 942 rx_le->msk_addr = htole32(MSK_ADDR_LO(segs[0].ds_addr)); 943 rx_le->msk_control = 944 htole32(segs[0].ds_len | OP_PACKET | HW_OWNER); 945 946 return (0); 947 } 948 949 static int 950 msk_jumbo_newbuf(struct msk_if_softc *sc_if, int idx) 951 { 952 struct msk_rx_desc *rx_le; 953 struct msk_rxdesc *rxd; 954 struct mbuf *m; 955 bus_dma_segment_t segs[1]; 956 bus_dmamap_t map; 957 int nsegs; 958 959 m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES); 960 if (m == NULL) 961 return (ENOBUFS); 962 m->m_len = m->m_pkthdr.len = MJUM9BYTES; 963 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) == 0) 964 m_adj(m, ETHER_ALIGN); 965 #ifndef __NO_STRICT_ALIGNMENT 966 else 967 m_adj(m, MSK_RX_BUF_ALIGN); 968 #endif 969 970 if (bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_jumbo_rx_tag, 971 sc_if->msk_cdata.msk_jumbo_rx_sparemap, m, segs, &nsegs, 972 BUS_DMA_NOWAIT) != 0) { 973 m_freem(m); 974 return (ENOBUFS); 975 } 976 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 977 978 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[idx]; 979 #ifdef MSK_64BIT_DMA 980 rx_le = rxd->rx_le; 981 rx_le->msk_addr = htole32(MSK_ADDR_HI(segs[0].ds_addr)); 982 rx_le->msk_control = htole32(OP_ADDR64 | HW_OWNER); 983 MSK_INC(idx, MSK_JUMBO_RX_RING_CNT); 984 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[idx]; 985 #endif 986 if (rxd->rx_m != NULL) { 987 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_tag, 988 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 989 bus_dmamap_unload(sc_if->msk_cdata.msk_jumbo_rx_tag, 990 rxd->rx_dmamap); 991 rxd->rx_m = NULL; 992 } 993 map = rxd->rx_dmamap; 994 rxd->rx_dmamap = sc_if->msk_cdata.msk_jumbo_rx_sparemap; 995 sc_if->msk_cdata.msk_jumbo_rx_sparemap = map; 996 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_tag, rxd->rx_dmamap, 997 BUS_DMASYNC_PREREAD); 998 rxd->rx_m = m; 999 rx_le = rxd->rx_le; 1000 rx_le->msk_addr = htole32(MSK_ADDR_LO(segs[0].ds_addr)); 1001 rx_le->msk_control = 1002 htole32(segs[0].ds_len | OP_PACKET | HW_OWNER); 1003 1004 return (0); 1005 } 1006 1007 /* 1008 * Set media options. 1009 */ 1010 static int 1011 msk_mediachange(if_t ifp) 1012 { 1013 struct msk_if_softc *sc_if; 1014 struct mii_data *mii; 1015 int error; 1016 1017 sc_if = if_getsoftc(ifp); 1018 1019 MSK_IF_LOCK(sc_if); 1020 mii = device_get_softc(sc_if->msk_miibus); 1021 error = mii_mediachg(mii); 1022 MSK_IF_UNLOCK(sc_if); 1023 1024 return (error); 1025 } 1026 1027 /* 1028 * Report current media status. 1029 */ 1030 static void 1031 msk_mediastatus(if_t ifp, struct ifmediareq *ifmr) 1032 { 1033 struct msk_if_softc *sc_if; 1034 struct mii_data *mii; 1035 1036 sc_if = if_getsoftc(ifp); 1037 MSK_IF_LOCK(sc_if); 1038 if ((if_getflags(ifp) & IFF_UP) == 0) { 1039 MSK_IF_UNLOCK(sc_if); 1040 return; 1041 } 1042 mii = device_get_softc(sc_if->msk_miibus); 1043 1044 mii_pollstat(mii); 1045 ifmr->ifm_active = mii->mii_media_active; 1046 ifmr->ifm_status = mii->mii_media_status; 1047 MSK_IF_UNLOCK(sc_if); 1048 } 1049 1050 static int 1051 msk_ioctl(if_t ifp, u_long command, caddr_t data) 1052 { 1053 struct msk_if_softc *sc_if; 1054 struct ifreq *ifr; 1055 struct mii_data *mii; 1056 int error, mask, reinit; 1057 1058 sc_if = if_getsoftc(ifp); 1059 ifr = (struct ifreq *)data; 1060 error = 0; 1061 1062 switch(command) { 1063 case SIOCSIFMTU: 1064 MSK_IF_LOCK(sc_if); 1065 if (ifr->ifr_mtu > MSK_JUMBO_MTU || ifr->ifr_mtu < ETHERMIN) 1066 error = EINVAL; 1067 else if (if_getmtu(ifp) != ifr->ifr_mtu) { 1068 if (ifr->ifr_mtu > ETHERMTU) { 1069 if ((sc_if->msk_flags & MSK_FLAG_JUMBO) == 0) { 1070 error = EINVAL; 1071 MSK_IF_UNLOCK(sc_if); 1072 break; 1073 } 1074 if ((sc_if->msk_flags & 1075 MSK_FLAG_JUMBO_NOCSUM) != 0) { 1076 if_sethwassistbits(ifp, 0, 1077 MSK_CSUM_FEATURES | CSUM_TSO); 1078 if_setcapenablebit(ifp, 0, 1079 IFCAP_TSO4 | IFCAP_TXCSUM); 1080 VLAN_CAPABILITIES(ifp); 1081 } 1082 } 1083 if_setmtu(ifp, ifr->ifr_mtu); 1084 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 1085 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 1086 msk_init_locked(sc_if); 1087 } 1088 } 1089 MSK_IF_UNLOCK(sc_if); 1090 break; 1091 case SIOCSIFFLAGS: 1092 MSK_IF_LOCK(sc_if); 1093 if ((if_getflags(ifp) & IFF_UP) != 0) { 1094 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0 && 1095 ((if_getflags(ifp) ^ sc_if->msk_if_flags) & 1096 (IFF_PROMISC | IFF_ALLMULTI)) != 0) 1097 msk_rxfilter(sc_if); 1098 else if ((sc_if->msk_flags & MSK_FLAG_DETACH) == 0) 1099 msk_init_locked(sc_if); 1100 } else if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 1101 msk_stop(sc_if); 1102 sc_if->msk_if_flags = if_getflags(ifp); 1103 MSK_IF_UNLOCK(sc_if); 1104 break; 1105 case SIOCADDMULTI: 1106 case SIOCDELMULTI: 1107 MSK_IF_LOCK(sc_if); 1108 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 1109 msk_rxfilter(sc_if); 1110 MSK_IF_UNLOCK(sc_if); 1111 break; 1112 case SIOCGIFMEDIA: 1113 case SIOCSIFMEDIA: 1114 mii = device_get_softc(sc_if->msk_miibus); 1115 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1116 break; 1117 case SIOCSIFCAP: 1118 reinit = 0; 1119 MSK_IF_LOCK(sc_if); 1120 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp); 1121 if ((mask & IFCAP_TXCSUM) != 0 && 1122 (IFCAP_TXCSUM & if_getcapabilities(ifp)) != 0) { 1123 if_togglecapenable(ifp, IFCAP_TXCSUM); 1124 if ((IFCAP_TXCSUM & if_getcapenable(ifp)) != 0) 1125 if_sethwassistbits(ifp, MSK_CSUM_FEATURES, 0); 1126 else 1127 if_sethwassistbits(ifp, 0, MSK_CSUM_FEATURES); 1128 } 1129 if ((mask & IFCAP_RXCSUM) != 0 && 1130 (IFCAP_RXCSUM & if_getcapabilities(ifp)) != 0) { 1131 if_togglecapenable(ifp, IFCAP_RXCSUM); 1132 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0) 1133 reinit = 1; 1134 } 1135 if ((mask & IFCAP_VLAN_HWCSUM) != 0 && 1136 (IFCAP_VLAN_HWCSUM & if_getcapabilities(ifp)) != 0) 1137 if_togglecapenable(ifp, IFCAP_VLAN_HWCSUM); 1138 if ((mask & IFCAP_TSO4) != 0 && 1139 (IFCAP_TSO4 & if_getcapabilities(ifp)) != 0) { 1140 if_togglecapenable(ifp, IFCAP_TSO4); 1141 if ((IFCAP_TSO4 & if_getcapenable(ifp)) != 0) 1142 if_sethwassistbits(ifp, CSUM_TSO, 0); 1143 else 1144 if_sethwassistbits(ifp, 0, CSUM_TSO); 1145 } 1146 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 1147 (IFCAP_VLAN_HWTSO & if_getcapabilities(ifp)) != 0) 1148 if_togglecapenable(ifp, IFCAP_VLAN_HWTSO); 1149 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 1150 (IFCAP_VLAN_HWTAGGING & if_getcapabilities(ifp)) != 0) { 1151 if_togglecapenable(ifp, IFCAP_VLAN_HWTAGGING); 1152 if ((IFCAP_VLAN_HWTAGGING & if_getcapenable(ifp)) == 0) 1153 if_setcapenablebit(ifp, 0, 1154 IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM); 1155 msk_setvlan(sc_if, ifp); 1156 } 1157 if (if_getmtu(ifp) > ETHERMTU && 1158 (sc_if->msk_flags & MSK_FLAG_JUMBO_NOCSUM) != 0) { 1159 if_sethwassistbits(ifp, 0, (MSK_CSUM_FEATURES | CSUM_TSO)); 1160 if_setcapenablebit(ifp, 0, (IFCAP_TSO4 | IFCAP_TXCSUM)); 1161 } 1162 VLAN_CAPABILITIES(ifp); 1163 if (reinit > 0 && (if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 1164 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 1165 msk_init_locked(sc_if); 1166 } 1167 MSK_IF_UNLOCK(sc_if); 1168 break; 1169 default: 1170 error = ether_ioctl(ifp, command, data); 1171 break; 1172 } 1173 1174 return (error); 1175 } 1176 1177 static int 1178 mskc_probe(device_t dev) 1179 { 1180 const struct msk_product *mp; 1181 uint16_t vendor, devid; 1182 int i; 1183 1184 vendor = pci_get_vendor(dev); 1185 devid = pci_get_device(dev); 1186 mp = msk_products; 1187 for (i = 0; i < nitems(msk_products); i++, mp++) { 1188 if (vendor == mp->msk_vendorid && devid == mp->msk_deviceid) { 1189 device_set_desc(dev, mp->msk_name); 1190 return (BUS_PROBE_DEFAULT); 1191 } 1192 } 1193 1194 return (ENXIO); 1195 } 1196 1197 static int 1198 mskc_setup_rambuffer(struct msk_softc *sc) 1199 { 1200 int next; 1201 int i; 1202 1203 /* Get adapter SRAM size. */ 1204 sc->msk_ramsize = CSR_READ_1(sc, B2_E_0) * 4; 1205 if (bootverbose) 1206 device_printf(sc->msk_dev, 1207 "RAM buffer size : %dKB\n", sc->msk_ramsize); 1208 if (sc->msk_ramsize == 0) 1209 return (0); 1210 1211 sc->msk_pflags |= MSK_FLAG_RAMBUF; 1212 /* 1213 * Give receiver 2/3 of memory and round down to the multiple 1214 * of 1024. Tx/Rx RAM buffer size of Yukon II should be multiple 1215 * of 1024. 1216 */ 1217 sc->msk_rxqsize = rounddown((sc->msk_ramsize * 1024 * 2) / 3, 1024); 1218 sc->msk_txqsize = (sc->msk_ramsize * 1024) - sc->msk_rxqsize; 1219 for (i = 0, next = 0; i < sc->msk_num_port; i++) { 1220 sc->msk_rxqstart[i] = next; 1221 sc->msk_rxqend[i] = next + sc->msk_rxqsize - 1; 1222 next = sc->msk_rxqend[i] + 1; 1223 sc->msk_txqstart[i] = next; 1224 sc->msk_txqend[i] = next + sc->msk_txqsize - 1; 1225 next = sc->msk_txqend[i] + 1; 1226 if (bootverbose) { 1227 device_printf(sc->msk_dev, 1228 "Port %d : Rx Queue %dKB(0x%08x:0x%08x)\n", i, 1229 sc->msk_rxqsize / 1024, sc->msk_rxqstart[i], 1230 sc->msk_rxqend[i]); 1231 device_printf(sc->msk_dev, 1232 "Port %d : Tx Queue %dKB(0x%08x:0x%08x)\n", i, 1233 sc->msk_txqsize / 1024, sc->msk_txqstart[i], 1234 sc->msk_txqend[i]); 1235 } 1236 } 1237 1238 return (0); 1239 } 1240 1241 static void 1242 msk_phy_power(struct msk_softc *sc, int mode) 1243 { 1244 uint32_t our, val; 1245 int i; 1246 1247 switch (mode) { 1248 case MSK_PHY_POWERUP: 1249 /* Switch power to VCC (WA for VAUX problem). */ 1250 CSR_WRITE_1(sc, B0_POWER_CTRL, 1251 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON); 1252 /* Disable Core Clock Division, set Clock Select to 0. */ 1253 CSR_WRITE_4(sc, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS); 1254 1255 val = 0; 1256 if (sc->msk_hw_id == CHIP_ID_YUKON_XL && 1257 sc->msk_hw_rev > CHIP_REV_YU_XL_A1) { 1258 /* Enable bits are inverted. */ 1259 val = Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS | 1260 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS | 1261 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS; 1262 } 1263 /* 1264 * Enable PCI & Core Clock, enable clock gating for both Links. 1265 */ 1266 CSR_WRITE_1(sc, B2_Y2_CLK_GATE, val); 1267 1268 our = CSR_PCI_READ_4(sc, PCI_OUR_REG_1); 1269 our &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD); 1270 if (sc->msk_hw_id == CHIP_ID_YUKON_XL) { 1271 if (sc->msk_hw_rev > CHIP_REV_YU_XL_A1) { 1272 /* Deassert Low Power for 1st PHY. */ 1273 our |= PCI_Y2_PHY1_COMA; 1274 if (sc->msk_num_port > 1) 1275 our |= PCI_Y2_PHY2_COMA; 1276 } 1277 } 1278 if (sc->msk_hw_id == CHIP_ID_YUKON_EC_U || 1279 sc->msk_hw_id == CHIP_ID_YUKON_EX || 1280 sc->msk_hw_id >= CHIP_ID_YUKON_FE_P) { 1281 val = CSR_PCI_READ_4(sc, PCI_OUR_REG_4); 1282 val &= (PCI_FORCE_ASPM_REQUEST | 1283 PCI_ASPM_GPHY_LINK_DOWN | PCI_ASPM_INT_FIFO_EMPTY | 1284 PCI_ASPM_CLKRUN_REQUEST); 1285 /* Set all bits to 0 except bits 15..12. */ 1286 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_4, val); 1287 val = CSR_PCI_READ_4(sc, PCI_OUR_REG_5); 1288 val &= PCI_CTL_TIM_VMAIN_AV_MSK; 1289 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_5, val); 1290 CSR_PCI_WRITE_4(sc, PCI_CFG_REG_1, 0); 1291 CSR_WRITE_2(sc, B0_CTST, Y2_HW_WOL_ON); 1292 /* 1293 * Disable status race, workaround for 1294 * Yukon EC Ultra & Yukon EX. 1295 */ 1296 val = CSR_READ_4(sc, B2_GP_IO); 1297 val |= GLB_GPIO_STAT_RACE_DIS; 1298 CSR_WRITE_4(sc, B2_GP_IO, val); 1299 CSR_READ_4(sc, B2_GP_IO); 1300 } 1301 /* Release PHY from PowerDown/COMA mode. */ 1302 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_1, our); 1303 1304 for (i = 0; i < sc->msk_num_port; i++) { 1305 CSR_WRITE_2(sc, MR_ADDR(i, GMAC_LINK_CTRL), 1306 GMLC_RST_SET); 1307 CSR_WRITE_2(sc, MR_ADDR(i, GMAC_LINK_CTRL), 1308 GMLC_RST_CLR); 1309 } 1310 break; 1311 case MSK_PHY_POWERDOWN: 1312 val = CSR_PCI_READ_4(sc, PCI_OUR_REG_1); 1313 val |= PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD; 1314 if (sc->msk_hw_id == CHIP_ID_YUKON_XL && 1315 sc->msk_hw_rev > CHIP_REV_YU_XL_A1) { 1316 val &= ~PCI_Y2_PHY1_COMA; 1317 if (sc->msk_num_port > 1) 1318 val &= ~PCI_Y2_PHY2_COMA; 1319 } 1320 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_1, val); 1321 1322 val = Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS | 1323 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS | 1324 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS; 1325 if (sc->msk_hw_id == CHIP_ID_YUKON_XL && 1326 sc->msk_hw_rev > CHIP_REV_YU_XL_A1) { 1327 /* Enable bits are inverted. */ 1328 val = 0; 1329 } 1330 /* 1331 * Disable PCI & Core Clock, disable clock gating for 1332 * both Links. 1333 */ 1334 CSR_WRITE_1(sc, B2_Y2_CLK_GATE, val); 1335 CSR_WRITE_1(sc, B0_POWER_CTRL, 1336 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_ON | PC_VCC_OFF); 1337 break; 1338 default: 1339 break; 1340 } 1341 } 1342 1343 static void 1344 mskc_reset(struct msk_softc *sc) 1345 { 1346 bus_addr_t addr; 1347 uint16_t status; 1348 uint32_t val; 1349 int i, initram; 1350 1351 /* Disable ASF. */ 1352 if (sc->msk_hw_id >= CHIP_ID_YUKON_XL && 1353 sc->msk_hw_id <= CHIP_ID_YUKON_SUPR) { 1354 if (sc->msk_hw_id == CHIP_ID_YUKON_EX || 1355 sc->msk_hw_id == CHIP_ID_YUKON_SUPR) { 1356 CSR_WRITE_4(sc, B28_Y2_CPU_WDOG, 0); 1357 status = CSR_READ_2(sc, B28_Y2_ASF_HCU_CCSR); 1358 /* Clear AHB bridge & microcontroller reset. */ 1359 status &= ~(Y2_ASF_HCU_CCSR_AHB_RST | 1360 Y2_ASF_HCU_CCSR_CPU_RST_MODE); 1361 /* Clear ASF microcontroller state. */ 1362 status &= ~Y2_ASF_HCU_CCSR_UC_STATE_MSK; 1363 status &= ~Y2_ASF_HCU_CCSR_CPU_CLK_DIVIDE_MSK; 1364 CSR_WRITE_2(sc, B28_Y2_ASF_HCU_CCSR, status); 1365 CSR_WRITE_4(sc, B28_Y2_CPU_WDOG, 0); 1366 } else 1367 CSR_WRITE_1(sc, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET); 1368 CSR_WRITE_2(sc, B0_CTST, Y2_ASF_DISABLE); 1369 /* 1370 * Since we disabled ASF, S/W reset is required for 1371 * Power Management. 1372 */ 1373 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); 1374 CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR); 1375 } 1376 1377 /* Clear all error bits in the PCI status register. */ 1378 status = pci_read_config(sc->msk_dev, PCIR_STATUS, 2); 1379 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON); 1380 1381 pci_write_config(sc->msk_dev, PCIR_STATUS, status | 1382 PCIM_STATUS_PERR | PCIM_STATUS_SERR | PCIM_STATUS_RMABORT | 1383 PCIM_STATUS_RTABORT | PCIM_STATUS_MDPERR, 2); 1384 CSR_WRITE_2(sc, B0_CTST, CS_MRST_CLR); 1385 1386 switch (sc->msk_bustype) { 1387 case MSK_PEX_BUS: 1388 /* Clear all PEX errors. */ 1389 CSR_PCI_WRITE_4(sc, PEX_UNC_ERR_STAT, 0xffffffff); 1390 val = CSR_PCI_READ_4(sc, PEX_UNC_ERR_STAT); 1391 if ((val & PEX_RX_OV) != 0) { 1392 sc->msk_intrmask &= ~Y2_IS_HW_ERR; 1393 sc->msk_intrhwemask &= ~Y2_IS_PCI_EXP; 1394 } 1395 break; 1396 case MSK_PCI_BUS: 1397 case MSK_PCIX_BUS: 1398 /* Set Cache Line Size to 2(8bytes) if configured to 0. */ 1399 val = pci_read_config(sc->msk_dev, PCIR_CACHELNSZ, 1); 1400 if (val == 0) 1401 pci_write_config(sc->msk_dev, PCIR_CACHELNSZ, 2, 1); 1402 if (sc->msk_bustype == MSK_PCIX_BUS) { 1403 /* Set Cache Line Size opt. */ 1404 val = pci_read_config(sc->msk_dev, PCI_OUR_REG_1, 4); 1405 val |= PCI_CLS_OPT; 1406 pci_write_config(sc->msk_dev, PCI_OUR_REG_1, val, 4); 1407 } 1408 break; 1409 } 1410 /* Set PHY power state. */ 1411 msk_phy_power(sc, MSK_PHY_POWERUP); 1412 1413 /* Reset GPHY/GMAC Control */ 1414 for (i = 0; i < sc->msk_num_port; i++) { 1415 /* GPHY Control reset. */ 1416 CSR_WRITE_1(sc, MR_ADDR(i, GPHY_CTRL), GPC_RST_SET); 1417 CSR_WRITE_1(sc, MR_ADDR(i, GPHY_CTRL), GPC_RST_CLR); 1418 /* GMAC Control reset. */ 1419 CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), GMC_RST_SET); 1420 CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), GMC_RST_CLR); 1421 CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), GMC_F_LOOPB_OFF); 1422 if (sc->msk_hw_id == CHIP_ID_YUKON_EX || 1423 sc->msk_hw_id == CHIP_ID_YUKON_SUPR) 1424 CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), 1425 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON | 1426 GMC_BYP_RETR_ON); 1427 } 1428 1429 if (sc->msk_hw_id == CHIP_ID_YUKON_SUPR && 1430 sc->msk_hw_rev > CHIP_REV_YU_SU_B0) 1431 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_3, PCI_CLK_MACSEC_DIS); 1432 if (sc->msk_hw_id == CHIP_ID_YUKON_OPT && sc->msk_hw_rev == 0) { 1433 /* Disable PCIe PHY powerdown(reg 0x80, bit7). */ 1434 CSR_WRITE_4(sc, Y2_PEX_PHY_DATA, (0x0080 << 16) | 0x0080); 1435 } 1436 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 1437 1438 /* LED On. */ 1439 CSR_WRITE_2(sc, B0_CTST, Y2_LED_STAT_ON); 1440 1441 /* Clear TWSI IRQ. */ 1442 CSR_WRITE_4(sc, B2_I2C_IRQ, I2C_CLR_IRQ); 1443 1444 /* Turn off hardware timer. */ 1445 CSR_WRITE_1(sc, B2_TI_CTRL, TIM_STOP); 1446 CSR_WRITE_1(sc, B2_TI_CTRL, TIM_CLR_IRQ); 1447 1448 /* Turn off descriptor polling. */ 1449 CSR_WRITE_1(sc, B28_DPT_CTRL, DPT_STOP); 1450 1451 /* Turn off time stamps. */ 1452 CSR_WRITE_1(sc, GMAC_TI_ST_CTRL, GMT_ST_STOP); 1453 CSR_WRITE_1(sc, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ); 1454 1455 initram = 0; 1456 if (sc->msk_hw_id == CHIP_ID_YUKON_XL || 1457 sc->msk_hw_id == CHIP_ID_YUKON_EC || 1458 sc->msk_hw_id == CHIP_ID_YUKON_FE) 1459 initram++; 1460 1461 /* Configure timeout values. */ 1462 for (i = 0; initram > 0 && i < sc->msk_num_port; i++) { 1463 CSR_WRITE_2(sc, SELECT_RAM_BUFFER(i, B3_RI_CTRL), RI_RST_SET); 1464 CSR_WRITE_2(sc, SELECT_RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR); 1465 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_R1), 1466 MSK_RI_TO_53); 1467 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XA1), 1468 MSK_RI_TO_53); 1469 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XS1), 1470 MSK_RI_TO_53); 1471 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_R1), 1472 MSK_RI_TO_53); 1473 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XA1), 1474 MSK_RI_TO_53); 1475 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XS1), 1476 MSK_RI_TO_53); 1477 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_R2), 1478 MSK_RI_TO_53); 1479 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XA2), 1480 MSK_RI_TO_53); 1481 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XS2), 1482 MSK_RI_TO_53); 1483 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_R2), 1484 MSK_RI_TO_53); 1485 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XA2), 1486 MSK_RI_TO_53); 1487 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XS2), 1488 MSK_RI_TO_53); 1489 } 1490 1491 /* Disable all interrupts. */ 1492 CSR_WRITE_4(sc, B0_HWE_IMSK, 0); 1493 CSR_READ_4(sc, B0_HWE_IMSK); 1494 CSR_WRITE_4(sc, B0_IMSK, 0); 1495 CSR_READ_4(sc, B0_IMSK); 1496 1497 /* 1498 * On dual port PCI-X card, there is an problem where status 1499 * can be received out of order due to split transactions. 1500 */ 1501 if (sc->msk_pcixcap != 0 && sc->msk_num_port > 1) { 1502 uint16_t pcix_cmd; 1503 1504 pcix_cmd = pci_read_config(sc->msk_dev, 1505 sc->msk_pcixcap + PCIXR_COMMAND, 2); 1506 /* Clear Max Outstanding Split Transactions. */ 1507 pcix_cmd &= ~PCIXM_COMMAND_MAX_SPLITS; 1508 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON); 1509 pci_write_config(sc->msk_dev, 1510 sc->msk_pcixcap + PCIXR_COMMAND, pcix_cmd, 2); 1511 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 1512 } 1513 if (sc->msk_expcap != 0) { 1514 /* Change Max. Read Request Size to 2048 bytes. */ 1515 if (pci_get_max_read_req(sc->msk_dev) == 512) 1516 pci_set_max_read_req(sc->msk_dev, 2048); 1517 } 1518 1519 /* Clear status list. */ 1520 bzero(sc->msk_stat_ring, 1521 sizeof(struct msk_stat_desc) * sc->msk_stat_count); 1522 sc->msk_stat_cons = 0; 1523 bus_dmamap_sync(sc->msk_stat_tag, sc->msk_stat_map, 1524 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1525 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_RST_SET); 1526 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_RST_CLR); 1527 /* Set the status list base address. */ 1528 addr = sc->msk_stat_ring_paddr; 1529 CSR_WRITE_4(sc, STAT_LIST_ADDR_LO, MSK_ADDR_LO(addr)); 1530 CSR_WRITE_4(sc, STAT_LIST_ADDR_HI, MSK_ADDR_HI(addr)); 1531 /* Set the status list last index. */ 1532 CSR_WRITE_2(sc, STAT_LAST_IDX, sc->msk_stat_count - 1); 1533 if (sc->msk_hw_id == CHIP_ID_YUKON_EC && 1534 sc->msk_hw_rev == CHIP_REV_YU_EC_A1) { 1535 /* WA for dev. #4.3 */ 1536 CSR_WRITE_2(sc, STAT_TX_IDX_TH, ST_TXTH_IDX_MASK); 1537 /* WA for dev. #4.18 */ 1538 CSR_WRITE_1(sc, STAT_FIFO_WM, 0x21); 1539 CSR_WRITE_1(sc, STAT_FIFO_ISR_WM, 0x07); 1540 } else { 1541 CSR_WRITE_2(sc, STAT_TX_IDX_TH, 0x0a); 1542 CSR_WRITE_1(sc, STAT_FIFO_WM, 0x10); 1543 if (sc->msk_hw_id == CHIP_ID_YUKON_XL && 1544 sc->msk_hw_rev == CHIP_REV_YU_XL_A0) 1545 CSR_WRITE_1(sc, STAT_FIFO_ISR_WM, 0x04); 1546 else 1547 CSR_WRITE_1(sc, STAT_FIFO_ISR_WM, 0x10); 1548 CSR_WRITE_4(sc, STAT_ISR_TIMER_INI, 0x0190); 1549 } 1550 /* 1551 * Use default value for STAT_ISR_TIMER_INI, STAT_LEV_TIMER_INI. 1552 */ 1553 CSR_WRITE_4(sc, STAT_TX_TIMER_INI, MSK_USECS(sc, 1000)); 1554 1555 /* Enable status unit. */ 1556 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_OP_ON); 1557 1558 CSR_WRITE_1(sc, STAT_TX_TIMER_CTRL, TIM_START); 1559 CSR_WRITE_1(sc, STAT_LEV_TIMER_CTRL, TIM_START); 1560 CSR_WRITE_1(sc, STAT_ISR_TIMER_CTRL, TIM_START); 1561 } 1562 1563 static int 1564 msk_probe(device_t dev) 1565 { 1566 struct msk_softc *sc; 1567 1568 sc = device_get_softc(device_get_parent(dev)); 1569 /* 1570 * Not much to do here. We always know there will be 1571 * at least one GMAC present, and if there are two, 1572 * mskc_attach() will create a second device instance 1573 * for us. 1574 */ 1575 device_set_descf(dev, 1576 "Marvell Technology Group Ltd. %s Id 0x%02x Rev 0x%02x", 1577 model_name[sc->msk_hw_id - CHIP_ID_YUKON_XL], sc->msk_hw_id, 1578 sc->msk_hw_rev); 1579 1580 return (BUS_PROBE_DEFAULT); 1581 } 1582 1583 static int 1584 msk_attach(device_t dev) 1585 { 1586 struct msk_softc *sc; 1587 struct msk_if_softc *sc_if; 1588 if_t ifp; 1589 struct msk_mii_data *mmd; 1590 int i, port, error; 1591 uint8_t eaddr[6]; 1592 1593 if (dev == NULL) 1594 return (EINVAL); 1595 1596 error = 0; 1597 sc_if = device_get_softc(dev); 1598 sc = device_get_softc(device_get_parent(dev)); 1599 mmd = device_get_ivars(dev); 1600 port = mmd->port; 1601 1602 sc_if->msk_if_dev = dev; 1603 sc_if->msk_port = port; 1604 sc_if->msk_softc = sc; 1605 sc_if->msk_flags = sc->msk_pflags; 1606 sc->msk_if[port] = sc_if; 1607 /* Setup Tx/Rx queue register offsets. */ 1608 if (port == MSK_PORT_A) { 1609 sc_if->msk_txq = Q_XA1; 1610 sc_if->msk_txsq = Q_XS1; 1611 sc_if->msk_rxq = Q_R1; 1612 } else { 1613 sc_if->msk_txq = Q_XA2; 1614 sc_if->msk_txsq = Q_XS2; 1615 sc_if->msk_rxq = Q_R2; 1616 } 1617 1618 callout_init_mtx(&sc_if->msk_tick_ch, &sc_if->msk_softc->msk_mtx, 0); 1619 msk_sysctl_node(sc_if); 1620 1621 if ((error = msk_txrx_dma_alloc(sc_if)) != 0) 1622 goto fail; 1623 msk_rx_dma_jalloc(sc_if); 1624 1625 ifp = sc_if->msk_ifp = if_alloc(IFT_ETHER); 1626 if (ifp == NULL) { 1627 device_printf(sc_if->msk_if_dev, "can not if_alloc()\n"); 1628 error = ENOSPC; 1629 goto fail; 1630 } 1631 if_setsoftc(ifp, sc_if); 1632 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1633 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 1634 if_setcapabilities(ifp, IFCAP_TXCSUM | IFCAP_TSO4); 1635 /* 1636 * Enable Rx checksum offloading if controller supports 1637 * new descriptor formant and controller is not Yukon XL. 1638 */ 1639 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0 && 1640 sc->msk_hw_id != CHIP_ID_YUKON_XL) 1641 if_setcapabilitiesbit(ifp, IFCAP_RXCSUM, 0); 1642 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) != 0 && 1643 (sc_if->msk_flags & MSK_FLAG_NORX_CSUM) == 0) 1644 if_setcapabilitiesbit(ifp, IFCAP_RXCSUM, 0); 1645 if_sethwassist(ifp, MSK_CSUM_FEATURES | CSUM_TSO); 1646 if_setcapenable(ifp, if_getcapabilities(ifp)); 1647 if_setioctlfn(ifp, msk_ioctl); 1648 if_setstartfn(ifp, msk_start); 1649 if_setinitfn(ifp, msk_init); 1650 if_setsendqlen(ifp, MSK_TX_RING_CNT - 1); 1651 if_setsendqready(ifp); 1652 /* 1653 * Get station address for this interface. Note that 1654 * dual port cards actually come with three station 1655 * addresses: one for each port, plus an extra. The 1656 * extra one is used by the SysKonnect driver software 1657 * as a 'virtual' station address for when both ports 1658 * are operating in failover mode. Currently we don't 1659 * use this extra address. 1660 */ 1661 MSK_IF_LOCK(sc_if); 1662 for (i = 0; i < ETHER_ADDR_LEN; i++) 1663 eaddr[i] = CSR_READ_1(sc, B2_MAC_1 + (port * 8) + i); 1664 1665 /* 1666 * Call MI attach routine. Can't hold locks when calling into ether_*. 1667 */ 1668 MSK_IF_UNLOCK(sc_if); 1669 ether_ifattach(ifp, eaddr); 1670 MSK_IF_LOCK(sc_if); 1671 1672 /* VLAN capability setup */ 1673 if_setcapabilitiesbit(ifp, IFCAP_VLAN_MTU, 0); 1674 if ((sc_if->msk_flags & MSK_FLAG_NOHWVLAN) == 0) { 1675 /* 1676 * Due to Tx checksum offload hardware bugs, msk(4) manually 1677 * computes checksum for short frames. For VLAN tagged frames 1678 * this workaround does not work so disable checksum offload 1679 * for VLAN interface. 1680 */ 1681 if_setcapabilitiesbit(ifp, IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWTSO, 0); 1682 /* 1683 * Enable Rx checksum offloading for VLAN tagged frames 1684 * if controller support new descriptor format. 1685 */ 1686 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) != 0 && 1687 (sc_if->msk_flags & MSK_FLAG_NORX_CSUM) == 0) 1688 if_setcapabilitiesbit(ifp, IFCAP_VLAN_HWCSUM, 0); 1689 } 1690 if_setcapenable(ifp, if_getcapabilities(ifp)); 1691 /* 1692 * Disable RX checksum offloading on controllers that don't use 1693 * new descriptor format but give chance to enable it. 1694 */ 1695 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0) 1696 if_setcapenablebit(ifp, 0, IFCAP_RXCSUM); 1697 1698 /* 1699 * Tell the upper layer(s) we support long frames. 1700 * Must appear after the call to ether_ifattach() because 1701 * ether_ifattach() sets ifi_hdrlen to the default value. 1702 */ 1703 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 1704 1705 /* 1706 * Do miibus setup. 1707 */ 1708 MSK_IF_UNLOCK(sc_if); 1709 error = mii_attach(dev, &sc_if->msk_miibus, ifp, msk_mediachange, 1710 msk_mediastatus, BMSR_DEFCAPMASK, PHY_ADDR_MARV, MII_OFFSET_ANY, 1711 mmd->mii_flags); 1712 if (error != 0) { 1713 device_printf(sc_if->msk_if_dev, "attaching PHYs failed\n"); 1714 ether_ifdetach(ifp); 1715 error = ENXIO; 1716 goto fail; 1717 } 1718 1719 fail: 1720 if (error != 0) { 1721 /* Access should be ok even though lock has been dropped */ 1722 sc->msk_if[port] = NULL; 1723 msk_detach(dev); 1724 } 1725 1726 return (error); 1727 } 1728 1729 /* 1730 * Attach the interface. Allocate softc structures, do ifmedia 1731 * setup and ethernet/BPF attach. 1732 */ 1733 static int 1734 mskc_attach(device_t dev) 1735 { 1736 struct msk_softc *sc; 1737 struct msk_mii_data *mmd; 1738 int error, msic, msir, reg; 1739 1740 sc = device_get_softc(dev); 1741 sc->msk_dev = dev; 1742 mtx_init(&sc->msk_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1743 MTX_DEF); 1744 1745 /* 1746 * Map control/status registers. 1747 */ 1748 pci_enable_busmaster(dev); 1749 1750 /* Allocate I/O resource */ 1751 #ifdef MSK_USEIOSPACE 1752 sc->msk_res_spec = msk_res_spec_io; 1753 #else 1754 sc->msk_res_spec = msk_res_spec_mem; 1755 #endif 1756 sc->msk_irq_spec = msk_irq_spec_legacy; 1757 error = bus_alloc_resources(dev, sc->msk_res_spec, sc->msk_res); 1758 if (error) { 1759 if (sc->msk_res_spec == msk_res_spec_mem) 1760 sc->msk_res_spec = msk_res_spec_io; 1761 else 1762 sc->msk_res_spec = msk_res_spec_mem; 1763 error = bus_alloc_resources(dev, sc->msk_res_spec, sc->msk_res); 1764 if (error) { 1765 device_printf(dev, "couldn't allocate %s resources\n", 1766 sc->msk_res_spec == msk_res_spec_mem ? "memory" : 1767 "I/O"); 1768 mtx_destroy(&sc->msk_mtx); 1769 return (ENXIO); 1770 } 1771 } 1772 1773 /* Enable all clocks before accessing any registers. */ 1774 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_3, 0); 1775 1776 CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR); 1777 sc->msk_hw_id = CSR_READ_1(sc, B2_CHIP_ID); 1778 sc->msk_hw_rev = (CSR_READ_1(sc, B2_MAC_CFG) >> 4) & 0x0f; 1779 /* Bail out if chip is not recognized. */ 1780 if (sc->msk_hw_id < CHIP_ID_YUKON_XL || 1781 sc->msk_hw_id > CHIP_ID_YUKON_OPT || 1782 sc->msk_hw_id == CHIP_ID_YUKON_UNKNOWN) { 1783 device_printf(dev, "unknown device: id=0x%02x, rev=0x%02x\n", 1784 sc->msk_hw_id, sc->msk_hw_rev); 1785 mtx_destroy(&sc->msk_mtx); 1786 return (ENXIO); 1787 } 1788 1789 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 1790 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 1791 OID_AUTO, "process_limit", 1792 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 1793 &sc->msk_process_limit, 0, sysctl_hw_msk_proc_limit, "I", 1794 "max number of Rx events to process"); 1795 1796 sc->msk_process_limit = MSK_PROC_DEFAULT; 1797 error = resource_int_value(device_get_name(dev), device_get_unit(dev), 1798 "process_limit", &sc->msk_process_limit); 1799 if (error == 0) { 1800 if (sc->msk_process_limit < MSK_PROC_MIN || 1801 sc->msk_process_limit > MSK_PROC_MAX) { 1802 device_printf(dev, "process_limit value out of range; " 1803 "using default: %d\n", MSK_PROC_DEFAULT); 1804 sc->msk_process_limit = MSK_PROC_DEFAULT; 1805 } 1806 } 1807 1808 sc->msk_int_holdoff = MSK_INT_HOLDOFF_DEFAULT; 1809 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 1810 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 1811 "int_holdoff", CTLFLAG_RW, &sc->msk_int_holdoff, 0, 1812 "Maximum number of time to delay interrupts"); 1813 resource_int_value(device_get_name(dev), device_get_unit(dev), 1814 "int_holdoff", &sc->msk_int_holdoff); 1815 1816 sc->msk_pmd = CSR_READ_1(sc, B2_PMD_TYP); 1817 /* Check number of MACs. */ 1818 sc->msk_num_port = 1; 1819 if ((CSR_READ_1(sc, B2_Y2_HW_RES) & CFG_DUAL_MAC_MSK) == 1820 CFG_DUAL_MAC_MSK) { 1821 if (!(CSR_READ_1(sc, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC)) 1822 sc->msk_num_port++; 1823 } 1824 1825 /* Check bus type. */ 1826 if (pci_find_cap(sc->msk_dev, PCIY_EXPRESS, ®) == 0) { 1827 sc->msk_bustype = MSK_PEX_BUS; 1828 sc->msk_expcap = reg; 1829 } else if (pci_find_cap(sc->msk_dev, PCIY_PCIX, ®) == 0) { 1830 sc->msk_bustype = MSK_PCIX_BUS; 1831 sc->msk_pcixcap = reg; 1832 } else 1833 sc->msk_bustype = MSK_PCI_BUS; 1834 1835 switch (sc->msk_hw_id) { 1836 case CHIP_ID_YUKON_EC: 1837 sc->msk_clock = 125; /* 125 MHz */ 1838 sc->msk_pflags |= MSK_FLAG_JUMBO; 1839 break; 1840 case CHIP_ID_YUKON_EC_U: 1841 sc->msk_clock = 125; /* 125 MHz */ 1842 sc->msk_pflags |= MSK_FLAG_JUMBO | MSK_FLAG_JUMBO_NOCSUM; 1843 break; 1844 case CHIP_ID_YUKON_EX: 1845 sc->msk_clock = 125; /* 125 MHz */ 1846 sc->msk_pflags |= MSK_FLAG_JUMBO | MSK_FLAG_DESCV2 | 1847 MSK_FLAG_AUTOTX_CSUM; 1848 /* 1849 * Yukon Extreme seems to have silicon bug for 1850 * automatic Tx checksum calculation capability. 1851 */ 1852 if (sc->msk_hw_rev == CHIP_REV_YU_EX_B0) 1853 sc->msk_pflags &= ~MSK_FLAG_AUTOTX_CSUM; 1854 /* 1855 * Yukon Extreme A0 could not use store-and-forward 1856 * for jumbo frames, so disable Tx checksum 1857 * offloading for jumbo frames. 1858 */ 1859 if (sc->msk_hw_rev == CHIP_REV_YU_EX_A0) 1860 sc->msk_pflags |= MSK_FLAG_JUMBO_NOCSUM; 1861 break; 1862 case CHIP_ID_YUKON_FE: 1863 sc->msk_clock = 100; /* 100 MHz */ 1864 sc->msk_pflags |= MSK_FLAG_FASTETHER; 1865 break; 1866 case CHIP_ID_YUKON_FE_P: 1867 sc->msk_clock = 50; /* 50 MHz */ 1868 sc->msk_pflags |= MSK_FLAG_FASTETHER | MSK_FLAG_DESCV2 | 1869 MSK_FLAG_AUTOTX_CSUM; 1870 if (sc->msk_hw_rev == CHIP_REV_YU_FE_P_A0) { 1871 /* 1872 * XXX 1873 * FE+ A0 has status LE writeback bug so msk(4) 1874 * does not rely on status word of received frame 1875 * in msk_rxeof() which in turn disables all 1876 * hardware assistance bits reported by the status 1877 * word as well as validity of the received frame. 1878 * Just pass received frames to upper stack with 1879 * minimal test and let upper stack handle them. 1880 */ 1881 sc->msk_pflags |= MSK_FLAG_NOHWVLAN | 1882 MSK_FLAG_NORXCHK | MSK_FLAG_NORX_CSUM; 1883 } 1884 break; 1885 case CHIP_ID_YUKON_XL: 1886 sc->msk_clock = 156; /* 156 MHz */ 1887 sc->msk_pflags |= MSK_FLAG_JUMBO; 1888 break; 1889 case CHIP_ID_YUKON_SUPR: 1890 sc->msk_clock = 125; /* 125 MHz */ 1891 sc->msk_pflags |= MSK_FLAG_JUMBO | MSK_FLAG_DESCV2 | 1892 MSK_FLAG_AUTOTX_CSUM; 1893 break; 1894 case CHIP_ID_YUKON_UL_2: 1895 sc->msk_clock = 125; /* 125 MHz */ 1896 sc->msk_pflags |= MSK_FLAG_JUMBO; 1897 break; 1898 case CHIP_ID_YUKON_OPT: 1899 sc->msk_clock = 125; /* 125 MHz */ 1900 sc->msk_pflags |= MSK_FLAG_JUMBO | MSK_FLAG_DESCV2; 1901 break; 1902 default: 1903 sc->msk_clock = 156; /* 156 MHz */ 1904 break; 1905 } 1906 1907 /* Allocate IRQ resources. */ 1908 msic = pci_msi_count(dev); 1909 if (bootverbose) 1910 device_printf(dev, "MSI count : %d\n", msic); 1911 if (legacy_intr != 0) 1912 msi_disable = 1; 1913 if (msi_disable == 0 && msic > 0) { 1914 msir = 1; 1915 if (pci_alloc_msi(dev, &msir) == 0) { 1916 if (msir == 1) { 1917 sc->msk_pflags |= MSK_FLAG_MSI; 1918 sc->msk_irq_spec = msk_irq_spec_msi; 1919 } else 1920 pci_release_msi(dev); 1921 } 1922 } 1923 1924 error = bus_alloc_resources(dev, sc->msk_irq_spec, sc->msk_irq); 1925 if (error) { 1926 device_printf(dev, "couldn't allocate IRQ resources\n"); 1927 goto fail; 1928 } 1929 1930 if ((error = msk_status_dma_alloc(sc)) != 0) 1931 goto fail; 1932 1933 /* Set base interrupt mask. */ 1934 sc->msk_intrmask = Y2_IS_HW_ERR | Y2_IS_STAT_BMU; 1935 sc->msk_intrhwemask = Y2_IS_TIST_OV | Y2_IS_MST_ERR | 1936 Y2_IS_IRQ_STAT | Y2_IS_PCI_EXP | Y2_IS_PCI_NEXP; 1937 1938 /* Reset the adapter. */ 1939 mskc_reset(sc); 1940 1941 if ((error = mskc_setup_rambuffer(sc)) != 0) 1942 goto fail; 1943 1944 sc->msk_devs[MSK_PORT_A] = device_add_child(dev, "msk", -1); 1945 if (sc->msk_devs[MSK_PORT_A] == NULL) { 1946 device_printf(dev, "failed to add child for PORT_A\n"); 1947 error = ENXIO; 1948 goto fail; 1949 } 1950 mmd = malloc(sizeof(struct msk_mii_data), M_DEVBUF, M_WAITOK | M_ZERO); 1951 mmd->port = MSK_PORT_A; 1952 mmd->pmd = sc->msk_pmd; 1953 mmd->mii_flags |= MIIF_DOPAUSE; 1954 if (sc->msk_pmd == 'L' || sc->msk_pmd == 'S') 1955 mmd->mii_flags |= MIIF_HAVEFIBER; 1956 if (sc->msk_pmd == 'P') 1957 mmd->mii_flags |= MIIF_HAVEFIBER | MIIF_MACPRIV0; 1958 device_set_ivars(sc->msk_devs[MSK_PORT_A], mmd); 1959 1960 if (sc->msk_num_port > 1) { 1961 sc->msk_devs[MSK_PORT_B] = device_add_child(dev, "msk", -1); 1962 if (sc->msk_devs[MSK_PORT_B] == NULL) { 1963 device_printf(dev, "failed to add child for PORT_B\n"); 1964 error = ENXIO; 1965 goto fail; 1966 } 1967 mmd = malloc(sizeof(struct msk_mii_data), M_DEVBUF, M_WAITOK | 1968 M_ZERO); 1969 mmd->port = MSK_PORT_B; 1970 mmd->pmd = sc->msk_pmd; 1971 if (sc->msk_pmd == 'L' || sc->msk_pmd == 'S') 1972 mmd->mii_flags |= MIIF_HAVEFIBER; 1973 if (sc->msk_pmd == 'P') 1974 mmd->mii_flags |= MIIF_HAVEFIBER | MIIF_MACPRIV0; 1975 device_set_ivars(sc->msk_devs[MSK_PORT_B], mmd); 1976 } 1977 1978 error = bus_generic_attach(dev); 1979 if (error) { 1980 device_printf(dev, "failed to attach port(s)\n"); 1981 goto fail; 1982 } 1983 1984 /* Hook interrupt last to avoid having to lock softc. */ 1985 error = bus_setup_intr(dev, sc->msk_irq[0], INTR_TYPE_NET | 1986 INTR_MPSAFE, NULL, msk_intr, sc, &sc->msk_intrhand); 1987 if (error != 0) { 1988 device_printf(dev, "couldn't set up interrupt handler\n"); 1989 goto fail; 1990 } 1991 fail: 1992 if (error != 0) 1993 mskc_detach(dev); 1994 1995 return (error); 1996 } 1997 1998 /* 1999 * Shutdown hardware and free up resources. This can be called any 2000 * time after the mutex has been initialized. It is called in both 2001 * the error case in attach and the normal detach case so it needs 2002 * to be careful about only freeing resources that have actually been 2003 * allocated. 2004 */ 2005 static int 2006 msk_detach(device_t dev) 2007 { 2008 struct msk_softc *sc; 2009 struct msk_if_softc *sc_if; 2010 if_t ifp; 2011 2012 sc_if = device_get_softc(dev); 2013 KASSERT(mtx_initialized(&sc_if->msk_softc->msk_mtx), 2014 ("msk mutex not initialized in msk_detach")); 2015 MSK_IF_LOCK(sc_if); 2016 2017 ifp = sc_if->msk_ifp; 2018 if (device_is_attached(dev)) { 2019 /* XXX */ 2020 sc_if->msk_flags |= MSK_FLAG_DETACH; 2021 msk_stop(sc_if); 2022 /* Can't hold locks while calling detach. */ 2023 MSK_IF_UNLOCK(sc_if); 2024 callout_drain(&sc_if->msk_tick_ch); 2025 if (ifp) 2026 ether_ifdetach(ifp); 2027 MSK_IF_LOCK(sc_if); 2028 } 2029 2030 /* 2031 * We're generally called from mskc_detach() which is using 2032 * device_delete_child() to get to here. It's already trashed 2033 * miibus for us, so don't do it here or we'll panic. 2034 * 2035 * if (sc_if->msk_miibus != NULL) { 2036 * device_delete_child(dev, sc_if->msk_miibus); 2037 * sc_if->msk_miibus = NULL; 2038 * } 2039 */ 2040 2041 msk_rx_dma_jfree(sc_if); 2042 msk_txrx_dma_free(sc_if); 2043 bus_generic_detach(dev); 2044 2045 sc = sc_if->msk_softc; 2046 sc->msk_if[sc_if->msk_port] = NULL; 2047 MSK_IF_UNLOCK(sc_if); 2048 if (ifp) 2049 if_free(ifp); 2050 2051 return (0); 2052 } 2053 2054 static int 2055 mskc_detach(device_t dev) 2056 { 2057 struct msk_softc *sc; 2058 2059 sc = device_get_softc(dev); 2060 KASSERT(mtx_initialized(&sc->msk_mtx), ("msk mutex not initialized")); 2061 2062 if (device_is_alive(dev)) { 2063 if (sc->msk_devs[MSK_PORT_A] != NULL) { 2064 free(device_get_ivars(sc->msk_devs[MSK_PORT_A]), 2065 M_DEVBUF); 2066 device_delete_child(dev, sc->msk_devs[MSK_PORT_A]); 2067 } 2068 if (sc->msk_devs[MSK_PORT_B] != NULL) { 2069 free(device_get_ivars(sc->msk_devs[MSK_PORT_B]), 2070 M_DEVBUF); 2071 device_delete_child(dev, sc->msk_devs[MSK_PORT_B]); 2072 } 2073 bus_generic_detach(dev); 2074 } 2075 2076 /* Disable all interrupts. */ 2077 CSR_WRITE_4(sc, B0_IMSK, 0); 2078 CSR_READ_4(sc, B0_IMSK); 2079 CSR_WRITE_4(sc, B0_HWE_IMSK, 0); 2080 CSR_READ_4(sc, B0_HWE_IMSK); 2081 2082 /* LED Off. */ 2083 CSR_WRITE_2(sc, B0_CTST, Y2_LED_STAT_OFF); 2084 2085 /* Put hardware reset. */ 2086 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); 2087 2088 msk_status_dma_free(sc); 2089 2090 if (sc->msk_intrhand) { 2091 bus_teardown_intr(dev, sc->msk_irq[0], sc->msk_intrhand); 2092 sc->msk_intrhand = NULL; 2093 } 2094 bus_release_resources(dev, sc->msk_irq_spec, sc->msk_irq); 2095 if ((sc->msk_pflags & MSK_FLAG_MSI) != 0) 2096 pci_release_msi(dev); 2097 bus_release_resources(dev, sc->msk_res_spec, sc->msk_res); 2098 mtx_destroy(&sc->msk_mtx); 2099 2100 return (0); 2101 } 2102 2103 static bus_dma_tag_t 2104 mskc_get_dma_tag(device_t bus, device_t child __unused) 2105 { 2106 2107 return (bus_get_dma_tag(bus)); 2108 } 2109 2110 struct msk_dmamap_arg { 2111 bus_addr_t msk_busaddr; 2112 }; 2113 2114 static void 2115 msk_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 2116 { 2117 struct msk_dmamap_arg *ctx; 2118 2119 if (error != 0) 2120 return; 2121 ctx = arg; 2122 ctx->msk_busaddr = segs[0].ds_addr; 2123 } 2124 2125 /* Create status DMA region. */ 2126 static int 2127 msk_status_dma_alloc(struct msk_softc *sc) 2128 { 2129 struct msk_dmamap_arg ctx; 2130 bus_size_t stat_sz; 2131 int count, error; 2132 2133 /* 2134 * It seems controller requires number of status LE entries 2135 * is power of 2 and the maximum number of status LE entries 2136 * is 4096. For dual-port controllers, the number of status 2137 * LE entries should be large enough to hold both port's 2138 * status updates. 2139 */ 2140 count = 3 * MSK_RX_RING_CNT + MSK_TX_RING_CNT; 2141 count = imin(4096, roundup2(count, 1024)); 2142 sc->msk_stat_count = count; 2143 stat_sz = count * sizeof(struct msk_stat_desc); 2144 error = bus_dma_tag_create( 2145 bus_get_dma_tag(sc->msk_dev), /* parent */ 2146 MSK_STAT_ALIGN, 0, /* alignment, boundary */ 2147 BUS_SPACE_MAXADDR, /* lowaddr */ 2148 BUS_SPACE_MAXADDR, /* highaddr */ 2149 NULL, NULL, /* filter, filterarg */ 2150 stat_sz, /* maxsize */ 2151 1, /* nsegments */ 2152 stat_sz, /* maxsegsize */ 2153 0, /* flags */ 2154 NULL, NULL, /* lockfunc, lockarg */ 2155 &sc->msk_stat_tag); 2156 if (error != 0) { 2157 device_printf(sc->msk_dev, 2158 "failed to create status DMA tag\n"); 2159 return (error); 2160 } 2161 2162 /* Allocate DMA'able memory and load the DMA map for status ring. */ 2163 error = bus_dmamem_alloc(sc->msk_stat_tag, 2164 (void **)&sc->msk_stat_ring, BUS_DMA_WAITOK | BUS_DMA_COHERENT | 2165 BUS_DMA_ZERO, &sc->msk_stat_map); 2166 if (error != 0) { 2167 device_printf(sc->msk_dev, 2168 "failed to allocate DMA'able memory for status ring\n"); 2169 return (error); 2170 } 2171 2172 ctx.msk_busaddr = 0; 2173 error = bus_dmamap_load(sc->msk_stat_tag, sc->msk_stat_map, 2174 sc->msk_stat_ring, stat_sz, msk_dmamap_cb, &ctx, BUS_DMA_NOWAIT); 2175 if (error != 0) { 2176 device_printf(sc->msk_dev, 2177 "failed to load DMA'able memory for status ring\n"); 2178 return (error); 2179 } 2180 sc->msk_stat_ring_paddr = ctx.msk_busaddr; 2181 2182 return (0); 2183 } 2184 2185 static void 2186 msk_status_dma_free(struct msk_softc *sc) 2187 { 2188 2189 /* Destroy status block. */ 2190 if (sc->msk_stat_tag) { 2191 if (sc->msk_stat_ring_paddr) { 2192 bus_dmamap_unload(sc->msk_stat_tag, sc->msk_stat_map); 2193 sc->msk_stat_ring_paddr = 0; 2194 } 2195 if (sc->msk_stat_ring) { 2196 bus_dmamem_free(sc->msk_stat_tag, 2197 sc->msk_stat_ring, sc->msk_stat_map); 2198 sc->msk_stat_ring = NULL; 2199 } 2200 bus_dma_tag_destroy(sc->msk_stat_tag); 2201 sc->msk_stat_tag = NULL; 2202 } 2203 } 2204 2205 static int 2206 msk_txrx_dma_alloc(struct msk_if_softc *sc_if) 2207 { 2208 struct msk_dmamap_arg ctx; 2209 struct msk_txdesc *txd; 2210 struct msk_rxdesc *rxd; 2211 bus_size_t rxalign; 2212 int error, i; 2213 2214 /* Create parent DMA tag. */ 2215 error = bus_dma_tag_create( 2216 bus_get_dma_tag(sc_if->msk_if_dev), /* parent */ 2217 1, 0, /* alignment, boundary */ 2218 BUS_SPACE_MAXADDR, /* lowaddr */ 2219 BUS_SPACE_MAXADDR, /* highaddr */ 2220 NULL, NULL, /* filter, filterarg */ 2221 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 2222 0, /* nsegments */ 2223 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 2224 0, /* flags */ 2225 NULL, NULL, /* lockfunc, lockarg */ 2226 &sc_if->msk_cdata.msk_parent_tag); 2227 if (error != 0) { 2228 device_printf(sc_if->msk_if_dev, 2229 "failed to create parent DMA tag\n"); 2230 goto fail; 2231 } 2232 /* Create tag for Tx ring. */ 2233 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2234 MSK_RING_ALIGN, 0, /* alignment, boundary */ 2235 BUS_SPACE_MAXADDR, /* lowaddr */ 2236 BUS_SPACE_MAXADDR, /* highaddr */ 2237 NULL, NULL, /* filter, filterarg */ 2238 MSK_TX_RING_SZ, /* maxsize */ 2239 1, /* nsegments */ 2240 MSK_TX_RING_SZ, /* maxsegsize */ 2241 0, /* flags */ 2242 NULL, NULL, /* lockfunc, lockarg */ 2243 &sc_if->msk_cdata.msk_tx_ring_tag); 2244 if (error != 0) { 2245 device_printf(sc_if->msk_if_dev, 2246 "failed to create Tx ring DMA tag\n"); 2247 goto fail; 2248 } 2249 2250 /* Create tag for Rx ring. */ 2251 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2252 MSK_RING_ALIGN, 0, /* alignment, boundary */ 2253 BUS_SPACE_MAXADDR, /* lowaddr */ 2254 BUS_SPACE_MAXADDR, /* highaddr */ 2255 NULL, NULL, /* filter, filterarg */ 2256 MSK_RX_RING_SZ, /* maxsize */ 2257 1, /* nsegments */ 2258 MSK_RX_RING_SZ, /* maxsegsize */ 2259 0, /* flags */ 2260 NULL, NULL, /* lockfunc, lockarg */ 2261 &sc_if->msk_cdata.msk_rx_ring_tag); 2262 if (error != 0) { 2263 device_printf(sc_if->msk_if_dev, 2264 "failed to create Rx ring DMA tag\n"); 2265 goto fail; 2266 } 2267 2268 /* Create tag for Tx buffers. */ 2269 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2270 1, 0, /* alignment, boundary */ 2271 BUS_SPACE_MAXADDR, /* lowaddr */ 2272 BUS_SPACE_MAXADDR, /* highaddr */ 2273 NULL, NULL, /* filter, filterarg */ 2274 MSK_TSO_MAXSIZE, /* maxsize */ 2275 MSK_MAXTXSEGS, /* nsegments */ 2276 MSK_TSO_MAXSGSIZE, /* maxsegsize */ 2277 0, /* flags */ 2278 NULL, NULL, /* lockfunc, lockarg */ 2279 &sc_if->msk_cdata.msk_tx_tag); 2280 if (error != 0) { 2281 device_printf(sc_if->msk_if_dev, 2282 "failed to create Tx DMA tag\n"); 2283 goto fail; 2284 } 2285 2286 rxalign = 1; 2287 /* 2288 * Workaround hardware hang which seems to happen when Rx buffer 2289 * is not aligned on multiple of FIFO word(8 bytes). 2290 */ 2291 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) != 0) 2292 rxalign = MSK_RX_BUF_ALIGN; 2293 /* Create tag for Rx buffers. */ 2294 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2295 rxalign, 0, /* alignment, boundary */ 2296 BUS_SPACE_MAXADDR, /* lowaddr */ 2297 BUS_SPACE_MAXADDR, /* highaddr */ 2298 NULL, NULL, /* filter, filterarg */ 2299 MCLBYTES, /* maxsize */ 2300 1, /* nsegments */ 2301 MCLBYTES, /* maxsegsize */ 2302 0, /* flags */ 2303 NULL, NULL, /* lockfunc, lockarg */ 2304 &sc_if->msk_cdata.msk_rx_tag); 2305 if (error != 0) { 2306 device_printf(sc_if->msk_if_dev, 2307 "failed to create Rx DMA tag\n"); 2308 goto fail; 2309 } 2310 2311 /* Allocate DMA'able memory and load the DMA map for Tx ring. */ 2312 error = bus_dmamem_alloc(sc_if->msk_cdata.msk_tx_ring_tag, 2313 (void **)&sc_if->msk_rdata.msk_tx_ring, BUS_DMA_WAITOK | 2314 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc_if->msk_cdata.msk_tx_ring_map); 2315 if (error != 0) { 2316 device_printf(sc_if->msk_if_dev, 2317 "failed to allocate DMA'able memory for Tx ring\n"); 2318 goto fail; 2319 } 2320 2321 ctx.msk_busaddr = 0; 2322 error = bus_dmamap_load(sc_if->msk_cdata.msk_tx_ring_tag, 2323 sc_if->msk_cdata.msk_tx_ring_map, sc_if->msk_rdata.msk_tx_ring, 2324 MSK_TX_RING_SZ, msk_dmamap_cb, &ctx, BUS_DMA_NOWAIT); 2325 if (error != 0) { 2326 device_printf(sc_if->msk_if_dev, 2327 "failed to load DMA'able memory for Tx ring\n"); 2328 goto fail; 2329 } 2330 sc_if->msk_rdata.msk_tx_ring_paddr = ctx.msk_busaddr; 2331 2332 /* Allocate DMA'able memory and load the DMA map for Rx ring. */ 2333 error = bus_dmamem_alloc(sc_if->msk_cdata.msk_rx_ring_tag, 2334 (void **)&sc_if->msk_rdata.msk_rx_ring, BUS_DMA_WAITOK | 2335 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc_if->msk_cdata.msk_rx_ring_map); 2336 if (error != 0) { 2337 device_printf(sc_if->msk_if_dev, 2338 "failed to allocate DMA'able memory for Rx ring\n"); 2339 goto fail; 2340 } 2341 2342 ctx.msk_busaddr = 0; 2343 error = bus_dmamap_load(sc_if->msk_cdata.msk_rx_ring_tag, 2344 sc_if->msk_cdata.msk_rx_ring_map, sc_if->msk_rdata.msk_rx_ring, 2345 MSK_RX_RING_SZ, msk_dmamap_cb, &ctx, BUS_DMA_NOWAIT); 2346 if (error != 0) { 2347 device_printf(sc_if->msk_if_dev, 2348 "failed to load DMA'able memory for Rx ring\n"); 2349 goto fail; 2350 } 2351 sc_if->msk_rdata.msk_rx_ring_paddr = ctx.msk_busaddr; 2352 2353 /* Create DMA maps for Tx buffers. */ 2354 for (i = 0; i < MSK_TX_RING_CNT; i++) { 2355 txd = &sc_if->msk_cdata.msk_txdesc[i]; 2356 txd->tx_m = NULL; 2357 txd->tx_dmamap = NULL; 2358 error = bus_dmamap_create(sc_if->msk_cdata.msk_tx_tag, 0, 2359 &txd->tx_dmamap); 2360 if (error != 0) { 2361 device_printf(sc_if->msk_if_dev, 2362 "failed to create Tx dmamap\n"); 2363 goto fail; 2364 } 2365 } 2366 /* Create DMA maps for Rx buffers. */ 2367 if ((error = bus_dmamap_create(sc_if->msk_cdata.msk_rx_tag, 0, 2368 &sc_if->msk_cdata.msk_rx_sparemap)) != 0) { 2369 device_printf(sc_if->msk_if_dev, 2370 "failed to create spare Rx dmamap\n"); 2371 goto fail; 2372 } 2373 for (i = 0; i < MSK_RX_RING_CNT; i++) { 2374 rxd = &sc_if->msk_cdata.msk_rxdesc[i]; 2375 rxd->rx_m = NULL; 2376 rxd->rx_dmamap = NULL; 2377 error = bus_dmamap_create(sc_if->msk_cdata.msk_rx_tag, 0, 2378 &rxd->rx_dmamap); 2379 if (error != 0) { 2380 device_printf(sc_if->msk_if_dev, 2381 "failed to create Rx dmamap\n"); 2382 goto fail; 2383 } 2384 } 2385 2386 fail: 2387 return (error); 2388 } 2389 2390 static int 2391 msk_rx_dma_jalloc(struct msk_if_softc *sc_if) 2392 { 2393 struct msk_dmamap_arg ctx; 2394 struct msk_rxdesc *jrxd; 2395 bus_size_t rxalign; 2396 int error, i; 2397 2398 if (jumbo_disable != 0 || (sc_if->msk_flags & MSK_FLAG_JUMBO) == 0) { 2399 sc_if->msk_flags &= ~MSK_FLAG_JUMBO; 2400 device_printf(sc_if->msk_if_dev, 2401 "disabling jumbo frame support\n"); 2402 return (0); 2403 } 2404 /* Create tag for jumbo Rx ring. */ 2405 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2406 MSK_RING_ALIGN, 0, /* alignment, boundary */ 2407 BUS_SPACE_MAXADDR, /* lowaddr */ 2408 BUS_SPACE_MAXADDR, /* highaddr */ 2409 NULL, NULL, /* filter, filterarg */ 2410 MSK_JUMBO_RX_RING_SZ, /* maxsize */ 2411 1, /* nsegments */ 2412 MSK_JUMBO_RX_RING_SZ, /* maxsegsize */ 2413 0, /* flags */ 2414 NULL, NULL, /* lockfunc, lockarg */ 2415 &sc_if->msk_cdata.msk_jumbo_rx_ring_tag); 2416 if (error != 0) { 2417 device_printf(sc_if->msk_if_dev, 2418 "failed to create jumbo Rx ring DMA tag\n"); 2419 goto jumbo_fail; 2420 } 2421 2422 rxalign = 1; 2423 /* 2424 * Workaround hardware hang which seems to happen when Rx buffer 2425 * is not aligned on multiple of FIFO word(8 bytes). 2426 */ 2427 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) != 0) 2428 rxalign = MSK_RX_BUF_ALIGN; 2429 /* Create tag for jumbo Rx buffers. */ 2430 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2431 rxalign, 0, /* alignment, boundary */ 2432 BUS_SPACE_MAXADDR, /* lowaddr */ 2433 BUS_SPACE_MAXADDR, /* highaddr */ 2434 NULL, NULL, /* filter, filterarg */ 2435 MJUM9BYTES, /* maxsize */ 2436 1, /* nsegments */ 2437 MJUM9BYTES, /* maxsegsize */ 2438 0, /* flags */ 2439 NULL, NULL, /* lockfunc, lockarg */ 2440 &sc_if->msk_cdata.msk_jumbo_rx_tag); 2441 if (error != 0) { 2442 device_printf(sc_if->msk_if_dev, 2443 "failed to create jumbo Rx DMA tag\n"); 2444 goto jumbo_fail; 2445 } 2446 2447 /* Allocate DMA'able memory and load the DMA map for jumbo Rx ring. */ 2448 error = bus_dmamem_alloc(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 2449 (void **)&sc_if->msk_rdata.msk_jumbo_rx_ring, 2450 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 2451 &sc_if->msk_cdata.msk_jumbo_rx_ring_map); 2452 if (error != 0) { 2453 device_printf(sc_if->msk_if_dev, 2454 "failed to allocate DMA'able memory for jumbo Rx ring\n"); 2455 goto jumbo_fail; 2456 } 2457 2458 ctx.msk_busaddr = 0; 2459 error = bus_dmamap_load(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 2460 sc_if->msk_cdata.msk_jumbo_rx_ring_map, 2461 sc_if->msk_rdata.msk_jumbo_rx_ring, MSK_JUMBO_RX_RING_SZ, 2462 msk_dmamap_cb, &ctx, BUS_DMA_NOWAIT); 2463 if (error != 0) { 2464 device_printf(sc_if->msk_if_dev, 2465 "failed to load DMA'able memory for jumbo Rx ring\n"); 2466 goto jumbo_fail; 2467 } 2468 sc_if->msk_rdata.msk_jumbo_rx_ring_paddr = ctx.msk_busaddr; 2469 2470 /* Create DMA maps for jumbo Rx buffers. */ 2471 if ((error = bus_dmamap_create(sc_if->msk_cdata.msk_jumbo_rx_tag, 0, 2472 &sc_if->msk_cdata.msk_jumbo_rx_sparemap)) != 0) { 2473 device_printf(sc_if->msk_if_dev, 2474 "failed to create spare jumbo Rx dmamap\n"); 2475 goto jumbo_fail; 2476 } 2477 for (i = 0; i < MSK_JUMBO_RX_RING_CNT; i++) { 2478 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[i]; 2479 jrxd->rx_m = NULL; 2480 jrxd->rx_dmamap = NULL; 2481 error = bus_dmamap_create(sc_if->msk_cdata.msk_jumbo_rx_tag, 0, 2482 &jrxd->rx_dmamap); 2483 if (error != 0) { 2484 device_printf(sc_if->msk_if_dev, 2485 "failed to create jumbo Rx dmamap\n"); 2486 goto jumbo_fail; 2487 } 2488 } 2489 2490 return (0); 2491 2492 jumbo_fail: 2493 msk_rx_dma_jfree(sc_if); 2494 device_printf(sc_if->msk_if_dev, "disabling jumbo frame support " 2495 "due to resource shortage\n"); 2496 sc_if->msk_flags &= ~MSK_FLAG_JUMBO; 2497 return (error); 2498 } 2499 2500 static void 2501 msk_txrx_dma_free(struct msk_if_softc *sc_if) 2502 { 2503 struct msk_txdesc *txd; 2504 struct msk_rxdesc *rxd; 2505 int i; 2506 2507 /* Tx ring. */ 2508 if (sc_if->msk_cdata.msk_tx_ring_tag) { 2509 if (sc_if->msk_rdata.msk_tx_ring_paddr) 2510 bus_dmamap_unload(sc_if->msk_cdata.msk_tx_ring_tag, 2511 sc_if->msk_cdata.msk_tx_ring_map); 2512 if (sc_if->msk_rdata.msk_tx_ring) 2513 bus_dmamem_free(sc_if->msk_cdata.msk_tx_ring_tag, 2514 sc_if->msk_rdata.msk_tx_ring, 2515 sc_if->msk_cdata.msk_tx_ring_map); 2516 sc_if->msk_rdata.msk_tx_ring = NULL; 2517 sc_if->msk_rdata.msk_tx_ring_paddr = 0; 2518 bus_dma_tag_destroy(sc_if->msk_cdata.msk_tx_ring_tag); 2519 sc_if->msk_cdata.msk_tx_ring_tag = NULL; 2520 } 2521 /* Rx ring. */ 2522 if (sc_if->msk_cdata.msk_rx_ring_tag) { 2523 if (sc_if->msk_rdata.msk_rx_ring_paddr) 2524 bus_dmamap_unload(sc_if->msk_cdata.msk_rx_ring_tag, 2525 sc_if->msk_cdata.msk_rx_ring_map); 2526 if (sc_if->msk_rdata.msk_rx_ring) 2527 bus_dmamem_free(sc_if->msk_cdata.msk_rx_ring_tag, 2528 sc_if->msk_rdata.msk_rx_ring, 2529 sc_if->msk_cdata.msk_rx_ring_map); 2530 sc_if->msk_rdata.msk_rx_ring = NULL; 2531 sc_if->msk_rdata.msk_rx_ring_paddr = 0; 2532 bus_dma_tag_destroy(sc_if->msk_cdata.msk_rx_ring_tag); 2533 sc_if->msk_cdata.msk_rx_ring_tag = NULL; 2534 } 2535 /* Tx buffers. */ 2536 if (sc_if->msk_cdata.msk_tx_tag) { 2537 for (i = 0; i < MSK_TX_RING_CNT; i++) { 2538 txd = &sc_if->msk_cdata.msk_txdesc[i]; 2539 if (txd->tx_dmamap) { 2540 bus_dmamap_destroy(sc_if->msk_cdata.msk_tx_tag, 2541 txd->tx_dmamap); 2542 txd->tx_dmamap = NULL; 2543 } 2544 } 2545 bus_dma_tag_destroy(sc_if->msk_cdata.msk_tx_tag); 2546 sc_if->msk_cdata.msk_tx_tag = NULL; 2547 } 2548 /* Rx buffers. */ 2549 if (sc_if->msk_cdata.msk_rx_tag) { 2550 for (i = 0; i < MSK_RX_RING_CNT; i++) { 2551 rxd = &sc_if->msk_cdata.msk_rxdesc[i]; 2552 if (rxd->rx_dmamap) { 2553 bus_dmamap_destroy(sc_if->msk_cdata.msk_rx_tag, 2554 rxd->rx_dmamap); 2555 rxd->rx_dmamap = NULL; 2556 } 2557 } 2558 if (sc_if->msk_cdata.msk_rx_sparemap) { 2559 bus_dmamap_destroy(sc_if->msk_cdata.msk_rx_tag, 2560 sc_if->msk_cdata.msk_rx_sparemap); 2561 sc_if->msk_cdata.msk_rx_sparemap = 0; 2562 } 2563 bus_dma_tag_destroy(sc_if->msk_cdata.msk_rx_tag); 2564 sc_if->msk_cdata.msk_rx_tag = NULL; 2565 } 2566 if (sc_if->msk_cdata.msk_parent_tag) { 2567 bus_dma_tag_destroy(sc_if->msk_cdata.msk_parent_tag); 2568 sc_if->msk_cdata.msk_parent_tag = NULL; 2569 } 2570 } 2571 2572 static void 2573 msk_rx_dma_jfree(struct msk_if_softc *sc_if) 2574 { 2575 struct msk_rxdesc *jrxd; 2576 int i; 2577 2578 /* Jumbo Rx ring. */ 2579 if (sc_if->msk_cdata.msk_jumbo_rx_ring_tag) { 2580 if (sc_if->msk_rdata.msk_jumbo_rx_ring_paddr) 2581 bus_dmamap_unload(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 2582 sc_if->msk_cdata.msk_jumbo_rx_ring_map); 2583 if (sc_if->msk_rdata.msk_jumbo_rx_ring) 2584 bus_dmamem_free(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 2585 sc_if->msk_rdata.msk_jumbo_rx_ring, 2586 sc_if->msk_cdata.msk_jumbo_rx_ring_map); 2587 sc_if->msk_rdata.msk_jumbo_rx_ring = NULL; 2588 sc_if->msk_rdata.msk_jumbo_rx_ring_paddr = 0; 2589 bus_dma_tag_destroy(sc_if->msk_cdata.msk_jumbo_rx_ring_tag); 2590 sc_if->msk_cdata.msk_jumbo_rx_ring_tag = NULL; 2591 } 2592 /* Jumbo Rx buffers. */ 2593 if (sc_if->msk_cdata.msk_jumbo_rx_tag) { 2594 for (i = 0; i < MSK_JUMBO_RX_RING_CNT; i++) { 2595 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[i]; 2596 if (jrxd->rx_dmamap) { 2597 bus_dmamap_destroy( 2598 sc_if->msk_cdata.msk_jumbo_rx_tag, 2599 jrxd->rx_dmamap); 2600 jrxd->rx_dmamap = NULL; 2601 } 2602 } 2603 if (sc_if->msk_cdata.msk_jumbo_rx_sparemap) { 2604 bus_dmamap_destroy(sc_if->msk_cdata.msk_jumbo_rx_tag, 2605 sc_if->msk_cdata.msk_jumbo_rx_sparemap); 2606 sc_if->msk_cdata.msk_jumbo_rx_sparemap = 0; 2607 } 2608 bus_dma_tag_destroy(sc_if->msk_cdata.msk_jumbo_rx_tag); 2609 sc_if->msk_cdata.msk_jumbo_rx_tag = NULL; 2610 } 2611 } 2612 2613 static int 2614 msk_encap(struct msk_if_softc *sc_if, struct mbuf **m_head) 2615 { 2616 struct msk_txdesc *txd, *txd_last; 2617 struct msk_tx_desc *tx_le; 2618 struct mbuf *m; 2619 bus_dmamap_t map; 2620 bus_dma_segment_t txsegs[MSK_MAXTXSEGS]; 2621 uint32_t control, csum, prod, si; 2622 uint16_t offset, tcp_offset, tso_mtu; 2623 int error, i, nseg, tso; 2624 2625 MSK_IF_LOCK_ASSERT(sc_if); 2626 2627 tcp_offset = offset = 0; 2628 m = *m_head; 2629 if (((sc_if->msk_flags & MSK_FLAG_AUTOTX_CSUM) == 0 && 2630 (m->m_pkthdr.csum_flags & MSK_CSUM_FEATURES) != 0) || 2631 ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0 && 2632 (m->m_pkthdr.csum_flags & CSUM_TSO) != 0)) { 2633 /* 2634 * Since mbuf has no protocol specific structure information 2635 * in it we have to inspect protocol information here to 2636 * setup TSO and checksum offload. I don't know why Marvell 2637 * made a such decision in chip design because other GigE 2638 * hardwares normally takes care of all these chores in 2639 * hardware. However, TSO performance of Yukon II is very 2640 * good such that it's worth to implement it. 2641 */ 2642 struct ether_header *eh; 2643 struct ip *ip; 2644 struct tcphdr *tcp; 2645 2646 if (M_WRITABLE(m) == 0) { 2647 /* Get a writable copy. */ 2648 m = m_dup(*m_head, M_NOWAIT); 2649 m_freem(*m_head); 2650 if (m == NULL) { 2651 *m_head = NULL; 2652 return (ENOBUFS); 2653 } 2654 *m_head = m; 2655 } 2656 2657 offset = sizeof(struct ether_header); 2658 m = m_pullup(m, offset); 2659 if (m == NULL) { 2660 *m_head = NULL; 2661 return (ENOBUFS); 2662 } 2663 eh = mtod(m, struct ether_header *); 2664 /* Check if hardware VLAN insertion is off. */ 2665 if (eh->ether_type == htons(ETHERTYPE_VLAN)) { 2666 offset = sizeof(struct ether_vlan_header); 2667 m = m_pullup(m, offset); 2668 if (m == NULL) { 2669 *m_head = NULL; 2670 return (ENOBUFS); 2671 } 2672 } 2673 m = m_pullup(m, offset + sizeof(struct ip)); 2674 if (m == NULL) { 2675 *m_head = NULL; 2676 return (ENOBUFS); 2677 } 2678 ip = (struct ip *)(mtod(m, char *) + offset); 2679 offset += (ip->ip_hl << 2); 2680 tcp_offset = offset; 2681 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 2682 m = m_pullup(m, offset + sizeof(struct tcphdr)); 2683 if (m == NULL) { 2684 *m_head = NULL; 2685 return (ENOBUFS); 2686 } 2687 tcp = (struct tcphdr *)(mtod(m, char *) + offset); 2688 offset += (tcp->th_off << 2); 2689 } else if ((sc_if->msk_flags & MSK_FLAG_AUTOTX_CSUM) == 0 && 2690 (m->m_pkthdr.len < MSK_MIN_FRAMELEN) && 2691 (m->m_pkthdr.csum_flags & CSUM_TCP) != 0) { 2692 /* 2693 * It seems that Yukon II has Tx checksum offload bug 2694 * for small TCP packets that's less than 60 bytes in 2695 * size (e.g. TCP window probe packet, pure ACK packet). 2696 * Common work around like padding with zeros to make 2697 * the frame minimum ethernet frame size didn't work at 2698 * all. 2699 * Instead of disabling checksum offload completely we 2700 * resort to S/W checksum routine when we encounter 2701 * short TCP frames. 2702 * Short UDP packets appear to be handled correctly by 2703 * Yukon II. Also I assume this bug does not happen on 2704 * controllers that use newer descriptor format or 2705 * automatic Tx checksum calculation. 2706 */ 2707 m = m_pullup(m, offset + sizeof(struct tcphdr)); 2708 if (m == NULL) { 2709 *m_head = NULL; 2710 return (ENOBUFS); 2711 } 2712 *(uint16_t *)(m->m_data + offset + 2713 m->m_pkthdr.csum_data) = in_cksum_skip(m, 2714 m->m_pkthdr.len, offset); 2715 m->m_pkthdr.csum_flags &= ~CSUM_TCP; 2716 } 2717 *m_head = m; 2718 } 2719 2720 prod = sc_if->msk_cdata.msk_tx_prod; 2721 txd = &sc_if->msk_cdata.msk_txdesc[prod]; 2722 txd_last = txd; 2723 map = txd->tx_dmamap; 2724 error = bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_tx_tag, map, 2725 *m_head, txsegs, &nseg, BUS_DMA_NOWAIT); 2726 if (error == EFBIG) { 2727 m = m_collapse(*m_head, M_NOWAIT, MSK_MAXTXSEGS); 2728 if (m == NULL) { 2729 m_freem(*m_head); 2730 *m_head = NULL; 2731 return (ENOBUFS); 2732 } 2733 *m_head = m; 2734 error = bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_tx_tag, 2735 map, *m_head, txsegs, &nseg, BUS_DMA_NOWAIT); 2736 if (error != 0) { 2737 m_freem(*m_head); 2738 *m_head = NULL; 2739 return (error); 2740 } 2741 } else if (error != 0) 2742 return (error); 2743 if (nseg == 0) { 2744 m_freem(*m_head); 2745 *m_head = NULL; 2746 return (EIO); 2747 } 2748 2749 /* Check number of available descriptors. */ 2750 if (sc_if->msk_cdata.msk_tx_cnt + nseg >= 2751 (MSK_TX_RING_CNT - MSK_RESERVED_TX_DESC_CNT)) { 2752 bus_dmamap_unload(sc_if->msk_cdata.msk_tx_tag, map); 2753 return (ENOBUFS); 2754 } 2755 2756 control = 0; 2757 tso = 0; 2758 tx_le = NULL; 2759 2760 /* Check TSO support. */ 2761 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 2762 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) != 0) 2763 tso_mtu = m->m_pkthdr.tso_segsz; 2764 else 2765 tso_mtu = offset + m->m_pkthdr.tso_segsz; 2766 if (tso_mtu != sc_if->msk_cdata.msk_tso_mtu) { 2767 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2768 tx_le->msk_addr = htole32(tso_mtu); 2769 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) != 0) 2770 tx_le->msk_control = htole32(OP_MSS | HW_OWNER); 2771 else 2772 tx_le->msk_control = 2773 htole32(OP_LRGLEN | HW_OWNER); 2774 sc_if->msk_cdata.msk_tx_cnt++; 2775 MSK_INC(prod, MSK_TX_RING_CNT); 2776 sc_if->msk_cdata.msk_tso_mtu = tso_mtu; 2777 } 2778 tso++; 2779 } 2780 /* Check if we have a VLAN tag to insert. */ 2781 if ((m->m_flags & M_VLANTAG) != 0) { 2782 if (tx_le == NULL) { 2783 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2784 tx_le->msk_addr = htole32(0); 2785 tx_le->msk_control = htole32(OP_VLAN | HW_OWNER | 2786 htons(m->m_pkthdr.ether_vtag)); 2787 sc_if->msk_cdata.msk_tx_cnt++; 2788 MSK_INC(prod, MSK_TX_RING_CNT); 2789 } else { 2790 tx_le->msk_control |= htole32(OP_VLAN | 2791 htons(m->m_pkthdr.ether_vtag)); 2792 } 2793 control |= INS_VLAN; 2794 } 2795 /* Check if we have to handle checksum offload. */ 2796 if (tso == 0 && (m->m_pkthdr.csum_flags & MSK_CSUM_FEATURES) != 0) { 2797 if ((sc_if->msk_flags & MSK_FLAG_AUTOTX_CSUM) != 0) 2798 control |= CALSUM; 2799 else { 2800 control |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM; 2801 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0) 2802 control |= UDPTCP; 2803 /* Checksum write position. */ 2804 csum = (tcp_offset + m->m_pkthdr.csum_data) & 0xffff; 2805 /* Checksum start position. */ 2806 csum |= (uint32_t)tcp_offset << 16; 2807 if (csum != sc_if->msk_cdata.msk_last_csum) { 2808 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2809 tx_le->msk_addr = htole32(csum); 2810 tx_le->msk_control = htole32(1 << 16 | 2811 (OP_TCPLISW | HW_OWNER)); 2812 sc_if->msk_cdata.msk_tx_cnt++; 2813 MSK_INC(prod, MSK_TX_RING_CNT); 2814 sc_if->msk_cdata.msk_last_csum = csum; 2815 } 2816 } 2817 } 2818 2819 #ifdef MSK_64BIT_DMA 2820 if (MSK_ADDR_HI(txsegs[0].ds_addr) != 2821 sc_if->msk_cdata.msk_tx_high_addr) { 2822 sc_if->msk_cdata.msk_tx_high_addr = 2823 MSK_ADDR_HI(txsegs[0].ds_addr); 2824 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2825 tx_le->msk_addr = htole32(MSK_ADDR_HI(txsegs[0].ds_addr)); 2826 tx_le->msk_control = htole32(OP_ADDR64 | HW_OWNER); 2827 sc_if->msk_cdata.msk_tx_cnt++; 2828 MSK_INC(prod, MSK_TX_RING_CNT); 2829 } 2830 #endif 2831 si = prod; 2832 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2833 tx_le->msk_addr = htole32(MSK_ADDR_LO(txsegs[0].ds_addr)); 2834 if (tso == 0) 2835 tx_le->msk_control = htole32(txsegs[0].ds_len | control | 2836 OP_PACKET); 2837 else 2838 tx_le->msk_control = htole32(txsegs[0].ds_len | control | 2839 OP_LARGESEND); 2840 sc_if->msk_cdata.msk_tx_cnt++; 2841 MSK_INC(prod, MSK_TX_RING_CNT); 2842 2843 for (i = 1; i < nseg; i++) { 2844 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2845 #ifdef MSK_64BIT_DMA 2846 if (MSK_ADDR_HI(txsegs[i].ds_addr) != 2847 sc_if->msk_cdata.msk_tx_high_addr) { 2848 sc_if->msk_cdata.msk_tx_high_addr = 2849 MSK_ADDR_HI(txsegs[i].ds_addr); 2850 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2851 tx_le->msk_addr = 2852 htole32(MSK_ADDR_HI(txsegs[i].ds_addr)); 2853 tx_le->msk_control = htole32(OP_ADDR64 | HW_OWNER); 2854 sc_if->msk_cdata.msk_tx_cnt++; 2855 MSK_INC(prod, MSK_TX_RING_CNT); 2856 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2857 } 2858 #endif 2859 tx_le->msk_addr = htole32(MSK_ADDR_LO(txsegs[i].ds_addr)); 2860 tx_le->msk_control = htole32(txsegs[i].ds_len | control | 2861 OP_BUFFER | HW_OWNER); 2862 sc_if->msk_cdata.msk_tx_cnt++; 2863 MSK_INC(prod, MSK_TX_RING_CNT); 2864 } 2865 /* Update producer index. */ 2866 sc_if->msk_cdata.msk_tx_prod = prod; 2867 2868 /* Set EOP on the last descriptor. */ 2869 prod = (prod + MSK_TX_RING_CNT - 1) % MSK_TX_RING_CNT; 2870 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2871 tx_le->msk_control |= htole32(EOP); 2872 2873 /* Turn the first descriptor ownership to hardware. */ 2874 tx_le = &sc_if->msk_rdata.msk_tx_ring[si]; 2875 tx_le->msk_control |= htole32(HW_OWNER); 2876 2877 txd = &sc_if->msk_cdata.msk_txdesc[prod]; 2878 map = txd_last->tx_dmamap; 2879 txd_last->tx_dmamap = txd->tx_dmamap; 2880 txd->tx_dmamap = map; 2881 txd->tx_m = m; 2882 2883 /* Sync descriptors. */ 2884 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_tag, map, BUS_DMASYNC_PREWRITE); 2885 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_ring_tag, 2886 sc_if->msk_cdata.msk_tx_ring_map, 2887 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2888 2889 return (0); 2890 } 2891 2892 static void 2893 msk_start(if_t ifp) 2894 { 2895 struct msk_if_softc *sc_if; 2896 2897 sc_if = if_getsoftc(ifp); 2898 MSK_IF_LOCK(sc_if); 2899 msk_start_locked(ifp); 2900 MSK_IF_UNLOCK(sc_if); 2901 } 2902 2903 static void 2904 msk_start_locked(if_t ifp) 2905 { 2906 struct msk_if_softc *sc_if; 2907 struct mbuf *m_head; 2908 int enq; 2909 2910 sc_if = if_getsoftc(ifp); 2911 MSK_IF_LOCK_ASSERT(sc_if); 2912 2913 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2914 IFF_DRV_RUNNING || (sc_if->msk_flags & MSK_FLAG_LINK) == 0) 2915 return; 2916 2917 for (enq = 0; !if_sendq_empty(ifp) && 2918 sc_if->msk_cdata.msk_tx_cnt < 2919 (MSK_TX_RING_CNT - MSK_RESERVED_TX_DESC_CNT); ) { 2920 m_head = if_dequeue(ifp); 2921 if (m_head == NULL) 2922 break; 2923 /* 2924 * Pack the data into the transmit ring. If we 2925 * don't have room, set the OACTIVE flag and wait 2926 * for the NIC to drain the ring. 2927 */ 2928 if (msk_encap(sc_if, &m_head) != 0) { 2929 if (m_head == NULL) 2930 break; 2931 if_sendq_prepend(ifp, m_head); 2932 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); 2933 break; 2934 } 2935 2936 enq++; 2937 /* 2938 * If there's a BPF listener, bounce a copy of this frame 2939 * to him. 2940 */ 2941 ETHER_BPF_MTAP(ifp, m_head); 2942 } 2943 2944 if (enq > 0) { 2945 /* Transmit */ 2946 CSR_WRITE_2(sc_if->msk_softc, 2947 Y2_PREF_Q_ADDR(sc_if->msk_txq, PREF_UNIT_PUT_IDX_REG), 2948 sc_if->msk_cdata.msk_tx_prod); 2949 2950 /* Set a timeout in case the chip goes out to lunch. */ 2951 sc_if->msk_watchdog_timer = MSK_TX_TIMEOUT; 2952 } 2953 } 2954 2955 static void 2956 msk_watchdog(struct msk_if_softc *sc_if) 2957 { 2958 if_t ifp; 2959 2960 MSK_IF_LOCK_ASSERT(sc_if); 2961 2962 if (sc_if->msk_watchdog_timer == 0 || --sc_if->msk_watchdog_timer) 2963 return; 2964 ifp = sc_if->msk_ifp; 2965 if ((sc_if->msk_flags & MSK_FLAG_LINK) == 0) { 2966 if (bootverbose) 2967 if_printf(sc_if->msk_ifp, "watchdog timeout " 2968 "(missed link)\n"); 2969 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 2970 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 2971 msk_init_locked(sc_if); 2972 return; 2973 } 2974 2975 if_printf(ifp, "watchdog timeout\n"); 2976 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 2977 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 2978 msk_init_locked(sc_if); 2979 if (!if_sendq_empty(ifp)) 2980 msk_start_locked(ifp); 2981 } 2982 2983 static int 2984 mskc_shutdown(device_t dev) 2985 { 2986 struct msk_softc *sc; 2987 int i; 2988 2989 sc = device_get_softc(dev); 2990 MSK_LOCK(sc); 2991 for (i = 0; i < sc->msk_num_port; i++) { 2992 if (sc->msk_if[i] != NULL && sc->msk_if[i]->msk_ifp != NULL && 2993 ((if_getdrvflags(sc->msk_if[i]->msk_ifp) & 2994 IFF_DRV_RUNNING) != 0)) 2995 msk_stop(sc->msk_if[i]); 2996 } 2997 MSK_UNLOCK(sc); 2998 2999 /* Put hardware reset. */ 3000 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); 3001 return (0); 3002 } 3003 3004 static int 3005 mskc_suspend(device_t dev) 3006 { 3007 struct msk_softc *sc; 3008 int i; 3009 3010 sc = device_get_softc(dev); 3011 3012 MSK_LOCK(sc); 3013 3014 for (i = 0; i < sc->msk_num_port; i++) { 3015 if (sc->msk_if[i] != NULL && sc->msk_if[i]->msk_ifp != NULL && 3016 ((if_getdrvflags(sc->msk_if[i]->msk_ifp) & 3017 IFF_DRV_RUNNING) != 0)) 3018 msk_stop(sc->msk_if[i]); 3019 } 3020 3021 /* Disable all interrupts. */ 3022 CSR_WRITE_4(sc, B0_IMSK, 0); 3023 CSR_READ_4(sc, B0_IMSK); 3024 CSR_WRITE_4(sc, B0_HWE_IMSK, 0); 3025 CSR_READ_4(sc, B0_HWE_IMSK); 3026 3027 msk_phy_power(sc, MSK_PHY_POWERDOWN); 3028 3029 /* Put hardware reset. */ 3030 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); 3031 sc->msk_pflags |= MSK_FLAG_SUSPEND; 3032 3033 MSK_UNLOCK(sc); 3034 3035 return (0); 3036 } 3037 3038 static int 3039 mskc_resume(device_t dev) 3040 { 3041 struct msk_softc *sc; 3042 int i; 3043 3044 sc = device_get_softc(dev); 3045 3046 MSK_LOCK(sc); 3047 3048 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_3, 0); 3049 mskc_reset(sc); 3050 for (i = 0; i < sc->msk_num_port; i++) { 3051 if (sc->msk_if[i] != NULL && sc->msk_if[i]->msk_ifp != NULL && 3052 ((if_getflags(sc->msk_if[i]->msk_ifp) & IFF_UP) != 0)) { 3053 if_setdrvflagbits(sc->msk_if[i]->msk_ifp, 0, 3054 IFF_DRV_RUNNING); 3055 msk_init_locked(sc->msk_if[i]); 3056 } 3057 } 3058 sc->msk_pflags &= ~MSK_FLAG_SUSPEND; 3059 3060 MSK_UNLOCK(sc); 3061 3062 return (0); 3063 } 3064 3065 #ifndef __NO_STRICT_ALIGNMENT 3066 static __inline void 3067 msk_fixup_rx(struct mbuf *m) 3068 { 3069 int i; 3070 uint16_t *src, *dst; 3071 3072 src = mtod(m, uint16_t *); 3073 dst = src - 3; 3074 3075 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 3076 *dst++ = *src++; 3077 3078 m->m_data -= (MSK_RX_BUF_ALIGN - ETHER_ALIGN); 3079 } 3080 #endif 3081 3082 static __inline void 3083 msk_rxcsum(struct msk_if_softc *sc_if, uint32_t control, struct mbuf *m) 3084 { 3085 struct ether_header *eh; 3086 struct ip *ip; 3087 struct udphdr *uh; 3088 int32_t hlen, len, pktlen, temp32; 3089 uint16_t csum, *opts; 3090 3091 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) != 0) { 3092 if ((control & (CSS_IPV4 | CSS_IPFRAG)) == CSS_IPV4) { 3093 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 3094 if ((control & CSS_IPV4_CSUM_OK) != 0) 3095 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 3096 if ((control & (CSS_TCP | CSS_UDP)) != 0 && 3097 (control & (CSS_TCPUDP_CSUM_OK)) != 0) { 3098 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID | 3099 CSUM_PSEUDO_HDR; 3100 m->m_pkthdr.csum_data = 0xffff; 3101 } 3102 } 3103 return; 3104 } 3105 /* 3106 * Marvell Yukon controllers that support OP_RXCHKS has known 3107 * to have various Rx checksum offloading bugs. These 3108 * controllers can be configured to compute simple checksum 3109 * at two different positions. So we can compute IP and TCP/UDP 3110 * checksum at the same time. We intentionally have controller 3111 * compute TCP/UDP checksum twice by specifying the same 3112 * checksum start position and compare the result. If the value 3113 * is different it would indicate the hardware logic was wrong. 3114 */ 3115 if ((sc_if->msk_csum & 0xFFFF) != (sc_if->msk_csum >> 16)) { 3116 if (bootverbose) 3117 device_printf(sc_if->msk_if_dev, 3118 "Rx checksum value mismatch!\n"); 3119 return; 3120 } 3121 pktlen = m->m_pkthdr.len; 3122 if (pktlen < sizeof(struct ether_header) + sizeof(struct ip)) 3123 return; 3124 eh = mtod(m, struct ether_header *); 3125 if (eh->ether_type != htons(ETHERTYPE_IP)) 3126 return; 3127 ip = (struct ip *)(eh + 1); 3128 if (ip->ip_v != IPVERSION) 3129 return; 3130 3131 hlen = ip->ip_hl << 2; 3132 pktlen -= sizeof(struct ether_header); 3133 if (hlen < sizeof(struct ip)) 3134 return; 3135 if (ntohs(ip->ip_len) < hlen) 3136 return; 3137 if (ntohs(ip->ip_len) != pktlen) 3138 return; 3139 if (ip->ip_off & htons(IP_MF | IP_OFFMASK)) 3140 return; /* can't handle fragmented packet. */ 3141 3142 switch (ip->ip_p) { 3143 case IPPROTO_TCP: 3144 if (pktlen < (hlen + sizeof(struct tcphdr))) 3145 return; 3146 break; 3147 case IPPROTO_UDP: 3148 if (pktlen < (hlen + sizeof(struct udphdr))) 3149 return; 3150 uh = (struct udphdr *)((caddr_t)ip + hlen); 3151 if (uh->uh_sum == 0) 3152 return; /* no checksum */ 3153 break; 3154 default: 3155 return; 3156 } 3157 csum = bswap16(sc_if->msk_csum & 0xFFFF); 3158 /* Checksum fixup for IP options. */ 3159 len = hlen - sizeof(struct ip); 3160 if (len > 0) { 3161 opts = (uint16_t *)(ip + 1); 3162 for (; len > 0; len -= sizeof(uint16_t), opts++) { 3163 temp32 = csum - *opts; 3164 temp32 = (temp32 >> 16) + (temp32 & 65535); 3165 csum = temp32 & 65535; 3166 } 3167 } 3168 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID; 3169 m->m_pkthdr.csum_data = csum; 3170 } 3171 3172 static void 3173 msk_rxeof(struct msk_if_softc *sc_if, uint32_t status, uint32_t control, 3174 int len) 3175 { 3176 struct mbuf *m; 3177 if_t ifp; 3178 struct msk_rxdesc *rxd; 3179 int cons, rxlen; 3180 3181 ifp = sc_if->msk_ifp; 3182 3183 MSK_IF_LOCK_ASSERT(sc_if); 3184 3185 cons = sc_if->msk_cdata.msk_rx_cons; 3186 do { 3187 rxlen = status >> 16; 3188 if ((status & GMR_FS_VLAN) != 0 && 3189 (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0) 3190 rxlen -= ETHER_VLAN_ENCAP_LEN; 3191 if ((sc_if->msk_flags & MSK_FLAG_NORXCHK) != 0) { 3192 /* 3193 * For controllers that returns bogus status code 3194 * just do minimal check and let upper stack 3195 * handle this frame. 3196 */ 3197 if (len > MSK_MAX_FRAMELEN || len < ETHER_HDR_LEN) { 3198 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 3199 msk_discard_rxbuf(sc_if, cons); 3200 break; 3201 } 3202 } else if (len > sc_if->msk_framesize || 3203 ((status & GMR_FS_ANY_ERR) != 0) || 3204 ((status & GMR_FS_RX_OK) == 0) || (rxlen != len)) { 3205 /* Don't count flow-control packet as errors. */ 3206 if ((status & GMR_FS_GOOD_FC) == 0) 3207 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 3208 msk_discard_rxbuf(sc_if, cons); 3209 break; 3210 } 3211 #ifdef MSK_64BIT_DMA 3212 rxd = &sc_if->msk_cdata.msk_rxdesc[(cons + 1) % 3213 MSK_RX_RING_CNT]; 3214 #else 3215 rxd = &sc_if->msk_cdata.msk_rxdesc[cons]; 3216 #endif 3217 m = rxd->rx_m; 3218 if (msk_newbuf(sc_if, cons) != 0) { 3219 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 3220 /* Reuse old buffer. */ 3221 msk_discard_rxbuf(sc_if, cons); 3222 break; 3223 } 3224 m->m_pkthdr.rcvif = ifp; 3225 m->m_pkthdr.len = m->m_len = len; 3226 #ifndef __NO_STRICT_ALIGNMENT 3227 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) != 0) 3228 msk_fixup_rx(m); 3229 #endif 3230 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 3231 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0) 3232 msk_rxcsum(sc_if, control, m); 3233 /* Check for VLAN tagged packets. */ 3234 if ((status & GMR_FS_VLAN) != 0 && 3235 (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0) { 3236 m->m_pkthdr.ether_vtag = sc_if->msk_vtag; 3237 m->m_flags |= M_VLANTAG; 3238 } 3239 MSK_IF_UNLOCK(sc_if); 3240 if_input(ifp, m); 3241 MSK_IF_LOCK(sc_if); 3242 } while (0); 3243 3244 MSK_RX_INC(sc_if->msk_cdata.msk_rx_cons, MSK_RX_RING_CNT); 3245 MSK_RX_INC(sc_if->msk_cdata.msk_rx_prod, MSK_RX_RING_CNT); 3246 } 3247 3248 static void 3249 msk_jumbo_rxeof(struct msk_if_softc *sc_if, uint32_t status, uint32_t control, 3250 int len) 3251 { 3252 struct mbuf *m; 3253 if_t ifp; 3254 struct msk_rxdesc *jrxd; 3255 int cons, rxlen; 3256 3257 ifp = sc_if->msk_ifp; 3258 3259 MSK_IF_LOCK_ASSERT(sc_if); 3260 3261 cons = sc_if->msk_cdata.msk_rx_cons; 3262 do { 3263 rxlen = status >> 16; 3264 if ((status & GMR_FS_VLAN) != 0 && 3265 (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0) 3266 rxlen -= ETHER_VLAN_ENCAP_LEN; 3267 if (len > sc_if->msk_framesize || 3268 ((status & GMR_FS_ANY_ERR) != 0) || 3269 ((status & GMR_FS_RX_OK) == 0) || (rxlen != len)) { 3270 /* Don't count flow-control packet as errors. */ 3271 if ((status & GMR_FS_GOOD_FC) == 0) 3272 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 3273 msk_discard_jumbo_rxbuf(sc_if, cons); 3274 break; 3275 } 3276 #ifdef MSK_64BIT_DMA 3277 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[(cons + 1) % 3278 MSK_JUMBO_RX_RING_CNT]; 3279 #else 3280 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[cons]; 3281 #endif 3282 m = jrxd->rx_m; 3283 if (msk_jumbo_newbuf(sc_if, cons) != 0) { 3284 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 3285 /* Reuse old buffer. */ 3286 msk_discard_jumbo_rxbuf(sc_if, cons); 3287 break; 3288 } 3289 m->m_pkthdr.rcvif = ifp; 3290 m->m_pkthdr.len = m->m_len = len; 3291 #ifndef __NO_STRICT_ALIGNMENT 3292 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) != 0) 3293 msk_fixup_rx(m); 3294 #endif 3295 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 3296 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0) 3297 msk_rxcsum(sc_if, control, m); 3298 /* Check for VLAN tagged packets. */ 3299 if ((status & GMR_FS_VLAN) != 0 && 3300 (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0) { 3301 m->m_pkthdr.ether_vtag = sc_if->msk_vtag; 3302 m->m_flags |= M_VLANTAG; 3303 } 3304 MSK_IF_UNLOCK(sc_if); 3305 if_input(ifp, m); 3306 MSK_IF_LOCK(sc_if); 3307 } while (0); 3308 3309 MSK_RX_INC(sc_if->msk_cdata.msk_rx_cons, MSK_JUMBO_RX_RING_CNT); 3310 MSK_RX_INC(sc_if->msk_cdata.msk_rx_prod, MSK_JUMBO_RX_RING_CNT); 3311 } 3312 3313 static void 3314 msk_txeof(struct msk_if_softc *sc_if, int idx) 3315 { 3316 struct msk_txdesc *txd; 3317 struct msk_tx_desc *cur_tx; 3318 if_t ifp; 3319 uint32_t control; 3320 int cons, prog; 3321 3322 MSK_IF_LOCK_ASSERT(sc_if); 3323 3324 ifp = sc_if->msk_ifp; 3325 3326 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_ring_tag, 3327 sc_if->msk_cdata.msk_tx_ring_map, 3328 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3329 /* 3330 * Go through our tx ring and free mbufs for those 3331 * frames that have been sent. 3332 */ 3333 cons = sc_if->msk_cdata.msk_tx_cons; 3334 prog = 0; 3335 for (; cons != idx; MSK_INC(cons, MSK_TX_RING_CNT)) { 3336 if (sc_if->msk_cdata.msk_tx_cnt <= 0) 3337 break; 3338 prog++; 3339 cur_tx = &sc_if->msk_rdata.msk_tx_ring[cons]; 3340 control = le32toh(cur_tx->msk_control); 3341 sc_if->msk_cdata.msk_tx_cnt--; 3342 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 3343 if ((control & EOP) == 0) 3344 continue; 3345 txd = &sc_if->msk_cdata.msk_txdesc[cons]; 3346 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_tag, txd->tx_dmamap, 3347 BUS_DMASYNC_POSTWRITE); 3348 bus_dmamap_unload(sc_if->msk_cdata.msk_tx_tag, txd->tx_dmamap); 3349 3350 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 3351 KASSERT(txd->tx_m != NULL, ("%s: freeing NULL mbuf!", 3352 __func__)); 3353 m_freem(txd->tx_m); 3354 txd->tx_m = NULL; 3355 } 3356 3357 if (prog > 0) { 3358 sc_if->msk_cdata.msk_tx_cons = cons; 3359 if (sc_if->msk_cdata.msk_tx_cnt == 0) 3360 sc_if->msk_watchdog_timer = 0; 3361 /* No need to sync LEs as we didn't update LEs. */ 3362 } 3363 } 3364 3365 static void 3366 msk_tick(void *xsc_if) 3367 { 3368 struct epoch_tracker et; 3369 struct msk_if_softc *sc_if; 3370 struct mii_data *mii; 3371 3372 sc_if = xsc_if; 3373 3374 MSK_IF_LOCK_ASSERT(sc_if); 3375 3376 mii = device_get_softc(sc_if->msk_miibus); 3377 3378 mii_tick(mii); 3379 if ((sc_if->msk_flags & MSK_FLAG_LINK) == 0) 3380 msk_miibus_statchg(sc_if->msk_if_dev); 3381 NET_EPOCH_ENTER(et); 3382 msk_handle_events(sc_if->msk_softc); 3383 NET_EPOCH_EXIT(et); 3384 msk_watchdog(sc_if); 3385 callout_reset(&sc_if->msk_tick_ch, hz, msk_tick, sc_if); 3386 } 3387 3388 static void 3389 msk_intr_phy(struct msk_if_softc *sc_if) 3390 { 3391 uint16_t status; 3392 3393 msk_phy_readreg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_STAT); 3394 status = msk_phy_readreg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_STAT); 3395 /* Handle FIFO Underrun/Overflow? */ 3396 if ((status & PHY_M_IS_FIFO_ERROR)) 3397 device_printf(sc_if->msk_if_dev, 3398 "PHY FIFO underrun/overflow.\n"); 3399 } 3400 3401 static void 3402 msk_intr_gmac(struct msk_if_softc *sc_if) 3403 { 3404 struct msk_softc *sc; 3405 uint8_t status; 3406 3407 sc = sc_if->msk_softc; 3408 status = CSR_READ_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_SRC)); 3409 3410 /* GMAC Rx FIFO overrun. */ 3411 if ((status & GM_IS_RX_FF_OR) != 0) 3412 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), 3413 GMF_CLI_RX_FO); 3414 /* GMAC Tx FIFO underrun. */ 3415 if ((status & GM_IS_TX_FF_UR) != 0) { 3416 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 3417 GMF_CLI_TX_FU); 3418 device_printf(sc_if->msk_if_dev, "Tx FIFO underrun!\n"); 3419 /* 3420 * XXX 3421 * In case of Tx underrun, we may need to flush/reset 3422 * Tx MAC but that would also require resynchronization 3423 * with status LEs. Reinitializing status LEs would 3424 * affect other port in dual MAC configuration so it 3425 * should be avoided as possible as we can. 3426 * Due to lack of documentation it's all vague guess but 3427 * it needs more investigation. 3428 */ 3429 } 3430 } 3431 3432 static void 3433 msk_handle_hwerr(struct msk_if_softc *sc_if, uint32_t status) 3434 { 3435 struct msk_softc *sc; 3436 3437 sc = sc_if->msk_softc; 3438 if ((status & Y2_IS_PAR_RD1) != 0) { 3439 device_printf(sc_if->msk_if_dev, 3440 "RAM buffer read parity error\n"); 3441 /* Clear IRQ. */ 3442 CSR_WRITE_2(sc, SELECT_RAM_BUFFER(sc_if->msk_port, B3_RI_CTRL), 3443 RI_CLR_RD_PERR); 3444 } 3445 if ((status & Y2_IS_PAR_WR1) != 0) { 3446 device_printf(sc_if->msk_if_dev, 3447 "RAM buffer write parity error\n"); 3448 /* Clear IRQ. */ 3449 CSR_WRITE_2(sc, SELECT_RAM_BUFFER(sc_if->msk_port, B3_RI_CTRL), 3450 RI_CLR_WR_PERR); 3451 } 3452 if ((status & Y2_IS_PAR_MAC1) != 0) { 3453 device_printf(sc_if->msk_if_dev, "Tx MAC parity error\n"); 3454 /* Clear IRQ. */ 3455 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 3456 GMF_CLI_TX_PE); 3457 } 3458 if ((status & Y2_IS_PAR_RX1) != 0) { 3459 device_printf(sc_if->msk_if_dev, "Rx parity error\n"); 3460 /* Clear IRQ. */ 3461 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_CLR_IRQ_PAR); 3462 } 3463 if ((status & (Y2_IS_TCP_TXS1 | Y2_IS_TCP_TXA1)) != 0) { 3464 device_printf(sc_if->msk_if_dev, "TCP segmentation error\n"); 3465 /* Clear IRQ. */ 3466 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_CLR_IRQ_TCP); 3467 } 3468 } 3469 3470 static void 3471 msk_intr_hwerr(struct msk_softc *sc) 3472 { 3473 uint32_t status; 3474 uint32_t tlphead[4]; 3475 3476 status = CSR_READ_4(sc, B0_HWE_ISRC); 3477 /* Time Stamp timer overflow. */ 3478 if ((status & Y2_IS_TIST_OV) != 0) 3479 CSR_WRITE_1(sc, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ); 3480 if ((status & Y2_IS_PCI_NEXP) != 0) { 3481 /* 3482 * PCI Express Error occurred which is not described in PEX 3483 * spec. 3484 * This error is also mapped either to Master Abort( 3485 * Y2_IS_MST_ERR) or Target Abort (Y2_IS_IRQ_STAT) bit and 3486 * can only be cleared there. 3487 */ 3488 device_printf(sc->msk_dev, 3489 "PCI Express protocol violation error\n"); 3490 } 3491 3492 if ((status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) != 0) { 3493 uint16_t v16; 3494 3495 if ((status & Y2_IS_MST_ERR) != 0) 3496 device_printf(sc->msk_dev, 3497 "unexpected IRQ Status error\n"); 3498 else 3499 device_printf(sc->msk_dev, 3500 "unexpected IRQ Master error\n"); 3501 /* Reset all bits in the PCI status register. */ 3502 v16 = pci_read_config(sc->msk_dev, PCIR_STATUS, 2); 3503 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON); 3504 pci_write_config(sc->msk_dev, PCIR_STATUS, v16 | 3505 PCIM_STATUS_PERR | PCIM_STATUS_SERR | PCIM_STATUS_RMABORT | 3506 PCIM_STATUS_RTABORT | PCIM_STATUS_MDPERR, 2); 3507 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 3508 } 3509 3510 /* Check for PCI Express Uncorrectable Error. */ 3511 if ((status & Y2_IS_PCI_EXP) != 0) { 3512 uint32_t v32; 3513 3514 /* 3515 * On PCI Express bus bridges are called root complexes (RC). 3516 * PCI Express errors are recognized by the root complex too, 3517 * which requests the system to handle the problem. After 3518 * error occurrence it may be that no access to the adapter 3519 * may be performed any longer. 3520 */ 3521 3522 v32 = CSR_PCI_READ_4(sc, PEX_UNC_ERR_STAT); 3523 if ((v32 & PEX_UNSUP_REQ) != 0) { 3524 /* Ignore unsupported request error. */ 3525 device_printf(sc->msk_dev, 3526 "Uncorrectable PCI Express error\n"); 3527 } 3528 if ((v32 & (PEX_FATAL_ERRORS | PEX_POIS_TLP)) != 0) { 3529 int i; 3530 3531 /* Get TLP header form Log Registers. */ 3532 for (i = 0; i < 4; i++) 3533 tlphead[i] = CSR_PCI_READ_4(sc, 3534 PEX_HEADER_LOG + i * 4); 3535 /* Check for vendor defined broadcast message. */ 3536 if (!(tlphead[0] == 0x73004001 && tlphead[1] == 0x7f)) { 3537 sc->msk_intrhwemask &= ~Y2_IS_PCI_EXP; 3538 CSR_WRITE_4(sc, B0_HWE_IMSK, 3539 sc->msk_intrhwemask); 3540 CSR_READ_4(sc, B0_HWE_IMSK); 3541 } 3542 } 3543 /* Clear the interrupt. */ 3544 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON); 3545 CSR_PCI_WRITE_4(sc, PEX_UNC_ERR_STAT, 0xffffffff); 3546 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 3547 } 3548 3549 if ((status & Y2_HWE_L1_MASK) != 0 && sc->msk_if[MSK_PORT_A] != NULL) 3550 msk_handle_hwerr(sc->msk_if[MSK_PORT_A], status); 3551 if ((status & Y2_HWE_L2_MASK) != 0 && sc->msk_if[MSK_PORT_B] != NULL) 3552 msk_handle_hwerr(sc->msk_if[MSK_PORT_B], status >> 8); 3553 } 3554 3555 static __inline void 3556 msk_rxput(struct msk_if_softc *sc_if) 3557 { 3558 struct msk_softc *sc; 3559 3560 sc = sc_if->msk_softc; 3561 if (sc_if->msk_framesize > (MCLBYTES - MSK_RX_BUF_ALIGN)) 3562 bus_dmamap_sync( 3563 sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 3564 sc_if->msk_cdata.msk_jumbo_rx_ring_map, 3565 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3566 else 3567 bus_dmamap_sync( 3568 sc_if->msk_cdata.msk_rx_ring_tag, 3569 sc_if->msk_cdata.msk_rx_ring_map, 3570 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3571 CSR_WRITE_2(sc, Y2_PREF_Q_ADDR(sc_if->msk_rxq, 3572 PREF_UNIT_PUT_IDX_REG), sc_if->msk_cdata.msk_rx_prod); 3573 } 3574 3575 static int 3576 msk_handle_events(struct msk_softc *sc) 3577 { 3578 struct msk_if_softc *sc_if; 3579 int rxput[2]; 3580 struct msk_stat_desc *sd; 3581 uint32_t control, status; 3582 int cons, len, port, rxprog; 3583 3584 if (sc->msk_stat_cons == CSR_READ_2(sc, STAT_PUT_IDX)) 3585 return (0); 3586 3587 /* Sync status LEs. */ 3588 bus_dmamap_sync(sc->msk_stat_tag, sc->msk_stat_map, 3589 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3590 3591 rxput[MSK_PORT_A] = rxput[MSK_PORT_B] = 0; 3592 rxprog = 0; 3593 cons = sc->msk_stat_cons; 3594 for (;;) { 3595 sd = &sc->msk_stat_ring[cons]; 3596 control = le32toh(sd->msk_control); 3597 if ((control & HW_OWNER) == 0) 3598 break; 3599 control &= ~HW_OWNER; 3600 sd->msk_control = htole32(control); 3601 status = le32toh(sd->msk_status); 3602 len = control & STLE_LEN_MASK; 3603 port = (control >> 16) & 0x01; 3604 sc_if = sc->msk_if[port]; 3605 if (sc_if == NULL) { 3606 device_printf(sc->msk_dev, "invalid port opcode " 3607 "0x%08x\n", control & STLE_OP_MASK); 3608 continue; 3609 } 3610 3611 switch (control & STLE_OP_MASK) { 3612 case OP_RXVLAN: 3613 sc_if->msk_vtag = ntohs(len); 3614 break; 3615 case OP_RXCHKSVLAN: 3616 sc_if->msk_vtag = ntohs(len); 3617 /* FALLTHROUGH */ 3618 case OP_RXCHKS: 3619 sc_if->msk_csum = status; 3620 break; 3621 case OP_RXSTAT: 3622 if (!(if_getdrvflags(sc_if->msk_ifp) & IFF_DRV_RUNNING)) 3623 break; 3624 if (sc_if->msk_framesize > 3625 (MCLBYTES - MSK_RX_BUF_ALIGN)) 3626 msk_jumbo_rxeof(sc_if, status, control, len); 3627 else 3628 msk_rxeof(sc_if, status, control, len); 3629 rxprog++; 3630 /* 3631 * Because there is no way to sync single Rx LE 3632 * put the DMA sync operation off until the end of 3633 * event processing. 3634 */ 3635 rxput[port]++; 3636 /* Update prefetch unit if we've passed water mark. */ 3637 if (rxput[port] >= sc_if->msk_cdata.msk_rx_putwm) { 3638 msk_rxput(sc_if); 3639 rxput[port] = 0; 3640 } 3641 break; 3642 case OP_TXINDEXLE: 3643 if (sc->msk_if[MSK_PORT_A] != NULL) 3644 msk_txeof(sc->msk_if[MSK_PORT_A], 3645 status & STLE_TXA1_MSKL); 3646 if (sc->msk_if[MSK_PORT_B] != NULL) 3647 msk_txeof(sc->msk_if[MSK_PORT_B], 3648 ((status & STLE_TXA2_MSKL) >> 3649 STLE_TXA2_SHIFTL) | 3650 ((len & STLE_TXA2_MSKH) << 3651 STLE_TXA2_SHIFTH)); 3652 break; 3653 default: 3654 device_printf(sc->msk_dev, "unhandled opcode 0x%08x\n", 3655 control & STLE_OP_MASK); 3656 break; 3657 } 3658 MSK_INC(cons, sc->msk_stat_count); 3659 if (rxprog > sc->msk_process_limit) 3660 break; 3661 } 3662 3663 sc->msk_stat_cons = cons; 3664 bus_dmamap_sync(sc->msk_stat_tag, sc->msk_stat_map, 3665 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3666 3667 if (rxput[MSK_PORT_A] > 0) 3668 msk_rxput(sc->msk_if[MSK_PORT_A]); 3669 if (rxput[MSK_PORT_B] > 0) 3670 msk_rxput(sc->msk_if[MSK_PORT_B]); 3671 3672 return (sc->msk_stat_cons != CSR_READ_2(sc, STAT_PUT_IDX)); 3673 } 3674 3675 static void 3676 msk_intr(void *xsc) 3677 { 3678 struct msk_softc *sc; 3679 struct msk_if_softc *sc_if0, *sc_if1; 3680 if_t ifp0, ifp1; 3681 uint32_t status; 3682 int domore; 3683 3684 sc = xsc; 3685 MSK_LOCK(sc); 3686 3687 /* Reading B0_Y2_SP_ISRC2 masks further interrupts. */ 3688 status = CSR_READ_4(sc, B0_Y2_SP_ISRC2); 3689 if (status == 0 || status == 0xffffffff || 3690 (sc->msk_pflags & MSK_FLAG_SUSPEND) != 0 || 3691 (status & sc->msk_intrmask) == 0) { 3692 CSR_WRITE_4(sc, B0_Y2_SP_ICR, 2); 3693 MSK_UNLOCK(sc); 3694 return; 3695 } 3696 3697 sc_if0 = sc->msk_if[MSK_PORT_A]; 3698 sc_if1 = sc->msk_if[MSK_PORT_B]; 3699 ifp0 = ifp1 = NULL; 3700 if (sc_if0 != NULL) 3701 ifp0 = sc_if0->msk_ifp; 3702 if (sc_if1 != NULL) 3703 ifp1 = sc_if1->msk_ifp; 3704 3705 if ((status & Y2_IS_IRQ_PHY1) != 0 && sc_if0 != NULL) 3706 msk_intr_phy(sc_if0); 3707 if ((status & Y2_IS_IRQ_PHY2) != 0 && sc_if1 != NULL) 3708 msk_intr_phy(sc_if1); 3709 if ((status & Y2_IS_IRQ_MAC1) != 0 && sc_if0 != NULL) 3710 msk_intr_gmac(sc_if0); 3711 if ((status & Y2_IS_IRQ_MAC2) != 0 && sc_if1 != NULL) 3712 msk_intr_gmac(sc_if1); 3713 if ((status & (Y2_IS_CHK_RX1 | Y2_IS_CHK_RX2)) != 0) { 3714 device_printf(sc->msk_dev, "Rx descriptor error\n"); 3715 sc->msk_intrmask &= ~(Y2_IS_CHK_RX1 | Y2_IS_CHK_RX2); 3716 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask); 3717 CSR_READ_4(sc, B0_IMSK); 3718 } 3719 if ((status & (Y2_IS_CHK_TXA1 | Y2_IS_CHK_TXA2)) != 0) { 3720 device_printf(sc->msk_dev, "Tx descriptor error\n"); 3721 sc->msk_intrmask &= ~(Y2_IS_CHK_TXA1 | Y2_IS_CHK_TXA2); 3722 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask); 3723 CSR_READ_4(sc, B0_IMSK); 3724 } 3725 if ((status & Y2_IS_HW_ERR) != 0) 3726 msk_intr_hwerr(sc); 3727 3728 domore = msk_handle_events(sc); 3729 if ((status & Y2_IS_STAT_BMU) != 0 && domore == 0) 3730 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_CLR_IRQ); 3731 3732 /* Reenable interrupts. */ 3733 CSR_WRITE_4(sc, B0_Y2_SP_ICR, 2); 3734 3735 if (ifp0 != NULL && (if_getdrvflags(ifp0) & IFF_DRV_RUNNING) != 0 && 3736 !if_sendq_empty(ifp0)) 3737 msk_start_locked(ifp0); 3738 if (ifp1 != NULL && (if_getdrvflags(ifp1) & IFF_DRV_RUNNING) != 0 && 3739 !if_sendq_empty(ifp1)) 3740 msk_start_locked(ifp1); 3741 3742 MSK_UNLOCK(sc); 3743 } 3744 3745 static void 3746 msk_set_tx_stfwd(struct msk_if_softc *sc_if) 3747 { 3748 struct msk_softc *sc; 3749 if_t ifp; 3750 3751 ifp = sc_if->msk_ifp; 3752 sc = sc_if->msk_softc; 3753 if ((sc->msk_hw_id == CHIP_ID_YUKON_EX && 3754 sc->msk_hw_rev != CHIP_REV_YU_EX_A0) || 3755 sc->msk_hw_id >= CHIP_ID_YUKON_SUPR) { 3756 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 3757 TX_STFW_ENA); 3758 } else { 3759 if (if_getmtu(ifp) > ETHERMTU) { 3760 /* Set Tx GMAC FIFO Almost Empty Threshold. */ 3761 CSR_WRITE_4(sc, 3762 MR_ADDR(sc_if->msk_port, TX_GMF_AE_THR), 3763 MSK_ECU_JUMBO_WM << 16 | MSK_ECU_AE_THR); 3764 /* Disable Store & Forward mode for Tx. */ 3765 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 3766 TX_STFW_DIS); 3767 } else { 3768 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 3769 TX_STFW_ENA); 3770 } 3771 } 3772 } 3773 3774 static void 3775 msk_init(void *xsc) 3776 { 3777 struct msk_if_softc *sc_if = xsc; 3778 3779 MSK_IF_LOCK(sc_if); 3780 msk_init_locked(sc_if); 3781 MSK_IF_UNLOCK(sc_if); 3782 } 3783 3784 static void 3785 msk_init_locked(struct msk_if_softc *sc_if) 3786 { 3787 struct msk_softc *sc; 3788 if_t ifp; 3789 struct mii_data *mii; 3790 uint8_t *eaddr; 3791 uint16_t gmac; 3792 uint32_t reg; 3793 int error; 3794 3795 MSK_IF_LOCK_ASSERT(sc_if); 3796 3797 ifp = sc_if->msk_ifp; 3798 sc = sc_if->msk_softc; 3799 mii = device_get_softc(sc_if->msk_miibus); 3800 3801 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 3802 return; 3803 3804 error = 0; 3805 /* Cancel pending I/O and free all Rx/Tx buffers. */ 3806 msk_stop(sc_if); 3807 3808 if (if_getmtu(ifp) < ETHERMTU) 3809 sc_if->msk_framesize = ETHERMTU; 3810 else 3811 sc_if->msk_framesize = if_getmtu(ifp); 3812 sc_if->msk_framesize += ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 3813 if (if_getmtu(ifp) > ETHERMTU && 3814 (sc_if->msk_flags & MSK_FLAG_JUMBO_NOCSUM) != 0) { 3815 if_sethwassistbits(ifp, 0, (MSK_CSUM_FEATURES | CSUM_TSO)); 3816 if_setcapenablebit(ifp, 0, (IFCAP_TSO4 | IFCAP_TXCSUM)); 3817 } 3818 3819 /* GMAC Control reset. */ 3820 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_RST_SET); 3821 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_RST_CLR); 3822 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_F_LOOPB_OFF); 3823 if (sc->msk_hw_id == CHIP_ID_YUKON_EX || 3824 sc->msk_hw_id == CHIP_ID_YUKON_SUPR) 3825 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), 3826 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON | 3827 GMC_BYP_RETR_ON); 3828 3829 /* 3830 * Initialize GMAC first such that speed/duplex/flow-control 3831 * parameters are renegotiated when interface is brought up. 3832 */ 3833 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, 0); 3834 3835 /* Dummy read the Interrupt Source Register. */ 3836 CSR_READ_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_SRC)); 3837 3838 /* Clear MIB stats. */ 3839 msk_stats_clear(sc_if); 3840 3841 /* Disable FCS. */ 3842 GMAC_WRITE_2(sc, sc_if->msk_port, GM_RX_CTRL, GM_RXCR_CRC_DIS); 3843 3844 /* Setup Transmit Control Register. */ 3845 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF)); 3846 3847 /* Setup Transmit Flow Control Register. */ 3848 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_FLOW_CTRL, 0xffff); 3849 3850 /* Setup Transmit Parameter Register. */ 3851 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_PARAM, 3852 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) | TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) | 3853 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) | TX_BACK_OFF_LIM(TX_BOF_LIM_DEF)); 3854 3855 gmac = DATA_BLIND_VAL(DATA_BLIND_DEF) | 3856 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF); 3857 3858 if (if_getmtu(ifp) > ETHERMTU) 3859 gmac |= GM_SMOD_JUMBO_ENA; 3860 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SERIAL_MODE, gmac); 3861 3862 /* Set station address. */ 3863 eaddr = if_getlladdr(ifp); 3864 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_1L, 3865 eaddr[0] | (eaddr[1] << 8)); 3866 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_1M, 3867 eaddr[2] | (eaddr[3] << 8)); 3868 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_1H, 3869 eaddr[4] | (eaddr[5] << 8)); 3870 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_2L, 3871 eaddr[0] | (eaddr[1] << 8)); 3872 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_2M, 3873 eaddr[2] | (eaddr[3] << 8)); 3874 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_2H, 3875 eaddr[4] | (eaddr[5] << 8)); 3876 3877 /* Disable interrupts for counter overflows. */ 3878 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_IRQ_MSK, 0); 3879 GMAC_WRITE_2(sc, sc_if->msk_port, GM_RX_IRQ_MSK, 0); 3880 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TR_IRQ_MSK, 0); 3881 3882 /* Configure Rx MAC FIFO. */ 3883 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), GMF_RST_SET); 3884 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), GMF_RST_CLR); 3885 reg = GMF_OPER_ON | GMF_RX_F_FL_ON; 3886 if (sc->msk_hw_id == CHIP_ID_YUKON_FE_P || 3887 sc->msk_hw_id == CHIP_ID_YUKON_EX) 3888 reg |= GMF_RX_OVER_ON; 3889 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), reg); 3890 3891 /* Set receive filter. */ 3892 msk_rxfilter(sc_if); 3893 3894 if (sc->msk_hw_id == CHIP_ID_YUKON_XL) { 3895 /* Clear flush mask - HW bug. */ 3896 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_FL_MSK), 0); 3897 } else { 3898 /* Flush Rx MAC FIFO on any flow control or error. */ 3899 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_FL_MSK), 3900 GMR_FS_ANY_ERR); 3901 } 3902 3903 /* 3904 * Set Rx FIFO flush threshold to 64 bytes + 1 FIFO word 3905 * due to hardware hang on receipt of pause frames. 3906 */ 3907 reg = RX_GMF_FL_THR_DEF + 1; 3908 /* Another magic for Yukon FE+ - From Linux. */ 3909 if (sc->msk_hw_id == CHIP_ID_YUKON_FE_P && 3910 sc->msk_hw_rev == CHIP_REV_YU_FE_P_A0) 3911 reg = 0x178; 3912 CSR_WRITE_2(sc, MR_ADDR(sc_if->msk_port, RX_GMF_FL_THR), reg); 3913 3914 /* Configure Tx MAC FIFO. */ 3915 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_RST_SET); 3916 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_RST_CLR); 3917 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_OPER_ON); 3918 3919 /* Configure hardware VLAN tag insertion/stripping. */ 3920 msk_setvlan(sc_if, ifp); 3921 3922 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) == 0) { 3923 /* Set Rx Pause threshold. */ 3924 CSR_WRITE_2(sc, MR_ADDR(sc_if->msk_port, RX_GMF_LP_THR), 3925 MSK_ECU_LLPP); 3926 CSR_WRITE_2(sc, MR_ADDR(sc_if->msk_port, RX_GMF_UP_THR), 3927 MSK_ECU_ULPP); 3928 /* Configure store-and-forward for Tx. */ 3929 msk_set_tx_stfwd(sc_if); 3930 } 3931 3932 if (sc->msk_hw_id == CHIP_ID_YUKON_FE_P && 3933 sc->msk_hw_rev == CHIP_REV_YU_FE_P_A0) { 3934 /* Disable dynamic watermark - from Linux. */ 3935 reg = CSR_READ_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_EA)); 3936 reg &= ~0x03; 3937 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_EA), reg); 3938 } 3939 3940 /* 3941 * Disable Force Sync bit and Alloc bit in Tx RAM interface 3942 * arbiter as we don't use Sync Tx queue. 3943 */ 3944 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, TXA_CTRL), 3945 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC); 3946 /* Enable the RAM Interface Arbiter. */ 3947 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, TXA_CTRL), TXA_ENA_ARB); 3948 3949 /* Setup RAM buffer. */ 3950 msk_set_rambuffer(sc_if); 3951 3952 /* Disable Tx sync Queue. */ 3953 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txsq, RB_CTRL), RB_RST_SET); 3954 3955 /* Setup Tx Queue Bus Memory Interface. */ 3956 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_CLR_RESET); 3957 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_OPER_INIT); 3958 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_FIFO_OP_ON); 3959 CSR_WRITE_2(sc, Q_ADDR(sc_if->msk_txq, Q_WM), MSK_BMU_TX_WM); 3960 switch (sc->msk_hw_id) { 3961 case CHIP_ID_YUKON_EC_U: 3962 if (sc->msk_hw_rev == CHIP_REV_YU_EC_U_A0) { 3963 /* Fix for Yukon-EC Ultra: set BMU FIFO level */ 3964 CSR_WRITE_2(sc, Q_ADDR(sc_if->msk_txq, Q_AL), 3965 MSK_ECU_TXFF_LEV); 3966 } 3967 break; 3968 case CHIP_ID_YUKON_EX: 3969 /* 3970 * Yukon Extreme seems to have silicon bug for 3971 * automatic Tx checksum calculation capability. 3972 */ 3973 if (sc->msk_hw_rev == CHIP_REV_YU_EX_B0) 3974 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_F), 3975 F_TX_CHK_AUTO_OFF); 3976 break; 3977 } 3978 3979 /* Setup Rx Queue Bus Memory Interface. */ 3980 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_CLR_RESET); 3981 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_OPER_INIT); 3982 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_FIFO_OP_ON); 3983 CSR_WRITE_2(sc, Q_ADDR(sc_if->msk_rxq, Q_WM), MSK_BMU_RX_WM); 3984 if (sc->msk_hw_id == CHIP_ID_YUKON_EC_U && 3985 sc->msk_hw_rev >= CHIP_REV_YU_EC_U_A1) { 3986 /* MAC Rx RAM Read is controlled by hardware. */ 3987 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_F), F_M_RX_RAM_DIS); 3988 } 3989 3990 msk_set_prefetch(sc, sc_if->msk_txq, 3991 sc_if->msk_rdata.msk_tx_ring_paddr, MSK_TX_RING_CNT - 1); 3992 msk_init_tx_ring(sc_if); 3993 3994 /* Disable Rx checksum offload and RSS hash. */ 3995 reg = BMU_DIS_RX_RSS_HASH; 3996 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0 && 3997 (if_getcapenable(ifp) & IFCAP_RXCSUM) != 0) 3998 reg |= BMU_ENA_RX_CHKSUM; 3999 else 4000 reg |= BMU_DIS_RX_CHKSUM; 4001 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), reg); 4002 if (sc_if->msk_framesize > (MCLBYTES - MSK_RX_BUF_ALIGN)) { 4003 msk_set_prefetch(sc, sc_if->msk_rxq, 4004 sc_if->msk_rdata.msk_jumbo_rx_ring_paddr, 4005 MSK_JUMBO_RX_RING_CNT - 1); 4006 error = msk_init_jumbo_rx_ring(sc_if); 4007 } else { 4008 msk_set_prefetch(sc, sc_if->msk_rxq, 4009 sc_if->msk_rdata.msk_rx_ring_paddr, 4010 MSK_RX_RING_CNT - 1); 4011 error = msk_init_rx_ring(sc_if); 4012 } 4013 if (error != 0) { 4014 device_printf(sc_if->msk_if_dev, 4015 "initialization failed: no memory for Rx buffers\n"); 4016 msk_stop(sc_if); 4017 return; 4018 } 4019 if (sc->msk_hw_id == CHIP_ID_YUKON_EX || 4020 sc->msk_hw_id == CHIP_ID_YUKON_SUPR) { 4021 /* Disable flushing of non-ASF packets. */ 4022 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), 4023 GMF_RX_MACSEC_FLUSH_OFF); 4024 } 4025 4026 /* Configure interrupt handling. */ 4027 if (sc_if->msk_port == MSK_PORT_A) { 4028 sc->msk_intrmask |= Y2_IS_PORT_A; 4029 sc->msk_intrhwemask |= Y2_HWE_L1_MASK; 4030 } else { 4031 sc->msk_intrmask |= Y2_IS_PORT_B; 4032 sc->msk_intrhwemask |= Y2_HWE_L2_MASK; 4033 } 4034 /* Configure IRQ moderation mask. */ 4035 CSR_WRITE_4(sc, B2_IRQM_MSK, sc->msk_intrmask); 4036 if (sc->msk_int_holdoff > 0) { 4037 /* Configure initial IRQ moderation timer value. */ 4038 CSR_WRITE_4(sc, B2_IRQM_INI, 4039 MSK_USECS(sc, sc->msk_int_holdoff)); 4040 CSR_WRITE_4(sc, B2_IRQM_VAL, 4041 MSK_USECS(sc, sc->msk_int_holdoff)); 4042 /* Start IRQ moderation. */ 4043 CSR_WRITE_1(sc, B2_IRQM_CTRL, TIM_START); 4044 } 4045 CSR_WRITE_4(sc, B0_HWE_IMSK, sc->msk_intrhwemask); 4046 CSR_READ_4(sc, B0_HWE_IMSK); 4047 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask); 4048 CSR_READ_4(sc, B0_IMSK); 4049 4050 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0); 4051 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 4052 4053 sc_if->msk_flags &= ~MSK_FLAG_LINK; 4054 mii_mediachg(mii); 4055 4056 callout_reset(&sc_if->msk_tick_ch, hz, msk_tick, sc_if); 4057 } 4058 4059 static void 4060 msk_set_rambuffer(struct msk_if_softc *sc_if) 4061 { 4062 struct msk_softc *sc; 4063 int ltpp, utpp; 4064 4065 sc = sc_if->msk_softc; 4066 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) == 0) 4067 return; 4068 4069 /* Setup Rx Queue. */ 4070 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_RST_CLR); 4071 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_START), 4072 sc->msk_rxqstart[sc_if->msk_port] / 8); 4073 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_END), 4074 sc->msk_rxqend[sc_if->msk_port] / 8); 4075 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_WP), 4076 sc->msk_rxqstart[sc_if->msk_port] / 8); 4077 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_RP), 4078 sc->msk_rxqstart[sc_if->msk_port] / 8); 4079 4080 utpp = (sc->msk_rxqend[sc_if->msk_port] + 1 - 4081 sc->msk_rxqstart[sc_if->msk_port] - MSK_RB_ULPP) / 8; 4082 ltpp = (sc->msk_rxqend[sc_if->msk_port] + 1 - 4083 sc->msk_rxqstart[sc_if->msk_port] - MSK_RB_LLPP_B) / 8; 4084 if (sc->msk_rxqsize < MSK_MIN_RXQ_SIZE) 4085 ltpp += (MSK_RB_LLPP_B - MSK_RB_LLPP_S) / 8; 4086 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_RX_UTPP), utpp); 4087 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_RX_LTPP), ltpp); 4088 /* Set Rx priority(RB_RX_UTHP/RB_RX_LTHP) thresholds? */ 4089 4090 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_ENA_OP_MD); 4091 CSR_READ_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL)); 4092 4093 /* Setup Tx Queue. */ 4094 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_RST_CLR); 4095 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_START), 4096 sc->msk_txqstart[sc_if->msk_port] / 8); 4097 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_END), 4098 sc->msk_txqend[sc_if->msk_port] / 8); 4099 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_WP), 4100 sc->msk_txqstart[sc_if->msk_port] / 8); 4101 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_RP), 4102 sc->msk_txqstart[sc_if->msk_port] / 8); 4103 /* Enable Store & Forward for Tx side. */ 4104 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_ENA_STFWD); 4105 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_ENA_OP_MD); 4106 CSR_READ_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL)); 4107 } 4108 4109 static void 4110 msk_set_prefetch(struct msk_softc *sc, int qaddr, bus_addr_t addr, 4111 uint32_t count) 4112 { 4113 4114 /* Reset the prefetch unit. */ 4115 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG), 4116 PREF_UNIT_RST_SET); 4117 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG), 4118 PREF_UNIT_RST_CLR); 4119 /* Set LE base address. */ 4120 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_ADDR_LOW_REG), 4121 MSK_ADDR_LO(addr)); 4122 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_ADDR_HI_REG), 4123 MSK_ADDR_HI(addr)); 4124 /* Set the list last index. */ 4125 CSR_WRITE_2(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_LAST_IDX_REG), 4126 count); 4127 /* Turn on prefetch unit. */ 4128 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG), 4129 PREF_UNIT_OP_ON); 4130 /* Dummy read to ensure write. */ 4131 CSR_READ_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG)); 4132 } 4133 4134 static void 4135 msk_stop(struct msk_if_softc *sc_if) 4136 { 4137 struct msk_softc *sc; 4138 struct msk_txdesc *txd; 4139 struct msk_rxdesc *rxd; 4140 struct msk_rxdesc *jrxd; 4141 if_t ifp; 4142 uint32_t val; 4143 int i; 4144 4145 MSK_IF_LOCK_ASSERT(sc_if); 4146 sc = sc_if->msk_softc; 4147 ifp = sc_if->msk_ifp; 4148 4149 callout_stop(&sc_if->msk_tick_ch); 4150 sc_if->msk_watchdog_timer = 0; 4151 4152 /* Disable interrupts. */ 4153 if (sc_if->msk_port == MSK_PORT_A) { 4154 sc->msk_intrmask &= ~Y2_IS_PORT_A; 4155 sc->msk_intrhwemask &= ~Y2_HWE_L1_MASK; 4156 } else { 4157 sc->msk_intrmask &= ~Y2_IS_PORT_B; 4158 sc->msk_intrhwemask &= ~Y2_HWE_L2_MASK; 4159 } 4160 CSR_WRITE_4(sc, B0_HWE_IMSK, sc->msk_intrhwemask); 4161 CSR_READ_4(sc, B0_HWE_IMSK); 4162 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask); 4163 CSR_READ_4(sc, B0_IMSK); 4164 4165 /* Disable Tx/Rx MAC. */ 4166 val = GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL); 4167 val &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA); 4168 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, val); 4169 /* Read again to ensure writing. */ 4170 GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL); 4171 /* Update stats and clear counters. */ 4172 msk_stats_update(sc_if); 4173 4174 /* Stop Tx BMU. */ 4175 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_STOP); 4176 val = CSR_READ_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR)); 4177 for (i = 0; i < MSK_TIMEOUT; i++) { 4178 if ((val & (BMU_STOP | BMU_IDLE)) == 0) { 4179 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), 4180 BMU_STOP); 4181 val = CSR_READ_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR)); 4182 } else 4183 break; 4184 DELAY(1); 4185 } 4186 if (i == MSK_TIMEOUT) 4187 device_printf(sc_if->msk_if_dev, "Tx BMU stop failed\n"); 4188 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), 4189 RB_RST_SET | RB_DIS_OP_MD); 4190 4191 /* Disable all GMAC interrupt. */ 4192 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_MSK), 0); 4193 /* Disable PHY interrupt. */ 4194 msk_phy_writereg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_MASK, 0); 4195 4196 /* Disable the RAM Interface Arbiter. */ 4197 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, TXA_CTRL), TXA_DIS_ARB); 4198 4199 /* Reset the PCI FIFO of the async Tx queue */ 4200 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), 4201 BMU_RST_SET | BMU_FIFO_RST); 4202 4203 /* Reset the Tx prefetch units. */ 4204 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(sc_if->msk_txq, PREF_UNIT_CTRL_REG), 4205 PREF_UNIT_RST_SET); 4206 4207 /* Reset the RAM Buffer async Tx queue. */ 4208 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_RST_SET); 4209 4210 /* Reset Tx MAC FIFO. */ 4211 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_RST_SET); 4212 /* Set Pause Off. */ 4213 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_PAUSE_OFF); 4214 4215 /* 4216 * The Rx Stop command will not work for Yukon-2 if the BMU does not 4217 * reach the end of packet and since we can't make sure that we have 4218 * incoming data, we must reset the BMU while it is not during a DMA 4219 * transfer. Since it is possible that the Rx path is still active, 4220 * the Rx RAM buffer will be stopped first, so any possible incoming 4221 * data will not trigger a DMA. After the RAM buffer is stopped, the 4222 * BMU is polled until any DMA in progress is ended and only then it 4223 * will be reset. 4224 */ 4225 4226 /* Disable the RAM Buffer receive queue. */ 4227 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_DIS_OP_MD); 4228 for (i = 0; i < MSK_TIMEOUT; i++) { 4229 if (CSR_READ_1(sc, RB_ADDR(sc_if->msk_rxq, Q_RSL)) == 4230 CSR_READ_1(sc, RB_ADDR(sc_if->msk_rxq, Q_RL))) 4231 break; 4232 DELAY(1); 4233 } 4234 if (i == MSK_TIMEOUT) 4235 device_printf(sc_if->msk_if_dev, "Rx BMU stop failed\n"); 4236 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), 4237 BMU_RST_SET | BMU_FIFO_RST); 4238 /* Reset the Rx prefetch unit. */ 4239 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_CTRL_REG), 4240 PREF_UNIT_RST_SET); 4241 /* Reset the RAM Buffer receive queue. */ 4242 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_RST_SET); 4243 /* Reset Rx MAC FIFO. */ 4244 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), GMF_RST_SET); 4245 4246 /* Free Rx and Tx mbufs still in the queues. */ 4247 for (i = 0; i < MSK_RX_RING_CNT; i++) { 4248 rxd = &sc_if->msk_cdata.msk_rxdesc[i]; 4249 if (rxd->rx_m != NULL) { 4250 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_tag, 4251 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 4252 bus_dmamap_unload(sc_if->msk_cdata.msk_rx_tag, 4253 rxd->rx_dmamap); 4254 m_freem(rxd->rx_m); 4255 rxd->rx_m = NULL; 4256 } 4257 } 4258 for (i = 0; i < MSK_JUMBO_RX_RING_CNT; i++) { 4259 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[i]; 4260 if (jrxd->rx_m != NULL) { 4261 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_tag, 4262 jrxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 4263 bus_dmamap_unload(sc_if->msk_cdata.msk_jumbo_rx_tag, 4264 jrxd->rx_dmamap); 4265 m_freem(jrxd->rx_m); 4266 jrxd->rx_m = NULL; 4267 } 4268 } 4269 for (i = 0; i < MSK_TX_RING_CNT; i++) { 4270 txd = &sc_if->msk_cdata.msk_txdesc[i]; 4271 if (txd->tx_m != NULL) { 4272 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_tag, 4273 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 4274 bus_dmamap_unload(sc_if->msk_cdata.msk_tx_tag, 4275 txd->tx_dmamap); 4276 m_freem(txd->tx_m); 4277 txd->tx_m = NULL; 4278 } 4279 } 4280 4281 /* 4282 * Mark the interface down. 4283 */ 4284 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)); 4285 sc_if->msk_flags &= ~MSK_FLAG_LINK; 4286 } 4287 4288 /* 4289 * When GM_PAR_MIB_CLR bit of GM_PHY_ADDR is set, reading lower 4290 * counter clears high 16 bits of the counter such that accessing 4291 * lower 16 bits should be the last operation. 4292 */ 4293 #define MSK_READ_MIB32(x, y) \ 4294 ((((uint32_t)GMAC_READ_2(sc, x, (y) + 4)) << 16) + \ 4295 (uint32_t)GMAC_READ_2(sc, x, y)) 4296 #define MSK_READ_MIB64(x, y) \ 4297 ((((uint64_t)MSK_READ_MIB32(x, (y) + 8)) << 32) + \ 4298 (uint64_t)MSK_READ_MIB32(x, y)) 4299 4300 static void 4301 msk_stats_clear(struct msk_if_softc *sc_if) 4302 { 4303 struct msk_softc *sc; 4304 uint16_t gmac; 4305 int i; 4306 4307 MSK_IF_LOCK_ASSERT(sc_if); 4308 4309 sc = sc_if->msk_softc; 4310 /* Set MIB Clear Counter Mode. */ 4311 gmac = GMAC_READ_2(sc, sc_if->msk_port, GM_PHY_ADDR); 4312 GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac | GM_PAR_MIB_CLR); 4313 /* Read all MIB Counters with Clear Mode set. */ 4314 for (i = GM_RXF_UC_OK; i <= GM_TXE_FIFO_UR; i += sizeof(uint32_t)) 4315 (void)MSK_READ_MIB32(sc_if->msk_port, i); 4316 /* Clear MIB Clear Counter Mode. */ 4317 gmac &= ~GM_PAR_MIB_CLR; 4318 GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac); 4319 } 4320 4321 static void 4322 msk_stats_update(struct msk_if_softc *sc_if) 4323 { 4324 struct msk_softc *sc; 4325 if_t ifp; 4326 struct msk_hw_stats *stats; 4327 uint16_t gmac; 4328 4329 MSK_IF_LOCK_ASSERT(sc_if); 4330 4331 ifp = sc_if->msk_ifp; 4332 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) 4333 return; 4334 sc = sc_if->msk_softc; 4335 stats = &sc_if->msk_stats; 4336 /* Set MIB Clear Counter Mode. */ 4337 gmac = GMAC_READ_2(sc, sc_if->msk_port, GM_PHY_ADDR); 4338 GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac | GM_PAR_MIB_CLR); 4339 4340 /* Rx stats. */ 4341 stats->rx_ucast_frames += 4342 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_UC_OK); 4343 stats->rx_bcast_frames += 4344 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_BC_OK); 4345 stats->rx_pause_frames += 4346 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_MPAUSE); 4347 stats->rx_mcast_frames += 4348 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_MC_OK); 4349 stats->rx_crc_errs += 4350 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_FCS_ERR); 4351 stats->rx_good_octets += 4352 MSK_READ_MIB64(sc_if->msk_port, GM_RXO_OK_LO); 4353 stats->rx_bad_octets += 4354 MSK_READ_MIB64(sc_if->msk_port, GM_RXO_ERR_LO); 4355 stats->rx_runts += 4356 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_SHT); 4357 stats->rx_runt_errs += 4358 MSK_READ_MIB32(sc_if->msk_port, GM_RXE_FRAG); 4359 stats->rx_pkts_64 += 4360 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_64B); 4361 stats->rx_pkts_65_127 += 4362 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_127B); 4363 stats->rx_pkts_128_255 += 4364 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_255B); 4365 stats->rx_pkts_256_511 += 4366 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_511B); 4367 stats->rx_pkts_512_1023 += 4368 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_1023B); 4369 stats->rx_pkts_1024_1518 += 4370 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_1518B); 4371 stats->rx_pkts_1519_max += 4372 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_MAX_SZ); 4373 stats->rx_pkts_too_long += 4374 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_LNG_ERR); 4375 stats->rx_pkts_jabbers += 4376 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_JAB_PKT); 4377 stats->rx_fifo_oflows += 4378 MSK_READ_MIB32(sc_if->msk_port, GM_RXE_FIFO_OV); 4379 4380 /* Tx stats. */ 4381 stats->tx_ucast_frames += 4382 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_UC_OK); 4383 stats->tx_bcast_frames += 4384 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_BC_OK); 4385 stats->tx_pause_frames += 4386 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_MPAUSE); 4387 stats->tx_mcast_frames += 4388 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_MC_OK); 4389 stats->tx_octets += 4390 MSK_READ_MIB64(sc_if->msk_port, GM_TXO_OK_LO); 4391 stats->tx_pkts_64 += 4392 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_64B); 4393 stats->tx_pkts_65_127 += 4394 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_127B); 4395 stats->tx_pkts_128_255 += 4396 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_255B); 4397 stats->tx_pkts_256_511 += 4398 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_511B); 4399 stats->tx_pkts_512_1023 += 4400 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_1023B); 4401 stats->tx_pkts_1024_1518 += 4402 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_1518B); 4403 stats->tx_pkts_1519_max += 4404 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_MAX_SZ); 4405 stats->tx_colls += 4406 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_COL); 4407 stats->tx_late_colls += 4408 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_LAT_COL); 4409 stats->tx_excess_colls += 4410 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_ABO_COL); 4411 stats->tx_multi_colls += 4412 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_MUL_COL); 4413 stats->tx_single_colls += 4414 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_SNG_COL); 4415 stats->tx_underflows += 4416 MSK_READ_MIB32(sc_if->msk_port, GM_TXE_FIFO_UR); 4417 /* Clear MIB Clear Counter Mode. */ 4418 gmac &= ~GM_PAR_MIB_CLR; 4419 GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac); 4420 } 4421 4422 static int 4423 msk_sysctl_stat32(SYSCTL_HANDLER_ARGS) 4424 { 4425 struct msk_softc *sc; 4426 struct msk_if_softc *sc_if; 4427 uint32_t result, *stat; 4428 int off; 4429 4430 sc_if = (struct msk_if_softc *)arg1; 4431 sc = sc_if->msk_softc; 4432 off = arg2; 4433 stat = (uint32_t *)((uint8_t *)&sc_if->msk_stats + off); 4434 4435 MSK_IF_LOCK(sc_if); 4436 result = MSK_READ_MIB32(sc_if->msk_port, GM_MIB_CNT_BASE + off * 2); 4437 result += *stat; 4438 MSK_IF_UNLOCK(sc_if); 4439 4440 return (sysctl_handle_int(oidp, &result, 0, req)); 4441 } 4442 4443 static int 4444 msk_sysctl_stat64(SYSCTL_HANDLER_ARGS) 4445 { 4446 struct msk_softc *sc; 4447 struct msk_if_softc *sc_if; 4448 uint64_t result, *stat; 4449 int off; 4450 4451 sc_if = (struct msk_if_softc *)arg1; 4452 sc = sc_if->msk_softc; 4453 off = arg2; 4454 stat = (uint64_t *)((uint8_t *)&sc_if->msk_stats + off); 4455 4456 MSK_IF_LOCK(sc_if); 4457 result = MSK_READ_MIB64(sc_if->msk_port, GM_MIB_CNT_BASE + off * 2); 4458 result += *stat; 4459 MSK_IF_UNLOCK(sc_if); 4460 4461 return (sysctl_handle_64(oidp, &result, 0, req)); 4462 } 4463 4464 #undef MSK_READ_MIB32 4465 #undef MSK_READ_MIB64 4466 4467 #define MSK_SYSCTL_STAT32(sc, c, o, p, n, d) \ 4468 SYSCTL_ADD_PROC(c, p, OID_AUTO, o, \ 4469 CTLTYPE_UINT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, \ 4470 sc, offsetof(struct msk_hw_stats, n), msk_sysctl_stat32, \ 4471 "IU", d) 4472 #define MSK_SYSCTL_STAT64(sc, c, o, p, n, d) \ 4473 SYSCTL_ADD_PROC(c, p, OID_AUTO, o, \ 4474 CTLTYPE_U64 | CTLFLAG_RD | CTLFLAG_NEEDGIANT, \ 4475 sc, offsetof(struct msk_hw_stats, n), msk_sysctl_stat64, \ 4476 "QU", d) 4477 4478 static void 4479 msk_sysctl_node(struct msk_if_softc *sc_if) 4480 { 4481 struct sysctl_ctx_list *ctx; 4482 struct sysctl_oid_list *child, *schild; 4483 struct sysctl_oid *tree; 4484 4485 ctx = device_get_sysctl_ctx(sc_if->msk_if_dev); 4486 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc_if->msk_if_dev)); 4487 4488 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", 4489 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "MSK Statistics"); 4490 schild = SYSCTL_CHILDREN(tree); 4491 tree = SYSCTL_ADD_NODE(ctx, schild, OID_AUTO, "rx", 4492 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "MSK RX Statistics"); 4493 child = SYSCTL_CHILDREN(tree); 4494 MSK_SYSCTL_STAT32(sc_if, ctx, "ucast_frames", 4495 child, rx_ucast_frames, "Good unicast frames"); 4496 MSK_SYSCTL_STAT32(sc_if, ctx, "bcast_frames", 4497 child, rx_bcast_frames, "Good broadcast frames"); 4498 MSK_SYSCTL_STAT32(sc_if, ctx, "pause_frames", 4499 child, rx_pause_frames, "Pause frames"); 4500 MSK_SYSCTL_STAT32(sc_if, ctx, "mcast_frames", 4501 child, rx_mcast_frames, "Multicast frames"); 4502 MSK_SYSCTL_STAT32(sc_if, ctx, "crc_errs", 4503 child, rx_crc_errs, "CRC errors"); 4504 MSK_SYSCTL_STAT64(sc_if, ctx, "good_octets", 4505 child, rx_good_octets, "Good octets"); 4506 MSK_SYSCTL_STAT64(sc_if, ctx, "bad_octets", 4507 child, rx_bad_octets, "Bad octets"); 4508 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_64", 4509 child, rx_pkts_64, "64 bytes frames"); 4510 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_65_127", 4511 child, rx_pkts_65_127, "65 to 127 bytes frames"); 4512 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_128_255", 4513 child, rx_pkts_128_255, "128 to 255 bytes frames"); 4514 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_256_511", 4515 child, rx_pkts_256_511, "256 to 511 bytes frames"); 4516 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_512_1023", 4517 child, rx_pkts_512_1023, "512 to 1023 bytes frames"); 4518 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_1024_1518", 4519 child, rx_pkts_1024_1518, "1024 to 1518 bytes frames"); 4520 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_1519_max", 4521 child, rx_pkts_1519_max, "1519 to max frames"); 4522 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_too_long", 4523 child, rx_pkts_too_long, "frames too long"); 4524 MSK_SYSCTL_STAT32(sc_if, ctx, "jabbers", 4525 child, rx_pkts_jabbers, "Jabber errors"); 4526 MSK_SYSCTL_STAT32(sc_if, ctx, "overflows", 4527 child, rx_fifo_oflows, "FIFO overflows"); 4528 4529 tree = SYSCTL_ADD_NODE(ctx, schild, OID_AUTO, "tx", 4530 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "MSK TX Statistics"); 4531 child = SYSCTL_CHILDREN(tree); 4532 MSK_SYSCTL_STAT32(sc_if, ctx, "ucast_frames", 4533 child, tx_ucast_frames, "Unicast frames"); 4534 MSK_SYSCTL_STAT32(sc_if, ctx, "bcast_frames", 4535 child, tx_bcast_frames, "Broadcast frames"); 4536 MSK_SYSCTL_STAT32(sc_if, ctx, "pause_frames", 4537 child, tx_pause_frames, "Pause frames"); 4538 MSK_SYSCTL_STAT32(sc_if, ctx, "mcast_frames", 4539 child, tx_mcast_frames, "Multicast frames"); 4540 MSK_SYSCTL_STAT64(sc_if, ctx, "octets", 4541 child, tx_octets, "Octets"); 4542 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_64", 4543 child, tx_pkts_64, "64 bytes frames"); 4544 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_65_127", 4545 child, tx_pkts_65_127, "65 to 127 bytes frames"); 4546 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_128_255", 4547 child, tx_pkts_128_255, "128 to 255 bytes frames"); 4548 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_256_511", 4549 child, tx_pkts_256_511, "256 to 511 bytes frames"); 4550 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_512_1023", 4551 child, tx_pkts_512_1023, "512 to 1023 bytes frames"); 4552 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_1024_1518", 4553 child, tx_pkts_1024_1518, "1024 to 1518 bytes frames"); 4554 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_1519_max", 4555 child, tx_pkts_1519_max, "1519 to max frames"); 4556 MSK_SYSCTL_STAT32(sc_if, ctx, "colls", 4557 child, tx_colls, "Collisions"); 4558 MSK_SYSCTL_STAT32(sc_if, ctx, "late_colls", 4559 child, tx_late_colls, "Late collisions"); 4560 MSK_SYSCTL_STAT32(sc_if, ctx, "excess_colls", 4561 child, tx_excess_colls, "Excessive collisions"); 4562 MSK_SYSCTL_STAT32(sc_if, ctx, "multi_colls", 4563 child, tx_multi_colls, "Multiple collisions"); 4564 MSK_SYSCTL_STAT32(sc_if, ctx, "single_colls", 4565 child, tx_single_colls, "Single collisions"); 4566 MSK_SYSCTL_STAT32(sc_if, ctx, "underflows", 4567 child, tx_underflows, "FIFO underflows"); 4568 } 4569 4570 #undef MSK_SYSCTL_STAT32 4571 #undef MSK_SYSCTL_STAT64 4572 4573 static int 4574 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 4575 { 4576 int error, value; 4577 4578 if (!arg1) 4579 return (EINVAL); 4580 value = *(int *)arg1; 4581 error = sysctl_handle_int(oidp, &value, 0, req); 4582 if (error || !req->newptr) 4583 return (error); 4584 if (value < low || value > high) 4585 return (EINVAL); 4586 *(int *)arg1 = value; 4587 4588 return (0); 4589 } 4590 4591 static int 4592 sysctl_hw_msk_proc_limit(SYSCTL_HANDLER_ARGS) 4593 { 4594 4595 return (sysctl_int_range(oidp, arg1, arg2, req, MSK_PROC_MIN, 4596 MSK_PROC_MAX)); 4597 } 4598