1 /****************************************************************************** 2 * 3 * Name : sky2.c 4 * Project: Gigabit Ethernet Driver for FreeBSD 5.x/6.x 5 * Version: $Revision: 1.23 $ 6 * Date : $Date: 2005/12/22 09:04:11 $ 7 * Purpose: Main driver source file 8 * 9 *****************************************************************************/ 10 11 /****************************************************************************** 12 * 13 * LICENSE: 14 * Copyright (C) Marvell International Ltd. and/or its affiliates 15 * 16 * The computer program files contained in this folder ("Files") 17 * are provided to you under the BSD-type license terms provided 18 * below, and any use of such Files and any derivative works 19 * thereof created by you shall be governed by the following terms 20 * and conditions: 21 * 22 * - Redistributions of source code must retain the above copyright 23 * notice, this list of conditions and the following disclaimer. 24 * - Redistributions in binary form must reproduce the above 25 * copyright notice, this list of conditions and the following 26 * disclaimer in the documentation and/or other materials provided 27 * with the distribution. 28 * - Neither the name of Marvell nor the names of its contributors 29 * may be used to endorse or promote products derived from this 30 * software without specific prior written permission. 31 * 32 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 33 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 34 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 35 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 36 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 37 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 38 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 39 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 40 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 41 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 42 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED 43 * OF THE POSSIBILITY OF SUCH DAMAGE. 44 * /LICENSE 45 * 46 *****************************************************************************/ 47 48 /*- 49 * Copyright (c) 1997, 1998, 1999, 2000 50 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 51 * 52 * Redistribution and use in source and binary forms, with or without 53 * modification, are permitted provided that the following conditions 54 * are met: 55 * 1. Redistributions of source code must retain the above copyright 56 * notice, this list of conditions and the following disclaimer. 57 * 2. Redistributions in binary form must reproduce the above copyright 58 * notice, this list of conditions and the following disclaimer in the 59 * documentation and/or other materials provided with the distribution. 60 * 3. All advertising materials mentioning features or use of this software 61 * must display the following acknowledgement: 62 * This product includes software developed by Bill Paul. 63 * 4. Neither the name of the author nor the names of any co-contributors 64 * may be used to endorse or promote products derived from this software 65 * without specific prior written permission. 66 * 67 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 68 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 69 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 70 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 71 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 72 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 73 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 74 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 75 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 76 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 77 * THE POSSIBILITY OF SUCH DAMAGE. 78 */ 79 /*- 80 * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu> 81 * 82 * Permission to use, copy, modify, and distribute this software for any 83 * purpose with or without fee is hereby granted, provided that the above 84 * copyright notice and this permission notice appear in all copies. 85 * 86 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 87 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 88 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 89 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 90 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 91 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 92 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 93 */ 94 95 /* 96 * Device driver for the Marvell Yukon II Ethernet controller. 97 * Due to lack of documentation, this driver is based on the code from 98 * sk(4) and Marvell's myk(4) driver for FreeBSD 5.x. 99 */ 100 101 #include <sys/cdefs.h> 102 __FBSDID("$FreeBSD$"); 103 104 #include <sys/param.h> 105 #include <sys/systm.h> 106 #include <sys/bus.h> 107 #include <sys/endian.h> 108 #include <sys/mbuf.h> 109 #include <sys/malloc.h> 110 #include <sys/kernel.h> 111 #include <sys/module.h> 112 #include <sys/socket.h> 113 #include <sys/sockio.h> 114 #include <sys/queue.h> 115 #include <sys/sysctl.h> 116 #include <sys/taskqueue.h> 117 118 #include <net/bpf.h> 119 #include <net/ethernet.h> 120 #include <net/if.h> 121 #include <net/if_arp.h> 122 #include <net/if_dl.h> 123 #include <net/if_media.h> 124 #include <net/if_types.h> 125 #include <net/if_vlan_var.h> 126 127 #include <netinet/in.h> 128 #include <netinet/in_systm.h> 129 #include <netinet/ip.h> 130 #include <netinet/tcp.h> 131 #include <netinet/udp.h> 132 133 #include <machine/bus.h> 134 #include <machine/in_cksum.h> 135 #include <machine/resource.h> 136 #include <sys/rman.h> 137 138 #include <dev/mii/mii.h> 139 #include <dev/mii/miivar.h> 140 #include <dev/mii/brgphyreg.h> 141 142 #include <dev/pci/pcireg.h> 143 #include <dev/pci/pcivar.h> 144 145 #include <dev/msk/if_mskreg.h> 146 147 MODULE_DEPEND(msk, pci, 1, 1, 1); 148 MODULE_DEPEND(msk, ether, 1, 1, 1); 149 MODULE_DEPEND(msk, miibus, 1, 1, 1); 150 151 /* "device miibus" required. See GENERIC if you get errors here. */ 152 #include "miibus_if.h" 153 154 /* Tunables. */ 155 static int msi_disable = 0; 156 TUNABLE_INT("hw.msk.msi_disable", &msi_disable); 157 static int legacy_intr = 0; 158 TUNABLE_INT("hw.msk.legacy_intr", &legacy_intr); 159 160 #define MSK_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 161 162 /* 163 * Devices supported by this driver. 164 */ 165 static struct msk_product { 166 uint16_t msk_vendorid; 167 uint16_t msk_deviceid; 168 const char *msk_name; 169 } msk_products[] = { 170 { VENDORID_SK, DEVICEID_SK_YUKON2, 171 "SK-9Sxx Gigabit Ethernet" }, 172 { VENDORID_SK, DEVICEID_SK_YUKON2_EXPR, 173 "SK-9Exx Gigabit Ethernet"}, 174 { VENDORID_MARVELL, DEVICEID_MRVL_8021CU, 175 "Marvell Yukon 88E8021CU Gigabit Ethernet" }, 176 { VENDORID_MARVELL, DEVICEID_MRVL_8021X, 177 "Marvell Yukon 88E8021 SX/LX Gigabit Ethernet" }, 178 { VENDORID_MARVELL, DEVICEID_MRVL_8022CU, 179 "Marvell Yukon 88E8022CU Gigabit Ethernet" }, 180 { VENDORID_MARVELL, DEVICEID_MRVL_8022X, 181 "Marvell Yukon 88E8022 SX/LX Gigabit Ethernet" }, 182 { VENDORID_MARVELL, DEVICEID_MRVL_8061CU, 183 "Marvell Yukon 88E8061CU Gigabit Ethernet" }, 184 { VENDORID_MARVELL, DEVICEID_MRVL_8061X, 185 "Marvell Yukon 88E8061 SX/LX Gigabit Ethernet" }, 186 { VENDORID_MARVELL, DEVICEID_MRVL_8062CU, 187 "Marvell Yukon 88E8062CU Gigabit Ethernet" }, 188 { VENDORID_MARVELL, DEVICEID_MRVL_8062X, 189 "Marvell Yukon 88E8062 SX/LX Gigabit Ethernet" }, 190 { VENDORID_MARVELL, DEVICEID_MRVL_8035, 191 "Marvell Yukon 88E8035 Gigabit Ethernet" }, 192 { VENDORID_MARVELL, DEVICEID_MRVL_8036, 193 "Marvell Yukon 88E8036 Gigabit Ethernet" }, 194 { VENDORID_MARVELL, DEVICEID_MRVL_8038, 195 "Marvell Yukon 88E8038 Gigabit Ethernet" }, 196 { VENDORID_MARVELL, DEVICEID_MRVL_8039, 197 "Marvell Yukon 88E8039 Gigabit Ethernet" }, 198 { VENDORID_MARVELL, DEVICEID_MRVL_4361, 199 "Marvell Yukon 88E8050 Gigabit Ethernet" }, 200 { VENDORID_MARVELL, DEVICEID_MRVL_4360, 201 "Marvell Yukon 88E8052 Gigabit Ethernet" }, 202 { VENDORID_MARVELL, DEVICEID_MRVL_4362, 203 "Marvell Yukon 88E8053 Gigabit Ethernet" }, 204 { VENDORID_MARVELL, DEVICEID_MRVL_4363, 205 "Marvell Yukon 88E8055 Gigabit Ethernet" }, 206 { VENDORID_MARVELL, DEVICEID_MRVL_4364, 207 "Marvell Yukon 88E8056 Gigabit Ethernet" }, 208 { VENDORID_MARVELL, DEVICEID_MRVL_436A, 209 "Marvell Yukon 88E8058 Gigabit Ethernet" }, 210 { VENDORID_DLINK, DEVICEID_DLINK_DGE550SX, 211 "D-Link 550SX Gigabit Ethernet" }, 212 { VENDORID_DLINK, DEVICEID_DLINK_DGE560T, 213 "D-Link 560T Gigabit Ethernet" } 214 }; 215 216 static const char *model_name[] = { 217 "Yukon XL", 218 "Yukon EC Ultra", 219 "Yukon Unknown", 220 "Yukon EC", 221 "Yukon FE" 222 }; 223 224 static int mskc_probe(device_t); 225 static int mskc_attach(device_t); 226 static int mskc_detach(device_t); 227 static int mskc_shutdown(device_t); 228 static int mskc_setup_rambuffer(struct msk_softc *); 229 static int mskc_suspend(device_t); 230 static int mskc_resume(device_t); 231 static void mskc_reset(struct msk_softc *); 232 233 static int msk_probe(device_t); 234 static int msk_attach(device_t); 235 static int msk_detach(device_t); 236 237 static void msk_tick(void *); 238 static void msk_legacy_intr(void *); 239 static int msk_intr(void *); 240 static void msk_int_task(void *, int); 241 static void msk_intr_phy(struct msk_if_softc *); 242 static void msk_intr_gmac(struct msk_if_softc *); 243 static __inline void msk_rxput(struct msk_if_softc *); 244 static int msk_handle_events(struct msk_softc *); 245 static void msk_handle_hwerr(struct msk_if_softc *, uint32_t); 246 static void msk_intr_hwerr(struct msk_softc *); 247 static void msk_rxeof(struct msk_if_softc *, uint32_t, int); 248 static void msk_jumbo_rxeof(struct msk_if_softc *, uint32_t, int); 249 static void msk_txeof(struct msk_if_softc *, int); 250 static int msk_encap(struct msk_if_softc *, struct mbuf **); 251 static void msk_tx_task(void *, int); 252 static void msk_start(struct ifnet *); 253 static int msk_ioctl(struct ifnet *, u_long, caddr_t); 254 static void msk_set_prefetch(struct msk_softc *, int, bus_addr_t, uint32_t); 255 static void msk_set_rambuffer(struct msk_if_softc *); 256 static void msk_init(void *); 257 static void msk_init_locked(struct msk_if_softc *); 258 static void msk_stop(struct msk_if_softc *); 259 static void msk_watchdog(struct msk_if_softc *); 260 static int msk_mediachange(struct ifnet *); 261 static void msk_mediastatus(struct ifnet *, struct ifmediareq *); 262 static void msk_phy_power(struct msk_softc *, int); 263 static void msk_dmamap_cb(void *, bus_dma_segment_t *, int, int); 264 static int msk_status_dma_alloc(struct msk_softc *); 265 static void msk_status_dma_free(struct msk_softc *); 266 static int msk_txrx_dma_alloc(struct msk_if_softc *); 267 static void msk_txrx_dma_free(struct msk_if_softc *); 268 static void *msk_jalloc(struct msk_if_softc *); 269 static void msk_jfree(void *, void *); 270 static int msk_init_rx_ring(struct msk_if_softc *); 271 static int msk_init_jumbo_rx_ring(struct msk_if_softc *); 272 static void msk_init_tx_ring(struct msk_if_softc *); 273 static __inline void msk_discard_rxbuf(struct msk_if_softc *, int); 274 static __inline void msk_discard_jumbo_rxbuf(struct msk_if_softc *, int); 275 static int msk_newbuf(struct msk_if_softc *, int); 276 static int msk_jumbo_newbuf(struct msk_if_softc *, int); 277 278 static int msk_phy_readreg(struct msk_if_softc *, int, int); 279 static int msk_phy_writereg(struct msk_if_softc *, int, int, int); 280 static int msk_miibus_readreg(device_t, int, int); 281 static int msk_miibus_writereg(device_t, int, int, int); 282 static void msk_miibus_statchg(device_t); 283 static void msk_link_task(void *, int); 284 285 static void msk_setmulti(struct msk_if_softc *); 286 static void msk_setvlan(struct msk_if_softc *, struct ifnet *); 287 static void msk_setpromisc(struct msk_if_softc *); 288 289 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int); 290 static int sysctl_hw_msk_proc_limit(SYSCTL_HANDLER_ARGS); 291 292 static device_method_t mskc_methods[] = { 293 /* Device interface */ 294 DEVMETHOD(device_probe, mskc_probe), 295 DEVMETHOD(device_attach, mskc_attach), 296 DEVMETHOD(device_detach, mskc_detach), 297 DEVMETHOD(device_suspend, mskc_suspend), 298 DEVMETHOD(device_resume, mskc_resume), 299 DEVMETHOD(device_shutdown, mskc_shutdown), 300 301 /* bus interface */ 302 DEVMETHOD(bus_print_child, bus_generic_print_child), 303 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 304 305 { NULL, NULL } 306 }; 307 308 static driver_t mskc_driver = { 309 "mskc", 310 mskc_methods, 311 sizeof(struct msk_softc) 312 }; 313 314 static devclass_t mskc_devclass; 315 316 static device_method_t msk_methods[] = { 317 /* Device interface */ 318 DEVMETHOD(device_probe, msk_probe), 319 DEVMETHOD(device_attach, msk_attach), 320 DEVMETHOD(device_detach, msk_detach), 321 DEVMETHOD(device_shutdown, bus_generic_shutdown), 322 323 /* bus interface */ 324 DEVMETHOD(bus_print_child, bus_generic_print_child), 325 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 326 327 /* MII interface */ 328 DEVMETHOD(miibus_readreg, msk_miibus_readreg), 329 DEVMETHOD(miibus_writereg, msk_miibus_writereg), 330 DEVMETHOD(miibus_statchg, msk_miibus_statchg), 331 332 { NULL, NULL } 333 }; 334 335 static driver_t msk_driver = { 336 "msk", 337 msk_methods, 338 sizeof(struct msk_if_softc) 339 }; 340 341 static devclass_t msk_devclass; 342 343 DRIVER_MODULE(mskc, pci, mskc_driver, mskc_devclass, 0, 0); 344 DRIVER_MODULE(msk, mskc, msk_driver, msk_devclass, 0, 0); 345 DRIVER_MODULE(miibus, msk, miibus_driver, miibus_devclass, 0, 0); 346 347 static struct resource_spec msk_res_spec_io[] = { 348 { SYS_RES_IOPORT, PCIR_BAR(1), RF_ACTIVE }, 349 { -1, 0, 0 } 350 }; 351 352 static struct resource_spec msk_res_spec_mem[] = { 353 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 354 { -1, 0, 0 } 355 }; 356 357 static struct resource_spec msk_irq_spec_legacy[] = { 358 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 359 { -1, 0, 0 } 360 }; 361 362 static struct resource_spec msk_irq_spec_msi[] = { 363 { SYS_RES_IRQ, 1, RF_ACTIVE }, 364 { -1, 0, 0 } 365 }; 366 367 static struct resource_spec msk_irq_spec_msi2[] = { 368 { SYS_RES_IRQ, 1, RF_ACTIVE }, 369 { SYS_RES_IRQ, 2, RF_ACTIVE }, 370 { -1, 0, 0 } 371 }; 372 373 static int 374 msk_miibus_readreg(device_t dev, int phy, int reg) 375 { 376 struct msk_if_softc *sc_if; 377 378 if (phy != PHY_ADDR_MARV) 379 return (0); 380 381 sc_if = device_get_softc(dev); 382 383 return (msk_phy_readreg(sc_if, phy, reg)); 384 } 385 386 static int 387 msk_phy_readreg(struct msk_if_softc *sc_if, int phy, int reg) 388 { 389 struct msk_softc *sc; 390 int i, val; 391 392 sc = sc_if->msk_softc; 393 394 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SMI_CTRL, 395 GM_SMI_CT_PHY_AD(phy) | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD); 396 397 for (i = 0; i < MSK_TIMEOUT; i++) { 398 DELAY(1); 399 val = GMAC_READ_2(sc, sc_if->msk_port, GM_SMI_CTRL); 400 if ((val & GM_SMI_CT_RD_VAL) != 0) { 401 val = GMAC_READ_2(sc, sc_if->msk_port, GM_SMI_DATA); 402 break; 403 } 404 } 405 406 if (i == MSK_TIMEOUT) { 407 if_printf(sc_if->msk_ifp, "phy failed to come ready\n"); 408 val = 0; 409 } 410 411 return (val); 412 } 413 414 static int 415 msk_miibus_writereg(device_t dev, int phy, int reg, int val) 416 { 417 struct msk_if_softc *sc_if; 418 419 if (phy != PHY_ADDR_MARV) 420 return (0); 421 422 sc_if = device_get_softc(dev); 423 424 return (msk_phy_writereg(sc_if, phy, reg, val)); 425 } 426 427 static int 428 msk_phy_writereg(struct msk_if_softc *sc_if, int phy, int reg, int val) 429 { 430 struct msk_softc *sc; 431 int i; 432 433 sc = sc_if->msk_softc; 434 435 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SMI_DATA, val); 436 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SMI_CTRL, 437 GM_SMI_CT_PHY_AD(phy) | GM_SMI_CT_REG_AD(reg)); 438 for (i = 0; i < MSK_TIMEOUT; i++) { 439 DELAY(1); 440 if ((GMAC_READ_2(sc, sc_if->msk_port, GM_SMI_CTRL) & 441 GM_SMI_CT_BUSY) == 0) 442 break; 443 } 444 if (i == MSK_TIMEOUT) 445 if_printf(sc_if->msk_ifp, "phy write timeout\n"); 446 447 return (0); 448 } 449 450 static void 451 msk_miibus_statchg(device_t dev) 452 { 453 struct msk_if_softc *sc_if; 454 455 sc_if = device_get_softc(dev); 456 taskqueue_enqueue(taskqueue_swi, &sc_if->msk_link_task); 457 } 458 459 static void 460 msk_link_task(void *arg, int pending) 461 { 462 struct msk_softc *sc; 463 struct msk_if_softc *sc_if; 464 struct mii_data *mii; 465 struct ifnet *ifp; 466 uint32_t gmac; 467 468 sc_if = (struct msk_if_softc *)arg; 469 sc = sc_if->msk_softc; 470 471 MSK_IF_LOCK(sc_if); 472 473 mii = device_get_softc(sc_if->msk_miibus); 474 ifp = sc_if->msk_ifp; 475 if (mii == NULL || ifp == NULL) { 476 MSK_IF_UNLOCK(sc_if); 477 return; 478 } 479 480 if (mii->mii_media_status & IFM_ACTIVE) { 481 if (IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 482 sc_if->msk_link = 1; 483 } else 484 sc_if->msk_link = 0; 485 486 if (sc_if->msk_link != 0) { 487 /* Enable Tx FIFO Underrun. */ 488 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_MSK), 489 GM_IS_TX_FF_UR | GM_IS_RX_FF_OR); 490 /* 491 * Because mii(4) notify msk(4) that it detected link status 492 * change, there is no need to enable automatic 493 * speed/flow-control/duplex updates. 494 */ 495 gmac = GM_GPCR_AU_ALL_DIS; 496 switch (IFM_SUBTYPE(mii->mii_media_active)) { 497 case IFM_1000_SX: 498 case IFM_1000_T: 499 gmac |= GM_GPCR_SPEED_1000; 500 break; 501 case IFM_100_TX: 502 gmac |= GM_GPCR_SPEED_100; 503 break; 504 case IFM_10_T: 505 break; 506 } 507 508 if (((mii->mii_media_active & IFM_GMASK) & IFM_FDX) != 0) 509 gmac |= GM_GPCR_DUP_FULL; 510 /* Disable Rx flow control. */ 511 if (((mii->mii_media_active & IFM_GMASK) & IFM_FLAG0) == 0) 512 gmac |= GM_GPCR_FC_RX_DIS; 513 /* Disable Tx flow control. */ 514 if (((mii->mii_media_active & IFM_GMASK) & IFM_FLAG1) == 0) 515 gmac |= GM_GPCR_FC_TX_DIS; 516 gmac |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA; 517 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, gmac); 518 /* Read again to ensure writing. */ 519 GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL); 520 521 gmac = GMC_PAUSE_ON; 522 if (((mii->mii_media_active & IFM_GMASK) & 523 (IFM_FLAG0 | IFM_FLAG1)) == 0) 524 gmac = GMC_PAUSE_OFF; 525 /* Diable pause for 10/100 Mbps in half-duplex mode. */ 526 if ((((mii->mii_media_active & IFM_GMASK) & IFM_FDX) == 0) && 527 (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX || 528 IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T)) 529 gmac = GMC_PAUSE_OFF; 530 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), gmac); 531 532 /* Enable PHY interrupt for FIFO underrun/overflow. */ 533 msk_phy_writereg(sc_if, PHY_ADDR_MARV, 534 PHY_MARV_INT_MASK, PHY_M_IS_FIFO_ERROR); 535 } else { 536 /* 537 * Link state changed to down. 538 * Disable PHY interrupts. 539 */ 540 msk_phy_writereg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_MASK, 0); 541 /* Disable Rx/Tx MAC. */ 542 gmac = GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL); 543 gmac &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA); 544 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, gmac); 545 /* Read again to ensure writing. */ 546 GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL); 547 } 548 549 MSK_IF_UNLOCK(sc_if); 550 } 551 552 static void 553 msk_setmulti(struct msk_if_softc *sc_if) 554 { 555 struct msk_softc *sc; 556 struct ifnet *ifp; 557 struct ifmultiaddr *ifma; 558 uint32_t mchash[2]; 559 uint32_t crc; 560 uint16_t mode; 561 562 sc = sc_if->msk_softc; 563 564 MSK_IF_LOCK_ASSERT(sc_if); 565 566 ifp = sc_if->msk_ifp; 567 568 bzero(mchash, sizeof(mchash)); 569 mode = GMAC_READ_2(sc, sc_if->msk_port, GM_RX_CTRL); 570 mode |= GM_RXCR_UCF_ENA; 571 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 572 if ((ifp->if_flags & IFF_PROMISC) != 0) 573 mode &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA); 574 else if ((ifp->if_flags & IFF_ALLMULTI) != 0) { 575 mchash[0] = 0xffff; 576 mchash[1] = 0xffff; 577 } 578 } else { 579 IF_ADDR_LOCK(ifp); 580 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 581 if (ifma->ifma_addr->sa_family != AF_LINK) 582 continue; 583 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *) 584 ifma->ifma_addr), ETHER_ADDR_LEN); 585 /* Just want the 6 least significant bits. */ 586 crc &= 0x3f; 587 /* Set the corresponding bit in the hash table. */ 588 mchash[crc >> 5] |= 1 << (crc & 0x1f); 589 } 590 IF_ADDR_UNLOCK(ifp); 591 mode |= GM_RXCR_MCF_ENA; 592 } 593 594 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H1, 595 mchash[0] & 0xffff); 596 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H2, 597 (mchash[0] >> 16) & 0xffff); 598 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H3, 599 mchash[1] & 0xffff); 600 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H4, 601 (mchash[1] >> 16) & 0xffff); 602 GMAC_WRITE_2(sc, sc_if->msk_port, GM_RX_CTRL, mode); 603 } 604 605 static void 606 msk_setvlan(struct msk_if_softc *sc_if, struct ifnet *ifp) 607 { 608 struct msk_softc *sc; 609 610 sc = sc_if->msk_softc; 611 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) { 612 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), 613 RX_VLAN_STRIP_ON); 614 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 615 TX_VLAN_TAG_ON); 616 } else { 617 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), 618 RX_VLAN_STRIP_OFF); 619 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 620 TX_VLAN_TAG_OFF); 621 } 622 } 623 624 static void 625 msk_setpromisc(struct msk_if_softc *sc_if) 626 { 627 struct msk_softc *sc; 628 struct ifnet *ifp; 629 uint16_t mode; 630 631 MSK_IF_LOCK_ASSERT(sc_if); 632 633 sc = sc_if->msk_softc; 634 ifp = sc_if->msk_ifp; 635 636 mode = GMAC_READ_2(sc, sc_if->msk_port, GM_RX_CTRL); 637 if (ifp->if_flags & IFF_PROMISC) 638 mode &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA); 639 else 640 mode |= (GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA); 641 GMAC_WRITE_2(sc, sc_if->msk_port, GM_RX_CTRL, mode); 642 } 643 644 static int 645 msk_init_rx_ring(struct msk_if_softc *sc_if) 646 { 647 struct msk_ring_data *rd; 648 struct msk_rxdesc *rxd; 649 int i, prod; 650 651 MSK_IF_LOCK_ASSERT(sc_if); 652 653 sc_if->msk_cdata.msk_rx_cons = 0; 654 sc_if->msk_cdata.msk_rx_prod = 0; 655 sc_if->msk_cdata.msk_rx_putwm = MSK_PUT_WM; 656 657 rd = &sc_if->msk_rdata; 658 bzero(rd->msk_rx_ring, sizeof(struct msk_rx_desc) * MSK_RX_RING_CNT); 659 prod = sc_if->msk_cdata.msk_rx_prod; 660 for (i = 0; i < MSK_RX_RING_CNT; i++) { 661 rxd = &sc_if->msk_cdata.msk_rxdesc[prod]; 662 rxd->rx_m = NULL; 663 rxd->rx_le = &rd->msk_rx_ring[prod]; 664 if (msk_newbuf(sc_if, prod) != 0) 665 return (ENOBUFS); 666 MSK_INC(prod, MSK_RX_RING_CNT); 667 } 668 669 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_ring_tag, 670 sc_if->msk_cdata.msk_rx_ring_map, 671 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 672 673 /* Update prefetch unit. */ 674 sc_if->msk_cdata.msk_rx_prod = MSK_RX_RING_CNT - 1; 675 CSR_WRITE_2(sc_if->msk_softc, 676 Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_PUT_IDX_REG), 677 sc_if->msk_cdata.msk_rx_prod); 678 679 return (0); 680 } 681 682 static int 683 msk_init_jumbo_rx_ring(struct msk_if_softc *sc_if) 684 { 685 struct msk_ring_data *rd; 686 struct msk_rxdesc *rxd; 687 int i, prod; 688 689 MSK_IF_LOCK_ASSERT(sc_if); 690 691 sc_if->msk_cdata.msk_rx_cons = 0; 692 sc_if->msk_cdata.msk_rx_prod = 0; 693 sc_if->msk_cdata.msk_rx_putwm = MSK_PUT_WM; 694 695 rd = &sc_if->msk_rdata; 696 bzero(rd->msk_jumbo_rx_ring, 697 sizeof(struct msk_rx_desc) * MSK_JUMBO_RX_RING_CNT); 698 prod = sc_if->msk_cdata.msk_rx_prod; 699 for (i = 0; i < MSK_JUMBO_RX_RING_CNT; i++) { 700 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[prod]; 701 rxd->rx_m = NULL; 702 rxd->rx_le = &rd->msk_jumbo_rx_ring[prod]; 703 if (msk_jumbo_newbuf(sc_if, prod) != 0) 704 return (ENOBUFS); 705 MSK_INC(prod, MSK_JUMBO_RX_RING_CNT); 706 } 707 708 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 709 sc_if->msk_cdata.msk_jumbo_rx_ring_map, 710 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 711 712 sc_if->msk_cdata.msk_rx_prod = MSK_JUMBO_RX_RING_CNT - 1; 713 CSR_WRITE_2(sc_if->msk_softc, 714 Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_PUT_IDX_REG), 715 sc_if->msk_cdata.msk_rx_prod); 716 717 return (0); 718 } 719 720 static void 721 msk_init_tx_ring(struct msk_if_softc *sc_if) 722 { 723 struct msk_ring_data *rd; 724 struct msk_txdesc *txd; 725 int i; 726 727 sc_if->msk_cdata.msk_tso_mtu = 0; 728 sc_if->msk_cdata.msk_tx_prod = 0; 729 sc_if->msk_cdata.msk_tx_cons = 0; 730 sc_if->msk_cdata.msk_tx_cnt = 0; 731 732 rd = &sc_if->msk_rdata; 733 bzero(rd->msk_tx_ring, sizeof(struct msk_tx_desc) * MSK_TX_RING_CNT); 734 for (i = 0; i < MSK_TX_RING_CNT; i++) { 735 txd = &sc_if->msk_cdata.msk_txdesc[i]; 736 txd->tx_m = NULL; 737 txd->tx_le = &rd->msk_tx_ring[i]; 738 } 739 740 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_ring_tag, 741 sc_if->msk_cdata.msk_tx_ring_map, 742 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 743 } 744 745 static __inline void 746 msk_discard_rxbuf(struct msk_if_softc *sc_if, int idx) 747 { 748 struct msk_rx_desc *rx_le; 749 struct msk_rxdesc *rxd; 750 struct mbuf *m; 751 752 rxd = &sc_if->msk_cdata.msk_rxdesc[idx]; 753 m = rxd->rx_m; 754 rx_le = rxd->rx_le; 755 rx_le->msk_control = htole32(m->m_len | OP_PACKET | HW_OWNER); 756 } 757 758 static __inline void 759 msk_discard_jumbo_rxbuf(struct msk_if_softc *sc_if, int idx) 760 { 761 struct msk_rx_desc *rx_le; 762 struct msk_rxdesc *rxd; 763 struct mbuf *m; 764 765 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[idx]; 766 m = rxd->rx_m; 767 rx_le = rxd->rx_le; 768 rx_le->msk_control = htole32(m->m_len | OP_PACKET | HW_OWNER); 769 } 770 771 static int 772 msk_newbuf(struct msk_if_softc *sc_if, int idx) 773 { 774 struct msk_rx_desc *rx_le; 775 struct msk_rxdesc *rxd; 776 struct mbuf *m; 777 bus_dma_segment_t segs[1]; 778 bus_dmamap_t map; 779 int nsegs; 780 781 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 782 if (m == NULL) 783 return (ENOBUFS); 784 785 m->m_len = m->m_pkthdr.len = MCLBYTES; 786 m_adj(m, ETHER_ALIGN); 787 788 if (bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_rx_tag, 789 sc_if->msk_cdata.msk_rx_sparemap, m, segs, &nsegs, 790 BUS_DMA_NOWAIT) != 0) { 791 m_freem(m); 792 return (ENOBUFS); 793 } 794 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 795 796 rxd = &sc_if->msk_cdata.msk_rxdesc[idx]; 797 if (rxd->rx_m != NULL) { 798 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_tag, rxd->rx_dmamap, 799 BUS_DMASYNC_POSTREAD); 800 bus_dmamap_unload(sc_if->msk_cdata.msk_rx_tag, rxd->rx_dmamap); 801 } 802 map = rxd->rx_dmamap; 803 rxd->rx_dmamap = sc_if->msk_cdata.msk_rx_sparemap; 804 sc_if->msk_cdata.msk_rx_sparemap = map; 805 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_tag, rxd->rx_dmamap, 806 BUS_DMASYNC_PREREAD); 807 rxd->rx_m = m; 808 rx_le = rxd->rx_le; 809 rx_le->msk_addr = htole32(MSK_ADDR_LO(segs[0].ds_addr)); 810 rx_le->msk_control = 811 htole32(segs[0].ds_len | OP_PACKET | HW_OWNER); 812 813 return (0); 814 } 815 816 static int 817 msk_jumbo_newbuf(struct msk_if_softc *sc_if, int idx) 818 { 819 struct msk_rx_desc *rx_le; 820 struct msk_rxdesc *rxd; 821 struct mbuf *m; 822 bus_dma_segment_t segs[1]; 823 bus_dmamap_t map; 824 int nsegs; 825 void *buf; 826 827 MGETHDR(m, M_DONTWAIT, MT_DATA); 828 if (m == NULL) 829 return (ENOBUFS); 830 buf = msk_jalloc(sc_if); 831 if (buf == NULL) { 832 m_freem(m); 833 return (ENOBUFS); 834 } 835 /* Attach the buffer to the mbuf. */ 836 MEXTADD(m, buf, MSK_JLEN, msk_jfree, buf, 837 (struct msk_if_softc *)sc_if, 0, EXT_NET_DRV); 838 if ((m->m_flags & M_EXT) == 0) { 839 m_freem(m); 840 return (ENOBUFS); 841 } 842 m->m_pkthdr.len = m->m_len = MSK_JLEN; 843 m_adj(m, ETHER_ALIGN); 844 845 if (bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_jumbo_rx_tag, 846 sc_if->msk_cdata.msk_jumbo_rx_sparemap, m, segs, &nsegs, 847 BUS_DMA_NOWAIT) != 0) { 848 m_freem(m); 849 return (ENOBUFS); 850 } 851 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 852 853 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[idx]; 854 if (rxd->rx_m != NULL) { 855 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_tag, 856 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 857 bus_dmamap_unload(sc_if->msk_cdata.msk_jumbo_rx_tag, 858 rxd->rx_dmamap); 859 } 860 map = rxd->rx_dmamap; 861 rxd->rx_dmamap = sc_if->msk_cdata.msk_jumbo_rx_sparemap; 862 sc_if->msk_cdata.msk_jumbo_rx_sparemap = map; 863 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_tag, rxd->rx_dmamap, 864 BUS_DMASYNC_PREREAD); 865 rxd->rx_m = m; 866 rx_le = rxd->rx_le; 867 rx_le->msk_addr = htole32(MSK_ADDR_LO(segs[0].ds_addr)); 868 rx_le->msk_control = 869 htole32(segs[0].ds_len | OP_PACKET | HW_OWNER); 870 871 return (0); 872 } 873 874 /* 875 * Set media options. 876 */ 877 static int 878 msk_mediachange(struct ifnet *ifp) 879 { 880 struct msk_if_softc *sc_if; 881 struct mii_data *mii; 882 883 sc_if = ifp->if_softc; 884 885 MSK_IF_LOCK(sc_if); 886 mii = device_get_softc(sc_if->msk_miibus); 887 mii_mediachg(mii); 888 MSK_IF_UNLOCK(sc_if); 889 890 return (0); 891 } 892 893 /* 894 * Report current media status. 895 */ 896 static void 897 msk_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 898 { 899 struct msk_if_softc *sc_if; 900 struct mii_data *mii; 901 902 sc_if = ifp->if_softc; 903 MSK_IF_LOCK(sc_if); 904 mii = device_get_softc(sc_if->msk_miibus); 905 906 mii_pollstat(mii); 907 MSK_IF_UNLOCK(sc_if); 908 ifmr->ifm_active = mii->mii_media_active; 909 ifmr->ifm_status = mii->mii_media_status; 910 } 911 912 static int 913 msk_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 914 { 915 struct msk_if_softc *sc_if; 916 struct ifreq *ifr; 917 struct mii_data *mii; 918 int error, mask; 919 920 sc_if = ifp->if_softc; 921 ifr = (struct ifreq *)data; 922 error = 0; 923 924 switch(command) { 925 case SIOCSIFMTU: 926 if (ifr->ifr_mtu > MSK_JUMBO_MTU || ifr->ifr_mtu < ETHERMIN) { 927 error = EINVAL; 928 break; 929 } 930 if (sc_if->msk_softc->msk_hw_id == CHIP_ID_YUKON_FE && 931 ifr->ifr_mtu > MSK_MAX_FRAMELEN) { 932 error = EINVAL; 933 break; 934 } 935 MSK_IF_LOCK(sc_if); 936 ifp->if_mtu = ifr->ifr_mtu; 937 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 938 msk_init_locked(sc_if); 939 MSK_IF_UNLOCK(sc_if); 940 break; 941 case SIOCSIFFLAGS: 942 MSK_IF_LOCK(sc_if); 943 if ((ifp->if_flags & IFF_UP) != 0) { 944 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 945 if (((ifp->if_flags ^ sc_if->msk_if_flags) 946 & IFF_PROMISC) != 0) { 947 msk_setpromisc(sc_if); 948 msk_setmulti(sc_if); 949 } 950 } else { 951 if (sc_if->msk_detach == 0) 952 msk_init_locked(sc_if); 953 } 954 } else { 955 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 956 msk_stop(sc_if); 957 } 958 sc_if->msk_if_flags = ifp->if_flags; 959 MSK_IF_UNLOCK(sc_if); 960 break; 961 case SIOCADDMULTI: 962 case SIOCDELMULTI: 963 MSK_IF_LOCK(sc_if); 964 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 965 msk_setmulti(sc_if); 966 MSK_IF_UNLOCK(sc_if); 967 break; 968 case SIOCGIFMEDIA: 969 case SIOCSIFMEDIA: 970 mii = device_get_softc(sc_if->msk_miibus); 971 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 972 break; 973 case SIOCSIFCAP: 974 MSK_IF_LOCK(sc_if); 975 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 976 if ((mask & IFCAP_TXCSUM) != 0) { 977 ifp->if_capenable ^= IFCAP_TXCSUM; 978 if ((IFCAP_TXCSUM & ifp->if_capenable) != 0 && 979 (IFCAP_TXCSUM & ifp->if_capabilities) != 0) 980 ifp->if_hwassist |= MSK_CSUM_FEATURES; 981 else 982 ifp->if_hwassist &= ~MSK_CSUM_FEATURES; 983 } 984 if ((mask & IFCAP_VLAN_HWTAGGING) != 0) { 985 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 986 msk_setvlan(sc_if, ifp); 987 } 988 989 if ((mask & IFCAP_TSO4) != 0) { 990 ifp->if_capenable ^= IFCAP_TSO4; 991 if ((IFCAP_TSO4 & ifp->if_capenable) != 0 && 992 (IFCAP_TSO4 & ifp->if_capabilities) != 0) 993 ifp->if_hwassist |= CSUM_TSO; 994 else 995 ifp->if_hwassist &= ~CSUM_TSO; 996 } 997 if (sc_if->msk_framesize > MSK_MAX_FRAMELEN && 998 sc_if->msk_softc->msk_hw_id == CHIP_ID_YUKON_EC_U) { 999 /* 1000 * In Yukon EC Ultra, TSO & checksum offload is not 1001 * supported for jumbo frame. 1002 */ 1003 ifp->if_hwassist &= ~(MSK_CSUM_FEATURES | CSUM_TSO); 1004 ifp->if_capenable &= ~(IFCAP_TSO4 | IFCAP_TXCSUM); 1005 } 1006 1007 VLAN_CAPABILITIES(ifp); 1008 MSK_IF_UNLOCK(sc_if); 1009 break; 1010 default: 1011 error = ether_ioctl(ifp, command, data); 1012 break; 1013 } 1014 1015 return (error); 1016 } 1017 1018 static int 1019 mskc_probe(device_t dev) 1020 { 1021 struct msk_product *mp; 1022 uint16_t vendor, devid; 1023 int i; 1024 1025 vendor = pci_get_vendor(dev); 1026 devid = pci_get_device(dev); 1027 mp = msk_products; 1028 for (i = 0; i < sizeof(msk_products)/sizeof(msk_products[0]); 1029 i++, mp++) { 1030 if (vendor == mp->msk_vendorid && devid == mp->msk_deviceid) { 1031 device_set_desc(dev, mp->msk_name); 1032 return (BUS_PROBE_DEFAULT); 1033 } 1034 } 1035 1036 return (ENXIO); 1037 } 1038 1039 static int 1040 mskc_setup_rambuffer(struct msk_softc *sc) 1041 { 1042 int next; 1043 int i; 1044 uint8_t val; 1045 1046 /* Get adapter SRAM size. */ 1047 val = CSR_READ_1(sc, B2_E_0); 1048 sc->msk_ramsize = (val == 0) ? 128 : val * 4; 1049 if (bootverbose) 1050 device_printf(sc->msk_dev, 1051 "RAM buffer size : %dKB\n", sc->msk_ramsize); 1052 /* 1053 * Give receiver 2/3 of memory and round down to the multiple 1054 * of 1024. Tx/Rx RAM buffer size of Yukon II shoud be multiple 1055 * of 1024. 1056 */ 1057 sc->msk_rxqsize = rounddown((sc->msk_ramsize * 1024 * 2) / 3, 1024); 1058 sc->msk_txqsize = (sc->msk_ramsize * 1024) - sc->msk_rxqsize; 1059 for (i = 0, next = 0; i < sc->msk_num_port; i++) { 1060 sc->msk_rxqstart[i] = next; 1061 sc->msk_rxqend[i] = next + sc->msk_rxqsize - 1; 1062 next = sc->msk_rxqend[i] + 1; 1063 sc->msk_txqstart[i] = next; 1064 sc->msk_txqend[i] = next + sc->msk_txqsize - 1; 1065 next = sc->msk_txqend[i] + 1; 1066 if (bootverbose) { 1067 device_printf(sc->msk_dev, 1068 "Port %d : Rx Queue %dKB(0x%08x:0x%08x)\n", i, 1069 sc->msk_rxqsize / 1024, sc->msk_rxqstart[i], 1070 sc->msk_rxqend[i]); 1071 device_printf(sc->msk_dev, 1072 "Port %d : Tx Queue %dKB(0x%08x:0x%08x)\n", i, 1073 sc->msk_txqsize / 1024, sc->msk_txqstart[i], 1074 sc->msk_txqend[i]); 1075 } 1076 } 1077 1078 return (0); 1079 } 1080 1081 static void 1082 msk_phy_power(struct msk_softc *sc, int mode) 1083 { 1084 uint32_t val; 1085 int i; 1086 1087 switch (mode) { 1088 case MSK_PHY_POWERUP: 1089 /* Switch power to VCC (WA for VAUX problem). */ 1090 CSR_WRITE_1(sc, B0_POWER_CTRL, 1091 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON); 1092 /* Disable Core Clock Division, set Clock Select to 0. */ 1093 CSR_WRITE_4(sc, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS); 1094 1095 val = 0; 1096 if (sc->msk_hw_id == CHIP_ID_YUKON_XL && 1097 sc->msk_hw_rev > CHIP_REV_YU_XL_A1) { 1098 /* Enable bits are inverted. */ 1099 val = Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS | 1100 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS | 1101 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS; 1102 } 1103 /* 1104 * Enable PCI & Core Clock, enable clock gating for both Links. 1105 */ 1106 CSR_WRITE_1(sc, B2_Y2_CLK_GATE, val); 1107 1108 val = pci_read_config(sc->msk_dev, PCI_OUR_REG_1, 4); 1109 val &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD); 1110 if (sc->msk_hw_id == CHIP_ID_YUKON_XL && 1111 sc->msk_hw_rev > CHIP_REV_YU_XL_A1) { 1112 /* Deassert Low Power for 1st PHY. */ 1113 val |= PCI_Y2_PHY1_COMA; 1114 if (sc->msk_num_port > 1) 1115 val |= PCI_Y2_PHY2_COMA; 1116 } else if (sc->msk_hw_id == CHIP_ID_YUKON_EC_U) { 1117 uint32_t our; 1118 1119 CSR_WRITE_2(sc, B0_CTST, Y2_HW_WOL_ON); 1120 1121 /* Enable all clocks. */ 1122 pci_write_config(sc->msk_dev, PCI_OUR_REG_3, 0, 4); 1123 our = pci_read_config(sc->msk_dev, PCI_OUR_REG_4, 4); 1124 our &= (PCI_FORCE_ASPM_REQUEST|PCI_ASPM_GPHY_LINK_DOWN| 1125 PCI_ASPM_INT_FIFO_EMPTY|PCI_ASPM_CLKRUN_REQUEST); 1126 /* Set all bits to 0 except bits 15..12. */ 1127 pci_write_config(sc->msk_dev, PCI_OUR_REG_4, our, 4); 1128 /* Set to default value. */ 1129 pci_write_config(sc->msk_dev, PCI_OUR_REG_5, 0, 4); 1130 } 1131 /* Release PHY from PowerDown/COMA mode. */ 1132 pci_write_config(sc->msk_dev, PCI_OUR_REG_1, val, 4); 1133 for (i = 0; i < sc->msk_num_port; i++) { 1134 CSR_WRITE_2(sc, MR_ADDR(i, GMAC_LINK_CTRL), 1135 GMLC_RST_SET); 1136 CSR_WRITE_2(sc, MR_ADDR(i, GMAC_LINK_CTRL), 1137 GMLC_RST_CLR); 1138 } 1139 break; 1140 case MSK_PHY_POWERDOWN: 1141 val = pci_read_config(sc->msk_dev, PCI_OUR_REG_1, 4); 1142 val |= PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD; 1143 if (sc->msk_hw_id == CHIP_ID_YUKON_XL && 1144 sc->msk_hw_rev > CHIP_REV_YU_XL_A1) { 1145 val &= ~PCI_Y2_PHY1_COMA; 1146 if (sc->msk_num_port > 1) 1147 val &= ~PCI_Y2_PHY2_COMA; 1148 } 1149 pci_write_config(sc->msk_dev, PCI_OUR_REG_1, val, 4); 1150 1151 val = Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS | 1152 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS | 1153 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS; 1154 if (sc->msk_hw_id == CHIP_ID_YUKON_XL && 1155 sc->msk_hw_rev > CHIP_REV_YU_XL_A1) { 1156 /* Enable bits are inverted. */ 1157 val = 0; 1158 } 1159 /* 1160 * Disable PCI & Core Clock, disable clock gating for 1161 * both Links. 1162 */ 1163 CSR_WRITE_1(sc, B2_Y2_CLK_GATE, val); 1164 CSR_WRITE_1(sc, B0_POWER_CTRL, 1165 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_ON | PC_VCC_OFF); 1166 break; 1167 default: 1168 break; 1169 } 1170 } 1171 1172 static void 1173 mskc_reset(struct msk_softc *sc) 1174 { 1175 bus_addr_t addr; 1176 uint16_t status; 1177 uint32_t val; 1178 int i; 1179 1180 CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR); 1181 1182 /* Disable ASF. */ 1183 if (sc->msk_hw_id < CHIP_ID_YUKON_XL) { 1184 CSR_WRITE_4(sc, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET); 1185 CSR_WRITE_2(sc, B0_CTST, Y2_ASF_DISABLE); 1186 } 1187 /* 1188 * Since we disabled ASF, S/W reset is required for Power Management. 1189 */ 1190 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); 1191 CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR); 1192 1193 /* Clear all error bits in the PCI status register. */ 1194 status = pci_read_config(sc->msk_dev, PCIR_STATUS, 2); 1195 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON); 1196 1197 pci_write_config(sc->msk_dev, PCIR_STATUS, status | 1198 PCIM_STATUS_PERR | PCIM_STATUS_SERR | PCIM_STATUS_RMABORT | 1199 PCIM_STATUS_RTABORT | PCIM_STATUS_PERRREPORT, 2); 1200 CSR_WRITE_2(sc, B0_CTST, CS_MRST_CLR); 1201 1202 switch (sc->msk_bustype) { 1203 case MSK_PEX_BUS: 1204 /* Clear all PEX errors. */ 1205 CSR_PCI_WRITE_4(sc, PEX_UNC_ERR_STAT, 0xffffffff); 1206 val = CSR_PCI_READ_4(sc, PEX_UNC_ERR_STAT); 1207 if ((val & PEX_RX_OV) != 0) { 1208 sc->msk_intrmask &= ~Y2_IS_HW_ERR; 1209 sc->msk_intrhwemask &= ~Y2_IS_PCI_EXP; 1210 } 1211 break; 1212 case MSK_PCI_BUS: 1213 case MSK_PCIX_BUS: 1214 /* Set Cache Line Size to 2(8bytes) if configured to 0. */ 1215 val = pci_read_config(sc->msk_dev, PCIR_CACHELNSZ, 1); 1216 if (val == 0) 1217 pci_write_config(sc->msk_dev, PCIR_CACHELNSZ, 2, 1); 1218 if (sc->msk_bustype == MSK_PCIX_BUS) { 1219 /* Set Cache Line Size opt. */ 1220 val = pci_read_config(sc->msk_dev, PCI_OUR_REG_1, 4); 1221 val |= PCI_CLS_OPT; 1222 pci_write_config(sc->msk_dev, PCI_OUR_REG_1, val, 4); 1223 } 1224 break; 1225 } 1226 /* Set PHY power state. */ 1227 msk_phy_power(sc, MSK_PHY_POWERUP); 1228 1229 /* Reset GPHY/GMAC Control */ 1230 for (i = 0; i < sc->msk_num_port; i++) { 1231 /* GPHY Control reset. */ 1232 CSR_WRITE_4(sc, MR_ADDR(i, GPHY_CTRL), GPC_RST_SET); 1233 CSR_WRITE_4(sc, MR_ADDR(i, GPHY_CTRL), GPC_RST_CLR); 1234 /* GMAC Control reset. */ 1235 CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), GMC_RST_SET); 1236 CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), GMC_RST_CLR); 1237 CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), GMC_F_LOOPB_OFF); 1238 } 1239 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 1240 1241 /* LED On. */ 1242 CSR_WRITE_2(sc, B0_CTST, Y2_LED_STAT_ON); 1243 1244 /* Clear TWSI IRQ. */ 1245 CSR_WRITE_4(sc, B2_I2C_IRQ, I2C_CLR_IRQ); 1246 1247 /* Turn off hardware timer. */ 1248 CSR_WRITE_1(sc, B2_TI_CTRL, TIM_STOP); 1249 CSR_WRITE_1(sc, B2_TI_CTRL, TIM_CLR_IRQ); 1250 1251 /* Turn off descriptor polling. */ 1252 CSR_WRITE_1(sc, B28_DPT_CTRL, DPT_STOP); 1253 1254 /* Turn off time stamps. */ 1255 CSR_WRITE_1(sc, GMAC_TI_ST_CTRL, GMT_ST_STOP); 1256 CSR_WRITE_1(sc, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ); 1257 1258 /* Configure timeout values. */ 1259 for (i = 0; i < sc->msk_num_port; i++) { 1260 CSR_WRITE_2(sc, SELECT_RAM_BUFFER(i, B3_RI_CTRL), RI_RST_SET); 1261 CSR_WRITE_2(sc, SELECT_RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR); 1262 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_R1), 1263 MSK_RI_TO_53); 1264 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XA1), 1265 MSK_RI_TO_53); 1266 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XS1), 1267 MSK_RI_TO_53); 1268 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_R1), 1269 MSK_RI_TO_53); 1270 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XA1), 1271 MSK_RI_TO_53); 1272 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XS1), 1273 MSK_RI_TO_53); 1274 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_R2), 1275 MSK_RI_TO_53); 1276 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XA2), 1277 MSK_RI_TO_53); 1278 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XS2), 1279 MSK_RI_TO_53); 1280 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_R2), 1281 MSK_RI_TO_53); 1282 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XA2), 1283 MSK_RI_TO_53); 1284 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XS2), 1285 MSK_RI_TO_53); 1286 } 1287 1288 /* Disable all interrupts. */ 1289 CSR_WRITE_4(sc, B0_HWE_IMSK, 0); 1290 CSR_READ_4(sc, B0_HWE_IMSK); 1291 CSR_WRITE_4(sc, B0_IMSK, 0); 1292 CSR_READ_4(sc, B0_IMSK); 1293 1294 /* 1295 * On dual port PCI-X card, there is an problem where status 1296 * can be received out of order due to split transactions. 1297 */ 1298 if (sc->msk_bustype == MSK_PCIX_BUS && sc->msk_num_port > 1) { 1299 int pcix; 1300 uint16_t pcix_cmd; 1301 1302 if (pci_find_extcap(sc->msk_dev, PCIY_PCIX, &pcix) == 0) { 1303 pcix_cmd = pci_read_config(sc->msk_dev, pcix + 2, 2); 1304 /* Clear Max Outstanding Split Transactions. */ 1305 pcix_cmd &= ~0x70; 1306 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON); 1307 pci_write_config(sc->msk_dev, pcix + 2, pcix_cmd, 2); 1308 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 1309 } 1310 } 1311 if (sc->msk_bustype == MSK_PEX_BUS) { 1312 uint16_t v, width; 1313 1314 v = pci_read_config(sc->msk_dev, PEX_DEV_CTRL, 2); 1315 /* Change Max. Read Request Size to 4096 bytes. */ 1316 v &= ~PEX_DC_MAX_RRS_MSK; 1317 v |= PEX_DC_MAX_RD_RQ_SIZE(5); 1318 pci_write_config(sc->msk_dev, PEX_DEV_CTRL, v, 2); 1319 width = pci_read_config(sc->msk_dev, PEX_LNK_STAT, 2); 1320 width = (width & PEX_LS_LINK_WI_MSK) >> 4; 1321 v = pci_read_config(sc->msk_dev, PEX_LNK_CAP, 2); 1322 v = (v & PEX_LS_LINK_WI_MSK) >> 4; 1323 if (v != width) 1324 device_printf(sc->msk_dev, 1325 "negotiated width of link(x%d) != " 1326 "max. width of link(x%d)\n", width, v); 1327 } 1328 1329 /* Clear status list. */ 1330 bzero(sc->msk_stat_ring, 1331 sizeof(struct msk_stat_desc) * MSK_STAT_RING_CNT); 1332 sc->msk_stat_cons = 0; 1333 bus_dmamap_sync(sc->msk_stat_tag, sc->msk_stat_map, 1334 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1335 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_RST_SET); 1336 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_RST_CLR); 1337 /* Set the status list base address. */ 1338 addr = sc->msk_stat_ring_paddr; 1339 CSR_WRITE_4(sc, STAT_LIST_ADDR_LO, MSK_ADDR_LO(addr)); 1340 CSR_WRITE_4(sc, STAT_LIST_ADDR_HI, MSK_ADDR_HI(addr)); 1341 /* Set the status list last index. */ 1342 CSR_WRITE_2(sc, STAT_LAST_IDX, MSK_STAT_RING_CNT - 1); 1343 if (sc->msk_hw_id == CHIP_ID_YUKON_EC && 1344 sc->msk_hw_rev == CHIP_REV_YU_EC_A1) { 1345 /* WA for dev. #4.3 */ 1346 CSR_WRITE_2(sc, STAT_TX_IDX_TH, ST_TXTH_IDX_MASK); 1347 /* WA for dev. #4.18 */ 1348 CSR_WRITE_1(sc, STAT_FIFO_WM, 0x21); 1349 CSR_WRITE_1(sc, STAT_FIFO_ISR_WM, 0x07); 1350 } else { 1351 CSR_WRITE_2(sc, STAT_TX_IDX_TH, 0x0a); 1352 CSR_WRITE_1(sc, STAT_FIFO_WM, 0x10); 1353 if (sc->msk_hw_id == CHIP_ID_YUKON_XL && 1354 sc->msk_hw_rev == CHIP_REV_YU_XL_A0) 1355 CSR_WRITE_1(sc, STAT_FIFO_ISR_WM, 0x04); 1356 else 1357 CSR_WRITE_1(sc, STAT_FIFO_ISR_WM, 0x10); 1358 CSR_WRITE_4(sc, STAT_ISR_TIMER_INI, 0x0190); 1359 } 1360 /* 1361 * Use default value for STAT_ISR_TIMER_INI, STAT_LEV_TIMER_INI. 1362 */ 1363 CSR_WRITE_4(sc, STAT_TX_TIMER_INI, MSK_USECS(sc, 1000)); 1364 1365 /* Enable status unit. */ 1366 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_OP_ON); 1367 1368 CSR_WRITE_1(sc, STAT_TX_TIMER_CTRL, TIM_START); 1369 CSR_WRITE_1(sc, STAT_LEV_TIMER_CTRL, TIM_START); 1370 CSR_WRITE_1(sc, STAT_ISR_TIMER_CTRL, TIM_START); 1371 } 1372 1373 static int 1374 msk_probe(device_t dev) 1375 { 1376 struct msk_softc *sc; 1377 char desc[100]; 1378 1379 sc = device_get_softc(device_get_parent(dev)); 1380 /* 1381 * Not much to do here. We always know there will be 1382 * at least one GMAC present, and if there are two, 1383 * mskc_attach() will create a second device instance 1384 * for us. 1385 */ 1386 snprintf(desc, sizeof(desc), 1387 "Marvell Technology Group Ltd. %s Id 0x%02x Rev 0x%02x", 1388 model_name[sc->msk_hw_id - CHIP_ID_YUKON_XL], sc->msk_hw_id, 1389 sc->msk_hw_rev); 1390 device_set_desc_copy(dev, desc); 1391 1392 return (BUS_PROBE_DEFAULT); 1393 } 1394 1395 static int 1396 msk_attach(device_t dev) 1397 { 1398 struct msk_softc *sc; 1399 struct msk_if_softc *sc_if; 1400 struct ifnet *ifp; 1401 int i, port, error; 1402 uint8_t eaddr[6]; 1403 1404 if (dev == NULL) 1405 return (EINVAL); 1406 1407 error = 0; 1408 sc_if = device_get_softc(dev); 1409 sc = device_get_softc(device_get_parent(dev)); 1410 port = *(int *)device_get_ivars(dev); 1411 1412 sc_if->msk_if_dev = dev; 1413 sc_if->msk_port = port; 1414 sc_if->msk_softc = sc; 1415 sc->msk_if[port] = sc_if; 1416 /* Setup Tx/Rx queue register offsets. */ 1417 if (port == MSK_PORT_A) { 1418 sc_if->msk_txq = Q_XA1; 1419 sc_if->msk_txsq = Q_XS1; 1420 sc_if->msk_rxq = Q_R1; 1421 } else { 1422 sc_if->msk_txq = Q_XA2; 1423 sc_if->msk_txsq = Q_XS2; 1424 sc_if->msk_rxq = Q_R2; 1425 } 1426 1427 callout_init_mtx(&sc_if->msk_tick_ch, &sc_if->msk_softc->msk_mtx, 0); 1428 TASK_INIT(&sc_if->msk_link_task, 0, msk_link_task, sc_if); 1429 1430 if ((error = msk_txrx_dma_alloc(sc_if) != 0)) 1431 goto fail; 1432 1433 ifp = sc_if->msk_ifp = if_alloc(IFT_ETHER); 1434 if (ifp == NULL) { 1435 device_printf(sc_if->msk_if_dev, "can not if_alloc()\n"); 1436 error = ENOSPC; 1437 goto fail; 1438 } 1439 ifp->if_softc = sc_if; 1440 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1441 ifp->if_mtu = ETHERMTU; 1442 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1443 /* 1444 * IFCAP_RXCSUM capability is intentionally disabled as the hardware 1445 * has serious bug in Rx checksum offload for all Yukon II family 1446 * hardware. It seems there is a workaround to make it work somtimes. 1447 * However, the workaround also have to check OP code sequences to 1448 * verify whether the OP code is correct. Sometimes it should compute 1449 * IP/TCP/UDP checksum in driver in order to verify correctness of 1450 * checksum computed by hardware. If you have to compute checksum 1451 * with software to verify the hardware's checksum why have hardware 1452 * compute the checksum? I think there is no reason to spend time to 1453 * make Rx checksum offload work on Yukon II hardware. 1454 */ 1455 ifp->if_capabilities = IFCAP_TXCSUM | IFCAP_TSO4; 1456 ifp->if_hwassist = MSK_CSUM_FEATURES | CSUM_TSO; 1457 ifp->if_capenable = ifp->if_capabilities; 1458 ifp->if_ioctl = msk_ioctl; 1459 ifp->if_start = msk_start; 1460 ifp->if_timer = 0; 1461 ifp->if_watchdog = NULL; 1462 ifp->if_init = msk_init; 1463 IFQ_SET_MAXLEN(&ifp->if_snd, MSK_TX_RING_CNT - 1); 1464 ifp->if_snd.ifq_drv_maxlen = MSK_TX_RING_CNT - 1; 1465 IFQ_SET_READY(&ifp->if_snd); 1466 1467 TASK_INIT(&sc_if->msk_tx_task, 1, msk_tx_task, ifp); 1468 1469 /* 1470 * Get station address for this interface. Note that 1471 * dual port cards actually come with three station 1472 * addresses: one for each port, plus an extra. The 1473 * extra one is used by the SysKonnect driver software 1474 * as a 'virtual' station address for when both ports 1475 * are operating in failover mode. Currently we don't 1476 * use this extra address. 1477 */ 1478 MSK_IF_LOCK(sc_if); 1479 for (i = 0; i < ETHER_ADDR_LEN; i++) 1480 eaddr[i] = CSR_READ_1(sc, B2_MAC_1 + (port * 8) + i); 1481 1482 /* 1483 * Call MI attach routine. Can't hold locks when calling into ether_*. 1484 */ 1485 MSK_IF_UNLOCK(sc_if); 1486 ether_ifattach(ifp, eaddr); 1487 MSK_IF_LOCK(sc_if); 1488 1489 /* VLAN capability setup */ 1490 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING; 1491 if (ifp->if_capabilities & IFCAP_HWCSUM) 1492 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM; 1493 ifp->if_capenable = ifp->if_capabilities; 1494 1495 /* 1496 * Tell the upper layer(s) we support long frames. 1497 * Must appear after the call to ether_ifattach() because 1498 * ether_ifattach() sets ifi_hdrlen to the default value. 1499 */ 1500 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1501 1502 sc_if->msk_framesize = ifp->if_mtu + ETHER_HDR_LEN + 1503 ETHER_VLAN_ENCAP_LEN; 1504 1505 /* 1506 * Do miibus setup. 1507 */ 1508 MSK_IF_UNLOCK(sc_if); 1509 error = mii_phy_probe(dev, &sc_if->msk_miibus, msk_mediachange, 1510 msk_mediastatus); 1511 if (error != 0) { 1512 device_printf(sc_if->msk_if_dev, "no PHY found!\n"); 1513 ether_ifdetach(ifp); 1514 error = ENXIO; 1515 goto fail; 1516 } 1517 1518 fail: 1519 if (error != 0) { 1520 /* Access should be ok even though lock has been dropped */ 1521 sc->msk_if[port] = NULL; 1522 msk_detach(dev); 1523 } 1524 1525 return (error); 1526 } 1527 1528 /* 1529 * Attach the interface. Allocate softc structures, do ifmedia 1530 * setup and ethernet/BPF attach. 1531 */ 1532 static int 1533 mskc_attach(device_t dev) 1534 { 1535 struct msk_softc *sc; 1536 int error, msic, msir, *port, reg; 1537 1538 sc = device_get_softc(dev); 1539 sc->msk_dev = dev; 1540 mtx_init(&sc->msk_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1541 MTX_DEF); 1542 1543 /* 1544 * Map control/status registers. 1545 */ 1546 pci_enable_busmaster(dev); 1547 1548 /* Allocate I/O resource */ 1549 #ifdef MSK_USEIOSPACE 1550 sc->msk_res_spec = msk_res_spec_io; 1551 #else 1552 sc->msk_res_spec = msk_res_spec_mem; 1553 #endif 1554 sc->msk_irq_spec = msk_irq_spec_legacy; 1555 error = bus_alloc_resources(dev, sc->msk_res_spec, sc->msk_res); 1556 if (error) { 1557 if (sc->msk_res_spec == msk_res_spec_mem) 1558 sc->msk_res_spec = msk_res_spec_io; 1559 else 1560 sc->msk_res_spec = msk_res_spec_mem; 1561 error = bus_alloc_resources(dev, sc->msk_res_spec, sc->msk_res); 1562 if (error) { 1563 device_printf(dev, "couldn't allocate %s resources\n", 1564 sc->msk_res_spec == msk_res_spec_mem ? "memory" : 1565 "I/O"); 1566 mtx_destroy(&sc->msk_mtx); 1567 return (ENXIO); 1568 } 1569 } 1570 1571 CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR); 1572 sc->msk_hw_id = CSR_READ_1(sc, B2_CHIP_ID); 1573 sc->msk_hw_rev = (CSR_READ_1(sc, B2_MAC_CFG) >> 4) & 0x0f; 1574 /* Bail out if chip is not recognized. */ 1575 if (sc->msk_hw_id < CHIP_ID_YUKON_XL || 1576 sc->msk_hw_id > CHIP_ID_YUKON_FE) { 1577 device_printf(dev, "unknown device: id=0x%02x, rev=0x%02x\n", 1578 sc->msk_hw_id, sc->msk_hw_rev); 1579 mtx_destroy(&sc->msk_mtx); 1580 return (ENXIO); 1581 } 1582 1583 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 1584 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 1585 OID_AUTO, "process_limit", CTLTYPE_INT | CTLFLAG_RW, 1586 &sc->msk_process_limit, 0, sysctl_hw_msk_proc_limit, "I", 1587 "max number of Rx events to process"); 1588 1589 sc->msk_process_limit = MSK_PROC_DEFAULT; 1590 error = resource_int_value(device_get_name(dev), device_get_unit(dev), 1591 "process_limit", &sc->msk_process_limit); 1592 if (error == 0) { 1593 if (sc->msk_process_limit < MSK_PROC_MIN || 1594 sc->msk_process_limit > MSK_PROC_MAX) { 1595 device_printf(dev, "process_limit value out of range; " 1596 "using default: %d\n", MSK_PROC_DEFAULT); 1597 sc->msk_process_limit = MSK_PROC_DEFAULT; 1598 } 1599 } 1600 1601 /* Soft reset. */ 1602 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); 1603 CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR); 1604 sc->msk_pmd = CSR_READ_1(sc, B2_PMD_TYP); 1605 if (sc->msk_pmd == 'L' || sc->msk_pmd == 'S') 1606 sc->msk_coppertype = 0; 1607 else 1608 sc->msk_coppertype = 1; 1609 /* Check number of MACs. */ 1610 sc->msk_num_port = 1; 1611 if ((CSR_READ_1(sc, B2_Y2_HW_RES) & CFG_DUAL_MAC_MSK) == 1612 CFG_DUAL_MAC_MSK) { 1613 if (!(CSR_READ_1(sc, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC)) 1614 sc->msk_num_port++; 1615 } 1616 1617 /* Check bus type. */ 1618 if (pci_find_extcap(sc->msk_dev, PCIY_EXPRESS, ®) == 0) 1619 sc->msk_bustype = MSK_PEX_BUS; 1620 else if (pci_find_extcap(sc->msk_dev, PCIY_PCIX, ®) == 0) 1621 sc->msk_bustype = MSK_PCIX_BUS; 1622 else 1623 sc->msk_bustype = MSK_PCI_BUS; 1624 1625 switch (sc->msk_hw_id) { 1626 case CHIP_ID_YUKON_EC: 1627 case CHIP_ID_YUKON_EC_U: 1628 sc->msk_clock = 125; /* 125 Mhz */ 1629 break; 1630 case CHIP_ID_YUKON_FE: 1631 sc->msk_clock = 100; /* 100 Mhz */ 1632 break; 1633 case CHIP_ID_YUKON_XL: 1634 sc->msk_clock = 156; /* 156 Mhz */ 1635 break; 1636 default: 1637 sc->msk_clock = 156; /* 156 Mhz */ 1638 break; 1639 } 1640 1641 /* Allocate IRQ resources. */ 1642 msic = pci_msi_count(dev); 1643 if (bootverbose) 1644 device_printf(dev, "MSI count : %d\n", msic); 1645 /* 1646 * The Yukon II reports it can handle two messages, one for each 1647 * possible port. We go ahead and allocate two messages and only 1648 * setup a handler for both if we have a dual port card. 1649 * 1650 * XXX: I haven't untangled the interrupt handler to handle dual 1651 * port cards with separate MSI messages, so for now I disable MSI 1652 * on dual port cards. 1653 */ 1654 if (legacy_intr != 0) 1655 msi_disable = 1; 1656 if (msi_disable == 0) { 1657 switch (msic) { 1658 case 2: 1659 case 1: /* 88E8058 reports 1 MSI message */ 1660 msir = msic; 1661 if (sc->msk_num_port == 1 && 1662 pci_alloc_msi(dev, &msir) == 0) { 1663 if (msic == msir) { 1664 sc->msk_msi = 1; 1665 sc->msk_irq_spec = msic == 2 ? 1666 msk_irq_spec_msi2 : 1667 msk_irq_spec_msi; 1668 } else 1669 pci_release_msi(dev); 1670 } 1671 break; 1672 default: 1673 device_printf(dev, 1674 "Unexpected number of MSI messages : %d\n", msic); 1675 break; 1676 } 1677 } 1678 1679 error = bus_alloc_resources(dev, sc->msk_irq_spec, sc->msk_irq); 1680 if (error) { 1681 device_printf(dev, "couldn't allocate IRQ resources\n"); 1682 goto fail; 1683 } 1684 1685 if ((error = msk_status_dma_alloc(sc)) != 0) 1686 goto fail; 1687 1688 /* Set base interrupt mask. */ 1689 sc->msk_intrmask = Y2_IS_HW_ERR | Y2_IS_STAT_BMU; 1690 sc->msk_intrhwemask = Y2_IS_TIST_OV | Y2_IS_MST_ERR | 1691 Y2_IS_IRQ_STAT | Y2_IS_PCI_EXP | Y2_IS_PCI_NEXP; 1692 1693 /* Reset the adapter. */ 1694 mskc_reset(sc); 1695 1696 if ((error = mskc_setup_rambuffer(sc)) != 0) 1697 goto fail; 1698 1699 sc->msk_devs[MSK_PORT_A] = device_add_child(dev, "msk", -1); 1700 if (sc->msk_devs[MSK_PORT_A] == NULL) { 1701 device_printf(dev, "failed to add child for PORT_A\n"); 1702 error = ENXIO; 1703 goto fail; 1704 } 1705 port = malloc(sizeof(int), M_DEVBUF, M_WAITOK); 1706 if (port == NULL) { 1707 device_printf(dev, "failed to allocate memory for " 1708 "ivars of PORT_A\n"); 1709 error = ENXIO; 1710 goto fail; 1711 } 1712 *port = MSK_PORT_A; 1713 device_set_ivars(sc->msk_devs[MSK_PORT_A], port); 1714 1715 if (sc->msk_num_port > 1) { 1716 sc->msk_devs[MSK_PORT_B] = device_add_child(dev, "msk", -1); 1717 if (sc->msk_devs[MSK_PORT_B] == NULL) { 1718 device_printf(dev, "failed to add child for PORT_B\n"); 1719 error = ENXIO; 1720 goto fail; 1721 } 1722 port = malloc(sizeof(int), M_DEVBUF, M_WAITOK); 1723 if (port == NULL) { 1724 device_printf(dev, "failed to allocate memory for " 1725 "ivars of PORT_B\n"); 1726 error = ENXIO; 1727 goto fail; 1728 } 1729 *port = MSK_PORT_B; 1730 device_set_ivars(sc->msk_devs[MSK_PORT_B], port); 1731 } 1732 1733 error = bus_generic_attach(dev); 1734 if (error) { 1735 device_printf(dev, "failed to attach port(s)\n"); 1736 goto fail; 1737 } 1738 1739 /* Hook interrupt last to avoid having to lock softc. */ 1740 if (legacy_intr) 1741 error = bus_setup_intr(dev, sc->msk_irq[0], INTR_TYPE_NET | 1742 INTR_MPSAFE, NULL, msk_legacy_intr, sc, 1743 &sc->msk_intrhand[0]); 1744 else { 1745 TASK_INIT(&sc->msk_int_task, 0, msk_int_task, sc); 1746 sc->msk_tq = taskqueue_create_fast("msk_taskq", M_WAITOK, 1747 taskqueue_thread_enqueue, &sc->msk_tq); 1748 taskqueue_start_threads(&sc->msk_tq, 1, PI_NET, "%s taskq", 1749 device_get_nameunit(sc->msk_dev)); 1750 error = bus_setup_intr(dev, sc->msk_irq[0], INTR_TYPE_NET | 1751 INTR_MPSAFE, msk_intr, NULL, sc, &sc->msk_intrhand[0]); 1752 } 1753 1754 if (error != 0) { 1755 device_printf(dev, "couldn't set up interrupt handler\n"); 1756 if (legacy_intr == 0) 1757 taskqueue_free(sc->msk_tq); 1758 sc->msk_tq = NULL; 1759 goto fail; 1760 } 1761 fail: 1762 if (error != 0) 1763 mskc_detach(dev); 1764 1765 return (error); 1766 } 1767 1768 /* 1769 * Shutdown hardware and free up resources. This can be called any 1770 * time after the mutex has been initialized. It is called in both 1771 * the error case in attach and the normal detach case so it needs 1772 * to be careful about only freeing resources that have actually been 1773 * allocated. 1774 */ 1775 static int 1776 msk_detach(device_t dev) 1777 { 1778 struct msk_softc *sc; 1779 struct msk_if_softc *sc_if; 1780 struct ifnet *ifp; 1781 1782 sc_if = device_get_softc(dev); 1783 KASSERT(mtx_initialized(&sc_if->msk_softc->msk_mtx), 1784 ("msk mutex not initialized in msk_detach")); 1785 MSK_IF_LOCK(sc_if); 1786 1787 ifp = sc_if->msk_ifp; 1788 if (device_is_attached(dev)) { 1789 /* XXX */ 1790 sc_if->msk_detach = 1; 1791 msk_stop(sc_if); 1792 /* Can't hold locks while calling detach. */ 1793 MSK_IF_UNLOCK(sc_if); 1794 callout_drain(&sc_if->msk_tick_ch); 1795 taskqueue_drain(taskqueue_fast, &sc_if->msk_tx_task); 1796 taskqueue_drain(taskqueue_swi, &sc_if->msk_link_task); 1797 ether_ifdetach(ifp); 1798 MSK_IF_LOCK(sc_if); 1799 } 1800 1801 /* 1802 * We're generally called from mskc_detach() which is using 1803 * device_delete_child() to get to here. It's already trashed 1804 * miibus for us, so don't do it here or we'll panic. 1805 * 1806 * if (sc_if->msk_miibus != NULL) { 1807 * device_delete_child(dev, sc_if->msk_miibus); 1808 * sc_if->msk_miibus = NULL; 1809 * } 1810 */ 1811 1812 msk_txrx_dma_free(sc_if); 1813 bus_generic_detach(dev); 1814 1815 if (ifp) 1816 if_free(ifp); 1817 sc = sc_if->msk_softc; 1818 sc->msk_if[sc_if->msk_port] = NULL; 1819 MSK_IF_UNLOCK(sc_if); 1820 1821 return (0); 1822 } 1823 1824 static int 1825 mskc_detach(device_t dev) 1826 { 1827 struct msk_softc *sc; 1828 1829 sc = device_get_softc(dev); 1830 KASSERT(mtx_initialized(&sc->msk_mtx), ("msk mutex not initialized")); 1831 1832 if (device_is_alive(dev)) { 1833 if (sc->msk_devs[MSK_PORT_A] != NULL) { 1834 free(device_get_ivars(sc->msk_devs[MSK_PORT_A]), 1835 M_DEVBUF); 1836 device_delete_child(dev, sc->msk_devs[MSK_PORT_A]); 1837 } 1838 if (sc->msk_devs[MSK_PORT_B] != NULL) { 1839 free(device_get_ivars(sc->msk_devs[MSK_PORT_B]), 1840 M_DEVBUF); 1841 device_delete_child(dev, sc->msk_devs[MSK_PORT_B]); 1842 } 1843 bus_generic_detach(dev); 1844 } 1845 1846 /* Disable all interrupts. */ 1847 CSR_WRITE_4(sc, B0_IMSK, 0); 1848 CSR_READ_4(sc, B0_IMSK); 1849 CSR_WRITE_4(sc, B0_HWE_IMSK, 0); 1850 CSR_READ_4(sc, B0_HWE_IMSK); 1851 1852 /* LED Off. */ 1853 CSR_WRITE_2(sc, B0_CTST, Y2_LED_STAT_OFF); 1854 1855 /* Put hardware reset. */ 1856 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); 1857 1858 msk_status_dma_free(sc); 1859 1860 if (legacy_intr == 0 && sc->msk_tq != NULL) { 1861 taskqueue_drain(sc->msk_tq, &sc->msk_int_task); 1862 taskqueue_free(sc->msk_tq); 1863 sc->msk_tq = NULL; 1864 } 1865 if (sc->msk_intrhand[0]) { 1866 bus_teardown_intr(dev, sc->msk_irq[0], sc->msk_intrhand[0]); 1867 sc->msk_intrhand[0] = NULL; 1868 } 1869 if (sc->msk_intrhand[1]) { 1870 bus_teardown_intr(dev, sc->msk_irq[0], sc->msk_intrhand[0]); 1871 sc->msk_intrhand[1] = NULL; 1872 } 1873 bus_release_resources(dev, sc->msk_irq_spec, sc->msk_irq); 1874 if (sc->msk_msi) 1875 pci_release_msi(dev); 1876 bus_release_resources(dev, sc->msk_res_spec, sc->msk_res); 1877 mtx_destroy(&sc->msk_mtx); 1878 1879 return (0); 1880 } 1881 1882 struct msk_dmamap_arg { 1883 bus_addr_t msk_busaddr; 1884 }; 1885 1886 static void 1887 msk_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1888 { 1889 struct msk_dmamap_arg *ctx; 1890 1891 if (error != 0) 1892 return; 1893 ctx = arg; 1894 ctx->msk_busaddr = segs[0].ds_addr; 1895 } 1896 1897 /* Create status DMA region. */ 1898 static int 1899 msk_status_dma_alloc(struct msk_softc *sc) 1900 { 1901 struct msk_dmamap_arg ctx; 1902 int error; 1903 1904 error = bus_dma_tag_create( 1905 bus_get_dma_tag(sc->msk_dev), /* parent */ 1906 MSK_STAT_ALIGN, 0, /* alignment, boundary */ 1907 BUS_SPACE_MAXADDR, /* lowaddr */ 1908 BUS_SPACE_MAXADDR, /* highaddr */ 1909 NULL, NULL, /* filter, filterarg */ 1910 MSK_STAT_RING_SZ, /* maxsize */ 1911 1, /* nsegments */ 1912 MSK_STAT_RING_SZ, /* maxsegsize */ 1913 0, /* flags */ 1914 NULL, NULL, /* lockfunc, lockarg */ 1915 &sc->msk_stat_tag); 1916 if (error != 0) { 1917 device_printf(sc->msk_dev, 1918 "failed to create status DMA tag\n"); 1919 return (error); 1920 } 1921 1922 /* Allocate DMA'able memory and load the DMA map for status ring. */ 1923 error = bus_dmamem_alloc(sc->msk_stat_tag, 1924 (void **)&sc->msk_stat_ring, BUS_DMA_WAITOK | BUS_DMA_COHERENT | 1925 BUS_DMA_ZERO, &sc->msk_stat_map); 1926 if (error != 0) { 1927 device_printf(sc->msk_dev, 1928 "failed to allocate DMA'able memory for status ring\n"); 1929 return (error); 1930 } 1931 1932 ctx.msk_busaddr = 0; 1933 error = bus_dmamap_load(sc->msk_stat_tag, 1934 sc->msk_stat_map, sc->msk_stat_ring, MSK_STAT_RING_SZ, 1935 msk_dmamap_cb, &ctx, 0); 1936 if (error != 0) { 1937 device_printf(sc->msk_dev, 1938 "failed to load DMA'able memory for status ring\n"); 1939 return (error); 1940 } 1941 sc->msk_stat_ring_paddr = ctx.msk_busaddr; 1942 1943 return (0); 1944 } 1945 1946 static void 1947 msk_status_dma_free(struct msk_softc *sc) 1948 { 1949 1950 /* Destroy status block. */ 1951 if (sc->msk_stat_tag) { 1952 if (sc->msk_stat_map) { 1953 bus_dmamap_unload(sc->msk_stat_tag, sc->msk_stat_map); 1954 if (sc->msk_stat_ring) { 1955 bus_dmamem_free(sc->msk_stat_tag, 1956 sc->msk_stat_ring, sc->msk_stat_map); 1957 sc->msk_stat_ring = NULL; 1958 } 1959 sc->msk_stat_map = NULL; 1960 } 1961 bus_dma_tag_destroy(sc->msk_stat_tag); 1962 sc->msk_stat_tag = NULL; 1963 } 1964 } 1965 1966 static int 1967 msk_txrx_dma_alloc(struct msk_if_softc *sc_if) 1968 { 1969 struct msk_dmamap_arg ctx; 1970 struct msk_txdesc *txd; 1971 struct msk_rxdesc *rxd; 1972 struct msk_rxdesc *jrxd; 1973 struct msk_jpool_entry *entry; 1974 uint8_t *ptr; 1975 int error, i; 1976 1977 mtx_init(&sc_if->msk_jlist_mtx, "msk_jlist_mtx", NULL, MTX_DEF); 1978 SLIST_INIT(&sc_if->msk_jfree_listhead); 1979 SLIST_INIT(&sc_if->msk_jinuse_listhead); 1980 1981 /* Create parent DMA tag. */ 1982 /* 1983 * XXX 1984 * It seems that Yukon II supports full 64bits DMA operations. But 1985 * it needs two descriptors(list elements) for 64bits DMA operations. 1986 * Since we don't know what DMA address mappings(32bits or 64bits) 1987 * would be used in advance for each mbufs, we limits its DMA space 1988 * to be in range of 32bits address space. Otherwise, we should check 1989 * what DMA address is used and chain another descriptor for the 1990 * 64bits DMA operation. This also means descriptor ring size is 1991 * variable. Limiting DMA address to be in 32bit address space greatly 1992 * simplyfies descriptor handling and possibly would increase 1993 * performance a bit due to efficient handling of descriptors. 1994 * Apart from harassing checksum offloading mechanisms, it seems 1995 * it's really bad idea to use a seperate descriptor for 64bit 1996 * DMA operation to save small descriptor memory. Anyway, I've 1997 * never seen these exotic scheme on ethernet interface hardware. 1998 */ 1999 error = bus_dma_tag_create( 2000 bus_get_dma_tag(sc_if->msk_if_dev), /* parent */ 2001 1, 0, /* alignment, boundary */ 2002 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 2003 BUS_SPACE_MAXADDR, /* highaddr */ 2004 NULL, NULL, /* filter, filterarg */ 2005 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 2006 0, /* nsegments */ 2007 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 2008 0, /* flags */ 2009 NULL, NULL, /* lockfunc, lockarg */ 2010 &sc_if->msk_cdata.msk_parent_tag); 2011 if (error != 0) { 2012 device_printf(sc_if->msk_if_dev, 2013 "failed to create parent DMA tag\n"); 2014 goto fail; 2015 } 2016 /* Create tag for Tx ring. */ 2017 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2018 MSK_RING_ALIGN, 0, /* alignment, boundary */ 2019 BUS_SPACE_MAXADDR, /* lowaddr */ 2020 BUS_SPACE_MAXADDR, /* highaddr */ 2021 NULL, NULL, /* filter, filterarg */ 2022 MSK_TX_RING_SZ, /* maxsize */ 2023 1, /* nsegments */ 2024 MSK_TX_RING_SZ, /* maxsegsize */ 2025 0, /* flags */ 2026 NULL, NULL, /* lockfunc, lockarg */ 2027 &sc_if->msk_cdata.msk_tx_ring_tag); 2028 if (error != 0) { 2029 device_printf(sc_if->msk_if_dev, 2030 "failed to create Tx ring DMA tag\n"); 2031 goto fail; 2032 } 2033 2034 /* Create tag for Rx ring. */ 2035 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2036 MSK_RING_ALIGN, 0, /* alignment, boundary */ 2037 BUS_SPACE_MAXADDR, /* lowaddr */ 2038 BUS_SPACE_MAXADDR, /* highaddr */ 2039 NULL, NULL, /* filter, filterarg */ 2040 MSK_RX_RING_SZ, /* maxsize */ 2041 1, /* nsegments */ 2042 MSK_RX_RING_SZ, /* maxsegsize */ 2043 0, /* flags */ 2044 NULL, NULL, /* lockfunc, lockarg */ 2045 &sc_if->msk_cdata.msk_rx_ring_tag); 2046 if (error != 0) { 2047 device_printf(sc_if->msk_if_dev, 2048 "failed to create Rx ring DMA tag\n"); 2049 goto fail; 2050 } 2051 2052 /* Create tag for jumbo Rx ring. */ 2053 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2054 MSK_RING_ALIGN, 0, /* alignment, boundary */ 2055 BUS_SPACE_MAXADDR, /* lowaddr */ 2056 BUS_SPACE_MAXADDR, /* highaddr */ 2057 NULL, NULL, /* filter, filterarg */ 2058 MSK_JUMBO_RX_RING_SZ, /* maxsize */ 2059 1, /* nsegments */ 2060 MSK_JUMBO_RX_RING_SZ, /* maxsegsize */ 2061 0, /* flags */ 2062 NULL, NULL, /* lockfunc, lockarg */ 2063 &sc_if->msk_cdata.msk_jumbo_rx_ring_tag); 2064 if (error != 0) { 2065 device_printf(sc_if->msk_if_dev, 2066 "failed to create jumbo Rx ring DMA tag\n"); 2067 goto fail; 2068 } 2069 2070 /* Create tag for jumbo buffer blocks. */ 2071 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2072 PAGE_SIZE, 0, /* alignment, boundary */ 2073 BUS_SPACE_MAXADDR, /* lowaddr */ 2074 BUS_SPACE_MAXADDR, /* highaddr */ 2075 NULL, NULL, /* filter, filterarg */ 2076 MSK_JMEM, /* maxsize */ 2077 1, /* nsegments */ 2078 MSK_JMEM, /* maxsegsize */ 2079 0, /* flags */ 2080 NULL, NULL, /* lockfunc, lockarg */ 2081 &sc_if->msk_cdata.msk_jumbo_tag); 2082 if (error != 0) { 2083 device_printf(sc_if->msk_if_dev, 2084 "failed to create jumbo Rx buffer block DMA tag\n"); 2085 goto fail; 2086 } 2087 2088 /* Create tag for Tx buffers. */ 2089 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2090 1, 0, /* alignment, boundary */ 2091 BUS_SPACE_MAXADDR, /* lowaddr */ 2092 BUS_SPACE_MAXADDR, /* highaddr */ 2093 NULL, NULL, /* filter, filterarg */ 2094 MSK_TSO_MAXSIZE, /* maxsize */ 2095 MSK_MAXTXSEGS, /* nsegments */ 2096 MSK_TSO_MAXSGSIZE, /* maxsegsize */ 2097 0, /* flags */ 2098 NULL, NULL, /* lockfunc, lockarg */ 2099 &sc_if->msk_cdata.msk_tx_tag); 2100 if (error != 0) { 2101 device_printf(sc_if->msk_if_dev, 2102 "failed to create Tx DMA tag\n"); 2103 goto fail; 2104 } 2105 2106 /* Create tag for Rx buffers. */ 2107 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2108 1, 0, /* alignment, boundary */ 2109 BUS_SPACE_MAXADDR, /* lowaddr */ 2110 BUS_SPACE_MAXADDR, /* highaddr */ 2111 NULL, NULL, /* filter, filterarg */ 2112 MCLBYTES, /* maxsize */ 2113 1, /* nsegments */ 2114 MCLBYTES, /* maxsegsize */ 2115 0, /* flags */ 2116 NULL, NULL, /* lockfunc, lockarg */ 2117 &sc_if->msk_cdata.msk_rx_tag); 2118 if (error != 0) { 2119 device_printf(sc_if->msk_if_dev, 2120 "failed to create Rx DMA tag\n"); 2121 goto fail; 2122 } 2123 2124 /* Create tag for jumbo Rx buffers. */ 2125 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2126 PAGE_SIZE, 0, /* alignment, boundary */ 2127 BUS_SPACE_MAXADDR, /* lowaddr */ 2128 BUS_SPACE_MAXADDR, /* highaddr */ 2129 NULL, NULL, /* filter, filterarg */ 2130 MCLBYTES * MSK_MAXRXSEGS, /* maxsize */ 2131 MSK_MAXRXSEGS, /* nsegments */ 2132 MSK_JLEN, /* maxsegsize */ 2133 0, /* flags */ 2134 NULL, NULL, /* lockfunc, lockarg */ 2135 &sc_if->msk_cdata.msk_jumbo_rx_tag); 2136 if (error != 0) { 2137 device_printf(sc_if->msk_if_dev, 2138 "failed to create jumbo Rx DMA tag\n"); 2139 goto fail; 2140 } 2141 2142 /* Allocate DMA'able memory and load the DMA map for Tx ring. */ 2143 error = bus_dmamem_alloc(sc_if->msk_cdata.msk_tx_ring_tag, 2144 (void **)&sc_if->msk_rdata.msk_tx_ring, BUS_DMA_WAITOK | 2145 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc_if->msk_cdata.msk_tx_ring_map); 2146 if (error != 0) { 2147 device_printf(sc_if->msk_if_dev, 2148 "failed to allocate DMA'able memory for Tx ring\n"); 2149 goto fail; 2150 } 2151 2152 ctx.msk_busaddr = 0; 2153 error = bus_dmamap_load(sc_if->msk_cdata.msk_tx_ring_tag, 2154 sc_if->msk_cdata.msk_tx_ring_map, sc_if->msk_rdata.msk_tx_ring, 2155 MSK_TX_RING_SZ, msk_dmamap_cb, &ctx, 0); 2156 if (error != 0) { 2157 device_printf(sc_if->msk_if_dev, 2158 "failed to load DMA'able memory for Tx ring\n"); 2159 goto fail; 2160 } 2161 sc_if->msk_rdata.msk_tx_ring_paddr = ctx.msk_busaddr; 2162 2163 /* Allocate DMA'able memory and load the DMA map for Rx ring. */ 2164 error = bus_dmamem_alloc(sc_if->msk_cdata.msk_rx_ring_tag, 2165 (void **)&sc_if->msk_rdata.msk_rx_ring, BUS_DMA_WAITOK | 2166 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc_if->msk_cdata.msk_rx_ring_map); 2167 if (error != 0) { 2168 device_printf(sc_if->msk_if_dev, 2169 "failed to allocate DMA'able memory for Rx ring\n"); 2170 goto fail; 2171 } 2172 2173 ctx.msk_busaddr = 0; 2174 error = bus_dmamap_load(sc_if->msk_cdata.msk_rx_ring_tag, 2175 sc_if->msk_cdata.msk_rx_ring_map, sc_if->msk_rdata.msk_rx_ring, 2176 MSK_RX_RING_SZ, msk_dmamap_cb, &ctx, 0); 2177 if (error != 0) { 2178 device_printf(sc_if->msk_if_dev, 2179 "failed to load DMA'able memory for Rx ring\n"); 2180 goto fail; 2181 } 2182 sc_if->msk_rdata.msk_rx_ring_paddr = ctx.msk_busaddr; 2183 2184 /* Allocate DMA'able memory and load the DMA map for jumbo Rx ring. */ 2185 error = bus_dmamem_alloc(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 2186 (void **)&sc_if->msk_rdata.msk_jumbo_rx_ring, 2187 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 2188 &sc_if->msk_cdata.msk_jumbo_rx_ring_map); 2189 if (error != 0) { 2190 device_printf(sc_if->msk_if_dev, 2191 "failed to allocate DMA'able memory for jumbo Rx ring\n"); 2192 goto fail; 2193 } 2194 2195 ctx.msk_busaddr = 0; 2196 error = bus_dmamap_load(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 2197 sc_if->msk_cdata.msk_jumbo_rx_ring_map, 2198 sc_if->msk_rdata.msk_jumbo_rx_ring, MSK_JUMBO_RX_RING_SZ, 2199 msk_dmamap_cb, &ctx, 0); 2200 if (error != 0) { 2201 device_printf(sc_if->msk_if_dev, 2202 "failed to load DMA'able memory for jumbo Rx ring\n"); 2203 goto fail; 2204 } 2205 sc_if->msk_rdata.msk_jumbo_rx_ring_paddr = ctx.msk_busaddr; 2206 2207 /* Create DMA maps for Tx buffers. */ 2208 for (i = 0; i < MSK_TX_RING_CNT; i++) { 2209 txd = &sc_if->msk_cdata.msk_txdesc[i]; 2210 txd->tx_m = NULL; 2211 txd->tx_dmamap = NULL; 2212 error = bus_dmamap_create(sc_if->msk_cdata.msk_tx_tag, 0, 2213 &txd->tx_dmamap); 2214 if (error != 0) { 2215 device_printf(sc_if->msk_if_dev, 2216 "failed to create Tx dmamap\n"); 2217 goto fail; 2218 } 2219 } 2220 /* Create DMA maps for Rx buffers. */ 2221 if ((error = bus_dmamap_create(sc_if->msk_cdata.msk_rx_tag, 0, 2222 &sc_if->msk_cdata.msk_rx_sparemap)) != 0) { 2223 device_printf(sc_if->msk_if_dev, 2224 "failed to create spare Rx dmamap\n"); 2225 goto fail; 2226 } 2227 for (i = 0; i < MSK_RX_RING_CNT; i++) { 2228 rxd = &sc_if->msk_cdata.msk_rxdesc[i]; 2229 rxd->rx_m = NULL; 2230 rxd->rx_dmamap = NULL; 2231 error = bus_dmamap_create(sc_if->msk_cdata.msk_rx_tag, 0, 2232 &rxd->rx_dmamap); 2233 if (error != 0) { 2234 device_printf(sc_if->msk_if_dev, 2235 "failed to create Rx dmamap\n"); 2236 goto fail; 2237 } 2238 } 2239 /* Create DMA maps for jumbo Rx buffers. */ 2240 if ((error = bus_dmamap_create(sc_if->msk_cdata.msk_jumbo_rx_tag, 0, 2241 &sc_if->msk_cdata.msk_jumbo_rx_sparemap)) != 0) { 2242 device_printf(sc_if->msk_if_dev, 2243 "failed to create spare jumbo Rx dmamap\n"); 2244 goto fail; 2245 } 2246 for (i = 0; i < MSK_JUMBO_RX_RING_CNT; i++) { 2247 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[i]; 2248 jrxd->rx_m = NULL; 2249 jrxd->rx_dmamap = NULL; 2250 error = bus_dmamap_create(sc_if->msk_cdata.msk_jumbo_rx_tag, 0, 2251 &jrxd->rx_dmamap); 2252 if (error != 0) { 2253 device_printf(sc_if->msk_if_dev, 2254 "failed to create jumbo Rx dmamap\n"); 2255 goto fail; 2256 } 2257 } 2258 2259 /* Allocate DMA'able memory and load the DMA map for jumbo buf. */ 2260 error = bus_dmamem_alloc(sc_if->msk_cdata.msk_jumbo_tag, 2261 (void **)&sc_if->msk_rdata.msk_jumbo_buf, 2262 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 2263 &sc_if->msk_cdata.msk_jumbo_map); 2264 if (error != 0) { 2265 device_printf(sc_if->msk_if_dev, 2266 "failed to allocate DMA'able memory for jumbo buf\n"); 2267 goto fail; 2268 } 2269 2270 ctx.msk_busaddr = 0; 2271 error = bus_dmamap_load(sc_if->msk_cdata.msk_jumbo_tag, 2272 sc_if->msk_cdata.msk_jumbo_map, sc_if->msk_rdata.msk_jumbo_buf, 2273 MSK_JMEM, msk_dmamap_cb, &ctx, 0); 2274 if (error != 0) { 2275 device_printf(sc_if->msk_if_dev, 2276 "failed to load DMA'able memory for jumbobuf\n"); 2277 goto fail; 2278 } 2279 sc_if->msk_rdata.msk_jumbo_buf_paddr = ctx.msk_busaddr; 2280 2281 /* 2282 * Now divide it up into 9K pieces and save the addresses 2283 * in an array. 2284 */ 2285 ptr = sc_if->msk_rdata.msk_jumbo_buf; 2286 for (i = 0; i < MSK_JSLOTS; i++) { 2287 sc_if->msk_cdata.msk_jslots[i] = ptr; 2288 ptr += MSK_JLEN; 2289 entry = malloc(sizeof(struct msk_jpool_entry), 2290 M_DEVBUF, M_WAITOK); 2291 if (entry == NULL) { 2292 device_printf(sc_if->msk_if_dev, 2293 "no memory for jumbo buffers!\n"); 2294 error = ENOMEM; 2295 goto fail; 2296 } 2297 entry->slot = i; 2298 SLIST_INSERT_HEAD(&sc_if->msk_jfree_listhead, entry, 2299 jpool_entries); 2300 } 2301 2302 fail: 2303 return (error); 2304 } 2305 2306 static void 2307 msk_txrx_dma_free(struct msk_if_softc *sc_if) 2308 { 2309 struct msk_txdesc *txd; 2310 struct msk_rxdesc *rxd; 2311 struct msk_rxdesc *jrxd; 2312 struct msk_jpool_entry *entry; 2313 int i; 2314 2315 MSK_JLIST_LOCK(sc_if); 2316 while ((entry = SLIST_FIRST(&sc_if->msk_jinuse_listhead))) { 2317 device_printf(sc_if->msk_if_dev, 2318 "asked to free buffer that is in use!\n"); 2319 SLIST_REMOVE_HEAD(&sc_if->msk_jinuse_listhead, jpool_entries); 2320 SLIST_INSERT_HEAD(&sc_if->msk_jfree_listhead, entry, 2321 jpool_entries); 2322 } 2323 2324 while (!SLIST_EMPTY(&sc_if->msk_jfree_listhead)) { 2325 entry = SLIST_FIRST(&sc_if->msk_jfree_listhead); 2326 SLIST_REMOVE_HEAD(&sc_if->msk_jfree_listhead, jpool_entries); 2327 free(entry, M_DEVBUF); 2328 } 2329 MSK_JLIST_UNLOCK(sc_if); 2330 2331 /* Destroy jumbo buffer block. */ 2332 if (sc_if->msk_cdata.msk_jumbo_map) 2333 bus_dmamap_unload(sc_if->msk_cdata.msk_jumbo_tag, 2334 sc_if->msk_cdata.msk_jumbo_map); 2335 2336 if (sc_if->msk_rdata.msk_jumbo_buf) { 2337 bus_dmamem_free(sc_if->msk_cdata.msk_jumbo_tag, 2338 sc_if->msk_rdata.msk_jumbo_buf, 2339 sc_if->msk_cdata.msk_jumbo_map); 2340 sc_if->msk_rdata.msk_jumbo_buf = NULL; 2341 sc_if->msk_cdata.msk_jumbo_map = NULL; 2342 } 2343 2344 /* Tx ring. */ 2345 if (sc_if->msk_cdata.msk_tx_ring_tag) { 2346 if (sc_if->msk_cdata.msk_tx_ring_map) 2347 bus_dmamap_unload(sc_if->msk_cdata.msk_tx_ring_tag, 2348 sc_if->msk_cdata.msk_tx_ring_map); 2349 if (sc_if->msk_cdata.msk_tx_ring_map && 2350 sc_if->msk_rdata.msk_tx_ring) 2351 bus_dmamem_free(sc_if->msk_cdata.msk_tx_ring_tag, 2352 sc_if->msk_rdata.msk_tx_ring, 2353 sc_if->msk_cdata.msk_tx_ring_map); 2354 sc_if->msk_rdata.msk_tx_ring = NULL; 2355 sc_if->msk_cdata.msk_tx_ring_map = NULL; 2356 bus_dma_tag_destroy(sc_if->msk_cdata.msk_tx_ring_tag); 2357 sc_if->msk_cdata.msk_tx_ring_tag = NULL; 2358 } 2359 /* Rx ring. */ 2360 if (sc_if->msk_cdata.msk_rx_ring_tag) { 2361 if (sc_if->msk_cdata.msk_rx_ring_map) 2362 bus_dmamap_unload(sc_if->msk_cdata.msk_rx_ring_tag, 2363 sc_if->msk_cdata.msk_rx_ring_map); 2364 if (sc_if->msk_cdata.msk_rx_ring_map && 2365 sc_if->msk_rdata.msk_rx_ring) 2366 bus_dmamem_free(sc_if->msk_cdata.msk_rx_ring_tag, 2367 sc_if->msk_rdata.msk_rx_ring, 2368 sc_if->msk_cdata.msk_rx_ring_map); 2369 sc_if->msk_rdata.msk_rx_ring = NULL; 2370 sc_if->msk_cdata.msk_rx_ring_map = NULL; 2371 bus_dma_tag_destroy(sc_if->msk_cdata.msk_rx_ring_tag); 2372 sc_if->msk_cdata.msk_rx_ring_tag = NULL; 2373 } 2374 /* Jumbo Rx ring. */ 2375 if (sc_if->msk_cdata.msk_jumbo_rx_ring_tag) { 2376 if (sc_if->msk_cdata.msk_jumbo_rx_ring_map) 2377 bus_dmamap_unload(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 2378 sc_if->msk_cdata.msk_jumbo_rx_ring_map); 2379 if (sc_if->msk_cdata.msk_jumbo_rx_ring_map && 2380 sc_if->msk_rdata.msk_jumbo_rx_ring) 2381 bus_dmamem_free(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 2382 sc_if->msk_rdata.msk_jumbo_rx_ring, 2383 sc_if->msk_cdata.msk_jumbo_rx_ring_map); 2384 sc_if->msk_rdata.msk_jumbo_rx_ring = NULL; 2385 sc_if->msk_cdata.msk_jumbo_rx_ring_map = NULL; 2386 bus_dma_tag_destroy(sc_if->msk_cdata.msk_jumbo_rx_ring_tag); 2387 sc_if->msk_cdata.msk_jumbo_rx_ring_tag = NULL; 2388 } 2389 /* Tx buffers. */ 2390 if (sc_if->msk_cdata.msk_tx_tag) { 2391 for (i = 0; i < MSK_TX_RING_CNT; i++) { 2392 txd = &sc_if->msk_cdata.msk_txdesc[i]; 2393 if (txd->tx_dmamap) { 2394 bus_dmamap_destroy(sc_if->msk_cdata.msk_tx_tag, 2395 txd->tx_dmamap); 2396 txd->tx_dmamap = NULL; 2397 } 2398 } 2399 bus_dma_tag_destroy(sc_if->msk_cdata.msk_tx_tag); 2400 sc_if->msk_cdata.msk_tx_tag = NULL; 2401 } 2402 /* Rx buffers. */ 2403 if (sc_if->msk_cdata.msk_rx_tag) { 2404 for (i = 0; i < MSK_RX_RING_CNT; i++) { 2405 rxd = &sc_if->msk_cdata.msk_rxdesc[i]; 2406 if (rxd->rx_dmamap) { 2407 bus_dmamap_destroy(sc_if->msk_cdata.msk_rx_tag, 2408 rxd->rx_dmamap); 2409 rxd->rx_dmamap = NULL; 2410 } 2411 } 2412 if (sc_if->msk_cdata.msk_rx_sparemap) { 2413 bus_dmamap_destroy(sc_if->msk_cdata.msk_rx_tag, 2414 sc_if->msk_cdata.msk_rx_sparemap); 2415 sc_if->msk_cdata.msk_rx_sparemap = 0; 2416 } 2417 bus_dma_tag_destroy(sc_if->msk_cdata.msk_rx_tag); 2418 sc_if->msk_cdata.msk_rx_tag = NULL; 2419 } 2420 /* Jumbo Rx buffers. */ 2421 if (sc_if->msk_cdata.msk_jumbo_rx_tag) { 2422 for (i = 0; i < MSK_JUMBO_RX_RING_CNT; i++) { 2423 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[i]; 2424 if (jrxd->rx_dmamap) { 2425 bus_dmamap_destroy( 2426 sc_if->msk_cdata.msk_jumbo_rx_tag, 2427 jrxd->rx_dmamap); 2428 jrxd->rx_dmamap = NULL; 2429 } 2430 } 2431 if (sc_if->msk_cdata.msk_jumbo_rx_sparemap) { 2432 bus_dmamap_destroy(sc_if->msk_cdata.msk_jumbo_rx_tag, 2433 sc_if->msk_cdata.msk_jumbo_rx_sparemap); 2434 sc_if->msk_cdata.msk_jumbo_rx_sparemap = 0; 2435 } 2436 bus_dma_tag_destroy(sc_if->msk_cdata.msk_jumbo_rx_tag); 2437 sc_if->msk_cdata.msk_jumbo_rx_tag = NULL; 2438 } 2439 2440 if (sc_if->msk_cdata.msk_parent_tag) { 2441 bus_dma_tag_destroy(sc_if->msk_cdata.msk_parent_tag); 2442 sc_if->msk_cdata.msk_parent_tag = NULL; 2443 } 2444 mtx_destroy(&sc_if->msk_jlist_mtx); 2445 } 2446 2447 /* 2448 * Allocate a jumbo buffer. 2449 */ 2450 static void * 2451 msk_jalloc(struct msk_if_softc *sc_if) 2452 { 2453 struct msk_jpool_entry *entry; 2454 2455 MSK_JLIST_LOCK(sc_if); 2456 2457 entry = SLIST_FIRST(&sc_if->msk_jfree_listhead); 2458 2459 if (entry == NULL) { 2460 MSK_JLIST_UNLOCK(sc_if); 2461 return (NULL); 2462 } 2463 2464 SLIST_REMOVE_HEAD(&sc_if->msk_jfree_listhead, jpool_entries); 2465 SLIST_INSERT_HEAD(&sc_if->msk_jinuse_listhead, entry, jpool_entries); 2466 2467 MSK_JLIST_UNLOCK(sc_if); 2468 2469 return (sc_if->msk_cdata.msk_jslots[entry->slot]); 2470 } 2471 2472 /* 2473 * Release a jumbo buffer. 2474 */ 2475 static void 2476 msk_jfree(void *buf, void *args) 2477 { 2478 struct msk_if_softc *sc_if; 2479 struct msk_jpool_entry *entry; 2480 int i; 2481 2482 /* Extract the softc struct pointer. */ 2483 sc_if = (struct msk_if_softc *)args; 2484 KASSERT(sc_if != NULL, ("%s: can't find softc pointer!", __func__)); 2485 2486 MSK_JLIST_LOCK(sc_if); 2487 /* Calculate the slot this buffer belongs to. */ 2488 i = ((vm_offset_t)buf 2489 - (vm_offset_t)sc_if->msk_rdata.msk_jumbo_buf) / MSK_JLEN; 2490 KASSERT(i >= 0 && i < MSK_JSLOTS, 2491 ("%s: asked to free buffer that we don't manage!", __func__)); 2492 2493 entry = SLIST_FIRST(&sc_if->msk_jinuse_listhead); 2494 KASSERT(entry != NULL, ("%s: buffer not in use!", __func__)); 2495 entry->slot = i; 2496 SLIST_REMOVE_HEAD(&sc_if->msk_jinuse_listhead, jpool_entries); 2497 SLIST_INSERT_HEAD(&sc_if->msk_jfree_listhead, entry, jpool_entries); 2498 if (SLIST_EMPTY(&sc_if->msk_jinuse_listhead)) 2499 wakeup(sc_if); 2500 2501 MSK_JLIST_UNLOCK(sc_if); 2502 } 2503 2504 static int 2505 msk_encap(struct msk_if_softc *sc_if, struct mbuf **m_head) 2506 { 2507 struct msk_txdesc *txd, *txd_last; 2508 struct msk_tx_desc *tx_le; 2509 struct mbuf *m; 2510 bus_dmamap_t map; 2511 bus_dma_segment_t txsegs[MSK_MAXTXSEGS]; 2512 uint32_t control, prod, si; 2513 uint16_t offset, tcp_offset, tso_mtu; 2514 int error, i, nseg, tso; 2515 2516 MSK_IF_LOCK_ASSERT(sc_if); 2517 2518 tcp_offset = offset = 0; 2519 m = *m_head; 2520 if ((m->m_pkthdr.csum_flags & (MSK_CSUM_FEATURES | CSUM_TSO)) != 0) { 2521 /* 2522 * Since mbuf has no protocol specific structure information 2523 * in it we have to inspect protocol information here to 2524 * setup TSO and checksum offload. I don't know why Marvell 2525 * made a such decision in chip design because other GigE 2526 * hardwares normally takes care of all these chores in 2527 * hardware. However, TSO performance of Yukon II is very 2528 * good such that it's worth to implement it. 2529 */ 2530 struct ether_header *eh; 2531 struct ip *ip; 2532 struct tcphdr *tcp; 2533 2534 /* TODO check for M_WRITABLE(m) */ 2535 2536 offset = sizeof(struct ether_header); 2537 m = m_pullup(m, offset); 2538 if (m == NULL) { 2539 *m_head = NULL; 2540 return (ENOBUFS); 2541 } 2542 eh = mtod(m, struct ether_header *); 2543 /* Check if hardware VLAN insertion is off. */ 2544 if (eh->ether_type == htons(ETHERTYPE_VLAN)) { 2545 offset = sizeof(struct ether_vlan_header); 2546 m = m_pullup(m, offset); 2547 if (m == NULL) { 2548 *m_head = NULL; 2549 return (ENOBUFS); 2550 } 2551 } 2552 m = m_pullup(m, offset + sizeof(struct ip)); 2553 if (m == NULL) { 2554 *m_head = NULL; 2555 return (ENOBUFS); 2556 } 2557 ip = (struct ip *)(mtod(m, char *) + offset); 2558 offset += (ip->ip_hl << 2); 2559 tcp_offset = offset; 2560 /* 2561 * It seems that Yukon II has Tx checksum offload bug for 2562 * small TCP packets that's less than 60 bytes in size 2563 * (e.g. TCP window probe packet, pure ACK packet). 2564 * Common work around like padding with zeros to make the 2565 * frame minimum ethernet frame size didn't work at all. 2566 * Instead of disabling checksum offload completely we 2567 * resort to S/W checksum routine when we encounter short 2568 * TCP frames. 2569 * Short UDP packets appear to be handled correctly by 2570 * Yukon II. 2571 */ 2572 if (m->m_pkthdr.len < MSK_MIN_FRAMELEN && 2573 (m->m_pkthdr.csum_flags & CSUM_TCP) != 0) { 2574 uint16_t csum; 2575 2576 csum = in_cksum_skip(m, ntohs(ip->ip_len) + offset - 2577 (ip->ip_hl << 2), offset); 2578 *(uint16_t *)(m->m_data + offset + 2579 m->m_pkthdr.csum_data) = csum; 2580 m->m_pkthdr.csum_flags &= ~CSUM_TCP; 2581 } 2582 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 2583 m = m_pullup(m, offset + sizeof(struct tcphdr)); 2584 if (m == NULL) { 2585 *m_head = NULL; 2586 return (ENOBUFS); 2587 } 2588 tcp = (struct tcphdr *)(mtod(m, char *) + offset); 2589 offset += (tcp->th_off << 2); 2590 } 2591 *m_head = m; 2592 } 2593 2594 prod = sc_if->msk_cdata.msk_tx_prod; 2595 txd = &sc_if->msk_cdata.msk_txdesc[prod]; 2596 txd_last = txd; 2597 map = txd->tx_dmamap; 2598 error = bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_tx_tag, map, 2599 *m_head, txsegs, &nseg, BUS_DMA_NOWAIT); 2600 if (error == EFBIG) { 2601 m = m_collapse(*m_head, M_DONTWAIT, MSK_MAXTXSEGS); 2602 if (m == NULL) { 2603 m_freem(*m_head); 2604 *m_head = NULL; 2605 return (ENOBUFS); 2606 } 2607 *m_head = m; 2608 error = bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_tx_tag, 2609 map, *m_head, txsegs, &nseg, BUS_DMA_NOWAIT); 2610 if (error != 0) { 2611 m_freem(*m_head); 2612 *m_head = NULL; 2613 return (error); 2614 } 2615 } else if (error != 0) 2616 return (error); 2617 if (nseg == 0) { 2618 m_freem(*m_head); 2619 *m_head = NULL; 2620 return (EIO); 2621 } 2622 2623 /* Check number of available descriptors. */ 2624 if (sc_if->msk_cdata.msk_tx_cnt + nseg >= 2625 (MSK_TX_RING_CNT - MSK_RESERVED_TX_DESC_CNT)) { 2626 bus_dmamap_unload(sc_if->msk_cdata.msk_tx_tag, map); 2627 return (ENOBUFS); 2628 } 2629 2630 control = 0; 2631 tso = 0; 2632 tx_le = NULL; 2633 2634 /* Check TSO support. */ 2635 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 2636 tso_mtu = offset + m->m_pkthdr.tso_segsz; 2637 if (tso_mtu != sc_if->msk_cdata.msk_tso_mtu) { 2638 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2639 tx_le->msk_addr = htole32(tso_mtu); 2640 tx_le->msk_control = htole32(OP_LRGLEN | HW_OWNER); 2641 sc_if->msk_cdata.msk_tx_cnt++; 2642 MSK_INC(prod, MSK_TX_RING_CNT); 2643 sc_if->msk_cdata.msk_tso_mtu = tso_mtu; 2644 } 2645 tso++; 2646 } 2647 /* Check if we have a VLAN tag to insert. */ 2648 if ((m->m_flags & M_VLANTAG) != 0) { 2649 if (tso == 0) { 2650 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2651 tx_le->msk_addr = htole32(0); 2652 tx_le->msk_control = htole32(OP_VLAN | HW_OWNER | 2653 htons(m->m_pkthdr.ether_vtag)); 2654 sc_if->msk_cdata.msk_tx_cnt++; 2655 MSK_INC(prod, MSK_TX_RING_CNT); 2656 } else { 2657 tx_le->msk_control |= htole32(OP_VLAN | 2658 htons(m->m_pkthdr.ether_vtag)); 2659 } 2660 control |= INS_VLAN; 2661 } 2662 /* Check if we have to handle checksum offload. */ 2663 if (tso == 0 && (m->m_pkthdr.csum_flags & MSK_CSUM_FEATURES) != 0) { 2664 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2665 tx_le->msk_addr = htole32(((tcp_offset + m->m_pkthdr.csum_data) 2666 & 0xffff) | ((uint32_t)tcp_offset << 16)); 2667 tx_le->msk_control = htole32(1 << 16 | (OP_TCPLISW | HW_OWNER)); 2668 control = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM; 2669 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0) 2670 control |= UDPTCP; 2671 sc_if->msk_cdata.msk_tx_cnt++; 2672 MSK_INC(prod, MSK_TX_RING_CNT); 2673 } 2674 2675 si = prod; 2676 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2677 tx_le->msk_addr = htole32(MSK_ADDR_LO(txsegs[0].ds_addr)); 2678 if (tso == 0) 2679 tx_le->msk_control = htole32(txsegs[0].ds_len | control | 2680 OP_PACKET); 2681 else 2682 tx_le->msk_control = htole32(txsegs[0].ds_len | control | 2683 OP_LARGESEND); 2684 sc_if->msk_cdata.msk_tx_cnt++; 2685 MSK_INC(prod, MSK_TX_RING_CNT); 2686 2687 for (i = 1; i < nseg; i++) { 2688 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2689 tx_le->msk_addr = htole32(MSK_ADDR_LO(txsegs[i].ds_addr)); 2690 tx_le->msk_control = htole32(txsegs[i].ds_len | control | 2691 OP_BUFFER | HW_OWNER); 2692 sc_if->msk_cdata.msk_tx_cnt++; 2693 MSK_INC(prod, MSK_TX_RING_CNT); 2694 } 2695 /* Update producer index. */ 2696 sc_if->msk_cdata.msk_tx_prod = prod; 2697 2698 /* Set EOP on the last desciptor. */ 2699 prod = (prod + MSK_TX_RING_CNT - 1) % MSK_TX_RING_CNT; 2700 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2701 tx_le->msk_control |= htole32(EOP); 2702 2703 /* Turn the first descriptor ownership to hardware. */ 2704 tx_le = &sc_if->msk_rdata.msk_tx_ring[si]; 2705 tx_le->msk_control |= htole32(HW_OWNER); 2706 2707 txd = &sc_if->msk_cdata.msk_txdesc[prod]; 2708 map = txd_last->tx_dmamap; 2709 txd_last->tx_dmamap = txd->tx_dmamap; 2710 txd->tx_dmamap = map; 2711 txd->tx_m = m; 2712 2713 /* Sync descriptors. */ 2714 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_tag, map, BUS_DMASYNC_PREWRITE); 2715 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_ring_tag, 2716 sc_if->msk_cdata.msk_tx_ring_map, 2717 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2718 2719 return (0); 2720 } 2721 2722 static void 2723 msk_tx_task(void *arg, int pending) 2724 { 2725 struct ifnet *ifp; 2726 2727 ifp = arg; 2728 msk_start(ifp); 2729 } 2730 2731 static void 2732 msk_start(struct ifnet *ifp) 2733 { 2734 struct msk_if_softc *sc_if; 2735 struct mbuf *m_head; 2736 int enq; 2737 2738 sc_if = ifp->if_softc; 2739 2740 MSK_IF_LOCK(sc_if); 2741 2742 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2743 IFF_DRV_RUNNING || sc_if->msk_link == 0) { 2744 MSK_IF_UNLOCK(sc_if); 2745 return; 2746 } 2747 2748 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 2749 sc_if->msk_cdata.msk_tx_cnt < 2750 (MSK_TX_RING_CNT - MSK_RESERVED_TX_DESC_CNT); ) { 2751 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2752 if (m_head == NULL) 2753 break; 2754 /* 2755 * Pack the data into the transmit ring. If we 2756 * don't have room, set the OACTIVE flag and wait 2757 * for the NIC to drain the ring. 2758 */ 2759 if (msk_encap(sc_if, &m_head) != 0) { 2760 if (m_head == NULL) 2761 break; 2762 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2763 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2764 break; 2765 } 2766 2767 enq++; 2768 /* 2769 * If there's a BPF listener, bounce a copy of this frame 2770 * to him. 2771 */ 2772 ETHER_BPF_MTAP(ifp, m_head); 2773 } 2774 2775 if (enq > 0) { 2776 /* Transmit */ 2777 CSR_WRITE_2(sc_if->msk_softc, 2778 Y2_PREF_Q_ADDR(sc_if->msk_txq, PREF_UNIT_PUT_IDX_REG), 2779 sc_if->msk_cdata.msk_tx_prod); 2780 2781 /* Set a timeout in case the chip goes out to lunch. */ 2782 sc_if->msk_watchdog_timer = MSK_TX_TIMEOUT; 2783 } 2784 2785 MSK_IF_UNLOCK(sc_if); 2786 } 2787 2788 static void 2789 msk_watchdog(struct msk_if_softc *sc_if) 2790 { 2791 struct ifnet *ifp; 2792 uint32_t ridx; 2793 int idx; 2794 2795 MSK_IF_LOCK_ASSERT(sc_if); 2796 2797 if (sc_if->msk_watchdog_timer == 0 || --sc_if->msk_watchdog_timer) 2798 return; 2799 ifp = sc_if->msk_ifp; 2800 if (sc_if->msk_link == 0) { 2801 if (bootverbose) 2802 if_printf(sc_if->msk_ifp, "watchdog timeout " 2803 "(missed link)\n"); 2804 ifp->if_oerrors++; 2805 msk_init_locked(sc_if); 2806 return; 2807 } 2808 2809 /* 2810 * Reclaim first as there is a possibility of losing Tx completion 2811 * interrupts. 2812 */ 2813 ridx = sc_if->msk_port == MSK_PORT_A ? STAT_TXA1_RIDX : STAT_TXA2_RIDX; 2814 idx = CSR_READ_2(sc_if->msk_softc, ridx); 2815 if (sc_if->msk_cdata.msk_tx_cons != idx) { 2816 msk_txeof(sc_if, idx); 2817 if (sc_if->msk_cdata.msk_tx_cnt == 0) { 2818 if_printf(ifp, "watchdog timeout (missed Tx interrupts) " 2819 "-- recovering\n"); 2820 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2821 taskqueue_enqueue(taskqueue_fast, 2822 &sc_if->msk_tx_task); 2823 return; 2824 } 2825 } 2826 2827 if_printf(ifp, "watchdog timeout\n"); 2828 ifp->if_oerrors++; 2829 msk_init_locked(sc_if); 2830 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2831 taskqueue_enqueue(taskqueue_fast, &sc_if->msk_tx_task); 2832 } 2833 2834 static int 2835 mskc_shutdown(device_t dev) 2836 { 2837 struct msk_softc *sc; 2838 int i; 2839 2840 sc = device_get_softc(dev); 2841 MSK_LOCK(sc); 2842 for (i = 0; i < sc->msk_num_port; i++) { 2843 if (sc->msk_if[i] != NULL) 2844 msk_stop(sc->msk_if[i]); 2845 } 2846 2847 /* Disable all interrupts. */ 2848 CSR_WRITE_4(sc, B0_IMSK, 0); 2849 CSR_READ_4(sc, B0_IMSK); 2850 CSR_WRITE_4(sc, B0_HWE_IMSK, 0); 2851 CSR_READ_4(sc, B0_HWE_IMSK); 2852 2853 /* Put hardware reset. */ 2854 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); 2855 2856 MSK_UNLOCK(sc); 2857 return (0); 2858 } 2859 2860 static int 2861 mskc_suspend(device_t dev) 2862 { 2863 struct msk_softc *sc; 2864 int i; 2865 2866 sc = device_get_softc(dev); 2867 2868 MSK_LOCK(sc); 2869 2870 for (i = 0; i < sc->msk_num_port; i++) { 2871 if (sc->msk_if[i] != NULL && sc->msk_if[i]->msk_ifp != NULL && 2872 ((sc->msk_if[i]->msk_ifp->if_drv_flags & 2873 IFF_DRV_RUNNING) != 0)) 2874 msk_stop(sc->msk_if[i]); 2875 } 2876 2877 /* Disable all interrupts. */ 2878 CSR_WRITE_4(sc, B0_IMSK, 0); 2879 CSR_READ_4(sc, B0_IMSK); 2880 CSR_WRITE_4(sc, B0_HWE_IMSK, 0); 2881 CSR_READ_4(sc, B0_HWE_IMSK); 2882 2883 msk_phy_power(sc, MSK_PHY_POWERDOWN); 2884 2885 /* Put hardware reset. */ 2886 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); 2887 sc->msk_suspended = 1; 2888 2889 MSK_UNLOCK(sc); 2890 2891 return (0); 2892 } 2893 2894 static int 2895 mskc_resume(device_t dev) 2896 { 2897 struct msk_softc *sc; 2898 int i; 2899 2900 sc = device_get_softc(dev); 2901 2902 MSK_LOCK(sc); 2903 2904 mskc_reset(sc); 2905 for (i = 0; i < sc->msk_num_port; i++) { 2906 if (sc->msk_if[i] != NULL && sc->msk_if[i]->msk_ifp != NULL && 2907 ((sc->msk_if[i]->msk_ifp->if_flags & IFF_UP) != 0)) 2908 msk_init_locked(sc->msk_if[i]); 2909 } 2910 sc->msk_suspended = 0; 2911 2912 MSK_UNLOCK(sc); 2913 2914 return (0); 2915 } 2916 2917 static void 2918 msk_rxeof(struct msk_if_softc *sc_if, uint32_t status, int len) 2919 { 2920 struct mbuf *m; 2921 struct ifnet *ifp; 2922 struct msk_rxdesc *rxd; 2923 int cons, rxlen; 2924 2925 ifp = sc_if->msk_ifp; 2926 2927 MSK_IF_LOCK_ASSERT(sc_if); 2928 2929 cons = sc_if->msk_cdata.msk_rx_cons; 2930 do { 2931 rxlen = status >> 16; 2932 if ((status & GMR_FS_VLAN) != 0 && 2933 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 2934 rxlen -= ETHER_VLAN_ENCAP_LEN; 2935 if (len > sc_if->msk_framesize || 2936 ((status & GMR_FS_ANY_ERR) != 0) || 2937 ((status & GMR_FS_RX_OK) == 0) || (rxlen != len)) { 2938 /* Don't count flow-control packet as errors. */ 2939 if ((status & GMR_FS_GOOD_FC) == 0) 2940 ifp->if_ierrors++; 2941 msk_discard_rxbuf(sc_if, cons); 2942 break; 2943 } 2944 rxd = &sc_if->msk_cdata.msk_rxdesc[cons]; 2945 m = rxd->rx_m; 2946 if (msk_newbuf(sc_if, cons) != 0) { 2947 ifp->if_iqdrops++; 2948 /* Reuse old buffer. */ 2949 msk_discard_rxbuf(sc_if, cons); 2950 break; 2951 } 2952 m->m_pkthdr.rcvif = ifp; 2953 m->m_pkthdr.len = m->m_len = len; 2954 ifp->if_ipackets++; 2955 /* Check for VLAN tagged packets. */ 2956 if ((status & GMR_FS_VLAN) != 0 && 2957 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) { 2958 m->m_pkthdr.ether_vtag = sc_if->msk_vtag; 2959 m->m_flags |= M_VLANTAG; 2960 } 2961 MSK_IF_UNLOCK(sc_if); 2962 (*ifp->if_input)(ifp, m); 2963 MSK_IF_LOCK(sc_if); 2964 } while (0); 2965 2966 MSK_INC(sc_if->msk_cdata.msk_rx_cons, MSK_RX_RING_CNT); 2967 MSK_INC(sc_if->msk_cdata.msk_rx_prod, MSK_RX_RING_CNT); 2968 } 2969 2970 static void 2971 msk_jumbo_rxeof(struct msk_if_softc *sc_if, uint32_t status, int len) 2972 { 2973 struct mbuf *m; 2974 struct ifnet *ifp; 2975 struct msk_rxdesc *jrxd; 2976 int cons, rxlen; 2977 2978 ifp = sc_if->msk_ifp; 2979 2980 MSK_IF_LOCK_ASSERT(sc_if); 2981 2982 cons = sc_if->msk_cdata.msk_rx_cons; 2983 do { 2984 rxlen = status >> 16; 2985 if ((status & GMR_FS_VLAN) != 0 && 2986 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 2987 rxlen -= ETHER_VLAN_ENCAP_LEN; 2988 if (len > sc_if->msk_framesize || 2989 ((status & GMR_FS_ANY_ERR) != 0) || 2990 ((status & GMR_FS_RX_OK) == 0) || (rxlen != len)) { 2991 /* Don't count flow-control packet as errors. */ 2992 if ((status & GMR_FS_GOOD_FC) == 0) 2993 ifp->if_ierrors++; 2994 msk_discard_jumbo_rxbuf(sc_if, cons); 2995 break; 2996 } 2997 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[cons]; 2998 m = jrxd->rx_m; 2999 if (msk_jumbo_newbuf(sc_if, cons) != 0) { 3000 ifp->if_iqdrops++; 3001 /* Reuse old buffer. */ 3002 msk_discard_jumbo_rxbuf(sc_if, cons); 3003 break; 3004 } 3005 m->m_pkthdr.rcvif = ifp; 3006 m->m_pkthdr.len = m->m_len = len; 3007 ifp->if_ipackets++; 3008 /* Check for VLAN tagged packets. */ 3009 if ((status & GMR_FS_VLAN) != 0 && 3010 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) { 3011 m->m_pkthdr.ether_vtag = sc_if->msk_vtag; 3012 m->m_flags |= M_VLANTAG; 3013 } 3014 MSK_IF_UNLOCK(sc_if); 3015 (*ifp->if_input)(ifp, m); 3016 MSK_IF_LOCK(sc_if); 3017 } while (0); 3018 3019 MSK_INC(sc_if->msk_cdata.msk_rx_cons, MSK_JUMBO_RX_RING_CNT); 3020 MSK_INC(sc_if->msk_cdata.msk_rx_prod, MSK_JUMBO_RX_RING_CNT); 3021 } 3022 3023 static void 3024 msk_txeof(struct msk_if_softc *sc_if, int idx) 3025 { 3026 struct msk_txdesc *txd; 3027 struct msk_tx_desc *cur_tx; 3028 struct ifnet *ifp; 3029 uint32_t control; 3030 int cons, prog; 3031 3032 MSK_IF_LOCK_ASSERT(sc_if); 3033 3034 ifp = sc_if->msk_ifp; 3035 3036 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_ring_tag, 3037 sc_if->msk_cdata.msk_tx_ring_map, 3038 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3039 /* 3040 * Go through our tx ring and free mbufs for those 3041 * frames that have been sent. 3042 */ 3043 cons = sc_if->msk_cdata.msk_tx_cons; 3044 prog = 0; 3045 for (; cons != idx; MSK_INC(cons, MSK_TX_RING_CNT)) { 3046 if (sc_if->msk_cdata.msk_tx_cnt <= 0) 3047 break; 3048 prog++; 3049 cur_tx = &sc_if->msk_rdata.msk_tx_ring[cons]; 3050 control = le32toh(cur_tx->msk_control); 3051 sc_if->msk_cdata.msk_tx_cnt--; 3052 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3053 if ((control & EOP) == 0) 3054 continue; 3055 txd = &sc_if->msk_cdata.msk_txdesc[cons]; 3056 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_tag, txd->tx_dmamap, 3057 BUS_DMASYNC_POSTWRITE); 3058 bus_dmamap_unload(sc_if->msk_cdata.msk_tx_tag, txd->tx_dmamap); 3059 3060 ifp->if_opackets++; 3061 KASSERT(txd->tx_m != NULL, ("%s: freeing NULL mbuf!", 3062 __func__)); 3063 m_freem(txd->tx_m); 3064 txd->tx_m = NULL; 3065 } 3066 3067 if (prog > 0) { 3068 sc_if->msk_cdata.msk_tx_cons = cons; 3069 if (sc_if->msk_cdata.msk_tx_cnt == 0) 3070 sc_if->msk_watchdog_timer = 0; 3071 /* No need to sync LEs as we didn't update LEs. */ 3072 } 3073 } 3074 3075 static void 3076 msk_tick(void *xsc_if) 3077 { 3078 struct msk_if_softc *sc_if; 3079 struct mii_data *mii; 3080 3081 sc_if = xsc_if; 3082 3083 MSK_IF_LOCK_ASSERT(sc_if); 3084 3085 mii = device_get_softc(sc_if->msk_miibus); 3086 3087 mii_tick(mii); 3088 msk_watchdog(sc_if); 3089 callout_reset(&sc_if->msk_tick_ch, hz, msk_tick, sc_if); 3090 } 3091 3092 static void 3093 msk_intr_phy(struct msk_if_softc *sc_if) 3094 { 3095 uint16_t status; 3096 3097 msk_phy_readreg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_STAT); 3098 status = msk_phy_readreg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_STAT); 3099 /* Handle FIFO Underrun/Overflow? */ 3100 if ((status & PHY_M_IS_FIFO_ERROR)) 3101 device_printf(sc_if->msk_if_dev, 3102 "PHY FIFO underrun/overflow.\n"); 3103 } 3104 3105 static void 3106 msk_intr_gmac(struct msk_if_softc *sc_if) 3107 { 3108 struct msk_softc *sc; 3109 uint8_t status; 3110 3111 sc = sc_if->msk_softc; 3112 status = CSR_READ_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_SRC)); 3113 3114 /* GMAC Rx FIFO overrun. */ 3115 if ((status & GM_IS_RX_FF_OR) != 0) { 3116 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), 3117 GMF_CLI_RX_FO); 3118 device_printf(sc_if->msk_if_dev, "Rx FIFO overrun!\n"); 3119 } 3120 /* GMAC Tx FIFO underrun. */ 3121 if ((status & GM_IS_TX_FF_UR) != 0) { 3122 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 3123 GMF_CLI_TX_FU); 3124 device_printf(sc_if->msk_if_dev, "Tx FIFO underrun!\n"); 3125 /* 3126 * XXX 3127 * In case of Tx underrun, we may need to flush/reset 3128 * Tx MAC but that would also require resynchronization 3129 * with status LEs. Reintializing status LEs would 3130 * affect other port in dual MAC configuration so it 3131 * should be avoided as possible as we can. 3132 * Due to lack of documentation it's all vague guess but 3133 * it needs more investigation. 3134 */ 3135 } 3136 } 3137 3138 static void 3139 msk_handle_hwerr(struct msk_if_softc *sc_if, uint32_t status) 3140 { 3141 struct msk_softc *sc; 3142 3143 sc = sc_if->msk_softc; 3144 if ((status & Y2_IS_PAR_RD1) != 0) { 3145 device_printf(sc_if->msk_if_dev, 3146 "RAM buffer read parity error\n"); 3147 /* Clear IRQ. */ 3148 CSR_WRITE_2(sc, SELECT_RAM_BUFFER(sc_if->msk_port, B3_RI_CTRL), 3149 RI_CLR_RD_PERR); 3150 } 3151 if ((status & Y2_IS_PAR_WR1) != 0) { 3152 device_printf(sc_if->msk_if_dev, 3153 "RAM buffer write parity error\n"); 3154 /* Clear IRQ. */ 3155 CSR_WRITE_2(sc, SELECT_RAM_BUFFER(sc_if->msk_port, B3_RI_CTRL), 3156 RI_CLR_WR_PERR); 3157 } 3158 if ((status & Y2_IS_PAR_MAC1) != 0) { 3159 device_printf(sc_if->msk_if_dev, "Tx MAC parity error\n"); 3160 /* Clear IRQ. */ 3161 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 3162 GMF_CLI_TX_PE); 3163 } 3164 if ((status & Y2_IS_PAR_RX1) != 0) { 3165 device_printf(sc_if->msk_if_dev, "Rx parity error\n"); 3166 /* Clear IRQ. */ 3167 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_CLR_IRQ_PAR); 3168 } 3169 if ((status & (Y2_IS_TCP_TXS1 | Y2_IS_TCP_TXA1)) != 0) { 3170 device_printf(sc_if->msk_if_dev, "TCP segmentation error\n"); 3171 /* Clear IRQ. */ 3172 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_CLR_IRQ_TCP); 3173 } 3174 } 3175 3176 static void 3177 msk_intr_hwerr(struct msk_softc *sc) 3178 { 3179 uint32_t status; 3180 uint32_t tlphead[4]; 3181 3182 status = CSR_READ_4(sc, B0_HWE_ISRC); 3183 /* Time Stamp timer overflow. */ 3184 if ((status & Y2_IS_TIST_OV) != 0) 3185 CSR_WRITE_1(sc, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ); 3186 if ((status & Y2_IS_PCI_NEXP) != 0) { 3187 /* 3188 * PCI Express Error occured which is not described in PEX 3189 * spec. 3190 * This error is also mapped either to Master Abort( 3191 * Y2_IS_MST_ERR) or Target Abort (Y2_IS_IRQ_STAT) bit and 3192 * can only be cleared there. 3193 */ 3194 device_printf(sc->msk_dev, 3195 "PCI Express protocol violation error\n"); 3196 } 3197 3198 if ((status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) != 0) { 3199 uint16_t v16; 3200 3201 if ((status & Y2_IS_MST_ERR) != 0) 3202 device_printf(sc->msk_dev, 3203 "unexpected IRQ Status error\n"); 3204 else 3205 device_printf(sc->msk_dev, 3206 "unexpected IRQ Master error\n"); 3207 /* Reset all bits in the PCI status register. */ 3208 v16 = pci_read_config(sc->msk_dev, PCIR_STATUS, 2); 3209 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON); 3210 pci_write_config(sc->msk_dev, PCIR_STATUS, v16 | 3211 PCIM_STATUS_PERR | PCIM_STATUS_SERR | PCIM_STATUS_RMABORT | 3212 PCIM_STATUS_RTABORT | PCIM_STATUS_PERRREPORT, 2); 3213 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 3214 } 3215 3216 /* Check for PCI Express Uncorrectable Error. */ 3217 if ((status & Y2_IS_PCI_EXP) != 0) { 3218 uint32_t v32; 3219 3220 /* 3221 * On PCI Express bus bridges are called root complexes (RC). 3222 * PCI Express errors are recognized by the root complex too, 3223 * which requests the system to handle the problem. After 3224 * error occurence it may be that no access to the adapter 3225 * may be performed any longer. 3226 */ 3227 3228 v32 = CSR_PCI_READ_4(sc, PEX_UNC_ERR_STAT); 3229 if ((v32 & PEX_UNSUP_REQ) != 0) { 3230 /* Ignore unsupported request error. */ 3231 device_printf(sc->msk_dev, 3232 "Uncorrectable PCI Express error\n"); 3233 } 3234 if ((v32 & (PEX_FATAL_ERRORS | PEX_POIS_TLP)) != 0) { 3235 int i; 3236 3237 /* Get TLP header form Log Registers. */ 3238 for (i = 0; i < 4; i++) 3239 tlphead[i] = CSR_PCI_READ_4(sc, 3240 PEX_HEADER_LOG + i * 4); 3241 /* Check for vendor defined broadcast message. */ 3242 if (!(tlphead[0] == 0x73004001 && tlphead[1] == 0x7f)) { 3243 sc->msk_intrhwemask &= ~Y2_IS_PCI_EXP; 3244 CSR_WRITE_4(sc, B0_HWE_IMSK, 3245 sc->msk_intrhwemask); 3246 CSR_READ_4(sc, B0_HWE_IMSK); 3247 } 3248 } 3249 /* Clear the interrupt. */ 3250 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON); 3251 CSR_PCI_WRITE_4(sc, PEX_UNC_ERR_STAT, 0xffffffff); 3252 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 3253 } 3254 3255 if ((status & Y2_HWE_L1_MASK) != 0 && sc->msk_if[MSK_PORT_A] != NULL) 3256 msk_handle_hwerr(sc->msk_if[MSK_PORT_A], status); 3257 if ((status & Y2_HWE_L2_MASK) != 0 && sc->msk_if[MSK_PORT_B] != NULL) 3258 msk_handle_hwerr(sc->msk_if[MSK_PORT_B], status >> 8); 3259 } 3260 3261 static __inline void 3262 msk_rxput(struct msk_if_softc *sc_if) 3263 { 3264 struct msk_softc *sc; 3265 3266 sc = sc_if->msk_softc; 3267 if (sc_if->msk_framesize >(MCLBYTES - ETHER_HDR_LEN)) 3268 bus_dmamap_sync( 3269 sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 3270 sc_if->msk_cdata.msk_jumbo_rx_ring_map, 3271 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3272 else 3273 bus_dmamap_sync( 3274 sc_if->msk_cdata.msk_rx_ring_tag, 3275 sc_if->msk_cdata.msk_rx_ring_map, 3276 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3277 CSR_WRITE_2(sc, Y2_PREF_Q_ADDR(sc_if->msk_rxq, 3278 PREF_UNIT_PUT_IDX_REG), sc_if->msk_cdata.msk_rx_prod); 3279 } 3280 3281 static int 3282 msk_handle_events(struct msk_softc *sc) 3283 { 3284 struct msk_if_softc *sc_if; 3285 int rxput[2]; 3286 struct msk_stat_desc *sd; 3287 uint32_t control, status; 3288 int cons, idx, len, port, rxprog; 3289 3290 idx = CSR_READ_2(sc, STAT_PUT_IDX); 3291 if (idx == sc->msk_stat_cons) 3292 return (0); 3293 3294 /* Sync status LEs. */ 3295 bus_dmamap_sync(sc->msk_stat_tag, sc->msk_stat_map, 3296 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3297 /* XXX Sync Rx LEs here. */ 3298 3299 rxput[MSK_PORT_A] = rxput[MSK_PORT_B] = 0; 3300 3301 rxprog = 0; 3302 for (cons = sc->msk_stat_cons; cons != idx;) { 3303 sd = &sc->msk_stat_ring[cons]; 3304 control = le32toh(sd->msk_control); 3305 if ((control & HW_OWNER) == 0) 3306 break; 3307 /* 3308 * Marvell's FreeBSD driver updates status LE after clearing 3309 * HW_OWNER. However we don't have a way to sync single LE 3310 * with bus_dma(9) API. bus_dma(9) provides a way to sync 3311 * an entire DMA map. So don't sync LE until we have a better 3312 * way to sync LEs. 3313 */ 3314 control &= ~HW_OWNER; 3315 sd->msk_control = htole32(control); 3316 status = le32toh(sd->msk_status); 3317 len = control & STLE_LEN_MASK; 3318 port = (control >> 16) & 0x01; 3319 sc_if = sc->msk_if[port]; 3320 if (sc_if == NULL) { 3321 device_printf(sc->msk_dev, "invalid port opcode " 3322 "0x%08x\n", control & STLE_OP_MASK); 3323 continue; 3324 } 3325 3326 switch (control & STLE_OP_MASK) { 3327 case OP_RXVLAN: 3328 sc_if->msk_vtag = ntohs(len); 3329 break; 3330 case OP_RXCHKSVLAN: 3331 sc_if->msk_vtag = ntohs(len); 3332 break; 3333 case OP_RXSTAT: 3334 if (sc_if->msk_framesize > (MCLBYTES - ETHER_HDR_LEN)) 3335 msk_jumbo_rxeof(sc_if, status, len); 3336 else 3337 msk_rxeof(sc_if, status, len); 3338 rxprog++; 3339 /* 3340 * Because there is no way to sync single Rx LE 3341 * put the DMA sync operation off until the end of 3342 * event processing. 3343 */ 3344 rxput[port]++; 3345 /* Update prefetch unit if we've passed water mark. */ 3346 if (rxput[port] >= sc_if->msk_cdata.msk_rx_putwm) { 3347 msk_rxput(sc_if); 3348 rxput[port] = 0; 3349 } 3350 break; 3351 case OP_TXINDEXLE: 3352 if (sc->msk_if[MSK_PORT_A] != NULL) 3353 msk_txeof(sc->msk_if[MSK_PORT_A], 3354 status & STLE_TXA1_MSKL); 3355 if (sc->msk_if[MSK_PORT_B] != NULL) 3356 msk_txeof(sc->msk_if[MSK_PORT_B], 3357 ((status & STLE_TXA2_MSKL) >> 3358 STLE_TXA2_SHIFTL) | 3359 ((len & STLE_TXA2_MSKH) << 3360 STLE_TXA2_SHIFTH)); 3361 break; 3362 default: 3363 device_printf(sc->msk_dev, "unhandled opcode 0x%08x\n", 3364 control & STLE_OP_MASK); 3365 break; 3366 } 3367 MSK_INC(cons, MSK_STAT_RING_CNT); 3368 if (rxprog > sc->msk_process_limit) 3369 break; 3370 } 3371 3372 sc->msk_stat_cons = cons; 3373 /* XXX We should sync status LEs here. See above notes. */ 3374 3375 if (rxput[MSK_PORT_A] > 0) 3376 msk_rxput(sc->msk_if[MSK_PORT_A]); 3377 if (rxput[MSK_PORT_B] > 0) 3378 msk_rxput(sc->msk_if[MSK_PORT_B]); 3379 3380 return (sc->msk_stat_cons != CSR_READ_2(sc, STAT_PUT_IDX)); 3381 } 3382 3383 /* Legacy interrupt handler for shared interrupt. */ 3384 static void 3385 msk_legacy_intr(void *xsc) 3386 { 3387 struct msk_softc *sc; 3388 struct msk_if_softc *sc_if0, *sc_if1; 3389 struct ifnet *ifp0, *ifp1; 3390 uint32_t status; 3391 3392 sc = xsc; 3393 MSK_LOCK(sc); 3394 3395 /* Reading B0_Y2_SP_ISRC2 masks further interrupts. */ 3396 status = CSR_READ_4(sc, B0_Y2_SP_ISRC2); 3397 if (status == 0 || status == 0xffffffff || sc->msk_suspended != 0 || 3398 (status & sc->msk_intrmask) == 0) { 3399 CSR_WRITE_4(sc, B0_Y2_SP_ICR, 2); 3400 return; 3401 } 3402 3403 sc_if0 = sc->msk_if[MSK_PORT_A]; 3404 sc_if1 = sc->msk_if[MSK_PORT_B]; 3405 ifp0 = ifp1 = NULL; 3406 if (sc_if0 != NULL) 3407 ifp0 = sc_if0->msk_ifp; 3408 if (sc_if1 != NULL) 3409 ifp1 = sc_if1->msk_ifp; 3410 3411 if ((status & Y2_IS_IRQ_PHY1) != 0 && sc_if0 != NULL) 3412 msk_intr_phy(sc_if0); 3413 if ((status & Y2_IS_IRQ_PHY2) != 0 && sc_if1 != NULL) 3414 msk_intr_phy(sc_if1); 3415 if ((status & Y2_IS_IRQ_MAC1) != 0 && sc_if0 != NULL) 3416 msk_intr_gmac(sc_if0); 3417 if ((status & Y2_IS_IRQ_MAC2) != 0 && sc_if1 != NULL) 3418 msk_intr_gmac(sc_if1); 3419 if ((status & (Y2_IS_CHK_RX1 | Y2_IS_CHK_RX2)) != 0) { 3420 device_printf(sc->msk_dev, "Rx descriptor error\n"); 3421 sc->msk_intrmask &= ~(Y2_IS_CHK_RX1 | Y2_IS_CHK_RX2); 3422 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask); 3423 CSR_READ_4(sc, B0_IMSK); 3424 } 3425 if ((status & (Y2_IS_CHK_TXA1 | Y2_IS_CHK_TXA2)) != 0) { 3426 device_printf(sc->msk_dev, "Tx descriptor error\n"); 3427 sc->msk_intrmask &= ~(Y2_IS_CHK_TXA1 | Y2_IS_CHK_TXA2); 3428 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask); 3429 CSR_READ_4(sc, B0_IMSK); 3430 } 3431 if ((status & Y2_IS_HW_ERR) != 0) 3432 msk_intr_hwerr(sc); 3433 3434 while (msk_handle_events(sc) != 0) 3435 ; 3436 if ((status & Y2_IS_STAT_BMU) != 0) 3437 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_CLR_IRQ); 3438 3439 /* Reenable interrupts. */ 3440 CSR_WRITE_4(sc, B0_Y2_SP_ICR, 2); 3441 3442 if (ifp0 != NULL && (ifp0->if_drv_flags & IFF_DRV_RUNNING) != 0 && 3443 !IFQ_DRV_IS_EMPTY(&ifp0->if_snd)) 3444 taskqueue_enqueue(taskqueue_fast, &sc_if0->msk_tx_task); 3445 if (ifp1 != NULL && (ifp1->if_drv_flags & IFF_DRV_RUNNING) != 0 && 3446 !IFQ_DRV_IS_EMPTY(&ifp1->if_snd)) 3447 taskqueue_enqueue(taskqueue_fast, &sc_if1->msk_tx_task); 3448 3449 MSK_UNLOCK(sc); 3450 } 3451 3452 static int 3453 msk_intr(void *xsc) 3454 { 3455 struct msk_softc *sc; 3456 uint32_t status; 3457 3458 sc = xsc; 3459 status = CSR_READ_4(sc, B0_Y2_SP_ISRC2); 3460 /* Reading B0_Y2_SP_ISRC2 masks further interrupts. */ 3461 if (status == 0 || status == 0xffffffff) { 3462 CSR_WRITE_4(sc, B0_Y2_SP_ICR, 2); 3463 return (FILTER_STRAY); 3464 } 3465 3466 taskqueue_enqueue(sc->msk_tq, &sc->msk_int_task); 3467 return (FILTER_HANDLED); 3468 } 3469 3470 static void 3471 msk_int_task(void *arg, int pending) 3472 { 3473 struct msk_softc *sc; 3474 struct msk_if_softc *sc_if0, *sc_if1; 3475 struct ifnet *ifp0, *ifp1; 3476 uint32_t status; 3477 int domore; 3478 3479 sc = arg; 3480 MSK_LOCK(sc); 3481 3482 /* Get interrupt source. */ 3483 status = CSR_READ_4(sc, B0_ISRC); 3484 if (status == 0 || status == 0xffffffff || sc->msk_suspended != 0 || 3485 (status & sc->msk_intrmask) == 0) 3486 goto done; 3487 3488 sc_if0 = sc->msk_if[MSK_PORT_A]; 3489 sc_if1 = sc->msk_if[MSK_PORT_B]; 3490 ifp0 = ifp1 = NULL; 3491 if (sc_if0 != NULL) 3492 ifp0 = sc_if0->msk_ifp; 3493 if (sc_if1 != NULL) 3494 ifp1 = sc_if1->msk_ifp; 3495 3496 if ((status & Y2_IS_IRQ_PHY1) != 0 && sc_if0 != NULL) 3497 msk_intr_phy(sc_if0); 3498 if ((status & Y2_IS_IRQ_PHY2) != 0 && sc_if1 != NULL) 3499 msk_intr_phy(sc_if1); 3500 if ((status & Y2_IS_IRQ_MAC1) != 0 && sc_if0 != NULL) 3501 msk_intr_gmac(sc_if0); 3502 if ((status & Y2_IS_IRQ_MAC2) != 0 && sc_if1 != NULL) 3503 msk_intr_gmac(sc_if1); 3504 if ((status & (Y2_IS_CHK_RX1 | Y2_IS_CHK_RX2)) != 0) { 3505 device_printf(sc->msk_dev, "Rx descriptor error\n"); 3506 sc->msk_intrmask &= ~(Y2_IS_CHK_RX1 | Y2_IS_CHK_RX2); 3507 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask); 3508 CSR_READ_4(sc, B0_IMSK); 3509 } 3510 if ((status & (Y2_IS_CHK_TXA1 | Y2_IS_CHK_TXA2)) != 0) { 3511 device_printf(sc->msk_dev, "Tx descriptor error\n"); 3512 sc->msk_intrmask &= ~(Y2_IS_CHK_TXA1 | Y2_IS_CHK_TXA2); 3513 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask); 3514 CSR_READ_4(sc, B0_IMSK); 3515 } 3516 if ((status & Y2_IS_HW_ERR) != 0) 3517 msk_intr_hwerr(sc); 3518 3519 domore = msk_handle_events(sc); 3520 if ((status & Y2_IS_STAT_BMU) != 0) 3521 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_CLR_IRQ); 3522 3523 if (ifp0 != NULL && (ifp0->if_drv_flags & IFF_DRV_RUNNING) != 0 && 3524 !IFQ_DRV_IS_EMPTY(&ifp0->if_snd)) 3525 taskqueue_enqueue(taskqueue_fast, &sc_if0->msk_tx_task); 3526 if (ifp1 != NULL && (ifp1->if_drv_flags & IFF_DRV_RUNNING) != 0 && 3527 !IFQ_DRV_IS_EMPTY(&ifp1->if_snd)) 3528 taskqueue_enqueue(taskqueue_fast, &sc_if1->msk_tx_task); 3529 3530 if (domore > 0) { 3531 taskqueue_enqueue(sc->msk_tq, &sc->msk_int_task); 3532 MSK_UNLOCK(sc); 3533 return; 3534 } 3535 done: 3536 MSK_UNLOCK(sc); 3537 3538 /* Reenable interrupts. */ 3539 CSR_WRITE_4(sc, B0_Y2_SP_ICR, 2); 3540 } 3541 3542 static void 3543 msk_init(void *xsc) 3544 { 3545 struct msk_if_softc *sc_if = xsc; 3546 3547 MSK_IF_LOCK(sc_if); 3548 msk_init_locked(sc_if); 3549 MSK_IF_UNLOCK(sc_if); 3550 } 3551 3552 static void 3553 msk_init_locked(struct msk_if_softc *sc_if) 3554 { 3555 struct msk_softc *sc; 3556 struct ifnet *ifp; 3557 struct mii_data *mii; 3558 uint16_t eaddr[ETHER_ADDR_LEN / 2]; 3559 uint16_t gmac; 3560 int error, i; 3561 3562 MSK_IF_LOCK_ASSERT(sc_if); 3563 3564 ifp = sc_if->msk_ifp; 3565 sc = sc_if->msk_softc; 3566 mii = device_get_softc(sc_if->msk_miibus); 3567 3568 error = 0; 3569 /* Cancel pending I/O and free all Rx/Tx buffers. */ 3570 msk_stop(sc_if); 3571 3572 sc_if->msk_framesize = ifp->if_mtu + ETHER_HDR_LEN + 3573 ETHER_VLAN_ENCAP_LEN; 3574 if (sc_if->msk_framesize > MSK_MAX_FRAMELEN && 3575 sc_if->msk_softc->msk_hw_id == CHIP_ID_YUKON_EC_U) { 3576 /* 3577 * In Yukon EC Ultra, TSO & checksum offload is not 3578 * supported for jumbo frame. 3579 */ 3580 ifp->if_hwassist &= ~(MSK_CSUM_FEATURES | CSUM_TSO); 3581 ifp->if_capenable &= ~(IFCAP_TSO4 | IFCAP_TXCSUM); 3582 } 3583 3584 /* 3585 * Initialize GMAC first. 3586 * Without this initialization, Rx MAC did not work as expected 3587 * and Rx MAC garbled status LEs and it resulted in out-of-order 3588 * or duplicated frame delivery which in turn showed very poor 3589 * Rx performance.(I had to write a packet analysis code that 3590 * could be embeded in driver to diagnose this issue.) 3591 * I've spent almost 2 months to fix this issue. If I have had 3592 * datasheet for Yukon II I wouldn't have encountered this. :-( 3593 */ 3594 gmac = GM_GPCR_SPEED_100 | GM_GPCR_SPEED_1000 | GM_GPCR_DUP_FULL; 3595 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, gmac); 3596 3597 /* Dummy read the Interrupt Source Register. */ 3598 CSR_READ_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_SRC)); 3599 3600 /* Set MIB Clear Counter Mode. */ 3601 gmac = GMAC_READ_2(sc, sc_if->msk_port, GM_PHY_ADDR); 3602 GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac | GM_PAR_MIB_CLR); 3603 /* Read all MIB Counters with Clear Mode set. */ 3604 for (i = 0; i < GM_MIB_CNT_SIZE; i++) 3605 GMAC_READ_2(sc, sc_if->msk_port, GM_MIB_CNT_BASE + 8 * i); 3606 /* Clear MIB Clear Counter Mode. */ 3607 gmac &= ~GM_PAR_MIB_CLR; 3608 GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac); 3609 3610 /* Disable FCS. */ 3611 GMAC_WRITE_2(sc, sc_if->msk_port, GM_RX_CTRL, GM_RXCR_CRC_DIS); 3612 3613 /* Setup Transmit Control Register. */ 3614 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF)); 3615 3616 /* Setup Transmit Flow Control Register. */ 3617 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_FLOW_CTRL, 0xffff); 3618 3619 /* Setup Transmit Parameter Register. */ 3620 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_PARAM, 3621 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) | TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) | 3622 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) | TX_BACK_OFF_LIM(TX_BOF_LIM_DEF)); 3623 3624 gmac = DATA_BLIND_VAL(DATA_BLIND_DEF) | 3625 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF); 3626 3627 if (sc_if->msk_framesize > MSK_MAX_FRAMELEN) 3628 gmac |= GM_SMOD_JUMBO_ENA; 3629 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SERIAL_MODE, gmac); 3630 3631 /* Set station address. */ 3632 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN); 3633 for (i = 0; i < ETHER_ADDR_LEN /2; i++) 3634 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_1L + i * 4, 3635 eaddr[i]); 3636 for (i = 0; i < ETHER_ADDR_LEN /2; i++) 3637 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_2L + i * 4, 3638 eaddr[i]); 3639 3640 /* Disable interrupts for counter overflows. */ 3641 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_IRQ_MSK, 0); 3642 GMAC_WRITE_2(sc, sc_if->msk_port, GM_RX_IRQ_MSK, 0); 3643 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TR_IRQ_MSK, 0); 3644 3645 /* Configure Rx MAC FIFO. */ 3646 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), GMF_RST_SET); 3647 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), GMF_RST_CLR); 3648 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), 3649 GMF_OPER_ON | GMF_RX_F_FL_ON); 3650 3651 /* Set promiscuous mode. */ 3652 msk_setpromisc(sc_if); 3653 3654 /* Set multicast filter. */ 3655 msk_setmulti(sc_if); 3656 3657 /* Flush Rx MAC FIFO on any flow control or error. */ 3658 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_FL_MSK), 3659 GMR_FS_ANY_ERR); 3660 3661 /* Set Rx FIFO flush threshold to 64 bytes. */ 3662 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_FL_THR), 3663 RX_GMF_FL_THR_DEF); 3664 3665 /* Configure Tx MAC FIFO. */ 3666 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_RST_SET); 3667 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_RST_CLR); 3668 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_OPER_ON); 3669 3670 /* Configure hardware VLAN tag insertion/stripping. */ 3671 msk_setvlan(sc_if, ifp); 3672 3673 if (sc->msk_hw_id == CHIP_ID_YUKON_EC_U) { 3674 /* Set Rx Pause threshould. */ 3675 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, RX_GMF_LP_THR), 3676 MSK_ECU_LLPP); 3677 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, RX_GMF_UP_THR), 3678 MSK_ECU_ULPP); 3679 if (sc_if->msk_framesize > MSK_MAX_FRAMELEN) { 3680 /* 3681 * Set Tx GMAC FIFO Almost Empty Threshold. 3682 */ 3683 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_AE_THR), 3684 MSK_ECU_JUMBO_WM << 16 | MSK_ECU_AE_THR); 3685 /* Disable Store & Forward mode for Tx. */ 3686 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 3687 TX_JUMBO_ENA | TX_STFW_DIS); 3688 } else { 3689 /* Enable Store & Forward mode for Tx. */ 3690 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 3691 TX_JUMBO_DIS | TX_STFW_ENA); 3692 } 3693 } 3694 3695 /* 3696 * Disable Force Sync bit and Alloc bit in Tx RAM interface 3697 * arbiter as we don't use Sync Tx queue. 3698 */ 3699 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, TXA_CTRL), 3700 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC); 3701 /* Enable the RAM Interface Arbiter. */ 3702 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, TXA_CTRL), TXA_ENA_ARB); 3703 3704 /* Setup RAM buffer. */ 3705 msk_set_rambuffer(sc_if); 3706 3707 /* Disable Tx sync Queue. */ 3708 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txsq, RB_CTRL), RB_RST_SET); 3709 3710 /* Setup Tx Queue Bus Memory Interface. */ 3711 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_CLR_RESET); 3712 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_OPER_INIT); 3713 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_FIFO_OP_ON); 3714 CSR_WRITE_2(sc, Q_ADDR(sc_if->msk_txq, Q_WM), MSK_BMU_TX_WM); 3715 if (sc->msk_hw_id == CHIP_ID_YUKON_EC_U && 3716 sc->msk_hw_rev == CHIP_REV_YU_EC_U_A0) { 3717 /* Fix for Yukon-EC Ultra: set BMU FIFO level */ 3718 CSR_WRITE_2(sc, Q_ADDR(sc_if->msk_txq, Q_AL), MSK_ECU_TXFF_LEV); 3719 } 3720 3721 /* Setup Rx Queue Bus Memory Interface. */ 3722 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_CLR_RESET); 3723 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_OPER_INIT); 3724 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_FIFO_OP_ON); 3725 CSR_WRITE_2(sc, Q_ADDR(sc_if->msk_rxq, Q_WM), MSK_BMU_RX_WM); 3726 if (sc->msk_hw_id == CHIP_ID_YUKON_EC_U && 3727 sc->msk_hw_rev >= CHIP_REV_YU_EC_U_A1) { 3728 /* MAC Rx RAM Read is controlled by hardware. */ 3729 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_F), F_M_RX_RAM_DIS); 3730 } 3731 3732 msk_set_prefetch(sc, sc_if->msk_txq, 3733 sc_if->msk_rdata.msk_tx_ring_paddr, MSK_TX_RING_CNT - 1); 3734 msk_init_tx_ring(sc_if); 3735 3736 /* Disable Rx checksum offload and RSS hash. */ 3737 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), 3738 BMU_DIS_RX_CHKSUM | BMU_DIS_RX_RSS_HASH); 3739 if (sc_if->msk_framesize > (MCLBYTES - ETHER_HDR_LEN)) { 3740 msk_set_prefetch(sc, sc_if->msk_rxq, 3741 sc_if->msk_rdata.msk_jumbo_rx_ring_paddr, 3742 MSK_JUMBO_RX_RING_CNT - 1); 3743 error = msk_init_jumbo_rx_ring(sc_if); 3744 } else { 3745 msk_set_prefetch(sc, sc_if->msk_rxq, 3746 sc_if->msk_rdata.msk_rx_ring_paddr, 3747 MSK_RX_RING_CNT - 1); 3748 error = msk_init_rx_ring(sc_if); 3749 } 3750 if (error != 0) { 3751 device_printf(sc_if->msk_if_dev, 3752 "initialization failed: no memory for Rx buffers\n"); 3753 msk_stop(sc_if); 3754 return; 3755 } 3756 3757 /* Configure interrupt handling. */ 3758 if (sc_if->msk_port == MSK_PORT_A) { 3759 sc->msk_intrmask |= Y2_IS_PORT_A; 3760 sc->msk_intrhwemask |= Y2_HWE_L1_MASK; 3761 } else { 3762 sc->msk_intrmask |= Y2_IS_PORT_B; 3763 sc->msk_intrhwemask |= Y2_HWE_L2_MASK; 3764 } 3765 CSR_WRITE_4(sc, B0_HWE_IMSK, sc->msk_intrhwemask); 3766 CSR_READ_4(sc, B0_HWE_IMSK); 3767 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask); 3768 CSR_READ_4(sc, B0_IMSK); 3769 3770 sc_if->msk_link = 0; 3771 mii_mediachg(mii); 3772 3773 ifp->if_drv_flags |= IFF_DRV_RUNNING; 3774 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3775 3776 callout_reset(&sc_if->msk_tick_ch, hz, msk_tick, sc_if); 3777 } 3778 3779 static void 3780 msk_set_rambuffer(struct msk_if_softc *sc_if) 3781 { 3782 struct msk_softc *sc; 3783 int ltpp, utpp; 3784 3785 sc = sc_if->msk_softc; 3786 3787 /* Setup Rx Queue. */ 3788 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_RST_CLR); 3789 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_START), 3790 sc->msk_rxqstart[sc_if->msk_port] / 8); 3791 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_END), 3792 sc->msk_rxqend[sc_if->msk_port] / 8); 3793 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_WP), 3794 sc->msk_rxqstart[sc_if->msk_port] / 8); 3795 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_RP), 3796 sc->msk_rxqstart[sc_if->msk_port] / 8); 3797 3798 utpp = (sc->msk_rxqend[sc_if->msk_port] + 1 - 3799 sc->msk_rxqstart[sc_if->msk_port] - MSK_RB_ULPP) / 8; 3800 ltpp = (sc->msk_rxqend[sc_if->msk_port] + 1 - 3801 sc->msk_rxqstart[sc_if->msk_port] - MSK_RB_LLPP_B) / 8; 3802 if (sc->msk_rxqsize < MSK_MIN_RXQ_SIZE) 3803 ltpp += (MSK_RB_LLPP_B - MSK_RB_LLPP_S) / 8; 3804 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_RX_UTPP), utpp); 3805 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_RX_LTPP), ltpp); 3806 /* Set Rx priority(RB_RX_UTHP/RB_RX_LTHP) thresholds? */ 3807 3808 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_ENA_OP_MD); 3809 CSR_READ_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL)); 3810 3811 /* Setup Tx Queue. */ 3812 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_RST_CLR); 3813 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_START), 3814 sc->msk_txqstart[sc_if->msk_port] / 8); 3815 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_END), 3816 sc->msk_txqend[sc_if->msk_port] / 8); 3817 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_WP), 3818 sc->msk_txqstart[sc_if->msk_port] / 8); 3819 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_RP), 3820 sc->msk_txqstart[sc_if->msk_port] / 8); 3821 /* Enable Store & Forward for Tx side. */ 3822 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_ENA_STFWD); 3823 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_ENA_OP_MD); 3824 CSR_READ_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL)); 3825 } 3826 3827 static void 3828 msk_set_prefetch(struct msk_softc *sc, int qaddr, bus_addr_t addr, 3829 uint32_t count) 3830 { 3831 3832 /* Reset the prefetch unit. */ 3833 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG), 3834 PREF_UNIT_RST_SET); 3835 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG), 3836 PREF_UNIT_RST_CLR); 3837 /* Set LE base address. */ 3838 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_ADDR_LOW_REG), 3839 MSK_ADDR_LO(addr)); 3840 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_ADDR_HI_REG), 3841 MSK_ADDR_HI(addr)); 3842 /* Set the list last index. */ 3843 CSR_WRITE_2(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_LAST_IDX_REG), 3844 count); 3845 /* Turn on prefetch unit. */ 3846 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG), 3847 PREF_UNIT_OP_ON); 3848 /* Dummy read to ensure write. */ 3849 CSR_READ_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG)); 3850 } 3851 3852 static void 3853 msk_stop(struct msk_if_softc *sc_if) 3854 { 3855 struct msk_softc *sc; 3856 struct msk_txdesc *txd; 3857 struct msk_rxdesc *rxd; 3858 struct msk_rxdesc *jrxd; 3859 struct ifnet *ifp; 3860 uint32_t val; 3861 int i; 3862 3863 MSK_IF_LOCK_ASSERT(sc_if); 3864 sc = sc_if->msk_softc; 3865 ifp = sc_if->msk_ifp; 3866 3867 callout_stop(&sc_if->msk_tick_ch); 3868 sc_if->msk_watchdog_timer = 0; 3869 3870 /* Disable interrupts. */ 3871 if (sc_if->msk_port == MSK_PORT_A) { 3872 sc->msk_intrmask &= ~Y2_IS_PORT_A; 3873 sc->msk_intrhwemask &= ~Y2_HWE_L1_MASK; 3874 } else { 3875 sc->msk_intrmask &= ~Y2_IS_PORT_B; 3876 sc->msk_intrhwemask &= ~Y2_HWE_L2_MASK; 3877 } 3878 CSR_WRITE_4(sc, B0_HWE_IMSK, sc->msk_intrhwemask); 3879 CSR_READ_4(sc, B0_HWE_IMSK); 3880 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask); 3881 CSR_READ_4(sc, B0_IMSK); 3882 3883 /* Disable Tx/Rx MAC. */ 3884 val = GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL); 3885 val &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA); 3886 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, val); 3887 /* Read again to ensure writing. */ 3888 GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL); 3889 3890 /* Stop Tx BMU. */ 3891 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_STOP); 3892 val = CSR_READ_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR)); 3893 for (i = 0; i < MSK_TIMEOUT; i++) { 3894 if ((val & (BMU_STOP | BMU_IDLE)) == 0) { 3895 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), 3896 BMU_STOP); 3897 CSR_READ_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR)); 3898 } else 3899 break; 3900 DELAY(1); 3901 } 3902 if (i == MSK_TIMEOUT) 3903 device_printf(sc_if->msk_if_dev, "Tx BMU stop failed\n"); 3904 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), 3905 RB_RST_SET | RB_DIS_OP_MD); 3906 3907 /* Disable all GMAC interrupt. */ 3908 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_MSK), 0); 3909 /* Disable PHY interrupt. */ 3910 msk_phy_writereg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_MASK, 0); 3911 3912 /* Disable the RAM Interface Arbiter. */ 3913 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, TXA_CTRL), TXA_DIS_ARB); 3914 3915 /* Reset the PCI FIFO of the async Tx queue */ 3916 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), 3917 BMU_RST_SET | BMU_FIFO_RST); 3918 3919 /* Reset the Tx prefetch units. */ 3920 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(sc_if->msk_txq, PREF_UNIT_CTRL_REG), 3921 PREF_UNIT_RST_SET); 3922 3923 /* Reset the RAM Buffer async Tx queue. */ 3924 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_RST_SET); 3925 3926 /* Reset Tx MAC FIFO. */ 3927 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_RST_SET); 3928 /* Set Pause Off. */ 3929 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_PAUSE_OFF); 3930 3931 /* 3932 * The Rx Stop command will not work for Yukon-2 if the BMU does not 3933 * reach the end of packet and since we can't make sure that we have 3934 * incoming data, we must reset the BMU while it is not during a DMA 3935 * transfer. Since it is possible that the Rx path is still active, 3936 * the Rx RAM buffer will be stopped first, so any possible incoming 3937 * data will not trigger a DMA. After the RAM buffer is stopped, the 3938 * BMU is polled until any DMA in progress is ended and only then it 3939 * will be reset. 3940 */ 3941 3942 /* Disable the RAM Buffer receive queue. */ 3943 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_DIS_OP_MD); 3944 for (i = 0; i < MSK_TIMEOUT; i++) { 3945 if (CSR_READ_1(sc, RB_ADDR(sc_if->msk_rxq, Q_RSL)) == 3946 CSR_READ_1(sc, RB_ADDR(sc_if->msk_rxq, Q_RL))) 3947 break; 3948 DELAY(1); 3949 } 3950 if (i == MSK_TIMEOUT) 3951 device_printf(sc_if->msk_if_dev, "Rx BMU stop failed\n"); 3952 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), 3953 BMU_RST_SET | BMU_FIFO_RST); 3954 /* Reset the Rx prefetch unit. */ 3955 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_CTRL_REG), 3956 PREF_UNIT_RST_SET); 3957 /* Reset the RAM Buffer receive queue. */ 3958 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_RST_SET); 3959 /* Reset Rx MAC FIFO. */ 3960 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), GMF_RST_SET); 3961 3962 /* Free Rx and Tx mbufs still in the queues. */ 3963 for (i = 0; i < MSK_RX_RING_CNT; i++) { 3964 rxd = &sc_if->msk_cdata.msk_rxdesc[i]; 3965 if (rxd->rx_m != NULL) { 3966 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_tag, 3967 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 3968 bus_dmamap_unload(sc_if->msk_cdata.msk_rx_tag, 3969 rxd->rx_dmamap); 3970 m_freem(rxd->rx_m); 3971 rxd->rx_m = NULL; 3972 } 3973 } 3974 for (i = 0; i < MSK_JUMBO_RX_RING_CNT; i++) { 3975 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[i]; 3976 if (jrxd->rx_m != NULL) { 3977 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_tag, 3978 jrxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 3979 bus_dmamap_unload(sc_if->msk_cdata.msk_jumbo_rx_tag, 3980 jrxd->rx_dmamap); 3981 m_freem(jrxd->rx_m); 3982 jrxd->rx_m = NULL; 3983 } 3984 } 3985 for (i = 0; i < MSK_TX_RING_CNT; i++) { 3986 txd = &sc_if->msk_cdata.msk_txdesc[i]; 3987 if (txd->tx_m != NULL) { 3988 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_tag, 3989 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 3990 bus_dmamap_unload(sc_if->msk_cdata.msk_tx_tag, 3991 txd->tx_dmamap); 3992 m_freem(txd->tx_m); 3993 txd->tx_m = NULL; 3994 } 3995 } 3996 3997 /* 3998 * Mark the interface down. 3999 */ 4000 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 4001 sc_if->msk_link = 0; 4002 } 4003 4004 static int 4005 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 4006 { 4007 int error, value; 4008 4009 if (!arg1) 4010 return (EINVAL); 4011 value = *(int *)arg1; 4012 error = sysctl_handle_int(oidp, &value, 0, req); 4013 if (error || !req->newptr) 4014 return (error); 4015 if (value < low || value > high) 4016 return (EINVAL); 4017 *(int *)arg1 = value; 4018 4019 return (0); 4020 } 4021 4022 static int 4023 sysctl_hw_msk_proc_limit(SYSCTL_HANDLER_ARGS) 4024 { 4025 4026 return (sysctl_int_range(oidp, arg1, arg2, req, MSK_PROC_MIN, 4027 MSK_PROC_MAX)); 4028 } 4029