1 /****************************************************************************** 2 * 3 * Name : sky2.c 4 * Project: Gigabit Ethernet Driver for FreeBSD 5.x/6.x 5 * Version: $Revision: 1.23 $ 6 * Date : $Date: 2005/12/22 09:04:11 $ 7 * Purpose: Main driver source file 8 * 9 *****************************************************************************/ 10 11 /****************************************************************************** 12 * 13 * LICENSE: 14 * Copyright (C) Marvell International Ltd. and/or its affiliates 15 * 16 * The computer program files contained in this folder ("Files") 17 * are provided to you under the BSD-type license terms provided 18 * below, and any use of such Files and any derivative works 19 * thereof created by you shall be governed by the following terms 20 * and conditions: 21 * 22 * - Redistributions of source code must retain the above copyright 23 * notice, this list of conditions and the following disclaimer. 24 * - Redistributions in binary form must reproduce the above 25 * copyright notice, this list of conditions and the following 26 * disclaimer in the documentation and/or other materials provided 27 * with the distribution. 28 * - Neither the name of Marvell nor the names of its contributors 29 * may be used to endorse or promote products derived from this 30 * software without specific prior written permission. 31 * 32 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 33 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 34 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 35 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 36 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 37 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 38 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 39 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 40 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 41 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 42 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED 43 * OF THE POSSIBILITY OF SUCH DAMAGE. 44 * /LICENSE 45 * 46 *****************************************************************************/ 47 48 /*- 49 * Copyright (c) 1997, 1998, 1999, 2000 50 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 51 * 52 * Redistribution and use in source and binary forms, with or without 53 * modification, are permitted provided that the following conditions 54 * are met: 55 * 1. Redistributions of source code must retain the above copyright 56 * notice, this list of conditions and the following disclaimer. 57 * 2. Redistributions in binary form must reproduce the above copyright 58 * notice, this list of conditions and the following disclaimer in the 59 * documentation and/or other materials provided with the distribution. 60 * 3. All advertising materials mentioning features or use of this software 61 * must display the following acknowledgement: 62 * This product includes software developed by Bill Paul. 63 * 4. Neither the name of the author nor the names of any co-contributors 64 * may be used to endorse or promote products derived from this software 65 * without specific prior written permission. 66 * 67 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 68 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 69 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 70 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 71 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 72 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 73 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 74 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 75 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 76 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 77 * THE POSSIBILITY OF SUCH DAMAGE. 78 */ 79 /*- 80 * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu> 81 * 82 * Permission to use, copy, modify, and distribute this software for any 83 * purpose with or without fee is hereby granted, provided that the above 84 * copyright notice and this permission notice appear in all copies. 85 * 86 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 87 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 88 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 89 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 90 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 91 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 92 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 93 */ 94 95 /* 96 * Device driver for the Marvell Yukon II Ethernet controller. 97 * Due to lack of documentation, this driver is based on the code from 98 * sk(4) and Marvell's myk(4) driver for FreeBSD 5.x. 99 */ 100 101 #include <sys/cdefs.h> 102 __FBSDID("$FreeBSD$"); 103 104 #include <sys/param.h> 105 #include <sys/systm.h> 106 #include <sys/bus.h> 107 #include <sys/endian.h> 108 #include <sys/mbuf.h> 109 #include <sys/malloc.h> 110 #include <sys/kernel.h> 111 #include <sys/module.h> 112 #include <sys/socket.h> 113 #include <sys/sockio.h> 114 #include <sys/queue.h> 115 #include <sys/sysctl.h> 116 #include <sys/taskqueue.h> 117 118 #include <net/bpf.h> 119 #include <net/ethernet.h> 120 #include <net/if.h> 121 #include <net/if_arp.h> 122 #include <net/if_dl.h> 123 #include <net/if_media.h> 124 #include <net/if_types.h> 125 #include <net/if_vlan_var.h> 126 127 #include <netinet/in.h> 128 #include <netinet/in_systm.h> 129 #include <netinet/ip.h> 130 #include <netinet/tcp.h> 131 #include <netinet/udp.h> 132 133 #include <machine/bus.h> 134 #include <machine/in_cksum.h> 135 #include <machine/resource.h> 136 #include <sys/rman.h> 137 138 #include <dev/mii/mii.h> 139 #include <dev/mii/miivar.h> 140 #include <dev/mii/brgphyreg.h> 141 142 #include <dev/pci/pcireg.h> 143 #include <dev/pci/pcivar.h> 144 145 #include <dev/msk/if_mskreg.h> 146 147 MODULE_DEPEND(msk, pci, 1, 1, 1); 148 MODULE_DEPEND(msk, ether, 1, 1, 1); 149 MODULE_DEPEND(msk, miibus, 1, 1, 1); 150 151 /* "device miibus" required. See GENERIC if you get errors here. */ 152 #include "miibus_if.h" 153 154 /* Tunables. */ 155 static int msi_disable = 0; 156 TUNABLE_INT("hw.msk.msi_disable", &msi_disable); 157 158 #define MSK_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 159 160 /* 161 * Devices supported by this driver. 162 */ 163 static struct msk_product { 164 uint16_t msk_vendorid; 165 uint16_t msk_deviceid; 166 const char *msk_name; 167 } msk_products[] = { 168 { VENDORID_SK, DEVICEID_SK_YUKON2, 169 "SK-9Sxx Gigabit Ethernet" }, 170 { VENDORID_SK, DEVICEID_SK_YUKON2_EXPR, 171 "SK-9Exx Gigabit Ethernet"}, 172 { VENDORID_MARVELL, DEVICEID_MRVL_8021CU, 173 "Marvell Yukon 88E8021CU Gigabit Ethernet" }, 174 { VENDORID_MARVELL, DEVICEID_MRVL_8021X, 175 "Marvell Yukon 88E8021 SX/LX Gigabit Ethernet" }, 176 { VENDORID_MARVELL, DEVICEID_MRVL_8022CU, 177 "Marvell Yukon 88E8022CU Gigabit Ethernet" }, 178 { VENDORID_MARVELL, DEVICEID_MRVL_8022X, 179 "Marvell Yukon 88E8022 SX/LX Gigabit Ethernet" }, 180 { VENDORID_MARVELL, DEVICEID_MRVL_8061CU, 181 "Marvell Yukon 88E8061CU Gigabit Ethernet" }, 182 { VENDORID_MARVELL, DEVICEID_MRVL_8061X, 183 "Marvell Yukon 88E8061 SX/LX Gigabit Ethernet" }, 184 { VENDORID_MARVELL, DEVICEID_MRVL_8062CU, 185 "Marvell Yukon 88E8062CU Gigabit Ethernet" }, 186 { VENDORID_MARVELL, DEVICEID_MRVL_8062X, 187 "Marvell Yukon 88E8062 SX/LX Gigabit Ethernet" }, 188 { VENDORID_MARVELL, DEVICEID_MRVL_8035, 189 "Marvell Yukon 88E8035 Gigabit Ethernet" }, 190 { VENDORID_MARVELL, DEVICEID_MRVL_8036, 191 "Marvell Yukon 88E8036 Gigabit Ethernet" }, 192 { VENDORID_MARVELL, DEVICEID_MRVL_8038, 193 "Marvell Yukon 88E8038 Gigabit Ethernet" }, 194 { VENDORID_MARVELL, DEVICEID_MRVL_4361, 195 "Marvell Yukon 88E8050 Gigabit Ethernet" }, 196 { VENDORID_MARVELL, DEVICEID_MRVL_4360, 197 "Marvell Yukon 88E8052 Gigabit Ethernet" }, 198 { VENDORID_MARVELL, DEVICEID_MRVL_4362, 199 "Marvell Yukon 88E8053 Gigabit Ethernet" }, 200 { VENDORID_MARVELL, DEVICEID_MRVL_4363, 201 "Marvell Yukon 88E8055 Gigabit Ethernet" }, 202 { VENDORID_MARVELL, DEVICEID_MRVL_4364, 203 "Marvell Yukon 88E8056 Gigabit Ethernet" }, 204 { VENDORID_DLINK, DEVICEID_DLINK_DGE550SX, 205 "D-Link 550SX Gigabit Ethernet" }, 206 { VENDORID_DLINK, DEVICEID_DLINK_DGE560T, 207 "D-Link 560T Gigabit Ethernet" } 208 }; 209 210 static const char *model_name[] = { 211 "Yukon XL", 212 "Yukon EC Ultra", 213 "Yukon Unknown", 214 "Yukon EC", 215 "Yukon FE" 216 }; 217 218 static int mskc_probe(device_t); 219 static int mskc_attach(device_t); 220 static int mskc_detach(device_t); 221 static void mskc_shutdown(device_t); 222 static int mskc_setup_rambuffer(struct msk_softc *); 223 static int mskc_suspend(device_t); 224 static int mskc_resume(device_t); 225 static void mskc_reset(struct msk_softc *); 226 227 static int msk_probe(device_t); 228 static int msk_attach(device_t); 229 static int msk_detach(device_t); 230 231 static void msk_tick(void *); 232 static int msk_intr(void *); 233 static void msk_int_task(void *, int); 234 static void msk_intr_phy(struct msk_if_softc *); 235 static void msk_intr_gmac(struct msk_if_softc *); 236 static __inline void msk_rxput(struct msk_if_softc *); 237 static int msk_handle_events(struct msk_softc *); 238 static void msk_handle_hwerr(struct msk_if_softc *, uint32_t); 239 static void msk_intr_hwerr(struct msk_softc *); 240 static void msk_rxeof(struct msk_if_softc *, uint32_t, int); 241 static void msk_jumbo_rxeof(struct msk_if_softc *, uint32_t, int); 242 static void msk_txeof(struct msk_if_softc *, int); 243 static struct mbuf *msk_defrag(struct mbuf *, int, int); 244 static int msk_encap(struct msk_if_softc *, struct mbuf **); 245 static void msk_tx_task(void *, int); 246 static void msk_start(struct ifnet *); 247 static int msk_ioctl(struct ifnet *, u_long, caddr_t); 248 static void msk_set_prefetch(struct msk_softc *, int, bus_addr_t, uint32_t); 249 static void msk_set_rambuffer(struct msk_if_softc *); 250 static void msk_init(void *); 251 static void msk_init_locked(struct msk_if_softc *); 252 static void msk_stop(struct msk_if_softc *); 253 static void msk_watchdog(struct msk_if_softc *); 254 static int msk_mediachange(struct ifnet *); 255 static void msk_mediastatus(struct ifnet *, struct ifmediareq *); 256 static void msk_phy_power(struct msk_softc *, int); 257 static void msk_dmamap_cb(void *, bus_dma_segment_t *, int, int); 258 static int msk_status_dma_alloc(struct msk_softc *); 259 static void msk_status_dma_free(struct msk_softc *); 260 static int msk_txrx_dma_alloc(struct msk_if_softc *); 261 static void msk_txrx_dma_free(struct msk_if_softc *); 262 static void *msk_jalloc(struct msk_if_softc *); 263 static void msk_jfree(void *, void *); 264 static int msk_init_rx_ring(struct msk_if_softc *); 265 static int msk_init_jumbo_rx_ring(struct msk_if_softc *); 266 static void msk_init_tx_ring(struct msk_if_softc *); 267 static __inline void msk_discard_rxbuf(struct msk_if_softc *, int); 268 static __inline void msk_discard_jumbo_rxbuf(struct msk_if_softc *, int); 269 static int msk_newbuf(struct msk_if_softc *, int); 270 static int msk_jumbo_newbuf(struct msk_if_softc *, int); 271 272 static int msk_phy_readreg(struct msk_if_softc *, int, int); 273 static int msk_phy_writereg(struct msk_if_softc *, int, int, int); 274 static int msk_miibus_readreg(device_t, int, int); 275 static int msk_miibus_writereg(device_t, int, int, int); 276 static void msk_miibus_statchg(device_t); 277 static void msk_link_task(void *, int); 278 279 static void msk_setmulti(struct msk_if_softc *); 280 static void msk_setvlan(struct msk_if_softc *, struct ifnet *); 281 static void msk_setpromisc(struct msk_if_softc *); 282 283 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int); 284 static int sysctl_hw_msk_proc_limit(SYSCTL_HANDLER_ARGS); 285 286 static device_method_t mskc_methods[] = { 287 /* Device interface */ 288 DEVMETHOD(device_probe, mskc_probe), 289 DEVMETHOD(device_attach, mskc_attach), 290 DEVMETHOD(device_detach, mskc_detach), 291 DEVMETHOD(device_suspend, mskc_suspend), 292 DEVMETHOD(device_resume, mskc_resume), 293 DEVMETHOD(device_shutdown, mskc_shutdown), 294 295 /* bus interface */ 296 DEVMETHOD(bus_print_child, bus_generic_print_child), 297 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 298 299 { NULL, NULL } 300 }; 301 302 static driver_t mskc_driver = { 303 "mskc", 304 mskc_methods, 305 sizeof(struct msk_softc) 306 }; 307 308 static devclass_t mskc_devclass; 309 310 static device_method_t msk_methods[] = { 311 /* Device interface */ 312 DEVMETHOD(device_probe, msk_probe), 313 DEVMETHOD(device_attach, msk_attach), 314 DEVMETHOD(device_detach, msk_detach), 315 DEVMETHOD(device_shutdown, bus_generic_shutdown), 316 317 /* bus interface */ 318 DEVMETHOD(bus_print_child, bus_generic_print_child), 319 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 320 321 /* MII interface */ 322 DEVMETHOD(miibus_readreg, msk_miibus_readreg), 323 DEVMETHOD(miibus_writereg, msk_miibus_writereg), 324 DEVMETHOD(miibus_statchg, msk_miibus_statchg), 325 326 { NULL, NULL } 327 }; 328 329 static driver_t msk_driver = { 330 "msk", 331 msk_methods, 332 sizeof(struct msk_if_softc) 333 }; 334 335 static devclass_t msk_devclass; 336 337 DRIVER_MODULE(mskc, pci, mskc_driver, mskc_devclass, 0, 0); 338 DRIVER_MODULE(msk, mskc, msk_driver, msk_devclass, 0, 0); 339 DRIVER_MODULE(miibus, msk, miibus_driver, miibus_devclass, 0, 0); 340 341 static struct resource_spec msk_res_spec_io[] = { 342 { SYS_RES_IOPORT, PCIR_BAR(1), RF_ACTIVE }, 343 { -1, 0, 0 } 344 }; 345 346 static struct resource_spec msk_res_spec_mem[] = { 347 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 348 { -1, 0, 0 } 349 }; 350 351 static struct resource_spec msk_irq_spec_legacy[] = { 352 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 353 { -1, 0, 0 } 354 }; 355 356 static struct resource_spec msk_irq_spec_msi[] = { 357 { SYS_RES_IRQ, 1, RF_ACTIVE }, 358 { SYS_RES_IRQ, 2, RF_ACTIVE }, 359 { -1, 0, 0 } 360 }; 361 362 static int 363 msk_miibus_readreg(device_t dev, int phy, int reg) 364 { 365 struct msk_if_softc *sc_if; 366 367 sc_if = device_get_softc(dev); 368 369 return (msk_phy_readreg(sc_if, phy, reg)); 370 } 371 372 static int 373 msk_phy_readreg(struct msk_if_softc *sc_if, int phy, int reg) 374 { 375 struct msk_softc *sc; 376 int i, val; 377 378 sc = sc_if->msk_softc; 379 380 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SMI_CTRL, 381 GM_SMI_CT_PHY_AD(phy) | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD); 382 383 for (i = 0; i < MSK_TIMEOUT; i++) { 384 DELAY(1); 385 val = GMAC_READ_2(sc, sc_if->msk_port, GM_SMI_CTRL); 386 if ((val & GM_SMI_CT_RD_VAL) != 0) { 387 val = GMAC_READ_2(sc, sc_if->msk_port, GM_SMI_DATA); 388 break; 389 } 390 } 391 392 if (i == MSK_TIMEOUT) { 393 if_printf(sc_if->msk_ifp, "phy failed to come ready\n"); 394 val = 0; 395 } 396 397 return (val); 398 } 399 400 static int 401 msk_miibus_writereg(device_t dev, int phy, int reg, int val) 402 { 403 struct msk_if_softc *sc_if; 404 405 sc_if = device_get_softc(dev); 406 407 return (msk_phy_writereg(sc_if, phy, reg, val)); 408 } 409 410 static int 411 msk_phy_writereg(struct msk_if_softc *sc_if, int phy, int reg, int val) 412 { 413 struct msk_softc *sc; 414 int i; 415 416 sc = sc_if->msk_softc; 417 418 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SMI_DATA, val); 419 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SMI_CTRL, 420 GM_SMI_CT_PHY_AD(phy) | GM_SMI_CT_REG_AD(reg)); 421 for (i = 0; i < MSK_TIMEOUT; i++) { 422 DELAY(1); 423 if ((GMAC_READ_2(sc, sc_if->msk_port, GM_SMI_CTRL) & 424 GM_SMI_CT_BUSY) == 0) 425 break; 426 } 427 if (i == MSK_TIMEOUT) 428 if_printf(sc_if->msk_ifp, "phy write timeout\n"); 429 430 return (0); 431 } 432 433 static void 434 msk_miibus_statchg(device_t dev) 435 { 436 struct msk_if_softc *sc_if; 437 438 sc_if = device_get_softc(dev); 439 taskqueue_enqueue(taskqueue_swi, &sc_if->msk_link_task); 440 } 441 442 static void 443 msk_link_task(void *arg, int pending) 444 { 445 struct msk_softc *sc; 446 struct msk_if_softc *sc_if; 447 struct mii_data *mii; 448 struct ifnet *ifp; 449 uint32_t gmac; 450 451 sc_if = (struct msk_if_softc *)arg; 452 sc = sc_if->msk_softc; 453 454 MSK_IF_LOCK(sc_if); 455 456 mii = device_get_softc(sc_if->msk_miibus); 457 ifp = sc_if->msk_ifp; 458 if (mii == NULL || ifp == NULL) { 459 MSK_IF_UNLOCK(sc_if); 460 return; 461 } 462 463 if (mii->mii_media_status & IFM_ACTIVE) { 464 if (IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 465 sc_if->msk_link = 1; 466 } else 467 sc_if->msk_link = 0; 468 469 if (sc_if->msk_link != 0) { 470 /* Enable Tx FIFO Underrun. */ 471 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_MSK), 472 GM_IS_TX_FF_UR | GM_IS_RX_FF_OR); 473 /* 474 * Because mii(4) notify msk(4) that it detected link status 475 * change, there is no need to enable automatic 476 * speed/flow-control/duplex updates. 477 */ 478 gmac = GM_GPCR_AU_ALL_DIS; 479 switch (IFM_SUBTYPE(mii->mii_media_active)) { 480 case IFM_1000_SX: 481 case IFM_1000_T: 482 gmac |= GM_GPCR_SPEED_1000; 483 break; 484 case IFM_100_TX: 485 gmac |= GM_GPCR_SPEED_100; 486 break; 487 case IFM_10_T: 488 break; 489 } 490 491 if (((mii->mii_media_active & IFM_GMASK) & IFM_FDX) != 0) 492 gmac |= GM_GPCR_DUP_FULL; 493 /* Disable Rx flow control. */ 494 if (((mii->mii_media_active & IFM_GMASK) & IFM_FLAG0) == 0) 495 gmac |= GM_GPCR_FC_RX_DIS; 496 /* Disable Tx flow control. */ 497 if (((mii->mii_media_active & IFM_GMASK) & IFM_FLAG1) == 0) 498 gmac |= GM_GPCR_FC_TX_DIS; 499 gmac |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA; 500 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, gmac); 501 /* Read again to ensure writing. */ 502 GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL); 503 504 gmac = GMC_PAUSE_ON; 505 if (((mii->mii_media_active & IFM_GMASK) & 506 (IFM_FLAG0 | IFM_FLAG1)) == 0) 507 gmac = GMC_PAUSE_OFF; 508 /* Diable pause for 10/100 Mbps in half-duplex mode. */ 509 if ((((mii->mii_media_active & IFM_GMASK) & IFM_FDX) == 0) && 510 (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX || 511 IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T)) 512 gmac = GMC_PAUSE_OFF; 513 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), gmac); 514 515 /* Enable PHY interrupt for FIFO underrun/overflow. */ 516 if (sc->msk_marvell_phy) 517 msk_phy_writereg(sc_if, PHY_ADDR_MARV, 518 PHY_MARV_INT_MASK, PHY_M_IS_FIFO_ERROR); 519 } else { 520 /* 521 * Link state changed to down. 522 * Disable PHY interrupts. 523 */ 524 if (sc->msk_marvell_phy) 525 msk_phy_writereg(sc_if, PHY_ADDR_MARV, 526 PHY_MARV_INT_MASK, 0); 527 /* Disable Rx/Tx MAC. */ 528 gmac = GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL); 529 gmac &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA); 530 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, gmac); 531 /* Read again to ensure writing. */ 532 GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL); 533 } 534 535 MSK_IF_UNLOCK(sc_if); 536 } 537 538 static void 539 msk_setmulti(struct msk_if_softc *sc_if) 540 { 541 struct msk_softc *sc; 542 struct ifnet *ifp; 543 struct ifmultiaddr *ifma; 544 uint32_t mchash[2]; 545 uint32_t crc; 546 uint16_t mode; 547 548 sc = sc_if->msk_softc; 549 550 MSK_IF_LOCK_ASSERT(sc_if); 551 552 ifp = sc_if->msk_ifp; 553 554 bzero(mchash, sizeof(mchash)); 555 mode = GMAC_READ_2(sc, sc_if->msk_port, GM_RX_CTRL); 556 mode |= GM_RXCR_UCF_ENA; 557 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 558 if ((ifp->if_flags & IFF_PROMISC) != 0) 559 mode &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA); 560 else if ((ifp->if_flags & IFF_ALLMULTI) != 0) { 561 mchash[0] = 0xffff; 562 mchash[1] = 0xffff; 563 } 564 } else { 565 IF_ADDR_LOCK(ifp); 566 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 567 if (ifma->ifma_addr->sa_family != AF_LINK) 568 continue; 569 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *) 570 ifma->ifma_addr), ETHER_ADDR_LEN); 571 /* Just want the 6 least significant bits. */ 572 crc &= 0x3f; 573 /* Set the corresponding bit in the hash table. */ 574 mchash[crc >> 5] |= 1 << (crc & 0x1f); 575 } 576 IF_ADDR_UNLOCK(ifp); 577 mode |= GM_RXCR_MCF_ENA; 578 } 579 580 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H1, 581 mchash[0] & 0xffff); 582 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H2, 583 (mchash[0] >> 16) & 0xffff); 584 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H3, 585 mchash[1] & 0xffff); 586 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H4, 587 (mchash[1] >> 16) & 0xffff); 588 GMAC_WRITE_2(sc, sc_if->msk_port, GM_RX_CTRL, mode); 589 } 590 591 static void 592 msk_setvlan(struct msk_if_softc *sc_if, struct ifnet *ifp) 593 { 594 struct msk_softc *sc; 595 596 sc = sc_if->msk_softc; 597 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) { 598 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), 599 RX_VLAN_STRIP_ON); 600 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 601 TX_VLAN_TAG_ON); 602 } else { 603 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), 604 RX_VLAN_STRIP_OFF); 605 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 606 TX_VLAN_TAG_OFF); 607 } 608 } 609 610 static void 611 msk_setpromisc(struct msk_if_softc *sc_if) 612 { 613 struct msk_softc *sc; 614 struct ifnet *ifp; 615 uint16_t mode; 616 617 MSK_IF_LOCK_ASSERT(sc_if); 618 619 sc = sc_if->msk_softc; 620 ifp = sc_if->msk_ifp; 621 622 mode = GMAC_READ_2(sc, sc_if->msk_port, GM_RX_CTRL); 623 if (ifp->if_flags & IFF_PROMISC) 624 mode &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA); 625 else 626 mode |= (GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA); 627 GMAC_WRITE_2(sc, sc_if->msk_port, GM_RX_CTRL, mode); 628 } 629 630 static int 631 msk_init_rx_ring(struct msk_if_softc *sc_if) 632 { 633 struct msk_ring_data *rd; 634 struct msk_rxdesc *rxd; 635 int i, prod; 636 637 MSK_IF_LOCK_ASSERT(sc_if); 638 639 sc_if->msk_cdata.msk_rx_cons = 0; 640 sc_if->msk_cdata.msk_rx_prod = 0; 641 sc_if->msk_cdata.msk_rx_putwm = MSK_PUT_WM; 642 643 rd = &sc_if->msk_rdata; 644 bzero(rd->msk_rx_ring, sizeof(struct msk_rx_desc) * MSK_RX_RING_CNT); 645 prod = sc_if->msk_cdata.msk_rx_prod; 646 for (i = 0; i < MSK_RX_RING_CNT; i++) { 647 rxd = &sc_if->msk_cdata.msk_rxdesc[prod]; 648 rxd->rx_m = NULL; 649 rxd->rx_le = &rd->msk_rx_ring[prod]; 650 if (msk_newbuf(sc_if, prod) != 0) 651 return (ENOBUFS); 652 MSK_INC(prod, MSK_RX_RING_CNT); 653 } 654 655 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_ring_tag, 656 sc_if->msk_cdata.msk_rx_ring_map, 657 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 658 659 /* Update prefetch unit. */ 660 sc_if->msk_cdata.msk_rx_prod = MSK_RX_RING_CNT - 1; 661 CSR_WRITE_2(sc_if->msk_softc, 662 Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_PUT_IDX_REG), 663 sc_if->msk_cdata.msk_rx_prod); 664 665 return (0); 666 } 667 668 static int 669 msk_init_jumbo_rx_ring(struct msk_if_softc *sc_if) 670 { 671 struct msk_ring_data *rd; 672 struct msk_rxdesc *rxd; 673 int i, prod; 674 675 MSK_IF_LOCK_ASSERT(sc_if); 676 677 sc_if->msk_cdata.msk_rx_cons = 0; 678 sc_if->msk_cdata.msk_rx_prod = 0; 679 sc_if->msk_cdata.msk_rx_putwm = MSK_PUT_WM; 680 681 rd = &sc_if->msk_rdata; 682 bzero(rd->msk_jumbo_rx_ring, 683 sizeof(struct msk_rx_desc) * MSK_JUMBO_RX_RING_CNT); 684 prod = sc_if->msk_cdata.msk_rx_prod; 685 for (i = 0; i < MSK_JUMBO_RX_RING_CNT; i++) { 686 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[prod]; 687 rxd->rx_m = NULL; 688 rxd->rx_le = &rd->msk_jumbo_rx_ring[prod]; 689 if (msk_jumbo_newbuf(sc_if, prod) != 0) 690 return (ENOBUFS); 691 MSK_INC(prod, MSK_JUMBO_RX_RING_CNT); 692 } 693 694 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 695 sc_if->msk_cdata.msk_jumbo_rx_ring_map, 696 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 697 698 sc_if->msk_cdata.msk_rx_prod = MSK_JUMBO_RX_RING_CNT - 1; 699 CSR_WRITE_2(sc_if->msk_softc, 700 Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_PUT_IDX_REG), 701 sc_if->msk_cdata.msk_rx_prod); 702 703 return (0); 704 } 705 706 static void 707 msk_init_tx_ring(struct msk_if_softc *sc_if) 708 { 709 struct msk_ring_data *rd; 710 struct msk_txdesc *txd; 711 int i; 712 713 sc_if->msk_cdata.msk_tso_mtu = 0; 714 sc_if->msk_cdata.msk_tx_prod = 0; 715 sc_if->msk_cdata.msk_tx_cons = 0; 716 sc_if->msk_cdata.msk_tx_cnt = 0; 717 718 rd = &sc_if->msk_rdata; 719 bzero(rd->msk_tx_ring, sizeof(struct msk_tx_desc) * MSK_TX_RING_CNT); 720 for (i = 0; i < MSK_TX_RING_CNT; i++) { 721 txd = &sc_if->msk_cdata.msk_txdesc[i]; 722 txd->tx_m = NULL; 723 txd->tx_le = &rd->msk_tx_ring[i]; 724 } 725 726 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_ring_tag, 727 sc_if->msk_cdata.msk_tx_ring_map, 728 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 729 } 730 731 static __inline void 732 msk_discard_rxbuf(struct msk_if_softc *sc_if, int idx) 733 { 734 struct msk_rx_desc *rx_le; 735 struct msk_rxdesc *rxd; 736 struct mbuf *m; 737 738 rxd = &sc_if->msk_cdata.msk_rxdesc[idx]; 739 m = rxd->rx_m; 740 rx_le = rxd->rx_le; 741 rx_le->msk_control = htole32(m->m_len | OP_PACKET | HW_OWNER); 742 } 743 744 static __inline void 745 msk_discard_jumbo_rxbuf(struct msk_if_softc *sc_if, int idx) 746 { 747 struct msk_rx_desc *rx_le; 748 struct msk_rxdesc *rxd; 749 struct mbuf *m; 750 751 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[idx]; 752 m = rxd->rx_m; 753 rx_le = rxd->rx_le; 754 rx_le->msk_control = htole32(m->m_len | OP_PACKET | HW_OWNER); 755 } 756 757 static int 758 msk_newbuf(struct msk_if_softc *sc_if, int idx) 759 { 760 struct msk_rx_desc *rx_le; 761 struct msk_rxdesc *rxd; 762 struct mbuf *m; 763 bus_dma_segment_t segs[1]; 764 bus_dmamap_t map; 765 int nsegs; 766 767 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 768 if (m == NULL) 769 return (ENOBUFS); 770 771 m->m_len = m->m_pkthdr.len = MCLBYTES; 772 m_adj(m, ETHER_ALIGN); 773 774 if (bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_rx_tag, 775 sc_if->msk_cdata.msk_rx_sparemap, m, segs, &nsegs, 776 BUS_DMA_NOWAIT) != 0) { 777 m_freem(m); 778 return (ENOBUFS); 779 } 780 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 781 782 rxd = &sc_if->msk_cdata.msk_rxdesc[idx]; 783 if (rxd->rx_m != NULL) { 784 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_tag, rxd->rx_dmamap, 785 BUS_DMASYNC_POSTREAD); 786 bus_dmamap_unload(sc_if->msk_cdata.msk_rx_tag, rxd->rx_dmamap); 787 } 788 map = rxd->rx_dmamap; 789 rxd->rx_dmamap = sc_if->msk_cdata.msk_rx_sparemap; 790 sc_if->msk_cdata.msk_rx_sparemap = map; 791 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_tag, rxd->rx_dmamap, 792 BUS_DMASYNC_PREREAD); 793 rxd->rx_m = m; 794 rx_le = rxd->rx_le; 795 rx_le->msk_addr = htole32(MSK_ADDR_LO(segs[0].ds_addr)); 796 rx_le->msk_control = 797 htole32(segs[0].ds_len | OP_PACKET | HW_OWNER); 798 799 return (0); 800 } 801 802 static int 803 msk_jumbo_newbuf(struct msk_if_softc *sc_if, int idx) 804 { 805 struct msk_rx_desc *rx_le; 806 struct msk_rxdesc *rxd; 807 struct mbuf *m; 808 bus_dma_segment_t segs[1]; 809 bus_dmamap_t map; 810 int nsegs; 811 void *buf; 812 813 MGETHDR(m, M_DONTWAIT, MT_DATA); 814 if (m == NULL) 815 return (ENOBUFS); 816 buf = msk_jalloc(sc_if); 817 if (buf == NULL) { 818 m_freem(m); 819 return (ENOBUFS); 820 } 821 /* Attach the buffer to the mbuf. */ 822 MEXTADD(m, buf, MSK_JLEN, msk_jfree, (struct msk_if_softc *)sc_if, 0, 823 EXT_NET_DRV); 824 if ((m->m_flags & M_EXT) == 0) { 825 m_freem(m); 826 return (ENOBUFS); 827 } 828 m->m_pkthdr.len = m->m_len = MSK_JLEN; 829 m_adj(m, ETHER_ALIGN); 830 831 if (bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_jumbo_rx_tag, 832 sc_if->msk_cdata.msk_jumbo_rx_sparemap, m, segs, &nsegs, 833 BUS_DMA_NOWAIT) != 0) { 834 m_freem(m); 835 return (ENOBUFS); 836 } 837 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 838 839 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[idx]; 840 if (rxd->rx_m != NULL) { 841 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_tag, 842 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 843 bus_dmamap_unload(sc_if->msk_cdata.msk_jumbo_rx_tag, 844 rxd->rx_dmamap); 845 } 846 map = rxd->rx_dmamap; 847 rxd->rx_dmamap = sc_if->msk_cdata.msk_jumbo_rx_sparemap; 848 sc_if->msk_cdata.msk_jumbo_rx_sparemap = map; 849 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_tag, rxd->rx_dmamap, 850 BUS_DMASYNC_PREREAD); 851 rxd->rx_m = m; 852 rx_le = rxd->rx_le; 853 rx_le->msk_addr = htole32(MSK_ADDR_LO(segs[0].ds_addr)); 854 rx_le->msk_control = 855 htole32(segs[0].ds_len | OP_PACKET | HW_OWNER); 856 857 return (0); 858 } 859 860 /* 861 * Set media options. 862 */ 863 static int 864 msk_mediachange(struct ifnet *ifp) 865 { 866 struct msk_if_softc *sc_if; 867 struct mii_data *mii; 868 869 sc_if = ifp->if_softc; 870 871 MSK_IF_LOCK(sc_if); 872 mii = device_get_softc(sc_if->msk_miibus); 873 mii_mediachg(mii); 874 MSK_IF_UNLOCK(sc_if); 875 876 return (0); 877 } 878 879 /* 880 * Report current media status. 881 */ 882 static void 883 msk_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 884 { 885 struct msk_if_softc *sc_if; 886 struct mii_data *mii; 887 888 sc_if = ifp->if_softc; 889 MSK_IF_LOCK(sc_if); 890 mii = device_get_softc(sc_if->msk_miibus); 891 892 mii_pollstat(mii); 893 MSK_IF_UNLOCK(sc_if); 894 ifmr->ifm_active = mii->mii_media_active; 895 ifmr->ifm_status = mii->mii_media_status; 896 } 897 898 static int 899 msk_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 900 { 901 struct msk_if_softc *sc_if; 902 struct ifreq *ifr; 903 struct mii_data *mii; 904 int error, mask; 905 906 sc_if = ifp->if_softc; 907 ifr = (struct ifreq *)data; 908 error = 0; 909 910 switch(command) { 911 case SIOCSIFMTU: 912 if (ifr->ifr_mtu > MSK_JUMBO_MTU || ifr->ifr_mtu < ETHERMIN) { 913 error = EINVAL; 914 break; 915 } 916 if (sc_if->msk_softc->msk_hw_id == CHIP_ID_YUKON_EC_U && 917 ifr->ifr_mtu > MSK_MAX_FRAMELEN) { 918 error = EINVAL; 919 break; 920 } 921 MSK_IF_LOCK(sc_if); 922 ifp->if_mtu = ifr->ifr_mtu; 923 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 924 msk_init_locked(sc_if); 925 MSK_IF_UNLOCK(sc_if); 926 break; 927 case SIOCSIFFLAGS: 928 MSK_IF_LOCK(sc_if); 929 if ((ifp->if_flags & IFF_UP) != 0) { 930 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 931 if (((ifp->if_flags ^ sc_if->msk_if_flags) 932 & IFF_PROMISC) != 0) { 933 msk_setpromisc(sc_if); 934 msk_setmulti(sc_if); 935 } 936 } else { 937 if (sc_if->msk_detach == 0) 938 msk_init_locked(sc_if); 939 } 940 } else { 941 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 942 msk_stop(sc_if); 943 } 944 sc_if->msk_if_flags = ifp->if_flags; 945 MSK_IF_UNLOCK(sc_if); 946 break; 947 case SIOCADDMULTI: 948 case SIOCDELMULTI: 949 MSK_IF_LOCK(sc_if); 950 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 951 msk_setmulti(sc_if); 952 MSK_IF_UNLOCK(sc_if); 953 break; 954 case SIOCGIFMEDIA: 955 case SIOCSIFMEDIA: 956 mii = device_get_softc(sc_if->msk_miibus); 957 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 958 break; 959 case SIOCSIFCAP: 960 MSK_IF_LOCK(sc_if); 961 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 962 if ((mask & IFCAP_TXCSUM) != 0) { 963 ifp->if_capenable ^= IFCAP_TXCSUM; 964 if ((IFCAP_TXCSUM & ifp->if_capenable) != 0 && 965 (IFCAP_TXCSUM & ifp->if_capabilities) != 0) 966 ifp->if_hwassist |= MSK_CSUM_FEATURES; 967 else 968 ifp->if_hwassist &= ~MSK_CSUM_FEATURES; 969 } 970 if ((mask & IFCAP_VLAN_HWTAGGING) != 0) { 971 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 972 msk_setvlan(sc_if, ifp); 973 } 974 975 if ((mask & IFCAP_TSO4) != 0) { 976 ifp->if_capenable ^= IFCAP_TSO4; 977 if ((IFCAP_TSO4 & ifp->if_capenable) != 0 && 978 (IFCAP_TSO4 & ifp->if_capabilities) != 0) 979 ifp->if_hwassist |= CSUM_TSO; 980 else 981 ifp->if_hwassist &= ~CSUM_TSO; 982 } 983 VLAN_CAPABILITIES(ifp); 984 MSK_IF_UNLOCK(sc_if); 985 break; 986 default: 987 error = ether_ioctl(ifp, command, data); 988 break; 989 } 990 991 return (error); 992 } 993 994 static int 995 mskc_probe(device_t dev) 996 { 997 struct msk_product *mp; 998 uint16_t vendor, devid; 999 int i; 1000 1001 vendor = pci_get_vendor(dev); 1002 devid = pci_get_device(dev); 1003 mp = msk_products; 1004 for (i = 0; i < sizeof(msk_products)/sizeof(msk_products[0]); 1005 i++, mp++) { 1006 if (vendor == mp->msk_vendorid && devid == mp->msk_deviceid) { 1007 device_set_desc(dev, mp->msk_name); 1008 return (BUS_PROBE_DEFAULT); 1009 } 1010 } 1011 1012 return (ENXIO); 1013 } 1014 1015 static int 1016 mskc_setup_rambuffer(struct msk_softc *sc) 1017 { 1018 int totqsize, minqsize; 1019 int avail, next; 1020 int i; 1021 uint8_t val; 1022 1023 /* Get adapter SRAM size. */ 1024 val = CSR_READ_1(sc, B2_E_0); 1025 sc->msk_ramsize = (val == 0) ? 128 : val * 4; 1026 if (sc->msk_hw_id == CHIP_ID_YUKON_FE) 1027 sc->msk_ramsize = 4 * 4; 1028 if (bootverbose) 1029 device_printf(sc->msk_dev, 1030 "RAM buffer size : %dKB\n", sc->msk_ramsize); 1031 1032 totqsize = sc->msk_ramsize * sc->msk_num_port; 1033 minqsize = MSK_MIN_RXQ_SIZE + MSK_MIN_TXQ_SIZE; 1034 if (minqsize > sc->msk_ramsize) 1035 minqsize = sc->msk_ramsize; 1036 1037 if (minqsize * sc->msk_num_port > totqsize) { 1038 device_printf(sc->msk_dev, 1039 "not enough RAM buffer memory : %d/%dKB\n", 1040 minqsize * sc->msk_num_port, totqsize); 1041 return (ENOSPC); 1042 } 1043 1044 avail = totqsize; 1045 if (sc->msk_num_port > 1) { 1046 /* 1047 * Divide up the memory evenly so that everyone gets a 1048 * fair share for dual port adapters. 1049 */ 1050 avail = sc->msk_ramsize; 1051 } 1052 1053 /* Take away the minimum memory for active queues. */ 1054 avail -= minqsize; 1055 /* Rx queue gets the minimum + 80% of the rest. */ 1056 sc->msk_rxqsize = 1057 (avail * MSK_RAM_QUOTA_RX) / 100 + MSK_MIN_RXQ_SIZE; 1058 avail -= (sc->msk_rxqsize - MSK_MIN_RXQ_SIZE); 1059 sc->msk_txqsize = avail + MSK_MIN_TXQ_SIZE; 1060 1061 for (i = 0, next = 0; i < sc->msk_num_port; i++) { 1062 sc->msk_rxqstart[i] = next; 1063 sc->msk_rxqend[i] = next + (sc->msk_rxqsize * 1024) - 1; 1064 next = sc->msk_rxqend[i] + 1; 1065 sc->msk_txqstart[i] = next; 1066 sc->msk_txqend[i] = next + (sc->msk_txqsize * 1024) - 1; 1067 next = sc->msk_txqend[i] + 1; 1068 if (bootverbose) { 1069 device_printf(sc->msk_dev, 1070 "Port %d : Rx Queue %dKB(0x%08x:0x%08x)\n", i, 1071 sc->msk_rxqsize, sc->msk_rxqstart[i], 1072 sc->msk_rxqend[i]); 1073 device_printf(sc->msk_dev, 1074 "Port %d : Tx Queue %dKB(0x%08x:0x%08x)\n", i, 1075 sc->msk_txqsize, sc->msk_txqstart[i], 1076 sc->msk_txqend[i]); 1077 } 1078 } 1079 1080 return (0); 1081 } 1082 1083 static void 1084 msk_phy_power(struct msk_softc *sc, int mode) 1085 { 1086 uint32_t val; 1087 int i; 1088 1089 switch (mode) { 1090 case MSK_PHY_POWERUP: 1091 /* Switch power to VCC (WA for VAUX problem). */ 1092 CSR_WRITE_1(sc, B0_POWER_CTRL, 1093 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON); 1094 /* Disable Core Clock Division, set Clock Select to 0. */ 1095 CSR_WRITE_4(sc, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS); 1096 1097 val = 0; 1098 if (sc->msk_hw_id == CHIP_ID_YUKON_XL && 1099 sc->msk_hw_rev > CHIP_REV_YU_XL_A1) { 1100 /* Enable bits are inverted. */ 1101 val = Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS | 1102 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS | 1103 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS; 1104 } 1105 /* 1106 * Enable PCI & Core Clock, enable clock gating for both Links. 1107 */ 1108 CSR_WRITE_1(sc, B2_Y2_CLK_GATE, val); 1109 1110 val = pci_read_config(sc->msk_dev, PCI_OUR_REG_1, 4); 1111 val &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD); 1112 if (sc->msk_hw_id == CHIP_ID_YUKON_XL && 1113 sc->msk_hw_rev > CHIP_REV_YU_XL_A1) { 1114 /* Deassert Low Power for 1st PHY. */ 1115 val |= PCI_Y2_PHY1_COMA; 1116 if (sc->msk_num_port > 1) 1117 val |= PCI_Y2_PHY2_COMA; 1118 } else if (sc->msk_hw_id == CHIP_ID_YUKON_EC_U) { 1119 uint32_t our; 1120 1121 CSR_WRITE_2(sc, B0_CTST, Y2_HW_WOL_ON); 1122 1123 /* Enable all clocks. */ 1124 pci_write_config(sc->msk_dev, PCI_OUR_REG_3, 0, 4); 1125 our = pci_read_config(sc->msk_dev, PCI_OUR_REG_4, 4); 1126 our &= (PCI_FORCE_ASPM_REQUEST|PCI_ASPM_GPHY_LINK_DOWN| 1127 PCI_ASPM_INT_FIFO_EMPTY|PCI_ASPM_CLKRUN_REQUEST); 1128 /* Set all bits to 0 except bits 15..12. */ 1129 pci_write_config(sc->msk_dev, PCI_OUR_REG_4, our, 4); 1130 /* Set to default value. */ 1131 pci_write_config(sc->msk_dev, PCI_OUR_REG_5, 0, 4); 1132 } 1133 /* Release PHY from PowerDown/COMA mode. */ 1134 pci_write_config(sc->msk_dev, PCI_OUR_REG_1, val, 4); 1135 for (i = 0; i < sc->msk_num_port; i++) { 1136 CSR_WRITE_2(sc, MR_ADDR(i, GMAC_LINK_CTRL), 1137 GMLC_RST_SET); 1138 CSR_WRITE_2(sc, MR_ADDR(i, GMAC_LINK_CTRL), 1139 GMLC_RST_CLR); 1140 } 1141 break; 1142 case MSK_PHY_POWERDOWN: 1143 val = pci_read_config(sc->msk_dev, PCI_OUR_REG_1, 4); 1144 val |= PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD; 1145 if (sc->msk_hw_id == CHIP_ID_YUKON_XL && 1146 sc->msk_hw_rev > CHIP_REV_YU_XL_A1) { 1147 val &= ~PCI_Y2_PHY1_COMA; 1148 if (sc->msk_num_port > 1) 1149 val &= ~PCI_Y2_PHY2_COMA; 1150 } 1151 pci_write_config(sc->msk_dev, PCI_OUR_REG_1, val, 4); 1152 1153 val = Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS | 1154 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS | 1155 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS; 1156 if (sc->msk_hw_id == CHIP_ID_YUKON_XL && 1157 sc->msk_hw_rev > CHIP_REV_YU_XL_A1) { 1158 /* Enable bits are inverted. */ 1159 val = 0; 1160 } 1161 /* 1162 * Disable PCI & Core Clock, disable clock gating for 1163 * both Links. 1164 */ 1165 CSR_WRITE_1(sc, B2_Y2_CLK_GATE, val); 1166 CSR_WRITE_1(sc, B0_POWER_CTRL, 1167 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_ON | PC_VCC_OFF); 1168 break; 1169 default: 1170 break; 1171 } 1172 } 1173 1174 static void 1175 mskc_reset(struct msk_softc *sc) 1176 { 1177 bus_addr_t addr; 1178 uint16_t status; 1179 uint32_t val; 1180 int i; 1181 1182 CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR); 1183 1184 /* Disable ASF. */ 1185 if (sc->msk_hw_id < CHIP_ID_YUKON_XL) { 1186 CSR_WRITE_4(sc, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET); 1187 CSR_WRITE_2(sc, B0_CTST, Y2_ASF_DISABLE); 1188 } 1189 /* 1190 * Since we disabled ASF, S/W reset is required for Power Management. 1191 */ 1192 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); 1193 CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR); 1194 1195 /* Clear all error bits in the PCI status register. */ 1196 status = pci_read_config(sc->msk_dev, PCIR_STATUS, 2); 1197 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON); 1198 1199 pci_write_config(sc->msk_dev, PCIR_STATUS, status | 1200 PCIM_STATUS_PERR | PCIM_STATUS_SERR | PCIM_STATUS_RMABORT | 1201 PCIM_STATUS_RTABORT | PCIM_STATUS_PERRREPORT, 2); 1202 CSR_WRITE_2(sc, B0_CTST, CS_MRST_CLR); 1203 1204 switch (sc->msk_bustype) { 1205 case MSK_PEX_BUS: 1206 /* Clear all PEX errors. */ 1207 CSR_PCI_WRITE_4(sc, PEX_UNC_ERR_STAT, 0xffffffff); 1208 val = CSR_PCI_READ_4(sc, PEX_UNC_ERR_STAT); 1209 if ((val & PEX_RX_OV) != 0) { 1210 sc->msk_intrmask &= ~Y2_IS_HW_ERR; 1211 sc->msk_intrhwemask &= ~Y2_IS_PCI_EXP; 1212 } 1213 break; 1214 case MSK_PCI_BUS: 1215 case MSK_PCIX_BUS: 1216 /* Set Cache Line Size to 2(8bytes) if configured to 0. */ 1217 val = pci_read_config(sc->msk_dev, PCIR_CACHELNSZ, 1); 1218 if (val == 0) 1219 pci_write_config(sc->msk_dev, PCIR_CACHELNSZ, 2, 1); 1220 if (sc->msk_bustype == MSK_PCIX_BUS) { 1221 /* Set Cache Line Size opt. */ 1222 val = pci_read_config(sc->msk_dev, PCI_OUR_REG_1, 4); 1223 val |= PCI_CLS_OPT; 1224 pci_write_config(sc->msk_dev, PCI_OUR_REG_1, val, 4); 1225 } 1226 break; 1227 } 1228 /* Set PHY power state. */ 1229 msk_phy_power(sc, MSK_PHY_POWERUP); 1230 1231 /* Reset GPHY/GMAC Control */ 1232 for (i = 0; i < sc->msk_num_port; i++) { 1233 /* GPHY Control reset. */ 1234 CSR_WRITE_4(sc, MR_ADDR(i, GPHY_CTRL), GPC_RST_SET); 1235 CSR_WRITE_4(sc, MR_ADDR(i, GPHY_CTRL), GPC_RST_CLR); 1236 /* GMAC Control reset. */ 1237 CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), GMC_RST_SET); 1238 CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), GMC_RST_CLR); 1239 CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), GMC_F_LOOPB_OFF); 1240 } 1241 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 1242 1243 /* LED On. */ 1244 CSR_WRITE_2(sc, B0_CTST, Y2_LED_STAT_ON); 1245 1246 /* Clear TWSI IRQ. */ 1247 CSR_WRITE_4(sc, B2_I2C_IRQ, I2C_CLR_IRQ); 1248 1249 /* Turn off hardware timer. */ 1250 CSR_WRITE_1(sc, B2_TI_CTRL, TIM_STOP); 1251 CSR_WRITE_1(sc, B2_TI_CTRL, TIM_CLR_IRQ); 1252 1253 /* Turn off descriptor polling. */ 1254 CSR_WRITE_1(sc, B28_DPT_CTRL, DPT_STOP); 1255 1256 /* Turn off time stamps. */ 1257 CSR_WRITE_1(sc, GMAC_TI_ST_CTRL, GMT_ST_STOP); 1258 CSR_WRITE_1(sc, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ); 1259 1260 /* Configure timeout values. */ 1261 for (i = 0; i < sc->msk_num_port; i++) { 1262 CSR_WRITE_2(sc, SELECT_RAM_BUFFER(i, B3_RI_CTRL), RI_RST_SET); 1263 CSR_WRITE_2(sc, SELECT_RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR); 1264 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_R1), 1265 MSK_RI_TO_53); 1266 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XA1), 1267 MSK_RI_TO_53); 1268 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XS1), 1269 MSK_RI_TO_53); 1270 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_R1), 1271 MSK_RI_TO_53); 1272 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XA1), 1273 MSK_RI_TO_53); 1274 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XS1), 1275 MSK_RI_TO_53); 1276 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_R2), 1277 MSK_RI_TO_53); 1278 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XA2), 1279 MSK_RI_TO_53); 1280 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XS2), 1281 MSK_RI_TO_53); 1282 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_R2), 1283 MSK_RI_TO_53); 1284 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XA2), 1285 MSK_RI_TO_53); 1286 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XS2), 1287 MSK_RI_TO_53); 1288 } 1289 1290 /* Disable all interrupts. */ 1291 CSR_WRITE_4(sc, B0_HWE_IMSK, 0); 1292 CSR_READ_4(sc, B0_HWE_IMSK); 1293 CSR_WRITE_4(sc, B0_IMSK, 0); 1294 CSR_READ_4(sc, B0_IMSK); 1295 1296 /* 1297 * On dual port PCI-X card, there is an problem where status 1298 * can be received out of order due to split transactions. 1299 */ 1300 if (sc->msk_bustype == MSK_PCIX_BUS && sc->msk_num_port > 1) { 1301 int pcix; 1302 uint16_t pcix_cmd; 1303 1304 if (pci_find_extcap(sc->msk_dev, PCIY_PCIX, &pcix) == 0) { 1305 pcix_cmd = pci_read_config(sc->msk_dev, pcix + 2, 2); 1306 /* Clear Max Outstanding Split Transactions. */ 1307 pcix_cmd &= ~0x70; 1308 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON); 1309 pci_write_config(sc->msk_dev, pcix + 2, pcix_cmd, 2); 1310 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 1311 } 1312 } 1313 if (sc->msk_bustype == MSK_PEX_BUS) { 1314 uint16_t v, width; 1315 1316 v = pci_read_config(sc->msk_dev, PEX_DEV_CTRL, 2); 1317 /* Change Max. Read Request Size to 4096 bytes. */ 1318 v &= ~PEX_DC_MAX_RRS_MSK; 1319 v |= PEX_DC_MAX_RD_RQ_SIZE(5); 1320 pci_write_config(sc->msk_dev, PEX_DEV_CTRL, v, 2); 1321 width = pci_read_config(sc->msk_dev, PEX_LNK_STAT, 2); 1322 width = (width & PEX_LS_LINK_WI_MSK) >> 4; 1323 v = pci_read_config(sc->msk_dev, PEX_LNK_CAP, 2); 1324 v = (v & PEX_LS_LINK_WI_MSK) >> 4; 1325 if (v != width) 1326 device_printf(sc->msk_dev, 1327 "negotiated width of link(x%d) != " 1328 "max. width of link(x%d)\n", width, v); 1329 } 1330 1331 /* Clear status list. */ 1332 bzero(sc->msk_stat_ring, 1333 sizeof(struct msk_stat_desc) * MSK_STAT_RING_CNT); 1334 sc->msk_stat_cons = 0; 1335 bus_dmamap_sync(sc->msk_stat_tag, sc->msk_stat_map, 1336 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1337 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_RST_SET); 1338 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_RST_CLR); 1339 /* Set the status list base address. */ 1340 addr = sc->msk_stat_ring_paddr; 1341 CSR_WRITE_4(sc, STAT_LIST_ADDR_LO, MSK_ADDR_LO(addr)); 1342 CSR_WRITE_4(sc, STAT_LIST_ADDR_HI, MSK_ADDR_HI(addr)); 1343 /* Set the status list last index. */ 1344 CSR_WRITE_2(sc, STAT_LAST_IDX, MSK_STAT_RING_CNT - 1); 1345 if (HW_FEATURE(sc, HWF_WA_DEV_43_418)) { 1346 /* WA for dev. #4.3 */ 1347 CSR_WRITE_2(sc, STAT_TX_IDX_TH, ST_TXTH_IDX_MASK); 1348 /* WA for dev. #4.18 */ 1349 CSR_WRITE_1(sc, STAT_FIFO_WM, 0x21); 1350 CSR_WRITE_1(sc, STAT_FIFO_ISR_WM, 0x07); 1351 } else { 1352 CSR_WRITE_2(sc, STAT_TX_IDX_TH, 0x0a); 1353 CSR_WRITE_1(sc, STAT_FIFO_WM, 0x10); 1354 CSR_WRITE_1(sc, STAT_FIFO_ISR_WM, 1355 HW_FEATURE(sc, HWF_WA_DEV_4109) ? 0x10 : 0x04); 1356 CSR_WRITE_4(sc, STAT_ISR_TIMER_INI, 0x0190); 1357 } 1358 /* 1359 * Use default value for STAT_ISR_TIMER_INI, STAT_LEV_TIMER_INI. 1360 */ 1361 CSR_WRITE_4(sc, STAT_TX_TIMER_INI, MSK_USECS(sc, 1000)); 1362 1363 /* Enable status unit. */ 1364 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_OP_ON); 1365 1366 CSR_WRITE_1(sc, STAT_TX_TIMER_CTRL, TIM_START); 1367 CSR_WRITE_1(sc, STAT_LEV_TIMER_CTRL, TIM_START); 1368 CSR_WRITE_1(sc, STAT_ISR_TIMER_CTRL, TIM_START); 1369 } 1370 1371 static int 1372 msk_probe(device_t dev) 1373 { 1374 struct msk_softc *sc; 1375 char desc[100]; 1376 1377 sc = device_get_softc(device_get_parent(dev)); 1378 /* 1379 * Not much to do here. We always know there will be 1380 * at least one GMAC present, and if there are two, 1381 * mskc_attach() will create a second device instance 1382 * for us. 1383 */ 1384 snprintf(desc, sizeof(desc), 1385 "Marvell Technology Group Ltd. %s Id 0x%02x Rev 0x%02x", 1386 model_name[sc->msk_hw_id - CHIP_ID_YUKON_XL], sc->msk_hw_id, 1387 sc->msk_hw_rev); 1388 device_set_desc_copy(dev, desc); 1389 1390 return (BUS_PROBE_DEFAULT); 1391 } 1392 1393 static int 1394 msk_attach(device_t dev) 1395 { 1396 struct msk_softc *sc; 1397 struct msk_if_softc *sc_if; 1398 struct ifnet *ifp; 1399 int i, port, error; 1400 uint8_t eaddr[6]; 1401 1402 if (dev == NULL) 1403 return (EINVAL); 1404 1405 error = 0; 1406 sc_if = device_get_softc(dev); 1407 sc = device_get_softc(device_get_parent(dev)); 1408 port = *(int *)device_get_ivars(dev); 1409 1410 sc_if->msk_if_dev = dev; 1411 sc_if->msk_port = port; 1412 sc_if->msk_softc = sc; 1413 sc->msk_if[port] = sc_if; 1414 /* Setup Tx/Rx queue register offsets. */ 1415 if (port == MSK_PORT_A) { 1416 sc_if->msk_txq = Q_XA1; 1417 sc_if->msk_txsq = Q_XS1; 1418 sc_if->msk_rxq = Q_R1; 1419 } else { 1420 sc_if->msk_txq = Q_XA2; 1421 sc_if->msk_txsq = Q_XS2; 1422 sc_if->msk_rxq = Q_R2; 1423 } 1424 1425 callout_init_mtx(&sc_if->msk_tick_ch, &sc_if->msk_softc->msk_mtx, 0); 1426 TASK_INIT(&sc_if->msk_link_task, 0, msk_link_task, sc_if); 1427 1428 if ((error = msk_txrx_dma_alloc(sc_if) != 0)) 1429 goto fail; 1430 1431 ifp = sc_if->msk_ifp = if_alloc(IFT_ETHER); 1432 if (ifp == NULL) { 1433 device_printf(sc_if->msk_if_dev, "can not if_alloc()\n"); 1434 error = ENOSPC; 1435 goto fail; 1436 } 1437 ifp->if_softc = sc_if; 1438 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1439 ifp->if_mtu = ETHERMTU; 1440 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1441 /* 1442 * IFCAP_RXCSUM capability is intentionally disabled as the hardware 1443 * has serious bug in Rx checksum offload for all Yukon II family 1444 * hardware. It seems there is a workaround to make it work somtimes. 1445 * However, the workaround also have to check OP code sequences to 1446 * verify whether the OP code is correct. Sometimes it should compute 1447 * IP/TCP/UDP checksum in driver in order to verify correctness of 1448 * checksum computed by hardware. If you have to compute checksum 1449 * with software to verify the hardware's checksum why have hardware 1450 * compute the checksum? I think there is no reason to spend time to 1451 * make Rx checksum offload work on Yukon II hardware. 1452 */ 1453 ifp->if_capabilities = IFCAP_TXCSUM; 1454 ifp->if_hwassist = MSK_CSUM_FEATURES; 1455 #if 0 1456 /* 1457 * Under certain circumtances, if TSO is active, Yukon II generates 1458 * corrupted IP packets. Disable TSO until we find a working 1459 * workaround or a new silicon revision that doesn't have this 1460 * hardware bug. 1461 */ 1462 if (sc->msk_hw_id != CHIP_ID_YUKON_EC_U) { 1463 /* It seems Yukon EC Ultra doesn't support TSO. */ 1464 ifp->if_capabilities |= IFCAP_TSO4; 1465 ifp->if_hwassist |= CSUM_TSO; 1466 } 1467 #endif 1468 ifp->if_capenable = ifp->if_capabilities; 1469 ifp->if_ioctl = msk_ioctl; 1470 ifp->if_start = msk_start; 1471 ifp->if_timer = 0; 1472 ifp->if_watchdog = NULL; 1473 ifp->if_init = msk_init; 1474 IFQ_SET_MAXLEN(&ifp->if_snd, MSK_TX_RING_CNT - 1); 1475 ifp->if_snd.ifq_drv_maxlen = MSK_TX_RING_CNT - 1; 1476 IFQ_SET_READY(&ifp->if_snd); 1477 1478 TASK_INIT(&sc_if->msk_tx_task, 1, msk_tx_task, ifp); 1479 1480 /* 1481 * Get station address for this interface. Note that 1482 * dual port cards actually come with three station 1483 * addresses: one for each port, plus an extra. The 1484 * extra one is used by the SysKonnect driver software 1485 * as a 'virtual' station address for when both ports 1486 * are operating in failover mode. Currently we don't 1487 * use this extra address. 1488 */ 1489 MSK_IF_LOCK(sc_if); 1490 for (i = 0; i < ETHER_ADDR_LEN; i++) 1491 eaddr[i] = CSR_READ_1(sc, B2_MAC_1 + (port * 8) + i); 1492 1493 /* 1494 * Call MI attach routine. Can't hold locks when calling into ether_*. 1495 */ 1496 MSK_IF_UNLOCK(sc_if); 1497 ether_ifattach(ifp, eaddr); 1498 MSK_IF_LOCK(sc_if); 1499 1500 /* VLAN capability setup */ 1501 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING; 1502 if (ifp->if_capabilities & IFCAP_HWCSUM) 1503 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM; 1504 ifp->if_capenable = ifp->if_capabilities; 1505 1506 /* 1507 * Tell the upper layer(s) we support long frames. 1508 * Must appear after the call to ether_ifattach() because 1509 * ether_ifattach() sets ifi_hdrlen to the default value. 1510 */ 1511 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1512 1513 /* 1514 * Do miibus setup. 1515 */ 1516 MSK_IF_UNLOCK(sc_if); 1517 error = mii_phy_probe(dev, &sc_if->msk_miibus, msk_mediachange, 1518 msk_mediastatus); 1519 if (error != 0) { 1520 device_printf(sc_if->msk_if_dev, "no PHY found!\n"); 1521 ether_ifdetach(ifp); 1522 error = ENXIO; 1523 goto fail; 1524 } 1525 /* Check whether PHY Id is MARVELL. */ 1526 if (msk_phy_readreg(sc_if, PHY_ADDR_MARV, PHY_MARV_ID0) 1527 == PHY_MARV_ID0_VAL) 1528 sc->msk_marvell_phy = 1; 1529 1530 fail: 1531 if (error != 0) { 1532 /* Access should be ok even though lock has been dropped */ 1533 sc->msk_if[port] = NULL; 1534 msk_detach(dev); 1535 } 1536 1537 return (error); 1538 } 1539 1540 /* 1541 * Attach the interface. Allocate softc structures, do ifmedia 1542 * setup and ethernet/BPF attach. 1543 */ 1544 static int 1545 mskc_attach(device_t dev) 1546 { 1547 struct msk_softc *sc; 1548 int error, msic, *port, reg; 1549 1550 sc = device_get_softc(dev); 1551 sc->msk_dev = dev; 1552 mtx_init(&sc->msk_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1553 MTX_DEF); 1554 1555 /* 1556 * Map control/status registers. 1557 */ 1558 pci_enable_busmaster(dev); 1559 1560 /* Allocate I/O resource */ 1561 #ifdef MSK_USEIOSPACE 1562 sc->msk_res_spec = msk_res_spec_io; 1563 #else 1564 sc->msk_res_spec = msk_res_spec_mem; 1565 #endif 1566 sc->msk_irq_spec = msk_irq_spec_legacy; 1567 error = bus_alloc_resources(dev, sc->msk_res_spec, sc->msk_res); 1568 if (error) { 1569 if (sc->msk_res_spec == msk_res_spec_mem) 1570 sc->msk_res_spec = msk_res_spec_io; 1571 else 1572 sc->msk_res_spec = msk_res_spec_mem; 1573 error = bus_alloc_resources(dev, sc->msk_res_spec, sc->msk_res); 1574 if (error) { 1575 device_printf(dev, "couldn't allocate %s resources\n", 1576 sc->msk_res_spec == msk_res_spec_mem ? "memory" : 1577 "I/O"); 1578 mtx_destroy(&sc->msk_mtx); 1579 return (ENXIO); 1580 } 1581 } 1582 1583 CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR); 1584 sc->msk_hw_id = CSR_READ_1(sc, B2_CHIP_ID); 1585 sc->msk_hw_rev = (CSR_READ_1(sc, B2_MAC_CFG) >> 4) & 0x0f; 1586 /* Bail out if chip is not recognized. */ 1587 if (sc->msk_hw_id < CHIP_ID_YUKON_XL || 1588 sc->msk_hw_id > CHIP_ID_YUKON_FE) { 1589 device_printf(dev, "unknown device: id=0x%02x, rev=0x%02x\n", 1590 sc->msk_hw_id, sc->msk_hw_rev); 1591 mtx_destroy(&sc->msk_mtx); 1592 return (ENXIO); 1593 } 1594 1595 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 1596 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 1597 OID_AUTO, "process_limit", CTLTYPE_INT | CTLFLAG_RW, 1598 &sc->msk_process_limit, 0, sysctl_hw_msk_proc_limit, "I", 1599 "max number of Rx events to process"); 1600 1601 sc->msk_process_limit = MSK_PROC_DEFAULT; 1602 error = resource_int_value(device_get_name(dev), device_get_unit(dev), 1603 "process_limit", &sc->msk_process_limit); 1604 if (error == 0) { 1605 if (sc->msk_process_limit < MSK_PROC_MIN || 1606 sc->msk_process_limit > MSK_PROC_MAX) { 1607 device_printf(dev, "process_limit value out of range; " 1608 "using default: %d\n", MSK_PROC_DEFAULT); 1609 sc->msk_process_limit = MSK_PROC_DEFAULT; 1610 } 1611 } 1612 1613 /* Soft reset. */ 1614 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); 1615 CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR); 1616 sc->msk_pmd = CSR_READ_1(sc, B2_PMD_TYP); 1617 if (sc->msk_pmd == 'L' || sc->msk_pmd == 'S') 1618 sc->msk_coppertype = 0; 1619 else 1620 sc->msk_coppertype = 1; 1621 /* Check number of MACs. */ 1622 sc->msk_num_port = 1; 1623 if ((CSR_READ_1(sc, B2_Y2_HW_RES) & CFG_DUAL_MAC_MSK) == 1624 CFG_DUAL_MAC_MSK) { 1625 if (!(CSR_READ_1(sc, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC)) 1626 sc->msk_num_port++; 1627 } 1628 1629 /* Check bus type. */ 1630 if (pci_find_extcap(sc->msk_dev, PCIY_EXPRESS, ®) == 0) 1631 sc->msk_bustype = MSK_PEX_BUS; 1632 else if (pci_find_extcap(sc->msk_dev, PCIY_PCIX, ®) == 0) 1633 sc->msk_bustype = MSK_PCIX_BUS; 1634 else 1635 sc->msk_bustype = MSK_PCI_BUS; 1636 1637 /* Get H/W features(bugs). */ 1638 switch (sc->msk_hw_id) { 1639 case CHIP_ID_YUKON_EC: 1640 sc->msk_clock = 125; /* 125 Mhz */ 1641 if (sc->msk_hw_rev == CHIP_REV_YU_EC_A1) { 1642 sc->msk_hw_feature = 1643 HWF_WA_DEV_42 | HWF_WA_DEV_46 | HWF_WA_DEV_43_418 | 1644 HWF_WA_DEV_420 | HWF_WA_DEV_423 | 1645 HWF_WA_DEV_424 | HWF_WA_DEV_425 | HWF_WA_DEV_427 | 1646 HWF_WA_DEV_428 | HWF_WA_DEV_483 | HWF_WA_DEV_4109 | 1647 HWF_WA_DEV_4152 | HWF_WA_DEV_4167; 1648 } else { 1649 /* A2/A3 */ 1650 sc->msk_hw_feature = 1651 HWF_WA_DEV_424 | HWF_WA_DEV_425 | HWF_WA_DEV_427 | 1652 HWF_WA_DEV_428 | HWF_WA_DEV_483 | HWF_WA_DEV_4109 | 1653 HWF_WA_DEV_4152 | HWF_WA_DEV_4167; 1654 } 1655 break; 1656 case CHIP_ID_YUKON_EC_U: 1657 sc->msk_clock = 125; /* 125 Mhz */ 1658 if (sc->msk_hw_rev == CHIP_REV_YU_EC_U_A0) { 1659 sc->msk_hw_feature = HWF_WA_DEV_427 | HWF_WA_DEV_483 | 1660 HWF_WA_DEV_4109; 1661 } else if (sc->msk_hw_rev == CHIP_REV_YU_EC_A1) { 1662 uint16_t v; 1663 1664 sc->msk_hw_feature = HWF_WA_DEV_427 | HWF_WA_DEV_4109 | 1665 HWF_WA_DEV_4185; 1666 v = CSR_READ_2(sc, Q_ADDR(Q_XA1, Q_WM)); 1667 if (v == 0) 1668 sc->msk_hw_feature |= HWF_WA_DEV_4185CS | 1669 HWF_WA_DEV_4200; 1670 } 1671 break; 1672 case CHIP_ID_YUKON_FE: 1673 sc->msk_clock = 100; /* 100 Mhz */ 1674 sc->msk_hw_feature = HWF_WA_DEV_427 | HWF_WA_DEV_4109 | 1675 HWF_WA_DEV_4152 | HWF_WA_DEV_4167; 1676 break; 1677 case CHIP_ID_YUKON_XL: 1678 sc->msk_clock = 156; /* 156 Mhz */ 1679 switch (sc->msk_hw_rev) { 1680 case CHIP_REV_YU_XL_A0: 1681 sc->msk_hw_feature = 1682 HWF_WA_DEV_427 | HWF_WA_DEV_463 | HWF_WA_DEV_472 | 1683 HWF_WA_DEV_479 | HWF_WA_DEV_483 | HWF_WA_DEV_4115 | 1684 HWF_WA_DEV_4152 | HWF_WA_DEV_4167; 1685 break; 1686 case CHIP_REV_YU_XL_A1: 1687 sc->msk_hw_feature = 1688 HWF_WA_DEV_427 | HWF_WA_DEV_483 | HWF_WA_DEV_4109 | 1689 HWF_WA_DEV_4115 | HWF_WA_DEV_4152 | HWF_WA_DEV_4167; 1690 break; 1691 case CHIP_REV_YU_XL_A2: 1692 sc->msk_hw_feature = 1693 HWF_WA_DEV_427 | HWF_WA_DEV_483 | HWF_WA_DEV_4109 | 1694 HWF_WA_DEV_4115 | HWF_WA_DEV_4167; 1695 break; 1696 case CHIP_REV_YU_XL_A3: 1697 sc->msk_hw_feature = 1698 HWF_WA_DEV_427 | HWF_WA_DEV_483 | HWF_WA_DEV_4109 | 1699 HWF_WA_DEV_4115; 1700 } 1701 break; 1702 default: 1703 sc->msk_clock = 156; /* 156 Mhz */ 1704 sc->msk_hw_feature = 0; 1705 } 1706 1707 /* Allocate IRQ resources. */ 1708 msic = pci_msi_count(dev); 1709 if (bootverbose) 1710 device_printf(dev, "MSI count : %d\n", msic); 1711 /* 1712 * The Yukon II reports it can handle two messages, one for each 1713 * possible port. We go ahead and allocate two messages and only 1714 * setup a handler for both if we have a dual port card. 1715 * 1716 * XXX: I haven't untangled the interrupt handler to handle dual 1717 * port cards with separate MSI messages, so for now I disable MSI 1718 * on dual port cards. 1719 */ 1720 if (msic == 2 && msi_disable == 0 && sc->msk_num_port == 1 && 1721 pci_alloc_msi(dev, &msic) == 0) { 1722 if (msic == 2) { 1723 sc->msk_msi = 1; 1724 sc->msk_irq_spec = msk_irq_spec_msi; 1725 } else 1726 pci_release_msi(dev); 1727 } 1728 1729 error = bus_alloc_resources(dev, sc->msk_irq_spec, sc->msk_irq); 1730 if (error) { 1731 device_printf(dev, "couldn't allocate IRQ resources\n"); 1732 goto fail; 1733 } 1734 1735 if ((error = msk_status_dma_alloc(sc)) != 0) 1736 goto fail; 1737 1738 /* Set base interrupt mask. */ 1739 sc->msk_intrmask = Y2_IS_HW_ERR | Y2_IS_STAT_BMU; 1740 sc->msk_intrhwemask = Y2_IS_TIST_OV | Y2_IS_MST_ERR | 1741 Y2_IS_IRQ_STAT | Y2_IS_PCI_EXP | Y2_IS_PCI_NEXP; 1742 1743 /* Reset the adapter. */ 1744 mskc_reset(sc); 1745 1746 if ((error = mskc_setup_rambuffer(sc)) != 0) 1747 goto fail; 1748 1749 sc->msk_devs[MSK_PORT_A] = device_add_child(dev, "msk", -1); 1750 if (sc->msk_devs[MSK_PORT_A] == NULL) { 1751 device_printf(dev, "failed to add child for PORT_A\n"); 1752 error = ENXIO; 1753 goto fail; 1754 } 1755 port = malloc(sizeof(int), M_DEVBUF, M_WAITOK); 1756 if (port == NULL) { 1757 device_printf(dev, "failed to allocate memory for " 1758 "ivars of PORT_A\n"); 1759 error = ENXIO; 1760 goto fail; 1761 } 1762 *port = MSK_PORT_A; 1763 device_set_ivars(sc->msk_devs[MSK_PORT_A], port); 1764 1765 if (sc->msk_num_port > 1) { 1766 sc->msk_devs[MSK_PORT_B] = device_add_child(dev, "msk", -1); 1767 if (sc->msk_devs[MSK_PORT_B] == NULL) { 1768 device_printf(dev, "failed to add child for PORT_B\n"); 1769 error = ENXIO; 1770 goto fail; 1771 } 1772 port = malloc(sizeof(int), M_DEVBUF, M_WAITOK); 1773 if (port == NULL) { 1774 device_printf(dev, "failed to allocate memory for " 1775 "ivars of PORT_B\n"); 1776 error = ENXIO; 1777 goto fail; 1778 } 1779 *port = MSK_PORT_B; 1780 device_set_ivars(sc->msk_devs[MSK_PORT_B], port); 1781 } 1782 1783 error = bus_generic_attach(dev); 1784 if (error) { 1785 device_printf(dev, "failed to attach port(s)\n"); 1786 goto fail; 1787 } 1788 1789 TASK_INIT(&sc->msk_int_task, 0, msk_int_task, sc); 1790 sc->msk_tq = taskqueue_create_fast("msk_taskq", M_WAITOK, 1791 taskqueue_thread_enqueue, &sc->msk_tq); 1792 taskqueue_start_threads(&sc->msk_tq, 1, PI_NET, "%s taskq", 1793 device_get_nameunit(sc->msk_dev)); 1794 /* Hook interrupt last to avoid having to lock softc. */ 1795 error = bus_setup_intr(dev, sc->msk_irq[0], INTR_TYPE_NET | 1796 INTR_MPSAFE, msk_intr, NULL, sc, &sc->msk_intrhand[0]); 1797 1798 if (error != 0) { 1799 device_printf(dev, "couldn't set up interrupt handler\n"); 1800 taskqueue_free(sc->msk_tq); 1801 sc->msk_tq = NULL; 1802 goto fail; 1803 } 1804 fail: 1805 if (error != 0) 1806 mskc_detach(dev); 1807 1808 return (error); 1809 } 1810 1811 /* 1812 * Shutdown hardware and free up resources. This can be called any 1813 * time after the mutex has been initialized. It is called in both 1814 * the error case in attach and the normal detach case so it needs 1815 * to be careful about only freeing resources that have actually been 1816 * allocated. 1817 */ 1818 static int 1819 msk_detach(device_t dev) 1820 { 1821 struct msk_softc *sc; 1822 struct msk_if_softc *sc_if; 1823 struct ifnet *ifp; 1824 1825 sc_if = device_get_softc(dev); 1826 KASSERT(mtx_initialized(&sc_if->msk_softc->msk_mtx), 1827 ("msk mutex not initialized in msk_detach")); 1828 MSK_IF_LOCK(sc_if); 1829 1830 ifp = sc_if->msk_ifp; 1831 if (device_is_attached(dev)) { 1832 /* XXX */ 1833 sc_if->msk_detach = 1; 1834 msk_stop(sc_if); 1835 /* Can't hold locks while calling detach. */ 1836 MSK_IF_UNLOCK(sc_if); 1837 callout_drain(&sc_if->msk_tick_ch); 1838 taskqueue_drain(taskqueue_fast, &sc_if->msk_tx_task); 1839 taskqueue_drain(taskqueue_swi, &sc_if->msk_link_task); 1840 ether_ifdetach(ifp); 1841 MSK_IF_LOCK(sc_if); 1842 } 1843 1844 /* 1845 * We're generally called from mskc_detach() which is using 1846 * device_delete_child() to get to here. It's already trashed 1847 * miibus for us, so don't do it here or we'll panic. 1848 * 1849 * if (sc_if->msk_miibus != NULL) { 1850 * device_delete_child(dev, sc_if->msk_miibus); 1851 * sc_if->msk_miibus = NULL; 1852 * } 1853 */ 1854 1855 msk_txrx_dma_free(sc_if); 1856 bus_generic_detach(dev); 1857 1858 if (ifp) 1859 if_free(ifp); 1860 sc = sc_if->msk_softc; 1861 sc->msk_if[sc_if->msk_port] = NULL; 1862 MSK_IF_UNLOCK(sc_if); 1863 1864 return (0); 1865 } 1866 1867 static int 1868 mskc_detach(device_t dev) 1869 { 1870 struct msk_softc *sc; 1871 1872 sc = device_get_softc(dev); 1873 KASSERT(mtx_initialized(&sc->msk_mtx), ("msk mutex not initialized")); 1874 1875 if (device_is_alive(dev)) { 1876 if (sc->msk_devs[MSK_PORT_A] != NULL) { 1877 free(device_get_ivars(sc->msk_devs[MSK_PORT_A]), 1878 M_DEVBUF); 1879 device_delete_child(dev, sc->msk_devs[MSK_PORT_A]); 1880 } 1881 if (sc->msk_devs[MSK_PORT_B] != NULL) { 1882 free(device_get_ivars(sc->msk_devs[MSK_PORT_B]), 1883 M_DEVBUF); 1884 device_delete_child(dev, sc->msk_devs[MSK_PORT_B]); 1885 } 1886 bus_generic_detach(dev); 1887 } 1888 1889 /* Disable all interrupts. */ 1890 CSR_WRITE_4(sc, B0_IMSK, 0); 1891 CSR_READ_4(sc, B0_IMSK); 1892 CSR_WRITE_4(sc, B0_HWE_IMSK, 0); 1893 CSR_READ_4(sc, B0_HWE_IMSK); 1894 1895 /* LED Off. */ 1896 CSR_WRITE_2(sc, B0_CTST, Y2_LED_STAT_OFF); 1897 1898 /* Put hardware reset. */ 1899 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); 1900 1901 msk_status_dma_free(sc); 1902 1903 if (sc->msk_tq != NULL) { 1904 taskqueue_drain(sc->msk_tq, &sc->msk_int_task); 1905 taskqueue_free(sc->msk_tq); 1906 sc->msk_tq = NULL; 1907 } 1908 if (sc->msk_intrhand[0]) { 1909 bus_teardown_intr(dev, sc->msk_irq[0], sc->msk_intrhand[0]); 1910 sc->msk_intrhand[0] = NULL; 1911 } 1912 if (sc->msk_intrhand[1]) { 1913 bus_teardown_intr(dev, sc->msk_irq[0], sc->msk_intrhand[0]); 1914 sc->msk_intrhand[1] = NULL; 1915 } 1916 bus_release_resources(dev, sc->msk_irq_spec, sc->msk_irq); 1917 if (sc->msk_msi) 1918 pci_release_msi(dev); 1919 bus_release_resources(dev, sc->msk_res_spec, sc->msk_res); 1920 mtx_destroy(&sc->msk_mtx); 1921 1922 return (0); 1923 } 1924 1925 struct msk_dmamap_arg { 1926 bus_addr_t msk_busaddr; 1927 }; 1928 1929 static void 1930 msk_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1931 { 1932 struct msk_dmamap_arg *ctx; 1933 1934 if (error != 0) 1935 return; 1936 ctx = arg; 1937 ctx->msk_busaddr = segs[0].ds_addr; 1938 } 1939 1940 /* Create status DMA region. */ 1941 static int 1942 msk_status_dma_alloc(struct msk_softc *sc) 1943 { 1944 struct msk_dmamap_arg ctx; 1945 int error; 1946 1947 error = bus_dma_tag_create( 1948 bus_get_dma_tag(sc->msk_dev), /* parent */ 1949 MSK_STAT_ALIGN, 0, /* alignment, boundary */ 1950 BUS_SPACE_MAXADDR, /* lowaddr */ 1951 BUS_SPACE_MAXADDR, /* highaddr */ 1952 NULL, NULL, /* filter, filterarg */ 1953 MSK_STAT_RING_SZ, /* maxsize */ 1954 1, /* nsegments */ 1955 MSK_STAT_RING_SZ, /* maxsegsize */ 1956 0, /* flags */ 1957 NULL, NULL, /* lockfunc, lockarg */ 1958 &sc->msk_stat_tag); 1959 if (error != 0) { 1960 device_printf(sc->msk_dev, 1961 "failed to create status DMA tag\n"); 1962 return (error); 1963 } 1964 1965 /* Allocate DMA'able memory and load the DMA map for status ring. */ 1966 error = bus_dmamem_alloc(sc->msk_stat_tag, 1967 (void **)&sc->msk_stat_ring, BUS_DMA_WAITOK | BUS_DMA_COHERENT | 1968 BUS_DMA_ZERO, &sc->msk_stat_map); 1969 if (error != 0) { 1970 device_printf(sc->msk_dev, 1971 "failed to allocate DMA'able memory for status ring\n"); 1972 return (error); 1973 } 1974 1975 ctx.msk_busaddr = 0; 1976 error = bus_dmamap_load(sc->msk_stat_tag, 1977 sc->msk_stat_map, sc->msk_stat_ring, MSK_STAT_RING_SZ, 1978 msk_dmamap_cb, &ctx, 0); 1979 if (error != 0) { 1980 device_printf(sc->msk_dev, 1981 "failed to load DMA'able memory for status ring\n"); 1982 return (error); 1983 } 1984 sc->msk_stat_ring_paddr = ctx.msk_busaddr; 1985 1986 return (0); 1987 } 1988 1989 static void 1990 msk_status_dma_free(struct msk_softc *sc) 1991 { 1992 1993 /* Destroy status block. */ 1994 if (sc->msk_stat_tag) { 1995 if (sc->msk_stat_map) { 1996 bus_dmamap_unload(sc->msk_stat_tag, sc->msk_stat_map); 1997 if (sc->msk_stat_ring) { 1998 bus_dmamem_free(sc->msk_stat_tag, 1999 sc->msk_stat_ring, sc->msk_stat_map); 2000 sc->msk_stat_ring = NULL; 2001 } 2002 sc->msk_stat_map = NULL; 2003 } 2004 bus_dma_tag_destroy(sc->msk_stat_tag); 2005 sc->msk_stat_tag = NULL; 2006 } 2007 } 2008 2009 static int 2010 msk_txrx_dma_alloc(struct msk_if_softc *sc_if) 2011 { 2012 struct msk_dmamap_arg ctx; 2013 struct msk_txdesc *txd; 2014 struct msk_rxdesc *rxd; 2015 struct msk_rxdesc *jrxd; 2016 struct msk_jpool_entry *entry; 2017 uint8_t *ptr; 2018 int error, i; 2019 2020 mtx_init(&sc_if->msk_jlist_mtx, "msk_jlist_mtx", NULL, MTX_DEF); 2021 SLIST_INIT(&sc_if->msk_jfree_listhead); 2022 SLIST_INIT(&sc_if->msk_jinuse_listhead); 2023 2024 /* Create parent DMA tag. */ 2025 /* 2026 * XXX 2027 * It seems that Yukon II supports full 64bits DMA operations. But 2028 * it needs two descriptors(list elements) for 64bits DMA operations. 2029 * Since we don't know what DMA address mappings(32bits or 64bits) 2030 * would be used in advance for each mbufs, we limits its DMA space 2031 * to be in range of 32bits address space. Otherwise, we should check 2032 * what DMA address is used and chain another descriptor for the 2033 * 64bits DMA operation. This also means descriptor ring size is 2034 * variable. Limiting DMA address to be in 32bit address space greatly 2035 * simplyfies descriptor handling and possibly would increase 2036 * performance a bit due to efficient handling of descriptors. 2037 * Apart from harassing checksum offloading mechanisms, it seems 2038 * it's really bad idea to use a seperate descriptor for 64bit 2039 * DMA operation to save small descriptor memory. Anyway, I've 2040 * never seen these exotic scheme on ethernet interface hardware. 2041 */ 2042 error = bus_dma_tag_create( 2043 bus_get_dma_tag(sc_if->msk_if_dev), /* parent */ 2044 1, 0, /* alignment, boundary */ 2045 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 2046 BUS_SPACE_MAXADDR, /* highaddr */ 2047 NULL, NULL, /* filter, filterarg */ 2048 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 2049 0, /* nsegments */ 2050 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 2051 0, /* flags */ 2052 NULL, NULL, /* lockfunc, lockarg */ 2053 &sc_if->msk_cdata.msk_parent_tag); 2054 if (error != 0) { 2055 device_printf(sc_if->msk_if_dev, 2056 "failed to create parent DMA tag\n"); 2057 goto fail; 2058 } 2059 /* Create tag for Tx ring. */ 2060 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2061 MSK_RING_ALIGN, 0, /* alignment, boundary */ 2062 BUS_SPACE_MAXADDR, /* lowaddr */ 2063 BUS_SPACE_MAXADDR, /* highaddr */ 2064 NULL, NULL, /* filter, filterarg */ 2065 MSK_TX_RING_SZ, /* maxsize */ 2066 1, /* nsegments */ 2067 MSK_TX_RING_SZ, /* maxsegsize */ 2068 0, /* flags */ 2069 NULL, NULL, /* lockfunc, lockarg */ 2070 &sc_if->msk_cdata.msk_tx_ring_tag); 2071 if (error != 0) { 2072 device_printf(sc_if->msk_if_dev, 2073 "failed to create Tx ring DMA tag\n"); 2074 goto fail; 2075 } 2076 2077 /* Create tag for Rx ring. */ 2078 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2079 MSK_RING_ALIGN, 0, /* alignment, boundary */ 2080 BUS_SPACE_MAXADDR, /* lowaddr */ 2081 BUS_SPACE_MAXADDR, /* highaddr */ 2082 NULL, NULL, /* filter, filterarg */ 2083 MSK_RX_RING_SZ, /* maxsize */ 2084 1, /* nsegments */ 2085 MSK_RX_RING_SZ, /* maxsegsize */ 2086 0, /* flags */ 2087 NULL, NULL, /* lockfunc, lockarg */ 2088 &sc_if->msk_cdata.msk_rx_ring_tag); 2089 if (error != 0) { 2090 device_printf(sc_if->msk_if_dev, 2091 "failed to create Rx ring DMA tag\n"); 2092 goto fail; 2093 } 2094 2095 /* Create tag for jumbo Rx ring. */ 2096 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2097 MSK_RING_ALIGN, 0, /* alignment, boundary */ 2098 BUS_SPACE_MAXADDR, /* lowaddr */ 2099 BUS_SPACE_MAXADDR, /* highaddr */ 2100 NULL, NULL, /* filter, filterarg */ 2101 MSK_JUMBO_RX_RING_SZ, /* maxsize */ 2102 1, /* nsegments */ 2103 MSK_JUMBO_RX_RING_SZ, /* maxsegsize */ 2104 0, /* flags */ 2105 NULL, NULL, /* lockfunc, lockarg */ 2106 &sc_if->msk_cdata.msk_jumbo_rx_ring_tag); 2107 if (error != 0) { 2108 device_printf(sc_if->msk_if_dev, 2109 "failed to create jumbo Rx ring DMA tag\n"); 2110 goto fail; 2111 } 2112 2113 /* Create tag for jumbo buffer blocks. */ 2114 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2115 PAGE_SIZE, 0, /* alignment, boundary */ 2116 BUS_SPACE_MAXADDR, /* lowaddr */ 2117 BUS_SPACE_MAXADDR, /* highaddr */ 2118 NULL, NULL, /* filter, filterarg */ 2119 MSK_JMEM, /* maxsize */ 2120 1, /* nsegments */ 2121 MSK_JMEM, /* maxsegsize */ 2122 0, /* flags */ 2123 NULL, NULL, /* lockfunc, lockarg */ 2124 &sc_if->msk_cdata.msk_jumbo_tag); 2125 if (error != 0) { 2126 device_printf(sc_if->msk_if_dev, 2127 "failed to create jumbo Rx buffer block DMA tag\n"); 2128 goto fail; 2129 } 2130 2131 /* Create tag for Tx buffers. */ 2132 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2133 1, 0, /* alignment, boundary */ 2134 BUS_SPACE_MAXADDR, /* lowaddr */ 2135 BUS_SPACE_MAXADDR, /* highaddr */ 2136 NULL, NULL, /* filter, filterarg */ 2137 MCLBYTES * MSK_MAXTXSEGS, /* maxsize */ 2138 MSK_MAXTXSEGS, /* nsegments */ 2139 MCLBYTES, /* maxsegsize */ 2140 0, /* flags */ 2141 NULL, NULL, /* lockfunc, lockarg */ 2142 &sc_if->msk_cdata.msk_tx_tag); 2143 if (error != 0) { 2144 device_printf(sc_if->msk_if_dev, 2145 "failed to create Tx DMA tag\n"); 2146 goto fail; 2147 } 2148 2149 /* Create tag for Rx buffers. */ 2150 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2151 1, 0, /* alignment, boundary */ 2152 BUS_SPACE_MAXADDR, /* lowaddr */ 2153 BUS_SPACE_MAXADDR, /* highaddr */ 2154 NULL, NULL, /* filter, filterarg */ 2155 MCLBYTES, /* maxsize */ 2156 1, /* nsegments */ 2157 MCLBYTES, /* maxsegsize */ 2158 0, /* flags */ 2159 NULL, NULL, /* lockfunc, lockarg */ 2160 &sc_if->msk_cdata.msk_rx_tag); 2161 if (error != 0) { 2162 device_printf(sc_if->msk_if_dev, 2163 "failed to create Rx DMA tag\n"); 2164 goto fail; 2165 } 2166 2167 /* Create tag for jumbo Rx buffers. */ 2168 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2169 PAGE_SIZE, 0, /* alignment, boundary */ 2170 BUS_SPACE_MAXADDR, /* lowaddr */ 2171 BUS_SPACE_MAXADDR, /* highaddr */ 2172 NULL, NULL, /* filter, filterarg */ 2173 MCLBYTES * MSK_MAXRXSEGS, /* maxsize */ 2174 MSK_MAXRXSEGS, /* nsegments */ 2175 MSK_JLEN, /* maxsegsize */ 2176 0, /* flags */ 2177 NULL, NULL, /* lockfunc, lockarg */ 2178 &sc_if->msk_cdata.msk_jumbo_rx_tag); 2179 if (error != 0) { 2180 device_printf(sc_if->msk_if_dev, 2181 "failed to create jumbo Rx DMA tag\n"); 2182 goto fail; 2183 } 2184 2185 /* Allocate DMA'able memory and load the DMA map for Tx ring. */ 2186 error = bus_dmamem_alloc(sc_if->msk_cdata.msk_tx_ring_tag, 2187 (void **)&sc_if->msk_rdata.msk_tx_ring, BUS_DMA_WAITOK | 2188 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc_if->msk_cdata.msk_tx_ring_map); 2189 if (error != 0) { 2190 device_printf(sc_if->msk_if_dev, 2191 "failed to allocate DMA'able memory for Tx ring\n"); 2192 goto fail; 2193 } 2194 2195 ctx.msk_busaddr = 0; 2196 error = bus_dmamap_load(sc_if->msk_cdata.msk_tx_ring_tag, 2197 sc_if->msk_cdata.msk_tx_ring_map, sc_if->msk_rdata.msk_tx_ring, 2198 MSK_TX_RING_SZ, msk_dmamap_cb, &ctx, 0); 2199 if (error != 0) { 2200 device_printf(sc_if->msk_if_dev, 2201 "failed to load DMA'able memory for Tx ring\n"); 2202 goto fail; 2203 } 2204 sc_if->msk_rdata.msk_tx_ring_paddr = ctx.msk_busaddr; 2205 2206 /* Allocate DMA'able memory and load the DMA map for Rx ring. */ 2207 error = bus_dmamem_alloc(sc_if->msk_cdata.msk_rx_ring_tag, 2208 (void **)&sc_if->msk_rdata.msk_rx_ring, BUS_DMA_WAITOK | 2209 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc_if->msk_cdata.msk_rx_ring_map); 2210 if (error != 0) { 2211 device_printf(sc_if->msk_if_dev, 2212 "failed to allocate DMA'able memory for Rx ring\n"); 2213 goto fail; 2214 } 2215 2216 ctx.msk_busaddr = 0; 2217 error = bus_dmamap_load(sc_if->msk_cdata.msk_rx_ring_tag, 2218 sc_if->msk_cdata.msk_rx_ring_map, sc_if->msk_rdata.msk_rx_ring, 2219 MSK_RX_RING_SZ, msk_dmamap_cb, &ctx, 0); 2220 if (error != 0) { 2221 device_printf(sc_if->msk_if_dev, 2222 "failed to load DMA'able memory for Rx ring\n"); 2223 goto fail; 2224 } 2225 sc_if->msk_rdata.msk_rx_ring_paddr = ctx.msk_busaddr; 2226 2227 /* Allocate DMA'able memory and load the DMA map for jumbo Rx ring. */ 2228 error = bus_dmamem_alloc(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 2229 (void **)&sc_if->msk_rdata.msk_jumbo_rx_ring, 2230 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 2231 &sc_if->msk_cdata.msk_jumbo_rx_ring_map); 2232 if (error != 0) { 2233 device_printf(sc_if->msk_if_dev, 2234 "failed to allocate DMA'able memory for jumbo Rx ring\n"); 2235 goto fail; 2236 } 2237 2238 ctx.msk_busaddr = 0; 2239 error = bus_dmamap_load(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 2240 sc_if->msk_cdata.msk_jumbo_rx_ring_map, 2241 sc_if->msk_rdata.msk_jumbo_rx_ring, MSK_JUMBO_RX_RING_SZ, 2242 msk_dmamap_cb, &ctx, 0); 2243 if (error != 0) { 2244 device_printf(sc_if->msk_if_dev, 2245 "failed to load DMA'able memory for jumbo Rx ring\n"); 2246 goto fail; 2247 } 2248 sc_if->msk_rdata.msk_jumbo_rx_ring_paddr = ctx.msk_busaddr; 2249 2250 /* Create DMA maps for Tx buffers. */ 2251 for (i = 0; i < MSK_TX_RING_CNT; i++) { 2252 txd = &sc_if->msk_cdata.msk_txdesc[i]; 2253 txd->tx_m = NULL; 2254 txd->tx_dmamap = NULL; 2255 error = bus_dmamap_create(sc_if->msk_cdata.msk_tx_tag, 0, 2256 &txd->tx_dmamap); 2257 if (error != 0) { 2258 device_printf(sc_if->msk_if_dev, 2259 "failed to create Tx dmamap\n"); 2260 goto fail; 2261 } 2262 } 2263 /* Create DMA maps for Rx buffers. */ 2264 if ((error = bus_dmamap_create(sc_if->msk_cdata.msk_rx_tag, 0, 2265 &sc_if->msk_cdata.msk_rx_sparemap)) != 0) { 2266 device_printf(sc_if->msk_if_dev, 2267 "failed to create spare Rx dmamap\n"); 2268 goto fail; 2269 } 2270 for (i = 0; i < MSK_RX_RING_CNT; i++) { 2271 rxd = &sc_if->msk_cdata.msk_rxdesc[i]; 2272 rxd->rx_m = NULL; 2273 rxd->rx_dmamap = NULL; 2274 error = bus_dmamap_create(sc_if->msk_cdata.msk_rx_tag, 0, 2275 &rxd->rx_dmamap); 2276 if (error != 0) { 2277 device_printf(sc_if->msk_if_dev, 2278 "failed to create Rx dmamap\n"); 2279 goto fail; 2280 } 2281 } 2282 /* Create DMA maps for jumbo Rx buffers. */ 2283 if ((error = bus_dmamap_create(sc_if->msk_cdata.msk_jumbo_rx_tag, 0, 2284 &sc_if->msk_cdata.msk_jumbo_rx_sparemap)) != 0) { 2285 device_printf(sc_if->msk_if_dev, 2286 "failed to create spare jumbo Rx dmamap\n"); 2287 goto fail; 2288 } 2289 for (i = 0; i < MSK_JUMBO_RX_RING_CNT; i++) { 2290 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[i]; 2291 jrxd->rx_m = NULL; 2292 jrxd->rx_dmamap = NULL; 2293 error = bus_dmamap_create(sc_if->msk_cdata.msk_jumbo_rx_tag, 0, 2294 &jrxd->rx_dmamap); 2295 if (error != 0) { 2296 device_printf(sc_if->msk_if_dev, 2297 "failed to create jumbo Rx dmamap\n"); 2298 goto fail; 2299 } 2300 } 2301 2302 /* Allocate DMA'able memory and load the DMA map for jumbo buf. */ 2303 error = bus_dmamem_alloc(sc_if->msk_cdata.msk_jumbo_tag, 2304 (void **)&sc_if->msk_rdata.msk_jumbo_buf, 2305 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 2306 &sc_if->msk_cdata.msk_jumbo_map); 2307 if (error != 0) { 2308 device_printf(sc_if->msk_if_dev, 2309 "failed to allocate DMA'able memory for jumbo buf\n"); 2310 goto fail; 2311 } 2312 2313 ctx.msk_busaddr = 0; 2314 error = bus_dmamap_load(sc_if->msk_cdata.msk_jumbo_tag, 2315 sc_if->msk_cdata.msk_jumbo_map, sc_if->msk_rdata.msk_jumbo_buf, 2316 MSK_JMEM, msk_dmamap_cb, &ctx, 0); 2317 if (error != 0) { 2318 device_printf(sc_if->msk_if_dev, 2319 "failed to load DMA'able memory for jumbobuf\n"); 2320 goto fail; 2321 } 2322 sc_if->msk_rdata.msk_jumbo_buf_paddr = ctx.msk_busaddr; 2323 2324 /* 2325 * Now divide it up into 9K pieces and save the addresses 2326 * in an array. 2327 */ 2328 ptr = sc_if->msk_rdata.msk_jumbo_buf; 2329 for (i = 0; i < MSK_JSLOTS; i++) { 2330 sc_if->msk_cdata.msk_jslots[i] = ptr; 2331 ptr += MSK_JLEN; 2332 entry = malloc(sizeof(struct msk_jpool_entry), 2333 M_DEVBUF, M_WAITOK); 2334 if (entry == NULL) { 2335 device_printf(sc_if->msk_if_dev, 2336 "no memory for jumbo buffers!\n"); 2337 error = ENOMEM; 2338 goto fail; 2339 } 2340 entry->slot = i; 2341 SLIST_INSERT_HEAD(&sc_if->msk_jfree_listhead, entry, 2342 jpool_entries); 2343 } 2344 2345 fail: 2346 return (error); 2347 } 2348 2349 static void 2350 msk_txrx_dma_free(struct msk_if_softc *sc_if) 2351 { 2352 struct msk_txdesc *txd; 2353 struct msk_rxdesc *rxd; 2354 struct msk_rxdesc *jrxd; 2355 struct msk_jpool_entry *entry; 2356 int i; 2357 2358 MSK_JLIST_LOCK(sc_if); 2359 while ((entry = SLIST_FIRST(&sc_if->msk_jinuse_listhead))) { 2360 device_printf(sc_if->msk_if_dev, 2361 "asked to free buffer that is in use!\n"); 2362 SLIST_REMOVE_HEAD(&sc_if->msk_jinuse_listhead, jpool_entries); 2363 SLIST_INSERT_HEAD(&sc_if->msk_jfree_listhead, entry, 2364 jpool_entries); 2365 } 2366 2367 while (!SLIST_EMPTY(&sc_if->msk_jfree_listhead)) { 2368 entry = SLIST_FIRST(&sc_if->msk_jfree_listhead); 2369 SLIST_REMOVE_HEAD(&sc_if->msk_jfree_listhead, jpool_entries); 2370 free(entry, M_DEVBUF); 2371 } 2372 MSK_JLIST_UNLOCK(sc_if); 2373 2374 /* Destroy jumbo buffer block. */ 2375 if (sc_if->msk_cdata.msk_jumbo_map) 2376 bus_dmamap_unload(sc_if->msk_cdata.msk_jumbo_tag, 2377 sc_if->msk_cdata.msk_jumbo_map); 2378 2379 if (sc_if->msk_rdata.msk_jumbo_buf) { 2380 bus_dmamem_free(sc_if->msk_cdata.msk_jumbo_tag, 2381 sc_if->msk_rdata.msk_jumbo_buf, 2382 sc_if->msk_cdata.msk_jumbo_map); 2383 sc_if->msk_rdata.msk_jumbo_buf = NULL; 2384 sc_if->msk_cdata.msk_jumbo_map = NULL; 2385 } 2386 2387 /* Tx ring. */ 2388 if (sc_if->msk_cdata.msk_tx_ring_tag) { 2389 if (sc_if->msk_cdata.msk_tx_ring_map) 2390 bus_dmamap_unload(sc_if->msk_cdata.msk_tx_ring_tag, 2391 sc_if->msk_cdata.msk_tx_ring_map); 2392 if (sc_if->msk_cdata.msk_tx_ring_map && 2393 sc_if->msk_rdata.msk_tx_ring) 2394 bus_dmamem_free(sc_if->msk_cdata.msk_tx_ring_tag, 2395 sc_if->msk_rdata.msk_tx_ring, 2396 sc_if->msk_cdata.msk_tx_ring_map); 2397 sc_if->msk_rdata.msk_tx_ring = NULL; 2398 sc_if->msk_cdata.msk_tx_ring_map = NULL; 2399 bus_dma_tag_destroy(sc_if->msk_cdata.msk_tx_ring_tag); 2400 sc_if->msk_cdata.msk_tx_ring_tag = NULL; 2401 } 2402 /* Rx ring. */ 2403 if (sc_if->msk_cdata.msk_rx_ring_tag) { 2404 if (sc_if->msk_cdata.msk_rx_ring_map) 2405 bus_dmamap_unload(sc_if->msk_cdata.msk_rx_ring_tag, 2406 sc_if->msk_cdata.msk_rx_ring_map); 2407 if (sc_if->msk_cdata.msk_rx_ring_map && 2408 sc_if->msk_rdata.msk_rx_ring) 2409 bus_dmamem_free(sc_if->msk_cdata.msk_rx_ring_tag, 2410 sc_if->msk_rdata.msk_rx_ring, 2411 sc_if->msk_cdata.msk_rx_ring_map); 2412 sc_if->msk_rdata.msk_rx_ring = NULL; 2413 sc_if->msk_cdata.msk_rx_ring_map = NULL; 2414 bus_dma_tag_destroy(sc_if->msk_cdata.msk_rx_ring_tag); 2415 sc_if->msk_cdata.msk_rx_ring_tag = NULL; 2416 } 2417 /* Jumbo Rx ring. */ 2418 if (sc_if->msk_cdata.msk_jumbo_rx_ring_tag) { 2419 if (sc_if->msk_cdata.msk_jumbo_rx_ring_map) 2420 bus_dmamap_unload(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 2421 sc_if->msk_cdata.msk_jumbo_rx_ring_map); 2422 if (sc_if->msk_cdata.msk_jumbo_rx_ring_map && 2423 sc_if->msk_rdata.msk_jumbo_rx_ring) 2424 bus_dmamem_free(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 2425 sc_if->msk_rdata.msk_jumbo_rx_ring, 2426 sc_if->msk_cdata.msk_jumbo_rx_ring_map); 2427 sc_if->msk_rdata.msk_jumbo_rx_ring = NULL; 2428 sc_if->msk_cdata.msk_jumbo_rx_ring_map = NULL; 2429 bus_dma_tag_destroy(sc_if->msk_cdata.msk_jumbo_rx_ring_tag); 2430 sc_if->msk_cdata.msk_jumbo_rx_ring_tag = NULL; 2431 } 2432 /* Tx buffers. */ 2433 if (sc_if->msk_cdata.msk_tx_tag) { 2434 for (i = 0; i < MSK_TX_RING_CNT; i++) { 2435 txd = &sc_if->msk_cdata.msk_txdesc[i]; 2436 if (txd->tx_dmamap) { 2437 bus_dmamap_destroy(sc_if->msk_cdata.msk_tx_tag, 2438 txd->tx_dmamap); 2439 txd->tx_dmamap = NULL; 2440 } 2441 } 2442 bus_dma_tag_destroy(sc_if->msk_cdata.msk_tx_tag); 2443 sc_if->msk_cdata.msk_tx_tag = NULL; 2444 } 2445 /* Rx buffers. */ 2446 if (sc_if->msk_cdata.msk_rx_tag) { 2447 for (i = 0; i < MSK_RX_RING_CNT; i++) { 2448 rxd = &sc_if->msk_cdata.msk_rxdesc[i]; 2449 if (rxd->rx_dmamap) { 2450 bus_dmamap_destroy(sc_if->msk_cdata.msk_rx_tag, 2451 rxd->rx_dmamap); 2452 rxd->rx_dmamap = NULL; 2453 } 2454 } 2455 if (sc_if->msk_cdata.msk_rx_sparemap) { 2456 bus_dmamap_destroy(sc_if->msk_cdata.msk_rx_tag, 2457 sc_if->msk_cdata.msk_rx_sparemap); 2458 sc_if->msk_cdata.msk_rx_sparemap = 0; 2459 } 2460 bus_dma_tag_destroy(sc_if->msk_cdata.msk_rx_tag); 2461 sc_if->msk_cdata.msk_rx_tag = NULL; 2462 } 2463 /* Jumbo Rx buffers. */ 2464 if (sc_if->msk_cdata.msk_jumbo_rx_tag) { 2465 for (i = 0; i < MSK_JUMBO_RX_RING_CNT; i++) { 2466 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[i]; 2467 if (jrxd->rx_dmamap) { 2468 bus_dmamap_destroy( 2469 sc_if->msk_cdata.msk_jumbo_rx_tag, 2470 jrxd->rx_dmamap); 2471 jrxd->rx_dmamap = NULL; 2472 } 2473 } 2474 if (sc_if->msk_cdata.msk_jumbo_rx_sparemap) { 2475 bus_dmamap_destroy(sc_if->msk_cdata.msk_jumbo_rx_tag, 2476 sc_if->msk_cdata.msk_jumbo_rx_sparemap); 2477 sc_if->msk_cdata.msk_jumbo_rx_sparemap = 0; 2478 } 2479 bus_dma_tag_destroy(sc_if->msk_cdata.msk_jumbo_rx_tag); 2480 sc_if->msk_cdata.msk_jumbo_rx_tag = NULL; 2481 } 2482 2483 if (sc_if->msk_cdata.msk_parent_tag) { 2484 bus_dma_tag_destroy(sc_if->msk_cdata.msk_parent_tag); 2485 sc_if->msk_cdata.msk_parent_tag = NULL; 2486 } 2487 mtx_destroy(&sc_if->msk_jlist_mtx); 2488 } 2489 2490 /* 2491 * Allocate a jumbo buffer. 2492 */ 2493 static void * 2494 msk_jalloc(struct msk_if_softc *sc_if) 2495 { 2496 struct msk_jpool_entry *entry; 2497 2498 MSK_JLIST_LOCK(sc_if); 2499 2500 entry = SLIST_FIRST(&sc_if->msk_jfree_listhead); 2501 2502 if (entry == NULL) { 2503 MSK_JLIST_UNLOCK(sc_if); 2504 return (NULL); 2505 } 2506 2507 SLIST_REMOVE_HEAD(&sc_if->msk_jfree_listhead, jpool_entries); 2508 SLIST_INSERT_HEAD(&sc_if->msk_jinuse_listhead, entry, jpool_entries); 2509 2510 MSK_JLIST_UNLOCK(sc_if); 2511 2512 return (sc_if->msk_cdata.msk_jslots[entry->slot]); 2513 } 2514 2515 /* 2516 * Release a jumbo buffer. 2517 */ 2518 static void 2519 msk_jfree(void *buf, void *args) 2520 { 2521 struct msk_if_softc *sc_if; 2522 struct msk_jpool_entry *entry; 2523 int i; 2524 2525 /* Extract the softc struct pointer. */ 2526 sc_if = (struct msk_if_softc *)args; 2527 KASSERT(sc_if != NULL, ("%s: can't find softc pointer!", __func__)); 2528 2529 MSK_JLIST_LOCK(sc_if); 2530 /* Calculate the slot this buffer belongs to. */ 2531 i = ((vm_offset_t)buf 2532 - (vm_offset_t)sc_if->msk_rdata.msk_jumbo_buf) / MSK_JLEN; 2533 KASSERT(i >= 0 && i < MSK_JSLOTS, 2534 ("%s: asked to free buffer that we don't manage!", __func__)); 2535 2536 entry = SLIST_FIRST(&sc_if->msk_jinuse_listhead); 2537 KASSERT(entry != NULL, ("%s: buffer not in use!", __func__)); 2538 entry->slot = i; 2539 SLIST_REMOVE_HEAD(&sc_if->msk_jinuse_listhead, jpool_entries); 2540 SLIST_INSERT_HEAD(&sc_if->msk_jfree_listhead, entry, jpool_entries); 2541 if (SLIST_EMPTY(&sc_if->msk_jinuse_listhead)) 2542 wakeup(sc_if); 2543 2544 MSK_JLIST_UNLOCK(sc_if); 2545 } 2546 2547 /* 2548 * It's copy of ath_defrag(ath(4)). 2549 * 2550 * Defragment an mbuf chain, returning at most maxfrags separate 2551 * mbufs+clusters. If this is not possible NULL is returned and 2552 * the original mbuf chain is left in it's present (potentially 2553 * modified) state. We use two techniques: collapsing consecutive 2554 * mbufs and replacing consecutive mbufs by a cluster. 2555 */ 2556 static struct mbuf * 2557 msk_defrag(struct mbuf *m0, int how, int maxfrags) 2558 { 2559 struct mbuf *m, *n, *n2, **prev; 2560 u_int curfrags; 2561 2562 /* 2563 * Calculate the current number of frags. 2564 */ 2565 curfrags = 0; 2566 for (m = m0; m != NULL; m = m->m_next) 2567 curfrags++; 2568 /* 2569 * First, try to collapse mbufs. Note that we always collapse 2570 * towards the front so we don't need to deal with moving the 2571 * pkthdr. This may be suboptimal if the first mbuf has much 2572 * less data than the following. 2573 */ 2574 m = m0; 2575 again: 2576 for (;;) { 2577 n = m->m_next; 2578 if (n == NULL) 2579 break; 2580 if ((m->m_flags & M_RDONLY) == 0 && 2581 n->m_len < M_TRAILINGSPACE(m)) { 2582 bcopy(mtod(n, void *), mtod(m, char *) + m->m_len, 2583 n->m_len); 2584 m->m_len += n->m_len; 2585 m->m_next = n->m_next; 2586 m_free(n); 2587 if (--curfrags <= maxfrags) 2588 return (m0); 2589 } else 2590 m = n; 2591 } 2592 KASSERT(maxfrags > 1, 2593 ("maxfrags %u, but normal collapse failed", maxfrags)); 2594 /* 2595 * Collapse consecutive mbufs to a cluster. 2596 */ 2597 prev = &m0->m_next; /* NB: not the first mbuf */ 2598 while ((n = *prev) != NULL) { 2599 if ((n2 = n->m_next) != NULL && 2600 n->m_len + n2->m_len < MCLBYTES) { 2601 m = m_getcl(how, MT_DATA, 0); 2602 if (m == NULL) 2603 goto bad; 2604 bcopy(mtod(n, void *), mtod(m, void *), n->m_len); 2605 bcopy(mtod(n2, void *), mtod(m, char *) + n->m_len, 2606 n2->m_len); 2607 m->m_len = n->m_len + n2->m_len; 2608 m->m_next = n2->m_next; 2609 *prev = m; 2610 m_free(n); 2611 m_free(n2); 2612 if (--curfrags <= maxfrags) /* +1 cl -2 mbufs */ 2613 return m0; 2614 /* 2615 * Still not there, try the normal collapse 2616 * again before we allocate another cluster. 2617 */ 2618 goto again; 2619 } 2620 prev = &n->m_next; 2621 } 2622 /* 2623 * No place where we can collapse to a cluster; punt. 2624 * This can occur if, for example, you request 2 frags 2625 * but the packet requires that both be clusters (we 2626 * never reallocate the first mbuf to avoid moving the 2627 * packet header). 2628 */ 2629 bad: 2630 return (NULL); 2631 } 2632 2633 static int 2634 msk_encap(struct msk_if_softc *sc_if, struct mbuf **m_head) 2635 { 2636 struct msk_txdesc *txd, *txd_last; 2637 struct msk_tx_desc *tx_le; 2638 struct mbuf *m; 2639 bus_dmamap_t map; 2640 bus_dma_segment_t txsegs[MSK_MAXTXSEGS]; 2641 uint32_t control, prod, si; 2642 uint16_t offset, tcp_offset, tso_mtu; 2643 int error, i, nseg, tso; 2644 2645 MSK_IF_LOCK_ASSERT(sc_if); 2646 2647 tcp_offset = offset = 0; 2648 m = *m_head; 2649 if ((m->m_pkthdr.csum_flags & (MSK_CSUM_FEATURES | CSUM_TSO)) != 0) { 2650 /* 2651 * Since mbuf has no protocol specific structure information 2652 * in it we have to inspect protocol information here to 2653 * setup TSO and checksum offload. I don't know why Marvell 2654 * made a such decision in chip design because other GigE 2655 * hardwares normally takes care of all these chores in 2656 * hardware. However, TSO performance of Yukon II is very 2657 * good such that it's worth to implement it. 2658 */ 2659 struct ether_header *eh; 2660 struct ip *ip; 2661 struct tcphdr *tcp; 2662 2663 /* TODO check for M_WRITABLE(m) */ 2664 2665 offset = sizeof(struct ether_header); 2666 m = m_pullup(m, offset); 2667 if (m == NULL) { 2668 *m_head = NULL; 2669 return (ENOBUFS); 2670 } 2671 eh = mtod(m, struct ether_header *); 2672 /* Check if hardware VLAN insertion is off. */ 2673 if (eh->ether_type == htons(ETHERTYPE_VLAN)) { 2674 offset = sizeof(struct ether_vlan_header); 2675 m = m_pullup(m, offset); 2676 if (m == NULL) { 2677 *m_head = NULL; 2678 return (ENOBUFS); 2679 } 2680 } 2681 m = m_pullup(m, offset + sizeof(struct ip)); 2682 if (m == NULL) { 2683 *m_head = NULL; 2684 return (ENOBUFS); 2685 } 2686 ip = (struct ip *)(mtod(m, char *) + offset); 2687 offset += (ip->ip_hl << 2); 2688 tcp_offset = offset; 2689 /* 2690 * It seems that Yukon II has Tx checksum offload bug for 2691 * small TCP packets that's less than 60 bytes in size 2692 * (e.g. TCP window probe packet, pure ACK packet). 2693 * Common work around like padding with zeros to make the 2694 * frame minimum ethernet frame size didn't work at all. 2695 * Instead of disabling checksum offload completely we 2696 * resort to S/W checksum routine when we encounter short 2697 * TCP frames. 2698 * Short UDP packets appear to be handled correctly by 2699 * Yukon II. 2700 */ 2701 if (m->m_pkthdr.len < MSK_MIN_FRAMELEN && 2702 (m->m_pkthdr.csum_flags & CSUM_TCP) != 0) { 2703 uint16_t csum; 2704 2705 csum = in_cksum_skip(m, ntohs(ip->ip_len) + offset - 2706 (ip->ip_hl << 2), offset); 2707 *(uint16_t *)(m->m_data + offset + 2708 m->m_pkthdr.csum_data) = csum; 2709 m->m_pkthdr.csum_flags &= ~CSUM_TCP; 2710 } 2711 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 2712 m = m_pullup(m, offset + sizeof(struct tcphdr)); 2713 if (m == NULL) { 2714 *m_head = NULL; 2715 return (ENOBUFS); 2716 } 2717 tcp = (struct tcphdr *)(mtod(m, char *) + offset); 2718 offset += (tcp->th_off << 2); 2719 } 2720 *m_head = m; 2721 } 2722 2723 prod = sc_if->msk_cdata.msk_tx_prod; 2724 txd = &sc_if->msk_cdata.msk_txdesc[prod]; 2725 txd_last = txd; 2726 map = txd->tx_dmamap; 2727 error = bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_tx_tag, map, 2728 *m_head, txsegs, &nseg, BUS_DMA_NOWAIT); 2729 if (error == EFBIG) { 2730 m = msk_defrag(*m_head, M_DONTWAIT, MSK_MAXTXSEGS); 2731 if (m == NULL) { 2732 m_freem(*m_head); 2733 *m_head = NULL; 2734 return (ENOBUFS); 2735 } 2736 *m_head = m; 2737 error = bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_tx_tag, 2738 map, *m_head, txsegs, &nseg, BUS_DMA_NOWAIT); 2739 if (error != 0) { 2740 m_freem(*m_head); 2741 *m_head = NULL; 2742 return (error); 2743 } 2744 } else if (error != 0) 2745 return (error); 2746 if (nseg == 0) { 2747 m_freem(*m_head); 2748 *m_head = NULL; 2749 return (EIO); 2750 } 2751 2752 /* Check number of available descriptors. */ 2753 if (sc_if->msk_cdata.msk_tx_cnt + nseg >= 2754 (MSK_TX_RING_CNT - MSK_RESERVED_TX_DESC_CNT)) { 2755 bus_dmamap_unload(sc_if->msk_cdata.msk_tx_tag, map); 2756 return (ENOBUFS); 2757 } 2758 2759 control = 0; 2760 tso = 0; 2761 tx_le = NULL; 2762 2763 /* Check TSO support. */ 2764 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 2765 tso_mtu = offset + m->m_pkthdr.tso_segsz; 2766 if (tso_mtu != sc_if->msk_cdata.msk_tso_mtu) { 2767 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2768 tx_le->msk_addr = htole32(tso_mtu); 2769 tx_le->msk_control = htole32(OP_LRGLEN | HW_OWNER); 2770 sc_if->msk_cdata.msk_tx_cnt++; 2771 MSK_INC(prod, MSK_TX_RING_CNT); 2772 sc_if->msk_cdata.msk_tso_mtu = tso_mtu; 2773 } 2774 tso++; 2775 } 2776 /* Check if we have a VLAN tag to insert. */ 2777 if ((m->m_flags & M_VLANTAG) != 0) { 2778 if (tso == 0) { 2779 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2780 tx_le->msk_addr = htole32(0); 2781 tx_le->msk_control = htole32(OP_VLAN | HW_OWNER | 2782 htons(m->m_pkthdr.ether_vtag)); 2783 sc_if->msk_cdata.msk_tx_cnt++; 2784 MSK_INC(prod, MSK_TX_RING_CNT); 2785 } else { 2786 tx_le->msk_control |= htole32(OP_VLAN | 2787 htons(m->m_pkthdr.ether_vtag)); 2788 } 2789 control |= INS_VLAN; 2790 } 2791 /* Check if we have to handle checksum offload. */ 2792 if (tso == 0 && (m->m_pkthdr.csum_flags & MSK_CSUM_FEATURES) != 0) { 2793 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2794 tx_le->msk_addr = htole32(((tcp_offset + m->m_pkthdr.csum_data) 2795 & 0xffff) | ((uint32_t)tcp_offset << 16)); 2796 tx_le->msk_control = htole32(1 << 16 | (OP_TCPLISW | HW_OWNER)); 2797 control = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM; 2798 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0) 2799 control |= UDPTCP; 2800 sc_if->msk_cdata.msk_tx_cnt++; 2801 MSK_INC(prod, MSK_TX_RING_CNT); 2802 } 2803 2804 si = prod; 2805 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2806 tx_le->msk_addr = htole32(MSK_ADDR_LO(txsegs[0].ds_addr)); 2807 if (tso == 0) 2808 tx_le->msk_control = htole32(txsegs[0].ds_len | control | 2809 OP_PACKET); 2810 else 2811 tx_le->msk_control = htole32(txsegs[0].ds_len | control | 2812 OP_LARGESEND); 2813 sc_if->msk_cdata.msk_tx_cnt++; 2814 MSK_INC(prod, MSK_TX_RING_CNT); 2815 2816 for (i = 1; i < nseg; i++) { 2817 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2818 tx_le->msk_addr = htole32(MSK_ADDR_LO(txsegs[i].ds_addr)); 2819 tx_le->msk_control = htole32(txsegs[i].ds_len | control | 2820 OP_BUFFER | HW_OWNER); 2821 sc_if->msk_cdata.msk_tx_cnt++; 2822 MSK_INC(prod, MSK_TX_RING_CNT); 2823 } 2824 /* Update producer index. */ 2825 sc_if->msk_cdata.msk_tx_prod = prod; 2826 2827 /* Set EOP on the last desciptor. */ 2828 prod = (prod + MSK_TX_RING_CNT - 1) % MSK_TX_RING_CNT; 2829 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2830 tx_le->msk_control |= htole32(EOP); 2831 2832 /* Turn the first descriptor ownership to hardware. */ 2833 tx_le = &sc_if->msk_rdata.msk_tx_ring[si]; 2834 tx_le->msk_control |= htole32(HW_OWNER); 2835 2836 txd = &sc_if->msk_cdata.msk_txdesc[prod]; 2837 map = txd_last->tx_dmamap; 2838 txd_last->tx_dmamap = txd->tx_dmamap; 2839 txd->tx_dmamap = map; 2840 txd->tx_m = m; 2841 2842 /* Sync descriptors. */ 2843 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_tag, map, BUS_DMASYNC_PREWRITE); 2844 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_ring_tag, 2845 sc_if->msk_cdata.msk_tx_ring_map, 2846 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2847 2848 return (0); 2849 } 2850 2851 static void 2852 msk_tx_task(void *arg, int pending) 2853 { 2854 struct ifnet *ifp; 2855 2856 ifp = arg; 2857 msk_start(ifp); 2858 } 2859 2860 static void 2861 msk_start(struct ifnet *ifp) 2862 { 2863 struct msk_if_softc *sc_if; 2864 struct mbuf *m_head; 2865 int enq; 2866 2867 sc_if = ifp->if_softc; 2868 2869 MSK_IF_LOCK(sc_if); 2870 2871 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2872 IFF_DRV_RUNNING || sc_if->msk_link == 0) { 2873 MSK_IF_UNLOCK(sc_if); 2874 return; 2875 } 2876 2877 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 2878 sc_if->msk_cdata.msk_tx_cnt < 2879 (MSK_TX_RING_CNT - MSK_RESERVED_TX_DESC_CNT); ) { 2880 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2881 if (m_head == NULL) 2882 break; 2883 /* 2884 * Pack the data into the transmit ring. If we 2885 * don't have room, set the OACTIVE flag and wait 2886 * for the NIC to drain the ring. 2887 */ 2888 if (msk_encap(sc_if, &m_head) != 0) { 2889 if (m_head == NULL) 2890 break; 2891 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2892 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2893 break; 2894 } 2895 2896 enq++; 2897 /* 2898 * If there's a BPF listener, bounce a copy of this frame 2899 * to him. 2900 */ 2901 ETHER_BPF_MTAP(ifp, m_head); 2902 } 2903 2904 if (enq > 0) { 2905 /* Transmit */ 2906 CSR_WRITE_2(sc_if->msk_softc, 2907 Y2_PREF_Q_ADDR(sc_if->msk_txq, PREF_UNIT_PUT_IDX_REG), 2908 sc_if->msk_cdata.msk_tx_prod); 2909 2910 /* Set a timeout in case the chip goes out to lunch. */ 2911 sc_if->msk_watchdog_timer = MSK_TX_TIMEOUT; 2912 } 2913 2914 MSK_IF_UNLOCK(sc_if); 2915 } 2916 2917 static void 2918 msk_watchdog(struct msk_if_softc *sc_if) 2919 { 2920 struct ifnet *ifp; 2921 uint32_t ridx; 2922 int idx; 2923 2924 MSK_IF_LOCK_ASSERT(sc_if); 2925 2926 if (sc_if->msk_watchdog_timer == 0 || --sc_if->msk_watchdog_timer) 2927 return; 2928 ifp = sc_if->msk_ifp; 2929 if (sc_if->msk_link == 0) { 2930 if (bootverbose) 2931 if_printf(sc_if->msk_ifp, "watchdog timeout " 2932 "(missed link)\n"); 2933 ifp->if_oerrors++; 2934 msk_init_locked(sc_if); 2935 return; 2936 } 2937 2938 /* 2939 * Reclaim first as there is a possibility of losing Tx completion 2940 * interrupts. 2941 */ 2942 ridx = sc_if->msk_port == MSK_PORT_A ? STAT_TXA1_RIDX : STAT_TXA2_RIDX; 2943 idx = CSR_READ_2(sc_if->msk_softc, ridx); 2944 if (sc_if->msk_cdata.msk_tx_cons != idx) { 2945 msk_txeof(sc_if, idx); 2946 if (sc_if->msk_cdata.msk_tx_cnt == 0) { 2947 if_printf(ifp, "watchdog timeout (missed Tx interrupts) " 2948 "-- recovering\n"); 2949 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2950 taskqueue_enqueue(taskqueue_fast, 2951 &sc_if->msk_tx_task); 2952 return; 2953 } 2954 } 2955 2956 if_printf(ifp, "watchdog timeout\n"); 2957 ifp->if_oerrors++; 2958 msk_init_locked(sc_if); 2959 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2960 taskqueue_enqueue(taskqueue_fast, &sc_if->msk_tx_task); 2961 } 2962 2963 static void 2964 mskc_shutdown(device_t dev) 2965 { 2966 struct msk_softc *sc; 2967 int i; 2968 2969 sc = device_get_softc(dev); 2970 MSK_LOCK(sc); 2971 for (i = 0; i < sc->msk_num_port; i++) { 2972 if (sc->msk_if[i] != NULL) 2973 msk_stop(sc->msk_if[i]); 2974 } 2975 2976 /* Disable all interrupts. */ 2977 CSR_WRITE_4(sc, B0_IMSK, 0); 2978 CSR_READ_4(sc, B0_IMSK); 2979 CSR_WRITE_4(sc, B0_HWE_IMSK, 0); 2980 CSR_READ_4(sc, B0_HWE_IMSK); 2981 2982 /* Put hardware reset. */ 2983 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); 2984 2985 MSK_UNLOCK(sc); 2986 } 2987 2988 static int 2989 mskc_suspend(device_t dev) 2990 { 2991 struct msk_softc *sc; 2992 int i; 2993 2994 sc = device_get_softc(dev); 2995 2996 MSK_LOCK(sc); 2997 2998 for (i = 0; i < sc->msk_num_port; i++) { 2999 if (sc->msk_if[i] != NULL && sc->msk_if[i]->msk_ifp != NULL && 3000 ((sc->msk_if[i]->msk_ifp->if_drv_flags & 3001 IFF_DRV_RUNNING) != 0)) 3002 msk_stop(sc->msk_if[i]); 3003 } 3004 3005 /* Disable all interrupts. */ 3006 CSR_WRITE_4(sc, B0_IMSK, 0); 3007 CSR_READ_4(sc, B0_IMSK); 3008 CSR_WRITE_4(sc, B0_HWE_IMSK, 0); 3009 CSR_READ_4(sc, B0_HWE_IMSK); 3010 3011 msk_phy_power(sc, MSK_PHY_POWERDOWN); 3012 3013 /* Put hardware reset. */ 3014 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); 3015 sc->msk_suspended = 1; 3016 3017 MSK_UNLOCK(sc); 3018 3019 return (0); 3020 } 3021 3022 static int 3023 mskc_resume(device_t dev) 3024 { 3025 struct msk_softc *sc; 3026 int i; 3027 3028 sc = device_get_softc(dev); 3029 3030 MSK_LOCK(sc); 3031 3032 mskc_reset(sc); 3033 for (i = 0; i < sc->msk_num_port; i++) { 3034 if (sc->msk_if[i] != NULL && sc->msk_if[i]->msk_ifp != NULL && 3035 ((sc->msk_if[i]->msk_ifp->if_flags & IFF_UP) != 0)) 3036 msk_init_locked(sc->msk_if[i]); 3037 } 3038 sc->msk_suspended = 0; 3039 3040 MSK_UNLOCK(sc); 3041 3042 return (0); 3043 } 3044 3045 static void 3046 msk_rxeof(struct msk_if_softc *sc_if, uint32_t status, int len) 3047 { 3048 struct mbuf *m; 3049 struct ifnet *ifp; 3050 struct msk_rxdesc *rxd; 3051 int cons, rxlen; 3052 3053 ifp = sc_if->msk_ifp; 3054 3055 MSK_IF_LOCK_ASSERT(sc_if); 3056 3057 cons = sc_if->msk_cdata.msk_rx_cons; 3058 do { 3059 rxlen = status >> 16; 3060 if ((status & GMR_FS_VLAN) != 0 && 3061 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 3062 rxlen -= ETHER_VLAN_ENCAP_LEN; 3063 if (len > sc_if->msk_framesize || 3064 ((status & GMR_FS_ANY_ERR) != 0) || 3065 ((status & GMR_FS_RX_OK) == 0) || (rxlen != len)) { 3066 /* Don't count flow-control packet as errors. */ 3067 if ((status & GMR_FS_GOOD_FC) == 0) 3068 ifp->if_ierrors++; 3069 msk_discard_rxbuf(sc_if, cons); 3070 break; 3071 } 3072 rxd = &sc_if->msk_cdata.msk_rxdesc[cons]; 3073 m = rxd->rx_m; 3074 if (msk_newbuf(sc_if, cons) != 0) { 3075 ifp->if_iqdrops++; 3076 /* Reuse old buffer. */ 3077 msk_discard_rxbuf(sc_if, cons); 3078 break; 3079 } 3080 m->m_pkthdr.rcvif = ifp; 3081 m->m_pkthdr.len = m->m_len = len; 3082 ifp->if_ipackets++; 3083 /* Check for VLAN tagged packets. */ 3084 if ((status & GMR_FS_VLAN) != 0 && 3085 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) { 3086 m->m_pkthdr.ether_vtag = sc_if->msk_vtag; 3087 m->m_flags |= M_VLANTAG; 3088 } 3089 MSK_IF_UNLOCK(sc_if); 3090 (*ifp->if_input)(ifp, m); 3091 MSK_IF_LOCK(sc_if); 3092 } while (0); 3093 3094 MSK_INC(sc_if->msk_cdata.msk_rx_cons, MSK_RX_RING_CNT); 3095 MSK_INC(sc_if->msk_cdata.msk_rx_prod, MSK_RX_RING_CNT); 3096 } 3097 3098 static void 3099 msk_jumbo_rxeof(struct msk_if_softc *sc_if, uint32_t status, int len) 3100 { 3101 struct mbuf *m; 3102 struct ifnet *ifp; 3103 struct msk_rxdesc *jrxd; 3104 int cons, rxlen; 3105 3106 ifp = sc_if->msk_ifp; 3107 3108 MSK_IF_LOCK_ASSERT(sc_if); 3109 3110 cons = sc_if->msk_cdata.msk_rx_cons; 3111 do { 3112 rxlen = status >> 16; 3113 if ((status & GMR_FS_VLAN) != 0 && 3114 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 3115 rxlen -= ETHER_VLAN_ENCAP_LEN; 3116 if (len > sc_if->msk_framesize || 3117 ((status & GMR_FS_ANY_ERR) != 0) || 3118 ((status & GMR_FS_RX_OK) == 0) || (rxlen != len)) { 3119 /* Don't count flow-control packet as errors. */ 3120 if ((status & GMR_FS_GOOD_FC) == 0) 3121 ifp->if_ierrors++; 3122 msk_discard_jumbo_rxbuf(sc_if, cons); 3123 break; 3124 } 3125 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[cons]; 3126 m = jrxd->rx_m; 3127 if (msk_jumbo_newbuf(sc_if, cons) != 0) { 3128 ifp->if_iqdrops++; 3129 /* Reuse old buffer. */ 3130 msk_discard_jumbo_rxbuf(sc_if, cons); 3131 break; 3132 } 3133 m->m_pkthdr.rcvif = ifp; 3134 m->m_pkthdr.len = m->m_len = len; 3135 ifp->if_ipackets++; 3136 /* Check for VLAN tagged packets. */ 3137 if ((status & GMR_FS_VLAN) != 0 && 3138 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) { 3139 m->m_pkthdr.ether_vtag = sc_if->msk_vtag; 3140 m->m_flags |= M_VLANTAG; 3141 } 3142 MSK_IF_UNLOCK(sc_if); 3143 (*ifp->if_input)(ifp, m); 3144 MSK_IF_LOCK(sc_if); 3145 } while (0); 3146 3147 MSK_INC(sc_if->msk_cdata.msk_rx_cons, MSK_JUMBO_RX_RING_CNT); 3148 MSK_INC(sc_if->msk_cdata.msk_rx_prod, MSK_JUMBO_RX_RING_CNT); 3149 } 3150 3151 static void 3152 msk_txeof(struct msk_if_softc *sc_if, int idx) 3153 { 3154 struct msk_txdesc *txd; 3155 struct msk_tx_desc *cur_tx; 3156 struct ifnet *ifp; 3157 uint32_t control; 3158 int cons, prog; 3159 3160 MSK_IF_LOCK_ASSERT(sc_if); 3161 3162 ifp = sc_if->msk_ifp; 3163 3164 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_ring_tag, 3165 sc_if->msk_cdata.msk_tx_ring_map, 3166 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3167 /* 3168 * Go through our tx ring and free mbufs for those 3169 * frames that have been sent. 3170 */ 3171 cons = sc_if->msk_cdata.msk_tx_cons; 3172 prog = 0; 3173 for (; cons != idx; MSK_INC(cons, MSK_TX_RING_CNT)) { 3174 if (sc_if->msk_cdata.msk_tx_cnt <= 0) 3175 break; 3176 prog++; 3177 cur_tx = &sc_if->msk_rdata.msk_tx_ring[cons]; 3178 control = le32toh(cur_tx->msk_control); 3179 sc_if->msk_cdata.msk_tx_cnt--; 3180 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3181 if ((control & EOP) == 0) 3182 continue; 3183 txd = &sc_if->msk_cdata.msk_txdesc[cons]; 3184 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_tag, txd->tx_dmamap, 3185 BUS_DMASYNC_POSTWRITE); 3186 bus_dmamap_unload(sc_if->msk_cdata.msk_tx_tag, txd->tx_dmamap); 3187 3188 ifp->if_opackets++; 3189 KASSERT(txd->tx_m != NULL, ("%s: freeing NULL mbuf!", 3190 __func__)); 3191 m_freem(txd->tx_m); 3192 txd->tx_m = NULL; 3193 } 3194 3195 if (prog > 0) { 3196 sc_if->msk_cdata.msk_tx_cons = cons; 3197 if (sc_if->msk_cdata.msk_tx_cnt == 0) 3198 sc_if->msk_watchdog_timer = 0; 3199 /* No need to sync LEs as we didn't update LEs. */ 3200 } 3201 } 3202 3203 static void 3204 msk_tick(void *xsc_if) 3205 { 3206 struct msk_if_softc *sc_if; 3207 struct mii_data *mii; 3208 3209 sc_if = xsc_if; 3210 3211 MSK_IF_LOCK_ASSERT(sc_if); 3212 3213 mii = device_get_softc(sc_if->msk_miibus); 3214 3215 mii_tick(mii); 3216 msk_watchdog(sc_if); 3217 callout_reset(&sc_if->msk_tick_ch, hz, msk_tick, sc_if); 3218 } 3219 3220 static void 3221 msk_intr_phy(struct msk_if_softc *sc_if) 3222 { 3223 uint16_t status; 3224 3225 if (sc_if->msk_softc->msk_marvell_phy) { 3226 msk_phy_readreg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_STAT); 3227 status = msk_phy_readreg(sc_if, PHY_ADDR_MARV, 3228 PHY_MARV_INT_STAT); 3229 /* Handle FIFO Underrun/Overflow? */ 3230 if ((status & PHY_M_IS_FIFO_ERROR)) 3231 device_printf(sc_if->msk_if_dev, 3232 "PHY FIFO underrun/overflow.\n"); 3233 } 3234 } 3235 3236 static void 3237 msk_intr_gmac(struct msk_if_softc *sc_if) 3238 { 3239 struct msk_softc *sc; 3240 uint8_t status; 3241 3242 sc = sc_if->msk_softc; 3243 status = CSR_READ_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_SRC)); 3244 3245 /* GMAC Rx FIFO overrun. */ 3246 if ((status & GM_IS_RX_FF_OR) != 0) { 3247 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), 3248 GMF_CLI_RX_FO); 3249 device_printf(sc_if->msk_if_dev, "Rx FIFO overrun!\n"); 3250 } 3251 /* GMAC Tx FIFO underrun. */ 3252 if ((status & GM_IS_TX_FF_UR) != 0) { 3253 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 3254 GMF_CLI_TX_FU); 3255 device_printf(sc_if->msk_if_dev, "Tx FIFO underrun!\n"); 3256 /* 3257 * XXX 3258 * In case of Tx underrun, we may need to flush/reset 3259 * Tx MAC but that would also require resynchronization 3260 * with status LEs. Reintializing status LEs would 3261 * affect other port in dual MAC configuration so it 3262 * should be avoided as possible as we can. 3263 * Due to lack of documentation it's all vague guess but 3264 * it needs more investigation. 3265 */ 3266 } 3267 } 3268 3269 static void 3270 msk_handle_hwerr(struct msk_if_softc *sc_if, uint32_t status) 3271 { 3272 struct msk_softc *sc; 3273 3274 sc = sc_if->msk_softc; 3275 if ((status & Y2_IS_PAR_RD1) != 0) { 3276 device_printf(sc_if->msk_if_dev, 3277 "RAM buffer read parity error\n"); 3278 /* Clear IRQ. */ 3279 CSR_WRITE_2(sc, SELECT_RAM_BUFFER(sc_if->msk_port, B3_RI_CTRL), 3280 RI_CLR_RD_PERR); 3281 } 3282 if ((status & Y2_IS_PAR_WR1) != 0) { 3283 device_printf(sc_if->msk_if_dev, 3284 "RAM buffer write parity error\n"); 3285 /* Clear IRQ. */ 3286 CSR_WRITE_2(sc, SELECT_RAM_BUFFER(sc_if->msk_port, B3_RI_CTRL), 3287 RI_CLR_WR_PERR); 3288 } 3289 if ((status & Y2_IS_PAR_MAC1) != 0) { 3290 device_printf(sc_if->msk_if_dev, "Tx MAC parity error\n"); 3291 /* Clear IRQ. */ 3292 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 3293 GMF_CLI_TX_PE); 3294 } 3295 if ((status & Y2_IS_PAR_RX1) != 0) { 3296 device_printf(sc_if->msk_if_dev, "Rx parity error\n"); 3297 /* Clear IRQ. */ 3298 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_CLR_IRQ_PAR); 3299 } 3300 if ((status & (Y2_IS_TCP_TXS1 | Y2_IS_TCP_TXA1)) != 0) { 3301 device_printf(sc_if->msk_if_dev, "TCP segmentation error\n"); 3302 /* Clear IRQ. */ 3303 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_CLR_IRQ_TCP); 3304 } 3305 } 3306 3307 static void 3308 msk_intr_hwerr(struct msk_softc *sc) 3309 { 3310 uint32_t status; 3311 uint32_t tlphead[4]; 3312 3313 status = CSR_READ_4(sc, B0_HWE_ISRC); 3314 /* Time Stamp timer overflow. */ 3315 if ((status & Y2_IS_TIST_OV) != 0) 3316 CSR_WRITE_1(sc, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ); 3317 if ((status & Y2_IS_PCI_NEXP) != 0) { 3318 /* 3319 * PCI Express Error occured which is not described in PEX 3320 * spec. 3321 * This error is also mapped either to Master Abort( 3322 * Y2_IS_MST_ERR) or Target Abort (Y2_IS_IRQ_STAT) bit and 3323 * can only be cleared there. 3324 */ 3325 device_printf(sc->msk_dev, 3326 "PCI Express protocol violation error\n"); 3327 } 3328 3329 if ((status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) != 0) { 3330 uint16_t v16; 3331 3332 if ((status & Y2_IS_MST_ERR) != 0) 3333 device_printf(sc->msk_dev, 3334 "unexpected IRQ Status error\n"); 3335 else 3336 device_printf(sc->msk_dev, 3337 "unexpected IRQ Master error\n"); 3338 /* Reset all bits in the PCI status register. */ 3339 v16 = pci_read_config(sc->msk_dev, PCIR_STATUS, 2); 3340 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON); 3341 pci_write_config(sc->msk_dev, PCIR_STATUS, v16 | 3342 PCIM_STATUS_PERR | PCIM_STATUS_SERR | PCIM_STATUS_RMABORT | 3343 PCIM_STATUS_RTABORT | PCIM_STATUS_PERRREPORT, 2); 3344 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 3345 } 3346 3347 /* Check for PCI Express Uncorrectable Error. */ 3348 if ((status & Y2_IS_PCI_EXP) != 0) { 3349 uint32_t v32; 3350 3351 /* 3352 * On PCI Express bus bridges are called root complexes (RC). 3353 * PCI Express errors are recognized by the root complex too, 3354 * which requests the system to handle the problem. After 3355 * error occurence it may be that no access to the adapter 3356 * may be performed any longer. 3357 */ 3358 3359 v32 = CSR_PCI_READ_4(sc, PEX_UNC_ERR_STAT); 3360 if ((v32 & PEX_UNSUP_REQ) != 0) { 3361 /* Ignore unsupported request error. */ 3362 device_printf(sc->msk_dev, 3363 "Uncorrectable PCI Express error\n"); 3364 } 3365 if ((v32 & (PEX_FATAL_ERRORS | PEX_POIS_TLP)) != 0) { 3366 int i; 3367 3368 /* Get TLP header form Log Registers. */ 3369 for (i = 0; i < 4; i++) 3370 tlphead[i] = CSR_PCI_READ_4(sc, 3371 PEX_HEADER_LOG + i * 4); 3372 /* Check for vendor defined broadcast message. */ 3373 if (!(tlphead[0] == 0x73004001 && tlphead[1] == 0x7f)) { 3374 sc->msk_intrhwemask &= ~Y2_IS_PCI_EXP; 3375 CSR_WRITE_4(sc, B0_HWE_IMSK, 3376 sc->msk_intrhwemask); 3377 CSR_READ_4(sc, B0_HWE_IMSK); 3378 } 3379 } 3380 /* Clear the interrupt. */ 3381 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON); 3382 CSR_PCI_WRITE_4(sc, PEX_UNC_ERR_STAT, 0xffffffff); 3383 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 3384 } 3385 3386 if ((status & Y2_HWE_L1_MASK) != 0 && sc->msk_if[MSK_PORT_A] != NULL) 3387 msk_handle_hwerr(sc->msk_if[MSK_PORT_A], status); 3388 if ((status & Y2_HWE_L2_MASK) != 0 && sc->msk_if[MSK_PORT_B] != NULL) 3389 msk_handle_hwerr(sc->msk_if[MSK_PORT_B], status >> 8); 3390 } 3391 3392 static __inline void 3393 msk_rxput(struct msk_if_softc *sc_if) 3394 { 3395 struct msk_softc *sc; 3396 3397 sc = sc_if->msk_softc; 3398 if (sc_if->msk_framesize >(MCLBYTES - ETHER_HDR_LEN)) 3399 bus_dmamap_sync( 3400 sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 3401 sc_if->msk_cdata.msk_jumbo_rx_ring_map, 3402 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3403 else 3404 bus_dmamap_sync( 3405 sc_if->msk_cdata.msk_rx_ring_tag, 3406 sc_if->msk_cdata.msk_rx_ring_map, 3407 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3408 CSR_WRITE_2(sc, Y2_PREF_Q_ADDR(sc_if->msk_rxq, 3409 PREF_UNIT_PUT_IDX_REG), sc_if->msk_cdata.msk_rx_prod); 3410 } 3411 3412 static int 3413 msk_handle_events(struct msk_softc *sc) 3414 { 3415 struct msk_if_softc *sc_if; 3416 int rxput[2]; 3417 struct msk_stat_desc *sd; 3418 uint32_t control, status; 3419 int cons, idx, len, port, rxprog; 3420 3421 idx = CSR_READ_2(sc, STAT_PUT_IDX); 3422 if (idx == sc->msk_stat_cons) 3423 return (0); 3424 3425 /* Sync status LEs. */ 3426 bus_dmamap_sync(sc->msk_stat_tag, sc->msk_stat_map, 3427 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3428 /* XXX Sync Rx LEs here. */ 3429 3430 rxput[MSK_PORT_A] = rxput[MSK_PORT_B] = 0; 3431 3432 rxprog = 0; 3433 for (cons = sc->msk_stat_cons; cons != idx;) { 3434 sd = &sc->msk_stat_ring[cons]; 3435 control = le32toh(sd->msk_control); 3436 if ((control & HW_OWNER) == 0) 3437 break; 3438 /* 3439 * Marvell's FreeBSD driver updates status LE after clearing 3440 * HW_OWNER. However we don't have a way to sync single LE 3441 * with bus_dma(9) API. bus_dma(9) provides a way to sync 3442 * an entire DMA map. So don't sync LE until we have a better 3443 * way to sync LEs. 3444 */ 3445 control &= ~HW_OWNER; 3446 sd->msk_control = htole32(control); 3447 status = le32toh(sd->msk_status); 3448 len = control & STLE_LEN_MASK; 3449 port = (control >> 16) & 0x01; 3450 sc_if = sc->msk_if[port]; 3451 if (sc_if == NULL) { 3452 device_printf(sc->msk_dev, "invalid port opcode " 3453 "0x%08x\n", control & STLE_OP_MASK); 3454 continue; 3455 } 3456 3457 switch (control & STLE_OP_MASK) { 3458 case OP_RXVLAN: 3459 sc_if->msk_vtag = ntohs(len); 3460 break; 3461 case OP_RXCHKSVLAN: 3462 sc_if->msk_vtag = ntohs(len); 3463 break; 3464 case OP_RXSTAT: 3465 if (sc_if->msk_framesize > (MCLBYTES - ETHER_HDR_LEN)) 3466 msk_jumbo_rxeof(sc_if, status, len); 3467 else 3468 msk_rxeof(sc_if, status, len); 3469 rxprog++; 3470 /* 3471 * Because there is no way to sync single Rx LE 3472 * put the DMA sync operation off until the end of 3473 * event processing. 3474 */ 3475 rxput[port]++; 3476 /* Update prefetch unit if we've passed water mark. */ 3477 if (rxput[port] >= sc_if->msk_cdata.msk_rx_putwm) { 3478 msk_rxput(sc_if); 3479 rxput[port] = 0; 3480 } 3481 break; 3482 case OP_TXINDEXLE: 3483 if (sc->msk_if[MSK_PORT_A] != NULL) 3484 msk_txeof(sc->msk_if[MSK_PORT_A], 3485 status & STLE_TXA1_MSKL); 3486 if (sc->msk_if[MSK_PORT_B] != NULL) 3487 msk_txeof(sc->msk_if[MSK_PORT_B], 3488 ((status & STLE_TXA2_MSKL) >> 3489 STLE_TXA2_SHIFTL) | 3490 ((len & STLE_TXA2_MSKH) << 3491 STLE_TXA2_SHIFTH)); 3492 break; 3493 default: 3494 device_printf(sc->msk_dev, "unhandled opcode 0x%08x\n", 3495 control & STLE_OP_MASK); 3496 break; 3497 } 3498 MSK_INC(cons, MSK_STAT_RING_CNT); 3499 if (rxprog > sc->msk_process_limit) 3500 break; 3501 } 3502 3503 sc->msk_stat_cons = cons; 3504 /* XXX We should sync status LEs here. See above notes. */ 3505 3506 if (rxput[MSK_PORT_A] > 0) 3507 msk_rxput(sc->msk_if[MSK_PORT_A]); 3508 if (rxput[MSK_PORT_B] > 0) 3509 msk_rxput(sc->msk_if[MSK_PORT_B]); 3510 3511 return (sc->msk_stat_cons != CSR_READ_2(sc, STAT_PUT_IDX)); 3512 } 3513 3514 static int 3515 msk_intr(void *xsc) 3516 { 3517 struct msk_softc *sc; 3518 uint32_t status; 3519 3520 sc = xsc; 3521 status = CSR_READ_4(sc, B0_Y2_SP_ISRC2); 3522 /* Reading B0_Y2_SP_ISRC2 masks further interrupts. */ 3523 if (status == 0 || status == 0xffffffff) { 3524 CSR_WRITE_4(sc, B0_Y2_SP_ICR, 2); 3525 return (FILTER_STRAY); 3526 } 3527 3528 taskqueue_enqueue(sc->msk_tq, &sc->msk_int_task); 3529 return (FILTER_HANDLED); 3530 } 3531 3532 static void 3533 msk_int_task(void *arg, int pending) 3534 { 3535 struct msk_softc *sc; 3536 struct msk_if_softc *sc_if0, *sc_if1; 3537 struct ifnet *ifp0, *ifp1; 3538 uint32_t status; 3539 int domore; 3540 3541 sc = arg; 3542 MSK_LOCK(sc); 3543 3544 /* Get interrupt source. */ 3545 status = CSR_READ_4(sc, B0_ISRC); 3546 if (status == 0 || status == 0xffffffff || sc->msk_suspended != 0 || 3547 (status & sc->msk_intrmask) == 0) 3548 goto done; 3549 3550 sc_if0 = sc->msk_if[MSK_PORT_A]; 3551 sc_if1 = sc->msk_if[MSK_PORT_B]; 3552 ifp0 = ifp1 = NULL; 3553 if (sc_if0 != NULL) 3554 ifp0 = sc_if0->msk_ifp; 3555 if (sc_if1 != NULL) 3556 ifp1 = sc_if1->msk_ifp; 3557 3558 if ((status & Y2_IS_IRQ_PHY1) != 0 && sc_if0 != NULL) 3559 msk_intr_phy(sc_if0); 3560 if ((status & Y2_IS_IRQ_PHY2) != 0 && sc_if1 != NULL) 3561 msk_intr_phy(sc_if1); 3562 if ((status & Y2_IS_IRQ_MAC1) != 0 && sc_if0 != NULL) 3563 msk_intr_gmac(sc_if0); 3564 if ((status & Y2_IS_IRQ_MAC2) != 0 && sc_if1 != NULL) 3565 msk_intr_gmac(sc_if1); 3566 if ((status & (Y2_IS_CHK_RX1 | Y2_IS_CHK_RX2)) != 0) { 3567 device_printf(sc->msk_dev, "Rx descriptor error\n"); 3568 sc->msk_intrmask &= ~(Y2_IS_CHK_RX1 | Y2_IS_CHK_RX2); 3569 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask); 3570 CSR_READ_4(sc, B0_IMSK); 3571 } 3572 if ((status & (Y2_IS_CHK_TXA1 | Y2_IS_CHK_TXA2)) != 0) { 3573 device_printf(sc->msk_dev, "Tx descriptor error\n"); 3574 sc->msk_intrmask &= ~(Y2_IS_CHK_TXA1 | Y2_IS_CHK_TXA2); 3575 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask); 3576 CSR_READ_4(sc, B0_IMSK); 3577 } 3578 if ((status & Y2_IS_HW_ERR) != 0) 3579 msk_intr_hwerr(sc); 3580 3581 domore = msk_handle_events(sc); 3582 if ((status & Y2_IS_STAT_BMU) != 0) 3583 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_CLR_IRQ); 3584 3585 if (ifp0 != NULL && (ifp0->if_drv_flags & IFF_DRV_RUNNING) != 0 && 3586 !IFQ_DRV_IS_EMPTY(&ifp0->if_snd)) 3587 taskqueue_enqueue(taskqueue_fast, &sc_if0->msk_tx_task); 3588 if (ifp1 != NULL && (ifp1->if_drv_flags & IFF_DRV_RUNNING) != 0 && 3589 !IFQ_DRV_IS_EMPTY(&ifp1->if_snd)) 3590 taskqueue_enqueue(taskqueue_fast, &sc_if1->msk_tx_task); 3591 3592 if (domore > 0) { 3593 taskqueue_enqueue(sc->msk_tq, &sc->msk_int_task); 3594 MSK_UNLOCK(sc); 3595 return; 3596 } 3597 done: 3598 MSK_UNLOCK(sc); 3599 3600 /* Reenable interrupts. */ 3601 CSR_WRITE_4(sc, B0_Y2_SP_ICR, 2); 3602 } 3603 3604 static void 3605 msk_init(void *xsc) 3606 { 3607 struct msk_if_softc *sc_if = xsc; 3608 3609 MSK_IF_LOCK(sc_if); 3610 msk_init_locked(sc_if); 3611 MSK_IF_UNLOCK(sc_if); 3612 } 3613 3614 static void 3615 msk_init_locked(struct msk_if_softc *sc_if) 3616 { 3617 struct msk_softc *sc; 3618 struct ifnet *ifp; 3619 struct mii_data *mii; 3620 uint16_t eaddr[ETHER_ADDR_LEN / 2]; 3621 uint16_t gmac; 3622 int error, i; 3623 3624 MSK_IF_LOCK_ASSERT(sc_if); 3625 3626 ifp = sc_if->msk_ifp; 3627 sc = sc_if->msk_softc; 3628 mii = device_get_softc(sc_if->msk_miibus); 3629 3630 error = 0; 3631 /* Cancel pending I/O and free all Rx/Tx buffers. */ 3632 msk_stop(sc_if); 3633 3634 sc_if->msk_framesize = ifp->if_mtu + ETHER_HDR_LEN + 3635 ETHER_VLAN_ENCAP_LEN; 3636 3637 /* 3638 * Initialize GMAC first. 3639 * Without this initialization, Rx MAC did not work as expected 3640 * and Rx MAC garbled status LEs and it resulted in out-of-order 3641 * or duplicated frame delivery which in turn showed very poor 3642 * Rx performance.(I had to write a packet analysis code that 3643 * could be embeded in driver to diagnose this issue.) 3644 * I've spent almost 2 months to fix this issue. If I have had 3645 * datasheet for Yukon II I wouldn't have encountered this. :-( 3646 */ 3647 gmac = GM_GPCR_SPEED_100 | GM_GPCR_SPEED_1000 | GM_GPCR_DUP_FULL; 3648 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, gmac); 3649 3650 /* Dummy read the Interrupt Source Register. */ 3651 CSR_READ_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_SRC)); 3652 3653 /* Set MIB Clear Counter Mode. */ 3654 gmac = GMAC_READ_2(sc, sc_if->msk_port, GM_PHY_ADDR); 3655 GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac | GM_PAR_MIB_CLR); 3656 /* Read all MIB Counters with Clear Mode set. */ 3657 for (i = 0; i < GM_MIB_CNT_SIZE; i++) 3658 GMAC_READ_2(sc, sc_if->msk_port, GM_MIB_CNT_BASE + 8 * i); 3659 /* Clear MIB Clear Counter Mode. */ 3660 gmac &= ~GM_PAR_MIB_CLR; 3661 GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac); 3662 3663 /* Disable FCS. */ 3664 GMAC_WRITE_2(sc, sc_if->msk_port, GM_RX_CTRL, GM_RXCR_CRC_DIS); 3665 3666 /* Setup Transmit Control Register. */ 3667 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF)); 3668 3669 /* Setup Transmit Flow Control Register. */ 3670 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_FLOW_CTRL, 0xffff); 3671 3672 /* Setup Transmit Parameter Register. */ 3673 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_PARAM, 3674 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) | TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) | 3675 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) | TX_BACK_OFF_LIM(TX_BOF_LIM_DEF)); 3676 3677 gmac = DATA_BLIND_VAL(DATA_BLIND_DEF) | 3678 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF); 3679 3680 if (sc_if->msk_framesize > MSK_MAX_FRAMELEN) 3681 gmac |= GM_SMOD_JUMBO_ENA; 3682 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SERIAL_MODE, gmac); 3683 3684 /* Set station address. */ 3685 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN); 3686 for (i = 0; i < ETHER_ADDR_LEN /2; i++) 3687 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_1L + i * 4, 3688 eaddr[i]); 3689 for (i = 0; i < ETHER_ADDR_LEN /2; i++) 3690 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_2L + i * 4, 3691 eaddr[i]); 3692 3693 /* Disable interrupts for counter overflows. */ 3694 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_IRQ_MSK, 0); 3695 GMAC_WRITE_2(sc, sc_if->msk_port, GM_RX_IRQ_MSK, 0); 3696 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TR_IRQ_MSK, 0); 3697 3698 /* Configure Rx MAC FIFO. */ 3699 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), GMF_RST_SET); 3700 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), GMF_RST_CLR); 3701 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), 3702 GMF_OPER_ON | GMF_RX_F_FL_ON); 3703 3704 /* Set promiscuous mode. */ 3705 msk_setpromisc(sc_if); 3706 3707 /* Set multicast filter. */ 3708 msk_setmulti(sc_if); 3709 3710 /* Flush Rx MAC FIFO on any flow control or error. */ 3711 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_FL_MSK), 3712 GMR_FS_ANY_ERR); 3713 3714 /* Set Rx FIFO flush threshold to 64 bytes. */ 3715 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_FL_THR), 3716 RX_GMF_FL_THR_DEF); 3717 3718 /* Configure Tx MAC FIFO. */ 3719 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_RST_SET); 3720 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_RST_CLR); 3721 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_OPER_ON); 3722 3723 /* Configure hardware VLAN tag insertion/stripping. */ 3724 msk_setvlan(sc_if, ifp); 3725 3726 /* XXX It seems STFW is requried for all cases. */ 3727 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), TX_STFW_ENA); 3728 3729 if (sc->msk_hw_id == CHIP_ID_YUKON_EC_U) { 3730 /* Set Rx Pause threshould. */ 3731 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, RX_GMF_LP_THR), 3732 MSK_ECU_LLPP); 3733 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, RX_GMF_UP_THR), 3734 MSK_ECU_ULPP); 3735 if (sc_if->msk_framesize > MSK_MAX_FRAMELEN) { 3736 /* 3737 * Can't sure the following code is needed as Yukon 3738 * Yukon EC Ultra may not support jumbo frames. 3739 * 3740 * Set Tx GMAC FIFO Almost Empty Threshold. 3741 */ 3742 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_AE_THR), 3743 MSK_ECU_AE_THR); 3744 /* Disable Store & Forward mode for Tx. */ 3745 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 3746 TX_STFW_DIS); 3747 } 3748 } 3749 3750 /* 3751 * Disable Force Sync bit and Alloc bit in Tx RAM interface 3752 * arbiter as we don't use Sync Tx queue. 3753 */ 3754 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, TXA_CTRL), 3755 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC); 3756 /* Enable the RAM Interface Arbiter. */ 3757 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, TXA_CTRL), TXA_ENA_ARB); 3758 3759 /* Setup RAM buffer. */ 3760 msk_set_rambuffer(sc_if); 3761 3762 /* Disable Tx sync Queue. */ 3763 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txsq, RB_CTRL), RB_RST_SET); 3764 3765 /* Setup Tx Queue Bus Memory Interface. */ 3766 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_CLR_RESET); 3767 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_OPER_INIT); 3768 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_FIFO_OP_ON); 3769 /* Increase IPID when hardware generates IP packets in TSO. */ 3770 if ((ifp->if_hwassist & CSUM_TSO) != 0) 3771 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), 3772 BMU_TX_IPIDINCR_ON); 3773 else 3774 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), 3775 BMU_TX_IPIDINCR_OFF); 3776 CSR_WRITE_2(sc, Q_ADDR(sc_if->msk_txq, Q_WM), MSK_BMU_TX_WM); 3777 if (sc->msk_hw_id == CHIP_ID_YUKON_EC_U && 3778 sc->msk_hw_rev == CHIP_REV_YU_EC_U_A0) { 3779 /* Fix for Yukon-EC Ultra: set BMU FIFO level */ 3780 CSR_WRITE_2(sc, Q_ADDR(sc_if->msk_txq, Q_AL), MSK_ECU_TXFF_LEV); 3781 } 3782 3783 /* Setup Rx Queue Bus Memory Interface. */ 3784 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_CLR_RESET); 3785 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_OPER_INIT); 3786 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_FIFO_OP_ON); 3787 CSR_WRITE_2(sc, Q_ADDR(sc_if->msk_rxq, Q_WM), MSK_BMU_RX_WM); 3788 if (sc->msk_hw_id == CHIP_ID_YUKON_EC_U && 3789 sc->msk_hw_rev >= CHIP_REV_YU_EC_U_A1) { 3790 /* MAC Rx RAM Read is controlled by hardware. */ 3791 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_F), F_M_RX_RAM_DIS); 3792 } 3793 3794 msk_set_prefetch(sc, sc_if->msk_txq, 3795 sc_if->msk_rdata.msk_tx_ring_paddr, MSK_TX_RING_CNT - 1); 3796 msk_init_tx_ring(sc_if); 3797 3798 /* Disable Rx checksum offload and RSS hash. */ 3799 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), 3800 BMU_DIS_RX_CHKSUM | BMU_DIS_RX_RSS_HASH); 3801 if (sc_if->msk_framesize > (MCLBYTES - ETHER_HDR_LEN)) { 3802 msk_set_prefetch(sc, sc_if->msk_rxq, 3803 sc_if->msk_rdata.msk_jumbo_rx_ring_paddr, 3804 MSK_JUMBO_RX_RING_CNT - 1); 3805 error = msk_init_jumbo_rx_ring(sc_if); 3806 } else { 3807 msk_set_prefetch(sc, sc_if->msk_rxq, 3808 sc_if->msk_rdata.msk_rx_ring_paddr, 3809 MSK_RX_RING_CNT - 1); 3810 error = msk_init_rx_ring(sc_if); 3811 } 3812 if (error != 0) { 3813 device_printf(sc_if->msk_if_dev, 3814 "initialization failed: no memory for Rx buffers\n"); 3815 msk_stop(sc_if); 3816 return; 3817 } 3818 3819 /* Configure interrupt handling. */ 3820 if (sc_if->msk_port == MSK_PORT_A) { 3821 sc->msk_intrmask |= Y2_IS_PORT_A; 3822 sc->msk_intrhwemask |= Y2_HWE_L1_MASK; 3823 } else { 3824 sc->msk_intrmask |= Y2_IS_PORT_B; 3825 sc->msk_intrhwemask |= Y2_HWE_L2_MASK; 3826 } 3827 CSR_WRITE_4(sc, B0_HWE_IMSK, sc->msk_intrhwemask); 3828 CSR_READ_4(sc, B0_HWE_IMSK); 3829 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask); 3830 CSR_READ_4(sc, B0_IMSK); 3831 3832 sc_if->msk_link = 0; 3833 mii_mediachg(mii); 3834 3835 ifp->if_drv_flags |= IFF_DRV_RUNNING; 3836 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3837 3838 callout_reset(&sc_if->msk_tick_ch, hz, msk_tick, sc_if); 3839 } 3840 3841 static void 3842 msk_set_rambuffer(struct msk_if_softc *sc_if) 3843 { 3844 struct msk_softc *sc; 3845 int ltpp, utpp; 3846 3847 sc = sc_if->msk_softc; 3848 3849 /* Setup Rx Queue. */ 3850 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_RST_CLR); 3851 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_START), 3852 sc->msk_rxqstart[sc_if->msk_port] / 8); 3853 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_END), 3854 sc->msk_rxqend[sc_if->msk_port] / 8); 3855 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_WP), 3856 sc->msk_rxqstart[sc_if->msk_port] / 8); 3857 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_RP), 3858 sc->msk_rxqstart[sc_if->msk_port] / 8); 3859 3860 utpp = (sc->msk_rxqend[sc_if->msk_port] + 1 - 3861 sc->msk_rxqstart[sc_if->msk_port] - MSK_RB_ULPP) / 8; 3862 ltpp = (sc->msk_rxqend[sc_if->msk_port] + 1 - 3863 sc->msk_rxqstart[sc_if->msk_port] - MSK_RB_LLPP_B) / 8; 3864 if (sc->msk_rxqsize < MSK_MIN_RXQ_SIZE) 3865 ltpp += (MSK_RB_LLPP_B - MSK_RB_LLPP_S) / 8; 3866 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_RX_UTPP), utpp); 3867 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_RX_LTPP), ltpp); 3868 /* Set Rx priority(RB_RX_UTHP/RB_RX_LTHP) thresholds? */ 3869 3870 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_ENA_OP_MD); 3871 CSR_READ_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL)); 3872 3873 /* Setup Tx Queue. */ 3874 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_RST_CLR); 3875 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_START), 3876 sc->msk_txqstart[sc_if->msk_port] / 8); 3877 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_END), 3878 sc->msk_txqend[sc_if->msk_port] / 8); 3879 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_WP), 3880 sc->msk_txqstart[sc_if->msk_port] / 8); 3881 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_RP), 3882 sc->msk_txqstart[sc_if->msk_port] / 8); 3883 /* Enable Store & Forward for Tx side. */ 3884 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_ENA_STFWD); 3885 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_ENA_OP_MD); 3886 CSR_READ_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL)); 3887 } 3888 3889 static void 3890 msk_set_prefetch(struct msk_softc *sc, int qaddr, bus_addr_t addr, 3891 uint32_t count) 3892 { 3893 3894 /* Reset the prefetch unit. */ 3895 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG), 3896 PREF_UNIT_RST_SET); 3897 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG), 3898 PREF_UNIT_RST_CLR); 3899 /* Set LE base address. */ 3900 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_ADDR_LOW_REG), 3901 MSK_ADDR_LO(addr)); 3902 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_ADDR_HI_REG), 3903 MSK_ADDR_HI(addr)); 3904 /* Set the list last index. */ 3905 CSR_WRITE_2(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_LAST_IDX_REG), 3906 count); 3907 /* Turn on prefetch unit. */ 3908 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG), 3909 PREF_UNIT_OP_ON); 3910 /* Dummy read to ensure write. */ 3911 CSR_READ_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG)); 3912 } 3913 3914 static void 3915 msk_stop(struct msk_if_softc *sc_if) 3916 { 3917 struct msk_softc *sc; 3918 struct msk_txdesc *txd; 3919 struct msk_rxdesc *rxd; 3920 struct msk_rxdesc *jrxd; 3921 struct ifnet *ifp; 3922 uint32_t val; 3923 int i; 3924 3925 MSK_IF_LOCK_ASSERT(sc_if); 3926 sc = sc_if->msk_softc; 3927 ifp = sc_if->msk_ifp; 3928 3929 callout_stop(&sc_if->msk_tick_ch); 3930 sc_if->msk_watchdog_timer = 0; 3931 3932 /* Disable interrupts. */ 3933 if (sc_if->msk_port == MSK_PORT_A) { 3934 sc->msk_intrmask &= ~Y2_IS_PORT_A; 3935 sc->msk_intrhwemask &= ~Y2_HWE_L1_MASK; 3936 } else { 3937 sc->msk_intrmask &= ~Y2_IS_PORT_B; 3938 sc->msk_intrhwemask &= ~Y2_HWE_L2_MASK; 3939 } 3940 CSR_WRITE_4(sc, B0_HWE_IMSK, sc->msk_intrhwemask); 3941 CSR_READ_4(sc, B0_HWE_IMSK); 3942 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask); 3943 CSR_READ_4(sc, B0_IMSK); 3944 3945 /* Disable Tx/Rx MAC. */ 3946 val = GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL); 3947 val &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA); 3948 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, val); 3949 /* Read again to ensure writing. */ 3950 GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL); 3951 3952 /* Stop Tx BMU. */ 3953 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_STOP); 3954 val = CSR_READ_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR)); 3955 for (i = 0; i < MSK_TIMEOUT; i++) { 3956 if ((val & (BMU_STOP | BMU_IDLE)) == 0) { 3957 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), 3958 BMU_STOP); 3959 CSR_READ_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR)); 3960 } else 3961 break; 3962 DELAY(1); 3963 } 3964 if (i == MSK_TIMEOUT) 3965 device_printf(sc_if->msk_if_dev, "Tx BMU stop failed\n"); 3966 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), 3967 RB_RST_SET | RB_DIS_OP_MD); 3968 3969 /* Disable all GMAC interrupt. */ 3970 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_MSK), 0); 3971 /* Disable PHY interrupt. */ 3972 if (sc->msk_marvell_phy) 3973 msk_phy_writereg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_MASK, 0); 3974 3975 /* Disable the RAM Interface Arbiter. */ 3976 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, TXA_CTRL), TXA_DIS_ARB); 3977 3978 /* Reset the PCI FIFO of the async Tx queue */ 3979 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), 3980 BMU_RST_SET | BMU_FIFO_RST); 3981 3982 /* Reset the Tx prefetch units. */ 3983 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(sc_if->msk_txq, PREF_UNIT_CTRL_REG), 3984 PREF_UNIT_RST_SET); 3985 3986 /* Reset the RAM Buffer async Tx queue. */ 3987 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_RST_SET); 3988 3989 /* Reset Tx MAC FIFO. */ 3990 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_RST_SET); 3991 /* Set Pause Off. */ 3992 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_PAUSE_OFF); 3993 3994 /* 3995 * The Rx Stop command will not work for Yukon-2 if the BMU does not 3996 * reach the end of packet and since we can't make sure that we have 3997 * incoming data, we must reset the BMU while it is not during a DMA 3998 * transfer. Since it is possible that the Rx path is still active, 3999 * the Rx RAM buffer will be stopped first, so any possible incoming 4000 * data will not trigger a DMA. After the RAM buffer is stopped, the 4001 * BMU is polled until any DMA in progress is ended and only then it 4002 * will be reset. 4003 */ 4004 4005 /* Disable the RAM Buffer receive queue. */ 4006 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_DIS_OP_MD); 4007 for (i = 0; i < MSK_TIMEOUT; i++) { 4008 if (CSR_READ_1(sc, RB_ADDR(sc_if->msk_rxq, Q_RSL)) == 4009 CSR_READ_1(sc, RB_ADDR(sc_if->msk_rxq, Q_RL))) 4010 break; 4011 DELAY(1); 4012 } 4013 if (i == MSK_TIMEOUT) 4014 device_printf(sc_if->msk_if_dev, "Rx BMU stop failed\n"); 4015 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), 4016 BMU_RST_SET | BMU_FIFO_RST); 4017 /* Reset the Rx prefetch unit. */ 4018 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_CTRL_REG), 4019 PREF_UNIT_RST_SET); 4020 /* Reset the RAM Buffer receive queue. */ 4021 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_RST_SET); 4022 /* Reset Rx MAC FIFO. */ 4023 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), GMF_RST_SET); 4024 4025 /* Free Rx and Tx mbufs still in the queues. */ 4026 for (i = 0; i < MSK_RX_RING_CNT; i++) { 4027 rxd = &sc_if->msk_cdata.msk_rxdesc[i]; 4028 if (rxd->rx_m != NULL) { 4029 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_tag, 4030 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 4031 bus_dmamap_unload(sc_if->msk_cdata.msk_rx_tag, 4032 rxd->rx_dmamap); 4033 m_freem(rxd->rx_m); 4034 rxd->rx_m = NULL; 4035 } 4036 } 4037 for (i = 0; i < MSK_JUMBO_RX_RING_CNT; i++) { 4038 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[i]; 4039 if (jrxd->rx_m != NULL) { 4040 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_tag, 4041 jrxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 4042 bus_dmamap_unload(sc_if->msk_cdata.msk_jumbo_rx_tag, 4043 jrxd->rx_dmamap); 4044 m_freem(jrxd->rx_m); 4045 jrxd->rx_m = NULL; 4046 } 4047 } 4048 for (i = 0; i < MSK_TX_RING_CNT; i++) { 4049 txd = &sc_if->msk_cdata.msk_txdesc[i]; 4050 if (txd->tx_m != NULL) { 4051 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_tag, 4052 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 4053 bus_dmamap_unload(sc_if->msk_cdata.msk_tx_tag, 4054 txd->tx_dmamap); 4055 m_freem(txd->tx_m); 4056 txd->tx_m = NULL; 4057 } 4058 } 4059 4060 /* 4061 * Mark the interface down. 4062 */ 4063 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 4064 sc_if->msk_link = 0; 4065 } 4066 4067 static int 4068 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 4069 { 4070 int error, value; 4071 4072 if (!arg1) 4073 return (EINVAL); 4074 value = *(int *)arg1; 4075 error = sysctl_handle_int(oidp, &value, 0, req); 4076 if (error || !req->newptr) 4077 return (error); 4078 if (value < low || value > high) 4079 return (EINVAL); 4080 *(int *)arg1 = value; 4081 4082 return (0); 4083 } 4084 4085 static int 4086 sysctl_hw_msk_proc_limit(SYSCTL_HANDLER_ARGS) 4087 { 4088 4089 return (sysctl_int_range(oidp, arg1, arg2, req, MSK_PROC_MIN, 4090 MSK_PROC_MAX)); 4091 } 4092