xref: /freebsd/sys/dev/msk/if_msk.c (revision 87c1627502a5dde91e5284118eec8682b60f27a2)
1 /******************************************************************************
2  *
3  * Name   : sky2.c
4  * Project: Gigabit Ethernet Driver for FreeBSD 5.x/6.x
5  * Version: $Revision: 1.23 $
6  * Date   : $Date: 2005/12/22 09:04:11 $
7  * Purpose: Main driver source file
8  *
9  *****************************************************************************/
10 
11 /******************************************************************************
12  *
13  *	LICENSE:
14  *	Copyright (C) Marvell International Ltd. and/or its affiliates
15  *
16  *	The computer program files contained in this folder ("Files")
17  *	are provided to you under the BSD-type license terms provided
18  *	below, and any use of such Files and any derivative works
19  *	thereof created by you shall be governed by the following terms
20  *	and conditions:
21  *
22  *	- Redistributions of source code must retain the above copyright
23  *	  notice, this list of conditions and the following disclaimer.
24  *	- Redistributions in binary form must reproduce the above
25  *	  copyright notice, this list of conditions and the following
26  *	  disclaimer in the documentation and/or other materials provided
27  *	  with the distribution.
28  *	- Neither the name of Marvell nor the names of its contributors
29  *	  may be used to endorse or promote products derived from this
30  *	  software without specific prior written permission.
31  *
32  *	THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
33  *	"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
34  *	LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
35  *	FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
36  *	COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
37  *	INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
38  *	BUT NOT LIMITED TO, PROCUREMENT OF  SUBSTITUTE GOODS OR SERVICES;
39  *	LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
40  *	HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
41  *	STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
42  *	ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
43  *	OF THE POSSIBILITY OF SUCH DAMAGE.
44  *	/LICENSE
45  *
46  *****************************************************************************/
47 
48 /*-
49  * Copyright (c) 1997, 1998, 1999, 2000
50  *	Bill Paul <wpaul@ctr.columbia.edu>.  All rights reserved.
51  *
52  * Redistribution and use in source and binary forms, with or without
53  * modification, are permitted provided that the following conditions
54  * are met:
55  * 1. Redistributions of source code must retain the above copyright
56  *    notice, this list of conditions and the following disclaimer.
57  * 2. Redistributions in binary form must reproduce the above copyright
58  *    notice, this list of conditions and the following disclaimer in the
59  *    documentation and/or other materials provided with the distribution.
60  * 3. All advertising materials mentioning features or use of this software
61  *    must display the following acknowledgement:
62  *	This product includes software developed by Bill Paul.
63  * 4. Neither the name of the author nor the names of any co-contributors
64  *    may be used to endorse or promote products derived from this software
65  *    without specific prior written permission.
66  *
67  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
68  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
69  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
70  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
71  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
72  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
73  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
74  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
75  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
76  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
77  * THE POSSIBILITY OF SUCH DAMAGE.
78  */
79 /*-
80  * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu>
81  *
82  * Permission to use, copy, modify, and distribute this software for any
83  * purpose with or without fee is hereby granted, provided that the above
84  * copyright notice and this permission notice appear in all copies.
85  *
86  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
87  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
88  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
89  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
90  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
91  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
92  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
93  */
94 
95 /*
96  * Device driver for the Marvell Yukon II Ethernet controller.
97  * Due to lack of documentation, this driver is based on the code from
98  * sk(4) and Marvell's myk(4) driver for FreeBSD 5.x.
99  */
100 
101 #include <sys/cdefs.h>
102 __FBSDID("$FreeBSD$");
103 
104 #include <sys/param.h>
105 #include <sys/systm.h>
106 #include <sys/bus.h>
107 #include <sys/endian.h>
108 #include <sys/mbuf.h>
109 #include <sys/malloc.h>
110 #include <sys/kernel.h>
111 #include <sys/module.h>
112 #include <sys/socket.h>
113 #include <sys/sockio.h>
114 #include <sys/queue.h>
115 #include <sys/sysctl.h>
116 
117 #include <net/bpf.h>
118 #include <net/ethernet.h>
119 #include <net/if.h>
120 #include <net/if_arp.h>
121 #include <net/if_dl.h>
122 #include <net/if_media.h>
123 #include <net/if_types.h>
124 #include <net/if_vlan_var.h>
125 
126 #include <netinet/in.h>
127 #include <netinet/in_systm.h>
128 #include <netinet/ip.h>
129 #include <netinet/tcp.h>
130 #include <netinet/udp.h>
131 
132 #include <machine/bus.h>
133 #include <machine/in_cksum.h>
134 #include <machine/resource.h>
135 #include <sys/rman.h>
136 
137 #include <dev/mii/mii.h>
138 #include <dev/mii/miivar.h>
139 
140 #include <dev/pci/pcireg.h>
141 #include <dev/pci/pcivar.h>
142 
143 #include <dev/msk/if_mskreg.h>
144 
145 MODULE_DEPEND(msk, pci, 1, 1, 1);
146 MODULE_DEPEND(msk, ether, 1, 1, 1);
147 MODULE_DEPEND(msk, miibus, 1, 1, 1);
148 
149 /* "device miibus" required.  See GENERIC if you get errors here. */
150 #include "miibus_if.h"
151 
152 /* Tunables. */
153 static int msi_disable = 0;
154 TUNABLE_INT("hw.msk.msi_disable", &msi_disable);
155 static int legacy_intr = 0;
156 TUNABLE_INT("hw.msk.legacy_intr", &legacy_intr);
157 static int jumbo_disable = 0;
158 TUNABLE_INT("hw.msk.jumbo_disable", &jumbo_disable);
159 
160 #define MSK_CSUM_FEATURES	(CSUM_TCP | CSUM_UDP)
161 
162 /*
163  * Devices supported by this driver.
164  */
165 static struct msk_product {
166 	uint16_t	msk_vendorid;
167 	uint16_t	msk_deviceid;
168 	const char	*msk_name;
169 } msk_products[] = {
170 	{ VENDORID_SK, DEVICEID_SK_YUKON2,
171 	    "SK-9Sxx Gigabit Ethernet" },
172 	{ VENDORID_SK, DEVICEID_SK_YUKON2_EXPR,
173 	    "SK-9Exx Gigabit Ethernet"},
174 	{ VENDORID_MARVELL, DEVICEID_MRVL_8021CU,
175 	    "Marvell Yukon 88E8021CU Gigabit Ethernet" },
176 	{ VENDORID_MARVELL, DEVICEID_MRVL_8021X,
177 	    "Marvell Yukon 88E8021 SX/LX Gigabit Ethernet" },
178 	{ VENDORID_MARVELL, DEVICEID_MRVL_8022CU,
179 	    "Marvell Yukon 88E8022CU Gigabit Ethernet" },
180 	{ VENDORID_MARVELL, DEVICEID_MRVL_8022X,
181 	    "Marvell Yukon 88E8022 SX/LX Gigabit Ethernet" },
182 	{ VENDORID_MARVELL, DEVICEID_MRVL_8061CU,
183 	    "Marvell Yukon 88E8061CU Gigabit Ethernet" },
184 	{ VENDORID_MARVELL, DEVICEID_MRVL_8061X,
185 	    "Marvell Yukon 88E8061 SX/LX Gigabit Ethernet" },
186 	{ VENDORID_MARVELL, DEVICEID_MRVL_8062CU,
187 	    "Marvell Yukon 88E8062CU Gigabit Ethernet" },
188 	{ VENDORID_MARVELL, DEVICEID_MRVL_8062X,
189 	    "Marvell Yukon 88E8062 SX/LX Gigabit Ethernet" },
190 	{ VENDORID_MARVELL, DEVICEID_MRVL_8035,
191 	    "Marvell Yukon 88E8035 Fast Ethernet" },
192 	{ VENDORID_MARVELL, DEVICEID_MRVL_8036,
193 	    "Marvell Yukon 88E8036 Fast Ethernet" },
194 	{ VENDORID_MARVELL, DEVICEID_MRVL_8038,
195 	    "Marvell Yukon 88E8038 Fast Ethernet" },
196 	{ VENDORID_MARVELL, DEVICEID_MRVL_8039,
197 	    "Marvell Yukon 88E8039 Fast Ethernet" },
198 	{ VENDORID_MARVELL, DEVICEID_MRVL_8040,
199 	    "Marvell Yukon 88E8040 Fast Ethernet" },
200 	{ VENDORID_MARVELL, DEVICEID_MRVL_8040T,
201 	    "Marvell Yukon 88E8040T Fast Ethernet" },
202 	{ VENDORID_MARVELL, DEVICEID_MRVL_8042,
203 	    "Marvell Yukon 88E8042 Fast Ethernet" },
204 	{ VENDORID_MARVELL, DEVICEID_MRVL_8048,
205 	    "Marvell Yukon 88E8048 Fast Ethernet" },
206 	{ VENDORID_MARVELL, DEVICEID_MRVL_4361,
207 	    "Marvell Yukon 88E8050 Gigabit Ethernet" },
208 	{ VENDORID_MARVELL, DEVICEID_MRVL_4360,
209 	    "Marvell Yukon 88E8052 Gigabit Ethernet" },
210 	{ VENDORID_MARVELL, DEVICEID_MRVL_4362,
211 	    "Marvell Yukon 88E8053 Gigabit Ethernet" },
212 	{ VENDORID_MARVELL, DEVICEID_MRVL_4363,
213 	    "Marvell Yukon 88E8055 Gigabit Ethernet" },
214 	{ VENDORID_MARVELL, DEVICEID_MRVL_4364,
215 	    "Marvell Yukon 88E8056 Gigabit Ethernet" },
216 	{ VENDORID_MARVELL, DEVICEID_MRVL_4365,
217 	    "Marvell Yukon 88E8070 Gigabit Ethernet" },
218 	{ VENDORID_MARVELL, DEVICEID_MRVL_436A,
219 	    "Marvell Yukon 88E8058 Gigabit Ethernet" },
220 	{ VENDORID_MARVELL, DEVICEID_MRVL_436B,
221 	    "Marvell Yukon 88E8071 Gigabit Ethernet" },
222 	{ VENDORID_MARVELL, DEVICEID_MRVL_436C,
223 	    "Marvell Yukon 88E8072 Gigabit Ethernet" },
224 	{ VENDORID_MARVELL, DEVICEID_MRVL_436D,
225 	    "Marvell Yukon 88E8055 Gigabit Ethernet" },
226 	{ VENDORID_MARVELL, DEVICEID_MRVL_4370,
227 	    "Marvell Yukon 88E8075 Gigabit Ethernet" },
228 	{ VENDORID_MARVELL, DEVICEID_MRVL_4380,
229 	    "Marvell Yukon 88E8057 Gigabit Ethernet" },
230 	{ VENDORID_MARVELL, DEVICEID_MRVL_4381,
231 	    "Marvell Yukon 88E8059 Gigabit Ethernet" },
232 	{ VENDORID_DLINK, DEVICEID_DLINK_DGE550SX,
233 	    "D-Link 550SX Gigabit Ethernet" },
234 	{ VENDORID_DLINK, DEVICEID_DLINK_DGE560SX,
235 	    "D-Link 560SX Gigabit Ethernet" },
236 	{ VENDORID_DLINK, DEVICEID_DLINK_DGE560T,
237 	    "D-Link 560T Gigabit Ethernet" }
238 };
239 
240 static const char *model_name[] = {
241 	"Yukon XL",
242         "Yukon EC Ultra",
243         "Yukon EX",
244         "Yukon EC",
245         "Yukon FE",
246         "Yukon FE+",
247         "Yukon Supreme",
248         "Yukon Ultra 2",
249         "Yukon Unknown",
250         "Yukon Optima",
251 };
252 
253 static int mskc_probe(device_t);
254 static int mskc_attach(device_t);
255 static int mskc_detach(device_t);
256 static int mskc_shutdown(device_t);
257 static int mskc_setup_rambuffer(struct msk_softc *);
258 static int mskc_suspend(device_t);
259 static int mskc_resume(device_t);
260 static void mskc_reset(struct msk_softc *);
261 
262 static int msk_probe(device_t);
263 static int msk_attach(device_t);
264 static int msk_detach(device_t);
265 
266 static void msk_tick(void *);
267 static void msk_intr(void *);
268 static void msk_intr_phy(struct msk_if_softc *);
269 static void msk_intr_gmac(struct msk_if_softc *);
270 static __inline void msk_rxput(struct msk_if_softc *);
271 static int msk_handle_events(struct msk_softc *);
272 static void msk_handle_hwerr(struct msk_if_softc *, uint32_t);
273 static void msk_intr_hwerr(struct msk_softc *);
274 #ifndef __NO_STRICT_ALIGNMENT
275 static __inline void msk_fixup_rx(struct mbuf *);
276 #endif
277 static __inline void msk_rxcsum(struct msk_if_softc *, uint32_t, struct mbuf *);
278 static void msk_rxeof(struct msk_if_softc *, uint32_t, uint32_t, int);
279 static void msk_jumbo_rxeof(struct msk_if_softc *, uint32_t, uint32_t, int);
280 static void msk_txeof(struct msk_if_softc *, int);
281 static int msk_encap(struct msk_if_softc *, struct mbuf **);
282 static void msk_start(struct ifnet *);
283 static void msk_start_locked(struct ifnet *);
284 static int msk_ioctl(struct ifnet *, u_long, caddr_t);
285 static void msk_set_prefetch(struct msk_softc *, int, bus_addr_t, uint32_t);
286 static void msk_set_rambuffer(struct msk_if_softc *);
287 static void msk_set_tx_stfwd(struct msk_if_softc *);
288 static void msk_init(void *);
289 static void msk_init_locked(struct msk_if_softc *);
290 static void msk_stop(struct msk_if_softc *);
291 static void msk_watchdog(struct msk_if_softc *);
292 static int msk_mediachange(struct ifnet *);
293 static void msk_mediastatus(struct ifnet *, struct ifmediareq *);
294 static void msk_phy_power(struct msk_softc *, int);
295 static void msk_dmamap_cb(void *, bus_dma_segment_t *, int, int);
296 static int msk_status_dma_alloc(struct msk_softc *);
297 static void msk_status_dma_free(struct msk_softc *);
298 static int msk_txrx_dma_alloc(struct msk_if_softc *);
299 static int msk_rx_dma_jalloc(struct msk_if_softc *);
300 static void msk_txrx_dma_free(struct msk_if_softc *);
301 static void msk_rx_dma_jfree(struct msk_if_softc *);
302 static int msk_rx_fill(struct msk_if_softc *, int);
303 static int msk_init_rx_ring(struct msk_if_softc *);
304 static int msk_init_jumbo_rx_ring(struct msk_if_softc *);
305 static void msk_init_tx_ring(struct msk_if_softc *);
306 static __inline void msk_discard_rxbuf(struct msk_if_softc *, int);
307 static __inline void msk_discard_jumbo_rxbuf(struct msk_if_softc *, int);
308 static int msk_newbuf(struct msk_if_softc *, int);
309 static int msk_jumbo_newbuf(struct msk_if_softc *, int);
310 
311 static int msk_phy_readreg(struct msk_if_softc *, int, int);
312 static int msk_phy_writereg(struct msk_if_softc *, int, int, int);
313 static int msk_miibus_readreg(device_t, int, int);
314 static int msk_miibus_writereg(device_t, int, int, int);
315 static void msk_miibus_statchg(device_t);
316 
317 static void msk_rxfilter(struct msk_if_softc *);
318 static void msk_setvlan(struct msk_if_softc *, struct ifnet *);
319 
320 static void msk_stats_clear(struct msk_if_softc *);
321 static void msk_stats_update(struct msk_if_softc *);
322 static int msk_sysctl_stat32(SYSCTL_HANDLER_ARGS);
323 static int msk_sysctl_stat64(SYSCTL_HANDLER_ARGS);
324 static void msk_sysctl_node(struct msk_if_softc *);
325 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int);
326 static int sysctl_hw_msk_proc_limit(SYSCTL_HANDLER_ARGS);
327 
328 static device_method_t mskc_methods[] = {
329 	/* Device interface */
330 	DEVMETHOD(device_probe,		mskc_probe),
331 	DEVMETHOD(device_attach,	mskc_attach),
332 	DEVMETHOD(device_detach,	mskc_detach),
333 	DEVMETHOD(device_suspend,	mskc_suspend),
334 	DEVMETHOD(device_resume,	mskc_resume),
335 	DEVMETHOD(device_shutdown,	mskc_shutdown),
336 
337 	DEVMETHOD_END
338 };
339 
340 static driver_t mskc_driver = {
341 	"mskc",
342 	mskc_methods,
343 	sizeof(struct msk_softc)
344 };
345 
346 static devclass_t mskc_devclass;
347 
348 static device_method_t msk_methods[] = {
349 	/* Device interface */
350 	DEVMETHOD(device_probe,		msk_probe),
351 	DEVMETHOD(device_attach,	msk_attach),
352 	DEVMETHOD(device_detach,	msk_detach),
353 	DEVMETHOD(device_shutdown,	bus_generic_shutdown),
354 
355 	/* MII interface */
356 	DEVMETHOD(miibus_readreg,	msk_miibus_readreg),
357 	DEVMETHOD(miibus_writereg,	msk_miibus_writereg),
358 	DEVMETHOD(miibus_statchg,	msk_miibus_statchg),
359 
360 	DEVMETHOD_END
361 };
362 
363 static driver_t msk_driver = {
364 	"msk",
365 	msk_methods,
366 	sizeof(struct msk_if_softc)
367 };
368 
369 static devclass_t msk_devclass;
370 
371 DRIVER_MODULE(mskc, pci, mskc_driver, mskc_devclass, 0, 0);
372 DRIVER_MODULE(msk, mskc, msk_driver, msk_devclass, 0, 0);
373 DRIVER_MODULE(miibus, msk, miibus_driver, miibus_devclass, 0, 0);
374 
375 static struct resource_spec msk_res_spec_io[] = {
376 	{ SYS_RES_IOPORT,	PCIR_BAR(1),	RF_ACTIVE },
377 	{ -1,			0,		0 }
378 };
379 
380 static struct resource_spec msk_res_spec_mem[] = {
381 	{ SYS_RES_MEMORY,	PCIR_BAR(0),	RF_ACTIVE },
382 	{ -1,			0,		0 }
383 };
384 
385 static struct resource_spec msk_irq_spec_legacy[] = {
386 	{ SYS_RES_IRQ,		0,		RF_ACTIVE | RF_SHAREABLE },
387 	{ -1,			0,		0 }
388 };
389 
390 static struct resource_spec msk_irq_spec_msi[] = {
391 	{ SYS_RES_IRQ,		1,		RF_ACTIVE },
392 	{ -1,			0,		0 }
393 };
394 
395 static int
396 msk_miibus_readreg(device_t dev, int phy, int reg)
397 {
398 	struct msk_if_softc *sc_if;
399 
400 	sc_if = device_get_softc(dev);
401 
402 	return (msk_phy_readreg(sc_if, phy, reg));
403 }
404 
405 static int
406 msk_phy_readreg(struct msk_if_softc *sc_if, int phy, int reg)
407 {
408 	struct msk_softc *sc;
409 	int i, val;
410 
411 	sc = sc_if->msk_softc;
412 
413         GMAC_WRITE_2(sc, sc_if->msk_port, GM_SMI_CTRL,
414 	    GM_SMI_CT_PHY_AD(phy) | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
415 
416 	for (i = 0; i < MSK_TIMEOUT; i++) {
417 		DELAY(1);
418 		val = GMAC_READ_2(sc, sc_if->msk_port, GM_SMI_CTRL);
419 		if ((val & GM_SMI_CT_RD_VAL) != 0) {
420 			val = GMAC_READ_2(sc, sc_if->msk_port, GM_SMI_DATA);
421 			break;
422 		}
423 	}
424 
425 	if (i == MSK_TIMEOUT) {
426 		if_printf(sc_if->msk_ifp, "phy failed to come ready\n");
427 		val = 0;
428 	}
429 
430 	return (val);
431 }
432 
433 static int
434 msk_miibus_writereg(device_t dev, int phy, int reg, int val)
435 {
436 	struct msk_if_softc *sc_if;
437 
438 	sc_if = device_get_softc(dev);
439 
440 	return (msk_phy_writereg(sc_if, phy, reg, val));
441 }
442 
443 static int
444 msk_phy_writereg(struct msk_if_softc *sc_if, int phy, int reg, int val)
445 {
446 	struct msk_softc *sc;
447 	int i;
448 
449 	sc = sc_if->msk_softc;
450 
451 	GMAC_WRITE_2(sc, sc_if->msk_port, GM_SMI_DATA, val);
452         GMAC_WRITE_2(sc, sc_if->msk_port, GM_SMI_CTRL,
453 	    GM_SMI_CT_PHY_AD(phy) | GM_SMI_CT_REG_AD(reg));
454 	for (i = 0; i < MSK_TIMEOUT; i++) {
455 		DELAY(1);
456 		if ((GMAC_READ_2(sc, sc_if->msk_port, GM_SMI_CTRL) &
457 		    GM_SMI_CT_BUSY) == 0)
458 			break;
459 	}
460 	if (i == MSK_TIMEOUT)
461 		if_printf(sc_if->msk_ifp, "phy write timeout\n");
462 
463 	return (0);
464 }
465 
466 static void
467 msk_miibus_statchg(device_t dev)
468 {
469 	struct msk_softc *sc;
470 	struct msk_if_softc *sc_if;
471 	struct mii_data *mii;
472 	struct ifnet *ifp;
473 	uint32_t gmac;
474 
475 	sc_if = device_get_softc(dev);
476 	sc = sc_if->msk_softc;
477 
478 	MSK_IF_LOCK_ASSERT(sc_if);
479 
480 	mii = device_get_softc(sc_if->msk_miibus);
481 	ifp = sc_if->msk_ifp;
482 	if (mii == NULL || ifp == NULL ||
483 	    (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
484 		return;
485 
486 	sc_if->msk_flags &= ~MSK_FLAG_LINK;
487 	if ((mii->mii_media_status & (IFM_AVALID | IFM_ACTIVE)) ==
488 	    (IFM_AVALID | IFM_ACTIVE)) {
489 		switch (IFM_SUBTYPE(mii->mii_media_active)) {
490 		case IFM_10_T:
491 		case IFM_100_TX:
492 			sc_if->msk_flags |= MSK_FLAG_LINK;
493 			break;
494 		case IFM_1000_T:
495 		case IFM_1000_SX:
496 		case IFM_1000_LX:
497 		case IFM_1000_CX:
498 			if ((sc_if->msk_flags & MSK_FLAG_FASTETHER) == 0)
499 				sc_if->msk_flags |= MSK_FLAG_LINK;
500 			break;
501 		default:
502 			break;
503 		}
504 	}
505 
506 	if ((sc_if->msk_flags & MSK_FLAG_LINK) != 0) {
507 		/* Enable Tx FIFO Underrun. */
508 		CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_MSK),
509 		    GM_IS_TX_FF_UR | GM_IS_RX_FF_OR);
510 		/*
511 		 * Because mii(4) notify msk(4) that it detected link status
512 		 * change, there is no need to enable automatic
513 		 * speed/flow-control/duplex updates.
514 		 */
515 		gmac = GM_GPCR_AU_ALL_DIS;
516 		switch (IFM_SUBTYPE(mii->mii_media_active)) {
517 		case IFM_1000_SX:
518 		case IFM_1000_T:
519 			gmac |= GM_GPCR_SPEED_1000;
520 			break;
521 		case IFM_100_TX:
522 			gmac |= GM_GPCR_SPEED_100;
523 			break;
524 		case IFM_10_T:
525 			break;
526 		}
527 
528 		if ((IFM_OPTIONS(mii->mii_media_active) &
529 		    IFM_ETH_RXPAUSE) == 0)
530 			gmac |= GM_GPCR_FC_RX_DIS;
531 		if ((IFM_OPTIONS(mii->mii_media_active) &
532 		     IFM_ETH_TXPAUSE) == 0)
533 			gmac |= GM_GPCR_FC_TX_DIS;
534 		if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0)
535 			gmac |= GM_GPCR_DUP_FULL;
536 		else
537 			gmac |= GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS;
538 		gmac |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
539 		GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, gmac);
540 		/* Read again to ensure writing. */
541 		GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL);
542 		gmac = GMC_PAUSE_OFF;
543 		if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
544 			if ((IFM_OPTIONS(mii->mii_media_active) &
545 			    IFM_ETH_RXPAUSE) != 0)
546 				gmac = GMC_PAUSE_ON;
547 		}
548 		CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), gmac);
549 
550 		/* Enable PHY interrupt for FIFO underrun/overflow. */
551 		msk_phy_writereg(sc_if, PHY_ADDR_MARV,
552 		    PHY_MARV_INT_MASK, PHY_M_IS_FIFO_ERROR);
553 	} else {
554 		/*
555 		 * Link state changed to down.
556 		 * Disable PHY interrupts.
557 		 */
558 		msk_phy_writereg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_MASK, 0);
559 		/* Disable Rx/Tx MAC. */
560 		gmac = GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL);
561 		if ((gmac & (GM_GPCR_RX_ENA | GM_GPCR_TX_ENA)) != 0) {
562 			gmac &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
563 			GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, gmac);
564 			/* Read again to ensure writing. */
565 			GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL);
566 		}
567 	}
568 }
569 
570 static void
571 msk_rxfilter(struct msk_if_softc *sc_if)
572 {
573 	struct msk_softc *sc;
574 	struct ifnet *ifp;
575 	struct ifmultiaddr *ifma;
576 	uint32_t mchash[2];
577 	uint32_t crc;
578 	uint16_t mode;
579 
580 	sc = sc_if->msk_softc;
581 
582 	MSK_IF_LOCK_ASSERT(sc_if);
583 
584 	ifp = sc_if->msk_ifp;
585 
586 	bzero(mchash, sizeof(mchash));
587 	mode = GMAC_READ_2(sc, sc_if->msk_port, GM_RX_CTRL);
588 	if ((ifp->if_flags & IFF_PROMISC) != 0)
589 		mode &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
590 	else if ((ifp->if_flags & IFF_ALLMULTI) != 0) {
591 		mode |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
592 		mchash[0] = 0xffff;
593 		mchash[1] = 0xffff;
594 	} else {
595 		mode |= GM_RXCR_UCF_ENA;
596 		if_maddr_rlock(ifp);
597 		TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
598 			if (ifma->ifma_addr->sa_family != AF_LINK)
599 				continue;
600 			crc = ether_crc32_be(LLADDR((struct sockaddr_dl *)
601 			    ifma->ifma_addr), ETHER_ADDR_LEN);
602 			/* Just want the 6 least significant bits. */
603 			crc &= 0x3f;
604 			/* Set the corresponding bit in the hash table. */
605 			mchash[crc >> 5] |= 1 << (crc & 0x1f);
606 		}
607 		if_maddr_runlock(ifp);
608 		if (mchash[0] != 0 || mchash[1] != 0)
609 			mode |= GM_RXCR_MCF_ENA;
610 	}
611 
612 	GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H1,
613 	    mchash[0] & 0xffff);
614 	GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H2,
615 	    (mchash[0] >> 16) & 0xffff);
616 	GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H3,
617 	    mchash[1] & 0xffff);
618 	GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H4,
619 	    (mchash[1] >> 16) & 0xffff);
620 	GMAC_WRITE_2(sc, sc_if->msk_port, GM_RX_CTRL, mode);
621 }
622 
623 static void
624 msk_setvlan(struct msk_if_softc *sc_if, struct ifnet *ifp)
625 {
626 	struct msk_softc *sc;
627 
628 	sc = sc_if->msk_softc;
629 	if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) {
630 		CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T),
631 		    RX_VLAN_STRIP_ON);
632 		CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T),
633 		    TX_VLAN_TAG_ON);
634 	} else {
635 		CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T),
636 		    RX_VLAN_STRIP_OFF);
637 		CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T),
638 		    TX_VLAN_TAG_OFF);
639 	}
640 }
641 
642 static int
643 msk_rx_fill(struct msk_if_softc *sc_if, int jumbo)
644 {
645 	uint16_t idx;
646 	int i;
647 
648 	if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0 &&
649 	    (sc_if->msk_ifp->if_capenable & IFCAP_RXCSUM) != 0) {
650 		/* Wait until controller executes OP_TCPSTART command. */
651 		for (i = 100; i > 0; i--) {
652 			DELAY(100);
653 			idx = CSR_READ_2(sc_if->msk_softc,
654 			    Y2_PREF_Q_ADDR(sc_if->msk_rxq,
655 			    PREF_UNIT_GET_IDX_REG));
656 			if (idx != 0)
657 				break;
658 		}
659 		if (i == 0) {
660 			device_printf(sc_if->msk_if_dev,
661 			    "prefetch unit stuck?\n");
662 			return (ETIMEDOUT);
663 		}
664 		/*
665 		 * Fill consumed LE with free buffer. This can be done
666 		 * in Rx handler but we don't want to add special code
667 		 * in fast handler.
668 		 */
669 		if (jumbo > 0) {
670 			if (msk_jumbo_newbuf(sc_if, 0) != 0)
671 				return (ENOBUFS);
672 			bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_ring_tag,
673 			    sc_if->msk_cdata.msk_jumbo_rx_ring_map,
674 			    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
675 		} else {
676 			if (msk_newbuf(sc_if, 0) != 0)
677 				return (ENOBUFS);
678 			bus_dmamap_sync(sc_if->msk_cdata.msk_rx_ring_tag,
679 			    sc_if->msk_cdata.msk_rx_ring_map,
680 			    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
681 		}
682 		sc_if->msk_cdata.msk_rx_prod = 0;
683 		CSR_WRITE_2(sc_if->msk_softc,
684 		    Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_PUT_IDX_REG),
685 		    sc_if->msk_cdata.msk_rx_prod);
686 	}
687 	return (0);
688 }
689 
690 static int
691 msk_init_rx_ring(struct msk_if_softc *sc_if)
692 {
693 	struct msk_ring_data *rd;
694 	struct msk_rxdesc *rxd;
695 	int i, nbuf, prod;
696 
697 	MSK_IF_LOCK_ASSERT(sc_if);
698 
699 	sc_if->msk_cdata.msk_rx_cons = 0;
700 	sc_if->msk_cdata.msk_rx_prod = 0;
701 	sc_if->msk_cdata.msk_rx_putwm = MSK_PUT_WM;
702 
703 	rd = &sc_if->msk_rdata;
704 	bzero(rd->msk_rx_ring, sizeof(struct msk_rx_desc) * MSK_RX_RING_CNT);
705 	for (i = prod = 0; i < MSK_RX_RING_CNT; i++) {
706 		rxd = &sc_if->msk_cdata.msk_rxdesc[prod];
707 		rxd->rx_m = NULL;
708 		rxd->rx_le = &rd->msk_rx_ring[prod];
709 		MSK_INC(prod, MSK_RX_RING_CNT);
710 	}
711 	nbuf = MSK_RX_BUF_CNT;
712 	prod = 0;
713 	/* Have controller know how to compute Rx checksum. */
714 	if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0 &&
715 	    (sc_if->msk_ifp->if_capenable & IFCAP_RXCSUM) != 0) {
716 #ifdef MSK_64BIT_DMA
717 		rxd = &sc_if->msk_cdata.msk_rxdesc[prod];
718 		rxd->rx_m = NULL;
719 		rxd->rx_le = &rd->msk_rx_ring[prod];
720 		rxd->rx_le->msk_addr = htole32(ETHER_HDR_LEN << 16 |
721 		    ETHER_HDR_LEN);
722 		rxd->rx_le->msk_control = htole32(OP_TCPSTART | HW_OWNER);
723 		MSK_INC(prod, MSK_RX_RING_CNT);
724 		MSK_INC(sc_if->msk_cdata.msk_rx_cons, MSK_RX_RING_CNT);
725 #endif
726 		rxd = &sc_if->msk_cdata.msk_rxdesc[prod];
727 		rxd->rx_m = NULL;
728 		rxd->rx_le = &rd->msk_rx_ring[prod];
729 		rxd->rx_le->msk_addr = htole32(ETHER_HDR_LEN << 16 |
730 		    ETHER_HDR_LEN);
731 		rxd->rx_le->msk_control = htole32(OP_TCPSTART | HW_OWNER);
732 		MSK_INC(prod, MSK_RX_RING_CNT);
733 		MSK_INC(sc_if->msk_cdata.msk_rx_cons, MSK_RX_RING_CNT);
734 		nbuf--;
735 	}
736 	for (i = 0; i < nbuf; i++) {
737 		if (msk_newbuf(sc_if, prod) != 0)
738 			return (ENOBUFS);
739 		MSK_RX_INC(prod, MSK_RX_RING_CNT);
740 	}
741 
742 	bus_dmamap_sync(sc_if->msk_cdata.msk_rx_ring_tag,
743 	    sc_if->msk_cdata.msk_rx_ring_map,
744 	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
745 
746 	/* Update prefetch unit. */
747 	sc_if->msk_cdata.msk_rx_prod = prod;
748 	CSR_WRITE_2(sc_if->msk_softc,
749 	    Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_PUT_IDX_REG),
750 	    (sc_if->msk_cdata.msk_rx_prod + MSK_RX_RING_CNT - 1) %
751 	    MSK_RX_RING_CNT);
752 	if (msk_rx_fill(sc_if, 0) != 0)
753 		return (ENOBUFS);
754 	return (0);
755 }
756 
757 static int
758 msk_init_jumbo_rx_ring(struct msk_if_softc *sc_if)
759 {
760 	struct msk_ring_data *rd;
761 	struct msk_rxdesc *rxd;
762 	int i, nbuf, prod;
763 
764 	MSK_IF_LOCK_ASSERT(sc_if);
765 
766 	sc_if->msk_cdata.msk_rx_cons = 0;
767 	sc_if->msk_cdata.msk_rx_prod = 0;
768 	sc_if->msk_cdata.msk_rx_putwm = MSK_PUT_WM;
769 
770 	rd = &sc_if->msk_rdata;
771 	bzero(rd->msk_jumbo_rx_ring,
772 	    sizeof(struct msk_rx_desc) * MSK_JUMBO_RX_RING_CNT);
773 	for (i = prod = 0; i < MSK_JUMBO_RX_RING_CNT; i++) {
774 		rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[prod];
775 		rxd->rx_m = NULL;
776 		rxd->rx_le = &rd->msk_jumbo_rx_ring[prod];
777 		MSK_INC(prod, MSK_JUMBO_RX_RING_CNT);
778 	}
779 	nbuf = MSK_RX_BUF_CNT;
780 	prod = 0;
781 	/* Have controller know how to compute Rx checksum. */
782 	if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0 &&
783 	    (sc_if->msk_ifp->if_capenable & IFCAP_RXCSUM) != 0) {
784 #ifdef MSK_64BIT_DMA
785 		rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[prod];
786 		rxd->rx_m = NULL;
787 		rxd->rx_le = &rd->msk_jumbo_rx_ring[prod];
788 		rxd->rx_le->msk_addr = htole32(ETHER_HDR_LEN << 16 |
789 		    ETHER_HDR_LEN);
790 		rxd->rx_le->msk_control = htole32(OP_TCPSTART | HW_OWNER);
791 		MSK_INC(prod, MSK_JUMBO_RX_RING_CNT);
792 		MSK_INC(sc_if->msk_cdata.msk_rx_cons, MSK_JUMBO_RX_RING_CNT);
793 #endif
794 		rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[prod];
795 		rxd->rx_m = NULL;
796 		rxd->rx_le = &rd->msk_jumbo_rx_ring[prod];
797 		rxd->rx_le->msk_addr = htole32(ETHER_HDR_LEN << 16 |
798 		    ETHER_HDR_LEN);
799 		rxd->rx_le->msk_control = htole32(OP_TCPSTART | HW_OWNER);
800 		MSK_INC(prod, MSK_JUMBO_RX_RING_CNT);
801 		MSK_INC(sc_if->msk_cdata.msk_rx_cons, MSK_JUMBO_RX_RING_CNT);
802 		nbuf--;
803 	}
804 	for (i = 0; i < nbuf; i++) {
805 		if (msk_jumbo_newbuf(sc_if, prod) != 0)
806 			return (ENOBUFS);
807 		MSK_RX_INC(prod, MSK_JUMBO_RX_RING_CNT);
808 	}
809 
810 	bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_ring_tag,
811 	    sc_if->msk_cdata.msk_jumbo_rx_ring_map,
812 	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
813 
814 	/* Update prefetch unit. */
815 	sc_if->msk_cdata.msk_rx_prod = prod;
816 	CSR_WRITE_2(sc_if->msk_softc,
817 	    Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_PUT_IDX_REG),
818 	    (sc_if->msk_cdata.msk_rx_prod + MSK_JUMBO_RX_RING_CNT - 1) %
819 	    MSK_JUMBO_RX_RING_CNT);
820 	if (msk_rx_fill(sc_if, 1) != 0)
821 		return (ENOBUFS);
822 	return (0);
823 }
824 
825 static void
826 msk_init_tx_ring(struct msk_if_softc *sc_if)
827 {
828 	struct msk_ring_data *rd;
829 	struct msk_txdesc *txd;
830 	int i;
831 
832 	sc_if->msk_cdata.msk_tso_mtu = 0;
833 	sc_if->msk_cdata.msk_last_csum = 0;
834 	sc_if->msk_cdata.msk_tx_prod = 0;
835 	sc_if->msk_cdata.msk_tx_cons = 0;
836 	sc_if->msk_cdata.msk_tx_cnt = 0;
837 	sc_if->msk_cdata.msk_tx_high_addr = 0;
838 
839 	rd = &sc_if->msk_rdata;
840 	bzero(rd->msk_tx_ring, sizeof(struct msk_tx_desc) * MSK_TX_RING_CNT);
841 	for (i = 0; i < MSK_TX_RING_CNT; i++) {
842 		txd = &sc_if->msk_cdata.msk_txdesc[i];
843 		txd->tx_m = NULL;
844 		txd->tx_le = &rd->msk_tx_ring[i];
845 	}
846 
847 	bus_dmamap_sync(sc_if->msk_cdata.msk_tx_ring_tag,
848 	    sc_if->msk_cdata.msk_tx_ring_map,
849 	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
850 }
851 
852 static __inline void
853 msk_discard_rxbuf(struct msk_if_softc *sc_if, int idx)
854 {
855 	struct msk_rx_desc *rx_le;
856 	struct msk_rxdesc *rxd;
857 	struct mbuf *m;
858 
859 #ifdef MSK_64BIT_DMA
860 	rxd = &sc_if->msk_cdata.msk_rxdesc[idx];
861 	rx_le = rxd->rx_le;
862 	rx_le->msk_control = htole32(OP_ADDR64 | HW_OWNER);
863 	MSK_INC(idx, MSK_RX_RING_CNT);
864 #endif
865 	rxd = &sc_if->msk_cdata.msk_rxdesc[idx];
866 	m = rxd->rx_m;
867 	rx_le = rxd->rx_le;
868 	rx_le->msk_control = htole32(m->m_len | OP_PACKET | HW_OWNER);
869 }
870 
871 static __inline void
872 msk_discard_jumbo_rxbuf(struct msk_if_softc *sc_if, int	idx)
873 {
874 	struct msk_rx_desc *rx_le;
875 	struct msk_rxdesc *rxd;
876 	struct mbuf *m;
877 
878 #ifdef MSK_64BIT_DMA
879 	rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[idx];
880 	rx_le = rxd->rx_le;
881 	rx_le->msk_control = htole32(OP_ADDR64 | HW_OWNER);
882 	MSK_INC(idx, MSK_JUMBO_RX_RING_CNT);
883 #endif
884 	rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[idx];
885 	m = rxd->rx_m;
886 	rx_le = rxd->rx_le;
887 	rx_le->msk_control = htole32(m->m_len | OP_PACKET | HW_OWNER);
888 }
889 
890 static int
891 msk_newbuf(struct msk_if_softc *sc_if, int idx)
892 {
893 	struct msk_rx_desc *rx_le;
894 	struct msk_rxdesc *rxd;
895 	struct mbuf *m;
896 	bus_dma_segment_t segs[1];
897 	bus_dmamap_t map;
898 	int nsegs;
899 
900 	m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
901 	if (m == NULL)
902 		return (ENOBUFS);
903 
904 	m->m_len = m->m_pkthdr.len = MCLBYTES;
905 	if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) == 0)
906 		m_adj(m, ETHER_ALIGN);
907 #ifndef __NO_STRICT_ALIGNMENT
908 	else
909 		m_adj(m, MSK_RX_BUF_ALIGN);
910 #endif
911 
912 	if (bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_rx_tag,
913 	    sc_if->msk_cdata.msk_rx_sparemap, m, segs, &nsegs,
914 	    BUS_DMA_NOWAIT) != 0) {
915 		m_freem(m);
916 		return (ENOBUFS);
917 	}
918 	KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
919 
920 	rxd = &sc_if->msk_cdata.msk_rxdesc[idx];
921 #ifdef MSK_64BIT_DMA
922 	rx_le = rxd->rx_le;
923 	rx_le->msk_addr = htole32(MSK_ADDR_HI(segs[0].ds_addr));
924 	rx_le->msk_control = htole32(OP_ADDR64 | HW_OWNER);
925 	MSK_INC(idx, MSK_RX_RING_CNT);
926 	rxd = &sc_if->msk_cdata.msk_rxdesc[idx];
927 #endif
928 	if (rxd->rx_m != NULL) {
929 		bus_dmamap_sync(sc_if->msk_cdata.msk_rx_tag, rxd->rx_dmamap,
930 		    BUS_DMASYNC_POSTREAD);
931 		bus_dmamap_unload(sc_if->msk_cdata.msk_rx_tag, rxd->rx_dmamap);
932 		rxd->rx_m = NULL;
933 	}
934 	map = rxd->rx_dmamap;
935 	rxd->rx_dmamap = sc_if->msk_cdata.msk_rx_sparemap;
936 	sc_if->msk_cdata.msk_rx_sparemap = map;
937 	bus_dmamap_sync(sc_if->msk_cdata.msk_rx_tag, rxd->rx_dmamap,
938 	    BUS_DMASYNC_PREREAD);
939 	rxd->rx_m = m;
940 	rx_le = rxd->rx_le;
941 	rx_le->msk_addr = htole32(MSK_ADDR_LO(segs[0].ds_addr));
942 	rx_le->msk_control =
943 	    htole32(segs[0].ds_len | OP_PACKET | HW_OWNER);
944 
945 	return (0);
946 }
947 
948 static int
949 msk_jumbo_newbuf(struct msk_if_softc *sc_if, int idx)
950 {
951 	struct msk_rx_desc *rx_le;
952 	struct msk_rxdesc *rxd;
953 	struct mbuf *m;
954 	bus_dma_segment_t segs[1];
955 	bus_dmamap_t map;
956 	int nsegs;
957 
958 	m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES);
959 	if (m == NULL)
960 		return (ENOBUFS);
961 	if ((m->m_flags & M_EXT) == 0) {
962 		m_freem(m);
963 		return (ENOBUFS);
964 	}
965 	m->m_len = m->m_pkthdr.len = MJUM9BYTES;
966 	if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) == 0)
967 		m_adj(m, ETHER_ALIGN);
968 #ifndef __NO_STRICT_ALIGNMENT
969 	else
970 		m_adj(m, MSK_RX_BUF_ALIGN);
971 #endif
972 
973 	if (bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_jumbo_rx_tag,
974 	    sc_if->msk_cdata.msk_jumbo_rx_sparemap, m, segs, &nsegs,
975 	    BUS_DMA_NOWAIT) != 0) {
976 		m_freem(m);
977 		return (ENOBUFS);
978 	}
979 	KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
980 
981 	rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[idx];
982 #ifdef MSK_64BIT_DMA
983 	rx_le = rxd->rx_le;
984 	rx_le->msk_addr = htole32(MSK_ADDR_HI(segs[0].ds_addr));
985 	rx_le->msk_control = htole32(OP_ADDR64 | HW_OWNER);
986 	MSK_INC(idx, MSK_JUMBO_RX_RING_CNT);
987 	rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[idx];
988 #endif
989 	if (rxd->rx_m != NULL) {
990 		bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_tag,
991 		    rxd->rx_dmamap, BUS_DMASYNC_POSTREAD);
992 		bus_dmamap_unload(sc_if->msk_cdata.msk_jumbo_rx_tag,
993 		    rxd->rx_dmamap);
994 		rxd->rx_m = NULL;
995 	}
996 	map = rxd->rx_dmamap;
997 	rxd->rx_dmamap = sc_if->msk_cdata.msk_jumbo_rx_sparemap;
998 	sc_if->msk_cdata.msk_jumbo_rx_sparemap = map;
999 	bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_tag, rxd->rx_dmamap,
1000 	    BUS_DMASYNC_PREREAD);
1001 	rxd->rx_m = m;
1002 	rx_le = rxd->rx_le;
1003 	rx_le->msk_addr = htole32(MSK_ADDR_LO(segs[0].ds_addr));
1004 	rx_le->msk_control =
1005 	    htole32(segs[0].ds_len | OP_PACKET | HW_OWNER);
1006 
1007 	return (0);
1008 }
1009 
1010 /*
1011  * Set media options.
1012  */
1013 static int
1014 msk_mediachange(struct ifnet *ifp)
1015 {
1016 	struct msk_if_softc *sc_if;
1017 	struct mii_data	*mii;
1018 	int error;
1019 
1020 	sc_if = ifp->if_softc;
1021 
1022 	MSK_IF_LOCK(sc_if);
1023 	mii = device_get_softc(sc_if->msk_miibus);
1024 	error = mii_mediachg(mii);
1025 	MSK_IF_UNLOCK(sc_if);
1026 
1027 	return (error);
1028 }
1029 
1030 /*
1031  * Report current media status.
1032  */
1033 static void
1034 msk_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
1035 {
1036 	struct msk_if_softc *sc_if;
1037 	struct mii_data	*mii;
1038 
1039 	sc_if = ifp->if_softc;
1040 	MSK_IF_LOCK(sc_if);
1041 	if ((ifp->if_flags & IFF_UP) == 0) {
1042 		MSK_IF_UNLOCK(sc_if);
1043 		return;
1044 	}
1045 	mii = device_get_softc(sc_if->msk_miibus);
1046 
1047 	mii_pollstat(mii);
1048 	ifmr->ifm_active = mii->mii_media_active;
1049 	ifmr->ifm_status = mii->mii_media_status;
1050 	MSK_IF_UNLOCK(sc_if);
1051 }
1052 
1053 static int
1054 msk_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
1055 {
1056 	struct msk_if_softc *sc_if;
1057 	struct ifreq *ifr;
1058 	struct mii_data	*mii;
1059 	int error, mask, reinit;
1060 
1061 	sc_if = ifp->if_softc;
1062 	ifr = (struct ifreq *)data;
1063 	error = 0;
1064 
1065 	switch(command) {
1066 	case SIOCSIFMTU:
1067 		MSK_IF_LOCK(sc_if);
1068 		if (ifr->ifr_mtu > MSK_JUMBO_MTU || ifr->ifr_mtu < ETHERMIN)
1069 			error = EINVAL;
1070 		else if (ifp->if_mtu != ifr->ifr_mtu) {
1071 			if (ifr->ifr_mtu > ETHERMTU) {
1072 				if ((sc_if->msk_flags & MSK_FLAG_JUMBO) == 0) {
1073 					error = EINVAL;
1074 					MSK_IF_UNLOCK(sc_if);
1075 					break;
1076 				}
1077 				if ((sc_if->msk_flags &
1078 				    MSK_FLAG_JUMBO_NOCSUM) != 0) {
1079 					ifp->if_hwassist &=
1080 					    ~(MSK_CSUM_FEATURES | CSUM_TSO);
1081 					ifp->if_capenable &=
1082 					    ~(IFCAP_TSO4 | IFCAP_TXCSUM);
1083 					VLAN_CAPABILITIES(ifp);
1084 				}
1085 			}
1086 			ifp->if_mtu = ifr->ifr_mtu;
1087 			if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
1088 				ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1089 				msk_init_locked(sc_if);
1090 			}
1091 		}
1092 		MSK_IF_UNLOCK(sc_if);
1093 		break;
1094 	case SIOCSIFFLAGS:
1095 		MSK_IF_LOCK(sc_if);
1096 		if ((ifp->if_flags & IFF_UP) != 0) {
1097 			if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 &&
1098 			    ((ifp->if_flags ^ sc_if->msk_if_flags) &
1099 			    (IFF_PROMISC | IFF_ALLMULTI)) != 0)
1100 				msk_rxfilter(sc_if);
1101 			else if ((sc_if->msk_flags & MSK_FLAG_DETACH) == 0)
1102 				msk_init_locked(sc_if);
1103 		} else if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
1104 			msk_stop(sc_if);
1105 		sc_if->msk_if_flags = ifp->if_flags;
1106 		MSK_IF_UNLOCK(sc_if);
1107 		break;
1108 	case SIOCADDMULTI:
1109 	case SIOCDELMULTI:
1110 		MSK_IF_LOCK(sc_if);
1111 		if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
1112 			msk_rxfilter(sc_if);
1113 		MSK_IF_UNLOCK(sc_if);
1114 		break;
1115 	case SIOCGIFMEDIA:
1116 	case SIOCSIFMEDIA:
1117 		mii = device_get_softc(sc_if->msk_miibus);
1118 		error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1119 		break;
1120 	case SIOCSIFCAP:
1121 		reinit = 0;
1122 		MSK_IF_LOCK(sc_if);
1123 		mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1124 		if ((mask & IFCAP_TXCSUM) != 0 &&
1125 		    (IFCAP_TXCSUM & ifp->if_capabilities) != 0) {
1126 			ifp->if_capenable ^= IFCAP_TXCSUM;
1127 			if ((IFCAP_TXCSUM & ifp->if_capenable) != 0)
1128 				ifp->if_hwassist |= MSK_CSUM_FEATURES;
1129 			else
1130 				ifp->if_hwassist &= ~MSK_CSUM_FEATURES;
1131 		}
1132 		if ((mask & IFCAP_RXCSUM) != 0 &&
1133 		    (IFCAP_RXCSUM & ifp->if_capabilities) != 0) {
1134 			ifp->if_capenable ^= IFCAP_RXCSUM;
1135 			if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0)
1136 				reinit = 1;
1137 		}
1138 		if ((mask & IFCAP_VLAN_HWCSUM) != 0 &&
1139 		    (IFCAP_VLAN_HWCSUM & ifp->if_capabilities) != 0)
1140 			ifp->if_capenable ^= IFCAP_VLAN_HWCSUM;
1141 		if ((mask & IFCAP_TSO4) != 0 &&
1142 		    (IFCAP_TSO4 & ifp->if_capabilities) != 0) {
1143 			ifp->if_capenable ^= IFCAP_TSO4;
1144 			if ((IFCAP_TSO4 & ifp->if_capenable) != 0)
1145 				ifp->if_hwassist |= CSUM_TSO;
1146 			else
1147 				ifp->if_hwassist &= ~CSUM_TSO;
1148 		}
1149 		if ((mask & IFCAP_VLAN_HWTSO) != 0 &&
1150 		    (IFCAP_VLAN_HWTSO & ifp->if_capabilities) != 0)
1151 			ifp->if_capenable ^= IFCAP_VLAN_HWTSO;
1152 		if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
1153 		    (IFCAP_VLAN_HWTAGGING & ifp->if_capabilities) != 0) {
1154 			ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
1155 			if ((IFCAP_VLAN_HWTAGGING & ifp->if_capenable) == 0)
1156 				ifp->if_capenable &=
1157 				    ~(IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM);
1158 			msk_setvlan(sc_if, ifp);
1159 		}
1160 		if (ifp->if_mtu > ETHERMTU &&
1161 		    (sc_if->msk_flags & MSK_FLAG_JUMBO_NOCSUM) != 0) {
1162 			ifp->if_hwassist &= ~(MSK_CSUM_FEATURES | CSUM_TSO);
1163 			ifp->if_capenable &= ~(IFCAP_TSO4 | IFCAP_TXCSUM);
1164 		}
1165 		VLAN_CAPABILITIES(ifp);
1166 		if (reinit > 0 && (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
1167 			ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1168 			msk_init_locked(sc_if);
1169 		}
1170 		MSK_IF_UNLOCK(sc_if);
1171 		break;
1172 	default:
1173 		error = ether_ioctl(ifp, command, data);
1174 		break;
1175 	}
1176 
1177 	return (error);
1178 }
1179 
1180 static int
1181 mskc_probe(device_t dev)
1182 {
1183 	struct msk_product *mp;
1184 	uint16_t vendor, devid;
1185 	int i;
1186 
1187 	vendor = pci_get_vendor(dev);
1188 	devid = pci_get_device(dev);
1189 	mp = msk_products;
1190 	for (i = 0; i < sizeof(msk_products)/sizeof(msk_products[0]);
1191 	    i++, mp++) {
1192 		if (vendor == mp->msk_vendorid && devid == mp->msk_deviceid) {
1193 			device_set_desc(dev, mp->msk_name);
1194 			return (BUS_PROBE_DEFAULT);
1195 		}
1196 	}
1197 
1198 	return (ENXIO);
1199 }
1200 
1201 static int
1202 mskc_setup_rambuffer(struct msk_softc *sc)
1203 {
1204 	int next;
1205 	int i;
1206 
1207 	/* Get adapter SRAM size. */
1208 	sc->msk_ramsize = CSR_READ_1(sc, B2_E_0) * 4;
1209 	if (bootverbose)
1210 		device_printf(sc->msk_dev,
1211 		    "RAM buffer size : %dKB\n", sc->msk_ramsize);
1212 	if (sc->msk_ramsize == 0)
1213 		return (0);
1214 
1215 	sc->msk_pflags |= MSK_FLAG_RAMBUF;
1216 	/*
1217 	 * Give receiver 2/3 of memory and round down to the multiple
1218 	 * of 1024. Tx/Rx RAM buffer size of Yukon II should be multiple
1219 	 * of 1024.
1220 	 */
1221 	sc->msk_rxqsize = rounddown((sc->msk_ramsize * 1024 * 2) / 3, 1024);
1222 	sc->msk_txqsize = (sc->msk_ramsize * 1024) - sc->msk_rxqsize;
1223 	for (i = 0, next = 0; i < sc->msk_num_port; i++) {
1224 		sc->msk_rxqstart[i] = next;
1225 		sc->msk_rxqend[i] = next + sc->msk_rxqsize - 1;
1226 		next = sc->msk_rxqend[i] + 1;
1227 		sc->msk_txqstart[i] = next;
1228 		sc->msk_txqend[i] = next + sc->msk_txqsize - 1;
1229 		next = sc->msk_txqend[i] + 1;
1230 		if (bootverbose) {
1231 			device_printf(sc->msk_dev,
1232 			    "Port %d : Rx Queue %dKB(0x%08x:0x%08x)\n", i,
1233 			    sc->msk_rxqsize / 1024, sc->msk_rxqstart[i],
1234 			    sc->msk_rxqend[i]);
1235 			device_printf(sc->msk_dev,
1236 			    "Port %d : Tx Queue %dKB(0x%08x:0x%08x)\n", i,
1237 			    sc->msk_txqsize / 1024, sc->msk_txqstart[i],
1238 			    sc->msk_txqend[i]);
1239 		}
1240 	}
1241 
1242 	return (0);
1243 }
1244 
1245 static void
1246 msk_phy_power(struct msk_softc *sc, int mode)
1247 {
1248 	uint32_t our, val;
1249 	int i;
1250 
1251 	switch (mode) {
1252 	case MSK_PHY_POWERUP:
1253 		/* Switch power to VCC (WA for VAUX problem). */
1254 		CSR_WRITE_1(sc, B0_POWER_CTRL,
1255 		    PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
1256 		/* Disable Core Clock Division, set Clock Select to 0. */
1257 		CSR_WRITE_4(sc, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
1258 
1259 		val = 0;
1260 		if (sc->msk_hw_id == CHIP_ID_YUKON_XL &&
1261 		    sc->msk_hw_rev > CHIP_REV_YU_XL_A1) {
1262 			/* Enable bits are inverted. */
1263 			val = Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
1264 			      Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
1265 			      Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS;
1266 		}
1267 		/*
1268 		 * Enable PCI & Core Clock, enable clock gating for both Links.
1269 		 */
1270 		CSR_WRITE_1(sc, B2_Y2_CLK_GATE, val);
1271 
1272 		our = CSR_PCI_READ_4(sc, PCI_OUR_REG_1);
1273 		our &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
1274 		if (sc->msk_hw_id == CHIP_ID_YUKON_XL) {
1275 			if (sc->msk_hw_rev > CHIP_REV_YU_XL_A1) {
1276 				/* Deassert Low Power for 1st PHY. */
1277 				our |= PCI_Y2_PHY1_COMA;
1278 				if (sc->msk_num_port > 1)
1279 					our |= PCI_Y2_PHY2_COMA;
1280 			}
1281 		}
1282 		if (sc->msk_hw_id == CHIP_ID_YUKON_EC_U ||
1283 		    sc->msk_hw_id == CHIP_ID_YUKON_EX ||
1284 		    sc->msk_hw_id >= CHIP_ID_YUKON_FE_P) {
1285 			val = CSR_PCI_READ_4(sc, PCI_OUR_REG_4);
1286 			val &= (PCI_FORCE_ASPM_REQUEST |
1287 			    PCI_ASPM_GPHY_LINK_DOWN | PCI_ASPM_INT_FIFO_EMPTY |
1288 			    PCI_ASPM_CLKRUN_REQUEST);
1289 			/* Set all bits to 0 except bits 15..12. */
1290 			CSR_PCI_WRITE_4(sc, PCI_OUR_REG_4, val);
1291 			val = CSR_PCI_READ_4(sc, PCI_OUR_REG_5);
1292 			val &= PCI_CTL_TIM_VMAIN_AV_MSK;
1293 			CSR_PCI_WRITE_4(sc, PCI_OUR_REG_5, val);
1294 			CSR_PCI_WRITE_4(sc, PCI_CFG_REG_1, 0);
1295 			CSR_WRITE_2(sc, B0_CTST, Y2_HW_WOL_ON);
1296 			/*
1297 			 * Disable status race, workaround for
1298 			 * Yukon EC Ultra & Yukon EX.
1299 			 */
1300 			val = CSR_READ_4(sc, B2_GP_IO);
1301 			val |= GLB_GPIO_STAT_RACE_DIS;
1302 			CSR_WRITE_4(sc, B2_GP_IO, val);
1303 			CSR_READ_4(sc, B2_GP_IO);
1304 		}
1305 		/* Release PHY from PowerDown/COMA mode. */
1306 		CSR_PCI_WRITE_4(sc, PCI_OUR_REG_1, our);
1307 
1308 		for (i = 0; i < sc->msk_num_port; i++) {
1309 			CSR_WRITE_2(sc, MR_ADDR(i, GMAC_LINK_CTRL),
1310 			    GMLC_RST_SET);
1311 			CSR_WRITE_2(sc, MR_ADDR(i, GMAC_LINK_CTRL),
1312 			    GMLC_RST_CLR);
1313 		}
1314 		break;
1315 	case MSK_PHY_POWERDOWN:
1316 		val = CSR_PCI_READ_4(sc, PCI_OUR_REG_1);
1317 		val |= PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD;
1318 		if (sc->msk_hw_id == CHIP_ID_YUKON_XL &&
1319 		    sc->msk_hw_rev > CHIP_REV_YU_XL_A1) {
1320 			val &= ~PCI_Y2_PHY1_COMA;
1321 			if (sc->msk_num_port > 1)
1322 				val &= ~PCI_Y2_PHY2_COMA;
1323 		}
1324 		CSR_PCI_WRITE_4(sc, PCI_OUR_REG_1, val);
1325 
1326 		val = Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
1327 		      Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
1328 		      Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS;
1329 		if (sc->msk_hw_id == CHIP_ID_YUKON_XL &&
1330 		    sc->msk_hw_rev > CHIP_REV_YU_XL_A1) {
1331 			/* Enable bits are inverted. */
1332 			val = 0;
1333 		}
1334 		/*
1335 		 * Disable PCI & Core Clock, disable clock gating for
1336 		 * both Links.
1337 		 */
1338 		CSR_WRITE_1(sc, B2_Y2_CLK_GATE, val);
1339 		CSR_WRITE_1(sc, B0_POWER_CTRL,
1340 		    PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_ON | PC_VCC_OFF);
1341 		break;
1342 	default:
1343 		break;
1344 	}
1345 }
1346 
1347 static void
1348 mskc_reset(struct msk_softc *sc)
1349 {
1350 	bus_addr_t addr;
1351 	uint16_t status;
1352 	uint32_t val;
1353 	int i, initram;
1354 
1355 	/* Disable ASF. */
1356 	if (sc->msk_hw_id >= CHIP_ID_YUKON_XL &&
1357 	    sc->msk_hw_id <= CHIP_ID_YUKON_SUPR) {
1358 		if (sc->msk_hw_id == CHIP_ID_YUKON_EX ||
1359 		    sc->msk_hw_id == CHIP_ID_YUKON_SUPR) {
1360 			CSR_WRITE_4(sc, B28_Y2_CPU_WDOG, 0);
1361 			status = CSR_READ_2(sc, B28_Y2_ASF_HCU_CCSR);
1362 			/* Clear AHB bridge & microcontroller reset. */
1363 			status &= ~(Y2_ASF_HCU_CCSR_AHB_RST |
1364 			    Y2_ASF_HCU_CCSR_CPU_RST_MODE);
1365 			/* Clear ASF microcontroller state. */
1366 			status &= ~Y2_ASF_HCU_CCSR_UC_STATE_MSK;
1367 			status &= ~Y2_ASF_HCU_CCSR_CPU_CLK_DIVIDE_MSK;
1368 			CSR_WRITE_2(sc, B28_Y2_ASF_HCU_CCSR, status);
1369 			CSR_WRITE_4(sc, B28_Y2_CPU_WDOG, 0);
1370 		} else
1371 			CSR_WRITE_1(sc, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
1372 		CSR_WRITE_2(sc, B0_CTST, Y2_ASF_DISABLE);
1373 		/*
1374 		 * Since we disabled ASF, S/W reset is required for
1375 		 * Power Management.
1376 		 */
1377 		CSR_WRITE_2(sc, B0_CTST, CS_RST_SET);
1378 		CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR);
1379 	}
1380 
1381 	/* Clear all error bits in the PCI status register. */
1382 	status = pci_read_config(sc->msk_dev, PCIR_STATUS, 2);
1383 	CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON);
1384 
1385 	pci_write_config(sc->msk_dev, PCIR_STATUS, status |
1386 	    PCIM_STATUS_PERR | PCIM_STATUS_SERR | PCIM_STATUS_RMABORT |
1387 	    PCIM_STATUS_RTABORT | PCIM_STATUS_MDPERR, 2);
1388 	CSR_WRITE_2(sc, B0_CTST, CS_MRST_CLR);
1389 
1390 	switch (sc->msk_bustype) {
1391 	case MSK_PEX_BUS:
1392 		/* Clear all PEX errors. */
1393 		CSR_PCI_WRITE_4(sc, PEX_UNC_ERR_STAT, 0xffffffff);
1394 		val = CSR_PCI_READ_4(sc, PEX_UNC_ERR_STAT);
1395 		if ((val & PEX_RX_OV) != 0) {
1396 			sc->msk_intrmask &= ~Y2_IS_HW_ERR;
1397 			sc->msk_intrhwemask &= ~Y2_IS_PCI_EXP;
1398 		}
1399 		break;
1400 	case MSK_PCI_BUS:
1401 	case MSK_PCIX_BUS:
1402 		/* Set Cache Line Size to 2(8bytes) if configured to 0. */
1403 		val = pci_read_config(sc->msk_dev, PCIR_CACHELNSZ, 1);
1404 		if (val == 0)
1405 			pci_write_config(sc->msk_dev, PCIR_CACHELNSZ, 2, 1);
1406 		if (sc->msk_bustype == MSK_PCIX_BUS) {
1407 			/* Set Cache Line Size opt. */
1408 			val = pci_read_config(sc->msk_dev, PCI_OUR_REG_1, 4);
1409 			val |= PCI_CLS_OPT;
1410 			pci_write_config(sc->msk_dev, PCI_OUR_REG_1, val, 4);
1411 		}
1412 		break;
1413 	}
1414 	/* Set PHY power state. */
1415 	msk_phy_power(sc, MSK_PHY_POWERUP);
1416 
1417 	/* Reset GPHY/GMAC Control */
1418 	for (i = 0; i < sc->msk_num_port; i++) {
1419 		/* GPHY Control reset. */
1420 		CSR_WRITE_1(sc, MR_ADDR(i, GPHY_CTRL), GPC_RST_SET);
1421 		CSR_WRITE_1(sc, MR_ADDR(i, GPHY_CTRL), GPC_RST_CLR);
1422 		/* GMAC Control reset. */
1423 		CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), GMC_RST_SET);
1424 		CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), GMC_RST_CLR);
1425 		CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), GMC_F_LOOPB_OFF);
1426 		if (sc->msk_hw_id == CHIP_ID_YUKON_EX ||
1427 		    sc->msk_hw_id == CHIP_ID_YUKON_SUPR)
1428 			CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL),
1429 			    GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON |
1430 			    GMC_BYP_RETR_ON);
1431 	}
1432 
1433 	if (sc->msk_hw_id == CHIP_ID_YUKON_SUPR &&
1434 	    sc->msk_hw_rev > CHIP_REV_YU_SU_B0)
1435 		CSR_PCI_WRITE_4(sc, PCI_OUR_REG_3, PCI_CLK_MACSEC_DIS);
1436 	if (sc->msk_hw_id == CHIP_ID_YUKON_OPT && sc->msk_hw_rev == 0) {
1437 		/* Disable PCIe PHY powerdown(reg 0x80, bit7). */
1438 		CSR_WRITE_4(sc, Y2_PEX_PHY_DATA, (0x0080 << 16) | 0x0080);
1439 	}
1440 	CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
1441 
1442 	/* LED On. */
1443 	CSR_WRITE_2(sc, B0_CTST, Y2_LED_STAT_ON);
1444 
1445 	/* Clear TWSI IRQ. */
1446 	CSR_WRITE_4(sc, B2_I2C_IRQ, I2C_CLR_IRQ);
1447 
1448 	/* Turn off hardware timer. */
1449 	CSR_WRITE_1(sc, B2_TI_CTRL, TIM_STOP);
1450 	CSR_WRITE_1(sc, B2_TI_CTRL, TIM_CLR_IRQ);
1451 
1452 	/* Turn off descriptor polling. */
1453 	CSR_WRITE_1(sc, B28_DPT_CTRL, DPT_STOP);
1454 
1455 	/* Turn off time stamps. */
1456 	CSR_WRITE_1(sc, GMAC_TI_ST_CTRL, GMT_ST_STOP);
1457 	CSR_WRITE_1(sc, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
1458 
1459 	initram = 0;
1460 	if (sc->msk_hw_id == CHIP_ID_YUKON_XL ||
1461 	    sc->msk_hw_id == CHIP_ID_YUKON_EC ||
1462 	    sc->msk_hw_id == CHIP_ID_YUKON_FE)
1463 		initram++;
1464 
1465 	/* Configure timeout values. */
1466 	for (i = 0; initram > 0 && i < sc->msk_num_port; i++) {
1467 		CSR_WRITE_2(sc, SELECT_RAM_BUFFER(i, B3_RI_CTRL), RI_RST_SET);
1468 		CSR_WRITE_2(sc, SELECT_RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
1469 		CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_R1),
1470 		    MSK_RI_TO_53);
1471 		CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XA1),
1472 		    MSK_RI_TO_53);
1473 		CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XS1),
1474 		    MSK_RI_TO_53);
1475 		CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_R1),
1476 		    MSK_RI_TO_53);
1477 		CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XA1),
1478 		    MSK_RI_TO_53);
1479 		CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XS1),
1480 		    MSK_RI_TO_53);
1481 		CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_R2),
1482 		    MSK_RI_TO_53);
1483 		CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XA2),
1484 		    MSK_RI_TO_53);
1485 		CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XS2),
1486 		    MSK_RI_TO_53);
1487 		CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_R2),
1488 		    MSK_RI_TO_53);
1489 		CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XA2),
1490 		    MSK_RI_TO_53);
1491 		CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XS2),
1492 		    MSK_RI_TO_53);
1493 	}
1494 
1495 	/* Disable all interrupts. */
1496 	CSR_WRITE_4(sc, B0_HWE_IMSK, 0);
1497 	CSR_READ_4(sc, B0_HWE_IMSK);
1498 	CSR_WRITE_4(sc, B0_IMSK, 0);
1499 	CSR_READ_4(sc, B0_IMSK);
1500 
1501         /*
1502          * On dual port PCI-X card, there is an problem where status
1503          * can be received out of order due to split transactions.
1504          */
1505 	if (sc->msk_pcixcap != 0 && sc->msk_num_port > 1) {
1506 		uint16_t pcix_cmd;
1507 
1508 		pcix_cmd = pci_read_config(sc->msk_dev,
1509 		    sc->msk_pcixcap + PCIXR_COMMAND, 2);
1510 		/* Clear Max Outstanding Split Transactions. */
1511 		pcix_cmd &= ~PCIXM_COMMAND_MAX_SPLITS;
1512 		CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON);
1513 		pci_write_config(sc->msk_dev,
1514 		    sc->msk_pcixcap + PCIXR_COMMAND, pcix_cmd, 2);
1515 		CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
1516         }
1517 	if (sc->msk_expcap != 0) {
1518 		/* Change Max. Read Request Size to 2048 bytes. */
1519 		if (pci_get_max_read_req(sc->msk_dev) == 512)
1520 			pci_set_max_read_req(sc->msk_dev, 2048);
1521 	}
1522 
1523 	/* Clear status list. */
1524 	bzero(sc->msk_stat_ring,
1525 	    sizeof(struct msk_stat_desc) * sc->msk_stat_count);
1526 	sc->msk_stat_cons = 0;
1527 	bus_dmamap_sync(sc->msk_stat_tag, sc->msk_stat_map,
1528 	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1529 	CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_RST_SET);
1530 	CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_RST_CLR);
1531 	/* Set the status list base address. */
1532 	addr = sc->msk_stat_ring_paddr;
1533 	CSR_WRITE_4(sc, STAT_LIST_ADDR_LO, MSK_ADDR_LO(addr));
1534 	CSR_WRITE_4(sc, STAT_LIST_ADDR_HI, MSK_ADDR_HI(addr));
1535 	/* Set the status list last index. */
1536 	CSR_WRITE_2(sc, STAT_LAST_IDX, sc->msk_stat_count - 1);
1537 	if (sc->msk_hw_id == CHIP_ID_YUKON_EC &&
1538 	    sc->msk_hw_rev == CHIP_REV_YU_EC_A1) {
1539 		/* WA for dev. #4.3 */
1540 		CSR_WRITE_2(sc, STAT_TX_IDX_TH, ST_TXTH_IDX_MASK);
1541 		/* WA for dev. #4.18 */
1542 		CSR_WRITE_1(sc, STAT_FIFO_WM, 0x21);
1543 		CSR_WRITE_1(sc, STAT_FIFO_ISR_WM, 0x07);
1544 	} else {
1545 		CSR_WRITE_2(sc, STAT_TX_IDX_TH, 0x0a);
1546 		CSR_WRITE_1(sc, STAT_FIFO_WM, 0x10);
1547 		if (sc->msk_hw_id == CHIP_ID_YUKON_XL &&
1548 		    sc->msk_hw_rev == CHIP_REV_YU_XL_A0)
1549 			CSR_WRITE_1(sc, STAT_FIFO_ISR_WM, 0x04);
1550 		else
1551 			CSR_WRITE_1(sc, STAT_FIFO_ISR_WM, 0x10);
1552 		CSR_WRITE_4(sc, STAT_ISR_TIMER_INI, 0x0190);
1553 	}
1554 	/*
1555 	 * Use default value for STAT_ISR_TIMER_INI, STAT_LEV_TIMER_INI.
1556 	 */
1557 	CSR_WRITE_4(sc, STAT_TX_TIMER_INI, MSK_USECS(sc, 1000));
1558 
1559 	/* Enable status unit. */
1560 	CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_OP_ON);
1561 
1562 	CSR_WRITE_1(sc, STAT_TX_TIMER_CTRL, TIM_START);
1563 	CSR_WRITE_1(sc, STAT_LEV_TIMER_CTRL, TIM_START);
1564 	CSR_WRITE_1(sc, STAT_ISR_TIMER_CTRL, TIM_START);
1565 }
1566 
1567 static int
1568 msk_probe(device_t dev)
1569 {
1570 	struct msk_softc *sc;
1571 	char desc[100];
1572 
1573 	sc = device_get_softc(device_get_parent(dev));
1574 	/*
1575 	 * Not much to do here. We always know there will be
1576 	 * at least one GMAC present, and if there are two,
1577 	 * mskc_attach() will create a second device instance
1578 	 * for us.
1579 	 */
1580 	snprintf(desc, sizeof(desc),
1581 	    "Marvell Technology Group Ltd. %s Id 0x%02x Rev 0x%02x",
1582 	    model_name[sc->msk_hw_id - CHIP_ID_YUKON_XL], sc->msk_hw_id,
1583 	    sc->msk_hw_rev);
1584 	device_set_desc_copy(dev, desc);
1585 
1586 	return (BUS_PROBE_DEFAULT);
1587 }
1588 
1589 static int
1590 msk_attach(device_t dev)
1591 {
1592 	struct msk_softc *sc;
1593 	struct msk_if_softc *sc_if;
1594 	struct ifnet *ifp;
1595 	struct msk_mii_data *mmd;
1596 	int i, port, error;
1597 	uint8_t eaddr[6];
1598 
1599 	if (dev == NULL)
1600 		return (EINVAL);
1601 
1602 	error = 0;
1603 	sc_if = device_get_softc(dev);
1604 	sc = device_get_softc(device_get_parent(dev));
1605 	mmd = device_get_ivars(dev);
1606 	port = mmd->port;
1607 
1608 	sc_if->msk_if_dev = dev;
1609 	sc_if->msk_port = port;
1610 	sc_if->msk_softc = sc;
1611 	sc_if->msk_flags = sc->msk_pflags;
1612 	sc->msk_if[port] = sc_if;
1613 	/* Setup Tx/Rx queue register offsets. */
1614 	if (port == MSK_PORT_A) {
1615 		sc_if->msk_txq = Q_XA1;
1616 		sc_if->msk_txsq = Q_XS1;
1617 		sc_if->msk_rxq = Q_R1;
1618 	} else {
1619 		sc_if->msk_txq = Q_XA2;
1620 		sc_if->msk_txsq = Q_XS2;
1621 		sc_if->msk_rxq = Q_R2;
1622 	}
1623 
1624 	callout_init_mtx(&sc_if->msk_tick_ch, &sc_if->msk_softc->msk_mtx, 0);
1625 	msk_sysctl_node(sc_if);
1626 
1627 	if ((error = msk_txrx_dma_alloc(sc_if) != 0))
1628 		goto fail;
1629 	msk_rx_dma_jalloc(sc_if);
1630 
1631 	ifp = sc_if->msk_ifp = if_alloc(IFT_ETHER);
1632 	if (ifp == NULL) {
1633 		device_printf(sc_if->msk_if_dev, "can not if_alloc()\n");
1634 		error = ENOSPC;
1635 		goto fail;
1636 	}
1637 	ifp->if_softc = sc_if;
1638 	if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1639 	ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1640 	ifp->if_capabilities = IFCAP_TXCSUM | IFCAP_TSO4;
1641 	/*
1642 	 * Enable Rx checksum offloading if controller supports
1643 	 * new descriptor formant and controller is not Yukon XL.
1644 	 */
1645 	if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0 &&
1646 	    sc->msk_hw_id != CHIP_ID_YUKON_XL)
1647 		ifp->if_capabilities |= IFCAP_RXCSUM;
1648 	if ((sc_if->msk_flags & MSK_FLAG_DESCV2) != 0 &&
1649 	    (sc_if->msk_flags & MSK_FLAG_NORX_CSUM) == 0)
1650 		ifp->if_capabilities |= IFCAP_RXCSUM;
1651 	ifp->if_hwassist = MSK_CSUM_FEATURES | CSUM_TSO;
1652 	ifp->if_capenable = ifp->if_capabilities;
1653 	ifp->if_ioctl = msk_ioctl;
1654 	ifp->if_start = msk_start;
1655 	ifp->if_init = msk_init;
1656 	IFQ_SET_MAXLEN(&ifp->if_snd, MSK_TX_RING_CNT - 1);
1657 	ifp->if_snd.ifq_drv_maxlen = MSK_TX_RING_CNT - 1;
1658 	IFQ_SET_READY(&ifp->if_snd);
1659 	/*
1660 	 * Get station address for this interface. Note that
1661 	 * dual port cards actually come with three station
1662 	 * addresses: one for each port, plus an extra. The
1663 	 * extra one is used by the SysKonnect driver software
1664 	 * as a 'virtual' station address for when both ports
1665 	 * are operating in failover mode. Currently we don't
1666 	 * use this extra address.
1667 	 */
1668 	MSK_IF_LOCK(sc_if);
1669 	for (i = 0; i < ETHER_ADDR_LEN; i++)
1670 		eaddr[i] = CSR_READ_1(sc, B2_MAC_1 + (port * 8) + i);
1671 
1672 	/*
1673 	 * Call MI attach routine.  Can't hold locks when calling into ether_*.
1674 	 */
1675 	MSK_IF_UNLOCK(sc_if);
1676 	ether_ifattach(ifp, eaddr);
1677 	MSK_IF_LOCK(sc_if);
1678 
1679 	/* VLAN capability setup */
1680 	ifp->if_capabilities |= IFCAP_VLAN_MTU;
1681 	if ((sc_if->msk_flags & MSK_FLAG_NOHWVLAN) == 0) {
1682 		/*
1683 		 * Due to Tx checksum offload hardware bugs, msk(4) manually
1684 		 * computes checksum for short frames. For VLAN tagged frames
1685 		 * this workaround does not work so disable checksum offload
1686 		 * for VLAN interface.
1687 		 */
1688 		ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWTSO;
1689 		/*
1690 		 * Enable Rx checksum offloading for VLAN tagged frames
1691 		 * if controller support new descriptor format.
1692 		 */
1693 		if ((sc_if->msk_flags & MSK_FLAG_DESCV2) != 0 &&
1694 		    (sc_if->msk_flags & MSK_FLAG_NORX_CSUM) == 0)
1695 			ifp->if_capabilities |= IFCAP_VLAN_HWCSUM;
1696 	}
1697 	ifp->if_capenable = ifp->if_capabilities;
1698 	/*
1699 	 * Disable RX checksum offloading on controllers that don't use
1700 	 * new descriptor format but give chance to enable it.
1701 	 */
1702 	if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0)
1703 		ifp->if_capenable &= ~IFCAP_RXCSUM;
1704 
1705 	/*
1706 	 * Tell the upper layer(s) we support long frames.
1707 	 * Must appear after the call to ether_ifattach() because
1708 	 * ether_ifattach() sets ifi_hdrlen to the default value.
1709 	 */
1710         ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1711 
1712 	/*
1713 	 * Do miibus setup.
1714 	 */
1715 	MSK_IF_UNLOCK(sc_if);
1716 	error = mii_attach(dev, &sc_if->msk_miibus, ifp, msk_mediachange,
1717 	    msk_mediastatus, BMSR_DEFCAPMASK, PHY_ADDR_MARV, MII_OFFSET_ANY,
1718 	    mmd->mii_flags);
1719 	if (error != 0) {
1720 		device_printf(sc_if->msk_if_dev, "attaching PHYs failed\n");
1721 		ether_ifdetach(ifp);
1722 		error = ENXIO;
1723 		goto fail;
1724 	}
1725 
1726 fail:
1727 	if (error != 0) {
1728 		/* Access should be ok even though lock has been dropped */
1729 		sc->msk_if[port] = NULL;
1730 		msk_detach(dev);
1731 	}
1732 
1733 	return (error);
1734 }
1735 
1736 /*
1737  * Attach the interface. Allocate softc structures, do ifmedia
1738  * setup and ethernet/BPF attach.
1739  */
1740 static int
1741 mskc_attach(device_t dev)
1742 {
1743 	struct msk_softc *sc;
1744 	struct msk_mii_data *mmd;
1745 	int error, msic, msir, reg;
1746 
1747 	sc = device_get_softc(dev);
1748 	sc->msk_dev = dev;
1749 	mtx_init(&sc->msk_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
1750 	    MTX_DEF);
1751 
1752 	/*
1753 	 * Map control/status registers.
1754 	 */
1755 	pci_enable_busmaster(dev);
1756 
1757 	/* Allocate I/O resource */
1758 #ifdef MSK_USEIOSPACE
1759 	sc->msk_res_spec = msk_res_spec_io;
1760 #else
1761 	sc->msk_res_spec = msk_res_spec_mem;
1762 #endif
1763 	sc->msk_irq_spec = msk_irq_spec_legacy;
1764 	error = bus_alloc_resources(dev, sc->msk_res_spec, sc->msk_res);
1765 	if (error) {
1766 		if (sc->msk_res_spec == msk_res_spec_mem)
1767 			sc->msk_res_spec = msk_res_spec_io;
1768 		else
1769 			sc->msk_res_spec = msk_res_spec_mem;
1770 		error = bus_alloc_resources(dev, sc->msk_res_spec, sc->msk_res);
1771 		if (error) {
1772 			device_printf(dev, "couldn't allocate %s resources\n",
1773 			    sc->msk_res_spec == msk_res_spec_mem ? "memory" :
1774 			    "I/O");
1775 			mtx_destroy(&sc->msk_mtx);
1776 			return (ENXIO);
1777 		}
1778 	}
1779 
1780 	/* Enable all clocks before accessing any registers. */
1781 	CSR_PCI_WRITE_4(sc, PCI_OUR_REG_3, 0);
1782 
1783 	CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR);
1784 	sc->msk_hw_id = CSR_READ_1(sc, B2_CHIP_ID);
1785 	sc->msk_hw_rev = (CSR_READ_1(sc, B2_MAC_CFG) >> 4) & 0x0f;
1786 	/* Bail out if chip is not recognized. */
1787 	if (sc->msk_hw_id < CHIP_ID_YUKON_XL ||
1788 	    sc->msk_hw_id > CHIP_ID_YUKON_OPT ||
1789 	    sc->msk_hw_id == CHIP_ID_YUKON_UNKNOWN) {
1790 		device_printf(dev, "unknown device: id=0x%02x, rev=0x%02x\n",
1791 		    sc->msk_hw_id, sc->msk_hw_rev);
1792 		mtx_destroy(&sc->msk_mtx);
1793 		return (ENXIO);
1794 	}
1795 
1796 	SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
1797 	    SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
1798 	    OID_AUTO, "process_limit", CTLTYPE_INT | CTLFLAG_RW,
1799 	    &sc->msk_process_limit, 0, sysctl_hw_msk_proc_limit, "I",
1800 	    "max number of Rx events to process");
1801 
1802 	sc->msk_process_limit = MSK_PROC_DEFAULT;
1803 	error = resource_int_value(device_get_name(dev), device_get_unit(dev),
1804 	    "process_limit", &sc->msk_process_limit);
1805 	if (error == 0) {
1806 		if (sc->msk_process_limit < MSK_PROC_MIN ||
1807 		    sc->msk_process_limit > MSK_PROC_MAX) {
1808 			device_printf(dev, "process_limit value out of range; "
1809 			    "using default: %d\n", MSK_PROC_DEFAULT);
1810 			sc->msk_process_limit = MSK_PROC_DEFAULT;
1811 		}
1812 	}
1813 
1814 	sc->msk_int_holdoff = MSK_INT_HOLDOFF_DEFAULT;
1815 	SYSCTL_ADD_INT(device_get_sysctl_ctx(dev),
1816 	    SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
1817 	    "int_holdoff", CTLFLAG_RW, &sc->msk_int_holdoff, 0,
1818 	    "Maximum number of time to delay interrupts");
1819 	resource_int_value(device_get_name(dev), device_get_unit(dev),
1820 	    "int_holdoff", &sc->msk_int_holdoff);
1821 
1822 	sc->msk_pmd = CSR_READ_1(sc, B2_PMD_TYP);
1823 	/* Check number of MACs. */
1824 	sc->msk_num_port = 1;
1825 	if ((CSR_READ_1(sc, B2_Y2_HW_RES) & CFG_DUAL_MAC_MSK) ==
1826 	    CFG_DUAL_MAC_MSK) {
1827 		if (!(CSR_READ_1(sc, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
1828 			sc->msk_num_port++;
1829 	}
1830 
1831 	/* Check bus type. */
1832 	if (pci_find_cap(sc->msk_dev, PCIY_EXPRESS, &reg) == 0) {
1833 		sc->msk_bustype = MSK_PEX_BUS;
1834 		sc->msk_expcap = reg;
1835 	} else if (pci_find_cap(sc->msk_dev, PCIY_PCIX, &reg) == 0) {
1836 		sc->msk_bustype = MSK_PCIX_BUS;
1837 		sc->msk_pcixcap = reg;
1838 	} else
1839 		sc->msk_bustype = MSK_PCI_BUS;
1840 
1841 	switch (sc->msk_hw_id) {
1842 	case CHIP_ID_YUKON_EC:
1843 		sc->msk_clock = 125;	/* 125 MHz */
1844 		sc->msk_pflags |= MSK_FLAG_JUMBO;
1845 		break;
1846 	case CHIP_ID_YUKON_EC_U:
1847 		sc->msk_clock = 125;	/* 125 MHz */
1848 		sc->msk_pflags |= MSK_FLAG_JUMBO | MSK_FLAG_JUMBO_NOCSUM;
1849 		break;
1850 	case CHIP_ID_YUKON_EX:
1851 		sc->msk_clock = 125;	/* 125 MHz */
1852 		sc->msk_pflags |= MSK_FLAG_JUMBO | MSK_FLAG_DESCV2 |
1853 		    MSK_FLAG_AUTOTX_CSUM;
1854 		/*
1855 		 * Yukon Extreme seems to have silicon bug for
1856 		 * automatic Tx checksum calculation capability.
1857 		 */
1858 		if (sc->msk_hw_rev == CHIP_REV_YU_EX_B0)
1859 			sc->msk_pflags &= ~MSK_FLAG_AUTOTX_CSUM;
1860 		/*
1861 		 * Yukon Extreme A0 could not use store-and-forward
1862 		 * for jumbo frames, so disable Tx checksum
1863 		 * offloading for jumbo frames.
1864 		 */
1865 		if (sc->msk_hw_rev == CHIP_REV_YU_EX_A0)
1866 			sc->msk_pflags |= MSK_FLAG_JUMBO_NOCSUM;
1867 		break;
1868 	case CHIP_ID_YUKON_FE:
1869 		sc->msk_clock = 100;	/* 100 MHz */
1870 		sc->msk_pflags |= MSK_FLAG_FASTETHER;
1871 		break;
1872 	case CHIP_ID_YUKON_FE_P:
1873 		sc->msk_clock = 50;	/* 50 MHz */
1874 		sc->msk_pflags |= MSK_FLAG_FASTETHER | MSK_FLAG_DESCV2 |
1875 		    MSK_FLAG_AUTOTX_CSUM;
1876 		if (sc->msk_hw_rev == CHIP_REV_YU_FE_P_A0) {
1877 			/*
1878 			 * XXX
1879 			 * FE+ A0 has status LE writeback bug so msk(4)
1880 			 * does not rely on status word of received frame
1881 			 * in msk_rxeof() which in turn disables all
1882 			 * hardware assistance bits reported by the status
1883 			 * word as well as validity of the received frame.
1884 			 * Just pass received frames to upper stack with
1885 			 * minimal test and let upper stack handle them.
1886 			 */
1887 			sc->msk_pflags |= MSK_FLAG_NOHWVLAN |
1888 			    MSK_FLAG_NORXCHK | MSK_FLAG_NORX_CSUM;
1889 		}
1890 		break;
1891 	case CHIP_ID_YUKON_XL:
1892 		sc->msk_clock = 156;	/* 156 MHz */
1893 		sc->msk_pflags |= MSK_FLAG_JUMBO;
1894 		break;
1895 	case CHIP_ID_YUKON_SUPR:
1896 		sc->msk_clock = 125;	/* 125 MHz */
1897 		sc->msk_pflags |= MSK_FLAG_JUMBO | MSK_FLAG_DESCV2 |
1898 		    MSK_FLAG_AUTOTX_CSUM;
1899 		break;
1900 	case CHIP_ID_YUKON_UL_2:
1901 		sc->msk_clock = 125;	/* 125 MHz */
1902 		sc->msk_pflags |= MSK_FLAG_JUMBO;
1903 		break;
1904 	case CHIP_ID_YUKON_OPT:
1905 		sc->msk_clock = 125;	/* 125 MHz */
1906 		sc->msk_pflags |= MSK_FLAG_JUMBO | MSK_FLAG_DESCV2;
1907 		break;
1908 	default:
1909 		sc->msk_clock = 156;	/* 156 MHz */
1910 		break;
1911 	}
1912 
1913 	/* Allocate IRQ resources. */
1914 	msic = pci_msi_count(dev);
1915 	if (bootverbose)
1916 		device_printf(dev, "MSI count : %d\n", msic);
1917 	if (legacy_intr != 0)
1918 		msi_disable = 1;
1919 	if (msi_disable == 0 && msic > 0) {
1920 		msir = 1;
1921 		if (pci_alloc_msi(dev, &msir) == 0) {
1922 			if (msir == 1) {
1923 				sc->msk_pflags |= MSK_FLAG_MSI;
1924 				sc->msk_irq_spec = msk_irq_spec_msi;
1925 			} else
1926 				pci_release_msi(dev);
1927 		}
1928 	}
1929 
1930 	error = bus_alloc_resources(dev, sc->msk_irq_spec, sc->msk_irq);
1931 	if (error) {
1932 		device_printf(dev, "couldn't allocate IRQ resources\n");
1933 		goto fail;
1934 	}
1935 
1936 	if ((error = msk_status_dma_alloc(sc)) != 0)
1937 		goto fail;
1938 
1939 	/* Set base interrupt mask. */
1940 	sc->msk_intrmask = Y2_IS_HW_ERR | Y2_IS_STAT_BMU;
1941 	sc->msk_intrhwemask = Y2_IS_TIST_OV | Y2_IS_MST_ERR |
1942 	    Y2_IS_IRQ_STAT | Y2_IS_PCI_EXP | Y2_IS_PCI_NEXP;
1943 
1944 	/* Reset the adapter. */
1945 	mskc_reset(sc);
1946 
1947 	if ((error = mskc_setup_rambuffer(sc)) != 0)
1948 		goto fail;
1949 
1950 	sc->msk_devs[MSK_PORT_A] = device_add_child(dev, "msk", -1);
1951 	if (sc->msk_devs[MSK_PORT_A] == NULL) {
1952 		device_printf(dev, "failed to add child for PORT_A\n");
1953 		error = ENXIO;
1954 		goto fail;
1955 	}
1956 	mmd = malloc(sizeof(struct msk_mii_data), M_DEVBUF, M_WAITOK | M_ZERO);
1957 	if (mmd == NULL) {
1958 		device_printf(dev, "failed to allocate memory for "
1959 		    "ivars of PORT_A\n");
1960 		error = ENXIO;
1961 		goto fail;
1962 	}
1963 	mmd->port = MSK_PORT_A;
1964 	mmd->pmd = sc->msk_pmd;
1965 	mmd->mii_flags |= MIIF_DOPAUSE;
1966 	if (sc->msk_pmd == 'L' || sc->msk_pmd == 'S')
1967 		mmd->mii_flags |= MIIF_HAVEFIBER;
1968 	if (sc->msk_pmd == 'P')
1969 		mmd->mii_flags |= MIIF_HAVEFIBER | MIIF_MACPRIV0;
1970 	device_set_ivars(sc->msk_devs[MSK_PORT_A], mmd);
1971 
1972 	if (sc->msk_num_port > 1) {
1973 		sc->msk_devs[MSK_PORT_B] = device_add_child(dev, "msk", -1);
1974 		if (sc->msk_devs[MSK_PORT_B] == NULL) {
1975 			device_printf(dev, "failed to add child for PORT_B\n");
1976 			error = ENXIO;
1977 			goto fail;
1978 		}
1979 		mmd = malloc(sizeof(struct msk_mii_data), M_DEVBUF, M_WAITOK |
1980 		    M_ZERO);
1981 		if (mmd == NULL) {
1982 			device_printf(dev, "failed to allocate memory for "
1983 			    "ivars of PORT_B\n");
1984 			error = ENXIO;
1985 			goto fail;
1986 		}
1987 		mmd->port = MSK_PORT_B;
1988 		mmd->pmd = sc->msk_pmd;
1989 		if (sc->msk_pmd == 'L' || sc->msk_pmd == 'S')
1990 			mmd->mii_flags |= MIIF_HAVEFIBER;
1991 		if (sc->msk_pmd == 'P')
1992 			mmd->mii_flags |= MIIF_HAVEFIBER | MIIF_MACPRIV0;
1993 		device_set_ivars(sc->msk_devs[MSK_PORT_B], mmd);
1994 	}
1995 
1996 	error = bus_generic_attach(dev);
1997 	if (error) {
1998 		device_printf(dev, "failed to attach port(s)\n");
1999 		goto fail;
2000 	}
2001 
2002 	/* Hook interrupt last to avoid having to lock softc. */
2003 	error = bus_setup_intr(dev, sc->msk_irq[0], INTR_TYPE_NET |
2004 	    INTR_MPSAFE, NULL, msk_intr, sc, &sc->msk_intrhand);
2005 	if (error != 0) {
2006 		device_printf(dev, "couldn't set up interrupt handler\n");
2007 		goto fail;
2008 	}
2009 fail:
2010 	if (error != 0)
2011 		mskc_detach(dev);
2012 
2013 	return (error);
2014 }
2015 
2016 /*
2017  * Shutdown hardware and free up resources. This can be called any
2018  * time after the mutex has been initialized. It is called in both
2019  * the error case in attach and the normal detach case so it needs
2020  * to be careful about only freeing resources that have actually been
2021  * allocated.
2022  */
2023 static int
2024 msk_detach(device_t dev)
2025 {
2026 	struct msk_softc *sc;
2027 	struct msk_if_softc *sc_if;
2028 	struct ifnet *ifp;
2029 
2030 	sc_if = device_get_softc(dev);
2031 	KASSERT(mtx_initialized(&sc_if->msk_softc->msk_mtx),
2032 	    ("msk mutex not initialized in msk_detach"));
2033 	MSK_IF_LOCK(sc_if);
2034 
2035 	ifp = sc_if->msk_ifp;
2036 	if (device_is_attached(dev)) {
2037 		/* XXX */
2038 		sc_if->msk_flags |= MSK_FLAG_DETACH;
2039 		msk_stop(sc_if);
2040 		/* Can't hold locks while calling detach. */
2041 		MSK_IF_UNLOCK(sc_if);
2042 		callout_drain(&sc_if->msk_tick_ch);
2043 		if (ifp)
2044 			ether_ifdetach(ifp);
2045 		MSK_IF_LOCK(sc_if);
2046 	}
2047 
2048 	/*
2049 	 * We're generally called from mskc_detach() which is using
2050 	 * device_delete_child() to get to here. It's already trashed
2051 	 * miibus for us, so don't do it here or we'll panic.
2052 	 *
2053 	 * if (sc_if->msk_miibus != NULL) {
2054 	 * 	device_delete_child(dev, sc_if->msk_miibus);
2055 	 * 	sc_if->msk_miibus = NULL;
2056 	 * }
2057 	 */
2058 
2059 	msk_rx_dma_jfree(sc_if);
2060 	msk_txrx_dma_free(sc_if);
2061 	bus_generic_detach(dev);
2062 
2063 	if (ifp)
2064 		if_free(ifp);
2065 	sc = sc_if->msk_softc;
2066 	sc->msk_if[sc_if->msk_port] = NULL;
2067 	MSK_IF_UNLOCK(sc_if);
2068 
2069 	return (0);
2070 }
2071 
2072 static int
2073 mskc_detach(device_t dev)
2074 {
2075 	struct msk_softc *sc;
2076 
2077 	sc = device_get_softc(dev);
2078 	KASSERT(mtx_initialized(&sc->msk_mtx), ("msk mutex not initialized"));
2079 
2080 	if (device_is_alive(dev)) {
2081 		if (sc->msk_devs[MSK_PORT_A] != NULL) {
2082 			free(device_get_ivars(sc->msk_devs[MSK_PORT_A]),
2083 			    M_DEVBUF);
2084 			device_delete_child(dev, sc->msk_devs[MSK_PORT_A]);
2085 		}
2086 		if (sc->msk_devs[MSK_PORT_B] != NULL) {
2087 			free(device_get_ivars(sc->msk_devs[MSK_PORT_B]),
2088 			    M_DEVBUF);
2089 			device_delete_child(dev, sc->msk_devs[MSK_PORT_B]);
2090 		}
2091 		bus_generic_detach(dev);
2092 	}
2093 
2094 	/* Disable all interrupts. */
2095 	CSR_WRITE_4(sc, B0_IMSK, 0);
2096 	CSR_READ_4(sc, B0_IMSK);
2097 	CSR_WRITE_4(sc, B0_HWE_IMSK, 0);
2098 	CSR_READ_4(sc, B0_HWE_IMSK);
2099 
2100 	/* LED Off. */
2101 	CSR_WRITE_2(sc, B0_CTST, Y2_LED_STAT_OFF);
2102 
2103 	/* Put hardware reset. */
2104 	CSR_WRITE_2(sc, B0_CTST, CS_RST_SET);
2105 
2106 	msk_status_dma_free(sc);
2107 
2108 	if (sc->msk_intrhand) {
2109 		bus_teardown_intr(dev, sc->msk_irq[0], sc->msk_intrhand);
2110 		sc->msk_intrhand = NULL;
2111 	}
2112 	bus_release_resources(dev, sc->msk_irq_spec, sc->msk_irq);
2113 	if ((sc->msk_pflags & MSK_FLAG_MSI) != 0)
2114 		pci_release_msi(dev);
2115 	bus_release_resources(dev, sc->msk_res_spec, sc->msk_res);
2116 	mtx_destroy(&sc->msk_mtx);
2117 
2118 	return (0);
2119 }
2120 
2121 struct msk_dmamap_arg {
2122 	bus_addr_t	msk_busaddr;
2123 };
2124 
2125 static void
2126 msk_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
2127 {
2128 	struct msk_dmamap_arg *ctx;
2129 
2130 	if (error != 0)
2131 		return;
2132 	ctx = arg;
2133 	ctx->msk_busaddr = segs[0].ds_addr;
2134 }
2135 
2136 /* Create status DMA region. */
2137 static int
2138 msk_status_dma_alloc(struct msk_softc *sc)
2139 {
2140 	struct msk_dmamap_arg ctx;
2141 	bus_size_t stat_sz;
2142 	int count, error;
2143 
2144 	/*
2145 	 * It seems controller requires number of status LE entries
2146 	 * is power of 2 and the maximum number of status LE entries
2147 	 * is 4096.  For dual-port controllers, the number of status
2148 	 * LE entries should be large enough to hold both port's
2149 	 * status updates.
2150 	 */
2151 	count = 3 * MSK_RX_RING_CNT + MSK_TX_RING_CNT;
2152 	count = imin(4096, roundup2(count, 1024));
2153 	sc->msk_stat_count = count;
2154 	stat_sz = count * sizeof(struct msk_stat_desc);
2155 	error = bus_dma_tag_create(
2156 		    bus_get_dma_tag(sc->msk_dev),	/* parent */
2157 		    MSK_STAT_ALIGN, 0,		/* alignment, boundary */
2158 		    BUS_SPACE_MAXADDR,		/* lowaddr */
2159 		    BUS_SPACE_MAXADDR,		/* highaddr */
2160 		    NULL, NULL,			/* filter, filterarg */
2161 		    stat_sz,			/* maxsize */
2162 		    1,				/* nsegments */
2163 		    stat_sz,			/* maxsegsize */
2164 		    0,				/* flags */
2165 		    NULL, NULL,			/* lockfunc, lockarg */
2166 		    &sc->msk_stat_tag);
2167 	if (error != 0) {
2168 		device_printf(sc->msk_dev,
2169 		    "failed to create status DMA tag\n");
2170 		return (error);
2171 	}
2172 
2173 	/* Allocate DMA'able memory and load the DMA map for status ring. */
2174 	error = bus_dmamem_alloc(sc->msk_stat_tag,
2175 	    (void **)&sc->msk_stat_ring, BUS_DMA_WAITOK | BUS_DMA_COHERENT |
2176 	    BUS_DMA_ZERO, &sc->msk_stat_map);
2177 	if (error != 0) {
2178 		device_printf(sc->msk_dev,
2179 		    "failed to allocate DMA'able memory for status ring\n");
2180 		return (error);
2181 	}
2182 
2183 	ctx.msk_busaddr = 0;
2184 	error = bus_dmamap_load(sc->msk_stat_tag, sc->msk_stat_map,
2185 	    sc->msk_stat_ring, stat_sz, msk_dmamap_cb, &ctx, BUS_DMA_NOWAIT);
2186 	if (error != 0) {
2187 		device_printf(sc->msk_dev,
2188 		    "failed to load DMA'able memory for status ring\n");
2189 		return (error);
2190 	}
2191 	sc->msk_stat_ring_paddr = ctx.msk_busaddr;
2192 
2193 	return (0);
2194 }
2195 
2196 static void
2197 msk_status_dma_free(struct msk_softc *sc)
2198 {
2199 
2200 	/* Destroy status block. */
2201 	if (sc->msk_stat_tag) {
2202 		if (sc->msk_stat_map) {
2203 			bus_dmamap_unload(sc->msk_stat_tag, sc->msk_stat_map);
2204 			if (sc->msk_stat_ring) {
2205 				bus_dmamem_free(sc->msk_stat_tag,
2206 				    sc->msk_stat_ring, sc->msk_stat_map);
2207 				sc->msk_stat_ring = NULL;
2208 			}
2209 			sc->msk_stat_map = NULL;
2210 		}
2211 		bus_dma_tag_destroy(sc->msk_stat_tag);
2212 		sc->msk_stat_tag = NULL;
2213 	}
2214 }
2215 
2216 static int
2217 msk_txrx_dma_alloc(struct msk_if_softc *sc_if)
2218 {
2219 	struct msk_dmamap_arg ctx;
2220 	struct msk_txdesc *txd;
2221 	struct msk_rxdesc *rxd;
2222 	bus_size_t rxalign;
2223 	int error, i;
2224 
2225 	/* Create parent DMA tag. */
2226 	error = bus_dma_tag_create(
2227 		    bus_get_dma_tag(sc_if->msk_if_dev),	/* parent */
2228 		    1, 0,			/* alignment, boundary */
2229 		    BUS_SPACE_MAXADDR,		/* lowaddr */
2230 		    BUS_SPACE_MAXADDR,		/* highaddr */
2231 		    NULL, NULL,			/* filter, filterarg */
2232 		    BUS_SPACE_MAXSIZE_32BIT,	/* maxsize */
2233 		    0,				/* nsegments */
2234 		    BUS_SPACE_MAXSIZE_32BIT,	/* maxsegsize */
2235 		    0,				/* flags */
2236 		    NULL, NULL,			/* lockfunc, lockarg */
2237 		    &sc_if->msk_cdata.msk_parent_tag);
2238 	if (error != 0) {
2239 		device_printf(sc_if->msk_if_dev,
2240 		    "failed to create parent DMA tag\n");
2241 		goto fail;
2242 	}
2243 	/* Create tag for Tx ring. */
2244 	error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */
2245 		    MSK_RING_ALIGN, 0,		/* alignment, boundary */
2246 		    BUS_SPACE_MAXADDR,		/* lowaddr */
2247 		    BUS_SPACE_MAXADDR,		/* highaddr */
2248 		    NULL, NULL,			/* filter, filterarg */
2249 		    MSK_TX_RING_SZ,		/* maxsize */
2250 		    1,				/* nsegments */
2251 		    MSK_TX_RING_SZ,		/* maxsegsize */
2252 		    0,				/* flags */
2253 		    NULL, NULL,			/* lockfunc, lockarg */
2254 		    &sc_if->msk_cdata.msk_tx_ring_tag);
2255 	if (error != 0) {
2256 		device_printf(sc_if->msk_if_dev,
2257 		    "failed to create Tx ring DMA tag\n");
2258 		goto fail;
2259 	}
2260 
2261 	/* Create tag for Rx ring. */
2262 	error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */
2263 		    MSK_RING_ALIGN, 0,		/* alignment, boundary */
2264 		    BUS_SPACE_MAXADDR,		/* lowaddr */
2265 		    BUS_SPACE_MAXADDR,		/* highaddr */
2266 		    NULL, NULL,			/* filter, filterarg */
2267 		    MSK_RX_RING_SZ,		/* maxsize */
2268 		    1,				/* nsegments */
2269 		    MSK_RX_RING_SZ,		/* maxsegsize */
2270 		    0,				/* flags */
2271 		    NULL, NULL,			/* lockfunc, lockarg */
2272 		    &sc_if->msk_cdata.msk_rx_ring_tag);
2273 	if (error != 0) {
2274 		device_printf(sc_if->msk_if_dev,
2275 		    "failed to create Rx ring DMA tag\n");
2276 		goto fail;
2277 	}
2278 
2279 	/* Create tag for Tx buffers. */
2280 	error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */
2281 		    1, 0,			/* alignment, boundary */
2282 		    BUS_SPACE_MAXADDR,		/* lowaddr */
2283 		    BUS_SPACE_MAXADDR,		/* highaddr */
2284 		    NULL, NULL,			/* filter, filterarg */
2285 		    MSK_TSO_MAXSIZE,		/* maxsize */
2286 		    MSK_MAXTXSEGS,		/* nsegments */
2287 		    MSK_TSO_MAXSGSIZE,		/* maxsegsize */
2288 		    0,				/* flags */
2289 		    NULL, NULL,			/* lockfunc, lockarg */
2290 		    &sc_if->msk_cdata.msk_tx_tag);
2291 	if (error != 0) {
2292 		device_printf(sc_if->msk_if_dev,
2293 		    "failed to create Tx DMA tag\n");
2294 		goto fail;
2295 	}
2296 
2297 	rxalign = 1;
2298 	/*
2299 	 * Workaround hardware hang which seems to happen when Rx buffer
2300 	 * is not aligned on multiple of FIFO word(8 bytes).
2301 	 */
2302 	if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) != 0)
2303 		rxalign = MSK_RX_BUF_ALIGN;
2304 	/* Create tag for Rx buffers. */
2305 	error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */
2306 		    rxalign, 0,			/* alignment, boundary */
2307 		    BUS_SPACE_MAXADDR,		/* lowaddr */
2308 		    BUS_SPACE_MAXADDR,		/* highaddr */
2309 		    NULL, NULL,			/* filter, filterarg */
2310 		    MCLBYTES,			/* maxsize */
2311 		    1,				/* nsegments */
2312 		    MCLBYTES,			/* maxsegsize */
2313 		    0,				/* flags */
2314 		    NULL, NULL,			/* lockfunc, lockarg */
2315 		    &sc_if->msk_cdata.msk_rx_tag);
2316 	if (error != 0) {
2317 		device_printf(sc_if->msk_if_dev,
2318 		    "failed to create Rx DMA tag\n");
2319 		goto fail;
2320 	}
2321 
2322 	/* Allocate DMA'able memory and load the DMA map for Tx ring. */
2323 	error = bus_dmamem_alloc(sc_if->msk_cdata.msk_tx_ring_tag,
2324 	    (void **)&sc_if->msk_rdata.msk_tx_ring, BUS_DMA_WAITOK |
2325 	    BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc_if->msk_cdata.msk_tx_ring_map);
2326 	if (error != 0) {
2327 		device_printf(sc_if->msk_if_dev,
2328 		    "failed to allocate DMA'able memory for Tx ring\n");
2329 		goto fail;
2330 	}
2331 
2332 	ctx.msk_busaddr = 0;
2333 	error = bus_dmamap_load(sc_if->msk_cdata.msk_tx_ring_tag,
2334 	    sc_if->msk_cdata.msk_tx_ring_map, sc_if->msk_rdata.msk_tx_ring,
2335 	    MSK_TX_RING_SZ, msk_dmamap_cb, &ctx, BUS_DMA_NOWAIT);
2336 	if (error != 0) {
2337 		device_printf(sc_if->msk_if_dev,
2338 		    "failed to load DMA'able memory for Tx ring\n");
2339 		goto fail;
2340 	}
2341 	sc_if->msk_rdata.msk_tx_ring_paddr = ctx.msk_busaddr;
2342 
2343 	/* Allocate DMA'able memory and load the DMA map for Rx ring. */
2344 	error = bus_dmamem_alloc(sc_if->msk_cdata.msk_rx_ring_tag,
2345 	    (void **)&sc_if->msk_rdata.msk_rx_ring, BUS_DMA_WAITOK |
2346 	    BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc_if->msk_cdata.msk_rx_ring_map);
2347 	if (error != 0) {
2348 		device_printf(sc_if->msk_if_dev,
2349 		    "failed to allocate DMA'able memory for Rx ring\n");
2350 		goto fail;
2351 	}
2352 
2353 	ctx.msk_busaddr = 0;
2354 	error = bus_dmamap_load(sc_if->msk_cdata.msk_rx_ring_tag,
2355 	    sc_if->msk_cdata.msk_rx_ring_map, sc_if->msk_rdata.msk_rx_ring,
2356 	    MSK_RX_RING_SZ, msk_dmamap_cb, &ctx, BUS_DMA_NOWAIT);
2357 	if (error != 0) {
2358 		device_printf(sc_if->msk_if_dev,
2359 		    "failed to load DMA'able memory for Rx ring\n");
2360 		goto fail;
2361 	}
2362 	sc_if->msk_rdata.msk_rx_ring_paddr = ctx.msk_busaddr;
2363 
2364 	/* Create DMA maps for Tx buffers. */
2365 	for (i = 0; i < MSK_TX_RING_CNT; i++) {
2366 		txd = &sc_if->msk_cdata.msk_txdesc[i];
2367 		txd->tx_m = NULL;
2368 		txd->tx_dmamap = NULL;
2369 		error = bus_dmamap_create(sc_if->msk_cdata.msk_tx_tag, 0,
2370 		    &txd->tx_dmamap);
2371 		if (error != 0) {
2372 			device_printf(sc_if->msk_if_dev,
2373 			    "failed to create Tx dmamap\n");
2374 			goto fail;
2375 		}
2376 	}
2377 	/* Create DMA maps for Rx buffers. */
2378 	if ((error = bus_dmamap_create(sc_if->msk_cdata.msk_rx_tag, 0,
2379 	    &sc_if->msk_cdata.msk_rx_sparemap)) != 0) {
2380 		device_printf(sc_if->msk_if_dev,
2381 		    "failed to create spare Rx dmamap\n");
2382 		goto fail;
2383 	}
2384 	for (i = 0; i < MSK_RX_RING_CNT; i++) {
2385 		rxd = &sc_if->msk_cdata.msk_rxdesc[i];
2386 		rxd->rx_m = NULL;
2387 		rxd->rx_dmamap = NULL;
2388 		error = bus_dmamap_create(sc_if->msk_cdata.msk_rx_tag, 0,
2389 		    &rxd->rx_dmamap);
2390 		if (error != 0) {
2391 			device_printf(sc_if->msk_if_dev,
2392 			    "failed to create Rx dmamap\n");
2393 			goto fail;
2394 		}
2395 	}
2396 
2397 fail:
2398 	return (error);
2399 }
2400 
2401 static int
2402 msk_rx_dma_jalloc(struct msk_if_softc *sc_if)
2403 {
2404 	struct msk_dmamap_arg ctx;
2405 	struct msk_rxdesc *jrxd;
2406 	bus_size_t rxalign;
2407 	int error, i;
2408 
2409 	if (jumbo_disable != 0 || (sc_if->msk_flags & MSK_FLAG_JUMBO) == 0) {
2410 		sc_if->msk_flags &= ~MSK_FLAG_JUMBO;
2411 		device_printf(sc_if->msk_if_dev,
2412 		    "disabling jumbo frame support\n");
2413 		return (0);
2414 	}
2415 	/* Create tag for jumbo Rx ring. */
2416 	error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */
2417 		    MSK_RING_ALIGN, 0,		/* alignment, boundary */
2418 		    BUS_SPACE_MAXADDR,		/* lowaddr */
2419 		    BUS_SPACE_MAXADDR,		/* highaddr */
2420 		    NULL, NULL,			/* filter, filterarg */
2421 		    MSK_JUMBO_RX_RING_SZ,	/* maxsize */
2422 		    1,				/* nsegments */
2423 		    MSK_JUMBO_RX_RING_SZ,	/* maxsegsize */
2424 		    0,				/* flags */
2425 		    NULL, NULL,			/* lockfunc, lockarg */
2426 		    &sc_if->msk_cdata.msk_jumbo_rx_ring_tag);
2427 	if (error != 0) {
2428 		device_printf(sc_if->msk_if_dev,
2429 		    "failed to create jumbo Rx ring DMA tag\n");
2430 		goto jumbo_fail;
2431 	}
2432 
2433 	rxalign = 1;
2434 	/*
2435 	 * Workaround hardware hang which seems to happen when Rx buffer
2436 	 * is not aligned on multiple of FIFO word(8 bytes).
2437 	 */
2438 	if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) != 0)
2439 		rxalign = MSK_RX_BUF_ALIGN;
2440 	/* Create tag for jumbo Rx buffers. */
2441 	error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */
2442 		    rxalign, 0,			/* alignment, boundary */
2443 		    BUS_SPACE_MAXADDR,		/* lowaddr */
2444 		    BUS_SPACE_MAXADDR,		/* highaddr */
2445 		    NULL, NULL,			/* filter, filterarg */
2446 		    MJUM9BYTES,			/* maxsize */
2447 		    1,				/* nsegments */
2448 		    MJUM9BYTES,			/* maxsegsize */
2449 		    0,				/* flags */
2450 		    NULL, NULL,			/* lockfunc, lockarg */
2451 		    &sc_if->msk_cdata.msk_jumbo_rx_tag);
2452 	if (error != 0) {
2453 		device_printf(sc_if->msk_if_dev,
2454 		    "failed to create jumbo Rx DMA tag\n");
2455 		goto jumbo_fail;
2456 	}
2457 
2458 	/* Allocate DMA'able memory and load the DMA map for jumbo Rx ring. */
2459 	error = bus_dmamem_alloc(sc_if->msk_cdata.msk_jumbo_rx_ring_tag,
2460 	    (void **)&sc_if->msk_rdata.msk_jumbo_rx_ring,
2461 	    BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO,
2462 	    &sc_if->msk_cdata.msk_jumbo_rx_ring_map);
2463 	if (error != 0) {
2464 		device_printf(sc_if->msk_if_dev,
2465 		    "failed to allocate DMA'able memory for jumbo Rx ring\n");
2466 		goto jumbo_fail;
2467 	}
2468 
2469 	ctx.msk_busaddr = 0;
2470 	error = bus_dmamap_load(sc_if->msk_cdata.msk_jumbo_rx_ring_tag,
2471 	    sc_if->msk_cdata.msk_jumbo_rx_ring_map,
2472 	    sc_if->msk_rdata.msk_jumbo_rx_ring, MSK_JUMBO_RX_RING_SZ,
2473 	    msk_dmamap_cb, &ctx, BUS_DMA_NOWAIT);
2474 	if (error != 0) {
2475 		device_printf(sc_if->msk_if_dev,
2476 		    "failed to load DMA'able memory for jumbo Rx ring\n");
2477 		goto jumbo_fail;
2478 	}
2479 	sc_if->msk_rdata.msk_jumbo_rx_ring_paddr = ctx.msk_busaddr;
2480 
2481 	/* Create DMA maps for jumbo Rx buffers. */
2482 	if ((error = bus_dmamap_create(sc_if->msk_cdata.msk_jumbo_rx_tag, 0,
2483 	    &sc_if->msk_cdata.msk_jumbo_rx_sparemap)) != 0) {
2484 		device_printf(sc_if->msk_if_dev,
2485 		    "failed to create spare jumbo Rx dmamap\n");
2486 		goto jumbo_fail;
2487 	}
2488 	for (i = 0; i < MSK_JUMBO_RX_RING_CNT; i++) {
2489 		jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[i];
2490 		jrxd->rx_m = NULL;
2491 		jrxd->rx_dmamap = NULL;
2492 		error = bus_dmamap_create(sc_if->msk_cdata.msk_jumbo_rx_tag, 0,
2493 		    &jrxd->rx_dmamap);
2494 		if (error != 0) {
2495 			device_printf(sc_if->msk_if_dev,
2496 			    "failed to create jumbo Rx dmamap\n");
2497 			goto jumbo_fail;
2498 		}
2499 	}
2500 
2501 	return (0);
2502 
2503 jumbo_fail:
2504 	msk_rx_dma_jfree(sc_if);
2505 	device_printf(sc_if->msk_if_dev, "disabling jumbo frame support "
2506 	    "due to resource shortage\n");
2507 	sc_if->msk_flags &= ~MSK_FLAG_JUMBO;
2508 	return (error);
2509 }
2510 
2511 static void
2512 msk_txrx_dma_free(struct msk_if_softc *sc_if)
2513 {
2514 	struct msk_txdesc *txd;
2515 	struct msk_rxdesc *rxd;
2516 	int i;
2517 
2518 	/* Tx ring. */
2519 	if (sc_if->msk_cdata.msk_tx_ring_tag) {
2520 		if (sc_if->msk_cdata.msk_tx_ring_map)
2521 			bus_dmamap_unload(sc_if->msk_cdata.msk_tx_ring_tag,
2522 			    sc_if->msk_cdata.msk_tx_ring_map);
2523 		if (sc_if->msk_cdata.msk_tx_ring_map &&
2524 		    sc_if->msk_rdata.msk_tx_ring)
2525 			bus_dmamem_free(sc_if->msk_cdata.msk_tx_ring_tag,
2526 			    sc_if->msk_rdata.msk_tx_ring,
2527 			    sc_if->msk_cdata.msk_tx_ring_map);
2528 		sc_if->msk_rdata.msk_tx_ring = NULL;
2529 		sc_if->msk_cdata.msk_tx_ring_map = NULL;
2530 		bus_dma_tag_destroy(sc_if->msk_cdata.msk_tx_ring_tag);
2531 		sc_if->msk_cdata.msk_tx_ring_tag = NULL;
2532 	}
2533 	/* Rx ring. */
2534 	if (sc_if->msk_cdata.msk_rx_ring_tag) {
2535 		if (sc_if->msk_cdata.msk_rx_ring_map)
2536 			bus_dmamap_unload(sc_if->msk_cdata.msk_rx_ring_tag,
2537 			    sc_if->msk_cdata.msk_rx_ring_map);
2538 		if (sc_if->msk_cdata.msk_rx_ring_map &&
2539 		    sc_if->msk_rdata.msk_rx_ring)
2540 			bus_dmamem_free(sc_if->msk_cdata.msk_rx_ring_tag,
2541 			    sc_if->msk_rdata.msk_rx_ring,
2542 			    sc_if->msk_cdata.msk_rx_ring_map);
2543 		sc_if->msk_rdata.msk_rx_ring = NULL;
2544 		sc_if->msk_cdata.msk_rx_ring_map = NULL;
2545 		bus_dma_tag_destroy(sc_if->msk_cdata.msk_rx_ring_tag);
2546 		sc_if->msk_cdata.msk_rx_ring_tag = NULL;
2547 	}
2548 	/* Tx buffers. */
2549 	if (sc_if->msk_cdata.msk_tx_tag) {
2550 		for (i = 0; i < MSK_TX_RING_CNT; i++) {
2551 			txd = &sc_if->msk_cdata.msk_txdesc[i];
2552 			if (txd->tx_dmamap) {
2553 				bus_dmamap_destroy(sc_if->msk_cdata.msk_tx_tag,
2554 				    txd->tx_dmamap);
2555 				txd->tx_dmamap = NULL;
2556 			}
2557 		}
2558 		bus_dma_tag_destroy(sc_if->msk_cdata.msk_tx_tag);
2559 		sc_if->msk_cdata.msk_tx_tag = NULL;
2560 	}
2561 	/* Rx buffers. */
2562 	if (sc_if->msk_cdata.msk_rx_tag) {
2563 		for (i = 0; i < MSK_RX_RING_CNT; i++) {
2564 			rxd = &sc_if->msk_cdata.msk_rxdesc[i];
2565 			if (rxd->rx_dmamap) {
2566 				bus_dmamap_destroy(sc_if->msk_cdata.msk_rx_tag,
2567 				    rxd->rx_dmamap);
2568 				rxd->rx_dmamap = NULL;
2569 			}
2570 		}
2571 		if (sc_if->msk_cdata.msk_rx_sparemap) {
2572 			bus_dmamap_destroy(sc_if->msk_cdata.msk_rx_tag,
2573 			    sc_if->msk_cdata.msk_rx_sparemap);
2574 			sc_if->msk_cdata.msk_rx_sparemap = 0;
2575 		}
2576 		bus_dma_tag_destroy(sc_if->msk_cdata.msk_rx_tag);
2577 		sc_if->msk_cdata.msk_rx_tag = NULL;
2578 	}
2579 	if (sc_if->msk_cdata.msk_parent_tag) {
2580 		bus_dma_tag_destroy(sc_if->msk_cdata.msk_parent_tag);
2581 		sc_if->msk_cdata.msk_parent_tag = NULL;
2582 	}
2583 }
2584 
2585 static void
2586 msk_rx_dma_jfree(struct msk_if_softc *sc_if)
2587 {
2588 	struct msk_rxdesc *jrxd;
2589 	int i;
2590 
2591 	/* Jumbo Rx ring. */
2592 	if (sc_if->msk_cdata.msk_jumbo_rx_ring_tag) {
2593 		if (sc_if->msk_cdata.msk_jumbo_rx_ring_map)
2594 			bus_dmamap_unload(sc_if->msk_cdata.msk_jumbo_rx_ring_tag,
2595 			    sc_if->msk_cdata.msk_jumbo_rx_ring_map);
2596 		if (sc_if->msk_cdata.msk_jumbo_rx_ring_map &&
2597 		    sc_if->msk_rdata.msk_jumbo_rx_ring)
2598 			bus_dmamem_free(sc_if->msk_cdata.msk_jumbo_rx_ring_tag,
2599 			    sc_if->msk_rdata.msk_jumbo_rx_ring,
2600 			    sc_if->msk_cdata.msk_jumbo_rx_ring_map);
2601 		sc_if->msk_rdata.msk_jumbo_rx_ring = NULL;
2602 		sc_if->msk_cdata.msk_jumbo_rx_ring_map = NULL;
2603 		bus_dma_tag_destroy(sc_if->msk_cdata.msk_jumbo_rx_ring_tag);
2604 		sc_if->msk_cdata.msk_jumbo_rx_ring_tag = NULL;
2605 	}
2606 	/* Jumbo Rx buffers. */
2607 	if (sc_if->msk_cdata.msk_jumbo_rx_tag) {
2608 		for (i = 0; i < MSK_JUMBO_RX_RING_CNT; i++) {
2609 			jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[i];
2610 			if (jrxd->rx_dmamap) {
2611 				bus_dmamap_destroy(
2612 				    sc_if->msk_cdata.msk_jumbo_rx_tag,
2613 				    jrxd->rx_dmamap);
2614 				jrxd->rx_dmamap = NULL;
2615 			}
2616 		}
2617 		if (sc_if->msk_cdata.msk_jumbo_rx_sparemap) {
2618 			bus_dmamap_destroy(sc_if->msk_cdata.msk_jumbo_rx_tag,
2619 			    sc_if->msk_cdata.msk_jumbo_rx_sparemap);
2620 			sc_if->msk_cdata.msk_jumbo_rx_sparemap = 0;
2621 		}
2622 		bus_dma_tag_destroy(sc_if->msk_cdata.msk_jumbo_rx_tag);
2623 		sc_if->msk_cdata.msk_jumbo_rx_tag = NULL;
2624 	}
2625 }
2626 
2627 static int
2628 msk_encap(struct msk_if_softc *sc_if, struct mbuf **m_head)
2629 {
2630 	struct msk_txdesc *txd, *txd_last;
2631 	struct msk_tx_desc *tx_le;
2632 	struct mbuf *m;
2633 	bus_dmamap_t map;
2634 	bus_dma_segment_t txsegs[MSK_MAXTXSEGS];
2635 	uint32_t control, csum, prod, si;
2636 	uint16_t offset, tcp_offset, tso_mtu;
2637 	int error, i, nseg, tso;
2638 
2639 	MSK_IF_LOCK_ASSERT(sc_if);
2640 
2641 	tcp_offset = offset = 0;
2642 	m = *m_head;
2643 	if (((sc_if->msk_flags & MSK_FLAG_AUTOTX_CSUM) == 0 &&
2644 	    (m->m_pkthdr.csum_flags & MSK_CSUM_FEATURES) != 0) ||
2645 	    ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0 &&
2646 	    (m->m_pkthdr.csum_flags & CSUM_TSO) != 0)) {
2647 		/*
2648 		 * Since mbuf has no protocol specific structure information
2649 		 * in it we have to inspect protocol information here to
2650 		 * setup TSO and checksum offload. I don't know why Marvell
2651 		 * made a such decision in chip design because other GigE
2652 		 * hardwares normally takes care of all these chores in
2653 		 * hardware. However, TSO performance of Yukon II is very
2654 		 * good such that it's worth to implement it.
2655 		 */
2656 		struct ether_header *eh;
2657 		struct ip *ip;
2658 		struct tcphdr *tcp;
2659 
2660 		if (M_WRITABLE(m) == 0) {
2661 			/* Get a writable copy. */
2662 			m = m_dup(*m_head, M_NOWAIT);
2663 			m_freem(*m_head);
2664 			if (m == NULL) {
2665 				*m_head = NULL;
2666 				return (ENOBUFS);
2667 			}
2668 			*m_head = m;
2669 		}
2670 
2671 		offset = sizeof(struct ether_header);
2672 		m = m_pullup(m, offset);
2673 		if (m == NULL) {
2674 			*m_head = NULL;
2675 			return (ENOBUFS);
2676 		}
2677 		eh = mtod(m, struct ether_header *);
2678 		/* Check if hardware VLAN insertion is off. */
2679 		if (eh->ether_type == htons(ETHERTYPE_VLAN)) {
2680 			offset = sizeof(struct ether_vlan_header);
2681 			m = m_pullup(m, offset);
2682 			if (m == NULL) {
2683 				*m_head = NULL;
2684 				return (ENOBUFS);
2685 			}
2686 		}
2687 		m = m_pullup(m, offset + sizeof(struct ip));
2688 		if (m == NULL) {
2689 			*m_head = NULL;
2690 			return (ENOBUFS);
2691 		}
2692 		ip = (struct ip *)(mtod(m, char *) + offset);
2693 		offset += (ip->ip_hl << 2);
2694 		tcp_offset = offset;
2695 		if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
2696 			m = m_pullup(m, offset + sizeof(struct tcphdr));
2697 			if (m == NULL) {
2698 				*m_head = NULL;
2699 				return (ENOBUFS);
2700 			}
2701 			tcp = (struct tcphdr *)(mtod(m, char *) + offset);
2702 			offset += (tcp->th_off << 2);
2703 		} else if ((sc_if->msk_flags & MSK_FLAG_AUTOTX_CSUM) == 0 &&
2704 		    (m->m_pkthdr.len < MSK_MIN_FRAMELEN) &&
2705 		    (m->m_pkthdr.csum_flags & CSUM_TCP) != 0) {
2706 			/*
2707 			 * It seems that Yukon II has Tx checksum offload bug
2708 			 * for small TCP packets that's less than 60 bytes in
2709 			 * size (e.g. TCP window probe packet, pure ACK packet).
2710 			 * Common work around like padding with zeros to make
2711 			 * the frame minimum ethernet frame size didn't work at
2712 			 * all.
2713 			 * Instead of disabling checksum offload completely we
2714 			 * resort to S/W checksum routine when we encounter
2715 			 * short TCP frames.
2716 			 * Short UDP packets appear to be handled correctly by
2717 			 * Yukon II. Also I assume this bug does not happen on
2718 			 * controllers that use newer descriptor format or
2719 			 * automatic Tx checksum calculation.
2720 			 */
2721 			m = m_pullup(m, offset + sizeof(struct tcphdr));
2722 			if (m == NULL) {
2723 				*m_head = NULL;
2724 				return (ENOBUFS);
2725 			}
2726 			*(uint16_t *)(m->m_data + offset +
2727 			    m->m_pkthdr.csum_data) = in_cksum_skip(m,
2728 			    m->m_pkthdr.len, offset);
2729 			m->m_pkthdr.csum_flags &= ~CSUM_TCP;
2730 		}
2731 		*m_head = m;
2732 	}
2733 
2734 	prod = sc_if->msk_cdata.msk_tx_prod;
2735 	txd = &sc_if->msk_cdata.msk_txdesc[prod];
2736 	txd_last = txd;
2737 	map = txd->tx_dmamap;
2738 	error = bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_tx_tag, map,
2739 	    *m_head, txsegs, &nseg, BUS_DMA_NOWAIT);
2740 	if (error == EFBIG) {
2741 		m = m_collapse(*m_head, M_NOWAIT, MSK_MAXTXSEGS);
2742 		if (m == NULL) {
2743 			m_freem(*m_head);
2744 			*m_head = NULL;
2745 			return (ENOBUFS);
2746 		}
2747 		*m_head = m;
2748 		error = bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_tx_tag,
2749 		    map, *m_head, txsegs, &nseg, BUS_DMA_NOWAIT);
2750 		if (error != 0) {
2751 			m_freem(*m_head);
2752 			*m_head = NULL;
2753 			return (error);
2754 		}
2755 	} else if (error != 0)
2756 		return (error);
2757 	if (nseg == 0) {
2758 		m_freem(*m_head);
2759 		*m_head = NULL;
2760 		return (EIO);
2761 	}
2762 
2763 	/* Check number of available descriptors. */
2764 	if (sc_if->msk_cdata.msk_tx_cnt + nseg >=
2765 	    (MSK_TX_RING_CNT - MSK_RESERVED_TX_DESC_CNT)) {
2766 		bus_dmamap_unload(sc_if->msk_cdata.msk_tx_tag, map);
2767 		return (ENOBUFS);
2768 	}
2769 
2770 	control = 0;
2771 	tso = 0;
2772 	tx_le = NULL;
2773 
2774 	/* Check TSO support. */
2775 	if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
2776 		if ((sc_if->msk_flags & MSK_FLAG_DESCV2) != 0)
2777 			tso_mtu = m->m_pkthdr.tso_segsz;
2778 		else
2779 			tso_mtu = offset + m->m_pkthdr.tso_segsz;
2780 		if (tso_mtu != sc_if->msk_cdata.msk_tso_mtu) {
2781 			tx_le = &sc_if->msk_rdata.msk_tx_ring[prod];
2782 			tx_le->msk_addr = htole32(tso_mtu);
2783 			if ((sc_if->msk_flags & MSK_FLAG_DESCV2) != 0)
2784 				tx_le->msk_control = htole32(OP_MSS | HW_OWNER);
2785 			else
2786 				tx_le->msk_control =
2787 				    htole32(OP_LRGLEN | HW_OWNER);
2788 			sc_if->msk_cdata.msk_tx_cnt++;
2789 			MSK_INC(prod, MSK_TX_RING_CNT);
2790 			sc_if->msk_cdata.msk_tso_mtu = tso_mtu;
2791 		}
2792 		tso++;
2793 	}
2794 	/* Check if we have a VLAN tag to insert. */
2795 	if ((m->m_flags & M_VLANTAG) != 0) {
2796 		if (tx_le == NULL) {
2797 			tx_le = &sc_if->msk_rdata.msk_tx_ring[prod];
2798 			tx_le->msk_addr = htole32(0);
2799 			tx_le->msk_control = htole32(OP_VLAN | HW_OWNER |
2800 			    htons(m->m_pkthdr.ether_vtag));
2801 			sc_if->msk_cdata.msk_tx_cnt++;
2802 			MSK_INC(prod, MSK_TX_RING_CNT);
2803 		} else {
2804 			tx_le->msk_control |= htole32(OP_VLAN |
2805 			    htons(m->m_pkthdr.ether_vtag));
2806 		}
2807 		control |= INS_VLAN;
2808 	}
2809 	/* Check if we have to handle checksum offload. */
2810 	if (tso == 0 && (m->m_pkthdr.csum_flags & MSK_CSUM_FEATURES) != 0) {
2811 		if ((sc_if->msk_flags & MSK_FLAG_AUTOTX_CSUM) != 0)
2812 			control |= CALSUM;
2813 		else {
2814 			control |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
2815 			if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0)
2816 				control |= UDPTCP;
2817 			/* Checksum write position. */
2818 			csum = (tcp_offset + m->m_pkthdr.csum_data) & 0xffff;
2819 			/* Checksum start position. */
2820 			csum |= (uint32_t)tcp_offset << 16;
2821 			if (csum != sc_if->msk_cdata.msk_last_csum) {
2822 				tx_le = &sc_if->msk_rdata.msk_tx_ring[prod];
2823 				tx_le->msk_addr = htole32(csum);
2824 				tx_le->msk_control = htole32(1 << 16 |
2825 				    (OP_TCPLISW | HW_OWNER));
2826 				sc_if->msk_cdata.msk_tx_cnt++;
2827 				MSK_INC(prod, MSK_TX_RING_CNT);
2828 				sc_if->msk_cdata.msk_last_csum = csum;
2829 			}
2830 		}
2831 	}
2832 
2833 #ifdef MSK_64BIT_DMA
2834 	if (MSK_ADDR_HI(txsegs[0].ds_addr) !=
2835 	    sc_if->msk_cdata.msk_tx_high_addr) {
2836 		sc_if->msk_cdata.msk_tx_high_addr =
2837 		    MSK_ADDR_HI(txsegs[0].ds_addr);
2838 		tx_le = &sc_if->msk_rdata.msk_tx_ring[prod];
2839 		tx_le->msk_addr = htole32(MSK_ADDR_HI(txsegs[0].ds_addr));
2840 		tx_le->msk_control = htole32(OP_ADDR64 | HW_OWNER);
2841 		sc_if->msk_cdata.msk_tx_cnt++;
2842 		MSK_INC(prod, MSK_TX_RING_CNT);
2843 	}
2844 #endif
2845 	si = prod;
2846 	tx_le = &sc_if->msk_rdata.msk_tx_ring[prod];
2847 	tx_le->msk_addr = htole32(MSK_ADDR_LO(txsegs[0].ds_addr));
2848 	if (tso == 0)
2849 		tx_le->msk_control = htole32(txsegs[0].ds_len | control |
2850 		    OP_PACKET);
2851 	else
2852 		tx_le->msk_control = htole32(txsegs[0].ds_len | control |
2853 		    OP_LARGESEND);
2854 	sc_if->msk_cdata.msk_tx_cnt++;
2855 	MSK_INC(prod, MSK_TX_RING_CNT);
2856 
2857 	for (i = 1; i < nseg; i++) {
2858 		tx_le = &sc_if->msk_rdata.msk_tx_ring[prod];
2859 #ifdef MSK_64BIT_DMA
2860 		if (MSK_ADDR_HI(txsegs[i].ds_addr) !=
2861 		    sc_if->msk_cdata.msk_tx_high_addr) {
2862 			sc_if->msk_cdata.msk_tx_high_addr =
2863 			    MSK_ADDR_HI(txsegs[i].ds_addr);
2864 			tx_le = &sc_if->msk_rdata.msk_tx_ring[prod];
2865 			tx_le->msk_addr =
2866 			    htole32(MSK_ADDR_HI(txsegs[i].ds_addr));
2867 			tx_le->msk_control = htole32(OP_ADDR64 | HW_OWNER);
2868 			sc_if->msk_cdata.msk_tx_cnt++;
2869 			MSK_INC(prod, MSK_TX_RING_CNT);
2870 			tx_le = &sc_if->msk_rdata.msk_tx_ring[prod];
2871 		}
2872 #endif
2873 		tx_le->msk_addr = htole32(MSK_ADDR_LO(txsegs[i].ds_addr));
2874 		tx_le->msk_control = htole32(txsegs[i].ds_len | control |
2875 		    OP_BUFFER | HW_OWNER);
2876 		sc_if->msk_cdata.msk_tx_cnt++;
2877 		MSK_INC(prod, MSK_TX_RING_CNT);
2878 	}
2879 	/* Update producer index. */
2880 	sc_if->msk_cdata.msk_tx_prod = prod;
2881 
2882 	/* Set EOP on the last descriptor. */
2883 	prod = (prod + MSK_TX_RING_CNT - 1) % MSK_TX_RING_CNT;
2884 	tx_le = &sc_if->msk_rdata.msk_tx_ring[prod];
2885 	tx_le->msk_control |= htole32(EOP);
2886 
2887 	/* Turn the first descriptor ownership to hardware. */
2888 	tx_le = &sc_if->msk_rdata.msk_tx_ring[si];
2889 	tx_le->msk_control |= htole32(HW_OWNER);
2890 
2891 	txd = &sc_if->msk_cdata.msk_txdesc[prod];
2892 	map = txd_last->tx_dmamap;
2893 	txd_last->tx_dmamap = txd->tx_dmamap;
2894 	txd->tx_dmamap = map;
2895 	txd->tx_m = m;
2896 
2897 	/* Sync descriptors. */
2898 	bus_dmamap_sync(sc_if->msk_cdata.msk_tx_tag, map, BUS_DMASYNC_PREWRITE);
2899 	bus_dmamap_sync(sc_if->msk_cdata.msk_tx_ring_tag,
2900 	    sc_if->msk_cdata.msk_tx_ring_map,
2901 	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2902 
2903 	return (0);
2904 }
2905 
2906 static void
2907 msk_start(struct ifnet *ifp)
2908 {
2909 	struct msk_if_softc *sc_if;
2910 
2911 	sc_if = ifp->if_softc;
2912 	MSK_IF_LOCK(sc_if);
2913 	msk_start_locked(ifp);
2914 	MSK_IF_UNLOCK(sc_if);
2915 }
2916 
2917 static void
2918 msk_start_locked(struct ifnet *ifp)
2919 {
2920 	struct msk_if_softc *sc_if;
2921 	struct mbuf *m_head;
2922 	int enq;
2923 
2924 	sc_if = ifp->if_softc;
2925 	MSK_IF_LOCK_ASSERT(sc_if);
2926 
2927 	if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
2928 	    IFF_DRV_RUNNING || (sc_if->msk_flags & MSK_FLAG_LINK) == 0)
2929 		return;
2930 
2931 	for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) &&
2932 	    sc_if->msk_cdata.msk_tx_cnt <
2933 	    (MSK_TX_RING_CNT - MSK_RESERVED_TX_DESC_CNT); ) {
2934 		IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
2935 		if (m_head == NULL)
2936 			break;
2937 		/*
2938 		 * Pack the data into the transmit ring. If we
2939 		 * don't have room, set the OACTIVE flag and wait
2940 		 * for the NIC to drain the ring.
2941 		 */
2942 		if (msk_encap(sc_if, &m_head) != 0) {
2943 			if (m_head == NULL)
2944 				break;
2945 			IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
2946 			ifp->if_drv_flags |= IFF_DRV_OACTIVE;
2947 			break;
2948 		}
2949 
2950 		enq++;
2951 		/*
2952 		 * If there's a BPF listener, bounce a copy of this frame
2953 		 * to him.
2954 		 */
2955 		ETHER_BPF_MTAP(ifp, m_head);
2956 	}
2957 
2958 	if (enq > 0) {
2959 		/* Transmit */
2960 		CSR_WRITE_2(sc_if->msk_softc,
2961 		    Y2_PREF_Q_ADDR(sc_if->msk_txq, PREF_UNIT_PUT_IDX_REG),
2962 		    sc_if->msk_cdata.msk_tx_prod);
2963 
2964 		/* Set a timeout in case the chip goes out to lunch. */
2965 		sc_if->msk_watchdog_timer = MSK_TX_TIMEOUT;
2966 	}
2967 }
2968 
2969 static void
2970 msk_watchdog(struct msk_if_softc *sc_if)
2971 {
2972 	struct ifnet *ifp;
2973 
2974 	MSK_IF_LOCK_ASSERT(sc_if);
2975 
2976 	if (sc_if->msk_watchdog_timer == 0 || --sc_if->msk_watchdog_timer)
2977 		return;
2978 	ifp = sc_if->msk_ifp;
2979 	if ((sc_if->msk_flags & MSK_FLAG_LINK) == 0) {
2980 		if (bootverbose)
2981 			if_printf(sc_if->msk_ifp, "watchdog timeout "
2982 			   "(missed link)\n");
2983 		ifp->if_oerrors++;
2984 		ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2985 		msk_init_locked(sc_if);
2986 		return;
2987 	}
2988 
2989 	if_printf(ifp, "watchdog timeout\n");
2990 	ifp->if_oerrors++;
2991 	ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2992 	msk_init_locked(sc_if);
2993 	if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
2994 		msk_start_locked(ifp);
2995 }
2996 
2997 static int
2998 mskc_shutdown(device_t dev)
2999 {
3000 	struct msk_softc *sc;
3001 	int i;
3002 
3003 	sc = device_get_softc(dev);
3004 	MSK_LOCK(sc);
3005 	for (i = 0; i < sc->msk_num_port; i++) {
3006 		if (sc->msk_if[i] != NULL && sc->msk_if[i]->msk_ifp != NULL &&
3007 		    ((sc->msk_if[i]->msk_ifp->if_drv_flags &
3008 		    IFF_DRV_RUNNING) != 0))
3009 			msk_stop(sc->msk_if[i]);
3010 	}
3011 	MSK_UNLOCK(sc);
3012 
3013 	/* Put hardware reset. */
3014 	CSR_WRITE_2(sc, B0_CTST, CS_RST_SET);
3015 	return (0);
3016 }
3017 
3018 static int
3019 mskc_suspend(device_t dev)
3020 {
3021 	struct msk_softc *sc;
3022 	int i;
3023 
3024 	sc = device_get_softc(dev);
3025 
3026 	MSK_LOCK(sc);
3027 
3028 	for (i = 0; i < sc->msk_num_port; i++) {
3029 		if (sc->msk_if[i] != NULL && sc->msk_if[i]->msk_ifp != NULL &&
3030 		    ((sc->msk_if[i]->msk_ifp->if_drv_flags &
3031 		    IFF_DRV_RUNNING) != 0))
3032 			msk_stop(sc->msk_if[i]);
3033 	}
3034 
3035 	/* Disable all interrupts. */
3036 	CSR_WRITE_4(sc, B0_IMSK, 0);
3037 	CSR_READ_4(sc, B0_IMSK);
3038 	CSR_WRITE_4(sc, B0_HWE_IMSK, 0);
3039 	CSR_READ_4(sc, B0_HWE_IMSK);
3040 
3041 	msk_phy_power(sc, MSK_PHY_POWERDOWN);
3042 
3043 	/* Put hardware reset. */
3044 	CSR_WRITE_2(sc, B0_CTST, CS_RST_SET);
3045 	sc->msk_pflags |= MSK_FLAG_SUSPEND;
3046 
3047 	MSK_UNLOCK(sc);
3048 
3049 	return (0);
3050 }
3051 
3052 static int
3053 mskc_resume(device_t dev)
3054 {
3055 	struct msk_softc *sc;
3056 	int i;
3057 
3058 	sc = device_get_softc(dev);
3059 
3060 	MSK_LOCK(sc);
3061 
3062 	CSR_PCI_WRITE_4(sc, PCI_OUR_REG_3, 0);
3063 	mskc_reset(sc);
3064 	for (i = 0; i < sc->msk_num_port; i++) {
3065 		if (sc->msk_if[i] != NULL && sc->msk_if[i]->msk_ifp != NULL &&
3066 		    ((sc->msk_if[i]->msk_ifp->if_flags & IFF_UP) != 0)) {
3067 			sc->msk_if[i]->msk_ifp->if_drv_flags &=
3068 			    ~IFF_DRV_RUNNING;
3069 			msk_init_locked(sc->msk_if[i]);
3070 		}
3071 	}
3072 	sc->msk_pflags &= ~MSK_FLAG_SUSPEND;
3073 
3074 	MSK_UNLOCK(sc);
3075 
3076 	return (0);
3077 }
3078 
3079 #ifndef __NO_STRICT_ALIGNMENT
3080 static __inline void
3081 msk_fixup_rx(struct mbuf *m)
3082 {
3083         int i;
3084         uint16_t *src, *dst;
3085 
3086 	src = mtod(m, uint16_t *);
3087 	dst = src - 3;
3088 
3089 	for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++)
3090 		*dst++ = *src++;
3091 
3092 	m->m_data -= (MSK_RX_BUF_ALIGN - ETHER_ALIGN);
3093 }
3094 #endif
3095 
3096 static __inline void
3097 msk_rxcsum(struct msk_if_softc *sc_if, uint32_t control, struct mbuf *m)
3098 {
3099 	struct ether_header *eh;
3100 	struct ip *ip;
3101 	struct udphdr *uh;
3102 	int32_t hlen, len, pktlen, temp32;
3103 	uint16_t csum, *opts;
3104 
3105 	if ((sc_if->msk_flags & MSK_FLAG_DESCV2) != 0) {
3106 		if ((control & (CSS_IPV4 | CSS_IPFRAG)) == CSS_IPV4) {
3107 			m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
3108 			if ((control & CSS_IPV4_CSUM_OK) != 0)
3109 				m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
3110 			if ((control & (CSS_TCP | CSS_UDP)) != 0 &&
3111 			    (control & (CSS_TCPUDP_CSUM_OK)) != 0) {
3112 				m->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
3113 				    CSUM_PSEUDO_HDR;
3114 				m->m_pkthdr.csum_data = 0xffff;
3115 			}
3116 		}
3117 		return;
3118 	}
3119 	/*
3120 	 * Marvell Yukon controllers that support OP_RXCHKS has known
3121 	 * to have various Rx checksum offloading bugs. These
3122 	 * controllers can be configured to compute simple checksum
3123 	 * at two different positions. So we can compute IP and TCP/UDP
3124 	 * checksum at the same time. We intentionally have controller
3125 	 * compute TCP/UDP checksum twice by specifying the same
3126 	 * checksum start position and compare the result. If the value
3127 	 * is different it would indicate the hardware logic was wrong.
3128 	 */
3129 	if ((sc_if->msk_csum & 0xFFFF) != (sc_if->msk_csum >> 16)) {
3130 		if (bootverbose)
3131 			device_printf(sc_if->msk_if_dev,
3132 			    "Rx checksum value mismatch!\n");
3133 		return;
3134 	}
3135 	pktlen = m->m_pkthdr.len;
3136 	if (pktlen < sizeof(struct ether_header) + sizeof(struct ip))
3137 		return;
3138 	eh = mtod(m, struct ether_header *);
3139 	if (eh->ether_type != htons(ETHERTYPE_IP))
3140 		return;
3141 	ip = (struct ip *)(eh + 1);
3142 	if (ip->ip_v != IPVERSION)
3143 		return;
3144 
3145 	hlen = ip->ip_hl << 2;
3146 	pktlen -= sizeof(struct ether_header);
3147 	if (hlen < sizeof(struct ip))
3148 		return;
3149 	if (ntohs(ip->ip_len) < hlen)
3150 		return;
3151 	if (ntohs(ip->ip_len) != pktlen)
3152 		return;
3153 	if (ip->ip_off & htons(IP_MF | IP_OFFMASK))
3154 		return;	/* can't handle fragmented packet. */
3155 
3156 	switch (ip->ip_p) {
3157 	case IPPROTO_TCP:
3158 		if (pktlen < (hlen + sizeof(struct tcphdr)))
3159 			return;
3160 		break;
3161 	case IPPROTO_UDP:
3162 		if (pktlen < (hlen + sizeof(struct udphdr)))
3163 			return;
3164 		uh = (struct udphdr *)((caddr_t)ip + hlen);
3165 		if (uh->uh_sum == 0)
3166 			return; /* no checksum */
3167 		break;
3168 	default:
3169 		return;
3170 	}
3171 	csum = bswap16(sc_if->msk_csum & 0xFFFF);
3172 	/* Checksum fixup for IP options. */
3173 	len = hlen - sizeof(struct ip);
3174 	if (len > 0) {
3175 		opts = (uint16_t *)(ip + 1);
3176 		for (; len > 0; len -= sizeof(uint16_t), opts++) {
3177 			temp32 = csum - *opts;
3178 			temp32 = (temp32 >> 16) + (temp32 & 65535);
3179 			csum = temp32 & 65535;
3180 		}
3181 	}
3182 	m->m_pkthdr.csum_flags |= CSUM_DATA_VALID;
3183 	m->m_pkthdr.csum_data = csum;
3184 }
3185 
3186 static void
3187 msk_rxeof(struct msk_if_softc *sc_if, uint32_t status, uint32_t control,
3188     int len)
3189 {
3190 	struct mbuf *m;
3191 	struct ifnet *ifp;
3192 	struct msk_rxdesc *rxd;
3193 	int cons, rxlen;
3194 
3195 	ifp = sc_if->msk_ifp;
3196 
3197 	MSK_IF_LOCK_ASSERT(sc_if);
3198 
3199 	cons = sc_if->msk_cdata.msk_rx_cons;
3200 	do {
3201 		rxlen = status >> 16;
3202 		if ((status & GMR_FS_VLAN) != 0 &&
3203 		    (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0)
3204 			rxlen -= ETHER_VLAN_ENCAP_LEN;
3205 		if ((sc_if->msk_flags & MSK_FLAG_NORXCHK) != 0) {
3206 			/*
3207 			 * For controllers that returns bogus status code
3208 			 * just do minimal check and let upper stack
3209 			 * handle this frame.
3210 			 */
3211 			if (len > MSK_MAX_FRAMELEN || len < ETHER_HDR_LEN) {
3212 				ifp->if_ierrors++;
3213 				msk_discard_rxbuf(sc_if, cons);
3214 				break;
3215 			}
3216 		} else if (len > sc_if->msk_framesize ||
3217 		    ((status & GMR_FS_ANY_ERR) != 0) ||
3218 		    ((status & GMR_FS_RX_OK) == 0) || (rxlen != len)) {
3219 			/* Don't count flow-control packet as errors. */
3220 			if ((status & GMR_FS_GOOD_FC) == 0)
3221 				ifp->if_ierrors++;
3222 			msk_discard_rxbuf(sc_if, cons);
3223 			break;
3224 		}
3225 #ifdef MSK_64BIT_DMA
3226 		rxd = &sc_if->msk_cdata.msk_rxdesc[(cons + 1) %
3227 		    MSK_RX_RING_CNT];
3228 #else
3229 		rxd = &sc_if->msk_cdata.msk_rxdesc[cons];
3230 #endif
3231 		m = rxd->rx_m;
3232 		if (msk_newbuf(sc_if, cons) != 0) {
3233 			ifp->if_iqdrops++;
3234 			/* Reuse old buffer. */
3235 			msk_discard_rxbuf(sc_if, cons);
3236 			break;
3237 		}
3238 		m->m_pkthdr.rcvif = ifp;
3239 		m->m_pkthdr.len = m->m_len = len;
3240 #ifndef __NO_STRICT_ALIGNMENT
3241 		if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) != 0)
3242 			msk_fixup_rx(m);
3243 #endif
3244 		ifp->if_ipackets++;
3245 		if ((ifp->if_capenable & IFCAP_RXCSUM) != 0)
3246 			msk_rxcsum(sc_if, control, m);
3247 		/* Check for VLAN tagged packets. */
3248 		if ((status & GMR_FS_VLAN) != 0 &&
3249 		    (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) {
3250 			m->m_pkthdr.ether_vtag = sc_if->msk_vtag;
3251 			m->m_flags |= M_VLANTAG;
3252 		}
3253 		MSK_IF_UNLOCK(sc_if);
3254 		(*ifp->if_input)(ifp, m);
3255 		MSK_IF_LOCK(sc_if);
3256 	} while (0);
3257 
3258 	MSK_RX_INC(sc_if->msk_cdata.msk_rx_cons, MSK_RX_RING_CNT);
3259 	MSK_RX_INC(sc_if->msk_cdata.msk_rx_prod, MSK_RX_RING_CNT);
3260 }
3261 
3262 static void
3263 msk_jumbo_rxeof(struct msk_if_softc *sc_if, uint32_t status, uint32_t control,
3264     int len)
3265 {
3266 	struct mbuf *m;
3267 	struct ifnet *ifp;
3268 	struct msk_rxdesc *jrxd;
3269 	int cons, rxlen;
3270 
3271 	ifp = sc_if->msk_ifp;
3272 
3273 	MSK_IF_LOCK_ASSERT(sc_if);
3274 
3275 	cons = sc_if->msk_cdata.msk_rx_cons;
3276 	do {
3277 		rxlen = status >> 16;
3278 		if ((status & GMR_FS_VLAN) != 0 &&
3279 		    (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0)
3280 			rxlen -= ETHER_VLAN_ENCAP_LEN;
3281 		if (len > sc_if->msk_framesize ||
3282 		    ((status & GMR_FS_ANY_ERR) != 0) ||
3283 		    ((status & GMR_FS_RX_OK) == 0) || (rxlen != len)) {
3284 			/* Don't count flow-control packet as errors. */
3285 			if ((status & GMR_FS_GOOD_FC) == 0)
3286 				ifp->if_ierrors++;
3287 			msk_discard_jumbo_rxbuf(sc_if, cons);
3288 			break;
3289 		}
3290 #ifdef MSK_64BIT_DMA
3291 		jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[(cons + 1) %
3292 		    MSK_JUMBO_RX_RING_CNT];
3293 #else
3294 		jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[cons];
3295 #endif
3296 		m = jrxd->rx_m;
3297 		if (msk_jumbo_newbuf(sc_if, cons) != 0) {
3298 			ifp->if_iqdrops++;
3299 			/* Reuse old buffer. */
3300 			msk_discard_jumbo_rxbuf(sc_if, cons);
3301 			break;
3302 		}
3303 		m->m_pkthdr.rcvif = ifp;
3304 		m->m_pkthdr.len = m->m_len = len;
3305 #ifndef __NO_STRICT_ALIGNMENT
3306 		if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) != 0)
3307 			msk_fixup_rx(m);
3308 #endif
3309 		ifp->if_ipackets++;
3310 		if ((ifp->if_capenable & IFCAP_RXCSUM) != 0)
3311 			msk_rxcsum(sc_if, control, m);
3312 		/* Check for VLAN tagged packets. */
3313 		if ((status & GMR_FS_VLAN) != 0 &&
3314 		    (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) {
3315 			m->m_pkthdr.ether_vtag = sc_if->msk_vtag;
3316 			m->m_flags |= M_VLANTAG;
3317 		}
3318 		MSK_IF_UNLOCK(sc_if);
3319 		(*ifp->if_input)(ifp, m);
3320 		MSK_IF_LOCK(sc_if);
3321 	} while (0);
3322 
3323 	MSK_RX_INC(sc_if->msk_cdata.msk_rx_cons, MSK_JUMBO_RX_RING_CNT);
3324 	MSK_RX_INC(sc_if->msk_cdata.msk_rx_prod, MSK_JUMBO_RX_RING_CNT);
3325 }
3326 
3327 static void
3328 msk_txeof(struct msk_if_softc *sc_if, int idx)
3329 {
3330 	struct msk_txdesc *txd;
3331 	struct msk_tx_desc *cur_tx;
3332 	struct ifnet *ifp;
3333 	uint32_t control;
3334 	int cons, prog;
3335 
3336 	MSK_IF_LOCK_ASSERT(sc_if);
3337 
3338 	ifp = sc_if->msk_ifp;
3339 
3340 	bus_dmamap_sync(sc_if->msk_cdata.msk_tx_ring_tag,
3341 	    sc_if->msk_cdata.msk_tx_ring_map,
3342 	    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
3343 	/*
3344 	 * Go through our tx ring and free mbufs for those
3345 	 * frames that have been sent.
3346 	 */
3347 	cons = sc_if->msk_cdata.msk_tx_cons;
3348 	prog = 0;
3349 	for (; cons != idx; MSK_INC(cons, MSK_TX_RING_CNT)) {
3350 		if (sc_if->msk_cdata.msk_tx_cnt <= 0)
3351 			break;
3352 		prog++;
3353 		cur_tx = &sc_if->msk_rdata.msk_tx_ring[cons];
3354 		control = le32toh(cur_tx->msk_control);
3355 		sc_if->msk_cdata.msk_tx_cnt--;
3356 		ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
3357 		if ((control & EOP) == 0)
3358 			continue;
3359 		txd = &sc_if->msk_cdata.msk_txdesc[cons];
3360 		bus_dmamap_sync(sc_if->msk_cdata.msk_tx_tag, txd->tx_dmamap,
3361 		    BUS_DMASYNC_POSTWRITE);
3362 		bus_dmamap_unload(sc_if->msk_cdata.msk_tx_tag, txd->tx_dmamap);
3363 
3364 		ifp->if_opackets++;
3365 		KASSERT(txd->tx_m != NULL, ("%s: freeing NULL mbuf!",
3366 		    __func__));
3367 		m_freem(txd->tx_m);
3368 		txd->tx_m = NULL;
3369 	}
3370 
3371 	if (prog > 0) {
3372 		sc_if->msk_cdata.msk_tx_cons = cons;
3373 		if (sc_if->msk_cdata.msk_tx_cnt == 0)
3374 			sc_if->msk_watchdog_timer = 0;
3375 		/* No need to sync LEs as we didn't update LEs. */
3376 	}
3377 }
3378 
3379 static void
3380 msk_tick(void *xsc_if)
3381 {
3382 	struct msk_if_softc *sc_if;
3383 	struct mii_data *mii;
3384 
3385 	sc_if = xsc_if;
3386 
3387 	MSK_IF_LOCK_ASSERT(sc_if);
3388 
3389 	mii = device_get_softc(sc_if->msk_miibus);
3390 
3391 	mii_tick(mii);
3392 	if ((sc_if->msk_flags & MSK_FLAG_LINK) == 0)
3393 		msk_miibus_statchg(sc_if->msk_if_dev);
3394 	msk_handle_events(sc_if->msk_softc);
3395 	msk_watchdog(sc_if);
3396 	callout_reset(&sc_if->msk_tick_ch, hz, msk_tick, sc_if);
3397 }
3398 
3399 static void
3400 msk_intr_phy(struct msk_if_softc *sc_if)
3401 {
3402 	uint16_t status;
3403 
3404 	msk_phy_readreg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_STAT);
3405 	status = msk_phy_readreg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_STAT);
3406 	/* Handle FIFO Underrun/Overflow? */
3407 	if ((status & PHY_M_IS_FIFO_ERROR))
3408 		device_printf(sc_if->msk_if_dev,
3409 		    "PHY FIFO underrun/overflow.\n");
3410 }
3411 
3412 static void
3413 msk_intr_gmac(struct msk_if_softc *sc_if)
3414 {
3415 	struct msk_softc *sc;
3416 	uint8_t status;
3417 
3418 	sc = sc_if->msk_softc;
3419 	status = CSR_READ_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_SRC));
3420 
3421 	/* GMAC Rx FIFO overrun. */
3422 	if ((status & GM_IS_RX_FF_OR) != 0)
3423 		CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T),
3424 		    GMF_CLI_RX_FO);
3425 	/* GMAC Tx FIFO underrun. */
3426 	if ((status & GM_IS_TX_FF_UR) != 0) {
3427 		CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T),
3428 		    GMF_CLI_TX_FU);
3429 		device_printf(sc_if->msk_if_dev, "Tx FIFO underrun!\n");
3430 		/*
3431 		 * XXX
3432 		 * In case of Tx underrun, we may need to flush/reset
3433 		 * Tx MAC but that would also require resynchronization
3434 		 * with status LEs. Reinitializing status LEs would
3435 		 * affect other port in dual MAC configuration so it
3436 		 * should be avoided as possible as we can.
3437 		 * Due to lack of documentation it's all vague guess but
3438 		 * it needs more investigation.
3439 		 */
3440 	}
3441 }
3442 
3443 static void
3444 msk_handle_hwerr(struct msk_if_softc *sc_if, uint32_t status)
3445 {
3446 	struct msk_softc *sc;
3447 
3448 	sc = sc_if->msk_softc;
3449 	if ((status & Y2_IS_PAR_RD1) != 0) {
3450 		device_printf(sc_if->msk_if_dev,
3451 		    "RAM buffer read parity error\n");
3452 		/* Clear IRQ. */
3453 		CSR_WRITE_2(sc, SELECT_RAM_BUFFER(sc_if->msk_port, B3_RI_CTRL),
3454 		    RI_CLR_RD_PERR);
3455 	}
3456 	if ((status & Y2_IS_PAR_WR1) != 0) {
3457 		device_printf(sc_if->msk_if_dev,
3458 		    "RAM buffer write parity error\n");
3459 		/* Clear IRQ. */
3460 		CSR_WRITE_2(sc, SELECT_RAM_BUFFER(sc_if->msk_port, B3_RI_CTRL),
3461 		    RI_CLR_WR_PERR);
3462 	}
3463 	if ((status & Y2_IS_PAR_MAC1) != 0) {
3464 		device_printf(sc_if->msk_if_dev, "Tx MAC parity error\n");
3465 		/* Clear IRQ. */
3466 		CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T),
3467 		    GMF_CLI_TX_PE);
3468 	}
3469 	if ((status & Y2_IS_PAR_RX1) != 0) {
3470 		device_printf(sc_if->msk_if_dev, "Rx parity error\n");
3471 		/* Clear IRQ. */
3472 		CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_CLR_IRQ_PAR);
3473 	}
3474 	if ((status & (Y2_IS_TCP_TXS1 | Y2_IS_TCP_TXA1)) != 0) {
3475 		device_printf(sc_if->msk_if_dev, "TCP segmentation error\n");
3476 		/* Clear IRQ. */
3477 		CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_CLR_IRQ_TCP);
3478 	}
3479 }
3480 
3481 static void
3482 msk_intr_hwerr(struct msk_softc *sc)
3483 {
3484 	uint32_t status;
3485 	uint32_t tlphead[4];
3486 
3487 	status = CSR_READ_4(sc, B0_HWE_ISRC);
3488 	/* Time Stamp timer overflow. */
3489 	if ((status & Y2_IS_TIST_OV) != 0)
3490 		CSR_WRITE_1(sc, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
3491 	if ((status & Y2_IS_PCI_NEXP) != 0) {
3492 		/*
3493 		 * PCI Express Error occured which is not described in PEX
3494 		 * spec.
3495 		 * This error is also mapped either to Master Abort(
3496 		 * Y2_IS_MST_ERR) or Target Abort (Y2_IS_IRQ_STAT) bit and
3497 		 * can only be cleared there.
3498                  */
3499 		device_printf(sc->msk_dev,
3500 		    "PCI Express protocol violation error\n");
3501 	}
3502 
3503 	if ((status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) != 0) {
3504 		uint16_t v16;
3505 
3506 		if ((status & Y2_IS_MST_ERR) != 0)
3507 			device_printf(sc->msk_dev,
3508 			    "unexpected IRQ Status error\n");
3509 		else
3510 			device_printf(sc->msk_dev,
3511 			    "unexpected IRQ Master error\n");
3512 		/* Reset all bits in the PCI status register. */
3513 		v16 = pci_read_config(sc->msk_dev, PCIR_STATUS, 2);
3514 		CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3515 		pci_write_config(sc->msk_dev, PCIR_STATUS, v16 |
3516 		    PCIM_STATUS_PERR | PCIM_STATUS_SERR | PCIM_STATUS_RMABORT |
3517 		    PCIM_STATUS_RTABORT | PCIM_STATUS_MDPERR, 2);
3518 		CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3519 	}
3520 
3521 	/* Check for PCI Express Uncorrectable Error. */
3522 	if ((status & Y2_IS_PCI_EXP) != 0) {
3523 		uint32_t v32;
3524 
3525 		/*
3526 		 * On PCI Express bus bridges are called root complexes (RC).
3527 		 * PCI Express errors are recognized by the root complex too,
3528 		 * which requests the system to handle the problem. After
3529 		 * error occurrence it may be that no access to the adapter
3530 		 * may be performed any longer.
3531 		 */
3532 
3533 		v32 = CSR_PCI_READ_4(sc, PEX_UNC_ERR_STAT);
3534 		if ((v32 & PEX_UNSUP_REQ) != 0) {
3535 			/* Ignore unsupported request error. */
3536 			device_printf(sc->msk_dev,
3537 			    "Uncorrectable PCI Express error\n");
3538 		}
3539 		if ((v32 & (PEX_FATAL_ERRORS | PEX_POIS_TLP)) != 0) {
3540 			int i;
3541 
3542 			/* Get TLP header form Log Registers. */
3543 			for (i = 0; i < 4; i++)
3544 				tlphead[i] = CSR_PCI_READ_4(sc,
3545 				    PEX_HEADER_LOG + i * 4);
3546 			/* Check for vendor defined broadcast message. */
3547 			if (!(tlphead[0] == 0x73004001 && tlphead[1] == 0x7f)) {
3548 				sc->msk_intrhwemask &= ~Y2_IS_PCI_EXP;
3549 				CSR_WRITE_4(sc, B0_HWE_IMSK,
3550 				    sc->msk_intrhwemask);
3551 				CSR_READ_4(sc, B0_HWE_IMSK);
3552 			}
3553 		}
3554 		/* Clear the interrupt. */
3555 		CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3556 		CSR_PCI_WRITE_4(sc, PEX_UNC_ERR_STAT, 0xffffffff);
3557 		CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3558 	}
3559 
3560 	if ((status & Y2_HWE_L1_MASK) != 0 && sc->msk_if[MSK_PORT_A] != NULL)
3561 		msk_handle_hwerr(sc->msk_if[MSK_PORT_A], status);
3562 	if ((status & Y2_HWE_L2_MASK) != 0 && sc->msk_if[MSK_PORT_B] != NULL)
3563 		msk_handle_hwerr(sc->msk_if[MSK_PORT_B], status >> 8);
3564 }
3565 
3566 static __inline void
3567 msk_rxput(struct msk_if_softc *sc_if)
3568 {
3569 	struct msk_softc *sc;
3570 
3571 	sc = sc_if->msk_softc;
3572 	if (sc_if->msk_framesize > (MCLBYTES - MSK_RX_BUF_ALIGN))
3573 		bus_dmamap_sync(
3574 		    sc_if->msk_cdata.msk_jumbo_rx_ring_tag,
3575 		    sc_if->msk_cdata.msk_jumbo_rx_ring_map,
3576 		    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3577 	else
3578 		bus_dmamap_sync(
3579 		    sc_if->msk_cdata.msk_rx_ring_tag,
3580 		    sc_if->msk_cdata.msk_rx_ring_map,
3581 		    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3582 	CSR_WRITE_2(sc, Y2_PREF_Q_ADDR(sc_if->msk_rxq,
3583 	    PREF_UNIT_PUT_IDX_REG), sc_if->msk_cdata.msk_rx_prod);
3584 }
3585 
3586 static int
3587 msk_handle_events(struct msk_softc *sc)
3588 {
3589 	struct msk_if_softc *sc_if;
3590 	int rxput[2];
3591 	struct msk_stat_desc *sd;
3592 	uint32_t control, status;
3593 	int cons, len, port, rxprog;
3594 
3595 	if (sc->msk_stat_cons == CSR_READ_2(sc, STAT_PUT_IDX))
3596 		return (0);
3597 
3598 	/* Sync status LEs. */
3599 	bus_dmamap_sync(sc->msk_stat_tag, sc->msk_stat_map,
3600 	    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
3601 
3602 	rxput[MSK_PORT_A] = rxput[MSK_PORT_B] = 0;
3603 	rxprog = 0;
3604 	cons = sc->msk_stat_cons;
3605 	for (;;) {
3606 		sd = &sc->msk_stat_ring[cons];
3607 		control = le32toh(sd->msk_control);
3608 		if ((control & HW_OWNER) == 0)
3609 			break;
3610 		control &= ~HW_OWNER;
3611 		sd->msk_control = htole32(control);
3612 		status = le32toh(sd->msk_status);
3613 		len = control & STLE_LEN_MASK;
3614 		port = (control >> 16) & 0x01;
3615 		sc_if = sc->msk_if[port];
3616 		if (sc_if == NULL) {
3617 			device_printf(sc->msk_dev, "invalid port opcode "
3618 			    "0x%08x\n", control & STLE_OP_MASK);
3619 			continue;
3620 		}
3621 
3622 		switch (control & STLE_OP_MASK) {
3623 		case OP_RXVLAN:
3624 			sc_if->msk_vtag = ntohs(len);
3625 			break;
3626 		case OP_RXCHKSVLAN:
3627 			sc_if->msk_vtag = ntohs(len);
3628 			/* FALLTHROUGH */
3629 		case OP_RXCHKS:
3630 			sc_if->msk_csum = status;
3631 			break;
3632 		case OP_RXSTAT:
3633 			if (!(sc_if->msk_ifp->if_drv_flags & IFF_DRV_RUNNING))
3634 				break;
3635 			if (sc_if->msk_framesize >
3636 			    (MCLBYTES - MSK_RX_BUF_ALIGN))
3637 				msk_jumbo_rxeof(sc_if, status, control, len);
3638 			else
3639 				msk_rxeof(sc_if, status, control, len);
3640 			rxprog++;
3641 			/*
3642 			 * Because there is no way to sync single Rx LE
3643 			 * put the DMA sync operation off until the end of
3644 			 * event processing.
3645 			 */
3646 			rxput[port]++;
3647 			/* Update prefetch unit if we've passed water mark. */
3648 			if (rxput[port] >= sc_if->msk_cdata.msk_rx_putwm) {
3649 				msk_rxput(sc_if);
3650 				rxput[port] = 0;
3651 			}
3652 			break;
3653 		case OP_TXINDEXLE:
3654 			if (sc->msk_if[MSK_PORT_A] != NULL)
3655 				msk_txeof(sc->msk_if[MSK_PORT_A],
3656 				    status & STLE_TXA1_MSKL);
3657 			if (sc->msk_if[MSK_PORT_B] != NULL)
3658 				msk_txeof(sc->msk_if[MSK_PORT_B],
3659 				    ((status & STLE_TXA2_MSKL) >>
3660 				    STLE_TXA2_SHIFTL) |
3661 				    ((len & STLE_TXA2_MSKH) <<
3662 				    STLE_TXA2_SHIFTH));
3663 			break;
3664 		default:
3665 			device_printf(sc->msk_dev, "unhandled opcode 0x%08x\n",
3666 			    control & STLE_OP_MASK);
3667 			break;
3668 		}
3669 		MSK_INC(cons, sc->msk_stat_count);
3670 		if (rxprog > sc->msk_process_limit)
3671 			break;
3672 	}
3673 
3674 	sc->msk_stat_cons = cons;
3675 	bus_dmamap_sync(sc->msk_stat_tag, sc->msk_stat_map,
3676 	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3677 
3678 	if (rxput[MSK_PORT_A] > 0)
3679 		msk_rxput(sc->msk_if[MSK_PORT_A]);
3680 	if (rxput[MSK_PORT_B] > 0)
3681 		msk_rxput(sc->msk_if[MSK_PORT_B]);
3682 
3683 	return (sc->msk_stat_cons != CSR_READ_2(sc, STAT_PUT_IDX));
3684 }
3685 
3686 static void
3687 msk_intr(void *xsc)
3688 {
3689 	struct msk_softc *sc;
3690 	struct msk_if_softc *sc_if0, *sc_if1;
3691 	struct ifnet *ifp0, *ifp1;
3692 	uint32_t status;
3693 	int domore;
3694 
3695 	sc = xsc;
3696 	MSK_LOCK(sc);
3697 
3698 	/* Reading B0_Y2_SP_ISRC2 masks further interrupts. */
3699 	status = CSR_READ_4(sc, B0_Y2_SP_ISRC2);
3700 	if (status == 0 || status == 0xffffffff ||
3701 	    (sc->msk_pflags & MSK_FLAG_SUSPEND) != 0 ||
3702 	    (status & sc->msk_intrmask) == 0) {
3703 		CSR_WRITE_4(sc, B0_Y2_SP_ICR, 2);
3704 		MSK_UNLOCK(sc);
3705 		return;
3706 	}
3707 
3708 	sc_if0 = sc->msk_if[MSK_PORT_A];
3709 	sc_if1 = sc->msk_if[MSK_PORT_B];
3710 	ifp0 = ifp1 = NULL;
3711 	if (sc_if0 != NULL)
3712 		ifp0 = sc_if0->msk_ifp;
3713 	if (sc_if1 != NULL)
3714 		ifp1 = sc_if1->msk_ifp;
3715 
3716 	if ((status & Y2_IS_IRQ_PHY1) != 0 && sc_if0 != NULL)
3717 		msk_intr_phy(sc_if0);
3718 	if ((status & Y2_IS_IRQ_PHY2) != 0 && sc_if1 != NULL)
3719 		msk_intr_phy(sc_if1);
3720 	if ((status & Y2_IS_IRQ_MAC1) != 0 && sc_if0 != NULL)
3721 		msk_intr_gmac(sc_if0);
3722 	if ((status & Y2_IS_IRQ_MAC2) != 0 && sc_if1 != NULL)
3723 		msk_intr_gmac(sc_if1);
3724 	if ((status & (Y2_IS_CHK_RX1 | Y2_IS_CHK_RX2)) != 0) {
3725 		device_printf(sc->msk_dev, "Rx descriptor error\n");
3726 		sc->msk_intrmask &= ~(Y2_IS_CHK_RX1 | Y2_IS_CHK_RX2);
3727 		CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask);
3728 		CSR_READ_4(sc, B0_IMSK);
3729 	}
3730         if ((status & (Y2_IS_CHK_TXA1 | Y2_IS_CHK_TXA2)) != 0) {
3731 		device_printf(sc->msk_dev, "Tx descriptor error\n");
3732 		sc->msk_intrmask &= ~(Y2_IS_CHK_TXA1 | Y2_IS_CHK_TXA2);
3733 		CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask);
3734 		CSR_READ_4(sc, B0_IMSK);
3735 	}
3736 	if ((status & Y2_IS_HW_ERR) != 0)
3737 		msk_intr_hwerr(sc);
3738 
3739 	domore = msk_handle_events(sc);
3740 	if ((status & Y2_IS_STAT_BMU) != 0 && domore == 0)
3741 		CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_CLR_IRQ);
3742 
3743 	/* Clear TWSI IRQ. */
3744 	if ((status & Y2_IS_TWSI_RDY) != 0)
3745 		CSR_WRITE_4(sc, B2_I2C_IRQ, 1);
3746 	/* Reenable interrupts. */
3747 	CSR_WRITE_4(sc, B0_Y2_SP_ICR, 2);
3748 
3749 	if (ifp0 != NULL && (ifp0->if_drv_flags & IFF_DRV_RUNNING) != 0 &&
3750 	    !IFQ_DRV_IS_EMPTY(&ifp0->if_snd))
3751 		msk_start_locked(ifp0);
3752 	if (ifp1 != NULL && (ifp1->if_drv_flags & IFF_DRV_RUNNING) != 0 &&
3753 	    !IFQ_DRV_IS_EMPTY(&ifp1->if_snd))
3754 		msk_start_locked(ifp1);
3755 
3756 	MSK_UNLOCK(sc);
3757 }
3758 
3759 static void
3760 msk_set_tx_stfwd(struct msk_if_softc *sc_if)
3761 {
3762 	struct msk_softc *sc;
3763 	struct ifnet *ifp;
3764 
3765 	ifp = sc_if->msk_ifp;
3766 	sc = sc_if->msk_softc;
3767 	if ((sc->msk_hw_id == CHIP_ID_YUKON_EX &&
3768 	    sc->msk_hw_rev != CHIP_REV_YU_EX_A0) ||
3769 	    sc->msk_hw_id >= CHIP_ID_YUKON_SUPR) {
3770 		CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T),
3771 		    TX_STFW_ENA);
3772 	} else {
3773 		if (ifp->if_mtu > ETHERMTU) {
3774 			/* Set Tx GMAC FIFO Almost Empty Threshold. */
3775 			CSR_WRITE_4(sc,
3776 			    MR_ADDR(sc_if->msk_port, TX_GMF_AE_THR),
3777 			    MSK_ECU_JUMBO_WM << 16 | MSK_ECU_AE_THR);
3778 			/* Disable Store & Forward mode for Tx. */
3779 			CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T),
3780 			    TX_STFW_DIS);
3781 		} else {
3782 			CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T),
3783 			    TX_STFW_ENA);
3784 		}
3785 	}
3786 }
3787 
3788 static void
3789 msk_init(void *xsc)
3790 {
3791 	struct msk_if_softc *sc_if = xsc;
3792 
3793 	MSK_IF_LOCK(sc_if);
3794 	msk_init_locked(sc_if);
3795 	MSK_IF_UNLOCK(sc_if);
3796 }
3797 
3798 static void
3799 msk_init_locked(struct msk_if_softc *sc_if)
3800 {
3801 	struct msk_softc *sc;
3802 	struct ifnet *ifp;
3803 	struct mii_data	 *mii;
3804 	uint8_t *eaddr;
3805 	uint16_t gmac;
3806 	uint32_t reg;
3807 	int error;
3808 
3809 	MSK_IF_LOCK_ASSERT(sc_if);
3810 
3811 	ifp = sc_if->msk_ifp;
3812 	sc = sc_if->msk_softc;
3813 	mii = device_get_softc(sc_if->msk_miibus);
3814 
3815 	if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
3816 		return;
3817 
3818 	error = 0;
3819 	/* Cancel pending I/O and free all Rx/Tx buffers. */
3820 	msk_stop(sc_if);
3821 
3822 	if (ifp->if_mtu < ETHERMTU)
3823 		sc_if->msk_framesize = ETHERMTU;
3824 	else
3825 		sc_if->msk_framesize = ifp->if_mtu;
3826 	sc_if->msk_framesize += ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
3827 	if (ifp->if_mtu > ETHERMTU &&
3828 	    (sc_if->msk_flags & MSK_FLAG_JUMBO_NOCSUM) != 0) {
3829 		ifp->if_hwassist &= ~(MSK_CSUM_FEATURES | CSUM_TSO);
3830 		ifp->if_capenable &= ~(IFCAP_TSO4 | IFCAP_TXCSUM);
3831 	}
3832 
3833 	/* GMAC Control reset. */
3834 	CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_RST_SET);
3835 	CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_RST_CLR);
3836 	CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_F_LOOPB_OFF);
3837 	if (sc->msk_hw_id == CHIP_ID_YUKON_EX ||
3838 	    sc->msk_hw_id == CHIP_ID_YUKON_SUPR)
3839 		CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL),
3840 		    GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON |
3841 		    GMC_BYP_RETR_ON);
3842 
3843 	/*
3844 	 * Initialize GMAC first such that speed/duplex/flow-control
3845 	 * parameters are renegotiated when interface is brought up.
3846 	 */
3847 	GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, 0);
3848 
3849 	/* Dummy read the Interrupt Source Register. */
3850 	CSR_READ_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_SRC));
3851 
3852 	/* Clear MIB stats. */
3853 	msk_stats_clear(sc_if);
3854 
3855 	/* Disable FCS. */
3856 	GMAC_WRITE_2(sc, sc_if->msk_port, GM_RX_CTRL, GM_RXCR_CRC_DIS);
3857 
3858 	/* Setup Transmit Control Register. */
3859 	GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
3860 
3861 	/* Setup Transmit Flow Control Register. */
3862 	GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_FLOW_CTRL, 0xffff);
3863 
3864 	/* Setup Transmit Parameter Register. */
3865 	GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_PARAM,
3866 	    TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) | TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
3867 	    TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) | TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
3868 
3869 	gmac = DATA_BLIND_VAL(DATA_BLIND_DEF) |
3870 	    GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
3871 
3872 	if (ifp->if_mtu > ETHERMTU)
3873 		gmac |= GM_SMOD_JUMBO_ENA;
3874 	GMAC_WRITE_2(sc, sc_if->msk_port, GM_SERIAL_MODE, gmac);
3875 
3876 	/* Set station address. */
3877 	eaddr = IF_LLADDR(ifp);
3878 	GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_1L,
3879 	    eaddr[0] | (eaddr[1] << 8));
3880 	GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_1M,
3881 	    eaddr[2] | (eaddr[3] << 8));
3882 	GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_1H,
3883 	    eaddr[4] | (eaddr[5] << 8));
3884 	GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_2L,
3885 	    eaddr[0] | (eaddr[1] << 8));
3886 	GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_2M,
3887 	    eaddr[2] | (eaddr[3] << 8));
3888 	GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_2H,
3889 	    eaddr[4] | (eaddr[5] << 8));
3890 
3891 	/* Disable interrupts for counter overflows. */
3892 	GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_IRQ_MSK, 0);
3893 	GMAC_WRITE_2(sc, sc_if->msk_port, GM_RX_IRQ_MSK, 0);
3894 	GMAC_WRITE_2(sc, sc_if->msk_port, GM_TR_IRQ_MSK, 0);
3895 
3896 	/* Configure Rx MAC FIFO. */
3897 	CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), GMF_RST_SET);
3898 	CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), GMF_RST_CLR);
3899 	reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
3900 	if (sc->msk_hw_id == CHIP_ID_YUKON_FE_P ||
3901 	    sc->msk_hw_id == CHIP_ID_YUKON_EX)
3902 		reg |= GMF_RX_OVER_ON;
3903 	CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), reg);
3904 
3905 	/* Set receive filter. */
3906 	msk_rxfilter(sc_if);
3907 
3908 	if (sc->msk_hw_id == CHIP_ID_YUKON_XL) {
3909 		/* Clear flush mask - HW bug. */
3910 		CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_FL_MSK), 0);
3911 	} else {
3912 		/* Flush Rx MAC FIFO on any flow control or error. */
3913 		CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_FL_MSK),
3914 		    GMR_FS_ANY_ERR);
3915 	}
3916 
3917 	/*
3918 	 * Set Rx FIFO flush threshold to 64 bytes + 1 FIFO word
3919 	 * due to hardware hang on receipt of pause frames.
3920 	 */
3921 	reg = RX_GMF_FL_THR_DEF + 1;
3922 	/* Another magic for Yukon FE+ - From Linux. */
3923 	if (sc->msk_hw_id == CHIP_ID_YUKON_FE_P &&
3924 	    sc->msk_hw_rev == CHIP_REV_YU_FE_P_A0)
3925 		reg = 0x178;
3926 	CSR_WRITE_2(sc, MR_ADDR(sc_if->msk_port, RX_GMF_FL_THR), reg);
3927 
3928 	/* Configure Tx MAC FIFO. */
3929 	CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_RST_SET);
3930 	CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_RST_CLR);
3931 	CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_OPER_ON);
3932 
3933 	/* Configure hardware VLAN tag insertion/stripping. */
3934 	msk_setvlan(sc_if, ifp);
3935 
3936 	if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) == 0) {
3937 		/* Set Rx Pause threshold. */
3938 		CSR_WRITE_2(sc, MR_ADDR(sc_if->msk_port, RX_GMF_LP_THR),
3939 		    MSK_ECU_LLPP);
3940 		CSR_WRITE_2(sc, MR_ADDR(sc_if->msk_port, RX_GMF_UP_THR),
3941 		    MSK_ECU_ULPP);
3942 		/* Configure store-and-forward for Tx. */
3943 		msk_set_tx_stfwd(sc_if);
3944 	}
3945 
3946 	if (sc->msk_hw_id == CHIP_ID_YUKON_FE_P &&
3947 	    sc->msk_hw_rev == CHIP_REV_YU_FE_P_A0) {
3948 		/* Disable dynamic watermark - from Linux. */
3949 		reg = CSR_READ_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_EA));
3950 		reg &= ~0x03;
3951 		CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_EA), reg);
3952 	}
3953 
3954 	/*
3955 	 * Disable Force Sync bit and Alloc bit in Tx RAM interface
3956 	 * arbiter as we don't use Sync Tx queue.
3957 	 */
3958 	CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, TXA_CTRL),
3959 	    TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
3960 	/* Enable the RAM Interface Arbiter. */
3961 	CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, TXA_CTRL), TXA_ENA_ARB);
3962 
3963 	/* Setup RAM buffer. */
3964 	msk_set_rambuffer(sc_if);
3965 
3966 	/* Disable Tx sync Queue. */
3967 	CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txsq, RB_CTRL), RB_RST_SET);
3968 
3969 	/* Setup Tx Queue Bus Memory Interface. */
3970 	CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_CLR_RESET);
3971 	CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_OPER_INIT);
3972 	CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_FIFO_OP_ON);
3973 	CSR_WRITE_2(sc, Q_ADDR(sc_if->msk_txq, Q_WM), MSK_BMU_TX_WM);
3974 	switch (sc->msk_hw_id) {
3975 	case CHIP_ID_YUKON_EC_U:
3976 		if (sc->msk_hw_rev == CHIP_REV_YU_EC_U_A0) {
3977 			/* Fix for Yukon-EC Ultra: set BMU FIFO level */
3978 			CSR_WRITE_2(sc, Q_ADDR(sc_if->msk_txq, Q_AL),
3979 			    MSK_ECU_TXFF_LEV);
3980 		}
3981 		break;
3982 	case CHIP_ID_YUKON_EX:
3983 		/*
3984 		 * Yukon Extreme seems to have silicon bug for
3985 		 * automatic Tx checksum calculation capability.
3986 		 */
3987 		if (sc->msk_hw_rev == CHIP_REV_YU_EX_B0)
3988 			CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_F),
3989 			    F_TX_CHK_AUTO_OFF);
3990 		break;
3991 	}
3992 
3993 	/* Setup Rx Queue Bus Memory Interface. */
3994 	CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_CLR_RESET);
3995 	CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_OPER_INIT);
3996 	CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_FIFO_OP_ON);
3997 	CSR_WRITE_2(sc, Q_ADDR(sc_if->msk_rxq, Q_WM), MSK_BMU_RX_WM);
3998         if (sc->msk_hw_id == CHIP_ID_YUKON_EC_U &&
3999 	    sc->msk_hw_rev >= CHIP_REV_YU_EC_U_A1) {
4000 		/* MAC Rx RAM Read is controlled by hardware. */
4001                 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_F), F_M_RX_RAM_DIS);
4002 	}
4003 
4004 	msk_set_prefetch(sc, sc_if->msk_txq,
4005 	    sc_if->msk_rdata.msk_tx_ring_paddr, MSK_TX_RING_CNT - 1);
4006 	msk_init_tx_ring(sc_if);
4007 
4008 	/* Disable Rx checksum offload and RSS hash. */
4009 	reg = BMU_DIS_RX_RSS_HASH;
4010 	if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0 &&
4011 	    (ifp->if_capenable & IFCAP_RXCSUM) != 0)
4012 		reg |= BMU_ENA_RX_CHKSUM;
4013 	else
4014 		reg |= BMU_DIS_RX_CHKSUM;
4015 	CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), reg);
4016 	if (sc_if->msk_framesize > (MCLBYTES - MSK_RX_BUF_ALIGN)) {
4017 		msk_set_prefetch(sc, sc_if->msk_rxq,
4018 		    sc_if->msk_rdata.msk_jumbo_rx_ring_paddr,
4019 		    MSK_JUMBO_RX_RING_CNT - 1);
4020 		error = msk_init_jumbo_rx_ring(sc_if);
4021 	 } else {
4022 		msk_set_prefetch(sc, sc_if->msk_rxq,
4023 		    sc_if->msk_rdata.msk_rx_ring_paddr,
4024 		    MSK_RX_RING_CNT - 1);
4025 		error = msk_init_rx_ring(sc_if);
4026 	}
4027 	if (error != 0) {
4028 		device_printf(sc_if->msk_if_dev,
4029 		    "initialization failed: no memory for Rx buffers\n");
4030 		msk_stop(sc_if);
4031 		return;
4032 	}
4033 	if (sc->msk_hw_id == CHIP_ID_YUKON_EX ||
4034 	    sc->msk_hw_id == CHIP_ID_YUKON_SUPR) {
4035 		/* Disable flushing of non-ASF packets. */
4036 		CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T),
4037 		    GMF_RX_MACSEC_FLUSH_OFF);
4038 	}
4039 
4040 	/* Configure interrupt handling. */
4041 	if (sc_if->msk_port == MSK_PORT_A) {
4042 		sc->msk_intrmask |= Y2_IS_PORT_A;
4043 		sc->msk_intrhwemask |= Y2_HWE_L1_MASK;
4044 	} else {
4045 		sc->msk_intrmask |= Y2_IS_PORT_B;
4046 		sc->msk_intrhwemask |= Y2_HWE_L2_MASK;
4047 	}
4048 	/* Configure IRQ moderation mask. */
4049 	CSR_WRITE_4(sc, B2_IRQM_MSK, sc->msk_intrmask);
4050 	if (sc->msk_int_holdoff > 0) {
4051 		/* Configure initial IRQ moderation timer value. */
4052 		CSR_WRITE_4(sc, B2_IRQM_INI,
4053 		    MSK_USECS(sc, sc->msk_int_holdoff));
4054 		CSR_WRITE_4(sc, B2_IRQM_VAL,
4055 		    MSK_USECS(sc, sc->msk_int_holdoff));
4056 		/* Start IRQ moderation. */
4057 		CSR_WRITE_1(sc, B2_IRQM_CTRL, TIM_START);
4058 	}
4059 	CSR_WRITE_4(sc, B0_HWE_IMSK, sc->msk_intrhwemask);
4060 	CSR_READ_4(sc, B0_HWE_IMSK);
4061 	CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask);
4062 	CSR_READ_4(sc, B0_IMSK);
4063 
4064 	sc_if->msk_flags &= ~MSK_FLAG_LINK;
4065 	mii_mediachg(mii);
4066 
4067 	ifp->if_drv_flags |= IFF_DRV_RUNNING;
4068 	ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
4069 
4070 	callout_reset(&sc_if->msk_tick_ch, hz, msk_tick, sc_if);
4071 }
4072 
4073 static void
4074 msk_set_rambuffer(struct msk_if_softc *sc_if)
4075 {
4076 	struct msk_softc *sc;
4077 	int ltpp, utpp;
4078 
4079 	sc = sc_if->msk_softc;
4080 	if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) == 0)
4081 		return;
4082 
4083 	/* Setup Rx Queue. */
4084 	CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_RST_CLR);
4085 	CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_START),
4086 	    sc->msk_rxqstart[sc_if->msk_port] / 8);
4087 	CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_END),
4088 	    sc->msk_rxqend[sc_if->msk_port] / 8);
4089 	CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_WP),
4090 	    sc->msk_rxqstart[sc_if->msk_port] / 8);
4091 	CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_RP),
4092 	    sc->msk_rxqstart[sc_if->msk_port] / 8);
4093 
4094 	utpp = (sc->msk_rxqend[sc_if->msk_port] + 1 -
4095 	    sc->msk_rxqstart[sc_if->msk_port] - MSK_RB_ULPP) / 8;
4096 	ltpp = (sc->msk_rxqend[sc_if->msk_port] + 1 -
4097 	    sc->msk_rxqstart[sc_if->msk_port] - MSK_RB_LLPP_B) / 8;
4098 	if (sc->msk_rxqsize < MSK_MIN_RXQ_SIZE)
4099 		ltpp += (MSK_RB_LLPP_B - MSK_RB_LLPP_S) / 8;
4100 	CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_RX_UTPP), utpp);
4101 	CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_RX_LTPP), ltpp);
4102 	/* Set Rx priority(RB_RX_UTHP/RB_RX_LTHP) thresholds? */
4103 
4104 	CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_ENA_OP_MD);
4105 	CSR_READ_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL));
4106 
4107 	/* Setup Tx Queue. */
4108 	CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_RST_CLR);
4109 	CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_START),
4110 	    sc->msk_txqstart[sc_if->msk_port] / 8);
4111 	CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_END),
4112 	    sc->msk_txqend[sc_if->msk_port] / 8);
4113 	CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_WP),
4114 	    sc->msk_txqstart[sc_if->msk_port] / 8);
4115 	CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_RP),
4116 	    sc->msk_txqstart[sc_if->msk_port] / 8);
4117 	/* Enable Store & Forward for Tx side. */
4118 	CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_ENA_STFWD);
4119 	CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_ENA_OP_MD);
4120 	CSR_READ_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL));
4121 }
4122 
4123 static void
4124 msk_set_prefetch(struct msk_softc *sc, int qaddr, bus_addr_t addr,
4125     uint32_t count)
4126 {
4127 
4128 	/* Reset the prefetch unit. */
4129 	CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG),
4130 	    PREF_UNIT_RST_SET);
4131 	CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG),
4132 	    PREF_UNIT_RST_CLR);
4133 	/* Set LE base address. */
4134 	CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_ADDR_LOW_REG),
4135 	    MSK_ADDR_LO(addr));
4136 	CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_ADDR_HI_REG),
4137 	    MSK_ADDR_HI(addr));
4138 	/* Set the list last index. */
4139 	CSR_WRITE_2(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_LAST_IDX_REG),
4140 	    count);
4141 	/* Turn on prefetch unit. */
4142 	CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG),
4143 	    PREF_UNIT_OP_ON);
4144 	/* Dummy read to ensure write. */
4145 	CSR_READ_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG));
4146 }
4147 
4148 static void
4149 msk_stop(struct msk_if_softc *sc_if)
4150 {
4151 	struct msk_softc *sc;
4152 	struct msk_txdesc *txd;
4153 	struct msk_rxdesc *rxd;
4154 	struct msk_rxdesc *jrxd;
4155 	struct ifnet *ifp;
4156 	uint32_t val;
4157 	int i;
4158 
4159 	MSK_IF_LOCK_ASSERT(sc_if);
4160 	sc = sc_if->msk_softc;
4161 	ifp = sc_if->msk_ifp;
4162 
4163 	callout_stop(&sc_if->msk_tick_ch);
4164 	sc_if->msk_watchdog_timer = 0;
4165 
4166 	/* Disable interrupts. */
4167 	if (sc_if->msk_port == MSK_PORT_A) {
4168 		sc->msk_intrmask &= ~Y2_IS_PORT_A;
4169 		sc->msk_intrhwemask &= ~Y2_HWE_L1_MASK;
4170 	} else {
4171 		sc->msk_intrmask &= ~Y2_IS_PORT_B;
4172 		sc->msk_intrhwemask &= ~Y2_HWE_L2_MASK;
4173 	}
4174 	CSR_WRITE_4(sc, B0_HWE_IMSK, sc->msk_intrhwemask);
4175 	CSR_READ_4(sc, B0_HWE_IMSK);
4176 	CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask);
4177 	CSR_READ_4(sc, B0_IMSK);
4178 
4179 	/* Disable Tx/Rx MAC. */
4180 	val = GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL);
4181 	val &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
4182 	GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, val);
4183 	/* Read again to ensure writing. */
4184 	GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL);
4185 	/* Update stats and clear counters. */
4186 	msk_stats_update(sc_if);
4187 
4188 	/* Stop Tx BMU. */
4189 	CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_STOP);
4190 	val = CSR_READ_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR));
4191 	for (i = 0; i < MSK_TIMEOUT; i++) {
4192 		if ((val & (BMU_STOP | BMU_IDLE)) == 0) {
4193 			CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR),
4194 			    BMU_STOP);
4195 			val = CSR_READ_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR));
4196 		} else
4197 			break;
4198 		DELAY(1);
4199 	}
4200 	if (i == MSK_TIMEOUT)
4201 		device_printf(sc_if->msk_if_dev, "Tx BMU stop failed\n");
4202 	CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL),
4203 	    RB_RST_SET | RB_DIS_OP_MD);
4204 
4205 	/* Disable all GMAC interrupt. */
4206 	CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_MSK), 0);
4207 	/* Disable PHY interrupt. */
4208 	msk_phy_writereg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_MASK, 0);
4209 
4210 	/* Disable the RAM Interface Arbiter. */
4211 	CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, TXA_CTRL), TXA_DIS_ARB);
4212 
4213 	/* Reset the PCI FIFO of the async Tx queue */
4214 	CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR),
4215 	    BMU_RST_SET | BMU_FIFO_RST);
4216 
4217 	/* Reset the Tx prefetch units. */
4218 	CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(sc_if->msk_txq, PREF_UNIT_CTRL_REG),
4219 	    PREF_UNIT_RST_SET);
4220 
4221 	/* Reset the RAM Buffer async Tx queue. */
4222 	CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_RST_SET);
4223 
4224 	/* Reset Tx MAC FIFO. */
4225 	CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_RST_SET);
4226 	/* Set Pause Off. */
4227 	CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_PAUSE_OFF);
4228 
4229 	/*
4230 	 * The Rx Stop command will not work for Yukon-2 if the BMU does not
4231 	 * reach the end of packet and since we can't make sure that we have
4232 	 * incoming data, we must reset the BMU while it is not during a DMA
4233 	 * transfer. Since it is possible that the Rx path is still active,
4234 	 * the Rx RAM buffer will be stopped first, so any possible incoming
4235 	 * data will not trigger a DMA. After the RAM buffer is stopped, the
4236 	 * BMU is polled until any DMA in progress is ended and only then it
4237 	 * will be reset.
4238 	 */
4239 
4240 	/* Disable the RAM Buffer receive queue. */
4241 	CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_DIS_OP_MD);
4242 	for (i = 0; i < MSK_TIMEOUT; i++) {
4243 		if (CSR_READ_1(sc, RB_ADDR(sc_if->msk_rxq, Q_RSL)) ==
4244 		    CSR_READ_1(sc, RB_ADDR(sc_if->msk_rxq, Q_RL)))
4245 			break;
4246 		DELAY(1);
4247 	}
4248 	if (i == MSK_TIMEOUT)
4249 		device_printf(sc_if->msk_if_dev, "Rx BMU stop failed\n");
4250 	CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR),
4251 	    BMU_RST_SET | BMU_FIFO_RST);
4252 	/* Reset the Rx prefetch unit. */
4253 	CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_CTRL_REG),
4254 	    PREF_UNIT_RST_SET);
4255 	/* Reset the RAM Buffer receive queue. */
4256 	CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_RST_SET);
4257 	/* Reset Rx MAC FIFO. */
4258 	CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), GMF_RST_SET);
4259 
4260 	/* Free Rx and Tx mbufs still in the queues. */
4261 	for (i = 0; i < MSK_RX_RING_CNT; i++) {
4262 		rxd = &sc_if->msk_cdata.msk_rxdesc[i];
4263 		if (rxd->rx_m != NULL) {
4264 			bus_dmamap_sync(sc_if->msk_cdata.msk_rx_tag,
4265 			    rxd->rx_dmamap, BUS_DMASYNC_POSTREAD);
4266 			bus_dmamap_unload(sc_if->msk_cdata.msk_rx_tag,
4267 			    rxd->rx_dmamap);
4268 			m_freem(rxd->rx_m);
4269 			rxd->rx_m = NULL;
4270 		}
4271 	}
4272 	for (i = 0; i < MSK_JUMBO_RX_RING_CNT; i++) {
4273 		jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[i];
4274 		if (jrxd->rx_m != NULL) {
4275 			bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_tag,
4276 			    jrxd->rx_dmamap, BUS_DMASYNC_POSTREAD);
4277 			bus_dmamap_unload(sc_if->msk_cdata.msk_jumbo_rx_tag,
4278 			    jrxd->rx_dmamap);
4279 			m_freem(jrxd->rx_m);
4280 			jrxd->rx_m = NULL;
4281 		}
4282 	}
4283 	for (i = 0; i < MSK_TX_RING_CNT; i++) {
4284 		txd = &sc_if->msk_cdata.msk_txdesc[i];
4285 		if (txd->tx_m != NULL) {
4286 			bus_dmamap_sync(sc_if->msk_cdata.msk_tx_tag,
4287 			    txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
4288 			bus_dmamap_unload(sc_if->msk_cdata.msk_tx_tag,
4289 			    txd->tx_dmamap);
4290 			m_freem(txd->tx_m);
4291 			txd->tx_m = NULL;
4292 		}
4293 	}
4294 
4295 	/*
4296 	 * Mark the interface down.
4297 	 */
4298 	ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
4299 	sc_if->msk_flags &= ~MSK_FLAG_LINK;
4300 }
4301 
4302 /*
4303  * When GM_PAR_MIB_CLR bit of GM_PHY_ADDR is set, reading lower
4304  * counter clears high 16 bits of the counter such that accessing
4305  * lower 16 bits should be the last operation.
4306  */
4307 #define	MSK_READ_MIB32(x, y)					\
4308 	(((uint32_t)GMAC_READ_2(sc, x, (y) + 4)) << 16) +	\
4309 	(uint32_t)GMAC_READ_2(sc, x, y)
4310 #define	MSK_READ_MIB64(x, y)					\
4311 	(((uint64_t)MSK_READ_MIB32(x, (y) + 8)) << 32) +	\
4312 	(uint64_t)MSK_READ_MIB32(x, y)
4313 
4314 static void
4315 msk_stats_clear(struct msk_if_softc *sc_if)
4316 {
4317 	struct msk_softc *sc;
4318 	uint32_t reg;
4319 	uint16_t gmac;
4320 	int i;
4321 
4322 	MSK_IF_LOCK_ASSERT(sc_if);
4323 
4324 	sc = sc_if->msk_softc;
4325 	/* Set MIB Clear Counter Mode. */
4326 	gmac = GMAC_READ_2(sc, sc_if->msk_port, GM_PHY_ADDR);
4327 	GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac | GM_PAR_MIB_CLR);
4328 	/* Read all MIB Counters with Clear Mode set. */
4329 	for (i = GM_RXF_UC_OK; i <= GM_TXE_FIFO_UR; i += sizeof(uint32_t))
4330 		reg = MSK_READ_MIB32(sc_if->msk_port, i);
4331 	/* Clear MIB Clear Counter Mode. */
4332 	gmac &= ~GM_PAR_MIB_CLR;
4333 	GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac);
4334 }
4335 
4336 static void
4337 msk_stats_update(struct msk_if_softc *sc_if)
4338 {
4339 	struct msk_softc *sc;
4340 	struct ifnet *ifp;
4341 	struct msk_hw_stats *stats;
4342 	uint16_t gmac;
4343 	uint32_t reg;
4344 
4345 	MSK_IF_LOCK_ASSERT(sc_if);
4346 
4347 	ifp = sc_if->msk_ifp;
4348 	if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
4349 		return;
4350 	sc = sc_if->msk_softc;
4351 	stats = &sc_if->msk_stats;
4352 	/* Set MIB Clear Counter Mode. */
4353 	gmac = GMAC_READ_2(sc, sc_if->msk_port, GM_PHY_ADDR);
4354 	GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac | GM_PAR_MIB_CLR);
4355 
4356 	/* Rx stats. */
4357 	stats->rx_ucast_frames +=
4358 	    MSK_READ_MIB32(sc_if->msk_port, GM_RXF_UC_OK);
4359 	stats->rx_bcast_frames +=
4360 	    MSK_READ_MIB32(sc_if->msk_port, GM_RXF_BC_OK);
4361 	stats->rx_pause_frames +=
4362 	    MSK_READ_MIB32(sc_if->msk_port, GM_RXF_MPAUSE);
4363 	stats->rx_mcast_frames +=
4364 	    MSK_READ_MIB32(sc_if->msk_port, GM_RXF_MC_OK);
4365 	stats->rx_crc_errs +=
4366 	    MSK_READ_MIB32(sc_if->msk_port, GM_RXF_FCS_ERR);
4367 	reg = MSK_READ_MIB32(sc_if->msk_port, GM_RXF_SPARE1);
4368 	stats->rx_good_octets +=
4369 	    MSK_READ_MIB64(sc_if->msk_port, GM_RXO_OK_LO);
4370 	stats->rx_bad_octets +=
4371 	    MSK_READ_MIB64(sc_if->msk_port, GM_RXO_ERR_LO);
4372 	stats->rx_runts +=
4373 	    MSK_READ_MIB32(sc_if->msk_port, GM_RXF_SHT);
4374 	stats->rx_runt_errs +=
4375 	    MSK_READ_MIB32(sc_if->msk_port, GM_RXE_FRAG);
4376 	stats->rx_pkts_64 +=
4377 	    MSK_READ_MIB32(sc_if->msk_port, GM_RXF_64B);
4378 	stats->rx_pkts_65_127 +=
4379 	    MSK_READ_MIB32(sc_if->msk_port, GM_RXF_127B);
4380 	stats->rx_pkts_128_255 +=
4381 	    MSK_READ_MIB32(sc_if->msk_port, GM_RXF_255B);
4382 	stats->rx_pkts_256_511 +=
4383 	    MSK_READ_MIB32(sc_if->msk_port, GM_RXF_511B);
4384 	stats->rx_pkts_512_1023 +=
4385 	    MSK_READ_MIB32(sc_if->msk_port, GM_RXF_1023B);
4386 	stats->rx_pkts_1024_1518 +=
4387 	    MSK_READ_MIB32(sc_if->msk_port, GM_RXF_1518B);
4388 	stats->rx_pkts_1519_max +=
4389 	    MSK_READ_MIB32(sc_if->msk_port, GM_RXF_MAX_SZ);
4390 	stats->rx_pkts_too_long +=
4391 	    MSK_READ_MIB32(sc_if->msk_port, GM_RXF_LNG_ERR);
4392 	stats->rx_pkts_jabbers +=
4393 	    MSK_READ_MIB32(sc_if->msk_port, GM_RXF_JAB_PKT);
4394 	reg = MSK_READ_MIB32(sc_if->msk_port, GM_RXF_SPARE2);
4395 	stats->rx_fifo_oflows +=
4396 	    MSK_READ_MIB32(sc_if->msk_port, GM_RXE_FIFO_OV);
4397 	reg = MSK_READ_MIB32(sc_if->msk_port, GM_RXF_SPARE3);
4398 
4399 	/* Tx stats. */
4400 	stats->tx_ucast_frames +=
4401 	    MSK_READ_MIB32(sc_if->msk_port, GM_TXF_UC_OK);
4402 	stats->tx_bcast_frames +=
4403 	    MSK_READ_MIB32(sc_if->msk_port, GM_TXF_BC_OK);
4404 	stats->tx_pause_frames +=
4405 	    MSK_READ_MIB32(sc_if->msk_port, GM_TXF_MPAUSE);
4406 	stats->tx_mcast_frames +=
4407 	    MSK_READ_MIB32(sc_if->msk_port, GM_TXF_MC_OK);
4408 	stats->tx_octets +=
4409 	    MSK_READ_MIB64(sc_if->msk_port, GM_TXO_OK_LO);
4410 	stats->tx_pkts_64 +=
4411 	    MSK_READ_MIB32(sc_if->msk_port, GM_TXF_64B);
4412 	stats->tx_pkts_65_127 +=
4413 	    MSK_READ_MIB32(sc_if->msk_port, GM_TXF_127B);
4414 	stats->tx_pkts_128_255 +=
4415 	    MSK_READ_MIB32(sc_if->msk_port, GM_TXF_255B);
4416 	stats->tx_pkts_256_511 +=
4417 	    MSK_READ_MIB32(sc_if->msk_port, GM_TXF_511B);
4418 	stats->tx_pkts_512_1023 +=
4419 	    MSK_READ_MIB32(sc_if->msk_port, GM_TXF_1023B);
4420 	stats->tx_pkts_1024_1518 +=
4421 	    MSK_READ_MIB32(sc_if->msk_port, GM_TXF_1518B);
4422 	stats->tx_pkts_1519_max +=
4423 	    MSK_READ_MIB32(sc_if->msk_port, GM_TXF_MAX_SZ);
4424 	reg = MSK_READ_MIB32(sc_if->msk_port, GM_TXF_SPARE1);
4425 	stats->tx_colls +=
4426 	    MSK_READ_MIB32(sc_if->msk_port, GM_TXF_COL);
4427 	stats->tx_late_colls +=
4428 	    MSK_READ_MIB32(sc_if->msk_port, GM_TXF_LAT_COL);
4429 	stats->tx_excess_colls +=
4430 	    MSK_READ_MIB32(sc_if->msk_port, GM_TXF_ABO_COL);
4431 	stats->tx_multi_colls +=
4432 	    MSK_READ_MIB32(sc_if->msk_port, GM_TXF_MUL_COL);
4433 	stats->tx_single_colls +=
4434 	    MSK_READ_MIB32(sc_if->msk_port, GM_TXF_SNG_COL);
4435 	stats->tx_underflows +=
4436 	    MSK_READ_MIB32(sc_if->msk_port, GM_TXE_FIFO_UR);
4437 	/* Clear MIB Clear Counter Mode. */
4438 	gmac &= ~GM_PAR_MIB_CLR;
4439 	GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac);
4440 }
4441 
4442 static int
4443 msk_sysctl_stat32(SYSCTL_HANDLER_ARGS)
4444 {
4445 	struct msk_softc *sc;
4446 	struct msk_if_softc *sc_if;
4447 	uint32_t result, *stat;
4448 	int off;
4449 
4450 	sc_if = (struct msk_if_softc *)arg1;
4451 	sc = sc_if->msk_softc;
4452 	off = arg2;
4453 	stat = (uint32_t *)((uint8_t *)&sc_if->msk_stats + off);
4454 
4455 	MSK_IF_LOCK(sc_if);
4456 	result = MSK_READ_MIB32(sc_if->msk_port, GM_MIB_CNT_BASE + off * 2);
4457 	result += *stat;
4458 	MSK_IF_UNLOCK(sc_if);
4459 
4460 	return (sysctl_handle_int(oidp, &result, 0, req));
4461 }
4462 
4463 static int
4464 msk_sysctl_stat64(SYSCTL_HANDLER_ARGS)
4465 {
4466 	struct msk_softc *sc;
4467 	struct msk_if_softc *sc_if;
4468 	uint64_t result, *stat;
4469 	int off;
4470 
4471 	sc_if = (struct msk_if_softc *)arg1;
4472 	sc = sc_if->msk_softc;
4473 	off = arg2;
4474 	stat = (uint64_t *)((uint8_t *)&sc_if->msk_stats + off);
4475 
4476 	MSK_IF_LOCK(sc_if);
4477 	result = MSK_READ_MIB64(sc_if->msk_port, GM_MIB_CNT_BASE + off * 2);
4478 	result += *stat;
4479 	MSK_IF_UNLOCK(sc_if);
4480 
4481 	return (sysctl_handle_64(oidp, &result, 0, req));
4482 }
4483 
4484 #undef MSK_READ_MIB32
4485 #undef MSK_READ_MIB64
4486 
4487 #define MSK_SYSCTL_STAT32(sc, c, o, p, n, d) 				\
4488 	SYSCTL_ADD_PROC(c, p, OID_AUTO, o, CTLTYPE_UINT | CTLFLAG_RD, 	\
4489 	    sc, offsetof(struct msk_hw_stats, n), msk_sysctl_stat32,	\
4490 	    "IU", d)
4491 #define MSK_SYSCTL_STAT64(sc, c, o, p, n, d) 				\
4492 	SYSCTL_ADD_PROC(c, p, OID_AUTO, o, CTLTYPE_U64 | CTLFLAG_RD, 	\
4493 	    sc, offsetof(struct msk_hw_stats, n), msk_sysctl_stat64,	\
4494 	    "QU", d)
4495 
4496 static void
4497 msk_sysctl_node(struct msk_if_softc *sc_if)
4498 {
4499 	struct sysctl_ctx_list *ctx;
4500 	struct sysctl_oid_list *child, *schild;
4501 	struct sysctl_oid *tree;
4502 
4503 	ctx = device_get_sysctl_ctx(sc_if->msk_if_dev);
4504 	child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc_if->msk_if_dev));
4505 
4506 	tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD,
4507 	    NULL, "MSK Statistics");
4508 	schild = child = SYSCTL_CHILDREN(tree);
4509 	tree = SYSCTL_ADD_NODE(ctx, schild, OID_AUTO, "rx", CTLFLAG_RD,
4510 	    NULL, "MSK RX Statistics");
4511 	child = SYSCTL_CHILDREN(tree);
4512 	MSK_SYSCTL_STAT32(sc_if, ctx, "ucast_frames",
4513 	    child, rx_ucast_frames, "Good unicast frames");
4514 	MSK_SYSCTL_STAT32(sc_if, ctx, "bcast_frames",
4515 	    child, rx_bcast_frames, "Good broadcast frames");
4516 	MSK_SYSCTL_STAT32(sc_if, ctx, "pause_frames",
4517 	    child, rx_pause_frames, "Pause frames");
4518 	MSK_SYSCTL_STAT32(sc_if, ctx, "mcast_frames",
4519 	    child, rx_mcast_frames, "Multicast frames");
4520 	MSK_SYSCTL_STAT32(sc_if, ctx, "crc_errs",
4521 	    child, rx_crc_errs, "CRC errors");
4522 	MSK_SYSCTL_STAT64(sc_if, ctx, "good_octets",
4523 	    child, rx_good_octets, "Good octets");
4524 	MSK_SYSCTL_STAT64(sc_if, ctx, "bad_octets",
4525 	    child, rx_bad_octets, "Bad octets");
4526 	MSK_SYSCTL_STAT32(sc_if, ctx, "frames_64",
4527 	    child, rx_pkts_64, "64 bytes frames");
4528 	MSK_SYSCTL_STAT32(sc_if, ctx, "frames_65_127",
4529 	    child, rx_pkts_65_127, "65 to 127 bytes frames");
4530 	MSK_SYSCTL_STAT32(sc_if, ctx, "frames_128_255",
4531 	    child, rx_pkts_128_255, "128 to 255 bytes frames");
4532 	MSK_SYSCTL_STAT32(sc_if, ctx, "frames_256_511",
4533 	    child, rx_pkts_256_511, "256 to 511 bytes frames");
4534 	MSK_SYSCTL_STAT32(sc_if, ctx, "frames_512_1023",
4535 	    child, rx_pkts_512_1023, "512 to 1023 bytes frames");
4536 	MSK_SYSCTL_STAT32(sc_if, ctx, "frames_1024_1518",
4537 	    child, rx_pkts_1024_1518, "1024 to 1518 bytes frames");
4538 	MSK_SYSCTL_STAT32(sc_if, ctx, "frames_1519_max",
4539 	    child, rx_pkts_1519_max, "1519 to max frames");
4540 	MSK_SYSCTL_STAT32(sc_if, ctx, "frames_too_long",
4541 	    child, rx_pkts_too_long, "frames too long");
4542 	MSK_SYSCTL_STAT32(sc_if, ctx, "jabbers",
4543 	    child, rx_pkts_jabbers, "Jabber errors");
4544 	MSK_SYSCTL_STAT32(sc_if, ctx, "overflows",
4545 	    child, rx_fifo_oflows, "FIFO overflows");
4546 
4547 	tree = SYSCTL_ADD_NODE(ctx, schild, OID_AUTO, "tx", CTLFLAG_RD,
4548 	    NULL, "MSK TX Statistics");
4549 	child = SYSCTL_CHILDREN(tree);
4550 	MSK_SYSCTL_STAT32(sc_if, ctx, "ucast_frames",
4551 	    child, tx_ucast_frames, "Unicast frames");
4552 	MSK_SYSCTL_STAT32(sc_if, ctx, "bcast_frames",
4553 	    child, tx_bcast_frames, "Broadcast frames");
4554 	MSK_SYSCTL_STAT32(sc_if, ctx, "pause_frames",
4555 	    child, tx_pause_frames, "Pause frames");
4556 	MSK_SYSCTL_STAT32(sc_if, ctx, "mcast_frames",
4557 	    child, tx_mcast_frames, "Multicast frames");
4558 	MSK_SYSCTL_STAT64(sc_if, ctx, "octets",
4559 	    child, tx_octets, "Octets");
4560 	MSK_SYSCTL_STAT32(sc_if, ctx, "frames_64",
4561 	    child, tx_pkts_64, "64 bytes frames");
4562 	MSK_SYSCTL_STAT32(sc_if, ctx, "frames_65_127",
4563 	    child, tx_pkts_65_127, "65 to 127 bytes frames");
4564 	MSK_SYSCTL_STAT32(sc_if, ctx, "frames_128_255",
4565 	    child, tx_pkts_128_255, "128 to 255 bytes frames");
4566 	MSK_SYSCTL_STAT32(sc_if, ctx, "frames_256_511",
4567 	    child, tx_pkts_256_511, "256 to 511 bytes frames");
4568 	MSK_SYSCTL_STAT32(sc_if, ctx, "frames_512_1023",
4569 	    child, tx_pkts_512_1023, "512 to 1023 bytes frames");
4570 	MSK_SYSCTL_STAT32(sc_if, ctx, "frames_1024_1518",
4571 	    child, tx_pkts_1024_1518, "1024 to 1518 bytes frames");
4572 	MSK_SYSCTL_STAT32(sc_if, ctx, "frames_1519_max",
4573 	    child, tx_pkts_1519_max, "1519 to max frames");
4574 	MSK_SYSCTL_STAT32(sc_if, ctx, "colls",
4575 	    child, tx_colls, "Collisions");
4576 	MSK_SYSCTL_STAT32(sc_if, ctx, "late_colls",
4577 	    child, tx_late_colls, "Late collisions");
4578 	MSK_SYSCTL_STAT32(sc_if, ctx, "excess_colls",
4579 	    child, tx_excess_colls, "Excessive collisions");
4580 	MSK_SYSCTL_STAT32(sc_if, ctx, "multi_colls",
4581 	    child, tx_multi_colls, "Multiple collisions");
4582 	MSK_SYSCTL_STAT32(sc_if, ctx, "single_colls",
4583 	    child, tx_single_colls, "Single collisions");
4584 	MSK_SYSCTL_STAT32(sc_if, ctx, "underflows",
4585 	    child, tx_underflows, "FIFO underflows");
4586 }
4587 
4588 #undef MSK_SYSCTL_STAT32
4589 #undef MSK_SYSCTL_STAT64
4590 
4591 static int
4592 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high)
4593 {
4594 	int error, value;
4595 
4596 	if (!arg1)
4597 		return (EINVAL);
4598 	value = *(int *)arg1;
4599 	error = sysctl_handle_int(oidp, &value, 0, req);
4600 	if (error || !req->newptr)
4601 		return (error);
4602 	if (value < low || value > high)
4603 		return (EINVAL);
4604 	*(int *)arg1 = value;
4605 
4606 	return (0);
4607 }
4608 
4609 static int
4610 sysctl_hw_msk_proc_limit(SYSCTL_HANDLER_ARGS)
4611 {
4612 
4613 	return (sysctl_int_range(oidp, arg1, arg2, req, MSK_PROC_MIN,
4614 	    MSK_PROC_MAX));
4615 }
4616