1 /****************************************************************************** 2 * 3 * Name : sky2.c 4 * Project: Gigabit Ethernet Driver for FreeBSD 5.x/6.x 5 * Version: $Revision: 1.23 $ 6 * Date : $Date: 2005/12/22 09:04:11 $ 7 * Purpose: Main driver source file 8 * 9 *****************************************************************************/ 10 11 /****************************************************************************** 12 * 13 * LICENSE: 14 * Copyright (C) Marvell International Ltd. and/or its affiliates 15 * 16 * The computer program files contained in this folder ("Files") 17 * are provided to you under the BSD-type license terms provided 18 * below, and any use of such Files and any derivative works 19 * thereof created by you shall be governed by the following terms 20 * and conditions: 21 * 22 * - Redistributions of source code must retain the above copyright 23 * notice, this list of conditions and the following disclaimer. 24 * - Redistributions in binary form must reproduce the above 25 * copyright notice, this list of conditions and the following 26 * disclaimer in the documentation and/or other materials provided 27 * with the distribution. 28 * - Neither the name of Marvell nor the names of its contributors 29 * may be used to endorse or promote products derived from this 30 * software without specific prior written permission. 31 * 32 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 33 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 34 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 35 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 36 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 37 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 38 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 39 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 40 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 41 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 42 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED 43 * OF THE POSSIBILITY OF SUCH DAMAGE. 44 * /LICENSE 45 * 46 *****************************************************************************/ 47 48 /*- 49 * Copyright (c) 1997, 1998, 1999, 2000 50 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 51 * 52 * Redistribution and use in source and binary forms, with or without 53 * modification, are permitted provided that the following conditions 54 * are met: 55 * 1. Redistributions of source code must retain the above copyright 56 * notice, this list of conditions and the following disclaimer. 57 * 2. Redistributions in binary form must reproduce the above copyright 58 * notice, this list of conditions and the following disclaimer in the 59 * documentation and/or other materials provided with the distribution. 60 * 3. All advertising materials mentioning features or use of this software 61 * must display the following acknowledgement: 62 * This product includes software developed by Bill Paul. 63 * 4. Neither the name of the author nor the names of any co-contributors 64 * may be used to endorse or promote products derived from this software 65 * without specific prior written permission. 66 * 67 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 68 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 69 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 70 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 71 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 72 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 73 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 74 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 75 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 76 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 77 * THE POSSIBILITY OF SUCH DAMAGE. 78 */ 79 /*- 80 * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu> 81 * 82 * Permission to use, copy, modify, and distribute this software for any 83 * purpose with or without fee is hereby granted, provided that the above 84 * copyright notice and this permission notice appear in all copies. 85 * 86 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 87 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 88 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 89 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 90 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 91 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 92 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 93 */ 94 95 /* 96 * Device driver for the Marvell Yukon II Ethernet controller. 97 * Due to lack of documentation, this driver is based on the code from 98 * sk(4) and Marvell's myk(4) driver for FreeBSD 5.x. 99 */ 100 101 #include <sys/cdefs.h> 102 __FBSDID("$FreeBSD$"); 103 104 #include <sys/param.h> 105 #include <sys/systm.h> 106 #include <sys/bus.h> 107 #include <sys/endian.h> 108 #include <sys/mbuf.h> 109 #include <sys/malloc.h> 110 #include <sys/kernel.h> 111 #include <sys/module.h> 112 #include <sys/socket.h> 113 #include <sys/sockio.h> 114 #include <sys/queue.h> 115 #include <sys/sysctl.h> 116 117 #include <net/bpf.h> 118 #include <net/ethernet.h> 119 #include <net/if.h> 120 #include <net/if_arp.h> 121 #include <net/if_dl.h> 122 #include <net/if_media.h> 123 #include <net/if_types.h> 124 #include <net/if_vlan_var.h> 125 126 #include <netinet/in.h> 127 #include <netinet/in_systm.h> 128 #include <netinet/ip.h> 129 #include <netinet/tcp.h> 130 #include <netinet/udp.h> 131 132 #include <machine/bus.h> 133 #include <machine/in_cksum.h> 134 #include <machine/resource.h> 135 #include <sys/rman.h> 136 137 #include <dev/mii/mii.h> 138 #include <dev/mii/miivar.h> 139 140 #include <dev/pci/pcireg.h> 141 #include <dev/pci/pcivar.h> 142 143 #include <dev/msk/if_mskreg.h> 144 145 MODULE_DEPEND(msk, pci, 1, 1, 1); 146 MODULE_DEPEND(msk, ether, 1, 1, 1); 147 MODULE_DEPEND(msk, miibus, 1, 1, 1); 148 149 /* "device miibus" required. See GENERIC if you get errors here. */ 150 #include "miibus_if.h" 151 152 /* Tunables. */ 153 static int msi_disable = 0; 154 TUNABLE_INT("hw.msk.msi_disable", &msi_disable); 155 static int legacy_intr = 0; 156 TUNABLE_INT("hw.msk.legacy_intr", &legacy_intr); 157 static int jumbo_disable = 0; 158 TUNABLE_INT("hw.msk.jumbo_disable", &jumbo_disable); 159 160 #define MSK_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 161 162 /* 163 * Devices supported by this driver. 164 */ 165 static struct msk_product { 166 uint16_t msk_vendorid; 167 uint16_t msk_deviceid; 168 const char *msk_name; 169 } msk_products[] = { 170 { VENDORID_SK, DEVICEID_SK_YUKON2, 171 "SK-9Sxx Gigabit Ethernet" }, 172 { VENDORID_SK, DEVICEID_SK_YUKON2_EXPR, 173 "SK-9Exx Gigabit Ethernet"}, 174 { VENDORID_MARVELL, DEVICEID_MRVL_8021CU, 175 "Marvell Yukon 88E8021CU Gigabit Ethernet" }, 176 { VENDORID_MARVELL, DEVICEID_MRVL_8021X, 177 "Marvell Yukon 88E8021 SX/LX Gigabit Ethernet" }, 178 { VENDORID_MARVELL, DEVICEID_MRVL_8022CU, 179 "Marvell Yukon 88E8022CU Gigabit Ethernet" }, 180 { VENDORID_MARVELL, DEVICEID_MRVL_8022X, 181 "Marvell Yukon 88E8022 SX/LX Gigabit Ethernet" }, 182 { VENDORID_MARVELL, DEVICEID_MRVL_8061CU, 183 "Marvell Yukon 88E8061CU Gigabit Ethernet" }, 184 { VENDORID_MARVELL, DEVICEID_MRVL_8061X, 185 "Marvell Yukon 88E8061 SX/LX Gigabit Ethernet" }, 186 { VENDORID_MARVELL, DEVICEID_MRVL_8062CU, 187 "Marvell Yukon 88E8062CU Gigabit Ethernet" }, 188 { VENDORID_MARVELL, DEVICEID_MRVL_8062X, 189 "Marvell Yukon 88E8062 SX/LX Gigabit Ethernet" }, 190 { VENDORID_MARVELL, DEVICEID_MRVL_8035, 191 "Marvell Yukon 88E8035 Fast Ethernet" }, 192 { VENDORID_MARVELL, DEVICEID_MRVL_8036, 193 "Marvell Yukon 88E8036 Fast Ethernet" }, 194 { VENDORID_MARVELL, DEVICEID_MRVL_8038, 195 "Marvell Yukon 88E8038 Fast Ethernet" }, 196 { VENDORID_MARVELL, DEVICEID_MRVL_8039, 197 "Marvell Yukon 88E8039 Fast Ethernet" }, 198 { VENDORID_MARVELL, DEVICEID_MRVL_8040, 199 "Marvell Yukon 88E8040 Fast Ethernet" }, 200 { VENDORID_MARVELL, DEVICEID_MRVL_8040T, 201 "Marvell Yukon 88E8040T Fast Ethernet" }, 202 { VENDORID_MARVELL, DEVICEID_MRVL_8042, 203 "Marvell Yukon 88E8042 Fast Ethernet" }, 204 { VENDORID_MARVELL, DEVICEID_MRVL_8048, 205 "Marvell Yukon 88E8048 Fast Ethernet" }, 206 { VENDORID_MARVELL, DEVICEID_MRVL_4361, 207 "Marvell Yukon 88E8050 Gigabit Ethernet" }, 208 { VENDORID_MARVELL, DEVICEID_MRVL_4360, 209 "Marvell Yukon 88E8052 Gigabit Ethernet" }, 210 { VENDORID_MARVELL, DEVICEID_MRVL_4362, 211 "Marvell Yukon 88E8053 Gigabit Ethernet" }, 212 { VENDORID_MARVELL, DEVICEID_MRVL_4363, 213 "Marvell Yukon 88E8055 Gigabit Ethernet" }, 214 { VENDORID_MARVELL, DEVICEID_MRVL_4364, 215 "Marvell Yukon 88E8056 Gigabit Ethernet" }, 216 { VENDORID_MARVELL, DEVICEID_MRVL_4365, 217 "Marvell Yukon 88E8070 Gigabit Ethernet" }, 218 { VENDORID_MARVELL, DEVICEID_MRVL_436A, 219 "Marvell Yukon 88E8058 Gigabit Ethernet" }, 220 { VENDORID_MARVELL, DEVICEID_MRVL_436B, 221 "Marvell Yukon 88E8071 Gigabit Ethernet" }, 222 { VENDORID_MARVELL, DEVICEID_MRVL_436C, 223 "Marvell Yukon 88E8072 Gigabit Ethernet" }, 224 { VENDORID_MARVELL, DEVICEID_MRVL_4380, 225 "Marvell Yukon 88E8057 Gigabit Ethernet" }, 226 { VENDORID_DLINK, DEVICEID_DLINK_DGE550SX, 227 "D-Link 550SX Gigabit Ethernet" }, 228 { VENDORID_DLINK, DEVICEID_DLINK_DGE560SX, 229 "D-Link 560SX Gigabit Ethernet" }, 230 { VENDORID_DLINK, DEVICEID_DLINK_DGE560T, 231 "D-Link 560T Gigabit Ethernet" } 232 }; 233 234 static const char *model_name[] = { 235 "Yukon XL", 236 "Yukon EC Ultra", 237 "Yukon EX", 238 "Yukon EC", 239 "Yukon FE", 240 "Yukon FE+", 241 "Yukon Supreme", 242 "Yukon Ultra 2" 243 }; 244 245 static int mskc_probe(device_t); 246 static int mskc_attach(device_t); 247 static int mskc_detach(device_t); 248 static int mskc_shutdown(device_t); 249 static int mskc_setup_rambuffer(struct msk_softc *); 250 static int mskc_suspend(device_t); 251 static int mskc_resume(device_t); 252 static void mskc_reset(struct msk_softc *); 253 254 static int msk_probe(device_t); 255 static int msk_attach(device_t); 256 static int msk_detach(device_t); 257 258 static void msk_tick(void *); 259 static void msk_intr(void *); 260 static void msk_intr_phy(struct msk_if_softc *); 261 static void msk_intr_gmac(struct msk_if_softc *); 262 static __inline void msk_rxput(struct msk_if_softc *); 263 static int msk_handle_events(struct msk_softc *); 264 static void msk_handle_hwerr(struct msk_if_softc *, uint32_t); 265 static void msk_intr_hwerr(struct msk_softc *); 266 #ifndef __NO_STRICT_ALIGNMENT 267 static __inline void msk_fixup_rx(struct mbuf *); 268 #endif 269 static __inline void msk_rxcsum(struct msk_if_softc *, uint32_t, struct mbuf *); 270 static void msk_rxeof(struct msk_if_softc *, uint32_t, uint32_t, int); 271 static void msk_jumbo_rxeof(struct msk_if_softc *, uint32_t, uint32_t, int); 272 static void msk_txeof(struct msk_if_softc *, int); 273 static int msk_encap(struct msk_if_softc *, struct mbuf **); 274 static void msk_start(struct ifnet *); 275 static void msk_start_locked(struct ifnet *); 276 static int msk_ioctl(struct ifnet *, u_long, caddr_t); 277 static void msk_set_prefetch(struct msk_softc *, int, bus_addr_t, uint32_t); 278 static void msk_set_rambuffer(struct msk_if_softc *); 279 static void msk_set_tx_stfwd(struct msk_if_softc *); 280 static void msk_init(void *); 281 static void msk_init_locked(struct msk_if_softc *); 282 static void msk_stop(struct msk_if_softc *); 283 static void msk_watchdog(struct msk_if_softc *); 284 static int msk_mediachange(struct ifnet *); 285 static void msk_mediastatus(struct ifnet *, struct ifmediareq *); 286 static void msk_phy_power(struct msk_softc *, int); 287 static void msk_dmamap_cb(void *, bus_dma_segment_t *, int, int); 288 static int msk_status_dma_alloc(struct msk_softc *); 289 static void msk_status_dma_free(struct msk_softc *); 290 static int msk_txrx_dma_alloc(struct msk_if_softc *); 291 static int msk_rx_dma_jalloc(struct msk_if_softc *); 292 static void msk_txrx_dma_free(struct msk_if_softc *); 293 static void msk_rx_dma_jfree(struct msk_if_softc *); 294 static int msk_rx_fill(struct msk_if_softc *, int); 295 static int msk_init_rx_ring(struct msk_if_softc *); 296 static int msk_init_jumbo_rx_ring(struct msk_if_softc *); 297 static void msk_init_tx_ring(struct msk_if_softc *); 298 static __inline void msk_discard_rxbuf(struct msk_if_softc *, int); 299 static __inline void msk_discard_jumbo_rxbuf(struct msk_if_softc *, int); 300 static int msk_newbuf(struct msk_if_softc *, int); 301 static int msk_jumbo_newbuf(struct msk_if_softc *, int); 302 303 static int msk_phy_readreg(struct msk_if_softc *, int, int); 304 static int msk_phy_writereg(struct msk_if_softc *, int, int, int); 305 static int msk_miibus_readreg(device_t, int, int); 306 static int msk_miibus_writereg(device_t, int, int, int); 307 static void msk_miibus_statchg(device_t); 308 309 static void msk_rxfilter(struct msk_if_softc *); 310 static void msk_setvlan(struct msk_if_softc *, struct ifnet *); 311 312 static void msk_stats_clear(struct msk_if_softc *); 313 static void msk_stats_update(struct msk_if_softc *); 314 static int msk_sysctl_stat32(SYSCTL_HANDLER_ARGS); 315 static int msk_sysctl_stat64(SYSCTL_HANDLER_ARGS); 316 static void msk_sysctl_node(struct msk_if_softc *); 317 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int); 318 static int sysctl_hw_msk_proc_limit(SYSCTL_HANDLER_ARGS); 319 320 static device_method_t mskc_methods[] = { 321 /* Device interface */ 322 DEVMETHOD(device_probe, mskc_probe), 323 DEVMETHOD(device_attach, mskc_attach), 324 DEVMETHOD(device_detach, mskc_detach), 325 DEVMETHOD(device_suspend, mskc_suspend), 326 DEVMETHOD(device_resume, mskc_resume), 327 DEVMETHOD(device_shutdown, mskc_shutdown), 328 329 /* bus interface */ 330 DEVMETHOD(bus_print_child, bus_generic_print_child), 331 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 332 333 { NULL, NULL } 334 }; 335 336 static driver_t mskc_driver = { 337 "mskc", 338 mskc_methods, 339 sizeof(struct msk_softc) 340 }; 341 342 static devclass_t mskc_devclass; 343 344 static device_method_t msk_methods[] = { 345 /* Device interface */ 346 DEVMETHOD(device_probe, msk_probe), 347 DEVMETHOD(device_attach, msk_attach), 348 DEVMETHOD(device_detach, msk_detach), 349 DEVMETHOD(device_shutdown, bus_generic_shutdown), 350 351 /* bus interface */ 352 DEVMETHOD(bus_print_child, bus_generic_print_child), 353 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 354 355 /* MII interface */ 356 DEVMETHOD(miibus_readreg, msk_miibus_readreg), 357 DEVMETHOD(miibus_writereg, msk_miibus_writereg), 358 DEVMETHOD(miibus_statchg, msk_miibus_statchg), 359 360 { NULL, NULL } 361 }; 362 363 static driver_t msk_driver = { 364 "msk", 365 msk_methods, 366 sizeof(struct msk_if_softc) 367 }; 368 369 static devclass_t msk_devclass; 370 371 DRIVER_MODULE(mskc, pci, mskc_driver, mskc_devclass, 0, 0); 372 DRIVER_MODULE(msk, mskc, msk_driver, msk_devclass, 0, 0); 373 DRIVER_MODULE(miibus, msk, miibus_driver, miibus_devclass, 0, 0); 374 375 static struct resource_spec msk_res_spec_io[] = { 376 { SYS_RES_IOPORT, PCIR_BAR(1), RF_ACTIVE }, 377 { -1, 0, 0 } 378 }; 379 380 static struct resource_spec msk_res_spec_mem[] = { 381 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 382 { -1, 0, 0 } 383 }; 384 385 static struct resource_spec msk_irq_spec_legacy[] = { 386 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 387 { -1, 0, 0 } 388 }; 389 390 static struct resource_spec msk_irq_spec_msi[] = { 391 { SYS_RES_IRQ, 1, RF_ACTIVE }, 392 { -1, 0, 0 } 393 }; 394 395 static int 396 msk_miibus_readreg(device_t dev, int phy, int reg) 397 { 398 struct msk_if_softc *sc_if; 399 400 if (phy != PHY_ADDR_MARV) 401 return (0); 402 403 sc_if = device_get_softc(dev); 404 405 return (msk_phy_readreg(sc_if, phy, reg)); 406 } 407 408 static int 409 msk_phy_readreg(struct msk_if_softc *sc_if, int phy, int reg) 410 { 411 struct msk_softc *sc; 412 int i, val; 413 414 sc = sc_if->msk_softc; 415 416 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SMI_CTRL, 417 GM_SMI_CT_PHY_AD(phy) | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD); 418 419 for (i = 0; i < MSK_TIMEOUT; i++) { 420 DELAY(1); 421 val = GMAC_READ_2(sc, sc_if->msk_port, GM_SMI_CTRL); 422 if ((val & GM_SMI_CT_RD_VAL) != 0) { 423 val = GMAC_READ_2(sc, sc_if->msk_port, GM_SMI_DATA); 424 break; 425 } 426 } 427 428 if (i == MSK_TIMEOUT) { 429 if_printf(sc_if->msk_ifp, "phy failed to come ready\n"); 430 val = 0; 431 } 432 433 return (val); 434 } 435 436 static int 437 msk_miibus_writereg(device_t dev, int phy, int reg, int val) 438 { 439 struct msk_if_softc *sc_if; 440 441 if (phy != PHY_ADDR_MARV) 442 return (0); 443 444 sc_if = device_get_softc(dev); 445 446 return (msk_phy_writereg(sc_if, phy, reg, val)); 447 } 448 449 static int 450 msk_phy_writereg(struct msk_if_softc *sc_if, int phy, int reg, int val) 451 { 452 struct msk_softc *sc; 453 int i; 454 455 sc = sc_if->msk_softc; 456 457 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SMI_DATA, val); 458 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SMI_CTRL, 459 GM_SMI_CT_PHY_AD(phy) | GM_SMI_CT_REG_AD(reg)); 460 for (i = 0; i < MSK_TIMEOUT; i++) { 461 DELAY(1); 462 if ((GMAC_READ_2(sc, sc_if->msk_port, GM_SMI_CTRL) & 463 GM_SMI_CT_BUSY) == 0) 464 break; 465 } 466 if (i == MSK_TIMEOUT) 467 if_printf(sc_if->msk_ifp, "phy write timeout\n"); 468 469 return (0); 470 } 471 472 static void 473 msk_miibus_statchg(device_t dev) 474 { 475 struct msk_softc *sc; 476 struct msk_if_softc *sc_if; 477 struct mii_data *mii; 478 struct ifnet *ifp; 479 uint32_t gmac; 480 481 sc_if = device_get_softc(dev); 482 sc = sc_if->msk_softc; 483 484 MSK_IF_LOCK_ASSERT(sc_if); 485 486 mii = device_get_softc(sc_if->msk_miibus); 487 ifp = sc_if->msk_ifp; 488 if (mii == NULL || ifp == NULL || 489 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 490 return; 491 492 sc_if->msk_flags &= ~MSK_FLAG_LINK; 493 if ((mii->mii_media_status & (IFM_AVALID | IFM_ACTIVE)) == 494 (IFM_AVALID | IFM_ACTIVE)) { 495 switch (IFM_SUBTYPE(mii->mii_media_active)) { 496 case IFM_10_T: 497 case IFM_100_TX: 498 sc_if->msk_flags |= MSK_FLAG_LINK; 499 break; 500 case IFM_1000_T: 501 case IFM_1000_SX: 502 case IFM_1000_LX: 503 case IFM_1000_CX: 504 if ((sc_if->msk_flags & MSK_FLAG_FASTETHER) == 0) 505 sc_if->msk_flags |= MSK_FLAG_LINK; 506 break; 507 default: 508 break; 509 } 510 } 511 512 if ((sc_if->msk_flags & MSK_FLAG_LINK) != 0) { 513 /* Enable Tx FIFO Underrun. */ 514 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_MSK), 515 GM_IS_TX_FF_UR | GM_IS_RX_FF_OR); 516 /* 517 * Because mii(4) notify msk(4) that it detected link status 518 * change, there is no need to enable automatic 519 * speed/flow-control/duplex updates. 520 */ 521 gmac = GM_GPCR_AU_ALL_DIS; 522 switch (IFM_SUBTYPE(mii->mii_media_active)) { 523 case IFM_1000_SX: 524 case IFM_1000_T: 525 gmac |= GM_GPCR_SPEED_1000; 526 break; 527 case IFM_100_TX: 528 gmac |= GM_GPCR_SPEED_100; 529 break; 530 case IFM_10_T: 531 break; 532 } 533 534 /* Disable Rx flow control. */ 535 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FLAG0) == 0) 536 gmac |= GM_GPCR_FC_RX_DIS; 537 /* Disable Tx flow control. */ 538 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FLAG1) == 0) 539 gmac |= GM_GPCR_FC_TX_DIS; 540 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) 541 gmac |= GM_GPCR_DUP_FULL; 542 else 543 gmac |= GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS; 544 gmac |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA; 545 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, gmac); 546 /* Read again to ensure writing. */ 547 GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL); 548 gmac = GMC_PAUSE_OFF; 549 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 550 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FLAG0) != 0) 551 gmac = GMC_PAUSE_ON; 552 } 553 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), gmac); 554 555 /* Enable PHY interrupt for FIFO underrun/overflow. */ 556 msk_phy_writereg(sc_if, PHY_ADDR_MARV, 557 PHY_MARV_INT_MASK, PHY_M_IS_FIFO_ERROR); 558 } else { 559 /* 560 * Link state changed to down. 561 * Disable PHY interrupts. 562 */ 563 msk_phy_writereg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_MASK, 0); 564 /* Disable Rx/Tx MAC. */ 565 gmac = GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL); 566 if ((GM_GPCR_RX_ENA | GM_GPCR_TX_ENA) != 0) { 567 gmac &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA); 568 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, gmac); 569 /* Read again to ensure writing. */ 570 GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL); 571 } 572 } 573 } 574 575 static void 576 msk_rxfilter(struct msk_if_softc *sc_if) 577 { 578 struct msk_softc *sc; 579 struct ifnet *ifp; 580 struct ifmultiaddr *ifma; 581 uint32_t mchash[2]; 582 uint32_t crc; 583 uint16_t mode; 584 585 sc = sc_if->msk_softc; 586 587 MSK_IF_LOCK_ASSERT(sc_if); 588 589 ifp = sc_if->msk_ifp; 590 591 bzero(mchash, sizeof(mchash)); 592 mode = GMAC_READ_2(sc, sc_if->msk_port, GM_RX_CTRL); 593 if ((ifp->if_flags & IFF_PROMISC) != 0) 594 mode &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA); 595 else if ((ifp->if_flags & IFF_ALLMULTI) != 0) { 596 mode |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA; 597 mchash[0] = 0xffff; 598 mchash[1] = 0xffff; 599 } else { 600 mode |= GM_RXCR_UCF_ENA; 601 if_maddr_rlock(ifp); 602 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 603 if (ifma->ifma_addr->sa_family != AF_LINK) 604 continue; 605 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *) 606 ifma->ifma_addr), ETHER_ADDR_LEN); 607 /* Just want the 6 least significant bits. */ 608 crc &= 0x3f; 609 /* Set the corresponding bit in the hash table. */ 610 mchash[crc >> 5] |= 1 << (crc & 0x1f); 611 } 612 if_maddr_runlock(ifp); 613 if (mchash[0] != 0 || mchash[1] != 0) 614 mode |= GM_RXCR_MCF_ENA; 615 } 616 617 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H1, 618 mchash[0] & 0xffff); 619 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H2, 620 (mchash[0] >> 16) & 0xffff); 621 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H3, 622 mchash[1] & 0xffff); 623 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H4, 624 (mchash[1] >> 16) & 0xffff); 625 GMAC_WRITE_2(sc, sc_if->msk_port, GM_RX_CTRL, mode); 626 } 627 628 static void 629 msk_setvlan(struct msk_if_softc *sc_if, struct ifnet *ifp) 630 { 631 struct msk_softc *sc; 632 633 sc = sc_if->msk_softc; 634 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) { 635 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), 636 RX_VLAN_STRIP_ON); 637 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 638 TX_VLAN_TAG_ON); 639 } else { 640 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), 641 RX_VLAN_STRIP_OFF); 642 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 643 TX_VLAN_TAG_OFF); 644 } 645 } 646 647 static int 648 msk_rx_fill(struct msk_if_softc *sc_if, int jumbo) 649 { 650 uint16_t idx; 651 int i; 652 653 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0 && 654 (sc_if->msk_ifp->if_capenable & IFCAP_RXCSUM) != 0) { 655 /* Wait until controller executes OP_TCPSTART command. */ 656 for (i = 10; i > 0; i--) { 657 DELAY(10); 658 idx = CSR_READ_2(sc_if->msk_softc, 659 Y2_PREF_Q_ADDR(sc_if->msk_rxq, 660 PREF_UNIT_GET_IDX_REG)); 661 if (idx != 0) 662 break; 663 } 664 if (i == 0) { 665 device_printf(sc_if->msk_if_dev, 666 "prefetch unit stuck?\n"); 667 return (ETIMEDOUT); 668 } 669 /* 670 * Fill consumed LE with free buffer. This can be done 671 * in Rx handler but we don't want to add special code 672 * in fast handler. 673 */ 674 if (jumbo > 0) { 675 if (msk_jumbo_newbuf(sc_if, 0) != 0) 676 return (ENOBUFS); 677 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 678 sc_if->msk_cdata.msk_jumbo_rx_ring_map, 679 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 680 } else { 681 if (msk_newbuf(sc_if, 0) != 0) 682 return (ENOBUFS); 683 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_ring_tag, 684 sc_if->msk_cdata.msk_rx_ring_map, 685 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 686 } 687 sc_if->msk_cdata.msk_rx_prod = 0; 688 CSR_WRITE_2(sc_if->msk_softc, 689 Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_PUT_IDX_REG), 690 sc_if->msk_cdata.msk_rx_prod); 691 } 692 return (0); 693 } 694 695 static int 696 msk_init_rx_ring(struct msk_if_softc *sc_if) 697 { 698 struct msk_ring_data *rd; 699 struct msk_rxdesc *rxd; 700 int i, prod; 701 702 MSK_IF_LOCK_ASSERT(sc_if); 703 704 sc_if->msk_cdata.msk_rx_cons = 0; 705 sc_if->msk_cdata.msk_rx_prod = 0; 706 sc_if->msk_cdata.msk_rx_putwm = MSK_PUT_WM; 707 708 rd = &sc_if->msk_rdata; 709 bzero(rd->msk_rx_ring, sizeof(struct msk_rx_desc) * MSK_RX_RING_CNT); 710 prod = sc_if->msk_cdata.msk_rx_prod; 711 i = 0; 712 /* Have controller know how to compute Rx checksum. */ 713 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0 && 714 (sc_if->msk_ifp->if_capenable & IFCAP_RXCSUM) != 0) { 715 rxd = &sc_if->msk_cdata.msk_rxdesc[prod]; 716 rxd->rx_m = NULL; 717 rxd->rx_le = &rd->msk_rx_ring[prod]; 718 rxd->rx_le->msk_addr = htole32(ETHER_HDR_LEN << 16 | 719 ETHER_HDR_LEN); 720 rxd->rx_le->msk_control = htole32(OP_TCPSTART | HW_OWNER); 721 MSK_INC(prod, MSK_RX_RING_CNT); 722 MSK_INC(sc_if->msk_cdata.msk_rx_cons, MSK_RX_RING_CNT); 723 i++; 724 } 725 for (; i < MSK_RX_RING_CNT; i++) { 726 rxd = &sc_if->msk_cdata.msk_rxdesc[prod]; 727 rxd->rx_m = NULL; 728 rxd->rx_le = &rd->msk_rx_ring[prod]; 729 if (msk_newbuf(sc_if, prod) != 0) 730 return (ENOBUFS); 731 MSK_INC(prod, MSK_RX_RING_CNT); 732 } 733 734 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_ring_tag, 735 sc_if->msk_cdata.msk_rx_ring_map, 736 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 737 738 /* Update prefetch unit. */ 739 sc_if->msk_cdata.msk_rx_prod = MSK_RX_RING_CNT - 1; 740 CSR_WRITE_2(sc_if->msk_softc, 741 Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_PUT_IDX_REG), 742 sc_if->msk_cdata.msk_rx_prod); 743 if (msk_rx_fill(sc_if, 0) != 0) 744 return (ENOBUFS); 745 return (0); 746 } 747 748 static int 749 msk_init_jumbo_rx_ring(struct msk_if_softc *sc_if) 750 { 751 struct msk_ring_data *rd; 752 struct msk_rxdesc *rxd; 753 int i, prod; 754 755 MSK_IF_LOCK_ASSERT(sc_if); 756 757 sc_if->msk_cdata.msk_rx_cons = 0; 758 sc_if->msk_cdata.msk_rx_prod = 0; 759 sc_if->msk_cdata.msk_rx_putwm = MSK_PUT_WM; 760 761 rd = &sc_if->msk_rdata; 762 bzero(rd->msk_jumbo_rx_ring, 763 sizeof(struct msk_rx_desc) * MSK_JUMBO_RX_RING_CNT); 764 prod = sc_if->msk_cdata.msk_rx_prod; 765 i = 0; 766 /* Have controller know how to compute Rx checksum. */ 767 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0 && 768 (sc_if->msk_ifp->if_capenable & IFCAP_RXCSUM) != 0) { 769 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[prod]; 770 rxd->rx_m = NULL; 771 rxd->rx_le = &rd->msk_jumbo_rx_ring[prod]; 772 rxd->rx_le->msk_addr = htole32(ETHER_HDR_LEN << 16 | 773 ETHER_HDR_LEN); 774 rxd->rx_le->msk_control = htole32(OP_TCPSTART | HW_OWNER); 775 MSK_INC(prod, MSK_JUMBO_RX_RING_CNT); 776 MSK_INC(sc_if->msk_cdata.msk_rx_cons, MSK_JUMBO_RX_RING_CNT); 777 i++; 778 } 779 for (; i < MSK_JUMBO_RX_RING_CNT; i++) { 780 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[prod]; 781 rxd->rx_m = NULL; 782 rxd->rx_le = &rd->msk_jumbo_rx_ring[prod]; 783 if (msk_jumbo_newbuf(sc_if, prod) != 0) 784 return (ENOBUFS); 785 MSK_INC(prod, MSK_JUMBO_RX_RING_CNT); 786 } 787 788 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 789 sc_if->msk_cdata.msk_jumbo_rx_ring_map, 790 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 791 792 sc_if->msk_cdata.msk_rx_prod = MSK_JUMBO_RX_RING_CNT - 1; 793 CSR_WRITE_2(sc_if->msk_softc, 794 Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_PUT_IDX_REG), 795 sc_if->msk_cdata.msk_rx_prod); 796 if (msk_rx_fill(sc_if, 1) != 0) 797 return (ENOBUFS); 798 return (0); 799 } 800 801 static void 802 msk_init_tx_ring(struct msk_if_softc *sc_if) 803 { 804 struct msk_ring_data *rd; 805 struct msk_txdesc *txd; 806 int i; 807 808 sc_if->msk_cdata.msk_tso_mtu = 0; 809 sc_if->msk_cdata.msk_last_csum = 0; 810 sc_if->msk_cdata.msk_tx_prod = 0; 811 sc_if->msk_cdata.msk_tx_cons = 0; 812 sc_if->msk_cdata.msk_tx_cnt = 0; 813 814 rd = &sc_if->msk_rdata; 815 bzero(rd->msk_tx_ring, sizeof(struct msk_tx_desc) * MSK_TX_RING_CNT); 816 for (i = 0; i < MSK_TX_RING_CNT; i++) { 817 txd = &sc_if->msk_cdata.msk_txdesc[i]; 818 txd->tx_m = NULL; 819 txd->tx_le = &rd->msk_tx_ring[i]; 820 } 821 822 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_ring_tag, 823 sc_if->msk_cdata.msk_tx_ring_map, 824 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 825 } 826 827 static __inline void 828 msk_discard_rxbuf(struct msk_if_softc *sc_if, int idx) 829 { 830 struct msk_rx_desc *rx_le; 831 struct msk_rxdesc *rxd; 832 struct mbuf *m; 833 834 rxd = &sc_if->msk_cdata.msk_rxdesc[idx]; 835 m = rxd->rx_m; 836 rx_le = rxd->rx_le; 837 rx_le->msk_control = htole32(m->m_len | OP_PACKET | HW_OWNER); 838 } 839 840 static __inline void 841 msk_discard_jumbo_rxbuf(struct msk_if_softc *sc_if, int idx) 842 { 843 struct msk_rx_desc *rx_le; 844 struct msk_rxdesc *rxd; 845 struct mbuf *m; 846 847 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[idx]; 848 m = rxd->rx_m; 849 rx_le = rxd->rx_le; 850 rx_le->msk_control = htole32(m->m_len | OP_PACKET | HW_OWNER); 851 } 852 853 static int 854 msk_newbuf(struct msk_if_softc *sc_if, int idx) 855 { 856 struct msk_rx_desc *rx_le; 857 struct msk_rxdesc *rxd; 858 struct mbuf *m; 859 bus_dma_segment_t segs[1]; 860 bus_dmamap_t map; 861 int nsegs; 862 863 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 864 if (m == NULL) 865 return (ENOBUFS); 866 867 m->m_len = m->m_pkthdr.len = MCLBYTES; 868 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) == 0) 869 m_adj(m, ETHER_ALIGN); 870 #ifndef __NO_STRICT_ALIGNMENT 871 else 872 m_adj(m, MSK_RX_BUF_ALIGN); 873 #endif 874 875 if (bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_rx_tag, 876 sc_if->msk_cdata.msk_rx_sparemap, m, segs, &nsegs, 877 BUS_DMA_NOWAIT) != 0) { 878 m_freem(m); 879 return (ENOBUFS); 880 } 881 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 882 883 rxd = &sc_if->msk_cdata.msk_rxdesc[idx]; 884 if (rxd->rx_m != NULL) { 885 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_tag, rxd->rx_dmamap, 886 BUS_DMASYNC_POSTREAD); 887 bus_dmamap_unload(sc_if->msk_cdata.msk_rx_tag, rxd->rx_dmamap); 888 } 889 map = rxd->rx_dmamap; 890 rxd->rx_dmamap = sc_if->msk_cdata.msk_rx_sparemap; 891 sc_if->msk_cdata.msk_rx_sparemap = map; 892 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_tag, rxd->rx_dmamap, 893 BUS_DMASYNC_PREREAD); 894 rxd->rx_m = m; 895 rx_le = rxd->rx_le; 896 rx_le->msk_addr = htole32(MSK_ADDR_LO(segs[0].ds_addr)); 897 rx_le->msk_control = 898 htole32(segs[0].ds_len | OP_PACKET | HW_OWNER); 899 900 return (0); 901 } 902 903 static int 904 msk_jumbo_newbuf(struct msk_if_softc *sc_if, int idx) 905 { 906 struct msk_rx_desc *rx_le; 907 struct msk_rxdesc *rxd; 908 struct mbuf *m; 909 bus_dma_segment_t segs[1]; 910 bus_dmamap_t map; 911 int nsegs; 912 913 m = m_getjcl(M_DONTWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES); 914 if (m == NULL) 915 return (ENOBUFS); 916 if ((m->m_flags & M_EXT) == 0) { 917 m_freem(m); 918 return (ENOBUFS); 919 } 920 m->m_len = m->m_pkthdr.len = MJUM9BYTES; 921 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) == 0) 922 m_adj(m, ETHER_ALIGN); 923 #ifndef __NO_STRICT_ALIGNMENT 924 else 925 m_adj(m, MSK_RX_BUF_ALIGN); 926 #endif 927 928 if (bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_jumbo_rx_tag, 929 sc_if->msk_cdata.msk_jumbo_rx_sparemap, m, segs, &nsegs, 930 BUS_DMA_NOWAIT) != 0) { 931 m_freem(m); 932 return (ENOBUFS); 933 } 934 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 935 936 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[idx]; 937 if (rxd->rx_m != NULL) { 938 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_tag, 939 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 940 bus_dmamap_unload(sc_if->msk_cdata.msk_jumbo_rx_tag, 941 rxd->rx_dmamap); 942 } 943 map = rxd->rx_dmamap; 944 rxd->rx_dmamap = sc_if->msk_cdata.msk_jumbo_rx_sparemap; 945 sc_if->msk_cdata.msk_jumbo_rx_sparemap = map; 946 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_tag, rxd->rx_dmamap, 947 BUS_DMASYNC_PREREAD); 948 rxd->rx_m = m; 949 rx_le = rxd->rx_le; 950 rx_le->msk_addr = htole32(MSK_ADDR_LO(segs[0].ds_addr)); 951 rx_le->msk_control = 952 htole32(segs[0].ds_len | OP_PACKET | HW_OWNER); 953 954 return (0); 955 } 956 957 /* 958 * Set media options. 959 */ 960 static int 961 msk_mediachange(struct ifnet *ifp) 962 { 963 struct msk_if_softc *sc_if; 964 struct mii_data *mii; 965 int error; 966 967 sc_if = ifp->if_softc; 968 969 MSK_IF_LOCK(sc_if); 970 mii = device_get_softc(sc_if->msk_miibus); 971 error = mii_mediachg(mii); 972 MSK_IF_UNLOCK(sc_if); 973 974 return (error); 975 } 976 977 /* 978 * Report current media status. 979 */ 980 static void 981 msk_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 982 { 983 struct msk_if_softc *sc_if; 984 struct mii_data *mii; 985 986 sc_if = ifp->if_softc; 987 MSK_IF_LOCK(sc_if); 988 if ((ifp->if_flags & IFF_UP) == 0) { 989 MSK_IF_UNLOCK(sc_if); 990 return; 991 } 992 mii = device_get_softc(sc_if->msk_miibus); 993 994 mii_pollstat(mii); 995 MSK_IF_UNLOCK(sc_if); 996 ifmr->ifm_active = mii->mii_media_active; 997 ifmr->ifm_status = mii->mii_media_status; 998 } 999 1000 static int 1001 msk_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1002 { 1003 struct msk_if_softc *sc_if; 1004 struct ifreq *ifr; 1005 struct mii_data *mii; 1006 int error, mask, reinit; 1007 1008 sc_if = ifp->if_softc; 1009 ifr = (struct ifreq *)data; 1010 error = 0; 1011 1012 switch(command) { 1013 case SIOCSIFMTU: 1014 MSK_IF_LOCK(sc_if); 1015 if (ifr->ifr_mtu > MSK_JUMBO_MTU || ifr->ifr_mtu < ETHERMIN) 1016 error = EINVAL; 1017 else if (ifp->if_mtu != ifr->ifr_mtu) { 1018 if (ifr->ifr_mtu > ETHERMTU) { 1019 if ((sc_if->msk_flags & MSK_FLAG_JUMBO) == 0) { 1020 error = EINVAL; 1021 MSK_IF_UNLOCK(sc_if); 1022 break; 1023 } 1024 if ((sc_if->msk_flags & 1025 MSK_FLAG_JUMBO_NOCSUM) != 0) { 1026 ifp->if_hwassist &= 1027 ~(MSK_CSUM_FEATURES | CSUM_TSO); 1028 ifp->if_capenable &= 1029 ~(IFCAP_TSO4 | IFCAP_TXCSUM); 1030 VLAN_CAPABILITIES(ifp); 1031 } 1032 } 1033 ifp->if_mtu = ifr->ifr_mtu; 1034 msk_init_locked(sc_if); 1035 } 1036 MSK_IF_UNLOCK(sc_if); 1037 break; 1038 case SIOCSIFFLAGS: 1039 MSK_IF_LOCK(sc_if); 1040 if ((ifp->if_flags & IFF_UP) != 0) { 1041 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 && 1042 ((ifp->if_flags ^ sc_if->msk_if_flags) & 1043 (IFF_PROMISC | IFF_ALLMULTI)) != 0) 1044 msk_rxfilter(sc_if); 1045 else if ((sc_if->msk_flags & MSK_FLAG_DETACH) == 0) 1046 msk_init_locked(sc_if); 1047 } else if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1048 msk_stop(sc_if); 1049 sc_if->msk_if_flags = ifp->if_flags; 1050 MSK_IF_UNLOCK(sc_if); 1051 break; 1052 case SIOCADDMULTI: 1053 case SIOCDELMULTI: 1054 MSK_IF_LOCK(sc_if); 1055 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1056 msk_rxfilter(sc_if); 1057 MSK_IF_UNLOCK(sc_if); 1058 break; 1059 case SIOCGIFMEDIA: 1060 case SIOCSIFMEDIA: 1061 mii = device_get_softc(sc_if->msk_miibus); 1062 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1063 break; 1064 case SIOCSIFCAP: 1065 reinit = 0; 1066 MSK_IF_LOCK(sc_if); 1067 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 1068 if ((mask & IFCAP_TXCSUM) != 0 && 1069 (IFCAP_TXCSUM & ifp->if_capabilities) != 0) { 1070 ifp->if_capenable ^= IFCAP_TXCSUM; 1071 if ((IFCAP_TXCSUM & ifp->if_capenable) != 0) 1072 ifp->if_hwassist |= MSK_CSUM_FEATURES; 1073 else 1074 ifp->if_hwassist &= ~MSK_CSUM_FEATURES; 1075 } 1076 if ((mask & IFCAP_RXCSUM) != 0 && 1077 (IFCAP_RXCSUM & ifp->if_capabilities) != 0) { 1078 ifp->if_capenable ^= IFCAP_RXCSUM; 1079 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0) 1080 reinit = 1; 1081 } 1082 if ((mask & IFCAP_VLAN_HWCSUM) != 0 && 1083 (IFCAP_VLAN_HWCSUM & ifp->if_capabilities) != 0) 1084 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; 1085 if ((mask & IFCAP_TSO4) != 0 && 1086 (IFCAP_TSO4 & ifp->if_capabilities) != 0) { 1087 ifp->if_capenable ^= IFCAP_TSO4; 1088 if ((IFCAP_TSO4 & ifp->if_capenable) != 0) 1089 ifp->if_hwassist |= CSUM_TSO; 1090 else 1091 ifp->if_hwassist &= ~CSUM_TSO; 1092 } 1093 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 1094 (IFCAP_VLAN_HWTSO & ifp->if_capabilities) != 0) 1095 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 1096 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 1097 (IFCAP_VLAN_HWTAGGING & ifp->if_capabilities) != 0) { 1098 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 1099 if ((IFCAP_VLAN_HWTAGGING & ifp->if_capenable) == 0) 1100 ifp->if_capenable &= ~IFCAP_VLAN_HWTSO; 1101 msk_setvlan(sc_if, ifp); 1102 } 1103 if (ifp->if_mtu > ETHERMTU && 1104 (sc_if->msk_flags & MSK_FLAG_JUMBO_NOCSUM) != 0) { 1105 ifp->if_hwassist &= ~(MSK_CSUM_FEATURES | CSUM_TSO); 1106 ifp->if_capenable &= ~(IFCAP_TSO4 | IFCAP_TXCSUM); 1107 } 1108 VLAN_CAPABILITIES(ifp); 1109 if (reinit > 0 && (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 1110 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1111 msk_init_locked(sc_if); 1112 } 1113 MSK_IF_UNLOCK(sc_if); 1114 break; 1115 default: 1116 error = ether_ioctl(ifp, command, data); 1117 break; 1118 } 1119 1120 return (error); 1121 } 1122 1123 static int 1124 mskc_probe(device_t dev) 1125 { 1126 struct msk_product *mp; 1127 uint16_t vendor, devid; 1128 int i; 1129 1130 vendor = pci_get_vendor(dev); 1131 devid = pci_get_device(dev); 1132 mp = msk_products; 1133 for (i = 0; i < sizeof(msk_products)/sizeof(msk_products[0]); 1134 i++, mp++) { 1135 if (vendor == mp->msk_vendorid && devid == mp->msk_deviceid) { 1136 device_set_desc(dev, mp->msk_name); 1137 return (BUS_PROBE_DEFAULT); 1138 } 1139 } 1140 1141 return (ENXIO); 1142 } 1143 1144 static int 1145 mskc_setup_rambuffer(struct msk_softc *sc) 1146 { 1147 int next; 1148 int i; 1149 1150 /* Get adapter SRAM size. */ 1151 sc->msk_ramsize = CSR_READ_1(sc, B2_E_0) * 4; 1152 if (bootverbose) 1153 device_printf(sc->msk_dev, 1154 "RAM buffer size : %dKB\n", sc->msk_ramsize); 1155 if (sc->msk_ramsize == 0) 1156 return (0); 1157 1158 sc->msk_pflags |= MSK_FLAG_RAMBUF; 1159 /* 1160 * Give receiver 2/3 of memory and round down to the multiple 1161 * of 1024. Tx/Rx RAM buffer size of Yukon II shoud be multiple 1162 * of 1024. 1163 */ 1164 sc->msk_rxqsize = rounddown((sc->msk_ramsize * 1024 * 2) / 3, 1024); 1165 sc->msk_txqsize = (sc->msk_ramsize * 1024) - sc->msk_rxqsize; 1166 for (i = 0, next = 0; i < sc->msk_num_port; i++) { 1167 sc->msk_rxqstart[i] = next; 1168 sc->msk_rxqend[i] = next + sc->msk_rxqsize - 1; 1169 next = sc->msk_rxqend[i] + 1; 1170 sc->msk_txqstart[i] = next; 1171 sc->msk_txqend[i] = next + sc->msk_txqsize - 1; 1172 next = sc->msk_txqend[i] + 1; 1173 if (bootverbose) { 1174 device_printf(sc->msk_dev, 1175 "Port %d : Rx Queue %dKB(0x%08x:0x%08x)\n", i, 1176 sc->msk_rxqsize / 1024, sc->msk_rxqstart[i], 1177 sc->msk_rxqend[i]); 1178 device_printf(sc->msk_dev, 1179 "Port %d : Tx Queue %dKB(0x%08x:0x%08x)\n", i, 1180 sc->msk_txqsize / 1024, sc->msk_txqstart[i], 1181 sc->msk_txqend[i]); 1182 } 1183 } 1184 1185 return (0); 1186 } 1187 1188 static void 1189 msk_phy_power(struct msk_softc *sc, int mode) 1190 { 1191 uint32_t our, val; 1192 int i; 1193 1194 switch (mode) { 1195 case MSK_PHY_POWERUP: 1196 /* Switch power to VCC (WA for VAUX problem). */ 1197 CSR_WRITE_1(sc, B0_POWER_CTRL, 1198 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON); 1199 /* Disable Core Clock Division, set Clock Select to 0. */ 1200 CSR_WRITE_4(sc, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS); 1201 1202 val = 0; 1203 if (sc->msk_hw_id == CHIP_ID_YUKON_XL && 1204 sc->msk_hw_rev > CHIP_REV_YU_XL_A1) { 1205 /* Enable bits are inverted. */ 1206 val = Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS | 1207 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS | 1208 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS; 1209 } 1210 /* 1211 * Enable PCI & Core Clock, enable clock gating for both Links. 1212 */ 1213 CSR_WRITE_1(sc, B2_Y2_CLK_GATE, val); 1214 1215 val = CSR_PCI_READ_4(sc, PCI_OUR_REG_1); 1216 val &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD); 1217 if (sc->msk_hw_id == CHIP_ID_YUKON_XL) { 1218 if (sc->msk_hw_rev > CHIP_REV_YU_XL_A1) { 1219 /* Deassert Low Power for 1st PHY. */ 1220 val |= PCI_Y2_PHY1_COMA; 1221 if (sc->msk_num_port > 1) 1222 val |= PCI_Y2_PHY2_COMA; 1223 } 1224 } 1225 /* Release PHY from PowerDown/COMA mode. */ 1226 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_1, val); 1227 switch (sc->msk_hw_id) { 1228 case CHIP_ID_YUKON_EC_U: 1229 case CHIP_ID_YUKON_EX: 1230 case CHIP_ID_YUKON_FE_P: 1231 case CHIP_ID_YUKON_UL_2: 1232 CSR_WRITE_2(sc, B0_CTST, Y2_HW_WOL_OFF); 1233 1234 /* Enable all clocks. */ 1235 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_3, 0); 1236 our = CSR_PCI_READ_4(sc, PCI_OUR_REG_4); 1237 our &= (PCI_FORCE_ASPM_REQUEST|PCI_ASPM_GPHY_LINK_DOWN| 1238 PCI_ASPM_INT_FIFO_EMPTY|PCI_ASPM_CLKRUN_REQUEST); 1239 /* Set all bits to 0 except bits 15..12. */ 1240 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_4, our); 1241 our = CSR_PCI_READ_4(sc, PCI_OUR_REG_5); 1242 our &= PCI_CTL_TIM_VMAIN_AV_MSK; 1243 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_5, our); 1244 CSR_PCI_WRITE_4(sc, PCI_CFG_REG_1, 0); 1245 /* 1246 * Disable status race, workaround for 1247 * Yukon EC Ultra & Yukon EX. 1248 */ 1249 val = CSR_READ_4(sc, B2_GP_IO); 1250 val |= GLB_GPIO_STAT_RACE_DIS; 1251 CSR_WRITE_4(sc, B2_GP_IO, val); 1252 CSR_READ_4(sc, B2_GP_IO); 1253 break; 1254 default: 1255 break; 1256 } 1257 for (i = 0; i < sc->msk_num_port; i++) { 1258 CSR_WRITE_2(sc, MR_ADDR(i, GMAC_LINK_CTRL), 1259 GMLC_RST_SET); 1260 CSR_WRITE_2(sc, MR_ADDR(i, GMAC_LINK_CTRL), 1261 GMLC_RST_CLR); 1262 } 1263 break; 1264 case MSK_PHY_POWERDOWN: 1265 val = CSR_PCI_READ_4(sc, PCI_OUR_REG_1); 1266 val |= PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD; 1267 if (sc->msk_hw_id == CHIP_ID_YUKON_XL && 1268 sc->msk_hw_rev > CHIP_REV_YU_XL_A1) { 1269 val &= ~PCI_Y2_PHY1_COMA; 1270 if (sc->msk_num_port > 1) 1271 val &= ~PCI_Y2_PHY2_COMA; 1272 } 1273 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_1, val); 1274 1275 val = Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS | 1276 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS | 1277 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS; 1278 if (sc->msk_hw_id == CHIP_ID_YUKON_XL && 1279 sc->msk_hw_rev > CHIP_REV_YU_XL_A1) { 1280 /* Enable bits are inverted. */ 1281 val = 0; 1282 } 1283 /* 1284 * Disable PCI & Core Clock, disable clock gating for 1285 * both Links. 1286 */ 1287 CSR_WRITE_1(sc, B2_Y2_CLK_GATE, val); 1288 CSR_WRITE_1(sc, B0_POWER_CTRL, 1289 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_ON | PC_VCC_OFF); 1290 break; 1291 default: 1292 break; 1293 } 1294 } 1295 1296 static void 1297 mskc_reset(struct msk_softc *sc) 1298 { 1299 bus_addr_t addr; 1300 uint16_t status; 1301 uint32_t val; 1302 int i; 1303 1304 CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR); 1305 1306 /* Disable ASF. */ 1307 if (sc->msk_hw_id == CHIP_ID_YUKON_EX) { 1308 status = CSR_READ_2(sc, B28_Y2_ASF_HCU_CCSR); 1309 /* Clear AHB bridge & microcontroller reset. */ 1310 status &= ~(Y2_ASF_HCU_CCSR_AHB_RST | 1311 Y2_ASF_HCU_CCSR_CPU_RST_MODE); 1312 /* Clear ASF microcontroller state. */ 1313 status &= ~ Y2_ASF_HCU_CCSR_UC_STATE_MSK; 1314 CSR_WRITE_2(sc, B28_Y2_ASF_HCU_CCSR, status); 1315 } else 1316 CSR_WRITE_1(sc, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET); 1317 CSR_WRITE_2(sc, B0_CTST, Y2_ASF_DISABLE); 1318 1319 /* 1320 * Since we disabled ASF, S/W reset is required for Power Management. 1321 */ 1322 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); 1323 CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR); 1324 1325 /* Clear all error bits in the PCI status register. */ 1326 status = pci_read_config(sc->msk_dev, PCIR_STATUS, 2); 1327 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON); 1328 1329 pci_write_config(sc->msk_dev, PCIR_STATUS, status | 1330 PCIM_STATUS_PERR | PCIM_STATUS_SERR | PCIM_STATUS_RMABORT | 1331 PCIM_STATUS_RTABORT | PCIM_STATUS_PERRREPORT, 2); 1332 CSR_WRITE_2(sc, B0_CTST, CS_MRST_CLR); 1333 1334 switch (sc->msk_bustype) { 1335 case MSK_PEX_BUS: 1336 /* Clear all PEX errors. */ 1337 CSR_PCI_WRITE_4(sc, PEX_UNC_ERR_STAT, 0xffffffff); 1338 val = CSR_PCI_READ_4(sc, PEX_UNC_ERR_STAT); 1339 if ((val & PEX_RX_OV) != 0) { 1340 sc->msk_intrmask &= ~Y2_IS_HW_ERR; 1341 sc->msk_intrhwemask &= ~Y2_IS_PCI_EXP; 1342 } 1343 break; 1344 case MSK_PCI_BUS: 1345 case MSK_PCIX_BUS: 1346 /* Set Cache Line Size to 2(8bytes) if configured to 0. */ 1347 val = pci_read_config(sc->msk_dev, PCIR_CACHELNSZ, 1); 1348 if (val == 0) 1349 pci_write_config(sc->msk_dev, PCIR_CACHELNSZ, 2, 1); 1350 if (sc->msk_bustype == MSK_PCIX_BUS) { 1351 /* Set Cache Line Size opt. */ 1352 val = pci_read_config(sc->msk_dev, PCI_OUR_REG_1, 4); 1353 val |= PCI_CLS_OPT; 1354 pci_write_config(sc->msk_dev, PCI_OUR_REG_1, val, 4); 1355 } 1356 break; 1357 } 1358 /* Set PHY power state. */ 1359 msk_phy_power(sc, MSK_PHY_POWERUP); 1360 1361 /* Reset GPHY/GMAC Control */ 1362 for (i = 0; i < sc->msk_num_port; i++) { 1363 /* GPHY Control reset. */ 1364 CSR_WRITE_4(sc, MR_ADDR(i, GPHY_CTRL), GPC_RST_SET); 1365 CSR_WRITE_4(sc, MR_ADDR(i, GPHY_CTRL), GPC_RST_CLR); 1366 /* GMAC Control reset. */ 1367 CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), GMC_RST_SET); 1368 CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), GMC_RST_CLR); 1369 CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), GMC_F_LOOPB_OFF); 1370 if (sc->msk_hw_id == CHIP_ID_YUKON_EX) 1371 CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), 1372 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON | 1373 GMC_BYP_RETR_ON); 1374 } 1375 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 1376 1377 /* LED On. */ 1378 CSR_WRITE_2(sc, B0_CTST, Y2_LED_STAT_ON); 1379 1380 /* Clear TWSI IRQ. */ 1381 CSR_WRITE_4(sc, B2_I2C_IRQ, I2C_CLR_IRQ); 1382 1383 /* Turn off hardware timer. */ 1384 CSR_WRITE_1(sc, B2_TI_CTRL, TIM_STOP); 1385 CSR_WRITE_1(sc, B2_TI_CTRL, TIM_CLR_IRQ); 1386 1387 /* Turn off descriptor polling. */ 1388 CSR_WRITE_1(sc, B28_DPT_CTRL, DPT_STOP); 1389 1390 /* Turn off time stamps. */ 1391 CSR_WRITE_1(sc, GMAC_TI_ST_CTRL, GMT_ST_STOP); 1392 CSR_WRITE_1(sc, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ); 1393 1394 /* Configure timeout values. */ 1395 for (i = 0; i < sc->msk_num_port; i++) { 1396 CSR_WRITE_2(sc, SELECT_RAM_BUFFER(i, B3_RI_CTRL), RI_RST_SET); 1397 CSR_WRITE_2(sc, SELECT_RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR); 1398 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_R1), 1399 MSK_RI_TO_53); 1400 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XA1), 1401 MSK_RI_TO_53); 1402 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XS1), 1403 MSK_RI_TO_53); 1404 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_R1), 1405 MSK_RI_TO_53); 1406 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XA1), 1407 MSK_RI_TO_53); 1408 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XS1), 1409 MSK_RI_TO_53); 1410 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_R2), 1411 MSK_RI_TO_53); 1412 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XA2), 1413 MSK_RI_TO_53); 1414 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XS2), 1415 MSK_RI_TO_53); 1416 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_R2), 1417 MSK_RI_TO_53); 1418 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XA2), 1419 MSK_RI_TO_53); 1420 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XS2), 1421 MSK_RI_TO_53); 1422 } 1423 1424 /* Disable all interrupts. */ 1425 CSR_WRITE_4(sc, B0_HWE_IMSK, 0); 1426 CSR_READ_4(sc, B0_HWE_IMSK); 1427 CSR_WRITE_4(sc, B0_IMSK, 0); 1428 CSR_READ_4(sc, B0_IMSK); 1429 1430 /* 1431 * On dual port PCI-X card, there is an problem where status 1432 * can be received out of order due to split transactions. 1433 */ 1434 if (sc->msk_pcixcap != 0 && sc->msk_num_port > 1) { 1435 uint16_t pcix_cmd; 1436 1437 pcix_cmd = pci_read_config(sc->msk_dev, 1438 sc->msk_pcixcap + PCIXR_COMMAND, 2); 1439 /* Clear Max Outstanding Split Transactions. */ 1440 pcix_cmd &= ~PCIXM_COMMAND_MAX_SPLITS; 1441 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON); 1442 pci_write_config(sc->msk_dev, 1443 sc->msk_pcixcap + PCIXR_COMMAND, pcix_cmd, 2); 1444 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 1445 } 1446 if (sc->msk_expcap != 0) { 1447 /* Change Max. Read Request Size to 2048 bytes. */ 1448 if (pci_get_max_read_req(sc->msk_dev) == 512) 1449 pci_set_max_read_req(sc->msk_dev, 2048); 1450 } 1451 1452 /* Clear status list. */ 1453 bzero(sc->msk_stat_ring, 1454 sizeof(struct msk_stat_desc) * MSK_STAT_RING_CNT); 1455 sc->msk_stat_cons = 0; 1456 bus_dmamap_sync(sc->msk_stat_tag, sc->msk_stat_map, 1457 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1458 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_RST_SET); 1459 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_RST_CLR); 1460 /* Set the status list base address. */ 1461 addr = sc->msk_stat_ring_paddr; 1462 CSR_WRITE_4(sc, STAT_LIST_ADDR_LO, MSK_ADDR_LO(addr)); 1463 CSR_WRITE_4(sc, STAT_LIST_ADDR_HI, MSK_ADDR_HI(addr)); 1464 /* Set the status list last index. */ 1465 CSR_WRITE_2(sc, STAT_LAST_IDX, MSK_STAT_RING_CNT - 1); 1466 if (sc->msk_hw_id == CHIP_ID_YUKON_EC && 1467 sc->msk_hw_rev == CHIP_REV_YU_EC_A1) { 1468 /* WA for dev. #4.3 */ 1469 CSR_WRITE_2(sc, STAT_TX_IDX_TH, ST_TXTH_IDX_MASK); 1470 /* WA for dev. #4.18 */ 1471 CSR_WRITE_1(sc, STAT_FIFO_WM, 0x21); 1472 CSR_WRITE_1(sc, STAT_FIFO_ISR_WM, 0x07); 1473 } else { 1474 CSR_WRITE_2(sc, STAT_TX_IDX_TH, 0x0a); 1475 CSR_WRITE_1(sc, STAT_FIFO_WM, 0x10); 1476 if (sc->msk_hw_id == CHIP_ID_YUKON_XL && 1477 sc->msk_hw_rev == CHIP_REV_YU_XL_A0) 1478 CSR_WRITE_1(sc, STAT_FIFO_ISR_WM, 0x04); 1479 else 1480 CSR_WRITE_1(sc, STAT_FIFO_ISR_WM, 0x10); 1481 CSR_WRITE_4(sc, STAT_ISR_TIMER_INI, 0x0190); 1482 } 1483 /* 1484 * Use default value for STAT_ISR_TIMER_INI, STAT_LEV_TIMER_INI. 1485 */ 1486 CSR_WRITE_4(sc, STAT_TX_TIMER_INI, MSK_USECS(sc, 1000)); 1487 1488 /* Enable status unit. */ 1489 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_OP_ON); 1490 1491 CSR_WRITE_1(sc, STAT_TX_TIMER_CTRL, TIM_START); 1492 CSR_WRITE_1(sc, STAT_LEV_TIMER_CTRL, TIM_START); 1493 CSR_WRITE_1(sc, STAT_ISR_TIMER_CTRL, TIM_START); 1494 } 1495 1496 static int 1497 msk_probe(device_t dev) 1498 { 1499 struct msk_softc *sc; 1500 char desc[100]; 1501 1502 sc = device_get_softc(device_get_parent(dev)); 1503 /* 1504 * Not much to do here. We always know there will be 1505 * at least one GMAC present, and if there are two, 1506 * mskc_attach() will create a second device instance 1507 * for us. 1508 */ 1509 snprintf(desc, sizeof(desc), 1510 "Marvell Technology Group Ltd. %s Id 0x%02x Rev 0x%02x", 1511 model_name[sc->msk_hw_id - CHIP_ID_YUKON_XL], sc->msk_hw_id, 1512 sc->msk_hw_rev); 1513 device_set_desc_copy(dev, desc); 1514 1515 return (BUS_PROBE_DEFAULT); 1516 } 1517 1518 static int 1519 msk_attach(device_t dev) 1520 { 1521 struct msk_softc *sc; 1522 struct msk_if_softc *sc_if; 1523 struct ifnet *ifp; 1524 struct msk_mii_data *mmd; 1525 int i, port, error; 1526 uint8_t eaddr[6]; 1527 1528 if (dev == NULL) 1529 return (EINVAL); 1530 1531 error = 0; 1532 sc_if = device_get_softc(dev); 1533 sc = device_get_softc(device_get_parent(dev)); 1534 mmd = device_get_ivars(dev); 1535 port = mmd->port; 1536 1537 sc_if->msk_if_dev = dev; 1538 sc_if->msk_port = port; 1539 sc_if->msk_softc = sc; 1540 sc_if->msk_flags = sc->msk_pflags; 1541 sc->msk_if[port] = sc_if; 1542 /* Setup Tx/Rx queue register offsets. */ 1543 if (port == MSK_PORT_A) { 1544 sc_if->msk_txq = Q_XA1; 1545 sc_if->msk_txsq = Q_XS1; 1546 sc_if->msk_rxq = Q_R1; 1547 } else { 1548 sc_if->msk_txq = Q_XA2; 1549 sc_if->msk_txsq = Q_XS2; 1550 sc_if->msk_rxq = Q_R2; 1551 } 1552 1553 callout_init_mtx(&sc_if->msk_tick_ch, &sc_if->msk_softc->msk_mtx, 0); 1554 msk_sysctl_node(sc_if); 1555 1556 if ((error = msk_txrx_dma_alloc(sc_if) != 0)) 1557 goto fail; 1558 msk_rx_dma_jalloc(sc_if); 1559 1560 ifp = sc_if->msk_ifp = if_alloc(IFT_ETHER); 1561 if (ifp == NULL) { 1562 device_printf(sc_if->msk_if_dev, "can not if_alloc()\n"); 1563 error = ENOSPC; 1564 goto fail; 1565 } 1566 ifp->if_softc = sc_if; 1567 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1568 ifp->if_mtu = ETHERMTU; 1569 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1570 ifp->if_capabilities = IFCAP_TXCSUM | IFCAP_TSO4; 1571 /* 1572 * Enable Rx checksum offloading if controller supports 1573 * new descriptor formant and controller is not Yukon XL. 1574 */ 1575 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0 && 1576 sc->msk_hw_id != CHIP_ID_YUKON_XL) 1577 ifp->if_capabilities |= IFCAP_RXCSUM; 1578 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) != 0 && 1579 (sc_if->msk_flags & MSK_FLAG_NORX_CSUM) == 0) 1580 ifp->if_capabilities |= IFCAP_RXCSUM; 1581 ifp->if_hwassist = MSK_CSUM_FEATURES | CSUM_TSO; 1582 ifp->if_capenable = ifp->if_capabilities; 1583 ifp->if_ioctl = msk_ioctl; 1584 ifp->if_start = msk_start; 1585 ifp->if_init = msk_init; 1586 IFQ_SET_MAXLEN(&ifp->if_snd, MSK_TX_RING_CNT - 1); 1587 ifp->if_snd.ifq_drv_maxlen = MSK_TX_RING_CNT - 1; 1588 IFQ_SET_READY(&ifp->if_snd); 1589 /* 1590 * Get station address for this interface. Note that 1591 * dual port cards actually come with three station 1592 * addresses: one for each port, plus an extra. The 1593 * extra one is used by the SysKonnect driver software 1594 * as a 'virtual' station address for when both ports 1595 * are operating in failover mode. Currently we don't 1596 * use this extra address. 1597 */ 1598 MSK_IF_LOCK(sc_if); 1599 for (i = 0; i < ETHER_ADDR_LEN; i++) 1600 eaddr[i] = CSR_READ_1(sc, B2_MAC_1 + (port * 8) + i); 1601 1602 /* 1603 * Call MI attach routine. Can't hold locks when calling into ether_*. 1604 */ 1605 MSK_IF_UNLOCK(sc_if); 1606 ether_ifattach(ifp, eaddr); 1607 MSK_IF_LOCK(sc_if); 1608 1609 /* VLAN capability setup */ 1610 ifp->if_capabilities |= IFCAP_VLAN_MTU; 1611 if ((sc_if->msk_flags & MSK_FLAG_NOHWVLAN) == 0) { 1612 /* 1613 * Due to Tx checksum offload hardware bugs, msk(4) manually 1614 * computes checksum for short frames. For VLAN tagged frames 1615 * this workaround does not work so disable checksum offload 1616 * for VLAN interface. 1617 */ 1618 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWTSO; 1619 /* 1620 * Enable Rx checksum offloading for VLAN taggedd frames 1621 * if controller support new descriptor format. 1622 */ 1623 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) != 0 && 1624 (sc_if->msk_flags & MSK_FLAG_NORX_CSUM) == 0) 1625 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM; 1626 } 1627 ifp->if_capenable = ifp->if_capabilities; 1628 1629 /* 1630 * Tell the upper layer(s) we support long frames. 1631 * Must appear after the call to ether_ifattach() because 1632 * ether_ifattach() sets ifi_hdrlen to the default value. 1633 */ 1634 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1635 1636 /* 1637 * Do miibus setup. 1638 */ 1639 MSK_IF_UNLOCK(sc_if); 1640 error = mii_phy_probe(dev, &sc_if->msk_miibus, msk_mediachange, 1641 msk_mediastatus); 1642 if (error != 0) { 1643 device_printf(sc_if->msk_if_dev, "no PHY found!\n"); 1644 ether_ifdetach(ifp); 1645 error = ENXIO; 1646 goto fail; 1647 } 1648 1649 fail: 1650 if (error != 0) { 1651 /* Access should be ok even though lock has been dropped */ 1652 sc->msk_if[port] = NULL; 1653 msk_detach(dev); 1654 } 1655 1656 return (error); 1657 } 1658 1659 /* 1660 * Attach the interface. Allocate softc structures, do ifmedia 1661 * setup and ethernet/BPF attach. 1662 */ 1663 static int 1664 mskc_attach(device_t dev) 1665 { 1666 struct msk_softc *sc; 1667 struct msk_mii_data *mmd; 1668 int error, msic, msir, reg; 1669 1670 sc = device_get_softc(dev); 1671 sc->msk_dev = dev; 1672 mtx_init(&sc->msk_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1673 MTX_DEF); 1674 1675 /* 1676 * Map control/status registers. 1677 */ 1678 pci_enable_busmaster(dev); 1679 1680 /* Allocate I/O resource */ 1681 #ifdef MSK_USEIOSPACE 1682 sc->msk_res_spec = msk_res_spec_io; 1683 #else 1684 sc->msk_res_spec = msk_res_spec_mem; 1685 #endif 1686 sc->msk_irq_spec = msk_irq_spec_legacy; 1687 error = bus_alloc_resources(dev, sc->msk_res_spec, sc->msk_res); 1688 if (error) { 1689 if (sc->msk_res_spec == msk_res_spec_mem) 1690 sc->msk_res_spec = msk_res_spec_io; 1691 else 1692 sc->msk_res_spec = msk_res_spec_mem; 1693 error = bus_alloc_resources(dev, sc->msk_res_spec, sc->msk_res); 1694 if (error) { 1695 device_printf(dev, "couldn't allocate %s resources\n", 1696 sc->msk_res_spec == msk_res_spec_mem ? "memory" : 1697 "I/O"); 1698 mtx_destroy(&sc->msk_mtx); 1699 return (ENXIO); 1700 } 1701 } 1702 1703 CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR); 1704 sc->msk_hw_id = CSR_READ_1(sc, B2_CHIP_ID); 1705 sc->msk_hw_rev = (CSR_READ_1(sc, B2_MAC_CFG) >> 4) & 0x0f; 1706 /* Bail out if chip is not recognized. */ 1707 if (sc->msk_hw_id < CHIP_ID_YUKON_XL || 1708 sc->msk_hw_id > CHIP_ID_YUKON_UL_2 || 1709 sc->msk_hw_id == CHIP_ID_YUKON_SUPR) { 1710 device_printf(dev, "unknown device: id=0x%02x, rev=0x%02x\n", 1711 sc->msk_hw_id, sc->msk_hw_rev); 1712 mtx_destroy(&sc->msk_mtx); 1713 return (ENXIO); 1714 } 1715 1716 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 1717 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 1718 OID_AUTO, "process_limit", CTLTYPE_INT | CTLFLAG_RW, 1719 &sc->msk_process_limit, 0, sysctl_hw_msk_proc_limit, "I", 1720 "max number of Rx events to process"); 1721 1722 sc->msk_process_limit = MSK_PROC_DEFAULT; 1723 error = resource_int_value(device_get_name(dev), device_get_unit(dev), 1724 "process_limit", &sc->msk_process_limit); 1725 if (error == 0) { 1726 if (sc->msk_process_limit < MSK_PROC_MIN || 1727 sc->msk_process_limit > MSK_PROC_MAX) { 1728 device_printf(dev, "process_limit value out of range; " 1729 "using default: %d\n", MSK_PROC_DEFAULT); 1730 sc->msk_process_limit = MSK_PROC_DEFAULT; 1731 } 1732 } 1733 1734 sc->msk_int_holdoff = MSK_INT_HOLDOFF_DEFAULT; 1735 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 1736 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 1737 "int_holdoff", CTLFLAG_RW, &sc->msk_int_holdoff, 0, 1738 "Maximum number of time to delay interrupts"); 1739 resource_int_value(device_get_name(dev), device_get_unit(dev), 1740 "int_holdoff", &sc->msk_int_holdoff); 1741 1742 /* Soft reset. */ 1743 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); 1744 CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR); 1745 sc->msk_pmd = CSR_READ_1(sc, B2_PMD_TYP); 1746 /* Check number of MACs. */ 1747 sc->msk_num_port = 1; 1748 if ((CSR_READ_1(sc, B2_Y2_HW_RES) & CFG_DUAL_MAC_MSK) == 1749 CFG_DUAL_MAC_MSK) { 1750 if (!(CSR_READ_1(sc, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC)) 1751 sc->msk_num_port++; 1752 } 1753 1754 /* Check bus type. */ 1755 if (pci_find_extcap(sc->msk_dev, PCIY_EXPRESS, ®) == 0) { 1756 sc->msk_bustype = MSK_PEX_BUS; 1757 sc->msk_expcap = reg; 1758 } else if (pci_find_extcap(sc->msk_dev, PCIY_PCIX, ®) == 0) { 1759 sc->msk_bustype = MSK_PCIX_BUS; 1760 sc->msk_pcixcap = reg; 1761 } else 1762 sc->msk_bustype = MSK_PCI_BUS; 1763 1764 switch (sc->msk_hw_id) { 1765 case CHIP_ID_YUKON_EC: 1766 sc->msk_clock = 125; /* 125 MHz */ 1767 sc->msk_pflags |= MSK_FLAG_JUMBO; 1768 break; 1769 case CHIP_ID_YUKON_EC_U: 1770 sc->msk_clock = 125; /* 125 MHz */ 1771 sc->msk_pflags |= MSK_FLAG_JUMBO | MSK_FLAG_JUMBO_NOCSUM; 1772 break; 1773 case CHIP_ID_YUKON_EX: 1774 sc->msk_clock = 125; /* 125 MHz */ 1775 sc->msk_pflags |= MSK_FLAG_JUMBO | MSK_FLAG_DESCV2 | 1776 MSK_FLAG_AUTOTX_CSUM; 1777 /* 1778 * Yukon Extreme seems to have silicon bug for 1779 * automatic Tx checksum calculation capability. 1780 */ 1781 if (sc->msk_hw_rev == CHIP_REV_YU_EX_B0) 1782 sc->msk_pflags &= ~MSK_FLAG_AUTOTX_CSUM; 1783 /* 1784 * Yukon Extreme A0 could not use store-and-forward 1785 * for jumbo frames, so disable Tx checksum 1786 * offloading for jumbo frames. 1787 */ 1788 if (sc->msk_hw_rev == CHIP_REV_YU_EX_A0) 1789 sc->msk_pflags |= MSK_FLAG_JUMBO_NOCSUM; 1790 break; 1791 case CHIP_ID_YUKON_FE: 1792 sc->msk_clock = 100; /* 100 MHz */ 1793 sc->msk_pflags |= MSK_FLAG_FASTETHER; 1794 break; 1795 case CHIP_ID_YUKON_FE_P: 1796 sc->msk_clock = 50; /* 50 MHz */ 1797 sc->msk_pflags |= MSK_FLAG_FASTETHER | MSK_FLAG_DESCV2 | 1798 MSK_FLAG_AUTOTX_CSUM; 1799 if (sc->msk_hw_rev == CHIP_REV_YU_FE_P_A0) { 1800 /* 1801 * XXX 1802 * FE+ A0 has status LE writeback bug so msk(4) 1803 * does not rely on status word of received frame 1804 * in msk_rxeof() which in turn disables all 1805 * hardware assistance bits reported by the status 1806 * word as well as validity of the recevied frame. 1807 * Just pass received frames to upper stack with 1808 * minimal test and let upper stack handle them. 1809 */ 1810 sc->msk_pflags |= MSK_FLAG_NOHWVLAN | 1811 MSK_FLAG_NORXCHK | MSK_FLAG_NORX_CSUM; 1812 } 1813 break; 1814 case CHIP_ID_YUKON_XL: 1815 sc->msk_clock = 156; /* 156 MHz */ 1816 sc->msk_pflags |= MSK_FLAG_JUMBO; 1817 break; 1818 case CHIP_ID_YUKON_UL_2: 1819 sc->msk_clock = 125; /* 125 MHz */ 1820 sc->msk_pflags |= MSK_FLAG_JUMBO; 1821 break; 1822 default: 1823 sc->msk_clock = 156; /* 156 MHz */ 1824 break; 1825 } 1826 1827 /* Allocate IRQ resources. */ 1828 msic = pci_msi_count(dev); 1829 if (bootverbose) 1830 device_printf(dev, "MSI count : %d\n", msic); 1831 if (legacy_intr != 0) 1832 msi_disable = 1; 1833 if (msi_disable == 0 && msic > 0) { 1834 msir = 1; 1835 if (pci_alloc_msi(dev, &msir) == 0) { 1836 if (msir == 1) { 1837 sc->msk_pflags |= MSK_FLAG_MSI; 1838 sc->msk_irq_spec = msk_irq_spec_msi; 1839 } else 1840 pci_release_msi(dev); 1841 } 1842 } 1843 1844 error = bus_alloc_resources(dev, sc->msk_irq_spec, sc->msk_irq); 1845 if (error) { 1846 device_printf(dev, "couldn't allocate IRQ resources\n"); 1847 goto fail; 1848 } 1849 1850 if ((error = msk_status_dma_alloc(sc)) != 0) 1851 goto fail; 1852 1853 /* Set base interrupt mask. */ 1854 sc->msk_intrmask = Y2_IS_HW_ERR | Y2_IS_STAT_BMU; 1855 sc->msk_intrhwemask = Y2_IS_TIST_OV | Y2_IS_MST_ERR | 1856 Y2_IS_IRQ_STAT | Y2_IS_PCI_EXP | Y2_IS_PCI_NEXP; 1857 1858 /* Reset the adapter. */ 1859 mskc_reset(sc); 1860 1861 if ((error = mskc_setup_rambuffer(sc)) != 0) 1862 goto fail; 1863 1864 sc->msk_devs[MSK_PORT_A] = device_add_child(dev, "msk", -1); 1865 if (sc->msk_devs[MSK_PORT_A] == NULL) { 1866 device_printf(dev, "failed to add child for PORT_A\n"); 1867 error = ENXIO; 1868 goto fail; 1869 } 1870 mmd = malloc(sizeof(struct msk_mii_data), M_DEVBUF, M_WAITOK | M_ZERO); 1871 if (mmd == NULL) { 1872 device_printf(dev, "failed to allocate memory for " 1873 "ivars of PORT_A\n"); 1874 error = ENXIO; 1875 goto fail; 1876 } 1877 mmd->port = MSK_PORT_A; 1878 mmd->pmd = sc->msk_pmd; 1879 if (sc->msk_pmd == 'L' || sc->msk_pmd == 'S' || sc->msk_pmd == 'P') 1880 mmd->mii_flags |= MIIF_HAVEFIBER; 1881 device_set_ivars(sc->msk_devs[MSK_PORT_A], mmd); 1882 1883 if (sc->msk_num_port > 1) { 1884 sc->msk_devs[MSK_PORT_B] = device_add_child(dev, "msk", -1); 1885 if (sc->msk_devs[MSK_PORT_B] == NULL) { 1886 device_printf(dev, "failed to add child for PORT_B\n"); 1887 error = ENXIO; 1888 goto fail; 1889 } 1890 mmd = malloc(sizeof(struct msk_mii_data), M_DEVBUF, M_WAITOK | M_ZERO); 1891 if (mmd == NULL) { 1892 device_printf(dev, "failed to allocate memory for " 1893 "ivars of PORT_B\n"); 1894 error = ENXIO; 1895 goto fail; 1896 } 1897 mmd->port = MSK_PORT_B; 1898 mmd->pmd = sc->msk_pmd; 1899 if (sc->msk_pmd == 'L' || sc->msk_pmd == 'S' || sc->msk_pmd == 'P') 1900 mmd->mii_flags |= MIIF_HAVEFIBER; 1901 device_set_ivars(sc->msk_devs[MSK_PORT_B], mmd); 1902 } 1903 1904 error = bus_generic_attach(dev); 1905 if (error) { 1906 device_printf(dev, "failed to attach port(s)\n"); 1907 goto fail; 1908 } 1909 1910 /* Hook interrupt last to avoid having to lock softc. */ 1911 error = bus_setup_intr(dev, sc->msk_irq[0], INTR_TYPE_NET | 1912 INTR_MPSAFE, NULL, msk_intr, sc, &sc->msk_intrhand); 1913 if (error != 0) { 1914 device_printf(dev, "couldn't set up interrupt handler\n"); 1915 goto fail; 1916 } 1917 fail: 1918 if (error != 0) 1919 mskc_detach(dev); 1920 1921 return (error); 1922 } 1923 1924 /* 1925 * Shutdown hardware and free up resources. This can be called any 1926 * time after the mutex has been initialized. It is called in both 1927 * the error case in attach and the normal detach case so it needs 1928 * to be careful about only freeing resources that have actually been 1929 * allocated. 1930 */ 1931 static int 1932 msk_detach(device_t dev) 1933 { 1934 struct msk_softc *sc; 1935 struct msk_if_softc *sc_if; 1936 struct ifnet *ifp; 1937 1938 sc_if = device_get_softc(dev); 1939 KASSERT(mtx_initialized(&sc_if->msk_softc->msk_mtx), 1940 ("msk mutex not initialized in msk_detach")); 1941 MSK_IF_LOCK(sc_if); 1942 1943 ifp = sc_if->msk_ifp; 1944 if (device_is_attached(dev)) { 1945 /* XXX */ 1946 sc_if->msk_flags |= MSK_FLAG_DETACH; 1947 msk_stop(sc_if); 1948 /* Can't hold locks while calling detach. */ 1949 MSK_IF_UNLOCK(sc_if); 1950 callout_drain(&sc_if->msk_tick_ch); 1951 ether_ifdetach(ifp); 1952 MSK_IF_LOCK(sc_if); 1953 } 1954 1955 /* 1956 * We're generally called from mskc_detach() which is using 1957 * device_delete_child() to get to here. It's already trashed 1958 * miibus for us, so don't do it here or we'll panic. 1959 * 1960 * if (sc_if->msk_miibus != NULL) { 1961 * device_delete_child(dev, sc_if->msk_miibus); 1962 * sc_if->msk_miibus = NULL; 1963 * } 1964 */ 1965 1966 msk_rx_dma_jfree(sc_if); 1967 msk_txrx_dma_free(sc_if); 1968 bus_generic_detach(dev); 1969 1970 if (ifp) 1971 if_free(ifp); 1972 sc = sc_if->msk_softc; 1973 sc->msk_if[sc_if->msk_port] = NULL; 1974 MSK_IF_UNLOCK(sc_if); 1975 1976 return (0); 1977 } 1978 1979 static int 1980 mskc_detach(device_t dev) 1981 { 1982 struct msk_softc *sc; 1983 1984 sc = device_get_softc(dev); 1985 KASSERT(mtx_initialized(&sc->msk_mtx), ("msk mutex not initialized")); 1986 1987 if (device_is_alive(dev)) { 1988 if (sc->msk_devs[MSK_PORT_A] != NULL) { 1989 free(device_get_ivars(sc->msk_devs[MSK_PORT_A]), 1990 M_DEVBUF); 1991 device_delete_child(dev, sc->msk_devs[MSK_PORT_A]); 1992 } 1993 if (sc->msk_devs[MSK_PORT_B] != NULL) { 1994 free(device_get_ivars(sc->msk_devs[MSK_PORT_B]), 1995 M_DEVBUF); 1996 device_delete_child(dev, sc->msk_devs[MSK_PORT_B]); 1997 } 1998 bus_generic_detach(dev); 1999 } 2000 2001 /* Disable all interrupts. */ 2002 CSR_WRITE_4(sc, B0_IMSK, 0); 2003 CSR_READ_4(sc, B0_IMSK); 2004 CSR_WRITE_4(sc, B0_HWE_IMSK, 0); 2005 CSR_READ_4(sc, B0_HWE_IMSK); 2006 2007 /* LED Off. */ 2008 CSR_WRITE_2(sc, B0_CTST, Y2_LED_STAT_OFF); 2009 2010 /* Put hardware reset. */ 2011 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); 2012 2013 msk_status_dma_free(sc); 2014 2015 if (sc->msk_intrhand) { 2016 bus_teardown_intr(dev, sc->msk_irq[0], sc->msk_intrhand); 2017 sc->msk_intrhand = NULL; 2018 } 2019 bus_release_resources(dev, sc->msk_irq_spec, sc->msk_irq); 2020 if ((sc->msk_pflags & MSK_FLAG_MSI) != 0) 2021 pci_release_msi(dev); 2022 bus_release_resources(dev, sc->msk_res_spec, sc->msk_res); 2023 mtx_destroy(&sc->msk_mtx); 2024 2025 return (0); 2026 } 2027 2028 struct msk_dmamap_arg { 2029 bus_addr_t msk_busaddr; 2030 }; 2031 2032 static void 2033 msk_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 2034 { 2035 struct msk_dmamap_arg *ctx; 2036 2037 if (error != 0) 2038 return; 2039 ctx = arg; 2040 ctx->msk_busaddr = segs[0].ds_addr; 2041 } 2042 2043 /* Create status DMA region. */ 2044 static int 2045 msk_status_dma_alloc(struct msk_softc *sc) 2046 { 2047 struct msk_dmamap_arg ctx; 2048 int error; 2049 2050 error = bus_dma_tag_create( 2051 bus_get_dma_tag(sc->msk_dev), /* parent */ 2052 MSK_STAT_ALIGN, 0, /* alignment, boundary */ 2053 BUS_SPACE_MAXADDR, /* lowaddr */ 2054 BUS_SPACE_MAXADDR, /* highaddr */ 2055 NULL, NULL, /* filter, filterarg */ 2056 MSK_STAT_RING_SZ, /* maxsize */ 2057 1, /* nsegments */ 2058 MSK_STAT_RING_SZ, /* maxsegsize */ 2059 0, /* flags */ 2060 NULL, NULL, /* lockfunc, lockarg */ 2061 &sc->msk_stat_tag); 2062 if (error != 0) { 2063 device_printf(sc->msk_dev, 2064 "failed to create status DMA tag\n"); 2065 return (error); 2066 } 2067 2068 /* Allocate DMA'able memory and load the DMA map for status ring. */ 2069 error = bus_dmamem_alloc(sc->msk_stat_tag, 2070 (void **)&sc->msk_stat_ring, BUS_DMA_WAITOK | BUS_DMA_COHERENT | 2071 BUS_DMA_ZERO, &sc->msk_stat_map); 2072 if (error != 0) { 2073 device_printf(sc->msk_dev, 2074 "failed to allocate DMA'able memory for status ring\n"); 2075 return (error); 2076 } 2077 2078 ctx.msk_busaddr = 0; 2079 error = bus_dmamap_load(sc->msk_stat_tag, 2080 sc->msk_stat_map, sc->msk_stat_ring, MSK_STAT_RING_SZ, 2081 msk_dmamap_cb, &ctx, 0); 2082 if (error != 0) { 2083 device_printf(sc->msk_dev, 2084 "failed to load DMA'able memory for status ring\n"); 2085 return (error); 2086 } 2087 sc->msk_stat_ring_paddr = ctx.msk_busaddr; 2088 2089 return (0); 2090 } 2091 2092 static void 2093 msk_status_dma_free(struct msk_softc *sc) 2094 { 2095 2096 /* Destroy status block. */ 2097 if (sc->msk_stat_tag) { 2098 if (sc->msk_stat_map) { 2099 bus_dmamap_unload(sc->msk_stat_tag, sc->msk_stat_map); 2100 if (sc->msk_stat_ring) { 2101 bus_dmamem_free(sc->msk_stat_tag, 2102 sc->msk_stat_ring, sc->msk_stat_map); 2103 sc->msk_stat_ring = NULL; 2104 } 2105 sc->msk_stat_map = NULL; 2106 } 2107 bus_dma_tag_destroy(sc->msk_stat_tag); 2108 sc->msk_stat_tag = NULL; 2109 } 2110 } 2111 2112 static int 2113 msk_txrx_dma_alloc(struct msk_if_softc *sc_if) 2114 { 2115 struct msk_dmamap_arg ctx; 2116 struct msk_txdesc *txd; 2117 struct msk_rxdesc *rxd; 2118 bus_size_t rxalign; 2119 int error, i; 2120 2121 /* Create parent DMA tag. */ 2122 /* 2123 * XXX 2124 * It seems that Yukon II supports full 64bits DMA operations. But 2125 * it needs two descriptors(list elements) for 64bits DMA operations. 2126 * Since we don't know what DMA address mappings(32bits or 64bits) 2127 * would be used in advance for each mbufs, we limits its DMA space 2128 * to be in range of 32bits address space. Otherwise, we should check 2129 * what DMA address is used and chain another descriptor for the 2130 * 64bits DMA operation. This also means descriptor ring size is 2131 * variable. Limiting DMA address to be in 32bit address space greatly 2132 * simplyfies descriptor handling and possibly would increase 2133 * performance a bit due to efficient handling of descriptors. 2134 * Apart from harassing checksum offloading mechanisms, it seems 2135 * it's really bad idea to use a seperate descriptor for 64bit 2136 * DMA operation to save small descriptor memory. Anyway, I've 2137 * never seen these exotic scheme on ethernet interface hardware. 2138 */ 2139 error = bus_dma_tag_create( 2140 bus_get_dma_tag(sc_if->msk_if_dev), /* parent */ 2141 1, 0, /* alignment, boundary */ 2142 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 2143 BUS_SPACE_MAXADDR, /* highaddr */ 2144 NULL, NULL, /* filter, filterarg */ 2145 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 2146 0, /* nsegments */ 2147 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 2148 0, /* flags */ 2149 NULL, NULL, /* lockfunc, lockarg */ 2150 &sc_if->msk_cdata.msk_parent_tag); 2151 if (error != 0) { 2152 device_printf(sc_if->msk_if_dev, 2153 "failed to create parent DMA tag\n"); 2154 goto fail; 2155 } 2156 /* Create tag for Tx ring. */ 2157 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2158 MSK_RING_ALIGN, 0, /* alignment, boundary */ 2159 BUS_SPACE_MAXADDR, /* lowaddr */ 2160 BUS_SPACE_MAXADDR, /* highaddr */ 2161 NULL, NULL, /* filter, filterarg */ 2162 MSK_TX_RING_SZ, /* maxsize */ 2163 1, /* nsegments */ 2164 MSK_TX_RING_SZ, /* maxsegsize */ 2165 0, /* flags */ 2166 NULL, NULL, /* lockfunc, lockarg */ 2167 &sc_if->msk_cdata.msk_tx_ring_tag); 2168 if (error != 0) { 2169 device_printf(sc_if->msk_if_dev, 2170 "failed to create Tx ring DMA tag\n"); 2171 goto fail; 2172 } 2173 2174 /* Create tag for Rx ring. */ 2175 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2176 MSK_RING_ALIGN, 0, /* alignment, boundary */ 2177 BUS_SPACE_MAXADDR, /* lowaddr */ 2178 BUS_SPACE_MAXADDR, /* highaddr */ 2179 NULL, NULL, /* filter, filterarg */ 2180 MSK_RX_RING_SZ, /* maxsize */ 2181 1, /* nsegments */ 2182 MSK_RX_RING_SZ, /* maxsegsize */ 2183 0, /* flags */ 2184 NULL, NULL, /* lockfunc, lockarg */ 2185 &sc_if->msk_cdata.msk_rx_ring_tag); 2186 if (error != 0) { 2187 device_printf(sc_if->msk_if_dev, 2188 "failed to create Rx ring DMA tag\n"); 2189 goto fail; 2190 } 2191 2192 /* Create tag for Tx buffers. */ 2193 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2194 1, 0, /* alignment, boundary */ 2195 BUS_SPACE_MAXADDR, /* lowaddr */ 2196 BUS_SPACE_MAXADDR, /* highaddr */ 2197 NULL, NULL, /* filter, filterarg */ 2198 MSK_TSO_MAXSIZE, /* maxsize */ 2199 MSK_MAXTXSEGS, /* nsegments */ 2200 MSK_TSO_MAXSGSIZE, /* maxsegsize */ 2201 0, /* flags */ 2202 NULL, NULL, /* lockfunc, lockarg */ 2203 &sc_if->msk_cdata.msk_tx_tag); 2204 if (error != 0) { 2205 device_printf(sc_if->msk_if_dev, 2206 "failed to create Tx DMA tag\n"); 2207 goto fail; 2208 } 2209 2210 rxalign = 1; 2211 /* 2212 * Workaround hardware hang which seems to happen when Rx buffer 2213 * is not aligned on multiple of FIFO word(8 bytes). 2214 */ 2215 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) != 0) 2216 rxalign = MSK_RX_BUF_ALIGN; 2217 /* Create tag for Rx buffers. */ 2218 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2219 rxalign, 0, /* alignment, boundary */ 2220 BUS_SPACE_MAXADDR, /* lowaddr */ 2221 BUS_SPACE_MAXADDR, /* highaddr */ 2222 NULL, NULL, /* filter, filterarg */ 2223 MCLBYTES, /* maxsize */ 2224 1, /* nsegments */ 2225 MCLBYTES, /* maxsegsize */ 2226 0, /* flags */ 2227 NULL, NULL, /* lockfunc, lockarg */ 2228 &sc_if->msk_cdata.msk_rx_tag); 2229 if (error != 0) { 2230 device_printf(sc_if->msk_if_dev, 2231 "failed to create Rx DMA tag\n"); 2232 goto fail; 2233 } 2234 2235 /* Allocate DMA'able memory and load the DMA map for Tx ring. */ 2236 error = bus_dmamem_alloc(sc_if->msk_cdata.msk_tx_ring_tag, 2237 (void **)&sc_if->msk_rdata.msk_tx_ring, BUS_DMA_WAITOK | 2238 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc_if->msk_cdata.msk_tx_ring_map); 2239 if (error != 0) { 2240 device_printf(sc_if->msk_if_dev, 2241 "failed to allocate DMA'able memory for Tx ring\n"); 2242 goto fail; 2243 } 2244 2245 ctx.msk_busaddr = 0; 2246 error = bus_dmamap_load(sc_if->msk_cdata.msk_tx_ring_tag, 2247 sc_if->msk_cdata.msk_tx_ring_map, sc_if->msk_rdata.msk_tx_ring, 2248 MSK_TX_RING_SZ, msk_dmamap_cb, &ctx, 0); 2249 if (error != 0) { 2250 device_printf(sc_if->msk_if_dev, 2251 "failed to load DMA'able memory for Tx ring\n"); 2252 goto fail; 2253 } 2254 sc_if->msk_rdata.msk_tx_ring_paddr = ctx.msk_busaddr; 2255 2256 /* Allocate DMA'able memory and load the DMA map for Rx ring. */ 2257 error = bus_dmamem_alloc(sc_if->msk_cdata.msk_rx_ring_tag, 2258 (void **)&sc_if->msk_rdata.msk_rx_ring, BUS_DMA_WAITOK | 2259 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc_if->msk_cdata.msk_rx_ring_map); 2260 if (error != 0) { 2261 device_printf(sc_if->msk_if_dev, 2262 "failed to allocate DMA'able memory for Rx ring\n"); 2263 goto fail; 2264 } 2265 2266 ctx.msk_busaddr = 0; 2267 error = bus_dmamap_load(sc_if->msk_cdata.msk_rx_ring_tag, 2268 sc_if->msk_cdata.msk_rx_ring_map, sc_if->msk_rdata.msk_rx_ring, 2269 MSK_RX_RING_SZ, msk_dmamap_cb, &ctx, 0); 2270 if (error != 0) { 2271 device_printf(sc_if->msk_if_dev, 2272 "failed to load DMA'able memory for Rx ring\n"); 2273 goto fail; 2274 } 2275 sc_if->msk_rdata.msk_rx_ring_paddr = ctx.msk_busaddr; 2276 2277 /* Create DMA maps for Tx buffers. */ 2278 for (i = 0; i < MSK_TX_RING_CNT; i++) { 2279 txd = &sc_if->msk_cdata.msk_txdesc[i]; 2280 txd->tx_m = NULL; 2281 txd->tx_dmamap = NULL; 2282 error = bus_dmamap_create(sc_if->msk_cdata.msk_tx_tag, 0, 2283 &txd->tx_dmamap); 2284 if (error != 0) { 2285 device_printf(sc_if->msk_if_dev, 2286 "failed to create Tx dmamap\n"); 2287 goto fail; 2288 } 2289 } 2290 /* Create DMA maps for Rx buffers. */ 2291 if ((error = bus_dmamap_create(sc_if->msk_cdata.msk_rx_tag, 0, 2292 &sc_if->msk_cdata.msk_rx_sparemap)) != 0) { 2293 device_printf(sc_if->msk_if_dev, 2294 "failed to create spare Rx dmamap\n"); 2295 goto fail; 2296 } 2297 for (i = 0; i < MSK_RX_RING_CNT; i++) { 2298 rxd = &sc_if->msk_cdata.msk_rxdesc[i]; 2299 rxd->rx_m = NULL; 2300 rxd->rx_dmamap = NULL; 2301 error = bus_dmamap_create(sc_if->msk_cdata.msk_rx_tag, 0, 2302 &rxd->rx_dmamap); 2303 if (error != 0) { 2304 device_printf(sc_if->msk_if_dev, 2305 "failed to create Rx dmamap\n"); 2306 goto fail; 2307 } 2308 } 2309 2310 fail: 2311 return (error); 2312 } 2313 2314 static int 2315 msk_rx_dma_jalloc(struct msk_if_softc *sc_if) 2316 { 2317 struct msk_dmamap_arg ctx; 2318 struct msk_rxdesc *jrxd; 2319 bus_size_t rxalign; 2320 int error, i; 2321 2322 if (jumbo_disable != 0 || (sc_if->msk_flags & MSK_FLAG_JUMBO) == 0) { 2323 sc_if->msk_flags &= ~MSK_FLAG_JUMBO; 2324 device_printf(sc_if->msk_if_dev, 2325 "disabling jumbo frame support\n"); 2326 return (0); 2327 } 2328 /* Create tag for jumbo Rx ring. */ 2329 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2330 MSK_RING_ALIGN, 0, /* alignment, boundary */ 2331 BUS_SPACE_MAXADDR, /* lowaddr */ 2332 BUS_SPACE_MAXADDR, /* highaddr */ 2333 NULL, NULL, /* filter, filterarg */ 2334 MSK_JUMBO_RX_RING_SZ, /* maxsize */ 2335 1, /* nsegments */ 2336 MSK_JUMBO_RX_RING_SZ, /* maxsegsize */ 2337 0, /* flags */ 2338 NULL, NULL, /* lockfunc, lockarg */ 2339 &sc_if->msk_cdata.msk_jumbo_rx_ring_tag); 2340 if (error != 0) { 2341 device_printf(sc_if->msk_if_dev, 2342 "failed to create jumbo Rx ring DMA tag\n"); 2343 goto jumbo_fail; 2344 } 2345 2346 rxalign = 1; 2347 /* 2348 * Workaround hardware hang which seems to happen when Rx buffer 2349 * is not aligned on multiple of FIFO word(8 bytes). 2350 */ 2351 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) != 0) 2352 rxalign = MSK_RX_BUF_ALIGN; 2353 /* Create tag for jumbo Rx buffers. */ 2354 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2355 rxalign, 0, /* alignment, boundary */ 2356 BUS_SPACE_MAXADDR, /* lowaddr */ 2357 BUS_SPACE_MAXADDR, /* highaddr */ 2358 NULL, NULL, /* filter, filterarg */ 2359 MJUM9BYTES, /* maxsize */ 2360 1, /* nsegments */ 2361 MJUM9BYTES, /* maxsegsize */ 2362 0, /* flags */ 2363 NULL, NULL, /* lockfunc, lockarg */ 2364 &sc_if->msk_cdata.msk_jumbo_rx_tag); 2365 if (error != 0) { 2366 device_printf(sc_if->msk_if_dev, 2367 "failed to create jumbo Rx DMA tag\n"); 2368 goto jumbo_fail; 2369 } 2370 2371 /* Allocate DMA'able memory and load the DMA map for jumbo Rx ring. */ 2372 error = bus_dmamem_alloc(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 2373 (void **)&sc_if->msk_rdata.msk_jumbo_rx_ring, 2374 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 2375 &sc_if->msk_cdata.msk_jumbo_rx_ring_map); 2376 if (error != 0) { 2377 device_printf(sc_if->msk_if_dev, 2378 "failed to allocate DMA'able memory for jumbo Rx ring\n"); 2379 goto jumbo_fail; 2380 } 2381 2382 ctx.msk_busaddr = 0; 2383 error = bus_dmamap_load(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 2384 sc_if->msk_cdata.msk_jumbo_rx_ring_map, 2385 sc_if->msk_rdata.msk_jumbo_rx_ring, MSK_JUMBO_RX_RING_SZ, 2386 msk_dmamap_cb, &ctx, 0); 2387 if (error != 0) { 2388 device_printf(sc_if->msk_if_dev, 2389 "failed to load DMA'able memory for jumbo Rx ring\n"); 2390 goto jumbo_fail; 2391 } 2392 sc_if->msk_rdata.msk_jumbo_rx_ring_paddr = ctx.msk_busaddr; 2393 2394 /* Create DMA maps for jumbo Rx buffers. */ 2395 if ((error = bus_dmamap_create(sc_if->msk_cdata.msk_jumbo_rx_tag, 0, 2396 &sc_if->msk_cdata.msk_jumbo_rx_sparemap)) != 0) { 2397 device_printf(sc_if->msk_if_dev, 2398 "failed to create spare jumbo Rx dmamap\n"); 2399 goto jumbo_fail; 2400 } 2401 for (i = 0; i < MSK_JUMBO_RX_RING_CNT; i++) { 2402 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[i]; 2403 jrxd->rx_m = NULL; 2404 jrxd->rx_dmamap = NULL; 2405 error = bus_dmamap_create(sc_if->msk_cdata.msk_jumbo_rx_tag, 0, 2406 &jrxd->rx_dmamap); 2407 if (error != 0) { 2408 device_printf(sc_if->msk_if_dev, 2409 "failed to create jumbo Rx dmamap\n"); 2410 goto jumbo_fail; 2411 } 2412 } 2413 2414 return (0); 2415 2416 jumbo_fail: 2417 msk_rx_dma_jfree(sc_if); 2418 device_printf(sc_if->msk_if_dev, "disabling jumbo frame support " 2419 "due to resource shortage\n"); 2420 sc_if->msk_flags &= ~MSK_FLAG_JUMBO; 2421 return (error); 2422 } 2423 2424 static void 2425 msk_txrx_dma_free(struct msk_if_softc *sc_if) 2426 { 2427 struct msk_txdesc *txd; 2428 struct msk_rxdesc *rxd; 2429 int i; 2430 2431 /* Tx ring. */ 2432 if (sc_if->msk_cdata.msk_tx_ring_tag) { 2433 if (sc_if->msk_cdata.msk_tx_ring_map) 2434 bus_dmamap_unload(sc_if->msk_cdata.msk_tx_ring_tag, 2435 sc_if->msk_cdata.msk_tx_ring_map); 2436 if (sc_if->msk_cdata.msk_tx_ring_map && 2437 sc_if->msk_rdata.msk_tx_ring) 2438 bus_dmamem_free(sc_if->msk_cdata.msk_tx_ring_tag, 2439 sc_if->msk_rdata.msk_tx_ring, 2440 sc_if->msk_cdata.msk_tx_ring_map); 2441 sc_if->msk_rdata.msk_tx_ring = NULL; 2442 sc_if->msk_cdata.msk_tx_ring_map = NULL; 2443 bus_dma_tag_destroy(sc_if->msk_cdata.msk_tx_ring_tag); 2444 sc_if->msk_cdata.msk_tx_ring_tag = NULL; 2445 } 2446 /* Rx ring. */ 2447 if (sc_if->msk_cdata.msk_rx_ring_tag) { 2448 if (sc_if->msk_cdata.msk_rx_ring_map) 2449 bus_dmamap_unload(sc_if->msk_cdata.msk_rx_ring_tag, 2450 sc_if->msk_cdata.msk_rx_ring_map); 2451 if (sc_if->msk_cdata.msk_rx_ring_map && 2452 sc_if->msk_rdata.msk_rx_ring) 2453 bus_dmamem_free(sc_if->msk_cdata.msk_rx_ring_tag, 2454 sc_if->msk_rdata.msk_rx_ring, 2455 sc_if->msk_cdata.msk_rx_ring_map); 2456 sc_if->msk_rdata.msk_rx_ring = NULL; 2457 sc_if->msk_cdata.msk_rx_ring_map = NULL; 2458 bus_dma_tag_destroy(sc_if->msk_cdata.msk_rx_ring_tag); 2459 sc_if->msk_cdata.msk_rx_ring_tag = NULL; 2460 } 2461 /* Tx buffers. */ 2462 if (sc_if->msk_cdata.msk_tx_tag) { 2463 for (i = 0; i < MSK_TX_RING_CNT; i++) { 2464 txd = &sc_if->msk_cdata.msk_txdesc[i]; 2465 if (txd->tx_dmamap) { 2466 bus_dmamap_destroy(sc_if->msk_cdata.msk_tx_tag, 2467 txd->tx_dmamap); 2468 txd->tx_dmamap = NULL; 2469 } 2470 } 2471 bus_dma_tag_destroy(sc_if->msk_cdata.msk_tx_tag); 2472 sc_if->msk_cdata.msk_tx_tag = NULL; 2473 } 2474 /* Rx buffers. */ 2475 if (sc_if->msk_cdata.msk_rx_tag) { 2476 for (i = 0; i < MSK_RX_RING_CNT; i++) { 2477 rxd = &sc_if->msk_cdata.msk_rxdesc[i]; 2478 if (rxd->rx_dmamap) { 2479 bus_dmamap_destroy(sc_if->msk_cdata.msk_rx_tag, 2480 rxd->rx_dmamap); 2481 rxd->rx_dmamap = NULL; 2482 } 2483 } 2484 if (sc_if->msk_cdata.msk_rx_sparemap) { 2485 bus_dmamap_destroy(sc_if->msk_cdata.msk_rx_tag, 2486 sc_if->msk_cdata.msk_rx_sparemap); 2487 sc_if->msk_cdata.msk_rx_sparemap = 0; 2488 } 2489 bus_dma_tag_destroy(sc_if->msk_cdata.msk_rx_tag); 2490 sc_if->msk_cdata.msk_rx_tag = NULL; 2491 } 2492 if (sc_if->msk_cdata.msk_parent_tag) { 2493 bus_dma_tag_destroy(sc_if->msk_cdata.msk_parent_tag); 2494 sc_if->msk_cdata.msk_parent_tag = NULL; 2495 } 2496 } 2497 2498 static void 2499 msk_rx_dma_jfree(struct msk_if_softc *sc_if) 2500 { 2501 struct msk_rxdesc *jrxd; 2502 int i; 2503 2504 /* Jumbo Rx ring. */ 2505 if (sc_if->msk_cdata.msk_jumbo_rx_ring_tag) { 2506 if (sc_if->msk_cdata.msk_jumbo_rx_ring_map) 2507 bus_dmamap_unload(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 2508 sc_if->msk_cdata.msk_jumbo_rx_ring_map); 2509 if (sc_if->msk_cdata.msk_jumbo_rx_ring_map && 2510 sc_if->msk_rdata.msk_jumbo_rx_ring) 2511 bus_dmamem_free(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 2512 sc_if->msk_rdata.msk_jumbo_rx_ring, 2513 sc_if->msk_cdata.msk_jumbo_rx_ring_map); 2514 sc_if->msk_rdata.msk_jumbo_rx_ring = NULL; 2515 sc_if->msk_cdata.msk_jumbo_rx_ring_map = NULL; 2516 bus_dma_tag_destroy(sc_if->msk_cdata.msk_jumbo_rx_ring_tag); 2517 sc_if->msk_cdata.msk_jumbo_rx_ring_tag = NULL; 2518 } 2519 /* Jumbo Rx buffers. */ 2520 if (sc_if->msk_cdata.msk_jumbo_rx_tag) { 2521 for (i = 0; i < MSK_JUMBO_RX_RING_CNT; i++) { 2522 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[i]; 2523 if (jrxd->rx_dmamap) { 2524 bus_dmamap_destroy( 2525 sc_if->msk_cdata.msk_jumbo_rx_tag, 2526 jrxd->rx_dmamap); 2527 jrxd->rx_dmamap = NULL; 2528 } 2529 } 2530 if (sc_if->msk_cdata.msk_jumbo_rx_sparemap) { 2531 bus_dmamap_destroy(sc_if->msk_cdata.msk_jumbo_rx_tag, 2532 sc_if->msk_cdata.msk_jumbo_rx_sparemap); 2533 sc_if->msk_cdata.msk_jumbo_rx_sparemap = 0; 2534 } 2535 bus_dma_tag_destroy(sc_if->msk_cdata.msk_jumbo_rx_tag); 2536 sc_if->msk_cdata.msk_jumbo_rx_tag = NULL; 2537 } 2538 } 2539 2540 static int 2541 msk_encap(struct msk_if_softc *sc_if, struct mbuf **m_head) 2542 { 2543 struct msk_txdesc *txd, *txd_last; 2544 struct msk_tx_desc *tx_le; 2545 struct mbuf *m; 2546 bus_dmamap_t map; 2547 bus_dma_segment_t txsegs[MSK_MAXTXSEGS]; 2548 uint32_t control, csum, prod, si; 2549 uint16_t offset, tcp_offset, tso_mtu; 2550 int error, i, nseg, tso; 2551 2552 MSK_IF_LOCK_ASSERT(sc_if); 2553 2554 tcp_offset = offset = 0; 2555 m = *m_head; 2556 if (((sc_if->msk_flags & MSK_FLAG_AUTOTX_CSUM) == 0 && 2557 (m->m_pkthdr.csum_flags & MSK_CSUM_FEATURES) != 0) || 2558 ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0 && 2559 (m->m_pkthdr.csum_flags & CSUM_TSO) != 0)) { 2560 /* 2561 * Since mbuf has no protocol specific structure information 2562 * in it we have to inspect protocol information here to 2563 * setup TSO and checksum offload. I don't know why Marvell 2564 * made a such decision in chip design because other GigE 2565 * hardwares normally takes care of all these chores in 2566 * hardware. However, TSO performance of Yukon II is very 2567 * good such that it's worth to implement it. 2568 */ 2569 struct ether_header *eh; 2570 struct ip *ip; 2571 struct tcphdr *tcp; 2572 2573 if (M_WRITABLE(m) == 0) { 2574 /* Get a writable copy. */ 2575 m = m_dup(*m_head, M_DONTWAIT); 2576 m_freem(*m_head); 2577 if (m == NULL) { 2578 *m_head = NULL; 2579 return (ENOBUFS); 2580 } 2581 *m_head = m; 2582 } 2583 2584 offset = sizeof(struct ether_header); 2585 m = m_pullup(m, offset); 2586 if (m == NULL) { 2587 *m_head = NULL; 2588 return (ENOBUFS); 2589 } 2590 eh = mtod(m, struct ether_header *); 2591 /* Check if hardware VLAN insertion is off. */ 2592 if (eh->ether_type == htons(ETHERTYPE_VLAN)) { 2593 offset = sizeof(struct ether_vlan_header); 2594 m = m_pullup(m, offset); 2595 if (m == NULL) { 2596 *m_head = NULL; 2597 return (ENOBUFS); 2598 } 2599 } 2600 m = m_pullup(m, offset + sizeof(struct ip)); 2601 if (m == NULL) { 2602 *m_head = NULL; 2603 return (ENOBUFS); 2604 } 2605 ip = (struct ip *)(mtod(m, char *) + offset); 2606 offset += (ip->ip_hl << 2); 2607 tcp_offset = offset; 2608 /* 2609 * It seems that Yukon II has Tx checksum offload bug for 2610 * small TCP packets that's less than 60 bytes in size 2611 * (e.g. TCP window probe packet, pure ACK packet). 2612 * Common work around like padding with zeros to make the 2613 * frame minimum ethernet frame size didn't work at all. 2614 * Instead of disabling checksum offload completely we 2615 * resort to S/W checksum routine when we encounter short 2616 * TCP frames. 2617 * Short UDP packets appear to be handled correctly by 2618 * Yukon II. Also I assume this bug does not happen on 2619 * controllers that use newer descriptor format or 2620 * automatic Tx checksum calaulcation. 2621 */ 2622 if ((sc_if->msk_flags & MSK_FLAG_AUTOTX_CSUM) == 0 && 2623 (m->m_pkthdr.len < MSK_MIN_FRAMELEN) && 2624 (m->m_pkthdr.csum_flags & CSUM_TCP) != 0) { 2625 m = m_pullup(m, offset + sizeof(struct tcphdr)); 2626 if (m == NULL) { 2627 *m_head = NULL; 2628 return (ENOBUFS); 2629 } 2630 *(uint16_t *)(m->m_data + offset + 2631 m->m_pkthdr.csum_data) = in_cksum_skip(m, 2632 m->m_pkthdr.len, offset); 2633 m->m_pkthdr.csum_flags &= ~CSUM_TCP; 2634 } 2635 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 2636 m = m_pullup(m, offset + sizeof(struct tcphdr)); 2637 if (m == NULL) { 2638 *m_head = NULL; 2639 return (ENOBUFS); 2640 } 2641 tcp = (struct tcphdr *)(mtod(m, char *) + offset); 2642 offset += (tcp->th_off << 2); 2643 } 2644 *m_head = m; 2645 } 2646 2647 prod = sc_if->msk_cdata.msk_tx_prod; 2648 txd = &sc_if->msk_cdata.msk_txdesc[prod]; 2649 txd_last = txd; 2650 map = txd->tx_dmamap; 2651 error = bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_tx_tag, map, 2652 *m_head, txsegs, &nseg, BUS_DMA_NOWAIT); 2653 if (error == EFBIG) { 2654 m = m_collapse(*m_head, M_DONTWAIT, MSK_MAXTXSEGS); 2655 if (m == NULL) { 2656 m_freem(*m_head); 2657 *m_head = NULL; 2658 return (ENOBUFS); 2659 } 2660 *m_head = m; 2661 error = bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_tx_tag, 2662 map, *m_head, txsegs, &nseg, BUS_DMA_NOWAIT); 2663 if (error != 0) { 2664 m_freem(*m_head); 2665 *m_head = NULL; 2666 return (error); 2667 } 2668 } else if (error != 0) 2669 return (error); 2670 if (nseg == 0) { 2671 m_freem(*m_head); 2672 *m_head = NULL; 2673 return (EIO); 2674 } 2675 2676 /* Check number of available descriptors. */ 2677 if (sc_if->msk_cdata.msk_tx_cnt + nseg >= 2678 (MSK_TX_RING_CNT - MSK_RESERVED_TX_DESC_CNT)) { 2679 bus_dmamap_unload(sc_if->msk_cdata.msk_tx_tag, map); 2680 return (ENOBUFS); 2681 } 2682 2683 control = 0; 2684 tso = 0; 2685 tx_le = NULL; 2686 2687 /* Check TSO support. */ 2688 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 2689 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) != 0) 2690 tso_mtu = m->m_pkthdr.tso_segsz; 2691 else 2692 tso_mtu = offset + m->m_pkthdr.tso_segsz; 2693 if (tso_mtu != sc_if->msk_cdata.msk_tso_mtu) { 2694 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2695 tx_le->msk_addr = htole32(tso_mtu); 2696 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) != 0) 2697 tx_le->msk_control = htole32(OP_MSS | HW_OWNER); 2698 else 2699 tx_le->msk_control = 2700 htole32(OP_LRGLEN | HW_OWNER); 2701 sc_if->msk_cdata.msk_tx_cnt++; 2702 MSK_INC(prod, MSK_TX_RING_CNT); 2703 sc_if->msk_cdata.msk_tso_mtu = tso_mtu; 2704 } 2705 tso++; 2706 } 2707 /* Check if we have a VLAN tag to insert. */ 2708 if ((m->m_flags & M_VLANTAG) != 0) { 2709 if (tx_le == NULL) { 2710 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2711 tx_le->msk_addr = htole32(0); 2712 tx_le->msk_control = htole32(OP_VLAN | HW_OWNER | 2713 htons(m->m_pkthdr.ether_vtag)); 2714 sc_if->msk_cdata.msk_tx_cnt++; 2715 MSK_INC(prod, MSK_TX_RING_CNT); 2716 } else { 2717 tx_le->msk_control |= htole32(OP_VLAN | 2718 htons(m->m_pkthdr.ether_vtag)); 2719 } 2720 control |= INS_VLAN; 2721 } 2722 /* Check if we have to handle checksum offload. */ 2723 if (tso == 0 && (m->m_pkthdr.csum_flags & MSK_CSUM_FEATURES) != 0) { 2724 if ((sc_if->msk_flags & MSK_FLAG_AUTOTX_CSUM) != 0) 2725 control |= CALSUM; 2726 else { 2727 control |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM; 2728 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0) 2729 control |= UDPTCP; 2730 /* Checksum write position. */ 2731 csum = (tcp_offset + m->m_pkthdr.csum_data) & 0xffff; 2732 /* Checksum start position. */ 2733 csum |= (uint32_t)tcp_offset << 16; 2734 if (csum != sc_if->msk_cdata.msk_last_csum) { 2735 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2736 tx_le->msk_addr = htole32(csum); 2737 tx_le->msk_control = htole32(1 << 16 | 2738 (OP_TCPLISW | HW_OWNER)); 2739 sc_if->msk_cdata.msk_tx_cnt++; 2740 MSK_INC(prod, MSK_TX_RING_CNT); 2741 sc_if->msk_cdata.msk_last_csum = csum; 2742 } 2743 } 2744 } 2745 2746 si = prod; 2747 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2748 tx_le->msk_addr = htole32(MSK_ADDR_LO(txsegs[0].ds_addr)); 2749 if (tso == 0) 2750 tx_le->msk_control = htole32(txsegs[0].ds_len | control | 2751 OP_PACKET); 2752 else 2753 tx_le->msk_control = htole32(txsegs[0].ds_len | control | 2754 OP_LARGESEND); 2755 sc_if->msk_cdata.msk_tx_cnt++; 2756 MSK_INC(prod, MSK_TX_RING_CNT); 2757 2758 for (i = 1; i < nseg; i++) { 2759 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2760 tx_le->msk_addr = htole32(MSK_ADDR_LO(txsegs[i].ds_addr)); 2761 tx_le->msk_control = htole32(txsegs[i].ds_len | control | 2762 OP_BUFFER | HW_OWNER); 2763 sc_if->msk_cdata.msk_tx_cnt++; 2764 MSK_INC(prod, MSK_TX_RING_CNT); 2765 } 2766 /* Update producer index. */ 2767 sc_if->msk_cdata.msk_tx_prod = prod; 2768 2769 /* Set EOP on the last desciptor. */ 2770 prod = (prod + MSK_TX_RING_CNT - 1) % MSK_TX_RING_CNT; 2771 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2772 tx_le->msk_control |= htole32(EOP); 2773 2774 /* Turn the first descriptor ownership to hardware. */ 2775 tx_le = &sc_if->msk_rdata.msk_tx_ring[si]; 2776 tx_le->msk_control |= htole32(HW_OWNER); 2777 2778 txd = &sc_if->msk_cdata.msk_txdesc[prod]; 2779 map = txd_last->tx_dmamap; 2780 txd_last->tx_dmamap = txd->tx_dmamap; 2781 txd->tx_dmamap = map; 2782 txd->tx_m = m; 2783 2784 /* Sync descriptors. */ 2785 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_tag, map, BUS_DMASYNC_PREWRITE); 2786 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_ring_tag, 2787 sc_if->msk_cdata.msk_tx_ring_map, 2788 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2789 2790 return (0); 2791 } 2792 2793 static void 2794 msk_start(struct ifnet *ifp) 2795 { 2796 struct msk_if_softc *sc_if; 2797 2798 sc_if = ifp->if_softc; 2799 MSK_IF_LOCK(sc_if); 2800 msk_start_locked(ifp); 2801 MSK_IF_UNLOCK(sc_if); 2802 } 2803 2804 static void 2805 msk_start_locked(struct ifnet *ifp) 2806 { 2807 struct msk_if_softc *sc_if; 2808 struct mbuf *m_head; 2809 int enq; 2810 2811 sc_if = ifp->if_softc; 2812 MSK_IF_LOCK_ASSERT(sc_if); 2813 2814 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2815 IFF_DRV_RUNNING || (sc_if->msk_flags & MSK_FLAG_LINK) == 0) 2816 return; 2817 2818 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 2819 sc_if->msk_cdata.msk_tx_cnt < 2820 (MSK_TX_RING_CNT - MSK_RESERVED_TX_DESC_CNT); ) { 2821 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2822 if (m_head == NULL) 2823 break; 2824 /* 2825 * Pack the data into the transmit ring. If we 2826 * don't have room, set the OACTIVE flag and wait 2827 * for the NIC to drain the ring. 2828 */ 2829 if (msk_encap(sc_if, &m_head) != 0) { 2830 if (m_head == NULL) 2831 break; 2832 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2833 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2834 break; 2835 } 2836 2837 enq++; 2838 /* 2839 * If there's a BPF listener, bounce a copy of this frame 2840 * to him. 2841 */ 2842 ETHER_BPF_MTAP(ifp, m_head); 2843 } 2844 2845 if (enq > 0) { 2846 /* Transmit */ 2847 CSR_WRITE_2(sc_if->msk_softc, 2848 Y2_PREF_Q_ADDR(sc_if->msk_txq, PREF_UNIT_PUT_IDX_REG), 2849 sc_if->msk_cdata.msk_tx_prod); 2850 2851 /* Set a timeout in case the chip goes out to lunch. */ 2852 sc_if->msk_watchdog_timer = MSK_TX_TIMEOUT; 2853 } 2854 } 2855 2856 static void 2857 msk_watchdog(struct msk_if_softc *sc_if) 2858 { 2859 struct ifnet *ifp; 2860 2861 MSK_IF_LOCK_ASSERT(sc_if); 2862 2863 if (sc_if->msk_watchdog_timer == 0 || --sc_if->msk_watchdog_timer) 2864 return; 2865 ifp = sc_if->msk_ifp; 2866 if ((sc_if->msk_flags & MSK_FLAG_LINK) == 0) { 2867 if (bootverbose) 2868 if_printf(sc_if->msk_ifp, "watchdog timeout " 2869 "(missed link)\n"); 2870 ifp->if_oerrors++; 2871 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2872 msk_init_locked(sc_if); 2873 return; 2874 } 2875 2876 if_printf(ifp, "watchdog timeout\n"); 2877 ifp->if_oerrors++; 2878 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2879 msk_init_locked(sc_if); 2880 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2881 msk_start_locked(ifp); 2882 } 2883 2884 static int 2885 mskc_shutdown(device_t dev) 2886 { 2887 struct msk_softc *sc; 2888 int i; 2889 2890 sc = device_get_softc(dev); 2891 MSK_LOCK(sc); 2892 for (i = 0; i < sc->msk_num_port; i++) { 2893 if (sc->msk_if[i] != NULL) 2894 msk_stop(sc->msk_if[i]); 2895 } 2896 2897 /* Disable all interrupts. */ 2898 CSR_WRITE_4(sc, B0_IMSK, 0); 2899 CSR_READ_4(sc, B0_IMSK); 2900 CSR_WRITE_4(sc, B0_HWE_IMSK, 0); 2901 CSR_READ_4(sc, B0_HWE_IMSK); 2902 2903 /* Put hardware reset. */ 2904 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); 2905 2906 MSK_UNLOCK(sc); 2907 return (0); 2908 } 2909 2910 static int 2911 mskc_suspend(device_t dev) 2912 { 2913 struct msk_softc *sc; 2914 int i; 2915 2916 sc = device_get_softc(dev); 2917 2918 MSK_LOCK(sc); 2919 2920 for (i = 0; i < sc->msk_num_port; i++) { 2921 if (sc->msk_if[i] != NULL && sc->msk_if[i]->msk_ifp != NULL && 2922 ((sc->msk_if[i]->msk_ifp->if_drv_flags & 2923 IFF_DRV_RUNNING) != 0)) 2924 msk_stop(sc->msk_if[i]); 2925 } 2926 2927 /* Disable all interrupts. */ 2928 CSR_WRITE_4(sc, B0_IMSK, 0); 2929 CSR_READ_4(sc, B0_IMSK); 2930 CSR_WRITE_4(sc, B0_HWE_IMSK, 0); 2931 CSR_READ_4(sc, B0_HWE_IMSK); 2932 2933 msk_phy_power(sc, MSK_PHY_POWERDOWN); 2934 2935 /* Put hardware reset. */ 2936 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); 2937 sc->msk_pflags |= MSK_FLAG_SUSPEND; 2938 2939 MSK_UNLOCK(sc); 2940 2941 return (0); 2942 } 2943 2944 static int 2945 mskc_resume(device_t dev) 2946 { 2947 struct msk_softc *sc; 2948 int i; 2949 2950 sc = device_get_softc(dev); 2951 2952 MSK_LOCK(sc); 2953 2954 mskc_reset(sc); 2955 for (i = 0; i < sc->msk_num_port; i++) { 2956 if (sc->msk_if[i] != NULL && sc->msk_if[i]->msk_ifp != NULL && 2957 ((sc->msk_if[i]->msk_ifp->if_flags & IFF_UP) != 0)) { 2958 sc->msk_if[i]->msk_ifp->if_drv_flags &= 2959 ~IFF_DRV_RUNNING; 2960 msk_init_locked(sc->msk_if[i]); 2961 } 2962 } 2963 sc->msk_pflags &= ~MSK_FLAG_SUSPEND; 2964 2965 MSK_UNLOCK(sc); 2966 2967 return (0); 2968 } 2969 2970 #ifndef __NO_STRICT_ALIGNMENT 2971 static __inline void 2972 msk_fixup_rx(struct mbuf *m) 2973 { 2974 int i; 2975 uint16_t *src, *dst; 2976 2977 src = mtod(m, uint16_t *); 2978 dst = src - 3; 2979 2980 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 2981 *dst++ = *src++; 2982 2983 m->m_data -= (MSK_RX_BUF_ALIGN - ETHER_ALIGN); 2984 } 2985 #endif 2986 2987 static __inline void 2988 msk_rxcsum(struct msk_if_softc *sc_if, uint32_t control, struct mbuf *m) 2989 { 2990 struct ether_header *eh; 2991 struct ip *ip; 2992 struct udphdr *uh; 2993 int32_t hlen, len, pktlen, temp32; 2994 uint16_t csum, *opts; 2995 2996 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) != 0) { 2997 if ((control & (CSS_IPV4 | CSS_IPFRAG)) == CSS_IPV4) { 2998 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 2999 if ((control & CSS_IPV4_CSUM_OK) != 0) 3000 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 3001 if ((control & (CSS_TCP | CSS_UDP)) != 0 && 3002 (control & (CSS_TCPUDP_CSUM_OK)) != 0) { 3003 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID | 3004 CSUM_PSEUDO_HDR; 3005 m->m_pkthdr.csum_data = 0xffff; 3006 } 3007 } 3008 return; 3009 } 3010 /* 3011 * Marvell Yukon controllers that support OP_RXCHKS has known 3012 * to have various Rx checksum offloading bugs. These 3013 * controllers can be configured to compute simple checksum 3014 * at two different positions. So we can compute IP and TCP/UDP 3015 * checksum at the same time. We intentionally have controller 3016 * compute TCP/UDP checksum twice by specifying the same 3017 * checksum start position and compare the result. If the value 3018 * is different it would indicate the hardware logic was wrong. 3019 */ 3020 if ((sc_if->msk_csum & 0xFFFF) != (sc_if->msk_csum >> 16)) { 3021 if (bootverbose) 3022 device_printf(sc_if->msk_if_dev, 3023 "Rx checksum value mismatch!\n"); 3024 return; 3025 } 3026 pktlen = m->m_pkthdr.len; 3027 if (pktlen < sizeof(struct ether_header) + sizeof(struct ip)) 3028 return; 3029 eh = mtod(m, struct ether_header *); 3030 if (eh->ether_type != htons(ETHERTYPE_IP)) 3031 return; 3032 ip = (struct ip *)(eh + 1); 3033 if (ip->ip_v != IPVERSION) 3034 return; 3035 3036 hlen = ip->ip_hl << 2; 3037 pktlen -= sizeof(struct ether_header); 3038 if (hlen < sizeof(struct ip)) 3039 return; 3040 if (ntohs(ip->ip_len) < hlen) 3041 return; 3042 if (ntohs(ip->ip_len) != pktlen) 3043 return; 3044 if (ip->ip_off & htons(IP_MF | IP_OFFMASK)) 3045 return; /* can't handle fragmented packet. */ 3046 3047 switch (ip->ip_p) { 3048 case IPPROTO_TCP: 3049 if (pktlen < (hlen + sizeof(struct tcphdr))) 3050 return; 3051 break; 3052 case IPPROTO_UDP: 3053 if (pktlen < (hlen + sizeof(struct udphdr))) 3054 return; 3055 uh = (struct udphdr *)((caddr_t)ip + hlen); 3056 if (uh->uh_sum == 0) 3057 return; /* no checksum */ 3058 break; 3059 default: 3060 return; 3061 } 3062 csum = ntohs(sc_if->msk_csum & 0xFFFF); 3063 /* Checksum fixup for IP options. */ 3064 len = hlen - sizeof(struct ip); 3065 if (len > 0) { 3066 opts = (uint16_t *)(ip + 1); 3067 for (; len > 0; len -= sizeof(uint16_t), opts++) { 3068 temp32 = csum - *opts; 3069 temp32 = (temp32 >> 16) + (temp32 & 65535); 3070 csum = temp32 & 65535; 3071 } 3072 } 3073 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID; 3074 m->m_pkthdr.csum_data = csum; 3075 } 3076 3077 static void 3078 msk_rxeof(struct msk_if_softc *sc_if, uint32_t status, uint32_t control, 3079 int len) 3080 { 3081 struct mbuf *m; 3082 struct ifnet *ifp; 3083 struct msk_rxdesc *rxd; 3084 int cons, rxlen; 3085 3086 ifp = sc_if->msk_ifp; 3087 3088 MSK_IF_LOCK_ASSERT(sc_if); 3089 3090 cons = sc_if->msk_cdata.msk_rx_cons; 3091 do { 3092 rxlen = status >> 16; 3093 if ((status & GMR_FS_VLAN) != 0 && 3094 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 3095 rxlen -= ETHER_VLAN_ENCAP_LEN; 3096 if ((sc_if->msk_flags & MSK_FLAG_NORXCHK) != 0) { 3097 /* 3098 * For controllers that returns bogus status code 3099 * just do minimal check and let upper stack 3100 * handle this frame. 3101 */ 3102 if (len > MSK_MAX_FRAMELEN || len < ETHER_HDR_LEN) { 3103 ifp->if_ierrors++; 3104 msk_discard_rxbuf(sc_if, cons); 3105 break; 3106 } 3107 } else if (len > sc_if->msk_framesize || 3108 ((status & GMR_FS_ANY_ERR) != 0) || 3109 ((status & GMR_FS_RX_OK) == 0) || (rxlen != len)) { 3110 /* Don't count flow-control packet as errors. */ 3111 if ((status & GMR_FS_GOOD_FC) == 0) 3112 ifp->if_ierrors++; 3113 msk_discard_rxbuf(sc_if, cons); 3114 break; 3115 } 3116 rxd = &sc_if->msk_cdata.msk_rxdesc[cons]; 3117 m = rxd->rx_m; 3118 if (msk_newbuf(sc_if, cons) != 0) { 3119 ifp->if_iqdrops++; 3120 /* Reuse old buffer. */ 3121 msk_discard_rxbuf(sc_if, cons); 3122 break; 3123 } 3124 m->m_pkthdr.rcvif = ifp; 3125 m->m_pkthdr.len = m->m_len = len; 3126 #ifndef __NO_STRICT_ALIGNMENT 3127 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) != 0) 3128 msk_fixup_rx(m); 3129 #endif 3130 ifp->if_ipackets++; 3131 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 3132 msk_rxcsum(sc_if, control, m); 3133 /* Check for VLAN tagged packets. */ 3134 if ((status & GMR_FS_VLAN) != 0 && 3135 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) { 3136 m->m_pkthdr.ether_vtag = sc_if->msk_vtag; 3137 m->m_flags |= M_VLANTAG; 3138 } 3139 MSK_IF_UNLOCK(sc_if); 3140 (*ifp->if_input)(ifp, m); 3141 MSK_IF_LOCK(sc_if); 3142 } while (0); 3143 3144 MSK_INC(sc_if->msk_cdata.msk_rx_cons, MSK_RX_RING_CNT); 3145 MSK_INC(sc_if->msk_cdata.msk_rx_prod, MSK_RX_RING_CNT); 3146 } 3147 3148 static void 3149 msk_jumbo_rxeof(struct msk_if_softc *sc_if, uint32_t status, uint32_t control, 3150 int len) 3151 { 3152 struct mbuf *m; 3153 struct ifnet *ifp; 3154 struct msk_rxdesc *jrxd; 3155 int cons, rxlen; 3156 3157 ifp = sc_if->msk_ifp; 3158 3159 MSK_IF_LOCK_ASSERT(sc_if); 3160 3161 cons = sc_if->msk_cdata.msk_rx_cons; 3162 do { 3163 rxlen = status >> 16; 3164 if ((status & GMR_FS_VLAN) != 0 && 3165 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 3166 rxlen -= ETHER_VLAN_ENCAP_LEN; 3167 if (len > sc_if->msk_framesize || 3168 ((status & GMR_FS_ANY_ERR) != 0) || 3169 ((status & GMR_FS_RX_OK) == 0) || (rxlen != len)) { 3170 /* Don't count flow-control packet as errors. */ 3171 if ((status & GMR_FS_GOOD_FC) == 0) 3172 ifp->if_ierrors++; 3173 msk_discard_jumbo_rxbuf(sc_if, cons); 3174 break; 3175 } 3176 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[cons]; 3177 m = jrxd->rx_m; 3178 if (msk_jumbo_newbuf(sc_if, cons) != 0) { 3179 ifp->if_iqdrops++; 3180 /* Reuse old buffer. */ 3181 msk_discard_jumbo_rxbuf(sc_if, cons); 3182 break; 3183 } 3184 m->m_pkthdr.rcvif = ifp; 3185 m->m_pkthdr.len = m->m_len = len; 3186 #ifndef __NO_STRICT_ALIGNMENT 3187 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) != 0) 3188 msk_fixup_rx(m); 3189 #endif 3190 ifp->if_ipackets++; 3191 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 3192 msk_rxcsum(sc_if, control, m); 3193 /* Check for VLAN tagged packets. */ 3194 if ((status & GMR_FS_VLAN) != 0 && 3195 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) { 3196 m->m_pkthdr.ether_vtag = sc_if->msk_vtag; 3197 m->m_flags |= M_VLANTAG; 3198 } 3199 MSK_IF_UNLOCK(sc_if); 3200 (*ifp->if_input)(ifp, m); 3201 MSK_IF_LOCK(sc_if); 3202 } while (0); 3203 3204 MSK_INC(sc_if->msk_cdata.msk_rx_cons, MSK_JUMBO_RX_RING_CNT); 3205 MSK_INC(sc_if->msk_cdata.msk_rx_prod, MSK_JUMBO_RX_RING_CNT); 3206 } 3207 3208 static void 3209 msk_txeof(struct msk_if_softc *sc_if, int idx) 3210 { 3211 struct msk_txdesc *txd; 3212 struct msk_tx_desc *cur_tx; 3213 struct ifnet *ifp; 3214 uint32_t control; 3215 int cons, prog; 3216 3217 MSK_IF_LOCK_ASSERT(sc_if); 3218 3219 ifp = sc_if->msk_ifp; 3220 3221 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_ring_tag, 3222 sc_if->msk_cdata.msk_tx_ring_map, 3223 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3224 /* 3225 * Go through our tx ring and free mbufs for those 3226 * frames that have been sent. 3227 */ 3228 cons = sc_if->msk_cdata.msk_tx_cons; 3229 prog = 0; 3230 for (; cons != idx; MSK_INC(cons, MSK_TX_RING_CNT)) { 3231 if (sc_if->msk_cdata.msk_tx_cnt <= 0) 3232 break; 3233 prog++; 3234 cur_tx = &sc_if->msk_rdata.msk_tx_ring[cons]; 3235 control = le32toh(cur_tx->msk_control); 3236 sc_if->msk_cdata.msk_tx_cnt--; 3237 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3238 if ((control & EOP) == 0) 3239 continue; 3240 txd = &sc_if->msk_cdata.msk_txdesc[cons]; 3241 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_tag, txd->tx_dmamap, 3242 BUS_DMASYNC_POSTWRITE); 3243 bus_dmamap_unload(sc_if->msk_cdata.msk_tx_tag, txd->tx_dmamap); 3244 3245 ifp->if_opackets++; 3246 KASSERT(txd->tx_m != NULL, ("%s: freeing NULL mbuf!", 3247 __func__)); 3248 m_freem(txd->tx_m); 3249 txd->tx_m = NULL; 3250 } 3251 3252 if (prog > 0) { 3253 sc_if->msk_cdata.msk_tx_cons = cons; 3254 if (sc_if->msk_cdata.msk_tx_cnt == 0) 3255 sc_if->msk_watchdog_timer = 0; 3256 /* No need to sync LEs as we didn't update LEs. */ 3257 } 3258 } 3259 3260 static void 3261 msk_tick(void *xsc_if) 3262 { 3263 struct msk_if_softc *sc_if; 3264 struct mii_data *mii; 3265 3266 sc_if = xsc_if; 3267 3268 MSK_IF_LOCK_ASSERT(sc_if); 3269 3270 mii = device_get_softc(sc_if->msk_miibus); 3271 3272 mii_tick(mii); 3273 if ((sc_if->msk_flags & MSK_FLAG_LINK) == 0) 3274 msk_miibus_statchg(sc_if->msk_if_dev); 3275 msk_handle_events(sc_if->msk_softc); 3276 msk_watchdog(sc_if); 3277 callout_reset(&sc_if->msk_tick_ch, hz, msk_tick, sc_if); 3278 } 3279 3280 static void 3281 msk_intr_phy(struct msk_if_softc *sc_if) 3282 { 3283 uint16_t status; 3284 3285 msk_phy_readreg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_STAT); 3286 status = msk_phy_readreg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_STAT); 3287 /* Handle FIFO Underrun/Overflow? */ 3288 if ((status & PHY_M_IS_FIFO_ERROR)) 3289 device_printf(sc_if->msk_if_dev, 3290 "PHY FIFO underrun/overflow.\n"); 3291 } 3292 3293 static void 3294 msk_intr_gmac(struct msk_if_softc *sc_if) 3295 { 3296 struct msk_softc *sc; 3297 uint8_t status; 3298 3299 sc = sc_if->msk_softc; 3300 status = CSR_READ_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_SRC)); 3301 3302 /* GMAC Rx FIFO overrun. */ 3303 if ((status & GM_IS_RX_FF_OR) != 0) 3304 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), 3305 GMF_CLI_RX_FO); 3306 /* GMAC Tx FIFO underrun. */ 3307 if ((status & GM_IS_TX_FF_UR) != 0) { 3308 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 3309 GMF_CLI_TX_FU); 3310 device_printf(sc_if->msk_if_dev, "Tx FIFO underrun!\n"); 3311 /* 3312 * XXX 3313 * In case of Tx underrun, we may need to flush/reset 3314 * Tx MAC but that would also require resynchronization 3315 * with status LEs. Reintializing status LEs would 3316 * affect other port in dual MAC configuration so it 3317 * should be avoided as possible as we can. 3318 * Due to lack of documentation it's all vague guess but 3319 * it needs more investigation. 3320 */ 3321 } 3322 } 3323 3324 static void 3325 msk_handle_hwerr(struct msk_if_softc *sc_if, uint32_t status) 3326 { 3327 struct msk_softc *sc; 3328 3329 sc = sc_if->msk_softc; 3330 if ((status & Y2_IS_PAR_RD1) != 0) { 3331 device_printf(sc_if->msk_if_dev, 3332 "RAM buffer read parity error\n"); 3333 /* Clear IRQ. */ 3334 CSR_WRITE_2(sc, SELECT_RAM_BUFFER(sc_if->msk_port, B3_RI_CTRL), 3335 RI_CLR_RD_PERR); 3336 } 3337 if ((status & Y2_IS_PAR_WR1) != 0) { 3338 device_printf(sc_if->msk_if_dev, 3339 "RAM buffer write parity error\n"); 3340 /* Clear IRQ. */ 3341 CSR_WRITE_2(sc, SELECT_RAM_BUFFER(sc_if->msk_port, B3_RI_CTRL), 3342 RI_CLR_WR_PERR); 3343 } 3344 if ((status & Y2_IS_PAR_MAC1) != 0) { 3345 device_printf(sc_if->msk_if_dev, "Tx MAC parity error\n"); 3346 /* Clear IRQ. */ 3347 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 3348 GMF_CLI_TX_PE); 3349 } 3350 if ((status & Y2_IS_PAR_RX1) != 0) { 3351 device_printf(sc_if->msk_if_dev, "Rx parity error\n"); 3352 /* Clear IRQ. */ 3353 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_CLR_IRQ_PAR); 3354 } 3355 if ((status & (Y2_IS_TCP_TXS1 | Y2_IS_TCP_TXA1)) != 0) { 3356 device_printf(sc_if->msk_if_dev, "TCP segmentation error\n"); 3357 /* Clear IRQ. */ 3358 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_CLR_IRQ_TCP); 3359 } 3360 } 3361 3362 static void 3363 msk_intr_hwerr(struct msk_softc *sc) 3364 { 3365 uint32_t status; 3366 uint32_t tlphead[4]; 3367 3368 status = CSR_READ_4(sc, B0_HWE_ISRC); 3369 /* Time Stamp timer overflow. */ 3370 if ((status & Y2_IS_TIST_OV) != 0) 3371 CSR_WRITE_1(sc, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ); 3372 if ((status & Y2_IS_PCI_NEXP) != 0) { 3373 /* 3374 * PCI Express Error occured which is not described in PEX 3375 * spec. 3376 * This error is also mapped either to Master Abort( 3377 * Y2_IS_MST_ERR) or Target Abort (Y2_IS_IRQ_STAT) bit and 3378 * can only be cleared there. 3379 */ 3380 device_printf(sc->msk_dev, 3381 "PCI Express protocol violation error\n"); 3382 } 3383 3384 if ((status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) != 0) { 3385 uint16_t v16; 3386 3387 if ((status & Y2_IS_MST_ERR) != 0) 3388 device_printf(sc->msk_dev, 3389 "unexpected IRQ Status error\n"); 3390 else 3391 device_printf(sc->msk_dev, 3392 "unexpected IRQ Master error\n"); 3393 /* Reset all bits in the PCI status register. */ 3394 v16 = pci_read_config(sc->msk_dev, PCIR_STATUS, 2); 3395 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON); 3396 pci_write_config(sc->msk_dev, PCIR_STATUS, v16 | 3397 PCIM_STATUS_PERR | PCIM_STATUS_SERR | PCIM_STATUS_RMABORT | 3398 PCIM_STATUS_RTABORT | PCIM_STATUS_PERRREPORT, 2); 3399 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 3400 } 3401 3402 /* Check for PCI Express Uncorrectable Error. */ 3403 if ((status & Y2_IS_PCI_EXP) != 0) { 3404 uint32_t v32; 3405 3406 /* 3407 * On PCI Express bus bridges are called root complexes (RC). 3408 * PCI Express errors are recognized by the root complex too, 3409 * which requests the system to handle the problem. After 3410 * error occurence it may be that no access to the adapter 3411 * may be performed any longer. 3412 */ 3413 3414 v32 = CSR_PCI_READ_4(sc, PEX_UNC_ERR_STAT); 3415 if ((v32 & PEX_UNSUP_REQ) != 0) { 3416 /* Ignore unsupported request error. */ 3417 device_printf(sc->msk_dev, 3418 "Uncorrectable PCI Express error\n"); 3419 } 3420 if ((v32 & (PEX_FATAL_ERRORS | PEX_POIS_TLP)) != 0) { 3421 int i; 3422 3423 /* Get TLP header form Log Registers. */ 3424 for (i = 0; i < 4; i++) 3425 tlphead[i] = CSR_PCI_READ_4(sc, 3426 PEX_HEADER_LOG + i * 4); 3427 /* Check for vendor defined broadcast message. */ 3428 if (!(tlphead[0] == 0x73004001 && tlphead[1] == 0x7f)) { 3429 sc->msk_intrhwemask &= ~Y2_IS_PCI_EXP; 3430 CSR_WRITE_4(sc, B0_HWE_IMSK, 3431 sc->msk_intrhwemask); 3432 CSR_READ_4(sc, B0_HWE_IMSK); 3433 } 3434 } 3435 /* Clear the interrupt. */ 3436 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON); 3437 CSR_PCI_WRITE_4(sc, PEX_UNC_ERR_STAT, 0xffffffff); 3438 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 3439 } 3440 3441 if ((status & Y2_HWE_L1_MASK) != 0 && sc->msk_if[MSK_PORT_A] != NULL) 3442 msk_handle_hwerr(sc->msk_if[MSK_PORT_A], status); 3443 if ((status & Y2_HWE_L2_MASK) != 0 && sc->msk_if[MSK_PORT_B] != NULL) 3444 msk_handle_hwerr(sc->msk_if[MSK_PORT_B], status >> 8); 3445 } 3446 3447 static __inline void 3448 msk_rxput(struct msk_if_softc *sc_if) 3449 { 3450 struct msk_softc *sc; 3451 3452 sc = sc_if->msk_softc; 3453 if (sc_if->msk_framesize > (MCLBYTES - MSK_RX_BUF_ALIGN)) 3454 bus_dmamap_sync( 3455 sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 3456 sc_if->msk_cdata.msk_jumbo_rx_ring_map, 3457 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3458 else 3459 bus_dmamap_sync( 3460 sc_if->msk_cdata.msk_rx_ring_tag, 3461 sc_if->msk_cdata.msk_rx_ring_map, 3462 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3463 CSR_WRITE_2(sc, Y2_PREF_Q_ADDR(sc_if->msk_rxq, 3464 PREF_UNIT_PUT_IDX_REG), sc_if->msk_cdata.msk_rx_prod); 3465 } 3466 3467 static int 3468 msk_handle_events(struct msk_softc *sc) 3469 { 3470 struct msk_if_softc *sc_if; 3471 int rxput[2]; 3472 struct msk_stat_desc *sd; 3473 uint32_t control, status; 3474 int cons, len, port, rxprog; 3475 3476 if (sc->msk_stat_cons == CSR_READ_2(sc, STAT_PUT_IDX)) 3477 return (0); 3478 3479 /* Sync status LEs. */ 3480 bus_dmamap_sync(sc->msk_stat_tag, sc->msk_stat_map, 3481 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3482 3483 rxput[MSK_PORT_A] = rxput[MSK_PORT_B] = 0; 3484 rxprog = 0; 3485 cons = sc->msk_stat_cons; 3486 for (;;) { 3487 sd = &sc->msk_stat_ring[cons]; 3488 control = le32toh(sd->msk_control); 3489 if ((control & HW_OWNER) == 0) 3490 break; 3491 control &= ~HW_OWNER; 3492 sd->msk_control = htole32(control); 3493 status = le32toh(sd->msk_status); 3494 len = control & STLE_LEN_MASK; 3495 port = (control >> 16) & 0x01; 3496 sc_if = sc->msk_if[port]; 3497 if (sc_if == NULL) { 3498 device_printf(sc->msk_dev, "invalid port opcode " 3499 "0x%08x\n", control & STLE_OP_MASK); 3500 continue; 3501 } 3502 3503 switch (control & STLE_OP_MASK) { 3504 case OP_RXVLAN: 3505 sc_if->msk_vtag = ntohs(len); 3506 break; 3507 case OP_RXCHKSVLAN: 3508 sc_if->msk_vtag = ntohs(len); 3509 /* FALLTHROUGH */ 3510 case OP_RXCHKS: 3511 sc_if->msk_csum = status; 3512 break; 3513 case OP_RXSTAT: 3514 if (sc_if->msk_framesize > 3515 (MCLBYTES - MSK_RX_BUF_ALIGN)) 3516 msk_jumbo_rxeof(sc_if, status, control, len); 3517 else 3518 msk_rxeof(sc_if, status, control, len); 3519 rxprog++; 3520 /* 3521 * Because there is no way to sync single Rx LE 3522 * put the DMA sync operation off until the end of 3523 * event processing. 3524 */ 3525 rxput[port]++; 3526 /* Update prefetch unit if we've passed water mark. */ 3527 if (rxput[port] >= sc_if->msk_cdata.msk_rx_putwm) { 3528 msk_rxput(sc_if); 3529 rxput[port] = 0; 3530 } 3531 break; 3532 case OP_TXINDEXLE: 3533 if (sc->msk_if[MSK_PORT_A] != NULL) 3534 msk_txeof(sc->msk_if[MSK_PORT_A], 3535 status & STLE_TXA1_MSKL); 3536 if (sc->msk_if[MSK_PORT_B] != NULL) 3537 msk_txeof(sc->msk_if[MSK_PORT_B], 3538 ((status & STLE_TXA2_MSKL) >> 3539 STLE_TXA2_SHIFTL) | 3540 ((len & STLE_TXA2_MSKH) << 3541 STLE_TXA2_SHIFTH)); 3542 break; 3543 default: 3544 device_printf(sc->msk_dev, "unhandled opcode 0x%08x\n", 3545 control & STLE_OP_MASK); 3546 break; 3547 } 3548 MSK_INC(cons, MSK_STAT_RING_CNT); 3549 if (rxprog > sc->msk_process_limit) 3550 break; 3551 } 3552 3553 sc->msk_stat_cons = cons; 3554 bus_dmamap_sync(sc->msk_stat_tag, sc->msk_stat_map, 3555 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3556 3557 if (rxput[MSK_PORT_A] > 0) 3558 msk_rxput(sc->msk_if[MSK_PORT_A]); 3559 if (rxput[MSK_PORT_B] > 0) 3560 msk_rxput(sc->msk_if[MSK_PORT_B]); 3561 3562 return (sc->msk_stat_cons != CSR_READ_2(sc, STAT_PUT_IDX)); 3563 } 3564 3565 static void 3566 msk_intr(void *xsc) 3567 { 3568 struct msk_softc *sc; 3569 struct msk_if_softc *sc_if0, *sc_if1; 3570 struct ifnet *ifp0, *ifp1; 3571 uint32_t status; 3572 int domore; 3573 3574 sc = xsc; 3575 MSK_LOCK(sc); 3576 3577 /* Reading B0_Y2_SP_ISRC2 masks further interrupts. */ 3578 status = CSR_READ_4(sc, B0_Y2_SP_ISRC2); 3579 if (status == 0 || status == 0xffffffff || 3580 (sc->msk_pflags & MSK_FLAG_SUSPEND) != 0 || 3581 (status & sc->msk_intrmask) == 0) { 3582 CSR_WRITE_4(sc, B0_Y2_SP_ICR, 2); 3583 return; 3584 } 3585 3586 sc_if0 = sc->msk_if[MSK_PORT_A]; 3587 sc_if1 = sc->msk_if[MSK_PORT_B]; 3588 ifp0 = ifp1 = NULL; 3589 if (sc_if0 != NULL) 3590 ifp0 = sc_if0->msk_ifp; 3591 if (sc_if1 != NULL) 3592 ifp1 = sc_if1->msk_ifp; 3593 3594 if ((status & Y2_IS_IRQ_PHY1) != 0 && sc_if0 != NULL) 3595 msk_intr_phy(sc_if0); 3596 if ((status & Y2_IS_IRQ_PHY2) != 0 && sc_if1 != NULL) 3597 msk_intr_phy(sc_if1); 3598 if ((status & Y2_IS_IRQ_MAC1) != 0 && sc_if0 != NULL) 3599 msk_intr_gmac(sc_if0); 3600 if ((status & Y2_IS_IRQ_MAC2) != 0 && sc_if1 != NULL) 3601 msk_intr_gmac(sc_if1); 3602 if ((status & (Y2_IS_CHK_RX1 | Y2_IS_CHK_RX2)) != 0) { 3603 device_printf(sc->msk_dev, "Rx descriptor error\n"); 3604 sc->msk_intrmask &= ~(Y2_IS_CHK_RX1 | Y2_IS_CHK_RX2); 3605 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask); 3606 CSR_READ_4(sc, B0_IMSK); 3607 } 3608 if ((status & (Y2_IS_CHK_TXA1 | Y2_IS_CHK_TXA2)) != 0) { 3609 device_printf(sc->msk_dev, "Tx descriptor error\n"); 3610 sc->msk_intrmask &= ~(Y2_IS_CHK_TXA1 | Y2_IS_CHK_TXA2); 3611 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask); 3612 CSR_READ_4(sc, B0_IMSK); 3613 } 3614 if ((status & Y2_IS_HW_ERR) != 0) 3615 msk_intr_hwerr(sc); 3616 3617 domore = msk_handle_events(sc); 3618 if ((status & Y2_IS_STAT_BMU) != 0 && domore == 0) 3619 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_CLR_IRQ); 3620 3621 /* Reenable interrupts. */ 3622 CSR_WRITE_4(sc, B0_Y2_SP_ICR, 2); 3623 3624 if (ifp0 != NULL && (ifp0->if_drv_flags & IFF_DRV_RUNNING) != 0 && 3625 !IFQ_DRV_IS_EMPTY(&ifp0->if_snd)) 3626 msk_start_locked(ifp0); 3627 if (ifp1 != NULL && (ifp1->if_drv_flags & IFF_DRV_RUNNING) != 0 && 3628 !IFQ_DRV_IS_EMPTY(&ifp1->if_snd)) 3629 msk_start_locked(ifp1); 3630 3631 MSK_UNLOCK(sc); 3632 } 3633 3634 static void 3635 msk_set_tx_stfwd(struct msk_if_softc *sc_if) 3636 { 3637 struct msk_softc *sc; 3638 struct ifnet *ifp; 3639 3640 ifp = sc_if->msk_ifp; 3641 sc = sc_if->msk_softc; 3642 switch (sc->msk_hw_id) { 3643 case CHIP_ID_YUKON_EX: 3644 if (sc->msk_hw_rev == CHIP_REV_YU_EX_A0) 3645 goto yukon_ex_workaround; 3646 if (ifp->if_mtu > ETHERMTU) 3647 CSR_WRITE_4(sc, 3648 MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 3649 TX_JUMBO_ENA | TX_STFW_ENA); 3650 else 3651 CSR_WRITE_4(sc, 3652 MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 3653 TX_JUMBO_DIS | TX_STFW_ENA); 3654 break; 3655 default: 3656 yukon_ex_workaround: 3657 if (ifp->if_mtu > ETHERMTU) { 3658 /* Set Tx GMAC FIFO Almost Empty Threshold. */ 3659 CSR_WRITE_4(sc, 3660 MR_ADDR(sc_if->msk_port, TX_GMF_AE_THR), 3661 MSK_ECU_JUMBO_WM << 16 | MSK_ECU_AE_THR); 3662 /* Disable Store & Forward mode for Tx. */ 3663 CSR_WRITE_4(sc, 3664 MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 3665 TX_JUMBO_ENA | TX_STFW_DIS); 3666 } else { 3667 /* Enable Store & Forward mode for Tx. */ 3668 CSR_WRITE_4(sc, 3669 MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 3670 TX_JUMBO_DIS | TX_STFW_ENA); 3671 } 3672 break; 3673 } 3674 } 3675 3676 static void 3677 msk_init(void *xsc) 3678 { 3679 struct msk_if_softc *sc_if = xsc; 3680 3681 MSK_IF_LOCK(sc_if); 3682 msk_init_locked(sc_if); 3683 MSK_IF_UNLOCK(sc_if); 3684 } 3685 3686 static void 3687 msk_init_locked(struct msk_if_softc *sc_if) 3688 { 3689 struct msk_softc *sc; 3690 struct ifnet *ifp; 3691 struct mii_data *mii; 3692 uint8_t *eaddr; 3693 uint16_t gmac; 3694 uint32_t reg; 3695 int error; 3696 3697 MSK_IF_LOCK_ASSERT(sc_if); 3698 3699 ifp = sc_if->msk_ifp; 3700 sc = sc_if->msk_softc; 3701 mii = device_get_softc(sc_if->msk_miibus); 3702 3703 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 3704 return; 3705 3706 error = 0; 3707 /* Cancel pending I/O and free all Rx/Tx buffers. */ 3708 msk_stop(sc_if); 3709 3710 if (ifp->if_mtu < ETHERMTU) 3711 sc_if->msk_framesize = ETHERMTU; 3712 else 3713 sc_if->msk_framesize = ifp->if_mtu; 3714 sc_if->msk_framesize += ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 3715 if (ifp->if_mtu > ETHERMTU && 3716 (sc_if->msk_flags & MSK_FLAG_JUMBO_NOCSUM) != 0) { 3717 ifp->if_hwassist &= ~(MSK_CSUM_FEATURES | CSUM_TSO); 3718 ifp->if_capenable &= ~(IFCAP_TSO4 | IFCAP_TXCSUM); 3719 } 3720 3721 /* GMAC Control reset. */ 3722 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_RST_SET); 3723 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_RST_CLR); 3724 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_F_LOOPB_OFF); 3725 if (sc->msk_hw_id == CHIP_ID_YUKON_EX) 3726 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), 3727 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON | 3728 GMC_BYP_RETR_ON); 3729 3730 /* 3731 * Initialize GMAC first such that speed/duplex/flow-control 3732 * parameters are renegotiated when interface is brought up. 3733 */ 3734 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, 0); 3735 3736 /* Dummy read the Interrupt Source Register. */ 3737 CSR_READ_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_SRC)); 3738 3739 /* Clear MIB stats. */ 3740 msk_stats_clear(sc_if); 3741 3742 /* Disable FCS. */ 3743 GMAC_WRITE_2(sc, sc_if->msk_port, GM_RX_CTRL, GM_RXCR_CRC_DIS); 3744 3745 /* Setup Transmit Control Register. */ 3746 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF)); 3747 3748 /* Setup Transmit Flow Control Register. */ 3749 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_FLOW_CTRL, 0xffff); 3750 3751 /* Setup Transmit Parameter Register. */ 3752 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_PARAM, 3753 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) | TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) | 3754 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) | TX_BACK_OFF_LIM(TX_BOF_LIM_DEF)); 3755 3756 gmac = DATA_BLIND_VAL(DATA_BLIND_DEF) | 3757 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF); 3758 3759 if (ifp->if_mtu > ETHERMTU) 3760 gmac |= GM_SMOD_JUMBO_ENA; 3761 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SERIAL_MODE, gmac); 3762 3763 /* Set station address. */ 3764 eaddr = IF_LLADDR(ifp); 3765 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_1L, 3766 eaddr[0] | (eaddr[1] << 8)); 3767 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_1M, 3768 eaddr[2] | (eaddr[3] << 8)); 3769 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_1H, 3770 eaddr[4] | (eaddr[5] << 8)); 3771 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_2L, 3772 eaddr[0] | (eaddr[1] << 8)); 3773 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_2M, 3774 eaddr[2] | (eaddr[3] << 8)); 3775 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_2H, 3776 eaddr[4] | (eaddr[5] << 8)); 3777 3778 /* Disable interrupts for counter overflows. */ 3779 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_IRQ_MSK, 0); 3780 GMAC_WRITE_2(sc, sc_if->msk_port, GM_RX_IRQ_MSK, 0); 3781 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TR_IRQ_MSK, 0); 3782 3783 /* Configure Rx MAC FIFO. */ 3784 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), GMF_RST_SET); 3785 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), GMF_RST_CLR); 3786 reg = GMF_OPER_ON | GMF_RX_F_FL_ON; 3787 if (sc->msk_hw_id == CHIP_ID_YUKON_FE_P || 3788 sc->msk_hw_id == CHIP_ID_YUKON_EX) 3789 reg |= GMF_RX_OVER_ON; 3790 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), reg); 3791 3792 /* Set receive filter. */ 3793 msk_rxfilter(sc_if); 3794 3795 if (sc->msk_hw_id == CHIP_ID_YUKON_XL) { 3796 /* Clear flush mask - HW bug. */ 3797 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_FL_MSK), 0); 3798 } else { 3799 /* Flush Rx MAC FIFO on any flow control or error. */ 3800 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_FL_MSK), 3801 GMR_FS_ANY_ERR); 3802 } 3803 3804 /* 3805 * Set Rx FIFO flush threshold to 64 bytes + 1 FIFO word 3806 * due to hardware hang on receipt of pause frames. 3807 */ 3808 reg = RX_GMF_FL_THR_DEF + 1; 3809 /* Another magic for Yukon FE+ - From Linux. */ 3810 if (sc->msk_hw_id == CHIP_ID_YUKON_FE_P && 3811 sc->msk_hw_rev == CHIP_REV_YU_FE_P_A0) 3812 reg = 0x178; 3813 CSR_WRITE_2(sc, MR_ADDR(sc_if->msk_port, RX_GMF_FL_THR), reg); 3814 3815 /* Configure Tx MAC FIFO. */ 3816 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_RST_SET); 3817 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_RST_CLR); 3818 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_OPER_ON); 3819 3820 /* Configure hardware VLAN tag insertion/stripping. */ 3821 msk_setvlan(sc_if, ifp); 3822 3823 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) == 0) { 3824 /* Set Rx Pause threshould. */ 3825 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, RX_GMF_LP_THR), 3826 MSK_ECU_LLPP); 3827 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, RX_GMF_UP_THR), 3828 MSK_ECU_ULPP); 3829 /* Configure store-and-forward for Tx. */ 3830 msk_set_tx_stfwd(sc_if); 3831 } 3832 3833 if (sc->msk_hw_id == CHIP_ID_YUKON_FE_P && 3834 sc->msk_hw_rev == CHIP_REV_YU_FE_P_A0) { 3835 /* Disable dynamic watermark - from Linux. */ 3836 reg = CSR_READ_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_EA)); 3837 reg &= ~0x03; 3838 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_EA), reg); 3839 } 3840 3841 /* 3842 * Disable Force Sync bit and Alloc bit in Tx RAM interface 3843 * arbiter as we don't use Sync Tx queue. 3844 */ 3845 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, TXA_CTRL), 3846 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC); 3847 /* Enable the RAM Interface Arbiter. */ 3848 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, TXA_CTRL), TXA_ENA_ARB); 3849 3850 /* Setup RAM buffer. */ 3851 msk_set_rambuffer(sc_if); 3852 3853 /* Disable Tx sync Queue. */ 3854 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txsq, RB_CTRL), RB_RST_SET); 3855 3856 /* Setup Tx Queue Bus Memory Interface. */ 3857 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_CLR_RESET); 3858 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_OPER_INIT); 3859 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_FIFO_OP_ON); 3860 CSR_WRITE_2(sc, Q_ADDR(sc_if->msk_txq, Q_WM), MSK_BMU_TX_WM); 3861 switch (sc->msk_hw_id) { 3862 case CHIP_ID_YUKON_EC_U: 3863 if (sc->msk_hw_rev == CHIP_REV_YU_EC_U_A0) { 3864 /* Fix for Yukon-EC Ultra: set BMU FIFO level */ 3865 CSR_WRITE_2(sc, Q_ADDR(sc_if->msk_txq, Q_AL), 3866 MSK_ECU_TXFF_LEV); 3867 } 3868 break; 3869 case CHIP_ID_YUKON_EX: 3870 /* 3871 * Yukon Extreme seems to have silicon bug for 3872 * automatic Tx checksum calculation capability. 3873 */ 3874 if (sc->msk_hw_rev == CHIP_REV_YU_EX_B0) 3875 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_F), 3876 F_TX_CHK_AUTO_OFF); 3877 break; 3878 } 3879 3880 /* Setup Rx Queue Bus Memory Interface. */ 3881 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_CLR_RESET); 3882 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_OPER_INIT); 3883 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_FIFO_OP_ON); 3884 CSR_WRITE_2(sc, Q_ADDR(sc_if->msk_rxq, Q_WM), MSK_BMU_RX_WM); 3885 if (sc->msk_hw_id == CHIP_ID_YUKON_EC_U && 3886 sc->msk_hw_rev >= CHIP_REV_YU_EC_U_A1) { 3887 /* MAC Rx RAM Read is controlled by hardware. */ 3888 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_F), F_M_RX_RAM_DIS); 3889 } 3890 3891 msk_set_prefetch(sc, sc_if->msk_txq, 3892 sc_if->msk_rdata.msk_tx_ring_paddr, MSK_TX_RING_CNT - 1); 3893 msk_init_tx_ring(sc_if); 3894 3895 /* Disable Rx checksum offload and RSS hash. */ 3896 reg = BMU_DIS_RX_RSS_HASH; 3897 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0 && 3898 (ifp->if_capenable & IFCAP_RXCSUM) != 0) 3899 reg |= BMU_ENA_RX_CHKSUM; 3900 else 3901 reg |= BMU_DIS_RX_CHKSUM; 3902 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), reg); 3903 if (sc_if->msk_framesize > (MCLBYTES - MSK_RX_BUF_ALIGN)) { 3904 msk_set_prefetch(sc, sc_if->msk_rxq, 3905 sc_if->msk_rdata.msk_jumbo_rx_ring_paddr, 3906 MSK_JUMBO_RX_RING_CNT - 1); 3907 error = msk_init_jumbo_rx_ring(sc_if); 3908 } else { 3909 msk_set_prefetch(sc, sc_if->msk_rxq, 3910 sc_if->msk_rdata.msk_rx_ring_paddr, 3911 MSK_RX_RING_CNT - 1); 3912 error = msk_init_rx_ring(sc_if); 3913 } 3914 if (error != 0) { 3915 device_printf(sc_if->msk_if_dev, 3916 "initialization failed: no memory for Rx buffers\n"); 3917 msk_stop(sc_if); 3918 return; 3919 } 3920 3921 /* Configure interrupt handling. */ 3922 if (sc_if->msk_port == MSK_PORT_A) { 3923 sc->msk_intrmask |= Y2_IS_PORT_A; 3924 sc->msk_intrhwemask |= Y2_HWE_L1_MASK; 3925 } else { 3926 sc->msk_intrmask |= Y2_IS_PORT_B; 3927 sc->msk_intrhwemask |= Y2_HWE_L2_MASK; 3928 } 3929 /* Configure IRQ moderation mask. */ 3930 CSR_WRITE_4(sc, B2_IRQM_MSK, sc->msk_intrmask); 3931 if (sc->msk_int_holdoff > 0) { 3932 /* Configure initial IRQ moderation timer value. */ 3933 CSR_WRITE_4(sc, B2_IRQM_INI, 3934 MSK_USECS(sc, sc->msk_int_holdoff)); 3935 CSR_WRITE_4(sc, B2_IRQM_VAL, 3936 MSK_USECS(sc, sc->msk_int_holdoff)); 3937 /* Start IRQ moderation. */ 3938 CSR_WRITE_1(sc, B2_IRQM_CTRL, TIM_START); 3939 } 3940 CSR_WRITE_4(sc, B0_HWE_IMSK, sc->msk_intrhwemask); 3941 CSR_READ_4(sc, B0_HWE_IMSK); 3942 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask); 3943 CSR_READ_4(sc, B0_IMSK); 3944 3945 sc_if->msk_flags &= ~MSK_FLAG_LINK; 3946 mii_mediachg(mii); 3947 3948 ifp->if_drv_flags |= IFF_DRV_RUNNING; 3949 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3950 3951 callout_reset(&sc_if->msk_tick_ch, hz, msk_tick, sc_if); 3952 } 3953 3954 static void 3955 msk_set_rambuffer(struct msk_if_softc *sc_if) 3956 { 3957 struct msk_softc *sc; 3958 int ltpp, utpp; 3959 3960 sc = sc_if->msk_softc; 3961 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) == 0) 3962 return; 3963 3964 /* Setup Rx Queue. */ 3965 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_RST_CLR); 3966 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_START), 3967 sc->msk_rxqstart[sc_if->msk_port] / 8); 3968 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_END), 3969 sc->msk_rxqend[sc_if->msk_port] / 8); 3970 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_WP), 3971 sc->msk_rxqstart[sc_if->msk_port] / 8); 3972 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_RP), 3973 sc->msk_rxqstart[sc_if->msk_port] / 8); 3974 3975 utpp = (sc->msk_rxqend[sc_if->msk_port] + 1 - 3976 sc->msk_rxqstart[sc_if->msk_port] - MSK_RB_ULPP) / 8; 3977 ltpp = (sc->msk_rxqend[sc_if->msk_port] + 1 - 3978 sc->msk_rxqstart[sc_if->msk_port] - MSK_RB_LLPP_B) / 8; 3979 if (sc->msk_rxqsize < MSK_MIN_RXQ_SIZE) 3980 ltpp += (MSK_RB_LLPP_B - MSK_RB_LLPP_S) / 8; 3981 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_RX_UTPP), utpp); 3982 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_RX_LTPP), ltpp); 3983 /* Set Rx priority(RB_RX_UTHP/RB_RX_LTHP) thresholds? */ 3984 3985 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_ENA_OP_MD); 3986 CSR_READ_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL)); 3987 3988 /* Setup Tx Queue. */ 3989 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_RST_CLR); 3990 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_START), 3991 sc->msk_txqstart[sc_if->msk_port] / 8); 3992 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_END), 3993 sc->msk_txqend[sc_if->msk_port] / 8); 3994 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_WP), 3995 sc->msk_txqstart[sc_if->msk_port] / 8); 3996 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_RP), 3997 sc->msk_txqstart[sc_if->msk_port] / 8); 3998 /* Enable Store & Forward for Tx side. */ 3999 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_ENA_STFWD); 4000 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_ENA_OP_MD); 4001 CSR_READ_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL)); 4002 } 4003 4004 static void 4005 msk_set_prefetch(struct msk_softc *sc, int qaddr, bus_addr_t addr, 4006 uint32_t count) 4007 { 4008 4009 /* Reset the prefetch unit. */ 4010 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG), 4011 PREF_UNIT_RST_SET); 4012 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG), 4013 PREF_UNIT_RST_CLR); 4014 /* Set LE base address. */ 4015 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_ADDR_LOW_REG), 4016 MSK_ADDR_LO(addr)); 4017 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_ADDR_HI_REG), 4018 MSK_ADDR_HI(addr)); 4019 /* Set the list last index. */ 4020 CSR_WRITE_2(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_LAST_IDX_REG), 4021 count); 4022 /* Turn on prefetch unit. */ 4023 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG), 4024 PREF_UNIT_OP_ON); 4025 /* Dummy read to ensure write. */ 4026 CSR_READ_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG)); 4027 } 4028 4029 static void 4030 msk_stop(struct msk_if_softc *sc_if) 4031 { 4032 struct msk_softc *sc; 4033 struct msk_txdesc *txd; 4034 struct msk_rxdesc *rxd; 4035 struct msk_rxdesc *jrxd; 4036 struct ifnet *ifp; 4037 uint32_t val; 4038 int i; 4039 4040 MSK_IF_LOCK_ASSERT(sc_if); 4041 sc = sc_if->msk_softc; 4042 ifp = sc_if->msk_ifp; 4043 4044 callout_stop(&sc_if->msk_tick_ch); 4045 sc_if->msk_watchdog_timer = 0; 4046 4047 /* Disable interrupts. */ 4048 if (sc_if->msk_port == MSK_PORT_A) { 4049 sc->msk_intrmask &= ~Y2_IS_PORT_A; 4050 sc->msk_intrhwemask &= ~Y2_HWE_L1_MASK; 4051 } else { 4052 sc->msk_intrmask &= ~Y2_IS_PORT_B; 4053 sc->msk_intrhwemask &= ~Y2_HWE_L2_MASK; 4054 } 4055 CSR_WRITE_4(sc, B0_HWE_IMSK, sc->msk_intrhwemask); 4056 CSR_READ_4(sc, B0_HWE_IMSK); 4057 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask); 4058 CSR_READ_4(sc, B0_IMSK); 4059 4060 /* Disable Tx/Rx MAC. */ 4061 val = GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL); 4062 val &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA); 4063 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, val); 4064 /* Read again to ensure writing. */ 4065 GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL); 4066 /* Update stats and clear counters. */ 4067 msk_stats_update(sc_if); 4068 4069 /* Stop Tx BMU. */ 4070 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_STOP); 4071 val = CSR_READ_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR)); 4072 for (i = 0; i < MSK_TIMEOUT; i++) { 4073 if ((val & (BMU_STOP | BMU_IDLE)) == 0) { 4074 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), 4075 BMU_STOP); 4076 val = CSR_READ_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR)); 4077 } else 4078 break; 4079 DELAY(1); 4080 } 4081 if (i == MSK_TIMEOUT) 4082 device_printf(sc_if->msk_if_dev, "Tx BMU stop failed\n"); 4083 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), 4084 RB_RST_SET | RB_DIS_OP_MD); 4085 4086 /* Disable all GMAC interrupt. */ 4087 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_MSK), 0); 4088 /* Disable PHY interrupt. */ 4089 msk_phy_writereg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_MASK, 0); 4090 4091 /* Disable the RAM Interface Arbiter. */ 4092 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, TXA_CTRL), TXA_DIS_ARB); 4093 4094 /* Reset the PCI FIFO of the async Tx queue */ 4095 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), 4096 BMU_RST_SET | BMU_FIFO_RST); 4097 4098 /* Reset the Tx prefetch units. */ 4099 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(sc_if->msk_txq, PREF_UNIT_CTRL_REG), 4100 PREF_UNIT_RST_SET); 4101 4102 /* Reset the RAM Buffer async Tx queue. */ 4103 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_RST_SET); 4104 4105 /* Reset Tx MAC FIFO. */ 4106 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_RST_SET); 4107 /* Set Pause Off. */ 4108 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_PAUSE_OFF); 4109 4110 /* 4111 * The Rx Stop command will not work for Yukon-2 if the BMU does not 4112 * reach the end of packet and since we can't make sure that we have 4113 * incoming data, we must reset the BMU while it is not during a DMA 4114 * transfer. Since it is possible that the Rx path is still active, 4115 * the Rx RAM buffer will be stopped first, so any possible incoming 4116 * data will not trigger a DMA. After the RAM buffer is stopped, the 4117 * BMU is polled until any DMA in progress is ended and only then it 4118 * will be reset. 4119 */ 4120 4121 /* Disable the RAM Buffer receive queue. */ 4122 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_DIS_OP_MD); 4123 for (i = 0; i < MSK_TIMEOUT; i++) { 4124 if (CSR_READ_1(sc, RB_ADDR(sc_if->msk_rxq, Q_RSL)) == 4125 CSR_READ_1(sc, RB_ADDR(sc_if->msk_rxq, Q_RL))) 4126 break; 4127 DELAY(1); 4128 } 4129 if (i == MSK_TIMEOUT) 4130 device_printf(sc_if->msk_if_dev, "Rx BMU stop failed\n"); 4131 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), 4132 BMU_RST_SET | BMU_FIFO_RST); 4133 /* Reset the Rx prefetch unit. */ 4134 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_CTRL_REG), 4135 PREF_UNIT_RST_SET); 4136 /* Reset the RAM Buffer receive queue. */ 4137 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_RST_SET); 4138 /* Reset Rx MAC FIFO. */ 4139 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), GMF_RST_SET); 4140 4141 /* Free Rx and Tx mbufs still in the queues. */ 4142 for (i = 0; i < MSK_RX_RING_CNT; i++) { 4143 rxd = &sc_if->msk_cdata.msk_rxdesc[i]; 4144 if (rxd->rx_m != NULL) { 4145 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_tag, 4146 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 4147 bus_dmamap_unload(sc_if->msk_cdata.msk_rx_tag, 4148 rxd->rx_dmamap); 4149 m_freem(rxd->rx_m); 4150 rxd->rx_m = NULL; 4151 } 4152 } 4153 for (i = 0; i < MSK_JUMBO_RX_RING_CNT; i++) { 4154 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[i]; 4155 if (jrxd->rx_m != NULL) { 4156 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_tag, 4157 jrxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 4158 bus_dmamap_unload(sc_if->msk_cdata.msk_jumbo_rx_tag, 4159 jrxd->rx_dmamap); 4160 m_freem(jrxd->rx_m); 4161 jrxd->rx_m = NULL; 4162 } 4163 } 4164 for (i = 0; i < MSK_TX_RING_CNT; i++) { 4165 txd = &sc_if->msk_cdata.msk_txdesc[i]; 4166 if (txd->tx_m != NULL) { 4167 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_tag, 4168 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 4169 bus_dmamap_unload(sc_if->msk_cdata.msk_tx_tag, 4170 txd->tx_dmamap); 4171 m_freem(txd->tx_m); 4172 txd->tx_m = NULL; 4173 } 4174 } 4175 4176 /* 4177 * Mark the interface down. 4178 */ 4179 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 4180 sc_if->msk_flags &= ~MSK_FLAG_LINK; 4181 } 4182 4183 /* 4184 * When GM_PAR_MIB_CLR bit of GM_PHY_ADDR is set, reading lower 4185 * counter clears high 16 bits of the counter such that accessing 4186 * lower 16 bits should be the last operation. 4187 */ 4188 #define MSK_READ_MIB32(x, y) \ 4189 (((uint32_t)GMAC_READ_2(sc, x, (y) + 4)) << 16) + \ 4190 (uint32_t)GMAC_READ_2(sc, x, y) 4191 #define MSK_READ_MIB64(x, y) \ 4192 (((uint64_t)MSK_READ_MIB32(x, (y) + 8)) << 32) + \ 4193 (uint64_t)MSK_READ_MIB32(x, y) 4194 4195 static void 4196 msk_stats_clear(struct msk_if_softc *sc_if) 4197 { 4198 struct msk_softc *sc; 4199 uint32_t reg; 4200 uint16_t gmac; 4201 int i; 4202 4203 MSK_IF_LOCK_ASSERT(sc_if); 4204 4205 sc = sc_if->msk_softc; 4206 /* Set MIB Clear Counter Mode. */ 4207 gmac = GMAC_READ_2(sc, sc_if->msk_port, GM_PHY_ADDR); 4208 GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac | GM_PAR_MIB_CLR); 4209 /* Read all MIB Counters with Clear Mode set. */ 4210 for (i = GM_RXF_UC_OK; i <= GM_TXE_FIFO_UR; i += sizeof(uint32_t)) 4211 reg = MSK_READ_MIB32(sc_if->msk_port, i); 4212 /* Clear MIB Clear Counter Mode. */ 4213 gmac &= ~GM_PAR_MIB_CLR; 4214 GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac); 4215 } 4216 4217 static void 4218 msk_stats_update(struct msk_if_softc *sc_if) 4219 { 4220 struct msk_softc *sc; 4221 struct ifnet *ifp; 4222 struct msk_hw_stats *stats; 4223 uint16_t gmac; 4224 uint32_t reg; 4225 4226 MSK_IF_LOCK_ASSERT(sc_if); 4227 4228 ifp = sc_if->msk_ifp; 4229 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 4230 return; 4231 sc = sc_if->msk_softc; 4232 stats = &sc_if->msk_stats; 4233 /* Set MIB Clear Counter Mode. */ 4234 gmac = GMAC_READ_2(sc, sc_if->msk_port, GM_PHY_ADDR); 4235 GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac | GM_PAR_MIB_CLR); 4236 4237 /* Rx stats. */ 4238 stats->rx_ucast_frames += 4239 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_UC_OK); 4240 stats->rx_bcast_frames += 4241 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_BC_OK); 4242 stats->rx_pause_frames += 4243 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_MPAUSE); 4244 stats->rx_mcast_frames += 4245 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_MC_OK); 4246 stats->rx_crc_errs += 4247 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_FCS_ERR); 4248 reg = MSK_READ_MIB32(sc_if->msk_port, GM_RXF_SPARE1); 4249 stats->rx_good_octets += 4250 MSK_READ_MIB64(sc_if->msk_port, GM_RXO_OK_LO); 4251 stats->rx_bad_octets += 4252 MSK_READ_MIB64(sc_if->msk_port, GM_RXO_ERR_LO); 4253 stats->rx_runts += 4254 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_SHT); 4255 stats->rx_runt_errs += 4256 MSK_READ_MIB32(sc_if->msk_port, GM_RXE_FRAG); 4257 stats->rx_pkts_64 += 4258 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_64B); 4259 stats->rx_pkts_65_127 += 4260 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_127B); 4261 stats->rx_pkts_128_255 += 4262 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_255B); 4263 stats->rx_pkts_256_511 += 4264 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_511B); 4265 stats->rx_pkts_512_1023 += 4266 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_1023B); 4267 stats->rx_pkts_1024_1518 += 4268 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_1518B); 4269 stats->rx_pkts_1519_max += 4270 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_MAX_SZ); 4271 stats->rx_pkts_too_long += 4272 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_LNG_ERR); 4273 stats->rx_pkts_jabbers += 4274 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_JAB_PKT); 4275 reg = MSK_READ_MIB32(sc_if->msk_port, GM_RXF_SPARE2); 4276 stats->rx_fifo_oflows += 4277 MSK_READ_MIB32(sc_if->msk_port, GM_RXE_FIFO_OV); 4278 reg = MSK_READ_MIB32(sc_if->msk_port, GM_RXF_SPARE3); 4279 4280 /* Tx stats. */ 4281 stats->tx_ucast_frames += 4282 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_UC_OK); 4283 stats->tx_bcast_frames += 4284 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_BC_OK); 4285 stats->tx_pause_frames += 4286 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_MPAUSE); 4287 stats->tx_mcast_frames += 4288 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_MC_OK); 4289 stats->tx_octets += 4290 MSK_READ_MIB64(sc_if->msk_port, GM_TXO_OK_LO); 4291 stats->tx_pkts_64 += 4292 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_64B); 4293 stats->tx_pkts_65_127 += 4294 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_127B); 4295 stats->tx_pkts_128_255 += 4296 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_255B); 4297 stats->tx_pkts_256_511 += 4298 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_511B); 4299 stats->tx_pkts_512_1023 += 4300 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_1023B); 4301 stats->tx_pkts_1024_1518 += 4302 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_1518B); 4303 stats->tx_pkts_1519_max += 4304 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_MAX_SZ); 4305 reg = MSK_READ_MIB32(sc_if->msk_port, GM_TXF_SPARE1); 4306 stats->tx_colls += 4307 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_COL); 4308 stats->tx_late_colls += 4309 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_LAT_COL); 4310 stats->tx_excess_colls += 4311 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_ABO_COL); 4312 stats->tx_multi_colls += 4313 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_MUL_COL); 4314 stats->tx_single_colls += 4315 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_SNG_COL); 4316 stats->tx_underflows += 4317 MSK_READ_MIB32(sc_if->msk_port, GM_TXE_FIFO_UR); 4318 /* Clear MIB Clear Counter Mode. */ 4319 gmac &= ~GM_PAR_MIB_CLR; 4320 GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac); 4321 } 4322 4323 static int 4324 msk_sysctl_stat32(SYSCTL_HANDLER_ARGS) 4325 { 4326 struct msk_softc *sc; 4327 struct msk_if_softc *sc_if; 4328 uint32_t result, *stat; 4329 int off; 4330 4331 sc_if = (struct msk_if_softc *)arg1; 4332 sc = sc_if->msk_softc; 4333 off = arg2; 4334 stat = (uint32_t *)((uint8_t *)&sc_if->msk_stats + off); 4335 4336 MSK_IF_LOCK(sc_if); 4337 result = MSK_READ_MIB32(sc_if->msk_port, GM_MIB_CNT_BASE + off * 2); 4338 result += *stat; 4339 MSK_IF_UNLOCK(sc_if); 4340 4341 return (sysctl_handle_int(oidp, &result, 0, req)); 4342 } 4343 4344 static int 4345 msk_sysctl_stat64(SYSCTL_HANDLER_ARGS) 4346 { 4347 struct msk_softc *sc; 4348 struct msk_if_softc *sc_if; 4349 uint64_t result, *stat; 4350 int off; 4351 4352 sc_if = (struct msk_if_softc *)arg1; 4353 sc = sc_if->msk_softc; 4354 off = arg2; 4355 stat = (uint64_t *)((uint8_t *)&sc_if->msk_stats + off); 4356 4357 MSK_IF_LOCK(sc_if); 4358 result = MSK_READ_MIB64(sc_if->msk_port, GM_MIB_CNT_BASE + off * 2); 4359 result += *stat; 4360 MSK_IF_UNLOCK(sc_if); 4361 4362 return (sysctl_handle_quad(oidp, &result, 0, req)); 4363 } 4364 4365 #undef MSK_READ_MIB32 4366 #undef MSK_READ_MIB64 4367 4368 #define MSK_SYSCTL_STAT32(sc, c, o, p, n, d) \ 4369 SYSCTL_ADD_PROC(c, p, OID_AUTO, o, CTLTYPE_UINT | CTLFLAG_RD, \ 4370 sc, offsetof(struct msk_hw_stats, n), msk_sysctl_stat32, \ 4371 "IU", d) 4372 #define MSK_SYSCTL_STAT64(sc, c, o, p, n, d) \ 4373 SYSCTL_ADD_PROC(c, p, OID_AUTO, o, CTLTYPE_UINT | CTLFLAG_RD, \ 4374 sc, offsetof(struct msk_hw_stats, n), msk_sysctl_stat64, \ 4375 "Q", d) 4376 4377 static void 4378 msk_sysctl_node(struct msk_if_softc *sc_if) 4379 { 4380 struct sysctl_ctx_list *ctx; 4381 struct sysctl_oid_list *child, *schild; 4382 struct sysctl_oid *tree; 4383 4384 ctx = device_get_sysctl_ctx(sc_if->msk_if_dev); 4385 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc_if->msk_if_dev)); 4386 4387 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD, 4388 NULL, "MSK Statistics"); 4389 schild = child = SYSCTL_CHILDREN(tree); 4390 tree = SYSCTL_ADD_NODE(ctx, schild, OID_AUTO, "rx", CTLFLAG_RD, 4391 NULL, "MSK RX Statistics"); 4392 child = SYSCTL_CHILDREN(tree); 4393 MSK_SYSCTL_STAT32(sc_if, ctx, "ucast_frames", 4394 child, rx_ucast_frames, "Good unicast frames"); 4395 MSK_SYSCTL_STAT32(sc_if, ctx, "bcast_frames", 4396 child, rx_bcast_frames, "Good broadcast frames"); 4397 MSK_SYSCTL_STAT32(sc_if, ctx, "pause_frames", 4398 child, rx_pause_frames, "Pause frames"); 4399 MSK_SYSCTL_STAT32(sc_if, ctx, "mcast_frames", 4400 child, rx_mcast_frames, "Multicast frames"); 4401 MSK_SYSCTL_STAT32(sc_if, ctx, "crc_errs", 4402 child, rx_crc_errs, "CRC errors"); 4403 MSK_SYSCTL_STAT64(sc_if, ctx, "good_octets", 4404 child, rx_good_octets, "Good octets"); 4405 MSK_SYSCTL_STAT64(sc_if, ctx, "bad_octets", 4406 child, rx_bad_octets, "Bad octets"); 4407 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_64", 4408 child, rx_pkts_64, "64 bytes frames"); 4409 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_65_127", 4410 child, rx_pkts_65_127, "65 to 127 bytes frames"); 4411 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_128_255", 4412 child, rx_pkts_128_255, "128 to 255 bytes frames"); 4413 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_256_511", 4414 child, rx_pkts_256_511, "256 to 511 bytes frames"); 4415 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_512_1023", 4416 child, rx_pkts_512_1023, "512 to 1023 bytes frames"); 4417 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_1024_1518", 4418 child, rx_pkts_1024_1518, "1024 to 1518 bytes frames"); 4419 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_1519_max", 4420 child, rx_pkts_1519_max, "1519 to max frames"); 4421 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_too_long", 4422 child, rx_pkts_too_long, "frames too long"); 4423 MSK_SYSCTL_STAT32(sc_if, ctx, "jabbers", 4424 child, rx_pkts_jabbers, "Jabber errors"); 4425 MSK_SYSCTL_STAT32(sc_if, ctx, "overflows", 4426 child, rx_fifo_oflows, "FIFO overflows"); 4427 4428 tree = SYSCTL_ADD_NODE(ctx, schild, OID_AUTO, "tx", CTLFLAG_RD, 4429 NULL, "MSK TX Statistics"); 4430 child = SYSCTL_CHILDREN(tree); 4431 MSK_SYSCTL_STAT32(sc_if, ctx, "ucast_frames", 4432 child, tx_ucast_frames, "Unicast frames"); 4433 MSK_SYSCTL_STAT32(sc_if, ctx, "bcast_frames", 4434 child, tx_bcast_frames, "Broadcast frames"); 4435 MSK_SYSCTL_STAT32(sc_if, ctx, "pause_frames", 4436 child, tx_pause_frames, "Pause frames"); 4437 MSK_SYSCTL_STAT32(sc_if, ctx, "mcast_frames", 4438 child, tx_mcast_frames, "Multicast frames"); 4439 MSK_SYSCTL_STAT64(sc_if, ctx, "octets", 4440 child, tx_octets, "Octets"); 4441 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_64", 4442 child, tx_pkts_64, "64 bytes frames"); 4443 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_65_127", 4444 child, tx_pkts_65_127, "65 to 127 bytes frames"); 4445 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_128_255", 4446 child, tx_pkts_128_255, "128 to 255 bytes frames"); 4447 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_256_511", 4448 child, tx_pkts_256_511, "256 to 511 bytes frames"); 4449 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_512_1023", 4450 child, tx_pkts_512_1023, "512 to 1023 bytes frames"); 4451 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_1024_1518", 4452 child, tx_pkts_1024_1518, "1024 to 1518 bytes frames"); 4453 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_1519_max", 4454 child, tx_pkts_1519_max, "1519 to max frames"); 4455 MSK_SYSCTL_STAT32(sc_if, ctx, "colls", 4456 child, tx_colls, "Collisions"); 4457 MSK_SYSCTL_STAT32(sc_if, ctx, "late_colls", 4458 child, tx_late_colls, "Late collisions"); 4459 MSK_SYSCTL_STAT32(sc_if, ctx, "excess_colls", 4460 child, tx_excess_colls, "Excessive collisions"); 4461 MSK_SYSCTL_STAT32(sc_if, ctx, "multi_colls", 4462 child, tx_multi_colls, "Multiple collisions"); 4463 MSK_SYSCTL_STAT32(sc_if, ctx, "single_colls", 4464 child, tx_single_colls, "Single collisions"); 4465 MSK_SYSCTL_STAT32(sc_if, ctx, "underflows", 4466 child, tx_underflows, "FIFO underflows"); 4467 } 4468 4469 #undef MSK_SYSCTL_STAT32 4470 #undef MSK_SYSCTL_STAT64 4471 4472 static int 4473 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 4474 { 4475 int error, value; 4476 4477 if (!arg1) 4478 return (EINVAL); 4479 value = *(int *)arg1; 4480 error = sysctl_handle_int(oidp, &value, 0, req); 4481 if (error || !req->newptr) 4482 return (error); 4483 if (value < low || value > high) 4484 return (EINVAL); 4485 *(int *)arg1 = value; 4486 4487 return (0); 4488 } 4489 4490 static int 4491 sysctl_hw_msk_proc_limit(SYSCTL_HANDLER_ARGS) 4492 { 4493 4494 return (sysctl_int_range(oidp, arg1, arg2, req, MSK_PROC_MIN, 4495 MSK_PROC_MAX)); 4496 } 4497