1 /****************************************************************************** 2 * 3 * Name : sky2.c 4 * Project: Gigabit Ethernet Driver for FreeBSD 5.x/6.x 5 * Version: $Revision: 1.23 $ 6 * Date : $Date: 2005/12/22 09:04:11 $ 7 * Purpose: Main driver source file 8 * 9 *****************************************************************************/ 10 11 /****************************************************************************** 12 * 13 * LICENSE: 14 * Copyright (C) Marvell International Ltd. and/or its affiliates 15 * 16 * The computer program files contained in this folder ("Files") 17 * are provided to you under the BSD-type license terms provided 18 * below, and any use of such Files and any derivative works 19 * thereof created by you shall be governed by the following terms 20 * and conditions: 21 * 22 * - Redistributions of source code must retain the above copyright 23 * notice, this list of conditions and the following disclaimer. 24 * - Redistributions in binary form must reproduce the above 25 * copyright notice, this list of conditions and the following 26 * disclaimer in the documentation and/or other materials provided 27 * with the distribution. 28 * - Neither the name of Marvell nor the names of its contributors 29 * may be used to endorse or promote products derived from this 30 * software without specific prior written permission. 31 * 32 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 33 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 34 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 35 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 36 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 37 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 38 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 39 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 40 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 41 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 42 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED 43 * OF THE POSSIBILITY OF SUCH DAMAGE. 44 * /LICENSE 45 * 46 *****************************************************************************/ 47 48 /*- 49 * Copyright (c) 1997, 1998, 1999, 2000 50 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 51 * 52 * Redistribution and use in source and binary forms, with or without 53 * modification, are permitted provided that the following conditions 54 * are met: 55 * 1. Redistributions of source code must retain the above copyright 56 * notice, this list of conditions and the following disclaimer. 57 * 2. Redistributions in binary form must reproduce the above copyright 58 * notice, this list of conditions and the following disclaimer in the 59 * documentation and/or other materials provided with the distribution. 60 * 3. All advertising materials mentioning features or use of this software 61 * must display the following acknowledgement: 62 * This product includes software developed by Bill Paul. 63 * 4. Neither the name of the author nor the names of any co-contributors 64 * may be used to endorse or promote products derived from this software 65 * without specific prior written permission. 66 * 67 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 68 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 69 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 70 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 71 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 72 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 73 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 74 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 75 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 76 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 77 * THE POSSIBILITY OF SUCH DAMAGE. 78 */ 79 /*- 80 * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu> 81 * 82 * Permission to use, copy, modify, and distribute this software for any 83 * purpose with or without fee is hereby granted, provided that the above 84 * copyright notice and this permission notice appear in all copies. 85 * 86 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 87 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 88 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 89 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 90 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 91 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 92 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 93 */ 94 95 /* 96 * Device driver for the Marvell Yukon II Ethernet controller. 97 * Due to lack of documentation, this driver is based on the code from 98 * sk(4) and Marvell's myk(4) driver for FreeBSD 5.x. 99 */ 100 101 #include <sys/cdefs.h> 102 __FBSDID("$FreeBSD$"); 103 104 #include <sys/param.h> 105 #include <sys/systm.h> 106 #include <sys/bus.h> 107 #include <sys/endian.h> 108 #include <sys/mbuf.h> 109 #include <sys/malloc.h> 110 #include <sys/kernel.h> 111 #include <sys/module.h> 112 #include <sys/socket.h> 113 #include <sys/sockio.h> 114 #include <sys/queue.h> 115 #include <sys/sysctl.h> 116 117 #include <net/bpf.h> 118 #include <net/ethernet.h> 119 #include <net/if.h> 120 #include <net/if_arp.h> 121 #include <net/if_dl.h> 122 #include <net/if_media.h> 123 #include <net/if_types.h> 124 #include <net/if_vlan_var.h> 125 126 #include <netinet/in.h> 127 #include <netinet/in_systm.h> 128 #include <netinet/ip.h> 129 #include <netinet/tcp.h> 130 #include <netinet/udp.h> 131 132 #include <machine/bus.h> 133 #include <machine/in_cksum.h> 134 #include <machine/resource.h> 135 #include <sys/rman.h> 136 137 #include <dev/mii/mii.h> 138 #include <dev/mii/miivar.h> 139 140 #include <dev/pci/pcireg.h> 141 #include <dev/pci/pcivar.h> 142 143 #include <dev/msk/if_mskreg.h> 144 145 MODULE_DEPEND(msk, pci, 1, 1, 1); 146 MODULE_DEPEND(msk, ether, 1, 1, 1); 147 MODULE_DEPEND(msk, miibus, 1, 1, 1); 148 149 /* "device miibus" required. See GENERIC if you get errors here. */ 150 #include "miibus_if.h" 151 152 /* Tunables. */ 153 static int msi_disable = 0; 154 TUNABLE_INT("hw.msk.msi_disable", &msi_disable); 155 static int legacy_intr = 0; 156 TUNABLE_INT("hw.msk.legacy_intr", &legacy_intr); 157 static int jumbo_disable = 0; 158 TUNABLE_INT("hw.msk.jumbo_disable", &jumbo_disable); 159 160 #define MSK_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 161 162 /* 163 * Devices supported by this driver. 164 */ 165 static struct msk_product { 166 uint16_t msk_vendorid; 167 uint16_t msk_deviceid; 168 const char *msk_name; 169 } msk_products[] = { 170 { VENDORID_SK, DEVICEID_SK_YUKON2, 171 "SK-9Sxx Gigabit Ethernet" }, 172 { VENDORID_SK, DEVICEID_SK_YUKON2_EXPR, 173 "SK-9Exx Gigabit Ethernet"}, 174 { VENDORID_MARVELL, DEVICEID_MRVL_8021CU, 175 "Marvell Yukon 88E8021CU Gigabit Ethernet" }, 176 { VENDORID_MARVELL, DEVICEID_MRVL_8021X, 177 "Marvell Yukon 88E8021 SX/LX Gigabit Ethernet" }, 178 { VENDORID_MARVELL, DEVICEID_MRVL_8022CU, 179 "Marvell Yukon 88E8022CU Gigabit Ethernet" }, 180 { VENDORID_MARVELL, DEVICEID_MRVL_8022X, 181 "Marvell Yukon 88E8022 SX/LX Gigabit Ethernet" }, 182 { VENDORID_MARVELL, DEVICEID_MRVL_8061CU, 183 "Marvell Yukon 88E8061CU Gigabit Ethernet" }, 184 { VENDORID_MARVELL, DEVICEID_MRVL_8061X, 185 "Marvell Yukon 88E8061 SX/LX Gigabit Ethernet" }, 186 { VENDORID_MARVELL, DEVICEID_MRVL_8062CU, 187 "Marvell Yukon 88E8062CU Gigabit Ethernet" }, 188 { VENDORID_MARVELL, DEVICEID_MRVL_8062X, 189 "Marvell Yukon 88E8062 SX/LX Gigabit Ethernet" }, 190 { VENDORID_MARVELL, DEVICEID_MRVL_8035, 191 "Marvell Yukon 88E8035 Fast Ethernet" }, 192 { VENDORID_MARVELL, DEVICEID_MRVL_8036, 193 "Marvell Yukon 88E8036 Fast Ethernet" }, 194 { VENDORID_MARVELL, DEVICEID_MRVL_8038, 195 "Marvell Yukon 88E8038 Fast Ethernet" }, 196 { VENDORID_MARVELL, DEVICEID_MRVL_8039, 197 "Marvell Yukon 88E8039 Fast Ethernet" }, 198 { VENDORID_MARVELL, DEVICEID_MRVL_8040, 199 "Marvell Yukon 88E8040 Fast Ethernet" }, 200 { VENDORID_MARVELL, DEVICEID_MRVL_8040T, 201 "Marvell Yukon 88E8040T Fast Ethernet" }, 202 { VENDORID_MARVELL, DEVICEID_MRVL_8042, 203 "Marvell Yukon 88E8042 Fast Ethernet" }, 204 { VENDORID_MARVELL, DEVICEID_MRVL_8048, 205 "Marvell Yukon 88E8048 Fast Ethernet" }, 206 { VENDORID_MARVELL, DEVICEID_MRVL_4361, 207 "Marvell Yukon 88E8050 Gigabit Ethernet" }, 208 { VENDORID_MARVELL, DEVICEID_MRVL_4360, 209 "Marvell Yukon 88E8052 Gigabit Ethernet" }, 210 { VENDORID_MARVELL, DEVICEID_MRVL_4362, 211 "Marvell Yukon 88E8053 Gigabit Ethernet" }, 212 { VENDORID_MARVELL, DEVICEID_MRVL_4363, 213 "Marvell Yukon 88E8055 Gigabit Ethernet" }, 214 { VENDORID_MARVELL, DEVICEID_MRVL_4364, 215 "Marvell Yukon 88E8056 Gigabit Ethernet" }, 216 { VENDORID_MARVELL, DEVICEID_MRVL_4365, 217 "Marvell Yukon 88E8070 Gigabit Ethernet" }, 218 { VENDORID_MARVELL, DEVICEID_MRVL_436A, 219 "Marvell Yukon 88E8058 Gigabit Ethernet" }, 220 { VENDORID_MARVELL, DEVICEID_MRVL_436B, 221 "Marvell Yukon 88E8071 Gigabit Ethernet" }, 222 { VENDORID_MARVELL, DEVICEID_MRVL_436C, 223 "Marvell Yukon 88E8072 Gigabit Ethernet" }, 224 { VENDORID_MARVELL, DEVICEID_MRVL_436D, 225 "Marvell Yukon 88E8055 Gigabit Ethernet" }, 226 { VENDORID_MARVELL, DEVICEID_MRVL_4370, 227 "Marvell Yukon 88E8075 Gigabit Ethernet" }, 228 { VENDORID_MARVELL, DEVICEID_MRVL_4380, 229 "Marvell Yukon 88E8057 Gigabit Ethernet" }, 230 { VENDORID_MARVELL, DEVICEID_MRVL_4381, 231 "Marvell Yukon 88E8059 Gigabit Ethernet" }, 232 { VENDORID_DLINK, DEVICEID_DLINK_DGE550SX, 233 "D-Link 550SX Gigabit Ethernet" }, 234 { VENDORID_DLINK, DEVICEID_DLINK_DGE560SX, 235 "D-Link 560SX Gigabit Ethernet" }, 236 { VENDORID_DLINK, DEVICEID_DLINK_DGE560T, 237 "D-Link 560T Gigabit Ethernet" } 238 }; 239 240 static const char *model_name[] = { 241 "Yukon XL", 242 "Yukon EC Ultra", 243 "Yukon EX", 244 "Yukon EC", 245 "Yukon FE", 246 "Yukon FE+", 247 "Yukon Supreme", 248 "Yukon Ultra 2", 249 "Yukon Unknown", 250 "Yukon Optima", 251 }; 252 253 static int mskc_probe(device_t); 254 static int mskc_attach(device_t); 255 static int mskc_detach(device_t); 256 static int mskc_shutdown(device_t); 257 static int mskc_setup_rambuffer(struct msk_softc *); 258 static int mskc_suspend(device_t); 259 static int mskc_resume(device_t); 260 static void mskc_reset(struct msk_softc *); 261 262 static int msk_probe(device_t); 263 static int msk_attach(device_t); 264 static int msk_detach(device_t); 265 266 static void msk_tick(void *); 267 static void msk_intr(void *); 268 static void msk_intr_phy(struct msk_if_softc *); 269 static void msk_intr_gmac(struct msk_if_softc *); 270 static __inline void msk_rxput(struct msk_if_softc *); 271 static int msk_handle_events(struct msk_softc *); 272 static void msk_handle_hwerr(struct msk_if_softc *, uint32_t); 273 static void msk_intr_hwerr(struct msk_softc *); 274 #ifndef __NO_STRICT_ALIGNMENT 275 static __inline void msk_fixup_rx(struct mbuf *); 276 #endif 277 static __inline void msk_rxcsum(struct msk_if_softc *, uint32_t, struct mbuf *); 278 static void msk_rxeof(struct msk_if_softc *, uint32_t, uint32_t, int); 279 static void msk_jumbo_rxeof(struct msk_if_softc *, uint32_t, uint32_t, int); 280 static void msk_txeof(struct msk_if_softc *, int); 281 static int msk_encap(struct msk_if_softc *, struct mbuf **); 282 static void msk_start(struct ifnet *); 283 static void msk_start_locked(struct ifnet *); 284 static int msk_ioctl(struct ifnet *, u_long, caddr_t); 285 static void msk_set_prefetch(struct msk_softc *, int, bus_addr_t, uint32_t); 286 static void msk_set_rambuffer(struct msk_if_softc *); 287 static void msk_set_tx_stfwd(struct msk_if_softc *); 288 static void msk_init(void *); 289 static void msk_init_locked(struct msk_if_softc *); 290 static void msk_stop(struct msk_if_softc *); 291 static void msk_watchdog(struct msk_if_softc *); 292 static int msk_mediachange(struct ifnet *); 293 static void msk_mediastatus(struct ifnet *, struct ifmediareq *); 294 static void msk_phy_power(struct msk_softc *, int); 295 static void msk_dmamap_cb(void *, bus_dma_segment_t *, int, int); 296 static int msk_status_dma_alloc(struct msk_softc *); 297 static void msk_status_dma_free(struct msk_softc *); 298 static int msk_txrx_dma_alloc(struct msk_if_softc *); 299 static int msk_rx_dma_jalloc(struct msk_if_softc *); 300 static void msk_txrx_dma_free(struct msk_if_softc *); 301 static void msk_rx_dma_jfree(struct msk_if_softc *); 302 static int msk_rx_fill(struct msk_if_softc *, int); 303 static int msk_init_rx_ring(struct msk_if_softc *); 304 static int msk_init_jumbo_rx_ring(struct msk_if_softc *); 305 static void msk_init_tx_ring(struct msk_if_softc *); 306 static __inline void msk_discard_rxbuf(struct msk_if_softc *, int); 307 static __inline void msk_discard_jumbo_rxbuf(struct msk_if_softc *, int); 308 static int msk_newbuf(struct msk_if_softc *, int); 309 static int msk_jumbo_newbuf(struct msk_if_softc *, int); 310 311 static int msk_phy_readreg(struct msk_if_softc *, int, int); 312 static int msk_phy_writereg(struct msk_if_softc *, int, int, int); 313 static int msk_miibus_readreg(device_t, int, int); 314 static int msk_miibus_writereg(device_t, int, int, int); 315 static void msk_miibus_statchg(device_t); 316 317 static void msk_rxfilter(struct msk_if_softc *); 318 static void msk_setvlan(struct msk_if_softc *, struct ifnet *); 319 320 static void msk_stats_clear(struct msk_if_softc *); 321 static void msk_stats_update(struct msk_if_softc *); 322 static int msk_sysctl_stat32(SYSCTL_HANDLER_ARGS); 323 static int msk_sysctl_stat64(SYSCTL_HANDLER_ARGS); 324 static void msk_sysctl_node(struct msk_if_softc *); 325 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int); 326 static int sysctl_hw_msk_proc_limit(SYSCTL_HANDLER_ARGS); 327 328 static device_method_t mskc_methods[] = { 329 /* Device interface */ 330 DEVMETHOD(device_probe, mskc_probe), 331 DEVMETHOD(device_attach, mskc_attach), 332 DEVMETHOD(device_detach, mskc_detach), 333 DEVMETHOD(device_suspend, mskc_suspend), 334 DEVMETHOD(device_resume, mskc_resume), 335 DEVMETHOD(device_shutdown, mskc_shutdown), 336 337 DEVMETHOD_END 338 }; 339 340 static driver_t mskc_driver = { 341 "mskc", 342 mskc_methods, 343 sizeof(struct msk_softc) 344 }; 345 346 static devclass_t mskc_devclass; 347 348 static device_method_t msk_methods[] = { 349 /* Device interface */ 350 DEVMETHOD(device_probe, msk_probe), 351 DEVMETHOD(device_attach, msk_attach), 352 DEVMETHOD(device_detach, msk_detach), 353 DEVMETHOD(device_shutdown, bus_generic_shutdown), 354 355 /* MII interface */ 356 DEVMETHOD(miibus_readreg, msk_miibus_readreg), 357 DEVMETHOD(miibus_writereg, msk_miibus_writereg), 358 DEVMETHOD(miibus_statchg, msk_miibus_statchg), 359 360 DEVMETHOD_END 361 }; 362 363 static driver_t msk_driver = { 364 "msk", 365 msk_methods, 366 sizeof(struct msk_if_softc) 367 }; 368 369 static devclass_t msk_devclass; 370 371 DRIVER_MODULE(mskc, pci, mskc_driver, mskc_devclass, 0, 0); 372 DRIVER_MODULE(msk, mskc, msk_driver, msk_devclass, 0, 0); 373 DRIVER_MODULE(miibus, msk, miibus_driver, miibus_devclass, 0, 0); 374 375 static struct resource_spec msk_res_spec_io[] = { 376 { SYS_RES_IOPORT, PCIR_BAR(1), RF_ACTIVE }, 377 { -1, 0, 0 } 378 }; 379 380 static struct resource_spec msk_res_spec_mem[] = { 381 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 382 { -1, 0, 0 } 383 }; 384 385 static struct resource_spec msk_irq_spec_legacy[] = { 386 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 387 { -1, 0, 0 } 388 }; 389 390 static struct resource_spec msk_irq_spec_msi[] = { 391 { SYS_RES_IRQ, 1, RF_ACTIVE }, 392 { -1, 0, 0 } 393 }; 394 395 static int 396 msk_miibus_readreg(device_t dev, int phy, int reg) 397 { 398 struct msk_if_softc *sc_if; 399 400 sc_if = device_get_softc(dev); 401 402 return (msk_phy_readreg(sc_if, phy, reg)); 403 } 404 405 static int 406 msk_phy_readreg(struct msk_if_softc *sc_if, int phy, int reg) 407 { 408 struct msk_softc *sc; 409 int i, val; 410 411 sc = sc_if->msk_softc; 412 413 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SMI_CTRL, 414 GM_SMI_CT_PHY_AD(phy) | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD); 415 416 for (i = 0; i < MSK_TIMEOUT; i++) { 417 DELAY(1); 418 val = GMAC_READ_2(sc, sc_if->msk_port, GM_SMI_CTRL); 419 if ((val & GM_SMI_CT_RD_VAL) != 0) { 420 val = GMAC_READ_2(sc, sc_if->msk_port, GM_SMI_DATA); 421 break; 422 } 423 } 424 425 if (i == MSK_TIMEOUT) { 426 if_printf(sc_if->msk_ifp, "phy failed to come ready\n"); 427 val = 0; 428 } 429 430 return (val); 431 } 432 433 static int 434 msk_miibus_writereg(device_t dev, int phy, int reg, int val) 435 { 436 struct msk_if_softc *sc_if; 437 438 sc_if = device_get_softc(dev); 439 440 return (msk_phy_writereg(sc_if, phy, reg, val)); 441 } 442 443 static int 444 msk_phy_writereg(struct msk_if_softc *sc_if, int phy, int reg, int val) 445 { 446 struct msk_softc *sc; 447 int i; 448 449 sc = sc_if->msk_softc; 450 451 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SMI_DATA, val); 452 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SMI_CTRL, 453 GM_SMI_CT_PHY_AD(phy) | GM_SMI_CT_REG_AD(reg)); 454 for (i = 0; i < MSK_TIMEOUT; i++) { 455 DELAY(1); 456 if ((GMAC_READ_2(sc, sc_if->msk_port, GM_SMI_CTRL) & 457 GM_SMI_CT_BUSY) == 0) 458 break; 459 } 460 if (i == MSK_TIMEOUT) 461 if_printf(sc_if->msk_ifp, "phy write timeout\n"); 462 463 return (0); 464 } 465 466 static void 467 msk_miibus_statchg(device_t dev) 468 { 469 struct msk_softc *sc; 470 struct msk_if_softc *sc_if; 471 struct mii_data *mii; 472 struct ifnet *ifp; 473 uint32_t gmac; 474 475 sc_if = device_get_softc(dev); 476 sc = sc_if->msk_softc; 477 478 MSK_IF_LOCK_ASSERT(sc_if); 479 480 mii = device_get_softc(sc_if->msk_miibus); 481 ifp = sc_if->msk_ifp; 482 if (mii == NULL || ifp == NULL || 483 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 484 return; 485 486 sc_if->msk_flags &= ~MSK_FLAG_LINK; 487 if ((mii->mii_media_status & (IFM_AVALID | IFM_ACTIVE)) == 488 (IFM_AVALID | IFM_ACTIVE)) { 489 switch (IFM_SUBTYPE(mii->mii_media_active)) { 490 case IFM_10_T: 491 case IFM_100_TX: 492 sc_if->msk_flags |= MSK_FLAG_LINK; 493 break; 494 case IFM_1000_T: 495 case IFM_1000_SX: 496 case IFM_1000_LX: 497 case IFM_1000_CX: 498 if ((sc_if->msk_flags & MSK_FLAG_FASTETHER) == 0) 499 sc_if->msk_flags |= MSK_FLAG_LINK; 500 break; 501 default: 502 break; 503 } 504 } 505 506 if ((sc_if->msk_flags & MSK_FLAG_LINK) != 0) { 507 /* Enable Tx FIFO Underrun. */ 508 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_MSK), 509 GM_IS_TX_FF_UR | GM_IS_RX_FF_OR); 510 /* 511 * Because mii(4) notify msk(4) that it detected link status 512 * change, there is no need to enable automatic 513 * speed/flow-control/duplex updates. 514 */ 515 gmac = GM_GPCR_AU_ALL_DIS; 516 switch (IFM_SUBTYPE(mii->mii_media_active)) { 517 case IFM_1000_SX: 518 case IFM_1000_T: 519 gmac |= GM_GPCR_SPEED_1000; 520 break; 521 case IFM_100_TX: 522 gmac |= GM_GPCR_SPEED_100; 523 break; 524 case IFM_10_T: 525 break; 526 } 527 528 if ((IFM_OPTIONS(mii->mii_media_active) & 529 IFM_ETH_RXPAUSE) == 0) 530 gmac |= GM_GPCR_FC_RX_DIS; 531 if ((IFM_OPTIONS(mii->mii_media_active) & 532 IFM_ETH_TXPAUSE) == 0) 533 gmac |= GM_GPCR_FC_TX_DIS; 534 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) 535 gmac |= GM_GPCR_DUP_FULL; 536 else 537 gmac |= GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS; 538 gmac |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA; 539 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, gmac); 540 /* Read again to ensure writing. */ 541 GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL); 542 gmac = GMC_PAUSE_OFF; 543 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 544 if ((IFM_OPTIONS(mii->mii_media_active) & 545 IFM_ETH_RXPAUSE) != 0) 546 gmac = GMC_PAUSE_ON; 547 } 548 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), gmac); 549 550 /* Enable PHY interrupt for FIFO underrun/overflow. */ 551 msk_phy_writereg(sc_if, PHY_ADDR_MARV, 552 PHY_MARV_INT_MASK, PHY_M_IS_FIFO_ERROR); 553 } else { 554 /* 555 * Link state changed to down. 556 * Disable PHY interrupts. 557 */ 558 msk_phy_writereg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_MASK, 0); 559 /* Disable Rx/Tx MAC. */ 560 gmac = GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL); 561 if ((gmac & (GM_GPCR_RX_ENA | GM_GPCR_TX_ENA)) != 0) { 562 gmac &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA); 563 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, gmac); 564 /* Read again to ensure writing. */ 565 GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL); 566 } 567 } 568 } 569 570 static void 571 msk_rxfilter(struct msk_if_softc *sc_if) 572 { 573 struct msk_softc *sc; 574 struct ifnet *ifp; 575 struct ifmultiaddr *ifma; 576 uint32_t mchash[2]; 577 uint32_t crc; 578 uint16_t mode; 579 580 sc = sc_if->msk_softc; 581 582 MSK_IF_LOCK_ASSERT(sc_if); 583 584 ifp = sc_if->msk_ifp; 585 586 bzero(mchash, sizeof(mchash)); 587 mode = GMAC_READ_2(sc, sc_if->msk_port, GM_RX_CTRL); 588 if ((ifp->if_flags & IFF_PROMISC) != 0) 589 mode &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA); 590 else if ((ifp->if_flags & IFF_ALLMULTI) != 0) { 591 mode |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA; 592 mchash[0] = 0xffff; 593 mchash[1] = 0xffff; 594 } else { 595 mode |= GM_RXCR_UCF_ENA; 596 if_maddr_rlock(ifp); 597 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 598 if (ifma->ifma_addr->sa_family != AF_LINK) 599 continue; 600 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *) 601 ifma->ifma_addr), ETHER_ADDR_LEN); 602 /* Just want the 6 least significant bits. */ 603 crc &= 0x3f; 604 /* Set the corresponding bit in the hash table. */ 605 mchash[crc >> 5] |= 1 << (crc & 0x1f); 606 } 607 if_maddr_runlock(ifp); 608 if (mchash[0] != 0 || mchash[1] != 0) 609 mode |= GM_RXCR_MCF_ENA; 610 } 611 612 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H1, 613 mchash[0] & 0xffff); 614 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H2, 615 (mchash[0] >> 16) & 0xffff); 616 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H3, 617 mchash[1] & 0xffff); 618 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H4, 619 (mchash[1] >> 16) & 0xffff); 620 GMAC_WRITE_2(sc, sc_if->msk_port, GM_RX_CTRL, mode); 621 } 622 623 static void 624 msk_setvlan(struct msk_if_softc *sc_if, struct ifnet *ifp) 625 { 626 struct msk_softc *sc; 627 628 sc = sc_if->msk_softc; 629 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) { 630 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), 631 RX_VLAN_STRIP_ON); 632 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 633 TX_VLAN_TAG_ON); 634 } else { 635 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), 636 RX_VLAN_STRIP_OFF); 637 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 638 TX_VLAN_TAG_OFF); 639 } 640 } 641 642 static int 643 msk_rx_fill(struct msk_if_softc *sc_if, int jumbo) 644 { 645 uint16_t idx; 646 int i; 647 648 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0 && 649 (sc_if->msk_ifp->if_capenable & IFCAP_RXCSUM) != 0) { 650 /* Wait until controller executes OP_TCPSTART command. */ 651 for (i = 100; i > 0; i--) { 652 DELAY(100); 653 idx = CSR_READ_2(sc_if->msk_softc, 654 Y2_PREF_Q_ADDR(sc_if->msk_rxq, 655 PREF_UNIT_GET_IDX_REG)); 656 if (idx != 0) 657 break; 658 } 659 if (i == 0) { 660 device_printf(sc_if->msk_if_dev, 661 "prefetch unit stuck?\n"); 662 return (ETIMEDOUT); 663 } 664 /* 665 * Fill consumed LE with free buffer. This can be done 666 * in Rx handler but we don't want to add special code 667 * in fast handler. 668 */ 669 if (jumbo > 0) { 670 if (msk_jumbo_newbuf(sc_if, 0) != 0) 671 return (ENOBUFS); 672 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 673 sc_if->msk_cdata.msk_jumbo_rx_ring_map, 674 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 675 } else { 676 if (msk_newbuf(sc_if, 0) != 0) 677 return (ENOBUFS); 678 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_ring_tag, 679 sc_if->msk_cdata.msk_rx_ring_map, 680 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 681 } 682 sc_if->msk_cdata.msk_rx_prod = 0; 683 CSR_WRITE_2(sc_if->msk_softc, 684 Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_PUT_IDX_REG), 685 sc_if->msk_cdata.msk_rx_prod); 686 } 687 return (0); 688 } 689 690 static int 691 msk_init_rx_ring(struct msk_if_softc *sc_if) 692 { 693 struct msk_ring_data *rd; 694 struct msk_rxdesc *rxd; 695 int i, nbuf, prod; 696 697 MSK_IF_LOCK_ASSERT(sc_if); 698 699 sc_if->msk_cdata.msk_rx_cons = 0; 700 sc_if->msk_cdata.msk_rx_prod = 0; 701 sc_if->msk_cdata.msk_rx_putwm = MSK_PUT_WM; 702 703 rd = &sc_if->msk_rdata; 704 bzero(rd->msk_rx_ring, sizeof(struct msk_rx_desc) * MSK_RX_RING_CNT); 705 for (i = prod = 0; i < MSK_RX_RING_CNT; i++) { 706 rxd = &sc_if->msk_cdata.msk_rxdesc[prod]; 707 rxd->rx_m = NULL; 708 rxd->rx_le = &rd->msk_rx_ring[prod]; 709 MSK_INC(prod, MSK_RX_RING_CNT); 710 } 711 nbuf = MSK_RX_BUF_CNT; 712 prod = 0; 713 /* Have controller know how to compute Rx checksum. */ 714 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0 && 715 (sc_if->msk_ifp->if_capenable & IFCAP_RXCSUM) != 0) { 716 #ifdef MSK_64BIT_DMA 717 rxd = &sc_if->msk_cdata.msk_rxdesc[prod]; 718 rxd->rx_m = NULL; 719 rxd->rx_le = &rd->msk_rx_ring[prod]; 720 rxd->rx_le->msk_addr = htole32(ETHER_HDR_LEN << 16 | 721 ETHER_HDR_LEN); 722 rxd->rx_le->msk_control = htole32(OP_TCPSTART | HW_OWNER); 723 MSK_INC(prod, MSK_RX_RING_CNT); 724 MSK_INC(sc_if->msk_cdata.msk_rx_cons, MSK_RX_RING_CNT); 725 #endif 726 rxd = &sc_if->msk_cdata.msk_rxdesc[prod]; 727 rxd->rx_m = NULL; 728 rxd->rx_le = &rd->msk_rx_ring[prod]; 729 rxd->rx_le->msk_addr = htole32(ETHER_HDR_LEN << 16 | 730 ETHER_HDR_LEN); 731 rxd->rx_le->msk_control = htole32(OP_TCPSTART | HW_OWNER); 732 MSK_INC(prod, MSK_RX_RING_CNT); 733 MSK_INC(sc_if->msk_cdata.msk_rx_cons, MSK_RX_RING_CNT); 734 nbuf--; 735 } 736 for (i = 0; i < nbuf; i++) { 737 if (msk_newbuf(sc_if, prod) != 0) 738 return (ENOBUFS); 739 MSK_RX_INC(prod, MSK_RX_RING_CNT); 740 } 741 742 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_ring_tag, 743 sc_if->msk_cdata.msk_rx_ring_map, 744 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 745 746 /* Update prefetch unit. */ 747 sc_if->msk_cdata.msk_rx_prod = prod; 748 CSR_WRITE_2(sc_if->msk_softc, 749 Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_PUT_IDX_REG), 750 (sc_if->msk_cdata.msk_rx_prod + MSK_RX_RING_CNT - 1) % 751 MSK_RX_RING_CNT); 752 if (msk_rx_fill(sc_if, 0) != 0) 753 return (ENOBUFS); 754 return (0); 755 } 756 757 static int 758 msk_init_jumbo_rx_ring(struct msk_if_softc *sc_if) 759 { 760 struct msk_ring_data *rd; 761 struct msk_rxdesc *rxd; 762 int i, nbuf, prod; 763 764 MSK_IF_LOCK_ASSERT(sc_if); 765 766 sc_if->msk_cdata.msk_rx_cons = 0; 767 sc_if->msk_cdata.msk_rx_prod = 0; 768 sc_if->msk_cdata.msk_rx_putwm = MSK_PUT_WM; 769 770 rd = &sc_if->msk_rdata; 771 bzero(rd->msk_jumbo_rx_ring, 772 sizeof(struct msk_rx_desc) * MSK_JUMBO_RX_RING_CNT); 773 for (i = prod = 0; i < MSK_JUMBO_RX_RING_CNT; i++) { 774 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[prod]; 775 rxd->rx_m = NULL; 776 rxd->rx_le = &rd->msk_jumbo_rx_ring[prod]; 777 MSK_INC(prod, MSK_JUMBO_RX_RING_CNT); 778 } 779 nbuf = MSK_RX_BUF_CNT; 780 prod = 0; 781 /* Have controller know how to compute Rx checksum. */ 782 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0 && 783 (sc_if->msk_ifp->if_capenable & IFCAP_RXCSUM) != 0) { 784 #ifdef MSK_64BIT_DMA 785 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[prod]; 786 rxd->rx_m = NULL; 787 rxd->rx_le = &rd->msk_jumbo_rx_ring[prod]; 788 rxd->rx_le->msk_addr = htole32(ETHER_HDR_LEN << 16 | 789 ETHER_HDR_LEN); 790 rxd->rx_le->msk_control = htole32(OP_TCPSTART | HW_OWNER); 791 MSK_INC(prod, MSK_JUMBO_RX_RING_CNT); 792 MSK_INC(sc_if->msk_cdata.msk_rx_cons, MSK_JUMBO_RX_RING_CNT); 793 #endif 794 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[prod]; 795 rxd->rx_m = NULL; 796 rxd->rx_le = &rd->msk_jumbo_rx_ring[prod]; 797 rxd->rx_le->msk_addr = htole32(ETHER_HDR_LEN << 16 | 798 ETHER_HDR_LEN); 799 rxd->rx_le->msk_control = htole32(OP_TCPSTART | HW_OWNER); 800 MSK_INC(prod, MSK_JUMBO_RX_RING_CNT); 801 MSK_INC(sc_if->msk_cdata.msk_rx_cons, MSK_JUMBO_RX_RING_CNT); 802 nbuf--; 803 } 804 for (i = 0; i < nbuf; i++) { 805 if (msk_jumbo_newbuf(sc_if, prod) != 0) 806 return (ENOBUFS); 807 MSK_RX_INC(prod, MSK_JUMBO_RX_RING_CNT); 808 } 809 810 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 811 sc_if->msk_cdata.msk_jumbo_rx_ring_map, 812 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 813 814 /* Update prefetch unit. */ 815 sc_if->msk_cdata.msk_rx_prod = prod; 816 CSR_WRITE_2(sc_if->msk_softc, 817 Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_PUT_IDX_REG), 818 (sc_if->msk_cdata.msk_rx_prod + MSK_JUMBO_RX_RING_CNT - 1) % 819 MSK_JUMBO_RX_RING_CNT); 820 if (msk_rx_fill(sc_if, 1) != 0) 821 return (ENOBUFS); 822 return (0); 823 } 824 825 static void 826 msk_init_tx_ring(struct msk_if_softc *sc_if) 827 { 828 struct msk_ring_data *rd; 829 struct msk_txdesc *txd; 830 int i; 831 832 sc_if->msk_cdata.msk_tso_mtu = 0; 833 sc_if->msk_cdata.msk_last_csum = 0; 834 sc_if->msk_cdata.msk_tx_prod = 0; 835 sc_if->msk_cdata.msk_tx_cons = 0; 836 sc_if->msk_cdata.msk_tx_cnt = 0; 837 sc_if->msk_cdata.msk_tx_high_addr = 0; 838 839 rd = &sc_if->msk_rdata; 840 bzero(rd->msk_tx_ring, sizeof(struct msk_tx_desc) * MSK_TX_RING_CNT); 841 for (i = 0; i < MSK_TX_RING_CNT; i++) { 842 txd = &sc_if->msk_cdata.msk_txdesc[i]; 843 txd->tx_m = NULL; 844 txd->tx_le = &rd->msk_tx_ring[i]; 845 } 846 847 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_ring_tag, 848 sc_if->msk_cdata.msk_tx_ring_map, 849 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 850 } 851 852 static __inline void 853 msk_discard_rxbuf(struct msk_if_softc *sc_if, int idx) 854 { 855 struct msk_rx_desc *rx_le; 856 struct msk_rxdesc *rxd; 857 struct mbuf *m; 858 859 #ifdef MSK_64BIT_DMA 860 rxd = &sc_if->msk_cdata.msk_rxdesc[idx]; 861 rx_le = rxd->rx_le; 862 rx_le->msk_control = htole32(OP_ADDR64 | HW_OWNER); 863 MSK_INC(idx, MSK_RX_RING_CNT); 864 #endif 865 rxd = &sc_if->msk_cdata.msk_rxdesc[idx]; 866 m = rxd->rx_m; 867 rx_le = rxd->rx_le; 868 rx_le->msk_control = htole32(m->m_len | OP_PACKET | HW_OWNER); 869 } 870 871 static __inline void 872 msk_discard_jumbo_rxbuf(struct msk_if_softc *sc_if, int idx) 873 { 874 struct msk_rx_desc *rx_le; 875 struct msk_rxdesc *rxd; 876 struct mbuf *m; 877 878 #ifdef MSK_64BIT_DMA 879 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[idx]; 880 rx_le = rxd->rx_le; 881 rx_le->msk_control = htole32(OP_ADDR64 | HW_OWNER); 882 MSK_INC(idx, MSK_JUMBO_RX_RING_CNT); 883 #endif 884 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[idx]; 885 m = rxd->rx_m; 886 rx_le = rxd->rx_le; 887 rx_le->msk_control = htole32(m->m_len | OP_PACKET | HW_OWNER); 888 } 889 890 static int 891 msk_newbuf(struct msk_if_softc *sc_if, int idx) 892 { 893 struct msk_rx_desc *rx_le; 894 struct msk_rxdesc *rxd; 895 struct mbuf *m; 896 bus_dma_segment_t segs[1]; 897 bus_dmamap_t map; 898 int nsegs; 899 900 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 901 if (m == NULL) 902 return (ENOBUFS); 903 904 m->m_len = m->m_pkthdr.len = MCLBYTES; 905 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) == 0) 906 m_adj(m, ETHER_ALIGN); 907 #ifndef __NO_STRICT_ALIGNMENT 908 else 909 m_adj(m, MSK_RX_BUF_ALIGN); 910 #endif 911 912 if (bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_rx_tag, 913 sc_if->msk_cdata.msk_rx_sparemap, m, segs, &nsegs, 914 BUS_DMA_NOWAIT) != 0) { 915 m_freem(m); 916 return (ENOBUFS); 917 } 918 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 919 920 rxd = &sc_if->msk_cdata.msk_rxdesc[idx]; 921 #ifdef MSK_64BIT_DMA 922 rx_le = rxd->rx_le; 923 rx_le->msk_addr = htole32(MSK_ADDR_HI(segs[0].ds_addr)); 924 rx_le->msk_control = htole32(OP_ADDR64 | HW_OWNER); 925 MSK_INC(idx, MSK_RX_RING_CNT); 926 rxd = &sc_if->msk_cdata.msk_rxdesc[idx]; 927 #endif 928 if (rxd->rx_m != NULL) { 929 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_tag, rxd->rx_dmamap, 930 BUS_DMASYNC_POSTREAD); 931 bus_dmamap_unload(sc_if->msk_cdata.msk_rx_tag, rxd->rx_dmamap); 932 rxd->rx_m = NULL; 933 } 934 map = rxd->rx_dmamap; 935 rxd->rx_dmamap = sc_if->msk_cdata.msk_rx_sparemap; 936 sc_if->msk_cdata.msk_rx_sparemap = map; 937 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_tag, rxd->rx_dmamap, 938 BUS_DMASYNC_PREREAD); 939 rxd->rx_m = m; 940 rx_le = rxd->rx_le; 941 rx_le->msk_addr = htole32(MSK_ADDR_LO(segs[0].ds_addr)); 942 rx_le->msk_control = 943 htole32(segs[0].ds_len | OP_PACKET | HW_OWNER); 944 945 return (0); 946 } 947 948 static int 949 msk_jumbo_newbuf(struct msk_if_softc *sc_if, int idx) 950 { 951 struct msk_rx_desc *rx_le; 952 struct msk_rxdesc *rxd; 953 struct mbuf *m; 954 bus_dma_segment_t segs[1]; 955 bus_dmamap_t map; 956 int nsegs; 957 958 m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES); 959 if (m == NULL) 960 return (ENOBUFS); 961 if ((m->m_flags & M_EXT) == 0) { 962 m_freem(m); 963 return (ENOBUFS); 964 } 965 m->m_len = m->m_pkthdr.len = MJUM9BYTES; 966 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) == 0) 967 m_adj(m, ETHER_ALIGN); 968 #ifndef __NO_STRICT_ALIGNMENT 969 else 970 m_adj(m, MSK_RX_BUF_ALIGN); 971 #endif 972 973 if (bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_jumbo_rx_tag, 974 sc_if->msk_cdata.msk_jumbo_rx_sparemap, m, segs, &nsegs, 975 BUS_DMA_NOWAIT) != 0) { 976 m_freem(m); 977 return (ENOBUFS); 978 } 979 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 980 981 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[idx]; 982 #ifdef MSK_64BIT_DMA 983 rx_le = rxd->rx_le; 984 rx_le->msk_addr = htole32(MSK_ADDR_HI(segs[0].ds_addr)); 985 rx_le->msk_control = htole32(OP_ADDR64 | HW_OWNER); 986 MSK_INC(idx, MSK_JUMBO_RX_RING_CNT); 987 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[idx]; 988 #endif 989 if (rxd->rx_m != NULL) { 990 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_tag, 991 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 992 bus_dmamap_unload(sc_if->msk_cdata.msk_jumbo_rx_tag, 993 rxd->rx_dmamap); 994 rxd->rx_m = NULL; 995 } 996 map = rxd->rx_dmamap; 997 rxd->rx_dmamap = sc_if->msk_cdata.msk_jumbo_rx_sparemap; 998 sc_if->msk_cdata.msk_jumbo_rx_sparemap = map; 999 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_tag, rxd->rx_dmamap, 1000 BUS_DMASYNC_PREREAD); 1001 rxd->rx_m = m; 1002 rx_le = rxd->rx_le; 1003 rx_le->msk_addr = htole32(MSK_ADDR_LO(segs[0].ds_addr)); 1004 rx_le->msk_control = 1005 htole32(segs[0].ds_len | OP_PACKET | HW_OWNER); 1006 1007 return (0); 1008 } 1009 1010 /* 1011 * Set media options. 1012 */ 1013 static int 1014 msk_mediachange(struct ifnet *ifp) 1015 { 1016 struct msk_if_softc *sc_if; 1017 struct mii_data *mii; 1018 int error; 1019 1020 sc_if = ifp->if_softc; 1021 1022 MSK_IF_LOCK(sc_if); 1023 mii = device_get_softc(sc_if->msk_miibus); 1024 error = mii_mediachg(mii); 1025 MSK_IF_UNLOCK(sc_if); 1026 1027 return (error); 1028 } 1029 1030 /* 1031 * Report current media status. 1032 */ 1033 static void 1034 msk_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1035 { 1036 struct msk_if_softc *sc_if; 1037 struct mii_data *mii; 1038 1039 sc_if = ifp->if_softc; 1040 MSK_IF_LOCK(sc_if); 1041 if ((ifp->if_flags & IFF_UP) == 0) { 1042 MSK_IF_UNLOCK(sc_if); 1043 return; 1044 } 1045 mii = device_get_softc(sc_if->msk_miibus); 1046 1047 mii_pollstat(mii); 1048 ifmr->ifm_active = mii->mii_media_active; 1049 ifmr->ifm_status = mii->mii_media_status; 1050 MSK_IF_UNLOCK(sc_if); 1051 } 1052 1053 static int 1054 msk_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1055 { 1056 struct msk_if_softc *sc_if; 1057 struct ifreq *ifr; 1058 struct mii_data *mii; 1059 int error, mask, reinit; 1060 1061 sc_if = ifp->if_softc; 1062 ifr = (struct ifreq *)data; 1063 error = 0; 1064 1065 switch(command) { 1066 case SIOCSIFMTU: 1067 MSK_IF_LOCK(sc_if); 1068 if (ifr->ifr_mtu > MSK_JUMBO_MTU || ifr->ifr_mtu < ETHERMIN) 1069 error = EINVAL; 1070 else if (ifp->if_mtu != ifr->ifr_mtu) { 1071 if (ifr->ifr_mtu > ETHERMTU) { 1072 if ((sc_if->msk_flags & MSK_FLAG_JUMBO) == 0) { 1073 error = EINVAL; 1074 MSK_IF_UNLOCK(sc_if); 1075 break; 1076 } 1077 if ((sc_if->msk_flags & 1078 MSK_FLAG_JUMBO_NOCSUM) != 0) { 1079 ifp->if_hwassist &= 1080 ~(MSK_CSUM_FEATURES | CSUM_TSO); 1081 ifp->if_capenable &= 1082 ~(IFCAP_TSO4 | IFCAP_TXCSUM); 1083 VLAN_CAPABILITIES(ifp); 1084 } 1085 } 1086 ifp->if_mtu = ifr->ifr_mtu; 1087 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 1088 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1089 msk_init_locked(sc_if); 1090 } 1091 } 1092 MSK_IF_UNLOCK(sc_if); 1093 break; 1094 case SIOCSIFFLAGS: 1095 MSK_IF_LOCK(sc_if); 1096 if ((ifp->if_flags & IFF_UP) != 0) { 1097 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 && 1098 ((ifp->if_flags ^ sc_if->msk_if_flags) & 1099 (IFF_PROMISC | IFF_ALLMULTI)) != 0) 1100 msk_rxfilter(sc_if); 1101 else if ((sc_if->msk_flags & MSK_FLAG_DETACH) == 0) 1102 msk_init_locked(sc_if); 1103 } else if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1104 msk_stop(sc_if); 1105 sc_if->msk_if_flags = ifp->if_flags; 1106 MSK_IF_UNLOCK(sc_if); 1107 break; 1108 case SIOCADDMULTI: 1109 case SIOCDELMULTI: 1110 MSK_IF_LOCK(sc_if); 1111 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1112 msk_rxfilter(sc_if); 1113 MSK_IF_UNLOCK(sc_if); 1114 break; 1115 case SIOCGIFMEDIA: 1116 case SIOCSIFMEDIA: 1117 mii = device_get_softc(sc_if->msk_miibus); 1118 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1119 break; 1120 case SIOCSIFCAP: 1121 reinit = 0; 1122 MSK_IF_LOCK(sc_if); 1123 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 1124 if ((mask & IFCAP_TXCSUM) != 0 && 1125 (IFCAP_TXCSUM & ifp->if_capabilities) != 0) { 1126 ifp->if_capenable ^= IFCAP_TXCSUM; 1127 if ((IFCAP_TXCSUM & ifp->if_capenable) != 0) 1128 ifp->if_hwassist |= MSK_CSUM_FEATURES; 1129 else 1130 ifp->if_hwassist &= ~MSK_CSUM_FEATURES; 1131 } 1132 if ((mask & IFCAP_RXCSUM) != 0 && 1133 (IFCAP_RXCSUM & ifp->if_capabilities) != 0) { 1134 ifp->if_capenable ^= IFCAP_RXCSUM; 1135 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0) 1136 reinit = 1; 1137 } 1138 if ((mask & IFCAP_VLAN_HWCSUM) != 0 && 1139 (IFCAP_VLAN_HWCSUM & ifp->if_capabilities) != 0) 1140 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; 1141 if ((mask & IFCAP_TSO4) != 0 && 1142 (IFCAP_TSO4 & ifp->if_capabilities) != 0) { 1143 ifp->if_capenable ^= IFCAP_TSO4; 1144 if ((IFCAP_TSO4 & ifp->if_capenable) != 0) 1145 ifp->if_hwassist |= CSUM_TSO; 1146 else 1147 ifp->if_hwassist &= ~CSUM_TSO; 1148 } 1149 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 1150 (IFCAP_VLAN_HWTSO & ifp->if_capabilities) != 0) 1151 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 1152 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 1153 (IFCAP_VLAN_HWTAGGING & ifp->if_capabilities) != 0) { 1154 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 1155 if ((IFCAP_VLAN_HWTAGGING & ifp->if_capenable) == 0) 1156 ifp->if_capenable &= 1157 ~(IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM); 1158 msk_setvlan(sc_if, ifp); 1159 } 1160 if (ifp->if_mtu > ETHERMTU && 1161 (sc_if->msk_flags & MSK_FLAG_JUMBO_NOCSUM) != 0) { 1162 ifp->if_hwassist &= ~(MSK_CSUM_FEATURES | CSUM_TSO); 1163 ifp->if_capenable &= ~(IFCAP_TSO4 | IFCAP_TXCSUM); 1164 } 1165 VLAN_CAPABILITIES(ifp); 1166 if (reinit > 0 && (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 1167 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1168 msk_init_locked(sc_if); 1169 } 1170 MSK_IF_UNLOCK(sc_if); 1171 break; 1172 default: 1173 error = ether_ioctl(ifp, command, data); 1174 break; 1175 } 1176 1177 return (error); 1178 } 1179 1180 static int 1181 mskc_probe(device_t dev) 1182 { 1183 struct msk_product *mp; 1184 uint16_t vendor, devid; 1185 int i; 1186 1187 vendor = pci_get_vendor(dev); 1188 devid = pci_get_device(dev); 1189 mp = msk_products; 1190 for (i = 0; i < sizeof(msk_products)/sizeof(msk_products[0]); 1191 i++, mp++) { 1192 if (vendor == mp->msk_vendorid && devid == mp->msk_deviceid) { 1193 device_set_desc(dev, mp->msk_name); 1194 return (BUS_PROBE_DEFAULT); 1195 } 1196 } 1197 1198 return (ENXIO); 1199 } 1200 1201 static int 1202 mskc_setup_rambuffer(struct msk_softc *sc) 1203 { 1204 int next; 1205 int i; 1206 1207 /* Get adapter SRAM size. */ 1208 sc->msk_ramsize = CSR_READ_1(sc, B2_E_0) * 4; 1209 if (bootverbose) 1210 device_printf(sc->msk_dev, 1211 "RAM buffer size : %dKB\n", sc->msk_ramsize); 1212 if (sc->msk_ramsize == 0) 1213 return (0); 1214 1215 sc->msk_pflags |= MSK_FLAG_RAMBUF; 1216 /* 1217 * Give receiver 2/3 of memory and round down to the multiple 1218 * of 1024. Tx/Rx RAM buffer size of Yukon II should be multiple 1219 * of 1024. 1220 */ 1221 sc->msk_rxqsize = rounddown((sc->msk_ramsize * 1024 * 2) / 3, 1024); 1222 sc->msk_txqsize = (sc->msk_ramsize * 1024) - sc->msk_rxqsize; 1223 for (i = 0, next = 0; i < sc->msk_num_port; i++) { 1224 sc->msk_rxqstart[i] = next; 1225 sc->msk_rxqend[i] = next + sc->msk_rxqsize - 1; 1226 next = sc->msk_rxqend[i] + 1; 1227 sc->msk_txqstart[i] = next; 1228 sc->msk_txqend[i] = next + sc->msk_txqsize - 1; 1229 next = sc->msk_txqend[i] + 1; 1230 if (bootverbose) { 1231 device_printf(sc->msk_dev, 1232 "Port %d : Rx Queue %dKB(0x%08x:0x%08x)\n", i, 1233 sc->msk_rxqsize / 1024, sc->msk_rxqstart[i], 1234 sc->msk_rxqend[i]); 1235 device_printf(sc->msk_dev, 1236 "Port %d : Tx Queue %dKB(0x%08x:0x%08x)\n", i, 1237 sc->msk_txqsize / 1024, sc->msk_txqstart[i], 1238 sc->msk_txqend[i]); 1239 } 1240 } 1241 1242 return (0); 1243 } 1244 1245 static void 1246 msk_phy_power(struct msk_softc *sc, int mode) 1247 { 1248 uint32_t our, val; 1249 int i; 1250 1251 switch (mode) { 1252 case MSK_PHY_POWERUP: 1253 /* Switch power to VCC (WA for VAUX problem). */ 1254 CSR_WRITE_1(sc, B0_POWER_CTRL, 1255 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON); 1256 /* Disable Core Clock Division, set Clock Select to 0. */ 1257 CSR_WRITE_4(sc, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS); 1258 1259 val = 0; 1260 if (sc->msk_hw_id == CHIP_ID_YUKON_XL && 1261 sc->msk_hw_rev > CHIP_REV_YU_XL_A1) { 1262 /* Enable bits are inverted. */ 1263 val = Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS | 1264 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS | 1265 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS; 1266 } 1267 /* 1268 * Enable PCI & Core Clock, enable clock gating for both Links. 1269 */ 1270 CSR_WRITE_1(sc, B2_Y2_CLK_GATE, val); 1271 1272 our = CSR_PCI_READ_4(sc, PCI_OUR_REG_1); 1273 our &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD); 1274 if (sc->msk_hw_id == CHIP_ID_YUKON_XL) { 1275 if (sc->msk_hw_rev > CHIP_REV_YU_XL_A1) { 1276 /* Deassert Low Power for 1st PHY. */ 1277 our |= PCI_Y2_PHY1_COMA; 1278 if (sc->msk_num_port > 1) 1279 our |= PCI_Y2_PHY2_COMA; 1280 } 1281 } 1282 if (sc->msk_hw_id == CHIP_ID_YUKON_EC_U || 1283 sc->msk_hw_id == CHIP_ID_YUKON_EX || 1284 sc->msk_hw_id >= CHIP_ID_YUKON_FE_P) { 1285 val = CSR_PCI_READ_4(sc, PCI_OUR_REG_4); 1286 val &= (PCI_FORCE_ASPM_REQUEST | 1287 PCI_ASPM_GPHY_LINK_DOWN | PCI_ASPM_INT_FIFO_EMPTY | 1288 PCI_ASPM_CLKRUN_REQUEST); 1289 /* Set all bits to 0 except bits 15..12. */ 1290 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_4, val); 1291 val = CSR_PCI_READ_4(sc, PCI_OUR_REG_5); 1292 val &= PCI_CTL_TIM_VMAIN_AV_MSK; 1293 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_5, val); 1294 CSR_PCI_WRITE_4(sc, PCI_CFG_REG_1, 0); 1295 CSR_WRITE_2(sc, B0_CTST, Y2_HW_WOL_ON); 1296 /* 1297 * Disable status race, workaround for 1298 * Yukon EC Ultra & Yukon EX. 1299 */ 1300 val = CSR_READ_4(sc, B2_GP_IO); 1301 val |= GLB_GPIO_STAT_RACE_DIS; 1302 CSR_WRITE_4(sc, B2_GP_IO, val); 1303 CSR_READ_4(sc, B2_GP_IO); 1304 } 1305 /* Release PHY from PowerDown/COMA mode. */ 1306 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_1, our); 1307 1308 for (i = 0; i < sc->msk_num_port; i++) { 1309 CSR_WRITE_2(sc, MR_ADDR(i, GMAC_LINK_CTRL), 1310 GMLC_RST_SET); 1311 CSR_WRITE_2(sc, MR_ADDR(i, GMAC_LINK_CTRL), 1312 GMLC_RST_CLR); 1313 } 1314 break; 1315 case MSK_PHY_POWERDOWN: 1316 val = CSR_PCI_READ_4(sc, PCI_OUR_REG_1); 1317 val |= PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD; 1318 if (sc->msk_hw_id == CHIP_ID_YUKON_XL && 1319 sc->msk_hw_rev > CHIP_REV_YU_XL_A1) { 1320 val &= ~PCI_Y2_PHY1_COMA; 1321 if (sc->msk_num_port > 1) 1322 val &= ~PCI_Y2_PHY2_COMA; 1323 } 1324 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_1, val); 1325 1326 val = Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS | 1327 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS | 1328 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS; 1329 if (sc->msk_hw_id == CHIP_ID_YUKON_XL && 1330 sc->msk_hw_rev > CHIP_REV_YU_XL_A1) { 1331 /* Enable bits are inverted. */ 1332 val = 0; 1333 } 1334 /* 1335 * Disable PCI & Core Clock, disable clock gating for 1336 * both Links. 1337 */ 1338 CSR_WRITE_1(sc, B2_Y2_CLK_GATE, val); 1339 CSR_WRITE_1(sc, B0_POWER_CTRL, 1340 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_ON | PC_VCC_OFF); 1341 break; 1342 default: 1343 break; 1344 } 1345 } 1346 1347 static void 1348 mskc_reset(struct msk_softc *sc) 1349 { 1350 bus_addr_t addr; 1351 uint16_t status; 1352 uint32_t val; 1353 int i, initram; 1354 1355 /* Disable ASF. */ 1356 if (sc->msk_hw_id >= CHIP_ID_YUKON_XL && 1357 sc->msk_hw_id <= CHIP_ID_YUKON_SUPR) { 1358 if (sc->msk_hw_id == CHIP_ID_YUKON_EX || 1359 sc->msk_hw_id == CHIP_ID_YUKON_SUPR) { 1360 CSR_WRITE_4(sc, B28_Y2_CPU_WDOG, 0); 1361 status = CSR_READ_2(sc, B28_Y2_ASF_HCU_CCSR); 1362 /* Clear AHB bridge & microcontroller reset. */ 1363 status &= ~(Y2_ASF_HCU_CCSR_AHB_RST | 1364 Y2_ASF_HCU_CCSR_CPU_RST_MODE); 1365 /* Clear ASF microcontroller state. */ 1366 status &= ~Y2_ASF_HCU_CCSR_UC_STATE_MSK; 1367 status &= ~Y2_ASF_HCU_CCSR_CPU_CLK_DIVIDE_MSK; 1368 CSR_WRITE_2(sc, B28_Y2_ASF_HCU_CCSR, status); 1369 CSR_WRITE_4(sc, B28_Y2_CPU_WDOG, 0); 1370 } else 1371 CSR_WRITE_1(sc, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET); 1372 CSR_WRITE_2(sc, B0_CTST, Y2_ASF_DISABLE); 1373 /* 1374 * Since we disabled ASF, S/W reset is required for 1375 * Power Management. 1376 */ 1377 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); 1378 CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR); 1379 } 1380 1381 /* Clear all error bits in the PCI status register. */ 1382 status = pci_read_config(sc->msk_dev, PCIR_STATUS, 2); 1383 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON); 1384 1385 pci_write_config(sc->msk_dev, PCIR_STATUS, status | 1386 PCIM_STATUS_PERR | PCIM_STATUS_SERR | PCIM_STATUS_RMABORT | 1387 PCIM_STATUS_RTABORT | PCIM_STATUS_MDPERR, 2); 1388 CSR_WRITE_2(sc, B0_CTST, CS_MRST_CLR); 1389 1390 switch (sc->msk_bustype) { 1391 case MSK_PEX_BUS: 1392 /* Clear all PEX errors. */ 1393 CSR_PCI_WRITE_4(sc, PEX_UNC_ERR_STAT, 0xffffffff); 1394 val = CSR_PCI_READ_4(sc, PEX_UNC_ERR_STAT); 1395 if ((val & PEX_RX_OV) != 0) { 1396 sc->msk_intrmask &= ~Y2_IS_HW_ERR; 1397 sc->msk_intrhwemask &= ~Y2_IS_PCI_EXP; 1398 } 1399 break; 1400 case MSK_PCI_BUS: 1401 case MSK_PCIX_BUS: 1402 /* Set Cache Line Size to 2(8bytes) if configured to 0. */ 1403 val = pci_read_config(sc->msk_dev, PCIR_CACHELNSZ, 1); 1404 if (val == 0) 1405 pci_write_config(sc->msk_dev, PCIR_CACHELNSZ, 2, 1); 1406 if (sc->msk_bustype == MSK_PCIX_BUS) { 1407 /* Set Cache Line Size opt. */ 1408 val = pci_read_config(sc->msk_dev, PCI_OUR_REG_1, 4); 1409 val |= PCI_CLS_OPT; 1410 pci_write_config(sc->msk_dev, PCI_OUR_REG_1, val, 4); 1411 } 1412 break; 1413 } 1414 /* Set PHY power state. */ 1415 msk_phy_power(sc, MSK_PHY_POWERUP); 1416 1417 /* Reset GPHY/GMAC Control */ 1418 for (i = 0; i < sc->msk_num_port; i++) { 1419 /* GPHY Control reset. */ 1420 CSR_WRITE_1(sc, MR_ADDR(i, GPHY_CTRL), GPC_RST_SET); 1421 CSR_WRITE_1(sc, MR_ADDR(i, GPHY_CTRL), GPC_RST_CLR); 1422 /* GMAC Control reset. */ 1423 CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), GMC_RST_SET); 1424 CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), GMC_RST_CLR); 1425 CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), GMC_F_LOOPB_OFF); 1426 if (sc->msk_hw_id == CHIP_ID_YUKON_EX || 1427 sc->msk_hw_id == CHIP_ID_YUKON_SUPR) 1428 CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), 1429 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON | 1430 GMC_BYP_RETR_ON); 1431 } 1432 1433 if (sc->msk_hw_id == CHIP_ID_YUKON_SUPR && 1434 sc->msk_hw_rev > CHIP_REV_YU_SU_B0) 1435 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_3, PCI_CLK_MACSEC_DIS); 1436 if (sc->msk_hw_id == CHIP_ID_YUKON_OPT && sc->msk_hw_rev == 0) { 1437 /* Disable PCIe PHY powerdown(reg 0x80, bit7). */ 1438 CSR_WRITE_4(sc, Y2_PEX_PHY_DATA, (0x0080 << 16) | 0x0080); 1439 } 1440 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 1441 1442 /* LED On. */ 1443 CSR_WRITE_2(sc, B0_CTST, Y2_LED_STAT_ON); 1444 1445 /* Clear TWSI IRQ. */ 1446 CSR_WRITE_4(sc, B2_I2C_IRQ, I2C_CLR_IRQ); 1447 1448 /* Turn off hardware timer. */ 1449 CSR_WRITE_1(sc, B2_TI_CTRL, TIM_STOP); 1450 CSR_WRITE_1(sc, B2_TI_CTRL, TIM_CLR_IRQ); 1451 1452 /* Turn off descriptor polling. */ 1453 CSR_WRITE_1(sc, B28_DPT_CTRL, DPT_STOP); 1454 1455 /* Turn off time stamps. */ 1456 CSR_WRITE_1(sc, GMAC_TI_ST_CTRL, GMT_ST_STOP); 1457 CSR_WRITE_1(sc, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ); 1458 1459 initram = 0; 1460 if (sc->msk_hw_id == CHIP_ID_YUKON_XL || 1461 sc->msk_hw_id == CHIP_ID_YUKON_EC || 1462 sc->msk_hw_id == CHIP_ID_YUKON_FE) 1463 initram++; 1464 1465 /* Configure timeout values. */ 1466 for (i = 0; initram > 0 && i < sc->msk_num_port; i++) { 1467 CSR_WRITE_2(sc, SELECT_RAM_BUFFER(i, B3_RI_CTRL), RI_RST_SET); 1468 CSR_WRITE_2(sc, SELECT_RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR); 1469 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_R1), 1470 MSK_RI_TO_53); 1471 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XA1), 1472 MSK_RI_TO_53); 1473 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XS1), 1474 MSK_RI_TO_53); 1475 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_R1), 1476 MSK_RI_TO_53); 1477 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XA1), 1478 MSK_RI_TO_53); 1479 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XS1), 1480 MSK_RI_TO_53); 1481 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_R2), 1482 MSK_RI_TO_53); 1483 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XA2), 1484 MSK_RI_TO_53); 1485 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XS2), 1486 MSK_RI_TO_53); 1487 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_R2), 1488 MSK_RI_TO_53); 1489 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XA2), 1490 MSK_RI_TO_53); 1491 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XS2), 1492 MSK_RI_TO_53); 1493 } 1494 1495 /* Disable all interrupts. */ 1496 CSR_WRITE_4(sc, B0_HWE_IMSK, 0); 1497 CSR_READ_4(sc, B0_HWE_IMSK); 1498 CSR_WRITE_4(sc, B0_IMSK, 0); 1499 CSR_READ_4(sc, B0_IMSK); 1500 1501 /* 1502 * On dual port PCI-X card, there is an problem where status 1503 * can be received out of order due to split transactions. 1504 */ 1505 if (sc->msk_pcixcap != 0 && sc->msk_num_port > 1) { 1506 uint16_t pcix_cmd; 1507 1508 pcix_cmd = pci_read_config(sc->msk_dev, 1509 sc->msk_pcixcap + PCIXR_COMMAND, 2); 1510 /* Clear Max Outstanding Split Transactions. */ 1511 pcix_cmd &= ~PCIXM_COMMAND_MAX_SPLITS; 1512 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON); 1513 pci_write_config(sc->msk_dev, 1514 sc->msk_pcixcap + PCIXR_COMMAND, pcix_cmd, 2); 1515 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 1516 } 1517 if (sc->msk_expcap != 0) { 1518 /* Change Max. Read Request Size to 2048 bytes. */ 1519 if (pci_get_max_read_req(sc->msk_dev) == 512) 1520 pci_set_max_read_req(sc->msk_dev, 2048); 1521 } 1522 1523 /* Clear status list. */ 1524 bzero(sc->msk_stat_ring, 1525 sizeof(struct msk_stat_desc) * sc->msk_stat_count); 1526 sc->msk_stat_cons = 0; 1527 bus_dmamap_sync(sc->msk_stat_tag, sc->msk_stat_map, 1528 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1529 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_RST_SET); 1530 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_RST_CLR); 1531 /* Set the status list base address. */ 1532 addr = sc->msk_stat_ring_paddr; 1533 CSR_WRITE_4(sc, STAT_LIST_ADDR_LO, MSK_ADDR_LO(addr)); 1534 CSR_WRITE_4(sc, STAT_LIST_ADDR_HI, MSK_ADDR_HI(addr)); 1535 /* Set the status list last index. */ 1536 CSR_WRITE_2(sc, STAT_LAST_IDX, sc->msk_stat_count - 1); 1537 if (sc->msk_hw_id == CHIP_ID_YUKON_EC && 1538 sc->msk_hw_rev == CHIP_REV_YU_EC_A1) { 1539 /* WA for dev. #4.3 */ 1540 CSR_WRITE_2(sc, STAT_TX_IDX_TH, ST_TXTH_IDX_MASK); 1541 /* WA for dev. #4.18 */ 1542 CSR_WRITE_1(sc, STAT_FIFO_WM, 0x21); 1543 CSR_WRITE_1(sc, STAT_FIFO_ISR_WM, 0x07); 1544 } else { 1545 CSR_WRITE_2(sc, STAT_TX_IDX_TH, 0x0a); 1546 CSR_WRITE_1(sc, STAT_FIFO_WM, 0x10); 1547 if (sc->msk_hw_id == CHIP_ID_YUKON_XL && 1548 sc->msk_hw_rev == CHIP_REV_YU_XL_A0) 1549 CSR_WRITE_1(sc, STAT_FIFO_ISR_WM, 0x04); 1550 else 1551 CSR_WRITE_1(sc, STAT_FIFO_ISR_WM, 0x10); 1552 CSR_WRITE_4(sc, STAT_ISR_TIMER_INI, 0x0190); 1553 } 1554 /* 1555 * Use default value for STAT_ISR_TIMER_INI, STAT_LEV_TIMER_INI. 1556 */ 1557 CSR_WRITE_4(sc, STAT_TX_TIMER_INI, MSK_USECS(sc, 1000)); 1558 1559 /* Enable status unit. */ 1560 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_OP_ON); 1561 1562 CSR_WRITE_1(sc, STAT_TX_TIMER_CTRL, TIM_START); 1563 CSR_WRITE_1(sc, STAT_LEV_TIMER_CTRL, TIM_START); 1564 CSR_WRITE_1(sc, STAT_ISR_TIMER_CTRL, TIM_START); 1565 } 1566 1567 static int 1568 msk_probe(device_t dev) 1569 { 1570 struct msk_softc *sc; 1571 char desc[100]; 1572 1573 sc = device_get_softc(device_get_parent(dev)); 1574 /* 1575 * Not much to do here. We always know there will be 1576 * at least one GMAC present, and if there are two, 1577 * mskc_attach() will create a second device instance 1578 * for us. 1579 */ 1580 snprintf(desc, sizeof(desc), 1581 "Marvell Technology Group Ltd. %s Id 0x%02x Rev 0x%02x", 1582 model_name[sc->msk_hw_id - CHIP_ID_YUKON_XL], sc->msk_hw_id, 1583 sc->msk_hw_rev); 1584 device_set_desc_copy(dev, desc); 1585 1586 return (BUS_PROBE_DEFAULT); 1587 } 1588 1589 static int 1590 msk_attach(device_t dev) 1591 { 1592 struct msk_softc *sc; 1593 struct msk_if_softc *sc_if; 1594 struct ifnet *ifp; 1595 struct msk_mii_data *mmd; 1596 int i, port, error; 1597 uint8_t eaddr[6]; 1598 1599 if (dev == NULL) 1600 return (EINVAL); 1601 1602 error = 0; 1603 sc_if = device_get_softc(dev); 1604 sc = device_get_softc(device_get_parent(dev)); 1605 mmd = device_get_ivars(dev); 1606 port = mmd->port; 1607 1608 sc_if->msk_if_dev = dev; 1609 sc_if->msk_port = port; 1610 sc_if->msk_softc = sc; 1611 sc_if->msk_flags = sc->msk_pflags; 1612 sc->msk_if[port] = sc_if; 1613 /* Setup Tx/Rx queue register offsets. */ 1614 if (port == MSK_PORT_A) { 1615 sc_if->msk_txq = Q_XA1; 1616 sc_if->msk_txsq = Q_XS1; 1617 sc_if->msk_rxq = Q_R1; 1618 } else { 1619 sc_if->msk_txq = Q_XA2; 1620 sc_if->msk_txsq = Q_XS2; 1621 sc_if->msk_rxq = Q_R2; 1622 } 1623 1624 callout_init_mtx(&sc_if->msk_tick_ch, &sc_if->msk_softc->msk_mtx, 0); 1625 msk_sysctl_node(sc_if); 1626 1627 if ((error = msk_txrx_dma_alloc(sc_if) != 0)) 1628 goto fail; 1629 msk_rx_dma_jalloc(sc_if); 1630 1631 ifp = sc_if->msk_ifp = if_alloc(IFT_ETHER); 1632 if (ifp == NULL) { 1633 device_printf(sc_if->msk_if_dev, "can not if_alloc()\n"); 1634 error = ENOSPC; 1635 goto fail; 1636 } 1637 ifp->if_softc = sc_if; 1638 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1639 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1640 ifp->if_capabilities = IFCAP_TXCSUM | IFCAP_TSO4; 1641 /* 1642 * Enable Rx checksum offloading if controller supports 1643 * new descriptor formant and controller is not Yukon XL. 1644 */ 1645 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0 && 1646 sc->msk_hw_id != CHIP_ID_YUKON_XL) 1647 ifp->if_capabilities |= IFCAP_RXCSUM; 1648 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) != 0 && 1649 (sc_if->msk_flags & MSK_FLAG_NORX_CSUM) == 0) 1650 ifp->if_capabilities |= IFCAP_RXCSUM; 1651 ifp->if_hwassist = MSK_CSUM_FEATURES | CSUM_TSO; 1652 ifp->if_capenable = ifp->if_capabilities; 1653 ifp->if_ioctl = msk_ioctl; 1654 ifp->if_start = msk_start; 1655 ifp->if_init = msk_init; 1656 IFQ_SET_MAXLEN(&ifp->if_snd, MSK_TX_RING_CNT - 1); 1657 ifp->if_snd.ifq_drv_maxlen = MSK_TX_RING_CNT - 1; 1658 IFQ_SET_READY(&ifp->if_snd); 1659 /* 1660 * Get station address for this interface. Note that 1661 * dual port cards actually come with three station 1662 * addresses: one for each port, plus an extra. The 1663 * extra one is used by the SysKonnect driver software 1664 * as a 'virtual' station address for when both ports 1665 * are operating in failover mode. Currently we don't 1666 * use this extra address. 1667 */ 1668 MSK_IF_LOCK(sc_if); 1669 for (i = 0; i < ETHER_ADDR_LEN; i++) 1670 eaddr[i] = CSR_READ_1(sc, B2_MAC_1 + (port * 8) + i); 1671 1672 /* 1673 * Call MI attach routine. Can't hold locks when calling into ether_*. 1674 */ 1675 MSK_IF_UNLOCK(sc_if); 1676 ether_ifattach(ifp, eaddr); 1677 MSK_IF_LOCK(sc_if); 1678 1679 /* VLAN capability setup */ 1680 ifp->if_capabilities |= IFCAP_VLAN_MTU; 1681 if ((sc_if->msk_flags & MSK_FLAG_NOHWVLAN) == 0) { 1682 /* 1683 * Due to Tx checksum offload hardware bugs, msk(4) manually 1684 * computes checksum for short frames. For VLAN tagged frames 1685 * this workaround does not work so disable checksum offload 1686 * for VLAN interface. 1687 */ 1688 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWTSO; 1689 /* 1690 * Enable Rx checksum offloading for VLAN tagged frames 1691 * if controller support new descriptor format. 1692 */ 1693 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) != 0 && 1694 (sc_if->msk_flags & MSK_FLAG_NORX_CSUM) == 0) 1695 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM; 1696 } 1697 ifp->if_capenable = ifp->if_capabilities; 1698 1699 /* 1700 * Tell the upper layer(s) we support long frames. 1701 * Must appear after the call to ether_ifattach() because 1702 * ether_ifattach() sets ifi_hdrlen to the default value. 1703 */ 1704 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1705 1706 /* 1707 * Do miibus setup. 1708 */ 1709 MSK_IF_UNLOCK(sc_if); 1710 error = mii_attach(dev, &sc_if->msk_miibus, ifp, msk_mediachange, 1711 msk_mediastatus, BMSR_DEFCAPMASK, PHY_ADDR_MARV, MII_OFFSET_ANY, 1712 mmd->mii_flags); 1713 if (error != 0) { 1714 device_printf(sc_if->msk_if_dev, "attaching PHYs failed\n"); 1715 ether_ifdetach(ifp); 1716 error = ENXIO; 1717 goto fail; 1718 } 1719 1720 fail: 1721 if (error != 0) { 1722 /* Access should be ok even though lock has been dropped */ 1723 sc->msk_if[port] = NULL; 1724 msk_detach(dev); 1725 } 1726 1727 return (error); 1728 } 1729 1730 /* 1731 * Attach the interface. Allocate softc structures, do ifmedia 1732 * setup and ethernet/BPF attach. 1733 */ 1734 static int 1735 mskc_attach(device_t dev) 1736 { 1737 struct msk_softc *sc; 1738 struct msk_mii_data *mmd; 1739 int error, msic, msir, reg; 1740 1741 sc = device_get_softc(dev); 1742 sc->msk_dev = dev; 1743 mtx_init(&sc->msk_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1744 MTX_DEF); 1745 1746 /* 1747 * Map control/status registers. 1748 */ 1749 pci_enable_busmaster(dev); 1750 1751 /* Allocate I/O resource */ 1752 #ifdef MSK_USEIOSPACE 1753 sc->msk_res_spec = msk_res_spec_io; 1754 #else 1755 sc->msk_res_spec = msk_res_spec_mem; 1756 #endif 1757 sc->msk_irq_spec = msk_irq_spec_legacy; 1758 error = bus_alloc_resources(dev, sc->msk_res_spec, sc->msk_res); 1759 if (error) { 1760 if (sc->msk_res_spec == msk_res_spec_mem) 1761 sc->msk_res_spec = msk_res_spec_io; 1762 else 1763 sc->msk_res_spec = msk_res_spec_mem; 1764 error = bus_alloc_resources(dev, sc->msk_res_spec, sc->msk_res); 1765 if (error) { 1766 device_printf(dev, "couldn't allocate %s resources\n", 1767 sc->msk_res_spec == msk_res_spec_mem ? "memory" : 1768 "I/O"); 1769 mtx_destroy(&sc->msk_mtx); 1770 return (ENXIO); 1771 } 1772 } 1773 1774 /* Enable all clocks before accessing any registers. */ 1775 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_3, 0); 1776 1777 CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR); 1778 sc->msk_hw_id = CSR_READ_1(sc, B2_CHIP_ID); 1779 sc->msk_hw_rev = (CSR_READ_1(sc, B2_MAC_CFG) >> 4) & 0x0f; 1780 /* Bail out if chip is not recognized. */ 1781 if (sc->msk_hw_id < CHIP_ID_YUKON_XL || 1782 sc->msk_hw_id > CHIP_ID_YUKON_OPT || 1783 sc->msk_hw_id == CHIP_ID_YUKON_UNKNOWN) { 1784 device_printf(dev, "unknown device: id=0x%02x, rev=0x%02x\n", 1785 sc->msk_hw_id, sc->msk_hw_rev); 1786 mtx_destroy(&sc->msk_mtx); 1787 return (ENXIO); 1788 } 1789 1790 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 1791 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 1792 OID_AUTO, "process_limit", CTLTYPE_INT | CTLFLAG_RW, 1793 &sc->msk_process_limit, 0, sysctl_hw_msk_proc_limit, "I", 1794 "max number of Rx events to process"); 1795 1796 sc->msk_process_limit = MSK_PROC_DEFAULT; 1797 error = resource_int_value(device_get_name(dev), device_get_unit(dev), 1798 "process_limit", &sc->msk_process_limit); 1799 if (error == 0) { 1800 if (sc->msk_process_limit < MSK_PROC_MIN || 1801 sc->msk_process_limit > MSK_PROC_MAX) { 1802 device_printf(dev, "process_limit value out of range; " 1803 "using default: %d\n", MSK_PROC_DEFAULT); 1804 sc->msk_process_limit = MSK_PROC_DEFAULT; 1805 } 1806 } 1807 1808 sc->msk_int_holdoff = MSK_INT_HOLDOFF_DEFAULT; 1809 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 1810 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 1811 "int_holdoff", CTLFLAG_RW, &sc->msk_int_holdoff, 0, 1812 "Maximum number of time to delay interrupts"); 1813 resource_int_value(device_get_name(dev), device_get_unit(dev), 1814 "int_holdoff", &sc->msk_int_holdoff); 1815 1816 sc->msk_pmd = CSR_READ_1(sc, B2_PMD_TYP); 1817 /* Check number of MACs. */ 1818 sc->msk_num_port = 1; 1819 if ((CSR_READ_1(sc, B2_Y2_HW_RES) & CFG_DUAL_MAC_MSK) == 1820 CFG_DUAL_MAC_MSK) { 1821 if (!(CSR_READ_1(sc, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC)) 1822 sc->msk_num_port++; 1823 } 1824 1825 /* Check bus type. */ 1826 if (pci_find_cap(sc->msk_dev, PCIY_EXPRESS, ®) == 0) { 1827 sc->msk_bustype = MSK_PEX_BUS; 1828 sc->msk_expcap = reg; 1829 } else if (pci_find_cap(sc->msk_dev, PCIY_PCIX, ®) == 0) { 1830 sc->msk_bustype = MSK_PCIX_BUS; 1831 sc->msk_pcixcap = reg; 1832 } else 1833 sc->msk_bustype = MSK_PCI_BUS; 1834 1835 switch (sc->msk_hw_id) { 1836 case CHIP_ID_YUKON_EC: 1837 sc->msk_clock = 125; /* 125 MHz */ 1838 sc->msk_pflags |= MSK_FLAG_JUMBO; 1839 break; 1840 case CHIP_ID_YUKON_EC_U: 1841 sc->msk_clock = 125; /* 125 MHz */ 1842 sc->msk_pflags |= MSK_FLAG_JUMBO | MSK_FLAG_JUMBO_NOCSUM; 1843 break; 1844 case CHIP_ID_YUKON_EX: 1845 sc->msk_clock = 125; /* 125 MHz */ 1846 sc->msk_pflags |= MSK_FLAG_JUMBO | MSK_FLAG_DESCV2 | 1847 MSK_FLAG_AUTOTX_CSUM; 1848 /* 1849 * Yukon Extreme seems to have silicon bug for 1850 * automatic Tx checksum calculation capability. 1851 */ 1852 if (sc->msk_hw_rev == CHIP_REV_YU_EX_B0) 1853 sc->msk_pflags &= ~MSK_FLAG_AUTOTX_CSUM; 1854 /* 1855 * Yukon Extreme A0 could not use store-and-forward 1856 * for jumbo frames, so disable Tx checksum 1857 * offloading for jumbo frames. 1858 */ 1859 if (sc->msk_hw_rev == CHIP_REV_YU_EX_A0) 1860 sc->msk_pflags |= MSK_FLAG_JUMBO_NOCSUM; 1861 break; 1862 case CHIP_ID_YUKON_FE: 1863 sc->msk_clock = 100; /* 100 MHz */ 1864 sc->msk_pflags |= MSK_FLAG_FASTETHER; 1865 break; 1866 case CHIP_ID_YUKON_FE_P: 1867 sc->msk_clock = 50; /* 50 MHz */ 1868 sc->msk_pflags |= MSK_FLAG_FASTETHER | MSK_FLAG_DESCV2 | 1869 MSK_FLAG_AUTOTX_CSUM; 1870 if (sc->msk_hw_rev == CHIP_REV_YU_FE_P_A0) { 1871 /* 1872 * XXX 1873 * FE+ A0 has status LE writeback bug so msk(4) 1874 * does not rely on status word of received frame 1875 * in msk_rxeof() which in turn disables all 1876 * hardware assistance bits reported by the status 1877 * word as well as validity of the received frame. 1878 * Just pass received frames to upper stack with 1879 * minimal test and let upper stack handle them. 1880 */ 1881 sc->msk_pflags |= MSK_FLAG_NOHWVLAN | 1882 MSK_FLAG_NORXCHK | MSK_FLAG_NORX_CSUM; 1883 } 1884 break; 1885 case CHIP_ID_YUKON_XL: 1886 sc->msk_clock = 156; /* 156 MHz */ 1887 sc->msk_pflags |= MSK_FLAG_JUMBO; 1888 break; 1889 case CHIP_ID_YUKON_SUPR: 1890 sc->msk_clock = 125; /* 125 MHz */ 1891 sc->msk_pflags |= MSK_FLAG_JUMBO | MSK_FLAG_DESCV2 | 1892 MSK_FLAG_AUTOTX_CSUM; 1893 break; 1894 case CHIP_ID_YUKON_UL_2: 1895 sc->msk_clock = 125; /* 125 MHz */ 1896 sc->msk_pflags |= MSK_FLAG_JUMBO; 1897 break; 1898 case CHIP_ID_YUKON_OPT: 1899 sc->msk_clock = 125; /* 125 MHz */ 1900 sc->msk_pflags |= MSK_FLAG_JUMBO | MSK_FLAG_DESCV2; 1901 break; 1902 default: 1903 sc->msk_clock = 156; /* 156 MHz */ 1904 break; 1905 } 1906 1907 /* Allocate IRQ resources. */ 1908 msic = pci_msi_count(dev); 1909 if (bootverbose) 1910 device_printf(dev, "MSI count : %d\n", msic); 1911 if (legacy_intr != 0) 1912 msi_disable = 1; 1913 if (msi_disable == 0 && msic > 0) { 1914 msir = 1; 1915 if (pci_alloc_msi(dev, &msir) == 0) { 1916 if (msir == 1) { 1917 sc->msk_pflags |= MSK_FLAG_MSI; 1918 sc->msk_irq_spec = msk_irq_spec_msi; 1919 } else 1920 pci_release_msi(dev); 1921 } 1922 } 1923 1924 error = bus_alloc_resources(dev, sc->msk_irq_spec, sc->msk_irq); 1925 if (error) { 1926 device_printf(dev, "couldn't allocate IRQ resources\n"); 1927 goto fail; 1928 } 1929 1930 if ((error = msk_status_dma_alloc(sc)) != 0) 1931 goto fail; 1932 1933 /* Set base interrupt mask. */ 1934 sc->msk_intrmask = Y2_IS_HW_ERR | Y2_IS_STAT_BMU; 1935 sc->msk_intrhwemask = Y2_IS_TIST_OV | Y2_IS_MST_ERR | 1936 Y2_IS_IRQ_STAT | Y2_IS_PCI_EXP | Y2_IS_PCI_NEXP; 1937 1938 /* Reset the adapter. */ 1939 mskc_reset(sc); 1940 1941 if ((error = mskc_setup_rambuffer(sc)) != 0) 1942 goto fail; 1943 1944 sc->msk_devs[MSK_PORT_A] = device_add_child(dev, "msk", -1); 1945 if (sc->msk_devs[MSK_PORT_A] == NULL) { 1946 device_printf(dev, "failed to add child for PORT_A\n"); 1947 error = ENXIO; 1948 goto fail; 1949 } 1950 mmd = malloc(sizeof(struct msk_mii_data), M_DEVBUF, M_WAITOK | M_ZERO); 1951 if (mmd == NULL) { 1952 device_printf(dev, "failed to allocate memory for " 1953 "ivars of PORT_A\n"); 1954 error = ENXIO; 1955 goto fail; 1956 } 1957 mmd->port = MSK_PORT_A; 1958 mmd->pmd = sc->msk_pmd; 1959 mmd->mii_flags |= MIIF_DOPAUSE; 1960 if (sc->msk_pmd == 'L' || sc->msk_pmd == 'S') 1961 mmd->mii_flags |= MIIF_HAVEFIBER; 1962 if (sc->msk_pmd == 'P') 1963 mmd->mii_flags |= MIIF_HAVEFIBER | MIIF_MACPRIV0; 1964 device_set_ivars(sc->msk_devs[MSK_PORT_A], mmd); 1965 1966 if (sc->msk_num_port > 1) { 1967 sc->msk_devs[MSK_PORT_B] = device_add_child(dev, "msk", -1); 1968 if (sc->msk_devs[MSK_PORT_B] == NULL) { 1969 device_printf(dev, "failed to add child for PORT_B\n"); 1970 error = ENXIO; 1971 goto fail; 1972 } 1973 mmd = malloc(sizeof(struct msk_mii_data), M_DEVBUF, M_WAITOK | 1974 M_ZERO); 1975 if (mmd == NULL) { 1976 device_printf(dev, "failed to allocate memory for " 1977 "ivars of PORT_B\n"); 1978 error = ENXIO; 1979 goto fail; 1980 } 1981 mmd->port = MSK_PORT_B; 1982 mmd->pmd = sc->msk_pmd; 1983 if (sc->msk_pmd == 'L' || sc->msk_pmd == 'S') 1984 mmd->mii_flags |= MIIF_HAVEFIBER; 1985 if (sc->msk_pmd == 'P') 1986 mmd->mii_flags |= MIIF_HAVEFIBER | MIIF_MACPRIV0; 1987 device_set_ivars(sc->msk_devs[MSK_PORT_B], mmd); 1988 } 1989 1990 error = bus_generic_attach(dev); 1991 if (error) { 1992 device_printf(dev, "failed to attach port(s)\n"); 1993 goto fail; 1994 } 1995 1996 /* Hook interrupt last to avoid having to lock softc. */ 1997 error = bus_setup_intr(dev, sc->msk_irq[0], INTR_TYPE_NET | 1998 INTR_MPSAFE, NULL, msk_intr, sc, &sc->msk_intrhand); 1999 if (error != 0) { 2000 device_printf(dev, "couldn't set up interrupt handler\n"); 2001 goto fail; 2002 } 2003 fail: 2004 if (error != 0) 2005 mskc_detach(dev); 2006 2007 return (error); 2008 } 2009 2010 /* 2011 * Shutdown hardware and free up resources. This can be called any 2012 * time after the mutex has been initialized. It is called in both 2013 * the error case in attach and the normal detach case so it needs 2014 * to be careful about only freeing resources that have actually been 2015 * allocated. 2016 */ 2017 static int 2018 msk_detach(device_t dev) 2019 { 2020 struct msk_softc *sc; 2021 struct msk_if_softc *sc_if; 2022 struct ifnet *ifp; 2023 2024 sc_if = device_get_softc(dev); 2025 KASSERT(mtx_initialized(&sc_if->msk_softc->msk_mtx), 2026 ("msk mutex not initialized in msk_detach")); 2027 MSK_IF_LOCK(sc_if); 2028 2029 ifp = sc_if->msk_ifp; 2030 if (device_is_attached(dev)) { 2031 /* XXX */ 2032 sc_if->msk_flags |= MSK_FLAG_DETACH; 2033 msk_stop(sc_if); 2034 /* Can't hold locks while calling detach. */ 2035 MSK_IF_UNLOCK(sc_if); 2036 callout_drain(&sc_if->msk_tick_ch); 2037 if (ifp) 2038 ether_ifdetach(ifp); 2039 MSK_IF_LOCK(sc_if); 2040 } 2041 2042 /* 2043 * We're generally called from mskc_detach() which is using 2044 * device_delete_child() to get to here. It's already trashed 2045 * miibus for us, so don't do it here or we'll panic. 2046 * 2047 * if (sc_if->msk_miibus != NULL) { 2048 * device_delete_child(dev, sc_if->msk_miibus); 2049 * sc_if->msk_miibus = NULL; 2050 * } 2051 */ 2052 2053 msk_rx_dma_jfree(sc_if); 2054 msk_txrx_dma_free(sc_if); 2055 bus_generic_detach(dev); 2056 2057 if (ifp) 2058 if_free(ifp); 2059 sc = sc_if->msk_softc; 2060 sc->msk_if[sc_if->msk_port] = NULL; 2061 MSK_IF_UNLOCK(sc_if); 2062 2063 return (0); 2064 } 2065 2066 static int 2067 mskc_detach(device_t dev) 2068 { 2069 struct msk_softc *sc; 2070 2071 sc = device_get_softc(dev); 2072 KASSERT(mtx_initialized(&sc->msk_mtx), ("msk mutex not initialized")); 2073 2074 if (device_is_alive(dev)) { 2075 if (sc->msk_devs[MSK_PORT_A] != NULL) { 2076 free(device_get_ivars(sc->msk_devs[MSK_PORT_A]), 2077 M_DEVBUF); 2078 device_delete_child(dev, sc->msk_devs[MSK_PORT_A]); 2079 } 2080 if (sc->msk_devs[MSK_PORT_B] != NULL) { 2081 free(device_get_ivars(sc->msk_devs[MSK_PORT_B]), 2082 M_DEVBUF); 2083 device_delete_child(dev, sc->msk_devs[MSK_PORT_B]); 2084 } 2085 bus_generic_detach(dev); 2086 } 2087 2088 /* Disable all interrupts. */ 2089 CSR_WRITE_4(sc, B0_IMSK, 0); 2090 CSR_READ_4(sc, B0_IMSK); 2091 CSR_WRITE_4(sc, B0_HWE_IMSK, 0); 2092 CSR_READ_4(sc, B0_HWE_IMSK); 2093 2094 /* LED Off. */ 2095 CSR_WRITE_2(sc, B0_CTST, Y2_LED_STAT_OFF); 2096 2097 /* Put hardware reset. */ 2098 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); 2099 2100 msk_status_dma_free(sc); 2101 2102 if (sc->msk_intrhand) { 2103 bus_teardown_intr(dev, sc->msk_irq[0], sc->msk_intrhand); 2104 sc->msk_intrhand = NULL; 2105 } 2106 bus_release_resources(dev, sc->msk_irq_spec, sc->msk_irq); 2107 if ((sc->msk_pflags & MSK_FLAG_MSI) != 0) 2108 pci_release_msi(dev); 2109 bus_release_resources(dev, sc->msk_res_spec, sc->msk_res); 2110 mtx_destroy(&sc->msk_mtx); 2111 2112 return (0); 2113 } 2114 2115 struct msk_dmamap_arg { 2116 bus_addr_t msk_busaddr; 2117 }; 2118 2119 static void 2120 msk_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 2121 { 2122 struct msk_dmamap_arg *ctx; 2123 2124 if (error != 0) 2125 return; 2126 ctx = arg; 2127 ctx->msk_busaddr = segs[0].ds_addr; 2128 } 2129 2130 /* Create status DMA region. */ 2131 static int 2132 msk_status_dma_alloc(struct msk_softc *sc) 2133 { 2134 struct msk_dmamap_arg ctx; 2135 bus_size_t stat_sz; 2136 int count, error; 2137 2138 /* 2139 * It seems controller requires number of status LE entries 2140 * is power of 2 and the maximum number of status LE entries 2141 * is 4096. For dual-port controllers, the number of status 2142 * LE entries should be large enough to hold both port's 2143 * status updates. 2144 */ 2145 count = 3 * MSK_RX_RING_CNT + MSK_TX_RING_CNT; 2146 count = imin(4096, roundup2(count, 1024)); 2147 sc->msk_stat_count = count; 2148 stat_sz = count * sizeof(struct msk_stat_desc); 2149 error = bus_dma_tag_create( 2150 bus_get_dma_tag(sc->msk_dev), /* parent */ 2151 MSK_STAT_ALIGN, 0, /* alignment, boundary */ 2152 BUS_SPACE_MAXADDR, /* lowaddr */ 2153 BUS_SPACE_MAXADDR, /* highaddr */ 2154 NULL, NULL, /* filter, filterarg */ 2155 stat_sz, /* maxsize */ 2156 1, /* nsegments */ 2157 stat_sz, /* maxsegsize */ 2158 0, /* flags */ 2159 NULL, NULL, /* lockfunc, lockarg */ 2160 &sc->msk_stat_tag); 2161 if (error != 0) { 2162 device_printf(sc->msk_dev, 2163 "failed to create status DMA tag\n"); 2164 return (error); 2165 } 2166 2167 /* Allocate DMA'able memory and load the DMA map for status ring. */ 2168 error = bus_dmamem_alloc(sc->msk_stat_tag, 2169 (void **)&sc->msk_stat_ring, BUS_DMA_WAITOK | BUS_DMA_COHERENT | 2170 BUS_DMA_ZERO, &sc->msk_stat_map); 2171 if (error != 0) { 2172 device_printf(sc->msk_dev, 2173 "failed to allocate DMA'able memory for status ring\n"); 2174 return (error); 2175 } 2176 2177 ctx.msk_busaddr = 0; 2178 error = bus_dmamap_load(sc->msk_stat_tag, sc->msk_stat_map, 2179 sc->msk_stat_ring, stat_sz, msk_dmamap_cb, &ctx, BUS_DMA_NOWAIT); 2180 if (error != 0) { 2181 device_printf(sc->msk_dev, 2182 "failed to load DMA'able memory for status ring\n"); 2183 return (error); 2184 } 2185 sc->msk_stat_ring_paddr = ctx.msk_busaddr; 2186 2187 return (0); 2188 } 2189 2190 static void 2191 msk_status_dma_free(struct msk_softc *sc) 2192 { 2193 2194 /* Destroy status block. */ 2195 if (sc->msk_stat_tag) { 2196 if (sc->msk_stat_map) { 2197 bus_dmamap_unload(sc->msk_stat_tag, sc->msk_stat_map); 2198 if (sc->msk_stat_ring) { 2199 bus_dmamem_free(sc->msk_stat_tag, 2200 sc->msk_stat_ring, sc->msk_stat_map); 2201 sc->msk_stat_ring = NULL; 2202 } 2203 sc->msk_stat_map = NULL; 2204 } 2205 bus_dma_tag_destroy(sc->msk_stat_tag); 2206 sc->msk_stat_tag = NULL; 2207 } 2208 } 2209 2210 static int 2211 msk_txrx_dma_alloc(struct msk_if_softc *sc_if) 2212 { 2213 struct msk_dmamap_arg ctx; 2214 struct msk_txdesc *txd; 2215 struct msk_rxdesc *rxd; 2216 bus_size_t rxalign; 2217 int error, i; 2218 2219 /* Create parent DMA tag. */ 2220 error = bus_dma_tag_create( 2221 bus_get_dma_tag(sc_if->msk_if_dev), /* parent */ 2222 1, 0, /* alignment, boundary */ 2223 BUS_SPACE_MAXADDR, /* lowaddr */ 2224 BUS_SPACE_MAXADDR, /* highaddr */ 2225 NULL, NULL, /* filter, filterarg */ 2226 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 2227 0, /* nsegments */ 2228 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 2229 0, /* flags */ 2230 NULL, NULL, /* lockfunc, lockarg */ 2231 &sc_if->msk_cdata.msk_parent_tag); 2232 if (error != 0) { 2233 device_printf(sc_if->msk_if_dev, 2234 "failed to create parent DMA tag\n"); 2235 goto fail; 2236 } 2237 /* Create tag for Tx ring. */ 2238 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2239 MSK_RING_ALIGN, 0, /* alignment, boundary */ 2240 BUS_SPACE_MAXADDR, /* lowaddr */ 2241 BUS_SPACE_MAXADDR, /* highaddr */ 2242 NULL, NULL, /* filter, filterarg */ 2243 MSK_TX_RING_SZ, /* maxsize */ 2244 1, /* nsegments */ 2245 MSK_TX_RING_SZ, /* maxsegsize */ 2246 0, /* flags */ 2247 NULL, NULL, /* lockfunc, lockarg */ 2248 &sc_if->msk_cdata.msk_tx_ring_tag); 2249 if (error != 0) { 2250 device_printf(sc_if->msk_if_dev, 2251 "failed to create Tx ring DMA tag\n"); 2252 goto fail; 2253 } 2254 2255 /* Create tag for Rx ring. */ 2256 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2257 MSK_RING_ALIGN, 0, /* alignment, boundary */ 2258 BUS_SPACE_MAXADDR, /* lowaddr */ 2259 BUS_SPACE_MAXADDR, /* highaddr */ 2260 NULL, NULL, /* filter, filterarg */ 2261 MSK_RX_RING_SZ, /* maxsize */ 2262 1, /* nsegments */ 2263 MSK_RX_RING_SZ, /* maxsegsize */ 2264 0, /* flags */ 2265 NULL, NULL, /* lockfunc, lockarg */ 2266 &sc_if->msk_cdata.msk_rx_ring_tag); 2267 if (error != 0) { 2268 device_printf(sc_if->msk_if_dev, 2269 "failed to create Rx ring DMA tag\n"); 2270 goto fail; 2271 } 2272 2273 /* Create tag for Tx buffers. */ 2274 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2275 1, 0, /* alignment, boundary */ 2276 BUS_SPACE_MAXADDR, /* lowaddr */ 2277 BUS_SPACE_MAXADDR, /* highaddr */ 2278 NULL, NULL, /* filter, filterarg */ 2279 MSK_TSO_MAXSIZE, /* maxsize */ 2280 MSK_MAXTXSEGS, /* nsegments */ 2281 MSK_TSO_MAXSGSIZE, /* maxsegsize */ 2282 0, /* flags */ 2283 NULL, NULL, /* lockfunc, lockarg */ 2284 &sc_if->msk_cdata.msk_tx_tag); 2285 if (error != 0) { 2286 device_printf(sc_if->msk_if_dev, 2287 "failed to create Tx DMA tag\n"); 2288 goto fail; 2289 } 2290 2291 rxalign = 1; 2292 /* 2293 * Workaround hardware hang which seems to happen when Rx buffer 2294 * is not aligned on multiple of FIFO word(8 bytes). 2295 */ 2296 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) != 0) 2297 rxalign = MSK_RX_BUF_ALIGN; 2298 /* Create tag for Rx buffers. */ 2299 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2300 rxalign, 0, /* alignment, boundary */ 2301 BUS_SPACE_MAXADDR, /* lowaddr */ 2302 BUS_SPACE_MAXADDR, /* highaddr */ 2303 NULL, NULL, /* filter, filterarg */ 2304 MCLBYTES, /* maxsize */ 2305 1, /* nsegments */ 2306 MCLBYTES, /* maxsegsize */ 2307 0, /* flags */ 2308 NULL, NULL, /* lockfunc, lockarg */ 2309 &sc_if->msk_cdata.msk_rx_tag); 2310 if (error != 0) { 2311 device_printf(sc_if->msk_if_dev, 2312 "failed to create Rx DMA tag\n"); 2313 goto fail; 2314 } 2315 2316 /* Allocate DMA'able memory and load the DMA map for Tx ring. */ 2317 error = bus_dmamem_alloc(sc_if->msk_cdata.msk_tx_ring_tag, 2318 (void **)&sc_if->msk_rdata.msk_tx_ring, BUS_DMA_WAITOK | 2319 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc_if->msk_cdata.msk_tx_ring_map); 2320 if (error != 0) { 2321 device_printf(sc_if->msk_if_dev, 2322 "failed to allocate DMA'able memory for Tx ring\n"); 2323 goto fail; 2324 } 2325 2326 ctx.msk_busaddr = 0; 2327 error = bus_dmamap_load(sc_if->msk_cdata.msk_tx_ring_tag, 2328 sc_if->msk_cdata.msk_tx_ring_map, sc_if->msk_rdata.msk_tx_ring, 2329 MSK_TX_RING_SZ, msk_dmamap_cb, &ctx, BUS_DMA_NOWAIT); 2330 if (error != 0) { 2331 device_printf(sc_if->msk_if_dev, 2332 "failed to load DMA'able memory for Tx ring\n"); 2333 goto fail; 2334 } 2335 sc_if->msk_rdata.msk_tx_ring_paddr = ctx.msk_busaddr; 2336 2337 /* Allocate DMA'able memory and load the DMA map for Rx ring. */ 2338 error = bus_dmamem_alloc(sc_if->msk_cdata.msk_rx_ring_tag, 2339 (void **)&sc_if->msk_rdata.msk_rx_ring, BUS_DMA_WAITOK | 2340 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc_if->msk_cdata.msk_rx_ring_map); 2341 if (error != 0) { 2342 device_printf(sc_if->msk_if_dev, 2343 "failed to allocate DMA'able memory for Rx ring\n"); 2344 goto fail; 2345 } 2346 2347 ctx.msk_busaddr = 0; 2348 error = bus_dmamap_load(sc_if->msk_cdata.msk_rx_ring_tag, 2349 sc_if->msk_cdata.msk_rx_ring_map, sc_if->msk_rdata.msk_rx_ring, 2350 MSK_RX_RING_SZ, msk_dmamap_cb, &ctx, BUS_DMA_NOWAIT); 2351 if (error != 0) { 2352 device_printf(sc_if->msk_if_dev, 2353 "failed to load DMA'able memory for Rx ring\n"); 2354 goto fail; 2355 } 2356 sc_if->msk_rdata.msk_rx_ring_paddr = ctx.msk_busaddr; 2357 2358 /* Create DMA maps for Tx buffers. */ 2359 for (i = 0; i < MSK_TX_RING_CNT; i++) { 2360 txd = &sc_if->msk_cdata.msk_txdesc[i]; 2361 txd->tx_m = NULL; 2362 txd->tx_dmamap = NULL; 2363 error = bus_dmamap_create(sc_if->msk_cdata.msk_tx_tag, 0, 2364 &txd->tx_dmamap); 2365 if (error != 0) { 2366 device_printf(sc_if->msk_if_dev, 2367 "failed to create Tx dmamap\n"); 2368 goto fail; 2369 } 2370 } 2371 /* Create DMA maps for Rx buffers. */ 2372 if ((error = bus_dmamap_create(sc_if->msk_cdata.msk_rx_tag, 0, 2373 &sc_if->msk_cdata.msk_rx_sparemap)) != 0) { 2374 device_printf(sc_if->msk_if_dev, 2375 "failed to create spare Rx dmamap\n"); 2376 goto fail; 2377 } 2378 for (i = 0; i < MSK_RX_RING_CNT; i++) { 2379 rxd = &sc_if->msk_cdata.msk_rxdesc[i]; 2380 rxd->rx_m = NULL; 2381 rxd->rx_dmamap = NULL; 2382 error = bus_dmamap_create(sc_if->msk_cdata.msk_rx_tag, 0, 2383 &rxd->rx_dmamap); 2384 if (error != 0) { 2385 device_printf(sc_if->msk_if_dev, 2386 "failed to create Rx dmamap\n"); 2387 goto fail; 2388 } 2389 } 2390 2391 fail: 2392 return (error); 2393 } 2394 2395 static int 2396 msk_rx_dma_jalloc(struct msk_if_softc *sc_if) 2397 { 2398 struct msk_dmamap_arg ctx; 2399 struct msk_rxdesc *jrxd; 2400 bus_size_t rxalign; 2401 int error, i; 2402 2403 if (jumbo_disable != 0 || (sc_if->msk_flags & MSK_FLAG_JUMBO) == 0) { 2404 sc_if->msk_flags &= ~MSK_FLAG_JUMBO; 2405 device_printf(sc_if->msk_if_dev, 2406 "disabling jumbo frame support\n"); 2407 return (0); 2408 } 2409 /* Create tag for jumbo Rx ring. */ 2410 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2411 MSK_RING_ALIGN, 0, /* alignment, boundary */ 2412 BUS_SPACE_MAXADDR, /* lowaddr */ 2413 BUS_SPACE_MAXADDR, /* highaddr */ 2414 NULL, NULL, /* filter, filterarg */ 2415 MSK_JUMBO_RX_RING_SZ, /* maxsize */ 2416 1, /* nsegments */ 2417 MSK_JUMBO_RX_RING_SZ, /* maxsegsize */ 2418 0, /* flags */ 2419 NULL, NULL, /* lockfunc, lockarg */ 2420 &sc_if->msk_cdata.msk_jumbo_rx_ring_tag); 2421 if (error != 0) { 2422 device_printf(sc_if->msk_if_dev, 2423 "failed to create jumbo Rx ring DMA tag\n"); 2424 goto jumbo_fail; 2425 } 2426 2427 rxalign = 1; 2428 /* 2429 * Workaround hardware hang which seems to happen when Rx buffer 2430 * is not aligned on multiple of FIFO word(8 bytes). 2431 */ 2432 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) != 0) 2433 rxalign = MSK_RX_BUF_ALIGN; 2434 /* Create tag for jumbo Rx buffers. */ 2435 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2436 rxalign, 0, /* alignment, boundary */ 2437 BUS_SPACE_MAXADDR, /* lowaddr */ 2438 BUS_SPACE_MAXADDR, /* highaddr */ 2439 NULL, NULL, /* filter, filterarg */ 2440 MJUM9BYTES, /* maxsize */ 2441 1, /* nsegments */ 2442 MJUM9BYTES, /* maxsegsize */ 2443 0, /* flags */ 2444 NULL, NULL, /* lockfunc, lockarg */ 2445 &sc_if->msk_cdata.msk_jumbo_rx_tag); 2446 if (error != 0) { 2447 device_printf(sc_if->msk_if_dev, 2448 "failed to create jumbo Rx DMA tag\n"); 2449 goto jumbo_fail; 2450 } 2451 2452 /* Allocate DMA'able memory and load the DMA map for jumbo Rx ring. */ 2453 error = bus_dmamem_alloc(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 2454 (void **)&sc_if->msk_rdata.msk_jumbo_rx_ring, 2455 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 2456 &sc_if->msk_cdata.msk_jumbo_rx_ring_map); 2457 if (error != 0) { 2458 device_printf(sc_if->msk_if_dev, 2459 "failed to allocate DMA'able memory for jumbo Rx ring\n"); 2460 goto jumbo_fail; 2461 } 2462 2463 ctx.msk_busaddr = 0; 2464 error = bus_dmamap_load(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 2465 sc_if->msk_cdata.msk_jumbo_rx_ring_map, 2466 sc_if->msk_rdata.msk_jumbo_rx_ring, MSK_JUMBO_RX_RING_SZ, 2467 msk_dmamap_cb, &ctx, BUS_DMA_NOWAIT); 2468 if (error != 0) { 2469 device_printf(sc_if->msk_if_dev, 2470 "failed to load DMA'able memory for jumbo Rx ring\n"); 2471 goto jumbo_fail; 2472 } 2473 sc_if->msk_rdata.msk_jumbo_rx_ring_paddr = ctx.msk_busaddr; 2474 2475 /* Create DMA maps for jumbo Rx buffers. */ 2476 if ((error = bus_dmamap_create(sc_if->msk_cdata.msk_jumbo_rx_tag, 0, 2477 &sc_if->msk_cdata.msk_jumbo_rx_sparemap)) != 0) { 2478 device_printf(sc_if->msk_if_dev, 2479 "failed to create spare jumbo Rx dmamap\n"); 2480 goto jumbo_fail; 2481 } 2482 for (i = 0; i < MSK_JUMBO_RX_RING_CNT; i++) { 2483 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[i]; 2484 jrxd->rx_m = NULL; 2485 jrxd->rx_dmamap = NULL; 2486 error = bus_dmamap_create(sc_if->msk_cdata.msk_jumbo_rx_tag, 0, 2487 &jrxd->rx_dmamap); 2488 if (error != 0) { 2489 device_printf(sc_if->msk_if_dev, 2490 "failed to create jumbo Rx dmamap\n"); 2491 goto jumbo_fail; 2492 } 2493 } 2494 2495 return (0); 2496 2497 jumbo_fail: 2498 msk_rx_dma_jfree(sc_if); 2499 device_printf(sc_if->msk_if_dev, "disabling jumbo frame support " 2500 "due to resource shortage\n"); 2501 sc_if->msk_flags &= ~MSK_FLAG_JUMBO; 2502 return (error); 2503 } 2504 2505 static void 2506 msk_txrx_dma_free(struct msk_if_softc *sc_if) 2507 { 2508 struct msk_txdesc *txd; 2509 struct msk_rxdesc *rxd; 2510 int i; 2511 2512 /* Tx ring. */ 2513 if (sc_if->msk_cdata.msk_tx_ring_tag) { 2514 if (sc_if->msk_cdata.msk_tx_ring_map) 2515 bus_dmamap_unload(sc_if->msk_cdata.msk_tx_ring_tag, 2516 sc_if->msk_cdata.msk_tx_ring_map); 2517 if (sc_if->msk_cdata.msk_tx_ring_map && 2518 sc_if->msk_rdata.msk_tx_ring) 2519 bus_dmamem_free(sc_if->msk_cdata.msk_tx_ring_tag, 2520 sc_if->msk_rdata.msk_tx_ring, 2521 sc_if->msk_cdata.msk_tx_ring_map); 2522 sc_if->msk_rdata.msk_tx_ring = NULL; 2523 sc_if->msk_cdata.msk_tx_ring_map = NULL; 2524 bus_dma_tag_destroy(sc_if->msk_cdata.msk_tx_ring_tag); 2525 sc_if->msk_cdata.msk_tx_ring_tag = NULL; 2526 } 2527 /* Rx ring. */ 2528 if (sc_if->msk_cdata.msk_rx_ring_tag) { 2529 if (sc_if->msk_cdata.msk_rx_ring_map) 2530 bus_dmamap_unload(sc_if->msk_cdata.msk_rx_ring_tag, 2531 sc_if->msk_cdata.msk_rx_ring_map); 2532 if (sc_if->msk_cdata.msk_rx_ring_map && 2533 sc_if->msk_rdata.msk_rx_ring) 2534 bus_dmamem_free(sc_if->msk_cdata.msk_rx_ring_tag, 2535 sc_if->msk_rdata.msk_rx_ring, 2536 sc_if->msk_cdata.msk_rx_ring_map); 2537 sc_if->msk_rdata.msk_rx_ring = NULL; 2538 sc_if->msk_cdata.msk_rx_ring_map = NULL; 2539 bus_dma_tag_destroy(sc_if->msk_cdata.msk_rx_ring_tag); 2540 sc_if->msk_cdata.msk_rx_ring_tag = NULL; 2541 } 2542 /* Tx buffers. */ 2543 if (sc_if->msk_cdata.msk_tx_tag) { 2544 for (i = 0; i < MSK_TX_RING_CNT; i++) { 2545 txd = &sc_if->msk_cdata.msk_txdesc[i]; 2546 if (txd->tx_dmamap) { 2547 bus_dmamap_destroy(sc_if->msk_cdata.msk_tx_tag, 2548 txd->tx_dmamap); 2549 txd->tx_dmamap = NULL; 2550 } 2551 } 2552 bus_dma_tag_destroy(sc_if->msk_cdata.msk_tx_tag); 2553 sc_if->msk_cdata.msk_tx_tag = NULL; 2554 } 2555 /* Rx buffers. */ 2556 if (sc_if->msk_cdata.msk_rx_tag) { 2557 for (i = 0; i < MSK_RX_RING_CNT; i++) { 2558 rxd = &sc_if->msk_cdata.msk_rxdesc[i]; 2559 if (rxd->rx_dmamap) { 2560 bus_dmamap_destroy(sc_if->msk_cdata.msk_rx_tag, 2561 rxd->rx_dmamap); 2562 rxd->rx_dmamap = NULL; 2563 } 2564 } 2565 if (sc_if->msk_cdata.msk_rx_sparemap) { 2566 bus_dmamap_destroy(sc_if->msk_cdata.msk_rx_tag, 2567 sc_if->msk_cdata.msk_rx_sparemap); 2568 sc_if->msk_cdata.msk_rx_sparemap = 0; 2569 } 2570 bus_dma_tag_destroy(sc_if->msk_cdata.msk_rx_tag); 2571 sc_if->msk_cdata.msk_rx_tag = NULL; 2572 } 2573 if (sc_if->msk_cdata.msk_parent_tag) { 2574 bus_dma_tag_destroy(sc_if->msk_cdata.msk_parent_tag); 2575 sc_if->msk_cdata.msk_parent_tag = NULL; 2576 } 2577 } 2578 2579 static void 2580 msk_rx_dma_jfree(struct msk_if_softc *sc_if) 2581 { 2582 struct msk_rxdesc *jrxd; 2583 int i; 2584 2585 /* Jumbo Rx ring. */ 2586 if (sc_if->msk_cdata.msk_jumbo_rx_ring_tag) { 2587 if (sc_if->msk_cdata.msk_jumbo_rx_ring_map) 2588 bus_dmamap_unload(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 2589 sc_if->msk_cdata.msk_jumbo_rx_ring_map); 2590 if (sc_if->msk_cdata.msk_jumbo_rx_ring_map && 2591 sc_if->msk_rdata.msk_jumbo_rx_ring) 2592 bus_dmamem_free(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 2593 sc_if->msk_rdata.msk_jumbo_rx_ring, 2594 sc_if->msk_cdata.msk_jumbo_rx_ring_map); 2595 sc_if->msk_rdata.msk_jumbo_rx_ring = NULL; 2596 sc_if->msk_cdata.msk_jumbo_rx_ring_map = NULL; 2597 bus_dma_tag_destroy(sc_if->msk_cdata.msk_jumbo_rx_ring_tag); 2598 sc_if->msk_cdata.msk_jumbo_rx_ring_tag = NULL; 2599 } 2600 /* Jumbo Rx buffers. */ 2601 if (sc_if->msk_cdata.msk_jumbo_rx_tag) { 2602 for (i = 0; i < MSK_JUMBO_RX_RING_CNT; i++) { 2603 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[i]; 2604 if (jrxd->rx_dmamap) { 2605 bus_dmamap_destroy( 2606 sc_if->msk_cdata.msk_jumbo_rx_tag, 2607 jrxd->rx_dmamap); 2608 jrxd->rx_dmamap = NULL; 2609 } 2610 } 2611 if (sc_if->msk_cdata.msk_jumbo_rx_sparemap) { 2612 bus_dmamap_destroy(sc_if->msk_cdata.msk_jumbo_rx_tag, 2613 sc_if->msk_cdata.msk_jumbo_rx_sparemap); 2614 sc_if->msk_cdata.msk_jumbo_rx_sparemap = 0; 2615 } 2616 bus_dma_tag_destroy(sc_if->msk_cdata.msk_jumbo_rx_tag); 2617 sc_if->msk_cdata.msk_jumbo_rx_tag = NULL; 2618 } 2619 } 2620 2621 static int 2622 msk_encap(struct msk_if_softc *sc_if, struct mbuf **m_head) 2623 { 2624 struct msk_txdesc *txd, *txd_last; 2625 struct msk_tx_desc *tx_le; 2626 struct mbuf *m; 2627 bus_dmamap_t map; 2628 bus_dma_segment_t txsegs[MSK_MAXTXSEGS]; 2629 uint32_t control, csum, prod, si; 2630 uint16_t offset, tcp_offset, tso_mtu; 2631 int error, i, nseg, tso; 2632 2633 MSK_IF_LOCK_ASSERT(sc_if); 2634 2635 tcp_offset = offset = 0; 2636 m = *m_head; 2637 if (((sc_if->msk_flags & MSK_FLAG_AUTOTX_CSUM) == 0 && 2638 (m->m_pkthdr.csum_flags & MSK_CSUM_FEATURES) != 0) || 2639 ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0 && 2640 (m->m_pkthdr.csum_flags & CSUM_TSO) != 0)) { 2641 /* 2642 * Since mbuf has no protocol specific structure information 2643 * in it we have to inspect protocol information here to 2644 * setup TSO and checksum offload. I don't know why Marvell 2645 * made a such decision in chip design because other GigE 2646 * hardwares normally takes care of all these chores in 2647 * hardware. However, TSO performance of Yukon II is very 2648 * good such that it's worth to implement it. 2649 */ 2650 struct ether_header *eh; 2651 struct ip *ip; 2652 struct tcphdr *tcp; 2653 2654 if (M_WRITABLE(m) == 0) { 2655 /* Get a writable copy. */ 2656 m = m_dup(*m_head, M_NOWAIT); 2657 m_freem(*m_head); 2658 if (m == NULL) { 2659 *m_head = NULL; 2660 return (ENOBUFS); 2661 } 2662 *m_head = m; 2663 } 2664 2665 offset = sizeof(struct ether_header); 2666 m = m_pullup(m, offset); 2667 if (m == NULL) { 2668 *m_head = NULL; 2669 return (ENOBUFS); 2670 } 2671 eh = mtod(m, struct ether_header *); 2672 /* Check if hardware VLAN insertion is off. */ 2673 if (eh->ether_type == htons(ETHERTYPE_VLAN)) { 2674 offset = sizeof(struct ether_vlan_header); 2675 m = m_pullup(m, offset); 2676 if (m == NULL) { 2677 *m_head = NULL; 2678 return (ENOBUFS); 2679 } 2680 } 2681 m = m_pullup(m, offset + sizeof(struct ip)); 2682 if (m == NULL) { 2683 *m_head = NULL; 2684 return (ENOBUFS); 2685 } 2686 ip = (struct ip *)(mtod(m, char *) + offset); 2687 offset += (ip->ip_hl << 2); 2688 tcp_offset = offset; 2689 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 2690 m = m_pullup(m, offset + sizeof(struct tcphdr)); 2691 if (m == NULL) { 2692 *m_head = NULL; 2693 return (ENOBUFS); 2694 } 2695 tcp = (struct tcphdr *)(mtod(m, char *) + offset); 2696 offset += (tcp->th_off << 2); 2697 } else if ((sc_if->msk_flags & MSK_FLAG_AUTOTX_CSUM) == 0 && 2698 (m->m_pkthdr.len < MSK_MIN_FRAMELEN) && 2699 (m->m_pkthdr.csum_flags & CSUM_TCP) != 0) { 2700 /* 2701 * It seems that Yukon II has Tx checksum offload bug 2702 * for small TCP packets that's less than 60 bytes in 2703 * size (e.g. TCP window probe packet, pure ACK packet). 2704 * Common work around like padding with zeros to make 2705 * the frame minimum ethernet frame size didn't work at 2706 * all. 2707 * Instead of disabling checksum offload completely we 2708 * resort to S/W checksum routine when we encounter 2709 * short TCP frames. 2710 * Short UDP packets appear to be handled correctly by 2711 * Yukon II. Also I assume this bug does not happen on 2712 * controllers that use newer descriptor format or 2713 * automatic Tx checksum calculation. 2714 */ 2715 m = m_pullup(m, offset + sizeof(struct tcphdr)); 2716 if (m == NULL) { 2717 *m_head = NULL; 2718 return (ENOBUFS); 2719 } 2720 *(uint16_t *)(m->m_data + offset + 2721 m->m_pkthdr.csum_data) = in_cksum_skip(m, 2722 m->m_pkthdr.len, offset); 2723 m->m_pkthdr.csum_flags &= ~CSUM_TCP; 2724 } 2725 *m_head = m; 2726 } 2727 2728 prod = sc_if->msk_cdata.msk_tx_prod; 2729 txd = &sc_if->msk_cdata.msk_txdesc[prod]; 2730 txd_last = txd; 2731 map = txd->tx_dmamap; 2732 error = bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_tx_tag, map, 2733 *m_head, txsegs, &nseg, BUS_DMA_NOWAIT); 2734 if (error == EFBIG) { 2735 m = m_collapse(*m_head, M_NOWAIT, MSK_MAXTXSEGS); 2736 if (m == NULL) { 2737 m_freem(*m_head); 2738 *m_head = NULL; 2739 return (ENOBUFS); 2740 } 2741 *m_head = m; 2742 error = bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_tx_tag, 2743 map, *m_head, txsegs, &nseg, BUS_DMA_NOWAIT); 2744 if (error != 0) { 2745 m_freem(*m_head); 2746 *m_head = NULL; 2747 return (error); 2748 } 2749 } else if (error != 0) 2750 return (error); 2751 if (nseg == 0) { 2752 m_freem(*m_head); 2753 *m_head = NULL; 2754 return (EIO); 2755 } 2756 2757 /* Check number of available descriptors. */ 2758 if (sc_if->msk_cdata.msk_tx_cnt + nseg >= 2759 (MSK_TX_RING_CNT - MSK_RESERVED_TX_DESC_CNT)) { 2760 bus_dmamap_unload(sc_if->msk_cdata.msk_tx_tag, map); 2761 return (ENOBUFS); 2762 } 2763 2764 control = 0; 2765 tso = 0; 2766 tx_le = NULL; 2767 2768 /* Check TSO support. */ 2769 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 2770 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) != 0) 2771 tso_mtu = m->m_pkthdr.tso_segsz; 2772 else 2773 tso_mtu = offset + m->m_pkthdr.tso_segsz; 2774 if (tso_mtu != sc_if->msk_cdata.msk_tso_mtu) { 2775 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2776 tx_le->msk_addr = htole32(tso_mtu); 2777 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) != 0) 2778 tx_le->msk_control = htole32(OP_MSS | HW_OWNER); 2779 else 2780 tx_le->msk_control = 2781 htole32(OP_LRGLEN | HW_OWNER); 2782 sc_if->msk_cdata.msk_tx_cnt++; 2783 MSK_INC(prod, MSK_TX_RING_CNT); 2784 sc_if->msk_cdata.msk_tso_mtu = tso_mtu; 2785 } 2786 tso++; 2787 } 2788 /* Check if we have a VLAN tag to insert. */ 2789 if ((m->m_flags & M_VLANTAG) != 0) { 2790 if (tx_le == NULL) { 2791 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2792 tx_le->msk_addr = htole32(0); 2793 tx_le->msk_control = htole32(OP_VLAN | HW_OWNER | 2794 htons(m->m_pkthdr.ether_vtag)); 2795 sc_if->msk_cdata.msk_tx_cnt++; 2796 MSK_INC(prod, MSK_TX_RING_CNT); 2797 } else { 2798 tx_le->msk_control |= htole32(OP_VLAN | 2799 htons(m->m_pkthdr.ether_vtag)); 2800 } 2801 control |= INS_VLAN; 2802 } 2803 /* Check if we have to handle checksum offload. */ 2804 if (tso == 0 && (m->m_pkthdr.csum_flags & MSK_CSUM_FEATURES) != 0) { 2805 if ((sc_if->msk_flags & MSK_FLAG_AUTOTX_CSUM) != 0) 2806 control |= CALSUM; 2807 else { 2808 control |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM; 2809 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0) 2810 control |= UDPTCP; 2811 /* Checksum write position. */ 2812 csum = (tcp_offset + m->m_pkthdr.csum_data) & 0xffff; 2813 /* Checksum start position. */ 2814 csum |= (uint32_t)tcp_offset << 16; 2815 if (csum != sc_if->msk_cdata.msk_last_csum) { 2816 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2817 tx_le->msk_addr = htole32(csum); 2818 tx_le->msk_control = htole32(1 << 16 | 2819 (OP_TCPLISW | HW_OWNER)); 2820 sc_if->msk_cdata.msk_tx_cnt++; 2821 MSK_INC(prod, MSK_TX_RING_CNT); 2822 sc_if->msk_cdata.msk_last_csum = csum; 2823 } 2824 } 2825 } 2826 2827 #ifdef MSK_64BIT_DMA 2828 if (MSK_ADDR_HI(txsegs[0].ds_addr) != 2829 sc_if->msk_cdata.msk_tx_high_addr) { 2830 sc_if->msk_cdata.msk_tx_high_addr = 2831 MSK_ADDR_HI(txsegs[0].ds_addr); 2832 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2833 tx_le->msk_addr = htole32(MSK_ADDR_HI(txsegs[0].ds_addr)); 2834 tx_le->msk_control = htole32(OP_ADDR64 | HW_OWNER); 2835 sc_if->msk_cdata.msk_tx_cnt++; 2836 MSK_INC(prod, MSK_TX_RING_CNT); 2837 } 2838 #endif 2839 si = prod; 2840 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2841 tx_le->msk_addr = htole32(MSK_ADDR_LO(txsegs[0].ds_addr)); 2842 if (tso == 0) 2843 tx_le->msk_control = htole32(txsegs[0].ds_len | control | 2844 OP_PACKET); 2845 else 2846 tx_le->msk_control = htole32(txsegs[0].ds_len | control | 2847 OP_LARGESEND); 2848 sc_if->msk_cdata.msk_tx_cnt++; 2849 MSK_INC(prod, MSK_TX_RING_CNT); 2850 2851 for (i = 1; i < nseg; i++) { 2852 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2853 #ifdef MSK_64BIT_DMA 2854 if (MSK_ADDR_HI(txsegs[i].ds_addr) != 2855 sc_if->msk_cdata.msk_tx_high_addr) { 2856 sc_if->msk_cdata.msk_tx_high_addr = 2857 MSK_ADDR_HI(txsegs[i].ds_addr); 2858 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2859 tx_le->msk_addr = 2860 htole32(MSK_ADDR_HI(txsegs[i].ds_addr)); 2861 tx_le->msk_control = htole32(OP_ADDR64 | HW_OWNER); 2862 sc_if->msk_cdata.msk_tx_cnt++; 2863 MSK_INC(prod, MSK_TX_RING_CNT); 2864 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2865 } 2866 #endif 2867 tx_le->msk_addr = htole32(MSK_ADDR_LO(txsegs[i].ds_addr)); 2868 tx_le->msk_control = htole32(txsegs[i].ds_len | control | 2869 OP_BUFFER | HW_OWNER); 2870 sc_if->msk_cdata.msk_tx_cnt++; 2871 MSK_INC(prod, MSK_TX_RING_CNT); 2872 } 2873 /* Update producer index. */ 2874 sc_if->msk_cdata.msk_tx_prod = prod; 2875 2876 /* Set EOP on the last descriptor. */ 2877 prod = (prod + MSK_TX_RING_CNT - 1) % MSK_TX_RING_CNT; 2878 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2879 tx_le->msk_control |= htole32(EOP); 2880 2881 /* Turn the first descriptor ownership to hardware. */ 2882 tx_le = &sc_if->msk_rdata.msk_tx_ring[si]; 2883 tx_le->msk_control |= htole32(HW_OWNER); 2884 2885 txd = &sc_if->msk_cdata.msk_txdesc[prod]; 2886 map = txd_last->tx_dmamap; 2887 txd_last->tx_dmamap = txd->tx_dmamap; 2888 txd->tx_dmamap = map; 2889 txd->tx_m = m; 2890 2891 /* Sync descriptors. */ 2892 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_tag, map, BUS_DMASYNC_PREWRITE); 2893 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_ring_tag, 2894 sc_if->msk_cdata.msk_tx_ring_map, 2895 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2896 2897 return (0); 2898 } 2899 2900 static void 2901 msk_start(struct ifnet *ifp) 2902 { 2903 struct msk_if_softc *sc_if; 2904 2905 sc_if = ifp->if_softc; 2906 MSK_IF_LOCK(sc_if); 2907 msk_start_locked(ifp); 2908 MSK_IF_UNLOCK(sc_if); 2909 } 2910 2911 static void 2912 msk_start_locked(struct ifnet *ifp) 2913 { 2914 struct msk_if_softc *sc_if; 2915 struct mbuf *m_head; 2916 int enq; 2917 2918 sc_if = ifp->if_softc; 2919 MSK_IF_LOCK_ASSERT(sc_if); 2920 2921 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2922 IFF_DRV_RUNNING || (sc_if->msk_flags & MSK_FLAG_LINK) == 0) 2923 return; 2924 2925 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 2926 sc_if->msk_cdata.msk_tx_cnt < 2927 (MSK_TX_RING_CNT - MSK_RESERVED_TX_DESC_CNT); ) { 2928 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2929 if (m_head == NULL) 2930 break; 2931 /* 2932 * Pack the data into the transmit ring. If we 2933 * don't have room, set the OACTIVE flag and wait 2934 * for the NIC to drain the ring. 2935 */ 2936 if (msk_encap(sc_if, &m_head) != 0) { 2937 if (m_head == NULL) 2938 break; 2939 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2940 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2941 break; 2942 } 2943 2944 enq++; 2945 /* 2946 * If there's a BPF listener, bounce a copy of this frame 2947 * to him. 2948 */ 2949 ETHER_BPF_MTAP(ifp, m_head); 2950 } 2951 2952 if (enq > 0) { 2953 /* Transmit */ 2954 CSR_WRITE_2(sc_if->msk_softc, 2955 Y2_PREF_Q_ADDR(sc_if->msk_txq, PREF_UNIT_PUT_IDX_REG), 2956 sc_if->msk_cdata.msk_tx_prod); 2957 2958 /* Set a timeout in case the chip goes out to lunch. */ 2959 sc_if->msk_watchdog_timer = MSK_TX_TIMEOUT; 2960 } 2961 } 2962 2963 static void 2964 msk_watchdog(struct msk_if_softc *sc_if) 2965 { 2966 struct ifnet *ifp; 2967 2968 MSK_IF_LOCK_ASSERT(sc_if); 2969 2970 if (sc_if->msk_watchdog_timer == 0 || --sc_if->msk_watchdog_timer) 2971 return; 2972 ifp = sc_if->msk_ifp; 2973 if ((sc_if->msk_flags & MSK_FLAG_LINK) == 0) { 2974 if (bootverbose) 2975 if_printf(sc_if->msk_ifp, "watchdog timeout " 2976 "(missed link)\n"); 2977 ifp->if_oerrors++; 2978 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2979 msk_init_locked(sc_if); 2980 return; 2981 } 2982 2983 if_printf(ifp, "watchdog timeout\n"); 2984 ifp->if_oerrors++; 2985 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2986 msk_init_locked(sc_if); 2987 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2988 msk_start_locked(ifp); 2989 } 2990 2991 static int 2992 mskc_shutdown(device_t dev) 2993 { 2994 struct msk_softc *sc; 2995 int i; 2996 2997 sc = device_get_softc(dev); 2998 MSK_LOCK(sc); 2999 for (i = 0; i < sc->msk_num_port; i++) { 3000 if (sc->msk_if[i] != NULL && sc->msk_if[i]->msk_ifp != NULL && 3001 ((sc->msk_if[i]->msk_ifp->if_drv_flags & 3002 IFF_DRV_RUNNING) != 0)) 3003 msk_stop(sc->msk_if[i]); 3004 } 3005 MSK_UNLOCK(sc); 3006 3007 /* Put hardware reset. */ 3008 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); 3009 return (0); 3010 } 3011 3012 static int 3013 mskc_suspend(device_t dev) 3014 { 3015 struct msk_softc *sc; 3016 int i; 3017 3018 sc = device_get_softc(dev); 3019 3020 MSK_LOCK(sc); 3021 3022 for (i = 0; i < sc->msk_num_port; i++) { 3023 if (sc->msk_if[i] != NULL && sc->msk_if[i]->msk_ifp != NULL && 3024 ((sc->msk_if[i]->msk_ifp->if_drv_flags & 3025 IFF_DRV_RUNNING) != 0)) 3026 msk_stop(sc->msk_if[i]); 3027 } 3028 3029 /* Disable all interrupts. */ 3030 CSR_WRITE_4(sc, B0_IMSK, 0); 3031 CSR_READ_4(sc, B0_IMSK); 3032 CSR_WRITE_4(sc, B0_HWE_IMSK, 0); 3033 CSR_READ_4(sc, B0_HWE_IMSK); 3034 3035 msk_phy_power(sc, MSK_PHY_POWERDOWN); 3036 3037 /* Put hardware reset. */ 3038 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); 3039 sc->msk_pflags |= MSK_FLAG_SUSPEND; 3040 3041 MSK_UNLOCK(sc); 3042 3043 return (0); 3044 } 3045 3046 static int 3047 mskc_resume(device_t dev) 3048 { 3049 struct msk_softc *sc; 3050 int i; 3051 3052 sc = device_get_softc(dev); 3053 3054 MSK_LOCK(sc); 3055 3056 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_3, 0); 3057 mskc_reset(sc); 3058 for (i = 0; i < sc->msk_num_port; i++) { 3059 if (sc->msk_if[i] != NULL && sc->msk_if[i]->msk_ifp != NULL && 3060 ((sc->msk_if[i]->msk_ifp->if_flags & IFF_UP) != 0)) { 3061 sc->msk_if[i]->msk_ifp->if_drv_flags &= 3062 ~IFF_DRV_RUNNING; 3063 msk_init_locked(sc->msk_if[i]); 3064 } 3065 } 3066 sc->msk_pflags &= ~MSK_FLAG_SUSPEND; 3067 3068 MSK_UNLOCK(sc); 3069 3070 return (0); 3071 } 3072 3073 #ifndef __NO_STRICT_ALIGNMENT 3074 static __inline void 3075 msk_fixup_rx(struct mbuf *m) 3076 { 3077 int i; 3078 uint16_t *src, *dst; 3079 3080 src = mtod(m, uint16_t *); 3081 dst = src - 3; 3082 3083 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 3084 *dst++ = *src++; 3085 3086 m->m_data -= (MSK_RX_BUF_ALIGN - ETHER_ALIGN); 3087 } 3088 #endif 3089 3090 static __inline void 3091 msk_rxcsum(struct msk_if_softc *sc_if, uint32_t control, struct mbuf *m) 3092 { 3093 struct ether_header *eh; 3094 struct ip *ip; 3095 struct udphdr *uh; 3096 int32_t hlen, len, pktlen, temp32; 3097 uint16_t csum, *opts; 3098 3099 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) != 0) { 3100 if ((control & (CSS_IPV4 | CSS_IPFRAG)) == CSS_IPV4) { 3101 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 3102 if ((control & CSS_IPV4_CSUM_OK) != 0) 3103 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 3104 if ((control & (CSS_TCP | CSS_UDP)) != 0 && 3105 (control & (CSS_TCPUDP_CSUM_OK)) != 0) { 3106 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID | 3107 CSUM_PSEUDO_HDR; 3108 m->m_pkthdr.csum_data = 0xffff; 3109 } 3110 } 3111 return; 3112 } 3113 /* 3114 * Marvell Yukon controllers that support OP_RXCHKS has known 3115 * to have various Rx checksum offloading bugs. These 3116 * controllers can be configured to compute simple checksum 3117 * at two different positions. So we can compute IP and TCP/UDP 3118 * checksum at the same time. We intentionally have controller 3119 * compute TCP/UDP checksum twice by specifying the same 3120 * checksum start position and compare the result. If the value 3121 * is different it would indicate the hardware logic was wrong. 3122 */ 3123 if ((sc_if->msk_csum & 0xFFFF) != (sc_if->msk_csum >> 16)) { 3124 if (bootverbose) 3125 device_printf(sc_if->msk_if_dev, 3126 "Rx checksum value mismatch!\n"); 3127 return; 3128 } 3129 pktlen = m->m_pkthdr.len; 3130 if (pktlen < sizeof(struct ether_header) + sizeof(struct ip)) 3131 return; 3132 eh = mtod(m, struct ether_header *); 3133 if (eh->ether_type != htons(ETHERTYPE_IP)) 3134 return; 3135 ip = (struct ip *)(eh + 1); 3136 if (ip->ip_v != IPVERSION) 3137 return; 3138 3139 hlen = ip->ip_hl << 2; 3140 pktlen -= sizeof(struct ether_header); 3141 if (hlen < sizeof(struct ip)) 3142 return; 3143 if (ntohs(ip->ip_len) < hlen) 3144 return; 3145 if (ntohs(ip->ip_len) != pktlen) 3146 return; 3147 if (ip->ip_off & htons(IP_MF | IP_OFFMASK)) 3148 return; /* can't handle fragmented packet. */ 3149 3150 switch (ip->ip_p) { 3151 case IPPROTO_TCP: 3152 if (pktlen < (hlen + sizeof(struct tcphdr))) 3153 return; 3154 break; 3155 case IPPROTO_UDP: 3156 if (pktlen < (hlen + sizeof(struct udphdr))) 3157 return; 3158 uh = (struct udphdr *)((caddr_t)ip + hlen); 3159 if (uh->uh_sum == 0) 3160 return; /* no checksum */ 3161 break; 3162 default: 3163 return; 3164 } 3165 csum = bswap16(sc_if->msk_csum & 0xFFFF); 3166 /* Checksum fixup for IP options. */ 3167 len = hlen - sizeof(struct ip); 3168 if (len > 0) { 3169 opts = (uint16_t *)(ip + 1); 3170 for (; len > 0; len -= sizeof(uint16_t), opts++) { 3171 temp32 = csum - *opts; 3172 temp32 = (temp32 >> 16) + (temp32 & 65535); 3173 csum = temp32 & 65535; 3174 } 3175 } 3176 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID; 3177 m->m_pkthdr.csum_data = csum; 3178 } 3179 3180 static void 3181 msk_rxeof(struct msk_if_softc *sc_if, uint32_t status, uint32_t control, 3182 int len) 3183 { 3184 struct mbuf *m; 3185 struct ifnet *ifp; 3186 struct msk_rxdesc *rxd; 3187 int cons, rxlen; 3188 3189 ifp = sc_if->msk_ifp; 3190 3191 MSK_IF_LOCK_ASSERT(sc_if); 3192 3193 cons = sc_if->msk_cdata.msk_rx_cons; 3194 do { 3195 rxlen = status >> 16; 3196 if ((status & GMR_FS_VLAN) != 0 && 3197 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 3198 rxlen -= ETHER_VLAN_ENCAP_LEN; 3199 if ((sc_if->msk_flags & MSK_FLAG_NORXCHK) != 0) { 3200 /* 3201 * For controllers that returns bogus status code 3202 * just do minimal check and let upper stack 3203 * handle this frame. 3204 */ 3205 if (len > MSK_MAX_FRAMELEN || len < ETHER_HDR_LEN) { 3206 ifp->if_ierrors++; 3207 msk_discard_rxbuf(sc_if, cons); 3208 break; 3209 } 3210 } else if (len > sc_if->msk_framesize || 3211 ((status & GMR_FS_ANY_ERR) != 0) || 3212 ((status & GMR_FS_RX_OK) == 0) || (rxlen != len)) { 3213 /* Don't count flow-control packet as errors. */ 3214 if ((status & GMR_FS_GOOD_FC) == 0) 3215 ifp->if_ierrors++; 3216 msk_discard_rxbuf(sc_if, cons); 3217 break; 3218 } 3219 #ifdef MSK_64BIT_DMA 3220 rxd = &sc_if->msk_cdata.msk_rxdesc[(cons + 1) % 3221 MSK_RX_RING_CNT]; 3222 #else 3223 rxd = &sc_if->msk_cdata.msk_rxdesc[cons]; 3224 #endif 3225 m = rxd->rx_m; 3226 if (msk_newbuf(sc_if, cons) != 0) { 3227 ifp->if_iqdrops++; 3228 /* Reuse old buffer. */ 3229 msk_discard_rxbuf(sc_if, cons); 3230 break; 3231 } 3232 m->m_pkthdr.rcvif = ifp; 3233 m->m_pkthdr.len = m->m_len = len; 3234 #ifndef __NO_STRICT_ALIGNMENT 3235 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) != 0) 3236 msk_fixup_rx(m); 3237 #endif 3238 ifp->if_ipackets++; 3239 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 3240 msk_rxcsum(sc_if, control, m); 3241 /* Check for VLAN tagged packets. */ 3242 if ((status & GMR_FS_VLAN) != 0 && 3243 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) { 3244 m->m_pkthdr.ether_vtag = sc_if->msk_vtag; 3245 m->m_flags |= M_VLANTAG; 3246 } 3247 MSK_IF_UNLOCK(sc_if); 3248 (*ifp->if_input)(ifp, m); 3249 MSK_IF_LOCK(sc_if); 3250 } while (0); 3251 3252 MSK_RX_INC(sc_if->msk_cdata.msk_rx_cons, MSK_RX_RING_CNT); 3253 MSK_RX_INC(sc_if->msk_cdata.msk_rx_prod, MSK_RX_RING_CNT); 3254 } 3255 3256 static void 3257 msk_jumbo_rxeof(struct msk_if_softc *sc_if, uint32_t status, uint32_t control, 3258 int len) 3259 { 3260 struct mbuf *m; 3261 struct ifnet *ifp; 3262 struct msk_rxdesc *jrxd; 3263 int cons, rxlen; 3264 3265 ifp = sc_if->msk_ifp; 3266 3267 MSK_IF_LOCK_ASSERT(sc_if); 3268 3269 cons = sc_if->msk_cdata.msk_rx_cons; 3270 do { 3271 rxlen = status >> 16; 3272 if ((status & GMR_FS_VLAN) != 0 && 3273 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 3274 rxlen -= ETHER_VLAN_ENCAP_LEN; 3275 if (len > sc_if->msk_framesize || 3276 ((status & GMR_FS_ANY_ERR) != 0) || 3277 ((status & GMR_FS_RX_OK) == 0) || (rxlen != len)) { 3278 /* Don't count flow-control packet as errors. */ 3279 if ((status & GMR_FS_GOOD_FC) == 0) 3280 ifp->if_ierrors++; 3281 msk_discard_jumbo_rxbuf(sc_if, cons); 3282 break; 3283 } 3284 #ifdef MSK_64BIT_DMA 3285 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[(cons + 1) % 3286 MSK_JUMBO_RX_RING_CNT]; 3287 #else 3288 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[cons]; 3289 #endif 3290 m = jrxd->rx_m; 3291 if (msk_jumbo_newbuf(sc_if, cons) != 0) { 3292 ifp->if_iqdrops++; 3293 /* Reuse old buffer. */ 3294 msk_discard_jumbo_rxbuf(sc_if, cons); 3295 break; 3296 } 3297 m->m_pkthdr.rcvif = ifp; 3298 m->m_pkthdr.len = m->m_len = len; 3299 #ifndef __NO_STRICT_ALIGNMENT 3300 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) != 0) 3301 msk_fixup_rx(m); 3302 #endif 3303 ifp->if_ipackets++; 3304 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 3305 msk_rxcsum(sc_if, control, m); 3306 /* Check for VLAN tagged packets. */ 3307 if ((status & GMR_FS_VLAN) != 0 && 3308 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) { 3309 m->m_pkthdr.ether_vtag = sc_if->msk_vtag; 3310 m->m_flags |= M_VLANTAG; 3311 } 3312 MSK_IF_UNLOCK(sc_if); 3313 (*ifp->if_input)(ifp, m); 3314 MSK_IF_LOCK(sc_if); 3315 } while (0); 3316 3317 MSK_RX_INC(sc_if->msk_cdata.msk_rx_cons, MSK_JUMBO_RX_RING_CNT); 3318 MSK_RX_INC(sc_if->msk_cdata.msk_rx_prod, MSK_JUMBO_RX_RING_CNT); 3319 } 3320 3321 static void 3322 msk_txeof(struct msk_if_softc *sc_if, int idx) 3323 { 3324 struct msk_txdesc *txd; 3325 struct msk_tx_desc *cur_tx; 3326 struct ifnet *ifp; 3327 uint32_t control; 3328 int cons, prog; 3329 3330 MSK_IF_LOCK_ASSERT(sc_if); 3331 3332 ifp = sc_if->msk_ifp; 3333 3334 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_ring_tag, 3335 sc_if->msk_cdata.msk_tx_ring_map, 3336 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3337 /* 3338 * Go through our tx ring and free mbufs for those 3339 * frames that have been sent. 3340 */ 3341 cons = sc_if->msk_cdata.msk_tx_cons; 3342 prog = 0; 3343 for (; cons != idx; MSK_INC(cons, MSK_TX_RING_CNT)) { 3344 if (sc_if->msk_cdata.msk_tx_cnt <= 0) 3345 break; 3346 prog++; 3347 cur_tx = &sc_if->msk_rdata.msk_tx_ring[cons]; 3348 control = le32toh(cur_tx->msk_control); 3349 sc_if->msk_cdata.msk_tx_cnt--; 3350 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3351 if ((control & EOP) == 0) 3352 continue; 3353 txd = &sc_if->msk_cdata.msk_txdesc[cons]; 3354 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_tag, txd->tx_dmamap, 3355 BUS_DMASYNC_POSTWRITE); 3356 bus_dmamap_unload(sc_if->msk_cdata.msk_tx_tag, txd->tx_dmamap); 3357 3358 ifp->if_opackets++; 3359 KASSERT(txd->tx_m != NULL, ("%s: freeing NULL mbuf!", 3360 __func__)); 3361 m_freem(txd->tx_m); 3362 txd->tx_m = NULL; 3363 } 3364 3365 if (prog > 0) { 3366 sc_if->msk_cdata.msk_tx_cons = cons; 3367 if (sc_if->msk_cdata.msk_tx_cnt == 0) 3368 sc_if->msk_watchdog_timer = 0; 3369 /* No need to sync LEs as we didn't update LEs. */ 3370 } 3371 } 3372 3373 static void 3374 msk_tick(void *xsc_if) 3375 { 3376 struct msk_if_softc *sc_if; 3377 struct mii_data *mii; 3378 3379 sc_if = xsc_if; 3380 3381 MSK_IF_LOCK_ASSERT(sc_if); 3382 3383 mii = device_get_softc(sc_if->msk_miibus); 3384 3385 mii_tick(mii); 3386 if ((sc_if->msk_flags & MSK_FLAG_LINK) == 0) 3387 msk_miibus_statchg(sc_if->msk_if_dev); 3388 msk_handle_events(sc_if->msk_softc); 3389 msk_watchdog(sc_if); 3390 callout_reset(&sc_if->msk_tick_ch, hz, msk_tick, sc_if); 3391 } 3392 3393 static void 3394 msk_intr_phy(struct msk_if_softc *sc_if) 3395 { 3396 uint16_t status; 3397 3398 msk_phy_readreg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_STAT); 3399 status = msk_phy_readreg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_STAT); 3400 /* Handle FIFO Underrun/Overflow? */ 3401 if ((status & PHY_M_IS_FIFO_ERROR)) 3402 device_printf(sc_if->msk_if_dev, 3403 "PHY FIFO underrun/overflow.\n"); 3404 } 3405 3406 static void 3407 msk_intr_gmac(struct msk_if_softc *sc_if) 3408 { 3409 struct msk_softc *sc; 3410 uint8_t status; 3411 3412 sc = sc_if->msk_softc; 3413 status = CSR_READ_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_SRC)); 3414 3415 /* GMAC Rx FIFO overrun. */ 3416 if ((status & GM_IS_RX_FF_OR) != 0) 3417 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), 3418 GMF_CLI_RX_FO); 3419 /* GMAC Tx FIFO underrun. */ 3420 if ((status & GM_IS_TX_FF_UR) != 0) { 3421 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 3422 GMF_CLI_TX_FU); 3423 device_printf(sc_if->msk_if_dev, "Tx FIFO underrun!\n"); 3424 /* 3425 * XXX 3426 * In case of Tx underrun, we may need to flush/reset 3427 * Tx MAC but that would also require resynchronization 3428 * with status LEs. Reinitializing status LEs would 3429 * affect other port in dual MAC configuration so it 3430 * should be avoided as possible as we can. 3431 * Due to lack of documentation it's all vague guess but 3432 * it needs more investigation. 3433 */ 3434 } 3435 } 3436 3437 static void 3438 msk_handle_hwerr(struct msk_if_softc *sc_if, uint32_t status) 3439 { 3440 struct msk_softc *sc; 3441 3442 sc = sc_if->msk_softc; 3443 if ((status & Y2_IS_PAR_RD1) != 0) { 3444 device_printf(sc_if->msk_if_dev, 3445 "RAM buffer read parity error\n"); 3446 /* Clear IRQ. */ 3447 CSR_WRITE_2(sc, SELECT_RAM_BUFFER(sc_if->msk_port, B3_RI_CTRL), 3448 RI_CLR_RD_PERR); 3449 } 3450 if ((status & Y2_IS_PAR_WR1) != 0) { 3451 device_printf(sc_if->msk_if_dev, 3452 "RAM buffer write parity error\n"); 3453 /* Clear IRQ. */ 3454 CSR_WRITE_2(sc, SELECT_RAM_BUFFER(sc_if->msk_port, B3_RI_CTRL), 3455 RI_CLR_WR_PERR); 3456 } 3457 if ((status & Y2_IS_PAR_MAC1) != 0) { 3458 device_printf(sc_if->msk_if_dev, "Tx MAC parity error\n"); 3459 /* Clear IRQ. */ 3460 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 3461 GMF_CLI_TX_PE); 3462 } 3463 if ((status & Y2_IS_PAR_RX1) != 0) { 3464 device_printf(sc_if->msk_if_dev, "Rx parity error\n"); 3465 /* Clear IRQ. */ 3466 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_CLR_IRQ_PAR); 3467 } 3468 if ((status & (Y2_IS_TCP_TXS1 | Y2_IS_TCP_TXA1)) != 0) { 3469 device_printf(sc_if->msk_if_dev, "TCP segmentation error\n"); 3470 /* Clear IRQ. */ 3471 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_CLR_IRQ_TCP); 3472 } 3473 } 3474 3475 static void 3476 msk_intr_hwerr(struct msk_softc *sc) 3477 { 3478 uint32_t status; 3479 uint32_t tlphead[4]; 3480 3481 status = CSR_READ_4(sc, B0_HWE_ISRC); 3482 /* Time Stamp timer overflow. */ 3483 if ((status & Y2_IS_TIST_OV) != 0) 3484 CSR_WRITE_1(sc, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ); 3485 if ((status & Y2_IS_PCI_NEXP) != 0) { 3486 /* 3487 * PCI Express Error occured which is not described in PEX 3488 * spec. 3489 * This error is also mapped either to Master Abort( 3490 * Y2_IS_MST_ERR) or Target Abort (Y2_IS_IRQ_STAT) bit and 3491 * can only be cleared there. 3492 */ 3493 device_printf(sc->msk_dev, 3494 "PCI Express protocol violation error\n"); 3495 } 3496 3497 if ((status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) != 0) { 3498 uint16_t v16; 3499 3500 if ((status & Y2_IS_MST_ERR) != 0) 3501 device_printf(sc->msk_dev, 3502 "unexpected IRQ Status error\n"); 3503 else 3504 device_printf(sc->msk_dev, 3505 "unexpected IRQ Master error\n"); 3506 /* Reset all bits in the PCI status register. */ 3507 v16 = pci_read_config(sc->msk_dev, PCIR_STATUS, 2); 3508 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON); 3509 pci_write_config(sc->msk_dev, PCIR_STATUS, v16 | 3510 PCIM_STATUS_PERR | PCIM_STATUS_SERR | PCIM_STATUS_RMABORT | 3511 PCIM_STATUS_RTABORT | PCIM_STATUS_MDPERR, 2); 3512 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 3513 } 3514 3515 /* Check for PCI Express Uncorrectable Error. */ 3516 if ((status & Y2_IS_PCI_EXP) != 0) { 3517 uint32_t v32; 3518 3519 /* 3520 * On PCI Express bus bridges are called root complexes (RC). 3521 * PCI Express errors are recognized by the root complex too, 3522 * which requests the system to handle the problem. After 3523 * error occurence it may be that no access to the adapter 3524 * may be performed any longer. 3525 */ 3526 3527 v32 = CSR_PCI_READ_4(sc, PEX_UNC_ERR_STAT); 3528 if ((v32 & PEX_UNSUP_REQ) != 0) { 3529 /* Ignore unsupported request error. */ 3530 device_printf(sc->msk_dev, 3531 "Uncorrectable PCI Express error\n"); 3532 } 3533 if ((v32 & (PEX_FATAL_ERRORS | PEX_POIS_TLP)) != 0) { 3534 int i; 3535 3536 /* Get TLP header form Log Registers. */ 3537 for (i = 0; i < 4; i++) 3538 tlphead[i] = CSR_PCI_READ_4(sc, 3539 PEX_HEADER_LOG + i * 4); 3540 /* Check for vendor defined broadcast message. */ 3541 if (!(tlphead[0] == 0x73004001 && tlphead[1] == 0x7f)) { 3542 sc->msk_intrhwemask &= ~Y2_IS_PCI_EXP; 3543 CSR_WRITE_4(sc, B0_HWE_IMSK, 3544 sc->msk_intrhwemask); 3545 CSR_READ_4(sc, B0_HWE_IMSK); 3546 } 3547 } 3548 /* Clear the interrupt. */ 3549 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON); 3550 CSR_PCI_WRITE_4(sc, PEX_UNC_ERR_STAT, 0xffffffff); 3551 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 3552 } 3553 3554 if ((status & Y2_HWE_L1_MASK) != 0 && sc->msk_if[MSK_PORT_A] != NULL) 3555 msk_handle_hwerr(sc->msk_if[MSK_PORT_A], status); 3556 if ((status & Y2_HWE_L2_MASK) != 0 && sc->msk_if[MSK_PORT_B] != NULL) 3557 msk_handle_hwerr(sc->msk_if[MSK_PORT_B], status >> 8); 3558 } 3559 3560 static __inline void 3561 msk_rxput(struct msk_if_softc *sc_if) 3562 { 3563 struct msk_softc *sc; 3564 3565 sc = sc_if->msk_softc; 3566 if (sc_if->msk_framesize > (MCLBYTES - MSK_RX_BUF_ALIGN)) 3567 bus_dmamap_sync( 3568 sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 3569 sc_if->msk_cdata.msk_jumbo_rx_ring_map, 3570 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3571 else 3572 bus_dmamap_sync( 3573 sc_if->msk_cdata.msk_rx_ring_tag, 3574 sc_if->msk_cdata.msk_rx_ring_map, 3575 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3576 CSR_WRITE_2(sc, Y2_PREF_Q_ADDR(sc_if->msk_rxq, 3577 PREF_UNIT_PUT_IDX_REG), sc_if->msk_cdata.msk_rx_prod); 3578 } 3579 3580 static int 3581 msk_handle_events(struct msk_softc *sc) 3582 { 3583 struct msk_if_softc *sc_if; 3584 int rxput[2]; 3585 struct msk_stat_desc *sd; 3586 uint32_t control, status; 3587 int cons, len, port, rxprog; 3588 3589 if (sc->msk_stat_cons == CSR_READ_2(sc, STAT_PUT_IDX)) 3590 return (0); 3591 3592 /* Sync status LEs. */ 3593 bus_dmamap_sync(sc->msk_stat_tag, sc->msk_stat_map, 3594 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3595 3596 rxput[MSK_PORT_A] = rxput[MSK_PORT_B] = 0; 3597 rxprog = 0; 3598 cons = sc->msk_stat_cons; 3599 for (;;) { 3600 sd = &sc->msk_stat_ring[cons]; 3601 control = le32toh(sd->msk_control); 3602 if ((control & HW_OWNER) == 0) 3603 break; 3604 control &= ~HW_OWNER; 3605 sd->msk_control = htole32(control); 3606 status = le32toh(sd->msk_status); 3607 len = control & STLE_LEN_MASK; 3608 port = (control >> 16) & 0x01; 3609 sc_if = sc->msk_if[port]; 3610 if (sc_if == NULL) { 3611 device_printf(sc->msk_dev, "invalid port opcode " 3612 "0x%08x\n", control & STLE_OP_MASK); 3613 continue; 3614 } 3615 3616 switch (control & STLE_OP_MASK) { 3617 case OP_RXVLAN: 3618 sc_if->msk_vtag = ntohs(len); 3619 break; 3620 case OP_RXCHKSVLAN: 3621 sc_if->msk_vtag = ntohs(len); 3622 /* FALLTHROUGH */ 3623 case OP_RXCHKS: 3624 sc_if->msk_csum = status; 3625 break; 3626 case OP_RXSTAT: 3627 if (!(sc_if->msk_ifp->if_drv_flags & IFF_DRV_RUNNING)) 3628 break; 3629 if (sc_if->msk_framesize > 3630 (MCLBYTES - MSK_RX_BUF_ALIGN)) 3631 msk_jumbo_rxeof(sc_if, status, control, len); 3632 else 3633 msk_rxeof(sc_if, status, control, len); 3634 rxprog++; 3635 /* 3636 * Because there is no way to sync single Rx LE 3637 * put the DMA sync operation off until the end of 3638 * event processing. 3639 */ 3640 rxput[port]++; 3641 /* Update prefetch unit if we've passed water mark. */ 3642 if (rxput[port] >= sc_if->msk_cdata.msk_rx_putwm) { 3643 msk_rxput(sc_if); 3644 rxput[port] = 0; 3645 } 3646 break; 3647 case OP_TXINDEXLE: 3648 if (sc->msk_if[MSK_PORT_A] != NULL) 3649 msk_txeof(sc->msk_if[MSK_PORT_A], 3650 status & STLE_TXA1_MSKL); 3651 if (sc->msk_if[MSK_PORT_B] != NULL) 3652 msk_txeof(sc->msk_if[MSK_PORT_B], 3653 ((status & STLE_TXA2_MSKL) >> 3654 STLE_TXA2_SHIFTL) | 3655 ((len & STLE_TXA2_MSKH) << 3656 STLE_TXA2_SHIFTH)); 3657 break; 3658 default: 3659 device_printf(sc->msk_dev, "unhandled opcode 0x%08x\n", 3660 control & STLE_OP_MASK); 3661 break; 3662 } 3663 MSK_INC(cons, sc->msk_stat_count); 3664 if (rxprog > sc->msk_process_limit) 3665 break; 3666 } 3667 3668 sc->msk_stat_cons = cons; 3669 bus_dmamap_sync(sc->msk_stat_tag, sc->msk_stat_map, 3670 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3671 3672 if (rxput[MSK_PORT_A] > 0) 3673 msk_rxput(sc->msk_if[MSK_PORT_A]); 3674 if (rxput[MSK_PORT_B] > 0) 3675 msk_rxput(sc->msk_if[MSK_PORT_B]); 3676 3677 return (sc->msk_stat_cons != CSR_READ_2(sc, STAT_PUT_IDX)); 3678 } 3679 3680 static void 3681 msk_intr(void *xsc) 3682 { 3683 struct msk_softc *sc; 3684 struct msk_if_softc *sc_if0, *sc_if1; 3685 struct ifnet *ifp0, *ifp1; 3686 uint32_t status; 3687 int domore; 3688 3689 sc = xsc; 3690 MSK_LOCK(sc); 3691 3692 /* Reading B0_Y2_SP_ISRC2 masks further interrupts. */ 3693 status = CSR_READ_4(sc, B0_Y2_SP_ISRC2); 3694 if (status == 0 || status == 0xffffffff || 3695 (sc->msk_pflags & MSK_FLAG_SUSPEND) != 0 || 3696 (status & sc->msk_intrmask) == 0) { 3697 CSR_WRITE_4(sc, B0_Y2_SP_ICR, 2); 3698 MSK_UNLOCK(sc); 3699 return; 3700 } 3701 3702 sc_if0 = sc->msk_if[MSK_PORT_A]; 3703 sc_if1 = sc->msk_if[MSK_PORT_B]; 3704 ifp0 = ifp1 = NULL; 3705 if (sc_if0 != NULL) 3706 ifp0 = sc_if0->msk_ifp; 3707 if (sc_if1 != NULL) 3708 ifp1 = sc_if1->msk_ifp; 3709 3710 if ((status & Y2_IS_IRQ_PHY1) != 0 && sc_if0 != NULL) 3711 msk_intr_phy(sc_if0); 3712 if ((status & Y2_IS_IRQ_PHY2) != 0 && sc_if1 != NULL) 3713 msk_intr_phy(sc_if1); 3714 if ((status & Y2_IS_IRQ_MAC1) != 0 && sc_if0 != NULL) 3715 msk_intr_gmac(sc_if0); 3716 if ((status & Y2_IS_IRQ_MAC2) != 0 && sc_if1 != NULL) 3717 msk_intr_gmac(sc_if1); 3718 if ((status & (Y2_IS_CHK_RX1 | Y2_IS_CHK_RX2)) != 0) { 3719 device_printf(sc->msk_dev, "Rx descriptor error\n"); 3720 sc->msk_intrmask &= ~(Y2_IS_CHK_RX1 | Y2_IS_CHK_RX2); 3721 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask); 3722 CSR_READ_4(sc, B0_IMSK); 3723 } 3724 if ((status & (Y2_IS_CHK_TXA1 | Y2_IS_CHK_TXA2)) != 0) { 3725 device_printf(sc->msk_dev, "Tx descriptor error\n"); 3726 sc->msk_intrmask &= ~(Y2_IS_CHK_TXA1 | Y2_IS_CHK_TXA2); 3727 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask); 3728 CSR_READ_4(sc, B0_IMSK); 3729 } 3730 if ((status & Y2_IS_HW_ERR) != 0) 3731 msk_intr_hwerr(sc); 3732 3733 domore = msk_handle_events(sc); 3734 if ((status & Y2_IS_STAT_BMU) != 0 && domore == 0) 3735 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_CLR_IRQ); 3736 3737 /* Clear TWSI IRQ. */ 3738 if ((status & Y2_IS_TWSI_RDY) != 0) 3739 CSR_WRITE_4(sc, B2_I2C_IRQ, 1); 3740 /* Reenable interrupts. */ 3741 CSR_WRITE_4(sc, B0_Y2_SP_ICR, 2); 3742 3743 if (ifp0 != NULL && (ifp0->if_drv_flags & IFF_DRV_RUNNING) != 0 && 3744 !IFQ_DRV_IS_EMPTY(&ifp0->if_snd)) 3745 msk_start_locked(ifp0); 3746 if (ifp1 != NULL && (ifp1->if_drv_flags & IFF_DRV_RUNNING) != 0 && 3747 !IFQ_DRV_IS_EMPTY(&ifp1->if_snd)) 3748 msk_start_locked(ifp1); 3749 3750 MSK_UNLOCK(sc); 3751 } 3752 3753 static void 3754 msk_set_tx_stfwd(struct msk_if_softc *sc_if) 3755 { 3756 struct msk_softc *sc; 3757 struct ifnet *ifp; 3758 3759 ifp = sc_if->msk_ifp; 3760 sc = sc_if->msk_softc; 3761 if ((sc->msk_hw_id == CHIP_ID_YUKON_EX && 3762 sc->msk_hw_rev != CHIP_REV_YU_EX_A0) || 3763 sc->msk_hw_id >= CHIP_ID_YUKON_SUPR) { 3764 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 3765 TX_STFW_ENA); 3766 } else { 3767 if (ifp->if_mtu > ETHERMTU) { 3768 /* Set Tx GMAC FIFO Almost Empty Threshold. */ 3769 CSR_WRITE_4(sc, 3770 MR_ADDR(sc_if->msk_port, TX_GMF_AE_THR), 3771 MSK_ECU_JUMBO_WM << 16 | MSK_ECU_AE_THR); 3772 /* Disable Store & Forward mode for Tx. */ 3773 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 3774 TX_STFW_DIS); 3775 } else { 3776 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 3777 TX_STFW_ENA); 3778 } 3779 } 3780 } 3781 3782 static void 3783 msk_init(void *xsc) 3784 { 3785 struct msk_if_softc *sc_if = xsc; 3786 3787 MSK_IF_LOCK(sc_if); 3788 msk_init_locked(sc_if); 3789 MSK_IF_UNLOCK(sc_if); 3790 } 3791 3792 static void 3793 msk_init_locked(struct msk_if_softc *sc_if) 3794 { 3795 struct msk_softc *sc; 3796 struct ifnet *ifp; 3797 struct mii_data *mii; 3798 uint8_t *eaddr; 3799 uint16_t gmac; 3800 uint32_t reg; 3801 int error; 3802 3803 MSK_IF_LOCK_ASSERT(sc_if); 3804 3805 ifp = sc_if->msk_ifp; 3806 sc = sc_if->msk_softc; 3807 mii = device_get_softc(sc_if->msk_miibus); 3808 3809 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 3810 return; 3811 3812 error = 0; 3813 /* Cancel pending I/O and free all Rx/Tx buffers. */ 3814 msk_stop(sc_if); 3815 3816 if (ifp->if_mtu < ETHERMTU) 3817 sc_if->msk_framesize = ETHERMTU; 3818 else 3819 sc_if->msk_framesize = ifp->if_mtu; 3820 sc_if->msk_framesize += ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 3821 if (ifp->if_mtu > ETHERMTU && 3822 (sc_if->msk_flags & MSK_FLAG_JUMBO_NOCSUM) != 0) { 3823 ifp->if_hwassist &= ~(MSK_CSUM_FEATURES | CSUM_TSO); 3824 ifp->if_capenable &= ~(IFCAP_TSO4 | IFCAP_TXCSUM); 3825 } 3826 3827 /* GMAC Control reset. */ 3828 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_RST_SET); 3829 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_RST_CLR); 3830 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_F_LOOPB_OFF); 3831 if (sc->msk_hw_id == CHIP_ID_YUKON_EX || 3832 sc->msk_hw_id == CHIP_ID_YUKON_SUPR) 3833 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), 3834 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON | 3835 GMC_BYP_RETR_ON); 3836 3837 /* 3838 * Initialize GMAC first such that speed/duplex/flow-control 3839 * parameters are renegotiated when interface is brought up. 3840 */ 3841 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, 0); 3842 3843 /* Dummy read the Interrupt Source Register. */ 3844 CSR_READ_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_SRC)); 3845 3846 /* Clear MIB stats. */ 3847 msk_stats_clear(sc_if); 3848 3849 /* Disable FCS. */ 3850 GMAC_WRITE_2(sc, sc_if->msk_port, GM_RX_CTRL, GM_RXCR_CRC_DIS); 3851 3852 /* Setup Transmit Control Register. */ 3853 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF)); 3854 3855 /* Setup Transmit Flow Control Register. */ 3856 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_FLOW_CTRL, 0xffff); 3857 3858 /* Setup Transmit Parameter Register. */ 3859 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_PARAM, 3860 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) | TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) | 3861 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) | TX_BACK_OFF_LIM(TX_BOF_LIM_DEF)); 3862 3863 gmac = DATA_BLIND_VAL(DATA_BLIND_DEF) | 3864 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF); 3865 3866 if (ifp->if_mtu > ETHERMTU) 3867 gmac |= GM_SMOD_JUMBO_ENA; 3868 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SERIAL_MODE, gmac); 3869 3870 /* Set station address. */ 3871 eaddr = IF_LLADDR(ifp); 3872 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_1L, 3873 eaddr[0] | (eaddr[1] << 8)); 3874 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_1M, 3875 eaddr[2] | (eaddr[3] << 8)); 3876 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_1H, 3877 eaddr[4] | (eaddr[5] << 8)); 3878 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_2L, 3879 eaddr[0] | (eaddr[1] << 8)); 3880 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_2M, 3881 eaddr[2] | (eaddr[3] << 8)); 3882 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_2H, 3883 eaddr[4] | (eaddr[5] << 8)); 3884 3885 /* Disable interrupts for counter overflows. */ 3886 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_IRQ_MSK, 0); 3887 GMAC_WRITE_2(sc, sc_if->msk_port, GM_RX_IRQ_MSK, 0); 3888 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TR_IRQ_MSK, 0); 3889 3890 /* Configure Rx MAC FIFO. */ 3891 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), GMF_RST_SET); 3892 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), GMF_RST_CLR); 3893 reg = GMF_OPER_ON | GMF_RX_F_FL_ON; 3894 if (sc->msk_hw_id == CHIP_ID_YUKON_FE_P || 3895 sc->msk_hw_id == CHIP_ID_YUKON_EX) 3896 reg |= GMF_RX_OVER_ON; 3897 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), reg); 3898 3899 /* Set receive filter. */ 3900 msk_rxfilter(sc_if); 3901 3902 if (sc->msk_hw_id == CHIP_ID_YUKON_XL) { 3903 /* Clear flush mask - HW bug. */ 3904 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_FL_MSK), 0); 3905 } else { 3906 /* Flush Rx MAC FIFO on any flow control or error. */ 3907 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_FL_MSK), 3908 GMR_FS_ANY_ERR); 3909 } 3910 3911 /* 3912 * Set Rx FIFO flush threshold to 64 bytes + 1 FIFO word 3913 * due to hardware hang on receipt of pause frames. 3914 */ 3915 reg = RX_GMF_FL_THR_DEF + 1; 3916 /* Another magic for Yukon FE+ - From Linux. */ 3917 if (sc->msk_hw_id == CHIP_ID_YUKON_FE_P && 3918 sc->msk_hw_rev == CHIP_REV_YU_FE_P_A0) 3919 reg = 0x178; 3920 CSR_WRITE_2(sc, MR_ADDR(sc_if->msk_port, RX_GMF_FL_THR), reg); 3921 3922 /* Configure Tx MAC FIFO. */ 3923 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_RST_SET); 3924 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_RST_CLR); 3925 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_OPER_ON); 3926 3927 /* Configure hardware VLAN tag insertion/stripping. */ 3928 msk_setvlan(sc_if, ifp); 3929 3930 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) == 0) { 3931 /* Set Rx Pause threshold. */ 3932 CSR_WRITE_2(sc, MR_ADDR(sc_if->msk_port, RX_GMF_LP_THR), 3933 MSK_ECU_LLPP); 3934 CSR_WRITE_2(sc, MR_ADDR(sc_if->msk_port, RX_GMF_UP_THR), 3935 MSK_ECU_ULPP); 3936 /* Configure store-and-forward for Tx. */ 3937 msk_set_tx_stfwd(sc_if); 3938 } 3939 3940 if (sc->msk_hw_id == CHIP_ID_YUKON_FE_P && 3941 sc->msk_hw_rev == CHIP_REV_YU_FE_P_A0) { 3942 /* Disable dynamic watermark - from Linux. */ 3943 reg = CSR_READ_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_EA)); 3944 reg &= ~0x03; 3945 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_EA), reg); 3946 } 3947 3948 /* 3949 * Disable Force Sync bit and Alloc bit in Tx RAM interface 3950 * arbiter as we don't use Sync Tx queue. 3951 */ 3952 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, TXA_CTRL), 3953 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC); 3954 /* Enable the RAM Interface Arbiter. */ 3955 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, TXA_CTRL), TXA_ENA_ARB); 3956 3957 /* Setup RAM buffer. */ 3958 msk_set_rambuffer(sc_if); 3959 3960 /* Disable Tx sync Queue. */ 3961 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txsq, RB_CTRL), RB_RST_SET); 3962 3963 /* Setup Tx Queue Bus Memory Interface. */ 3964 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_CLR_RESET); 3965 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_OPER_INIT); 3966 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_FIFO_OP_ON); 3967 CSR_WRITE_2(sc, Q_ADDR(sc_if->msk_txq, Q_WM), MSK_BMU_TX_WM); 3968 switch (sc->msk_hw_id) { 3969 case CHIP_ID_YUKON_EC_U: 3970 if (sc->msk_hw_rev == CHIP_REV_YU_EC_U_A0) { 3971 /* Fix for Yukon-EC Ultra: set BMU FIFO level */ 3972 CSR_WRITE_2(sc, Q_ADDR(sc_if->msk_txq, Q_AL), 3973 MSK_ECU_TXFF_LEV); 3974 } 3975 break; 3976 case CHIP_ID_YUKON_EX: 3977 /* 3978 * Yukon Extreme seems to have silicon bug for 3979 * automatic Tx checksum calculation capability. 3980 */ 3981 if (sc->msk_hw_rev == CHIP_REV_YU_EX_B0) 3982 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_F), 3983 F_TX_CHK_AUTO_OFF); 3984 break; 3985 } 3986 3987 /* Setup Rx Queue Bus Memory Interface. */ 3988 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_CLR_RESET); 3989 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_OPER_INIT); 3990 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_FIFO_OP_ON); 3991 CSR_WRITE_2(sc, Q_ADDR(sc_if->msk_rxq, Q_WM), MSK_BMU_RX_WM); 3992 if (sc->msk_hw_id == CHIP_ID_YUKON_EC_U && 3993 sc->msk_hw_rev >= CHIP_REV_YU_EC_U_A1) { 3994 /* MAC Rx RAM Read is controlled by hardware. */ 3995 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_F), F_M_RX_RAM_DIS); 3996 } 3997 3998 msk_set_prefetch(sc, sc_if->msk_txq, 3999 sc_if->msk_rdata.msk_tx_ring_paddr, MSK_TX_RING_CNT - 1); 4000 msk_init_tx_ring(sc_if); 4001 4002 /* Disable Rx checksum offload and RSS hash. */ 4003 reg = BMU_DIS_RX_RSS_HASH; 4004 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0 && 4005 (ifp->if_capenable & IFCAP_RXCSUM) != 0) 4006 reg |= BMU_ENA_RX_CHKSUM; 4007 else 4008 reg |= BMU_DIS_RX_CHKSUM; 4009 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), reg); 4010 if (sc_if->msk_framesize > (MCLBYTES - MSK_RX_BUF_ALIGN)) { 4011 msk_set_prefetch(sc, sc_if->msk_rxq, 4012 sc_if->msk_rdata.msk_jumbo_rx_ring_paddr, 4013 MSK_JUMBO_RX_RING_CNT - 1); 4014 error = msk_init_jumbo_rx_ring(sc_if); 4015 } else { 4016 msk_set_prefetch(sc, sc_if->msk_rxq, 4017 sc_if->msk_rdata.msk_rx_ring_paddr, 4018 MSK_RX_RING_CNT - 1); 4019 error = msk_init_rx_ring(sc_if); 4020 } 4021 if (error != 0) { 4022 device_printf(sc_if->msk_if_dev, 4023 "initialization failed: no memory for Rx buffers\n"); 4024 msk_stop(sc_if); 4025 return; 4026 } 4027 if (sc->msk_hw_id == CHIP_ID_YUKON_EX || 4028 sc->msk_hw_id == CHIP_ID_YUKON_SUPR) { 4029 /* Disable flushing of non-ASF packets. */ 4030 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), 4031 GMF_RX_MACSEC_FLUSH_OFF); 4032 } 4033 4034 /* Configure interrupt handling. */ 4035 if (sc_if->msk_port == MSK_PORT_A) { 4036 sc->msk_intrmask |= Y2_IS_PORT_A; 4037 sc->msk_intrhwemask |= Y2_HWE_L1_MASK; 4038 } else { 4039 sc->msk_intrmask |= Y2_IS_PORT_B; 4040 sc->msk_intrhwemask |= Y2_HWE_L2_MASK; 4041 } 4042 /* Configure IRQ moderation mask. */ 4043 CSR_WRITE_4(sc, B2_IRQM_MSK, sc->msk_intrmask); 4044 if (sc->msk_int_holdoff > 0) { 4045 /* Configure initial IRQ moderation timer value. */ 4046 CSR_WRITE_4(sc, B2_IRQM_INI, 4047 MSK_USECS(sc, sc->msk_int_holdoff)); 4048 CSR_WRITE_4(sc, B2_IRQM_VAL, 4049 MSK_USECS(sc, sc->msk_int_holdoff)); 4050 /* Start IRQ moderation. */ 4051 CSR_WRITE_1(sc, B2_IRQM_CTRL, TIM_START); 4052 } 4053 CSR_WRITE_4(sc, B0_HWE_IMSK, sc->msk_intrhwemask); 4054 CSR_READ_4(sc, B0_HWE_IMSK); 4055 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask); 4056 CSR_READ_4(sc, B0_IMSK); 4057 4058 sc_if->msk_flags &= ~MSK_FLAG_LINK; 4059 mii_mediachg(mii); 4060 4061 ifp->if_drv_flags |= IFF_DRV_RUNNING; 4062 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 4063 4064 callout_reset(&sc_if->msk_tick_ch, hz, msk_tick, sc_if); 4065 } 4066 4067 static void 4068 msk_set_rambuffer(struct msk_if_softc *sc_if) 4069 { 4070 struct msk_softc *sc; 4071 int ltpp, utpp; 4072 4073 sc = sc_if->msk_softc; 4074 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) == 0) 4075 return; 4076 4077 /* Setup Rx Queue. */ 4078 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_RST_CLR); 4079 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_START), 4080 sc->msk_rxqstart[sc_if->msk_port] / 8); 4081 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_END), 4082 sc->msk_rxqend[sc_if->msk_port] / 8); 4083 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_WP), 4084 sc->msk_rxqstart[sc_if->msk_port] / 8); 4085 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_RP), 4086 sc->msk_rxqstart[sc_if->msk_port] / 8); 4087 4088 utpp = (sc->msk_rxqend[sc_if->msk_port] + 1 - 4089 sc->msk_rxqstart[sc_if->msk_port] - MSK_RB_ULPP) / 8; 4090 ltpp = (sc->msk_rxqend[sc_if->msk_port] + 1 - 4091 sc->msk_rxqstart[sc_if->msk_port] - MSK_RB_LLPP_B) / 8; 4092 if (sc->msk_rxqsize < MSK_MIN_RXQ_SIZE) 4093 ltpp += (MSK_RB_LLPP_B - MSK_RB_LLPP_S) / 8; 4094 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_RX_UTPP), utpp); 4095 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_RX_LTPP), ltpp); 4096 /* Set Rx priority(RB_RX_UTHP/RB_RX_LTHP) thresholds? */ 4097 4098 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_ENA_OP_MD); 4099 CSR_READ_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL)); 4100 4101 /* Setup Tx Queue. */ 4102 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_RST_CLR); 4103 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_START), 4104 sc->msk_txqstart[sc_if->msk_port] / 8); 4105 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_END), 4106 sc->msk_txqend[sc_if->msk_port] / 8); 4107 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_WP), 4108 sc->msk_txqstart[sc_if->msk_port] / 8); 4109 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_RP), 4110 sc->msk_txqstart[sc_if->msk_port] / 8); 4111 /* Enable Store & Forward for Tx side. */ 4112 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_ENA_STFWD); 4113 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_ENA_OP_MD); 4114 CSR_READ_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL)); 4115 } 4116 4117 static void 4118 msk_set_prefetch(struct msk_softc *sc, int qaddr, bus_addr_t addr, 4119 uint32_t count) 4120 { 4121 4122 /* Reset the prefetch unit. */ 4123 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG), 4124 PREF_UNIT_RST_SET); 4125 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG), 4126 PREF_UNIT_RST_CLR); 4127 /* Set LE base address. */ 4128 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_ADDR_LOW_REG), 4129 MSK_ADDR_LO(addr)); 4130 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_ADDR_HI_REG), 4131 MSK_ADDR_HI(addr)); 4132 /* Set the list last index. */ 4133 CSR_WRITE_2(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_LAST_IDX_REG), 4134 count); 4135 /* Turn on prefetch unit. */ 4136 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG), 4137 PREF_UNIT_OP_ON); 4138 /* Dummy read to ensure write. */ 4139 CSR_READ_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG)); 4140 } 4141 4142 static void 4143 msk_stop(struct msk_if_softc *sc_if) 4144 { 4145 struct msk_softc *sc; 4146 struct msk_txdesc *txd; 4147 struct msk_rxdesc *rxd; 4148 struct msk_rxdesc *jrxd; 4149 struct ifnet *ifp; 4150 uint32_t val; 4151 int i; 4152 4153 MSK_IF_LOCK_ASSERT(sc_if); 4154 sc = sc_if->msk_softc; 4155 ifp = sc_if->msk_ifp; 4156 4157 callout_stop(&sc_if->msk_tick_ch); 4158 sc_if->msk_watchdog_timer = 0; 4159 4160 /* Disable interrupts. */ 4161 if (sc_if->msk_port == MSK_PORT_A) { 4162 sc->msk_intrmask &= ~Y2_IS_PORT_A; 4163 sc->msk_intrhwemask &= ~Y2_HWE_L1_MASK; 4164 } else { 4165 sc->msk_intrmask &= ~Y2_IS_PORT_B; 4166 sc->msk_intrhwemask &= ~Y2_HWE_L2_MASK; 4167 } 4168 CSR_WRITE_4(sc, B0_HWE_IMSK, sc->msk_intrhwemask); 4169 CSR_READ_4(sc, B0_HWE_IMSK); 4170 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask); 4171 CSR_READ_4(sc, B0_IMSK); 4172 4173 /* Disable Tx/Rx MAC. */ 4174 val = GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL); 4175 val &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA); 4176 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, val); 4177 /* Read again to ensure writing. */ 4178 GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL); 4179 /* Update stats and clear counters. */ 4180 msk_stats_update(sc_if); 4181 4182 /* Stop Tx BMU. */ 4183 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_STOP); 4184 val = CSR_READ_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR)); 4185 for (i = 0; i < MSK_TIMEOUT; i++) { 4186 if ((val & (BMU_STOP | BMU_IDLE)) == 0) { 4187 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), 4188 BMU_STOP); 4189 val = CSR_READ_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR)); 4190 } else 4191 break; 4192 DELAY(1); 4193 } 4194 if (i == MSK_TIMEOUT) 4195 device_printf(sc_if->msk_if_dev, "Tx BMU stop failed\n"); 4196 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), 4197 RB_RST_SET | RB_DIS_OP_MD); 4198 4199 /* Disable all GMAC interrupt. */ 4200 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_MSK), 0); 4201 /* Disable PHY interrupt. */ 4202 msk_phy_writereg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_MASK, 0); 4203 4204 /* Disable the RAM Interface Arbiter. */ 4205 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, TXA_CTRL), TXA_DIS_ARB); 4206 4207 /* Reset the PCI FIFO of the async Tx queue */ 4208 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), 4209 BMU_RST_SET | BMU_FIFO_RST); 4210 4211 /* Reset the Tx prefetch units. */ 4212 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(sc_if->msk_txq, PREF_UNIT_CTRL_REG), 4213 PREF_UNIT_RST_SET); 4214 4215 /* Reset the RAM Buffer async Tx queue. */ 4216 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_RST_SET); 4217 4218 /* Reset Tx MAC FIFO. */ 4219 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_RST_SET); 4220 /* Set Pause Off. */ 4221 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_PAUSE_OFF); 4222 4223 /* 4224 * The Rx Stop command will not work for Yukon-2 if the BMU does not 4225 * reach the end of packet and since we can't make sure that we have 4226 * incoming data, we must reset the BMU while it is not during a DMA 4227 * transfer. Since it is possible that the Rx path is still active, 4228 * the Rx RAM buffer will be stopped first, so any possible incoming 4229 * data will not trigger a DMA. After the RAM buffer is stopped, the 4230 * BMU is polled until any DMA in progress is ended and only then it 4231 * will be reset. 4232 */ 4233 4234 /* Disable the RAM Buffer receive queue. */ 4235 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_DIS_OP_MD); 4236 for (i = 0; i < MSK_TIMEOUT; i++) { 4237 if (CSR_READ_1(sc, RB_ADDR(sc_if->msk_rxq, Q_RSL)) == 4238 CSR_READ_1(sc, RB_ADDR(sc_if->msk_rxq, Q_RL))) 4239 break; 4240 DELAY(1); 4241 } 4242 if (i == MSK_TIMEOUT) 4243 device_printf(sc_if->msk_if_dev, "Rx BMU stop failed\n"); 4244 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), 4245 BMU_RST_SET | BMU_FIFO_RST); 4246 /* Reset the Rx prefetch unit. */ 4247 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_CTRL_REG), 4248 PREF_UNIT_RST_SET); 4249 /* Reset the RAM Buffer receive queue. */ 4250 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_RST_SET); 4251 /* Reset Rx MAC FIFO. */ 4252 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), GMF_RST_SET); 4253 4254 /* Free Rx and Tx mbufs still in the queues. */ 4255 for (i = 0; i < MSK_RX_RING_CNT; i++) { 4256 rxd = &sc_if->msk_cdata.msk_rxdesc[i]; 4257 if (rxd->rx_m != NULL) { 4258 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_tag, 4259 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 4260 bus_dmamap_unload(sc_if->msk_cdata.msk_rx_tag, 4261 rxd->rx_dmamap); 4262 m_freem(rxd->rx_m); 4263 rxd->rx_m = NULL; 4264 } 4265 } 4266 for (i = 0; i < MSK_JUMBO_RX_RING_CNT; i++) { 4267 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[i]; 4268 if (jrxd->rx_m != NULL) { 4269 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_tag, 4270 jrxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 4271 bus_dmamap_unload(sc_if->msk_cdata.msk_jumbo_rx_tag, 4272 jrxd->rx_dmamap); 4273 m_freem(jrxd->rx_m); 4274 jrxd->rx_m = NULL; 4275 } 4276 } 4277 for (i = 0; i < MSK_TX_RING_CNT; i++) { 4278 txd = &sc_if->msk_cdata.msk_txdesc[i]; 4279 if (txd->tx_m != NULL) { 4280 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_tag, 4281 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 4282 bus_dmamap_unload(sc_if->msk_cdata.msk_tx_tag, 4283 txd->tx_dmamap); 4284 m_freem(txd->tx_m); 4285 txd->tx_m = NULL; 4286 } 4287 } 4288 4289 /* 4290 * Mark the interface down. 4291 */ 4292 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 4293 sc_if->msk_flags &= ~MSK_FLAG_LINK; 4294 } 4295 4296 /* 4297 * When GM_PAR_MIB_CLR bit of GM_PHY_ADDR is set, reading lower 4298 * counter clears high 16 bits of the counter such that accessing 4299 * lower 16 bits should be the last operation. 4300 */ 4301 #define MSK_READ_MIB32(x, y) \ 4302 (((uint32_t)GMAC_READ_2(sc, x, (y) + 4)) << 16) + \ 4303 (uint32_t)GMAC_READ_2(sc, x, y) 4304 #define MSK_READ_MIB64(x, y) \ 4305 (((uint64_t)MSK_READ_MIB32(x, (y) + 8)) << 32) + \ 4306 (uint64_t)MSK_READ_MIB32(x, y) 4307 4308 static void 4309 msk_stats_clear(struct msk_if_softc *sc_if) 4310 { 4311 struct msk_softc *sc; 4312 uint32_t reg; 4313 uint16_t gmac; 4314 int i; 4315 4316 MSK_IF_LOCK_ASSERT(sc_if); 4317 4318 sc = sc_if->msk_softc; 4319 /* Set MIB Clear Counter Mode. */ 4320 gmac = GMAC_READ_2(sc, sc_if->msk_port, GM_PHY_ADDR); 4321 GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac | GM_PAR_MIB_CLR); 4322 /* Read all MIB Counters with Clear Mode set. */ 4323 for (i = GM_RXF_UC_OK; i <= GM_TXE_FIFO_UR; i += sizeof(uint32_t)) 4324 reg = MSK_READ_MIB32(sc_if->msk_port, i); 4325 /* Clear MIB Clear Counter Mode. */ 4326 gmac &= ~GM_PAR_MIB_CLR; 4327 GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac); 4328 } 4329 4330 static void 4331 msk_stats_update(struct msk_if_softc *sc_if) 4332 { 4333 struct msk_softc *sc; 4334 struct ifnet *ifp; 4335 struct msk_hw_stats *stats; 4336 uint16_t gmac; 4337 uint32_t reg; 4338 4339 MSK_IF_LOCK_ASSERT(sc_if); 4340 4341 ifp = sc_if->msk_ifp; 4342 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 4343 return; 4344 sc = sc_if->msk_softc; 4345 stats = &sc_if->msk_stats; 4346 /* Set MIB Clear Counter Mode. */ 4347 gmac = GMAC_READ_2(sc, sc_if->msk_port, GM_PHY_ADDR); 4348 GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac | GM_PAR_MIB_CLR); 4349 4350 /* Rx stats. */ 4351 stats->rx_ucast_frames += 4352 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_UC_OK); 4353 stats->rx_bcast_frames += 4354 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_BC_OK); 4355 stats->rx_pause_frames += 4356 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_MPAUSE); 4357 stats->rx_mcast_frames += 4358 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_MC_OK); 4359 stats->rx_crc_errs += 4360 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_FCS_ERR); 4361 reg = MSK_READ_MIB32(sc_if->msk_port, GM_RXF_SPARE1); 4362 stats->rx_good_octets += 4363 MSK_READ_MIB64(sc_if->msk_port, GM_RXO_OK_LO); 4364 stats->rx_bad_octets += 4365 MSK_READ_MIB64(sc_if->msk_port, GM_RXO_ERR_LO); 4366 stats->rx_runts += 4367 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_SHT); 4368 stats->rx_runt_errs += 4369 MSK_READ_MIB32(sc_if->msk_port, GM_RXE_FRAG); 4370 stats->rx_pkts_64 += 4371 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_64B); 4372 stats->rx_pkts_65_127 += 4373 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_127B); 4374 stats->rx_pkts_128_255 += 4375 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_255B); 4376 stats->rx_pkts_256_511 += 4377 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_511B); 4378 stats->rx_pkts_512_1023 += 4379 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_1023B); 4380 stats->rx_pkts_1024_1518 += 4381 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_1518B); 4382 stats->rx_pkts_1519_max += 4383 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_MAX_SZ); 4384 stats->rx_pkts_too_long += 4385 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_LNG_ERR); 4386 stats->rx_pkts_jabbers += 4387 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_JAB_PKT); 4388 reg = MSK_READ_MIB32(sc_if->msk_port, GM_RXF_SPARE2); 4389 stats->rx_fifo_oflows += 4390 MSK_READ_MIB32(sc_if->msk_port, GM_RXE_FIFO_OV); 4391 reg = MSK_READ_MIB32(sc_if->msk_port, GM_RXF_SPARE3); 4392 4393 /* Tx stats. */ 4394 stats->tx_ucast_frames += 4395 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_UC_OK); 4396 stats->tx_bcast_frames += 4397 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_BC_OK); 4398 stats->tx_pause_frames += 4399 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_MPAUSE); 4400 stats->tx_mcast_frames += 4401 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_MC_OK); 4402 stats->tx_octets += 4403 MSK_READ_MIB64(sc_if->msk_port, GM_TXO_OK_LO); 4404 stats->tx_pkts_64 += 4405 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_64B); 4406 stats->tx_pkts_65_127 += 4407 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_127B); 4408 stats->tx_pkts_128_255 += 4409 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_255B); 4410 stats->tx_pkts_256_511 += 4411 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_511B); 4412 stats->tx_pkts_512_1023 += 4413 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_1023B); 4414 stats->tx_pkts_1024_1518 += 4415 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_1518B); 4416 stats->tx_pkts_1519_max += 4417 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_MAX_SZ); 4418 reg = MSK_READ_MIB32(sc_if->msk_port, GM_TXF_SPARE1); 4419 stats->tx_colls += 4420 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_COL); 4421 stats->tx_late_colls += 4422 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_LAT_COL); 4423 stats->tx_excess_colls += 4424 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_ABO_COL); 4425 stats->tx_multi_colls += 4426 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_MUL_COL); 4427 stats->tx_single_colls += 4428 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_SNG_COL); 4429 stats->tx_underflows += 4430 MSK_READ_MIB32(sc_if->msk_port, GM_TXE_FIFO_UR); 4431 /* Clear MIB Clear Counter Mode. */ 4432 gmac &= ~GM_PAR_MIB_CLR; 4433 GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac); 4434 } 4435 4436 static int 4437 msk_sysctl_stat32(SYSCTL_HANDLER_ARGS) 4438 { 4439 struct msk_softc *sc; 4440 struct msk_if_softc *sc_if; 4441 uint32_t result, *stat; 4442 int off; 4443 4444 sc_if = (struct msk_if_softc *)arg1; 4445 sc = sc_if->msk_softc; 4446 off = arg2; 4447 stat = (uint32_t *)((uint8_t *)&sc_if->msk_stats + off); 4448 4449 MSK_IF_LOCK(sc_if); 4450 result = MSK_READ_MIB32(sc_if->msk_port, GM_MIB_CNT_BASE + off * 2); 4451 result += *stat; 4452 MSK_IF_UNLOCK(sc_if); 4453 4454 return (sysctl_handle_int(oidp, &result, 0, req)); 4455 } 4456 4457 static int 4458 msk_sysctl_stat64(SYSCTL_HANDLER_ARGS) 4459 { 4460 struct msk_softc *sc; 4461 struct msk_if_softc *sc_if; 4462 uint64_t result, *stat; 4463 int off; 4464 4465 sc_if = (struct msk_if_softc *)arg1; 4466 sc = sc_if->msk_softc; 4467 off = arg2; 4468 stat = (uint64_t *)((uint8_t *)&sc_if->msk_stats + off); 4469 4470 MSK_IF_LOCK(sc_if); 4471 result = MSK_READ_MIB64(sc_if->msk_port, GM_MIB_CNT_BASE + off * 2); 4472 result += *stat; 4473 MSK_IF_UNLOCK(sc_if); 4474 4475 return (sysctl_handle_64(oidp, &result, 0, req)); 4476 } 4477 4478 #undef MSK_READ_MIB32 4479 #undef MSK_READ_MIB64 4480 4481 #define MSK_SYSCTL_STAT32(sc, c, o, p, n, d) \ 4482 SYSCTL_ADD_PROC(c, p, OID_AUTO, o, CTLTYPE_UINT | CTLFLAG_RD, \ 4483 sc, offsetof(struct msk_hw_stats, n), msk_sysctl_stat32, \ 4484 "IU", d) 4485 #define MSK_SYSCTL_STAT64(sc, c, o, p, n, d) \ 4486 SYSCTL_ADD_PROC(c, p, OID_AUTO, o, CTLTYPE_U64 | CTLFLAG_RD, \ 4487 sc, offsetof(struct msk_hw_stats, n), msk_sysctl_stat64, \ 4488 "QU", d) 4489 4490 static void 4491 msk_sysctl_node(struct msk_if_softc *sc_if) 4492 { 4493 struct sysctl_ctx_list *ctx; 4494 struct sysctl_oid_list *child, *schild; 4495 struct sysctl_oid *tree; 4496 4497 ctx = device_get_sysctl_ctx(sc_if->msk_if_dev); 4498 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc_if->msk_if_dev)); 4499 4500 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD, 4501 NULL, "MSK Statistics"); 4502 schild = child = SYSCTL_CHILDREN(tree); 4503 tree = SYSCTL_ADD_NODE(ctx, schild, OID_AUTO, "rx", CTLFLAG_RD, 4504 NULL, "MSK RX Statistics"); 4505 child = SYSCTL_CHILDREN(tree); 4506 MSK_SYSCTL_STAT32(sc_if, ctx, "ucast_frames", 4507 child, rx_ucast_frames, "Good unicast frames"); 4508 MSK_SYSCTL_STAT32(sc_if, ctx, "bcast_frames", 4509 child, rx_bcast_frames, "Good broadcast frames"); 4510 MSK_SYSCTL_STAT32(sc_if, ctx, "pause_frames", 4511 child, rx_pause_frames, "Pause frames"); 4512 MSK_SYSCTL_STAT32(sc_if, ctx, "mcast_frames", 4513 child, rx_mcast_frames, "Multicast frames"); 4514 MSK_SYSCTL_STAT32(sc_if, ctx, "crc_errs", 4515 child, rx_crc_errs, "CRC errors"); 4516 MSK_SYSCTL_STAT64(sc_if, ctx, "good_octets", 4517 child, rx_good_octets, "Good octets"); 4518 MSK_SYSCTL_STAT64(sc_if, ctx, "bad_octets", 4519 child, rx_bad_octets, "Bad octets"); 4520 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_64", 4521 child, rx_pkts_64, "64 bytes frames"); 4522 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_65_127", 4523 child, rx_pkts_65_127, "65 to 127 bytes frames"); 4524 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_128_255", 4525 child, rx_pkts_128_255, "128 to 255 bytes frames"); 4526 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_256_511", 4527 child, rx_pkts_256_511, "256 to 511 bytes frames"); 4528 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_512_1023", 4529 child, rx_pkts_512_1023, "512 to 1023 bytes frames"); 4530 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_1024_1518", 4531 child, rx_pkts_1024_1518, "1024 to 1518 bytes frames"); 4532 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_1519_max", 4533 child, rx_pkts_1519_max, "1519 to max frames"); 4534 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_too_long", 4535 child, rx_pkts_too_long, "frames too long"); 4536 MSK_SYSCTL_STAT32(sc_if, ctx, "jabbers", 4537 child, rx_pkts_jabbers, "Jabber errors"); 4538 MSK_SYSCTL_STAT32(sc_if, ctx, "overflows", 4539 child, rx_fifo_oflows, "FIFO overflows"); 4540 4541 tree = SYSCTL_ADD_NODE(ctx, schild, OID_AUTO, "tx", CTLFLAG_RD, 4542 NULL, "MSK TX Statistics"); 4543 child = SYSCTL_CHILDREN(tree); 4544 MSK_SYSCTL_STAT32(sc_if, ctx, "ucast_frames", 4545 child, tx_ucast_frames, "Unicast frames"); 4546 MSK_SYSCTL_STAT32(sc_if, ctx, "bcast_frames", 4547 child, tx_bcast_frames, "Broadcast frames"); 4548 MSK_SYSCTL_STAT32(sc_if, ctx, "pause_frames", 4549 child, tx_pause_frames, "Pause frames"); 4550 MSK_SYSCTL_STAT32(sc_if, ctx, "mcast_frames", 4551 child, tx_mcast_frames, "Multicast frames"); 4552 MSK_SYSCTL_STAT64(sc_if, ctx, "octets", 4553 child, tx_octets, "Octets"); 4554 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_64", 4555 child, tx_pkts_64, "64 bytes frames"); 4556 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_65_127", 4557 child, tx_pkts_65_127, "65 to 127 bytes frames"); 4558 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_128_255", 4559 child, tx_pkts_128_255, "128 to 255 bytes frames"); 4560 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_256_511", 4561 child, tx_pkts_256_511, "256 to 511 bytes frames"); 4562 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_512_1023", 4563 child, tx_pkts_512_1023, "512 to 1023 bytes frames"); 4564 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_1024_1518", 4565 child, tx_pkts_1024_1518, "1024 to 1518 bytes frames"); 4566 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_1519_max", 4567 child, tx_pkts_1519_max, "1519 to max frames"); 4568 MSK_SYSCTL_STAT32(sc_if, ctx, "colls", 4569 child, tx_colls, "Collisions"); 4570 MSK_SYSCTL_STAT32(sc_if, ctx, "late_colls", 4571 child, tx_late_colls, "Late collisions"); 4572 MSK_SYSCTL_STAT32(sc_if, ctx, "excess_colls", 4573 child, tx_excess_colls, "Excessive collisions"); 4574 MSK_SYSCTL_STAT32(sc_if, ctx, "multi_colls", 4575 child, tx_multi_colls, "Multiple collisions"); 4576 MSK_SYSCTL_STAT32(sc_if, ctx, "single_colls", 4577 child, tx_single_colls, "Single collisions"); 4578 MSK_SYSCTL_STAT32(sc_if, ctx, "underflows", 4579 child, tx_underflows, "FIFO underflows"); 4580 } 4581 4582 #undef MSK_SYSCTL_STAT32 4583 #undef MSK_SYSCTL_STAT64 4584 4585 static int 4586 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 4587 { 4588 int error, value; 4589 4590 if (!arg1) 4591 return (EINVAL); 4592 value = *(int *)arg1; 4593 error = sysctl_handle_int(oidp, &value, 0, req); 4594 if (error || !req->newptr) 4595 return (error); 4596 if (value < low || value > high) 4597 return (EINVAL); 4598 *(int *)arg1 = value; 4599 4600 return (0); 4601 } 4602 4603 static int 4604 sysctl_hw_msk_proc_limit(SYSCTL_HANDLER_ARGS) 4605 { 4606 4607 return (sysctl_int_range(oidp, arg1, arg2, req, MSK_PROC_MIN, 4608 MSK_PROC_MAX)); 4609 } 4610